From 247ad37c4bd0c27e3cf358df30fa29517f033260 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Fri, 21 Dec 2012 21:30:33 +0000
Subject: configs/sim/nxwm now uses kconfig-frontends

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5449 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/arch/sim/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'nuttx/arch')

diff --git a/nuttx/arch/sim/Kconfig b/nuttx/arch/sim/Kconfig
index 331f61c79..dc3a85b54 100644
--- a/nuttx/arch/sim/Kconfig
+++ b/nuttx/arch/sim/Kconfig
@@ -50,7 +50,7 @@ config SIM_FRAMEBUFFER
 config SIM_X11FB
 	bool "Use X11 window"
 	default n
-	depends on NX && FB_CMAP
+	depends on NX
 	---help---
 		Use an X11 graphics window to simulate the graphics device"
 
-- 
cgit v1.2.3


From c62d3d93deef9ec14e80c3a96d70f846deeff66e Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Sun, 23 Dec 2012 17:32:41 +0000
Subject: Mostly costmetic updates

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5452 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/Documentation/NuttX.html          | 15 +++++-------
 nuttx/README.txt                        | 24 +++++++++++--------
 nuttx/arch/arm/src/arm/up_doirq.c       |  8 ++++---
 nuttx/arch/arm/src/armv7-m/up_doirq.c   |  8 ++++---
 nuttx/arch/avr/src/avr/up_doirq.c       |  8 ++++---
 nuttx/arch/avr/src/avr32/up_doirq.c     |  8 ++++---
 nuttx/arch/hc/src/common/up_doirq.c     |  8 ++++---
 nuttx/arch/mips/src/mips32/up_doirq.c   |  8 ++++---
 nuttx/arch/sh/src/common/up_doirq.c     |  9 ++++++++
 nuttx/arch/z16/src/common/up_doirq.c    |  9 ++++++++
 nuttx/arch/z80/include/z80/chip.h       |  6 ++---
 nuttx/arch/z80/src/common/up_internal.h | 41 +++++++++++++++------------------
 nuttx/arch/z80/src/ez80/switch.h        | 26 ++++++++++++---------
 nuttx/arch/z80/src/z180/switch.h        | 25 ++++++++++----------
 nuttx/arch/z80/src/z8/switch.h          | 28 ++++++++++++----------
 nuttx/arch/z80/src/z80/switch.h         | 26 ++++++++++++---------
 16 files changed, 149 insertions(+), 108 deletions(-)

(limited to 'nuttx/arch')

diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html
index f48994bab..84f298d3a 100644
--- a/nuttx/Documentation/NuttX.html
+++ b/nuttx/Documentation/NuttX.html
@@ -1078,7 +1078,6 @@ svn checkout -r5447 svn://svn.code.sf.net/p/nuttx/code/trunk nuttx-code
 svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code
 </pre></ul>
 
-
 <p>
   <b>Additional new features and extended functionality</b>
 </p>
@@ -1244,7 +1243,7 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code
           This build: (1) Uses all Windows style paths, (2) Uses primarily Windows batch commands from <code>CMD.exe</code>, with (3) a few extensions from <i>GNUWin32</i>.
         </p>
         <p>
-          This capability should still be considered a work in progress because: (1) it has not been verfied on all targets and tools, and (2) still lacks some of the creature-comforts of the more mature environments (like a function <code>configure.sh</code> script and <code>make menuconfig</code> support).
+          This capability should still be considered a work in progress because: (1) It has not been verfied on all targets and tools, and (2) it still lacks some of the creature-comforts of the more mature environments (like a functional <code>configure.sh</code> script and <code>make menuconfig</code> support).
       </li>
       <li>
         Example Windows native builds for STM32F4Discovery, eZ80, z16f, z8, Z80, and Z180.
@@ -1890,8 +1889,7 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code
       </li>
     </ol>
     <p>
-      These ports uses a GNU arm-nuttx-elf toolchain* under either Linux or Cygwin (with native Windows GNU
-      tools or Cygwin-based GNU tools).
+      These ports uses a GNU arm-nuttx-elf toolchain* under either Linux or Cygwin (with native Windows GNU tools or Cygwin-based GNU tools).
     </p>
     <ul>
       <p>
@@ -1999,8 +1997,7 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code
       <b>Atmel AT91SAM3U</b>.
       This port uses the <a href="http://www.atmel.com/">Atmel</a> SAM3U-EK
       development board that features the AT91SAM3U4E MCU.
-      This port uses a GNU arm-nuttx-elf or arm-eabi toolchain* under either Linux or Cygwin (with native Windows GNU
-      tools or Cygwin-based GNU tools).
+      This port uses a GNU arm-nuttx-elf or arm-eabi toolchain* under either Linux or Cygwin (with native Windows GNU tools or Cygwin-based GNU tools).
     </p>
     <ul>
       <p>
@@ -2884,7 +2881,7 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);
       <b>Zilog z16f Microncontroller</b>.
       This port use the Zilog z16f2800100zcog development kit and the Zilog
       ZDS-II Windows command line tools.
-      The development environment is Cygwin under WinXP.
+      The development environment is either Windows native or Cygwin under Windows.
     </p>
     <ul>
       <p>
@@ -2914,7 +2911,7 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);
     <p>
       Both boards are based on the eZ80F091 part and both use the Zilog ZDS-II
       Windows command line tools.
-      The development environment is Cygwin under WinXP.
+      The development environment is either Windows native or Cygwin under Windows.
     </p>
     <ul>
       <p>
@@ -2946,7 +2943,7 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);
     </ul>
     <p>
       and the Zilog ZDS-II Windows command line tools.
-      The development environment is Cygwin under WinXP.
+      The development environment is either Windows native or Cygwin under Windows.
     </p>
     <ul>
        <p>
diff --git a/nuttx/README.txt b/nuttx/README.txt
index b71012cd8..dc3c9fb67 100644
--- a/nuttx/README.txt
+++ b/nuttx/README.txt
@@ -10,7 +10,7 @@ README
   o Configuring NuttX
     - Instantiating "Canned" Configurations
     - NuttX Configuration Tool
-    - NuttX Configuration Tool from DOS
+    - NuttX Configuration Tool under DOS
   o Toolchains
     - Cross-Development Toolchains
     - NuttX Buildroot Toolchain
@@ -292,16 +292,16 @@ NuttX Configuration Tool
      install 'mconf', make certain that your PATH variable includes
      a path to that installation directory.
 
-NuttX Configuration Tool from DOS
----------------------------------
+NuttX Configuration Tool under DOS
+----------------------------------
 
-Recent versions of NuttX support building NuttX from a native Windows
-CMD.exe shell (see "Native Windows Build" below).  But kconfig-frontends
-is a Linux tool.  There have been some successes building a Windows
-native version of the kconfig-frontends tool, but that is not ready
-for prime time.
+  Recent versions of NuttX support building NuttX from a native Windows
+  CMD.exe shell (see "Native Windows Build" below).  But kconfig-frontends
+  is a Linux tool.  There have been some successes building a Windows
+  native version of the kconfig-frontends tool, but that is not ready
+  for prime time.
 
-At this point, there are only a few options for the Windows user:
+  At this point, there are only a few options for the Windows user:
 
   1. You can run the configuration tool using Cygwin.  However, the
      Cygwin Makefile.win will complain so to do this will, you have
@@ -566,6 +566,12 @@ Native Windows Build
   http://www.mingw.org/.  If you are using GNUWin32, then it is recommended
   the you not install the optional MSYS components as there may be conflicts.
 
+  This capability should still be considered a work in progress because:
+  (1) It has not been verfied on all targets and tools, and
+  (2) itstill lacks some of the creature-comforts of the more mature environments
+  (like a functional configure.sh script and 'make menuconfig' support.
+  See the section "NuttX Configuration Tool under DOS" above).
+
 Installing GNUWin32
 -------------------
 
diff --git a/nuttx/arch/arm/src/arm/up_doirq.c b/nuttx/arch/arm/src/arm/up_doirq.c
index c82587fff..7cd1a6a1b 100644
--- a/nuttx/arch/arm/src/arm/up_doirq.c
+++ b/nuttx/arch/arm/src/arm/up_doirq.c
@@ -79,9 +79,11 @@ void up_doirq(int irq, uint32_t *regs)
   uint32_t *savestate;
 
   /* Nested interrupts are not supported in this implementation.  If you want
-   * implemented nested interrupts, you would have to (1) change the way that
-   * current regs is handled and (2) the design associated with
-   * CONFIG_ARCH_INTERRUPTSTACK.
+   * to implement nested interrupts, you would have to (1) change the way that
+   * current_regs is handled and (2) the design associated with
+   * CONFIG_ARCH_INTERRUPTSTACK.  The savestate variable will not work for
+   * that purpose as implemented here because only the outermost nested
+   * interrupt can result in a context switch (it can probably be deleted).
    */
 
   /* Current regs non-zero indicates that we are processing an interrupt;
diff --git a/nuttx/arch/arm/src/armv7-m/up_doirq.c b/nuttx/arch/arm/src/armv7-m/up_doirq.c
index 375054fba..6063f9ca1 100644
--- a/nuttx/arch/arm/src/armv7-m/up_doirq.c
+++ b/nuttx/arch/arm/src/armv7-m/up_doirq.c
@@ -79,9 +79,11 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
   uint32_t *savestate;
 
   /* Nested interrupts are not supported in this implementation.  If you want
-   * implemented nested interrupts, you would have to (1) change the way that
-   * current regs is handled and (2) the design associated with
-   * CONFIG_ARCH_INTERRUPTSTACK.
+   * to implement nested interrupts, you would have to (1) change the way that
+   * current_regs is handled and (2) the design associated with
+   * CONFIG_ARCH_INTERRUPTSTACK.  The savestate variable will not work for
+   * that purpose as implemented here because only the outermost nested
+   * interrupt can result in a context switch (it can probably be deleted).
    */
 
   /* Current regs non-zero indicates that we are processing an interrupt;
diff --git a/nuttx/arch/avr/src/avr/up_doirq.c b/nuttx/arch/avr/src/avr/up_doirq.c
index e38bf7fa8..7533d2159 100644
--- a/nuttx/arch/avr/src/avr/up_doirq.c
+++ b/nuttx/arch/avr/src/avr/up_doirq.c
@@ -79,9 +79,11 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs)
   uint8_t *savestate;
 
   /* Nested interrupts are not supported in this implementation.  If you want
-   * implemented nested interrupts, you would have to (1) change the way that
-   * current regs is handled and (2) the design associated with
-   * CONFIG_ARCH_INTERRUPTSTACK.
+   * to implement nested interrupts, you would have to (1) change the way that
+   * current_regs is handled and (2) the design associated with
+   * CONFIG_ARCH_INTERRUPTSTACK.  The savestate variable will not work for
+   * that purpose as implemented here because only the outermost nested
+   * interrupt can result in a context switch (it can probably be deleted).
    */
 
   /* Current regs non-zero indicates that we are processing an interrupt;
diff --git a/nuttx/arch/avr/src/avr32/up_doirq.c b/nuttx/arch/avr/src/avr32/up_doirq.c
index 7ade35fad..2d4a5e14a 100644
--- a/nuttx/arch/avr/src/avr32/up_doirq.c
+++ b/nuttx/arch/avr/src/avr32/up_doirq.c
@@ -79,9 +79,11 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
   uint32_t *savestate;
 
   /* Nested interrupts are not supported in this implementation.  If you want
-   * implemented nested interrupts, you would have to (1) change the way that
-   * current regs is handled and (2) the design associated with
-   * CONFIG_ARCH_INTERRUPTSTACK.
+   * to implement nested interrupts, you would have to (1) change the way that
+   * current_regs is handled and (2) the design associated with
+   * CONFIG_ARCH_INTERRUPTSTACK.  The savestate variable will not work for
+   * that purpose as implemented here because only the outermost nested
+   * interrupt can result in a context switch (it can probably be deleted).
    */
 
   /* Current regs non-zero indicates that we are processing an interrupt;
diff --git a/nuttx/arch/hc/src/common/up_doirq.c b/nuttx/arch/hc/src/common/up_doirq.c
index d03b007df..4a56dedbd 100644
--- a/nuttx/arch/hc/src/common/up_doirq.c
+++ b/nuttx/arch/hc/src/common/up_doirq.c
@@ -79,9 +79,11 @@ uint8_t *up_doirq(int irq, uint8_t *regs)
   uint8_t *savestate;
 
   /* Nested interrupts are not supported in this implementation.  If you want
-   * implemented nested interrupts, you would have to (1) change the way that
-   * current regs is handled and (2) the design associated with
-   * CONFIG_ARCH_INTERRUPTSTACK.
+   * to implement nested interrupts, you would have to (1) change the way that
+   * current_regs is handled and (2) the design associated with
+   * CONFIG_ARCH_INTERRUPTSTACK.  The savestate variable will not work for
+   * that purpose as implemented here because only the outermost nested
+   * interrupt can result in a context switch (it can probably be deleted).
    */
 
   /* Current regs non-zero indicates that we are processing an interrupt;
diff --git a/nuttx/arch/mips/src/mips32/up_doirq.c b/nuttx/arch/mips/src/mips32/up_doirq.c
index 29cdf9c60..b963881e3 100644
--- a/nuttx/arch/mips/src/mips32/up_doirq.c
+++ b/nuttx/arch/mips/src/mips32/up_doirq.c
@@ -79,9 +79,11 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
   uint32_t *savestate;
 
   /* Nested interrupts are not supported in this implementation.  If you want
-   * implemented nested interrupts, you would have to (1) change the way that
-   * current regs is handled and (2) the design associated with
-   * CONFIG_ARCH_INTERRUPTSTACK.
+   * to implement nested interrupts, you would have to (1) change the way that
+   * current_regs is handled and (2) the design associated with
+   * CONFIG_ARCH_INTERRUPTSTACK.  The savestate variable will not work for
+   * that purpose as implemented here because only the outermost nested
+   * interrupt can result in a context switch (it can probably be deleted).
    */
 
   /* Current regs non-zero indicates that we are processing an interrupt;
diff --git a/nuttx/arch/sh/src/common/up_doirq.c b/nuttx/arch/sh/src/common/up_doirq.c
index 717196682..185fa9684 100644
--- a/nuttx/arch/sh/src/common/up_doirq.c
+++ b/nuttx/arch/sh/src/common/up_doirq.c
@@ -79,6 +79,15 @@ uint32_t *up_doirq(int irq, uint32_t* regs)
     {
        uint32_t *savestate;
 
+       /* Nested interrupts are not supported in this implementation.  If
+        * you want to implement nested interrupts, you would have to (1)
+        * change the way that current_regs is handled and (2) the design
+        * associated with CONFIG_ARCH_INTERRUPTSTACK.  The savestate
+        * variable will not work for that purpose as implemented here
+        * because only the outermost nested interrupt can result in a
+        * context switch (it can probably be deleted).
+        */
+
        /* Current regs non-zero indicates that we are processing
         * an interrupt; current_regs is also used to manage
         * interrupt level context switches.
diff --git a/nuttx/arch/z16/src/common/up_doirq.c b/nuttx/arch/z16/src/common/up_doirq.c
index 670e6985d..9964f4432 100644
--- a/nuttx/arch/z16/src/common/up_doirq.c
+++ b/nuttx/arch/z16/src/common/up_doirq.c
@@ -90,6 +90,15 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs)
     {
       FAR chipreg_t *savestate;
 
+      /* Nested interrupts are not supported in this implementation.  If
+       * you want to implement nested interrupts, you would have to (1) change
+       * the way that current_regs is handled and (2) the design associated
+       * with CONFIG_ARCH_INTERRUPTSTACK.  The savestate variable will not
+       * work for that purpose as implemented here because only the outermost
+       * nested interrupt can result in a context switch (it can probably be
+       * deleted).
+       */
+
       /* Current regs non-zero indicates that we are processing
        * an interrupt; current_regs is also used to manage
        * interrupt level context switches.
diff --git a/nuttx/arch/z80/include/z80/chip.h b/nuttx/arch/z80/include/z80/chip.h
index 5c0c61166..c355eb788 100644
--- a/nuttx/arch/z80/include/z80/chip.h
+++ b/nuttx/arch/z80/include/z80/chip.h
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_Z80_SRC_Z80_CHIP_H
-#define __ARCH_Z80_SRC_Z80_CHIP_H
+#ifndef __ARCH_Z80_INCLUDE_Z80_CHIP_H
+#define __ARCH_Z80_INCLUDE_Z80_CHIP_H
 
 /************************************************************************************
  * Included Files
@@ -76,4 +76,4 @@ extern "C" {
 #endif
 #endif
 
-#endif  /* __ARCH_Z80_SRC_Z80_CHIP_H */
+#endif  /* __ARCH_Z80_INCLUDE_Z80_CHIP_H */
diff --git a/nuttx/arch/z80/src/common/up_internal.h b/nuttx/arch/z80/src/common/up_internal.h
index def13b546..5f1750b64 100644
--- a/nuttx/arch/z80/src/common/up_internal.h
+++ b/nuttx/arch/z80/src/common/up_internal.h
@@ -94,28 +94,26 @@
 
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
+extern "C"
+{
 #endif
 
 /* Supplied by chip- or board-specific logic */
 
-EXTERN void up_irqinitialize(void);
-EXTERN int  up_timerisr(int irq, FAR chipreg_t *regs);
+void up_irqinitialize(void);
+int  up_timerisr(int irq, FAR chipreg_t *regs);
 
 #ifdef USE_LOWSERIALINIT
-EXTERN void up_lowserialinit(void);
+void up_lowserialinit(void);
 #endif
 
 /* Defined in up_doirq.c */
 
-EXTERN FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs);
+FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs);
 
 /* Define in up_sigdeliver */
 
-EXTERN void up_sigdeliver(void);
+void up_sigdeliver(void);
 
 /* Defined in CPU-specific logic (only for Z180) */
 
@@ -132,7 +130,7 @@ void up_addregion(void);
 /* Defined in up_serial.c */
 
 #ifdef USE_SERIALDRIVER
-EXTERN void up_serialinit(void);
+void up_serialinit(void);
 #else
 # define up_serialinit()
 #endif
@@ -140,7 +138,7 @@ EXTERN void up_serialinit(void);
 /* Defined in drivers/lowconsole.c */
 
 #ifdef CONFIG_DEV_LOWCONSOLE
-EXTERN void lowconsole_init(void);
+void lowconsole_init(void);
 #else
 # define lowconsole_init()
 #endif
@@ -159,14 +157,14 @@ extern void up_puts(const char *str);
 
 /* Defined in up_timerisr.c */
 
-EXTERN void up_timerinit(void);
+void up_timerinit(void);
 
 /* Defined in board/up_leds.c */
 
 #ifdef CONFIG_ARCH_LEDS
-EXTERN void up_ledinit(void);
-EXTERN void up_ledon(int led);
-EXTERN void up_ledoff(int led);
+void up_ledinit(void);
+void up_ledon(int led);
+void up_ledoff(int led);
 #else
 # define up_ledinit()
 # define up_ledon(led)
@@ -176,16 +174,16 @@ EXTERN void up_ledoff(int led);
 /* Architecture specific hook into the timer interrupt handler */
 
 #ifdef CONFIG_ARCH_TIMERHOOK
-EXTERN void up_timerhook(void);
+void up_timerhook(void);
 #endif
 
 /* Defined in board/up_network.c */
 
 #ifdef CONFIG_NET
-EXTERN int  up_netinitialize(void);
-EXTERN void up_netuninitialize(void);
+int  up_netinitialize(void);
+void up_netuninitialize(void);
 # ifdef CONFIG_ARCH_MCFILTER
-EXTERN int up_multicastfilter(FAR struct uip_driver_s *dev, FAR uint8_t *mac, bool enable);
+int up_multicastfilter(FAR struct uip_driver_s *dev, FAR uint8_t *mac, bool enable);
 # else
 #   define up_multicastfilter(dev, mac, enable)
 # endif
@@ -197,19 +195,18 @@ EXTERN int up_multicastfilter(FAR struct uip_driver_s *dev, FAR uint8_t *mac, bo
 
 /* Return the current value of the stack pointer (used in stack dump logic) */
 
-EXTERN uint16_t up_getsp(void);
+uint16_t up_getsp(void);
 
 /* Dump stack and registers */
 
 #ifdef CONFIG_ARCH_STACKDUMP
-EXTERN void up_stackdump(void);
+void up_stackdump(void);
 # define REGISTER_DUMP() _REGISTER_DUMP()
 #else
 # define up_stackdump()
 # define REGISTER_DUMP()
 #endif
 
-#undef EXTERN
 #ifdef __cplusplus
 }
 #endif
diff --git a/nuttx/arch/z80/src/ez80/switch.h b/nuttx/arch/z80/src/ez80/switch.h
index 0bac6aed1..0970b25ce 100644
--- a/nuttx/arch/z80/src/ez80/switch.h
+++ b/nuttx/arch/z80/src/ez80/switch.h
@@ -67,7 +67,14 @@
 
 #define IN_INTERRUPT()           (current_regs != NULL)
 
-/* The following macro is used when the system enters interrupt handling logic */
+/* The following macro is used when the system enters interrupt handling logic
+ *
+ * NOTE: Nested interrupts are not supported in this implementation.  If you want
+ * to implement nested interrupts, you would have to change the way that
+ * current_regs is handled.  The savestate variable would not work for
+ * that purpose as implemented here because only the outermost nested
+ * interrupt can result in a context switch (it can probably be deleted).
+ */
 
 #define DECL_SAVESTATE() \
   FAR chipreg_t *savestate
@@ -132,33 +139,30 @@ extern volatile chipreg_t *current_regs;
 
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
+extern "C"
+{
 #endif
 
 /* Defined in ez80_copystate.c */
 
-EXTERN void ez80_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src);
+void ez80_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src);
 
 /* Defined in ez80_saveusercontext.asm */
 
-EXTERN int ez80_saveusercontext(FAR chipreg_t *regs);
+int ez80_saveusercontext(FAR chipreg_t *regs);
 
 /* Defined in ez80_restorecontext.asm */
 
-EXTERN void ez80_restorecontext(FAR chipreg_t *regs);
+void ez80_restorecontext(FAR chipreg_t *regs);
 
 /* Defined in ez80_sigsetup.c */
 
-EXTERN void ez80_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, chipreg_t *regs);
+void ez80_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, chipreg_t *regs);
 
 /* Defined in ez80_registerdump.c */
 
-EXTERN void ez80_registerdump(void);
+void ez80_registerdump(void);
 
-#undef EXTERN
 #ifdef __cplusplus
 }
 #endif
diff --git a/nuttx/arch/z80/src/z180/switch.h b/nuttx/arch/z80/src/z180/switch.h
index ae80f4f76..7bf851a7c 100644
--- a/nuttx/arch/z80/src/z180/switch.h
+++ b/nuttx/arch/z80/src/z180/switch.h
@@ -77,9 +77,11 @@
  * - savestate holds the previous value of current_state.
  * - savecpr holds the previous value of current_cpr.
  *
- * TODO:  I think this logic is bad... I do not thing that this will really
- * handle nested interrupts correctly.  What if we are nested and then a
- * context switch occurs?  current_regs will not be updated correctly!
+ * NOTE: Nested interrupts are not supported in this implementation.  If you want
+ * to implement nested interrupts, you would have to change the way that
+ * current_regs/cbr is handled.  The savestate/savecbr variables would not work
+ * for that purpose as implemented here because only the outermost nested
+ * interrupt can result in a context switch (they can probabaly be deleted).
  */
 
 #define DECL_SAVESTATE() \
@@ -203,33 +205,30 @@ extern uint8_t current_cbr;
 
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
+extern "C"
+{
 #endif
 
 /* Defined in z180_copystate.c */
 
-EXTERN void z180_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src);
+void z180_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src);
 
 /* Defined in z180_saveusercontext.asm */
 
-EXTERN int z180_saveusercontext(FAR chipreg_t *regs);
+int z180_saveusercontext(FAR chipreg_t *regs);
 
 /* Defined in z180_restoreusercontext.asm */
 
-EXTERN void z180_restoreusercontext(FAR chipreg_t *regs);
+void z180_restoreusercontext(FAR chipreg_t *regs);
 
 /* Defined in z180_sigsetup.c */
 
-EXTERN void z180_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs);
+void z180_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs);
 
 /* Defined in z180_registerdump.c */
 
-EXTERN void z180_registerdump(void);
+void z180_registerdump(void);
 
-#undef EXTERN
 #ifdef __cplusplus
 }
 #endif
diff --git a/nuttx/arch/z80/src/z8/switch.h b/nuttx/arch/z80/src/z8/switch.h
index 45089947c..17f15b6da 100644
--- a/nuttx/arch/z80/src/z8/switch.h
+++ b/nuttx/arch/z80/src/z8/switch.h
@@ -112,7 +112,14 @@
 #define IN_INTERRUPT() \
   (g_z8irqstate.state != Z8_IRQSTATE_NONE)
 
-/* The following macro is used when the system enters interrupt handling logic */
+/* The following macro is used when the system enters interrupt handling logic
+ *
+ * NOTE: Nested interrupts are not supported in this implementation.  If you want
+ * to implement nested interrupts, you would have to change the way that
+ * current_regs is handled.  The savestate variable would not work for
+ * that purpose as implemented here because only the outermost nested
+ * interrupt can result in a context switch (it can probably be deleted).
+ */
 
 #define DECL_SAVESTATE() \
   struct z8_irqstate_s savestate
@@ -216,37 +223,34 @@ extern struct z8_irqstate_s g_z8irqstate;
 
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
+extern "C"
+{
 #endif
 
 /* Defined in z8_irq.c */
 
-EXTERN void up_maskack_irq(int irq);
+void up_maskack_irq(int irq);
 
 /* Defined in z8_saveusercontext.asm */
 
-EXTERN int z8_saveusercontext(FAR chipreg_t *regs);
+int z8_saveusercontext(FAR chipreg_t *regs);
 
 /* Defined in z8_saveirqcontext.c */
 
-EXTERN void z8_saveirqcontext(FAR chipreg_t *regs);
+void z8_saveirqcontext(FAR chipreg_t *regs);
 
 /* Defined in z8_restorecontext.asm */
 
-EXTERN void z8_restorecontext(FAR chipreg_t *regs);
+void z8_restorecontext(FAR chipreg_t *regs);
 
 /* Defined in z8_sigsetup.c */
 
-EXTERN void z8_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs);
+void z8_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs);
 
 /* Defined in z8_registerdump.c */
 
-EXTERN void z8_registerdump(void);
+void z8_registerdump(void);
 
-#undef EXTERN
 #ifdef __cplusplus
 }
 #endif
diff --git a/nuttx/arch/z80/src/z80/switch.h b/nuttx/arch/z80/src/z80/switch.h
index 3732a32a3..4a49c70ef 100644
--- a/nuttx/arch/z80/src/z80/switch.h
+++ b/nuttx/arch/z80/src/z80/switch.h
@@ -66,7 +66,14 @@
 
 #define IN_INTERRUPT()           (current_regs != NULL)
 
-/* The following macro is used when the system enters interrupt handling logic */
+/* The following macro is used when the system enters interrupt handling logic
+ *
+ * NOTE: Nested interrupts are not supported in this implementation.  If you want
+ * to implement nested interrupts, you would have to change the way that
+ * current_regs is handled.  The savestate variable would not work for
+ * that purpose as implemented here because only the outermost nested
+ * interrupt can result in a context switch (it can probably be deleted).
+ */
 
 #define DECL_SAVESTATE() \
   FAR chipreg_t *savestate
@@ -131,33 +138,30 @@ extern volatile chipreg_t *current_regs;
 
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
+extern "C"
+{
 #endif
 
 /* Defined in z80_copystate.c */
 
-EXTERN void z80_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src);
+void z80_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src);
 
 /* Defined in z80_saveusercontext.asm */
 
-EXTERN int z80_saveusercontext(FAR chipreg_t *regs);
+int z80_saveusercontext(FAR chipreg_t *regs);
 
 /* Defined in z80_restoreusercontext.asm */
 
-EXTERN void z80_restoreusercontext(FAR chipreg_t *regs);
+void z80_restoreusercontext(FAR chipreg_t *regs);
 
 /* Defined in z80_sigsetup.c */
 
-EXTERN void z80_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs);
+void z80_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs);
 
 /* Defined in z80_registerdump.c */
 
-EXTERN void z80_registerdump(void);
+void z80_registerdump(void);
 
-#undef EXTERN
 #ifdef __cplusplus
 }
 #endif
-- 
cgit v1.2.3


From 6953365d30f06846a8f3877b73e01ee7d8321db0 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Mon, 24 Dec 2012 20:22:14 +0000
Subject: Fix several build issues noted by Mike Smith

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5459 42af7a65-404d-4744-a932-0658087f49c3
---
 apps/ChangeLog.txt                          | 10 ++++-
 apps/builtin/Makefile                       |  5 ++-
 apps/examples/nettest/Makefile              | 57 +++++++++++++++--------------
 nuttx/ChangeLog                             |  3 ++
 nuttx/arch/arm/src/arm/up_head.S            | 51 +++++++++++++++++++-------
 nuttx/configs/ntosd-dm320/nettest/setenv.sh | 26 ++++++++++---
 nuttx/configs/ntosd-dm320/nsh/setenv.sh     | 26 ++++++++++---
 nuttx/configs/ntosd-dm320/ostest/setenv.sh  | 26 ++++++++++---
 nuttx/configs/ntosd-dm320/poll/setenv.sh    | 26 ++++++++++---
 nuttx/configs/ntosd-dm320/thttpd/setenv.sh  | 26 ++++++++++---
 nuttx/configs/ntosd-dm320/udp/setenv.sh     | 26 ++++++++++---
 nuttx/configs/ntosd-dm320/uip/setenv.sh     | 26 ++++++++++---
 12 files changed, 228 insertions(+), 80 deletions(-)

(limited to 'nuttx/arch')

diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt
index 09a4f634d..ea1b247f5 100644
--- a/apps/ChangeLog.txt
+++ b/apps/ChangeLog.txt
@@ -439,12 +439,18 @@
 	* Makefiles: Removed dependency of distclean on clean in most top-level
 	  files.  It makes sense for 'leaf' Makefiles to have this dependency,
 	  but it does not make sense for upper-level Makefiles.
-	* namedapp/: Renamed to builtins in preparation for another change.
+	* apps/namedapp/: Renamed to builtins in preparation for another change.
 	* .context:  Removed the .context kludge.  This caused lots of problems
 	  when changing configurations because there is no easy way to get the
 	  system to rebuild the context.  Now, the context will be rebuilt
 	  whenever there is a change in either .config or the Makefile.
-	* builtin/registry:  Updated new built-in registration logic to handle
+	* apps/builtin/registry:  Updated new built-in registration logic to handle
 	  cases where (1) old apps/.config is used, and (2) applications ared
 	  removed, not just added.
+	* apps/examples/nettest/Makefile:  Fix an error that crept in during
+	  some of the recent, massive build system changes.
+	* apps/builtin/Makefile:  Need to have auto-generated header files
+	  in place early in the dependency generation phase to avoid warnings.
+	  It is not important if they are only stubbed out header files at
+	  this build phase.
 
diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile
index 0efb832f8..ccb860c88 100644
--- a/apps/builtin/Makefile
+++ b/apps/builtin/Makefile
@@ -75,6 +75,9 @@ $(AOBJS): %$(OBJEXT): %.S
 $(COBJS): %$(OBJEXT): %.c
 	$(call COMPILE, $<, $@)
 
+registry/.updated:
+	$(V) $(MAKE) -C registry .updated TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)"
+
 builtin_list.h: registry/.updated
 	$(call DELFILE, builtin_list.h)
 	$(Q) touch builtin_list.h
@@ -110,7 +113,7 @@ endif
 context:
 	$(Q) $(MAKE) -C registry context TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)"
 
-.depend: Makefile $(SRCS)
+.depend: Makefile $(SRCS) builtin_list.h builtin_proto.h
 	$(Q) $(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep
 	$(Q) touch $@
 
diff --git a/apps/examples/nettest/Makefile b/apps/examples/nettest/Makefile
index a0308713c..5368bdefc 100644
--- a/apps/examples/nettest/Makefile
+++ b/apps/examples/nettest/Makefile
@@ -39,64 +39,64 @@ include $(APPDIR)/Make.defs
 
 # Basic TCP networking test
 
-TARG_ASRCS	= 
-TARG_AOBJS	= $(TARG_ASRCS:.S=$(OBJEXT))
+TARG_ASRCS = 
+TARG_AOBJS = $(TARG_ASRCS:.S=$(OBJEXT))
 
-TARG_CSRCS	= nettest.c
+TARG_CSRCS = nettest.c
 ifeq ($(CONFIG_EXAMPLES_NETTEST_SERVER),y)
-TARG_CSRCS	+= nettest_server.c
+TARG_CSRCS += nettest_server.c
 else
-TARG_CSRCS	+= nettest_client.c
+TARG_CSRCS += nettest_client.c
 endif
 
-TARG_COBJS	= $(TARG_CSRCS:.c=$(OBJEXT))
+TARG_COBJS = $(TARG_CSRCS:.c=$(OBJEXT))
 
-TARG_SRCS	= $(TARG_ASRCS) $(TARG_CSRCS)
-TARG_OBJS	= $(TARG_AOBJS) $(TARG_COBJS)
+TARG_SRCS = $(TARG_ASRCS) $(TARG_CSRCS)
+TARG_OBJS = $(TARG_AOBJS) $(TARG_COBJS)
 
 ifeq ($(CONFIG_WINDOWS_NATIVE),y)
-  TARG_BIN		= ..\..\libapps$(LIBEXT)
+  TARG_BIN = ..\..\libapps$(LIBEXT)
 else
 ifeq ($(WINTOOL),y)
-  TARG_BIN		= ..\\..\\libapps$(LIBEXT)
+  TARG_BIN = ..\\..\\libapps$(LIBEXT)
 else
-  TARG_BIN		= ../../libapps$(LIBEXT)
+  TARG_BIN = ../../libapps$(LIBEXT)
 endif
 endif
 
-HOSTCFLAGS	+= -DCONFIG_EXAMPLES_NETTEST_HOST=1
+HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_HOST=1
 ifeq ($(CONFIG_EXAMPLES_NETTEST_SERVER),y)
-HOSTCFLAGS	+= -DCONFIG_EXAMPLES_NETTEST_SERVER=1 \
-		   -DCONFIG_EXAMPLES_NETTEST_CLIENTIP="$(CONFIG_EXAMPLES_NETTEST_CLIENTIP)"
+HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_SERVER=1 -DCONFIG_EXAMPLES_NETTEST_CLIENTIP="$(CONFIG_EXAMPLES_NETTEST_CLIENTIP)"
 endif
 ifeq ($(CONFIG_EXAMPLES_NETTEST_PERFORMANCE),y)
-HOSTCFLAGS	+= -DCONFIG_EXAMPLES_NETTEST_PERFORMANCE=1
+HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_PERFORMANCE=1
 endif
 
-HOST_SRCS	= host.c
+HOST_SRCS = host.c
 ifeq ($(CONFIG_EXAMPLES_NETTEST_SERVER),y)
-HOST_SRCS	+= nettest_client.c
+HOST_SRCS += nettest_client.c
 else
-HOST_SRCS	+= nettest_server.c
+HOST_SRCS += nettest_server.c
 endif
 
-HOST_OBJS	= $(HOST_SRCS:.c=.o)
-HOST_BIN	= host
+HOSTOBJEXT ?= .hobj
+HOST_OBJS = $(HOST_SRCS:.c=$(HOSTOBJEXT))
+HOST_BIN = host
 
-ROOTDEPPATH	= --dep-path .
+ROOTDEPPATH = --dep-path .
 
 # NET test built-in application info
 
-APPNAME		= nettest
-PRIORITY	= SCHED_PRIORITY_DEFAULT
-STACKSIZE	= 2048
+APPNAME = nettest
+PRIORITY = SCHED_PRIORITY_DEFAULT
+STACKSIZE = 2048
 
 # Common build
 
-VPATH		= 
+VPATH = 
 
 all: .built $(HOST_BIN)
-.PHONY:	clean depend distclean
+.PHONY: clean depend distclean
 
 $(TARG_AOBJS): %$(OBJEXT): %.S
 	$(call ASSEMBLE, $<, $@)
@@ -104,7 +104,7 @@ $(TARG_AOBJS): %$(OBJEXT): %.S
 $(TARG_COBJS): %$(OBJEXT): %.c
 	$(call COMPILE, $<, $@)
 
-$(HOST_OBJS): %.o: %.c
+$(HOST_OBJS): %$(HOSTOBJEXT): %.c
 	@echo "CC:  $<"
 	@$(HOSTCC) -c $(HOSTCFLAGS) $< -o $@
 
@@ -113,7 +113,7 @@ $(HOST_BIN): $(HOST_OBJS)
 	@$(HOSTCC) $(HOSTLDFLAGS) $(HOST_OBJS) -o $@
 
 .built: $(TARG_OBJS)
-	$(call ARCHIVE, $(BIN), $(TARG_OBJS))
+	$(call ARCHIVE, $(TARG_BIN), $(TARG_OBJS))
 	@touch .built
 
 ifeq ($(CONFIG_NSH_BUILTIN_APPS),y)
@@ -132,6 +132,7 @@ endif
 depend: .depend
 
 clean:
+	$(call DELFILE, *$(HOSTOBJEXT))
 	$(call DELFILE, $(HOST_BIN))
 	$(call DELFILE, .built)
 	$(call CLEAN)
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 6c6fd7843..c5cc9b54a 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3815,4 +3815,7 @@
 	* sched/sig_timedwait.c:  Should always move the time up to the next
 	  largest number of system ticks.  The logic was rounding.  Noted by
 	  Petteri Aimonen.
+	* arch/arm/src/up_head.S:  Fix backward conditional compilation.  NOTE
+	  there is a issue of ARM9 systems with low vectors and large memories
+	  that will have to be addressed in the future.
 
diff --git a/nuttx/arch/arm/src/arm/up_head.S b/nuttx/arch/arm/src/arm/up_head.S
index 91d67fd15..46efd8772 100644
--- a/nuttx/arch/arm/src/arm/up_head.S
+++ b/nuttx/arch/arm/src/arm/up_head.S
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/arm/up_head.S
+ * arch/arm/src/arm/up_pghead.S
  *
  *   Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -78,6 +78,10 @@
    * beginning of FLASH.
    */
 
+#  if !defined(CONFIG_FLASH_START) || !defined(CONFIG_FLASH_VSTART)
+#    error "CONFIG_FLASH_START or CONFIG_FLASH_VSTART is not defined"
+#  endif
+
 #  if CONFIG_FLASH_START == CONFIG_FLASH_VSTART
 #    define CONFIG_IDENTITY_TEXTMAP 1
 #  endif
@@ -102,6 +106,10 @@
    * beginning of FLASH.
    */
 
+#  if !defined(CONFIG_FLASH_START) || !defined(CONFIG_FLASH_VSTART)
+#    error "CONFIG_FLASH_START or CONFIG_FLASH_VSTART is not defined"
+#  endif
+
 #  if CONFIG_FLASH_START == CONFIG_FLASH_VSTART
 #    define CONFIG_IDENTITY_TEXTMAP 1
 #  endif
@@ -120,6 +128,10 @@
    * beginning of RAM.
    */
 
+#  if !defined(CONFIG_DRAM_START) || !defined(CONFIG_DRAM_VSTART)
+#    error "CONFIG_DRAM_START or CONFIG_DRAM_VSTART is not defined"
+#  endif
+
 #  if CONFIG_DRAM_START == CONFIG_DRAM_VSTART
 #    define CONFIG_IDENTITY_TEXTMAP 1
 #  endif
@@ -162,26 +174,37 @@
  * Assembly Macros
  ****************************************************************************/
 
-/* The ARM9 L1 page table can be placed at the beginning or at the end of the
- * RAM space.  This decision is based on the placement of the vector area:
- * If the vectors are place in low memory at address 0x0000 0000, then the
- * page table is placed in high memory; if the vectors are placed in high
- * memory at address 0xfff0 0000, then the page table is locating at the
- * beginning of RAM.
+/* The ARM9 L1 page table can be placed at the beginning or at the end of
+ * the RAM space.  This decision is based on the placement of the vector
+ * area: If the vectors are place in low memory at address 0x0000 0000, then
+ * the page table is placed in high memory; if the vectors are placed in
+ * high memory at address 0xfff0 0000, then the page table is locating at
+ * the beginning of RAM.
  *
- * For the special case where (1) the program executes out of RAM, and (2) the
- * page is located at the beginning of RAM, then the following macro can
- * easily find the physical address of the section that includes the first
- * part of the text region:  Since the page table is closely related to the
- * NuttX base address in this case, we can convert the page table base address
- * to the base address of the section containing both.
+ * For the special case where (1) the program executes out of RAM, and (2)
+ * the page is located at the beginning of RAM (i.e., the high vector case),
+ * then the following macro can easily find the physical address of the
+ * section that includes the first part of the text region:  Since the page
+ * table is closely related to the NuttX base address in this case, we can
+ * convert the page table base address to the base address of the section
+ * containing both.
+ */
+
+/* REVISIT:  This works now of the low vector case only because the RAM
+ * sizes that we have been dealing with are less then 1MB so that both the
+ * page table and the vector table are in the same 1MB RAM block.  But
+ * this will certainly break later. Hence, the annoying warning.
  */
 
 #ifdef CONFIG_ARCH_LOWVECTORS
+#  warning "REVISIT"
+#endif
+
+//#ifndef CONFIG_ARCH_LOWVECTORS
 	.macro	mksection, section, pgtable
 	bic	\section, \pgtable, #0x000ff000
 	.endm
-#endif
+//#endif
 
 /* This macro will modify r0, r1, r2 and r14 */
 
diff --git a/nuttx/configs/ntosd-dm320/nettest/setenv.sh b/nuttx/configs/ntosd-dm320/nettest/setenv.sh
index 6090d4cea..cfb438ce7 100755
--- a/nuttx/configs/ntosd-dm320/nettest/setenv.sh
+++ b/nuttx/configs/ntosd-dm320/nettest/setenv.sh
@@ -32,15 +32,31 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-if [ "$(basename $0)" = "setenv.sh" ] ; then
+if [ "$_" = "$0" ] ; then
   echo "You must source this script, not run it!" 1>&2
   exit 1
 fi
 
-if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi
-
 WD=`pwd`
-export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin
-export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
 
 echo "PATH : ${PATH}"
diff --git a/nuttx/configs/ntosd-dm320/nsh/setenv.sh b/nuttx/configs/ntosd-dm320/nsh/setenv.sh
index a84e68884..005aa8153 100755
--- a/nuttx/configs/ntosd-dm320/nsh/setenv.sh
+++ b/nuttx/configs/ntosd-dm320/nsh/setenv.sh
@@ -32,15 +32,31 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-if [ "$(basename $0)" = "setenv.sh" ] ; then
+if [ "$_" = "$0" ] ; then
   echo "You must source this script, not run it!" 1>&2
   exit 1
 fi
 
-if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi
-
 WD=`pwd`
-export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin
-export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
 
 echo "PATH : ${PATH}"
diff --git a/nuttx/configs/ntosd-dm320/ostest/setenv.sh b/nuttx/configs/ntosd-dm320/ostest/setenv.sh
index a65be2677..75d6f0cd0 100755
--- a/nuttx/configs/ntosd-dm320/ostest/setenv.sh
+++ b/nuttx/configs/ntosd-dm320/ostest/setenv.sh
@@ -32,15 +32,31 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-if [ "$(basename $0)" = "setenv.sh" ] ; then
+if [ "$_" = "$0" ] ; then
   echo "You must source this script, not run it!" 1>&2
   exit 1
 fi
 
-if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi
-
 WD=`pwd`
-export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin
-export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
 
 echo "PATH : ${PATH}"
diff --git a/nuttx/configs/ntosd-dm320/poll/setenv.sh b/nuttx/configs/ntosd-dm320/poll/setenv.sh
index de3b64ea9..427ffe26a 100755
--- a/nuttx/configs/ntosd-dm320/poll/setenv.sh
+++ b/nuttx/configs/ntosd-dm320/poll/setenv.sh
@@ -32,15 +32,31 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-if [ "$(basename $0)" = "setenv.sh" ] ; then
+if [ "$_" = "$0" ] ; then
   echo "You must source this script, not run it!" 1>&2
   exit 1
 fi
 
-if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi
-
 WD=`pwd`
-export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin
-export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
 
 echo "PATH : ${PATH}"
diff --git a/nuttx/configs/ntosd-dm320/thttpd/setenv.sh b/nuttx/configs/ntosd-dm320/thttpd/setenv.sh
index 92ff91700..ea38c09a5 100755
--- a/nuttx/configs/ntosd-dm320/thttpd/setenv.sh
+++ b/nuttx/configs/ntosd-dm320/thttpd/setenv.sh
@@ -32,15 +32,31 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-if [ "$(basename $0)" = "setenv.sh" ] ; then
+if [ "$_" = "$0" ] ; then
   echo "You must source this script, not run it!" 1>&2
   exit 1
 fi
 
-if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi
-
 WD=`pwd`
-export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin
-export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
 
 echo "PATH : ${PATH}"
diff --git a/nuttx/configs/ntosd-dm320/udp/setenv.sh b/nuttx/configs/ntosd-dm320/udp/setenv.sh
index 052413b08..92995bee5 100755
--- a/nuttx/configs/ntosd-dm320/udp/setenv.sh
+++ b/nuttx/configs/ntosd-dm320/udp/setenv.sh
@@ -32,15 +32,31 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-if [ "$(basename $0)" = "setenv.sh" ] ; then
+if [ "$_" = "$0" ] ; then
   echo "You must source this script, not run it!" 1>&2
   exit 1
 fi
 
-if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi
-
 WD=`pwd`
-export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin
-export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
 
 echo "PATH : ${PATH}"
diff --git a/nuttx/configs/ntosd-dm320/uip/setenv.sh b/nuttx/configs/ntosd-dm320/uip/setenv.sh
index 988e0a126..33c252e1e 100755
--- a/nuttx/configs/ntosd-dm320/uip/setenv.sh
+++ b/nuttx/configs/ntosd-dm320/uip/setenv.sh
@@ -32,15 +32,31 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-if [ "$(basename $0)" = "setenv.sh" ] ; then
+if [ "$_" = "$0" ] ; then
   echo "You must source this script, not run it!" 1>&2
   exit 1
 fi
 
-if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi
-
 WD=`pwd`
-export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin
-export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
 
 echo "PATH : ${PATH}"
-- 
cgit v1.2.3


From e0be95b9a02ebd38cc370b81586371bd93e6ac76 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Fri, 28 Dec 2012 23:40:54 +0000
Subject: Add board support at configs/zp214xpa for the The0.net ZP213X/4XPA
 board with the LPC2148; Add configurations sim/nxlines.  convert
 mcu123-lpc214x/nsh to use the kconfig-frontends.

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5465 42af7a65-404d-4744-a932-0658087f49c3
---
 apps/examples/hidkbd/hidkbd_main.c             |  11 +-
 nuttx/ChangeLog                                |   6 +
 nuttx/Documentation/NuttX.html                 |   5 +-
 nuttx/arch/arm/src/lpc214x/Kconfig             | 134 +++++
 nuttx/configs/Kconfig                          |  14 +-
 nuttx/configs/README.txt                       |   5 +
 nuttx/configs/mcu123-lpc214x/README.txt        |  18 +-
 nuttx/configs/mcu123-lpc214x/nsh/appconfig     |  44 --
 nuttx/configs/mcu123-lpc214x/nsh/defconfig     | 760 ++++++++++++++++---------
 nuttx/configs/mcu123-lpc214x/scripts/ld.script |   6 +-
 nuttx/configs/sim/nxlines/Make.defs            | 107 ++++
 nuttx/configs/sim/nxlines/defconfig            | 591 +++++++++++++++++++
 nuttx/configs/sim/nxlines/setenv.sh            |  53 ++
 nuttx/configs/zp214xpa/Kconfig                 |   7 +
 nuttx/configs/zp214xpa/README.txt              | 136 +++++
 nuttx/configs/zp214xpa/include/board.h         |  68 +++
 nuttx/configs/zp214xpa/nsh/Make.defs           | 128 +++++
 nuttx/configs/zp214xpa/nsh/defconfig           | 574 +++++++++++++++++++
 nuttx/configs/zp214xpa/nsh/setenv.sh           |  65 +++
 nuttx/configs/zp214xpa/scripts/ld.script       | 120 ++++
 nuttx/configs/zp214xpa/src/Makefile            |  84 +++
 nuttx/drivers/mmcsd/Kconfig                    |   1 +
 nuttx/drivers/usbhost/usbhost_hidkbd.c         |   6 +-
 23 files changed, 2626 insertions(+), 317 deletions(-)
 delete mode 100644 nuttx/configs/mcu123-lpc214x/nsh/appconfig
 create mode 100644 nuttx/configs/sim/nxlines/Make.defs
 create mode 100644 nuttx/configs/sim/nxlines/defconfig
 create mode 100755 nuttx/configs/sim/nxlines/setenv.sh
 create mode 100644 nuttx/configs/zp214xpa/Kconfig
 create mode 100644 nuttx/configs/zp214xpa/README.txt
 create mode 100644 nuttx/configs/zp214xpa/include/board.h
 create mode 100644 nuttx/configs/zp214xpa/nsh/Make.defs
 create mode 100644 nuttx/configs/zp214xpa/nsh/defconfig
 create mode 100755 nuttx/configs/zp214xpa/nsh/setenv.sh
 create mode 100644 nuttx/configs/zp214xpa/scripts/ld.script
 create mode 100644 nuttx/configs/zp214xpa/src/Makefile

(limited to 'nuttx/arch')

diff --git a/apps/examples/hidkbd/hidkbd_main.c b/apps/examples/hidkbd/hidkbd_main.c
index d7e79b121..abc942a44 100644
--- a/apps/examples/hidkbd/hidkbd_main.c
+++ b/apps/examples/hidkbd/hidkbd_main.c
@@ -177,12 +177,14 @@ static void hidkbd_decode(FAR char *buffer, ssize_t nbytes)
       /* Decode the next thing from the buffer */
 
       ret = kbd_decode((FAR struct lib_instream_s *)&kbdstream, &state, &ch);
-      if (ret == KBD_ERROR)
+      if (ret == KBD_ERROR) /* Error or end-of-file */
         {
+          /* Break out when all of the data has been processed */
+
           break;
         }
 
-      /* Normal data?  Or special key? */
+      /* Normal data?  Or special key?  Press?  Or release? */
 
       switch (ret)
         {
@@ -202,10 +204,7 @@ static void hidkbd_decode(FAR char *buffer, ssize_t nbytes)
           printf("Special Release: %d\n", ch);
           break;
 
-        case KBD_ERROR: /* Error or end-of-file */
-          printf("EOF:             %d\n", ret);
-          break;
-
+        case KBD_ERROR: /* Error or end-of-file, already handled */
         default:
           printf("Unexpected:      %d\n", ret);
           break;
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 2e114af8c..dcabb6c07 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3836,4 +3836,10 @@
 	  events too.  However, the USB HID keyboard drier has not yet been
 	  updated to detect key release events.  That is kind of tricky in
 	  the USB HID keyboard report data.
+	* configs/mcu123-214x/nsh:  Converted to use the kconfig-frontends
+	  configuration tool.
+	* configs/zp214xpa:  Add basic support for the The0.net ZP213x/4xPA
+	  board (with the LPC2148 and the UG_2864AMBAG01).
+	* configs/sim/nxlines:  Add an nxlines configuration for the
+	  simulator.
 
diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html
index 84f298d3a..dc454c0b6 100644
--- a/nuttx/Documentation/NuttX.html
+++ b/nuttx/Documentation/NuttX.html
@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: December 20, 2012</p>
+      <p>Last Updated: December 28, 2012</p>
     </td>
   </tr>
 </table>
@@ -1505,7 +1505,8 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code
     <p>
       <b>NXP LPC214x</b>.
       Support is provided for the NXP LPC214x family of processors.  In particular,
-      support is provided for the mcu123.com lpc214x evaluation board (LPC2148).
+      support is provided for (1) the mcu123.com lpc214x evaluation board (LPC2148)
+      and (1) the The0.net ZPA213X/4XPA development board (with the The0.net UG-2864AMBAG01 OLED)
       This port also used the GNU arm-nuttx-elf toolchain* under Linux or Cygwin.
     </p>
     <ul>
diff --git a/nuttx/arch/arm/src/lpc214x/Kconfig b/nuttx/arch/arm/src/lpc214x/Kconfig
index a26483ed9..5d52eb000 100644
--- a/nuttx/arch/arm/src/lpc214x/Kconfig
+++ b/nuttx/arch/arm/src/lpc214x/Kconfig
@@ -4,3 +4,137 @@
 #
 
 comment "LPC214x Configuration Options"
+
+# Fragments of LPC214x chip selection logic.  The LPC2148 is the only chip
+# supported for now.
+
+config ARCH_CHIP_LPC2148
+	bool
+	default y
+
+comment "LPC214x Initialization Options"
+
+choice
+	prompt "Memory Execution Mode"
+	default DEFAULT_MODE
+
+config EXTMEM_MODE
+	bool "External Memory Mode"
+	---help---
+		Code executes from external memory starting at address 0x8000:0000.
+
+config RAM_MODE
+	bool "RAM Memory Mode"
+	---help---
+		Code executes from on-chip RAM at address 0x4000:0000.
+
+config DEFAULT_MODE
+	bool "Default Memory Mode"
+	---help---
+		Executes from 0x0000:0000.  In non-default modes, the MEMAP register
+		is set override the settings of the CPU configuration pins.
+
+endchoice
+
+config CODE_BASE
+	hex "Execuation Base Address"
+	default 0x00000000
+	---help---
+		This must match the expected address for the selected "Memory
+		Execution Address":
+
+		EXTMEM_MODE:  0x8000:0000
+		RAM_MODE:     0x4000:0000
+		DEFAULT)MODE: 0x0000:0000
+
+config PLL_SETUP
+	bool "Configure the PLL"
+	default y
+
+config MAM_SETUP
+	bool "Configure the Memory Accelerator Module (MAM)"
+	default y
+
+config APBDIV_SETUP
+	bool "Configure the APB Divider"
+	default y
+
+config APBDIV_VALUE
+	int "APB Divisor"
+	default 1
+
+config EMC_SETUP
+	bool "Configure EMC"
+	default n
+
+config BCFG0_SETUP
+	bool "Configure BCFG0"
+	default n
+
+config BCFG1_SETUP
+	bool "Configure BCFG1"
+	default n
+
+config BCFG2_SETUP
+	bool "Configure BCFG2"
+	default n
+
+config BCFG3_SETUP
+	bool "Configure BCFG3"
+	default n
+
+config ADC_SETUP
+	bool "Configure ADC"
+	default y
+
+menu "LPC214x Peripheral Support"
+
+config LPC214X_UART0
+	bool
+	default y
+	select ARCH_HAVE_UART0
+
+config LPC214X_UART1
+	bool
+	default y
+	select ARCH_HAVE_UART1
+
+config LPC214X_USBDEV
+	bool "USB Device"
+	default y
+	depends on USBDEV
+
+endmenu
+
+config LPC214x_FIO
+	bool "Fast GPIO"
+	default n
+
+if LPC214X_USBDEV
+menu "LPC214x USB Device Configuration"
+
+config LPC214X_USBDEV_DMA
+	bool "USB Device DMA Support"
+	default n
+
+config CONFIG_LPC214X_USBDEV_NDMADESCRIPTORS
+	int "Number of USB DMA Descriptors"
+	default 8
+	depends on LPC214X_USBDEV_DMA
+
+config LPC214X_USBDEV_EPFAST_INTERRUPT
+	bool "USB Device Fast Endpoint Interrupts"
+	default n
+
+config LPC214X_USBDEV_FRAME_INTERRUPT
+	bool "USB Device Frame Interrupts"
+	default n
+
+config LPC214X_USBDEV_REGDEBUG
+	bool "USB Device Register-Level Debug Output"
+	default n
+	depends on DEBUG
+
+endmenu
+endif
+
diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig
index bba1444c4..cda5aa7bc 100644
--- a/nuttx/configs/Kconfig
+++ b/nuttx/configs/Kconfig
@@ -619,6 +619,14 @@ config ARCH_BOARD_Z8F64200100KIT
 		development kit, Z8F6423 part, and the Zilog ZDS-II Windows command line
 		tools.  The development environment is Cygwin under WinXP.
 
+config ARCH_BOARD_ZP214XPA
+	bool "The0.net LPC2148 Development Board"
+	depends on ARCH_CHIP_LPC2148
+	---help---
+		This port is for the NXP LPC2148 as provided on the The0.net
+		ZPA213X/4XPA development board. Includes support for the
+		UG-2864AMBAG01 OLED also from The0.net
+
 config ARCH_BOARD_SIM
 	bool "User mode simulation"
 	depends on ARCH_SIM
@@ -700,6 +708,7 @@ config ARCH_BOARD
 	default "z80sim"              if ARCH_BOARD_Z80SIM
 	default "z8encore000zco"      if ARCH_BOARD_Z8ENCORE000ZCO
 	default "z8f64200100kit"      if ARCH_BOARD_Z8F64200100KIT
+	default "zp214xpa"            if ARCH_BOARD_ZP214XPA
 	default "sim"                 if ARCH_BOARD_SIM
 	default ""                    if ARCH_BOARD_CUSTOM
 
@@ -709,7 +718,7 @@ config ARCH_HAVE_LEDS
 	bool
 
 config ARCH_LEDS
-	bool "Board LEDs support"
+	bool "Board LED support"
 	default y
 	depends on ARCH_HAVE_LEDS
 	---help---
@@ -935,6 +944,9 @@ endif
 if ARCH_BOARD_Z8F64200100KIT
 source "configs/z8f64200100kit/Kconfig"
 endif
+if ARCH_BOARD_ZP214XPA
+source "configs/zp214xpa/Kconfig"
+endif
 if ARCH_BOARD_SIM
 source "configs/sim/Kconfig"
 endif
diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt
index 21aace2af..4e9bcca14 100644
--- a/nuttx/configs/README.txt
+++ b/nuttx/configs/README.txt
@@ -1936,6 +1936,11 @@ configs/z8f64200100kit
   development kit, Z8F6423 part, and the Zilog ZDS-II Windows command line
   tools.  The development environment is Cygwin under WinXP.
 
+configs/zp214xpa
+  This port is for the NXP LPC2148 as provided on the The0.net
+  ZPA213X/4XPA development board. Includes support for the
+  UG-2864AMBAG01 OLED also from The0.net
+
 Configuring NuttX
 ^^^^^^^^^^^^^^^^^
 
diff --git a/nuttx/configs/mcu123-lpc214x/README.txt b/nuttx/configs/mcu123-lpc214x/README.txt
index 435f8647d..4c7c608b7 100644
--- a/nuttx/configs/mcu123-lpc214x/README.txt
+++ b/nuttx/configs/mcu123-lpc214x/README.txt
@@ -349,8 +349,22 @@ nsh:
   Configures the NuttShell (nsh) located at examples/nsh.  The
   Configuration enables only the serial NSH interfaces.
 
-  Default toolchain:  Buildroot
-  Output format:  ELF and binary
+    NOTES:
+ 
+    1. This configuration uses the mconf-based configuration tool.  To
+       change this configuration using that tool, you should:
+
+       a. Build and install the mconf tool.  See nuttx/README.txt and
+          misc/tools/
+
+       b. Execute 'make menuconfig' in nuttx/ in order to start the
+          reconfiguration process.
+
+    2. Default platform/toolchain:
+
+       CONFIG_HOST_LINUX=y             : Windows
+       CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc)
+       CONFIG_RAW_BINARY=y             : Output formats: ELF and raw binary
 
 ostest:
 -------
diff --git a/nuttx/configs/mcu123-lpc214x/nsh/appconfig b/nuttx/configs/mcu123-lpc214x/nsh/appconfig
deleted file mode 100644
index f8e2d5165..000000000
--- a/nuttx/configs/mcu123-lpc214x/nsh/appconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-############################################################################
-# configs/mcu123-lpc214x/nsh/appconfig
-#
-#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-# Path to example in apps/examples containing the user_start entry point
-
-CONFIGURED_APPS += examples/nsh
-
-# The NSH library
-
-CONFIGURED_APPS += system/readline
-CONFIGURED_APPS += nshlib
-
diff --git a/nuttx/configs/mcu123-lpc214x/nsh/defconfig b/nuttx/configs/mcu123-lpc214x/nsh/defconfig
index a8a53a340..6ae163386 100644
--- a/nuttx/configs/mcu123-lpc214x/nsh/defconfig
+++ b/nuttx/configs/mcu123-lpc214x/nsh/defconfig
@@ -1,169 +1,207 @@
-############################################################################
-# configs/mcu123-lpc214x/nsh/defconfig
-#
-#   Copyright (C) 2008-2010, 2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-#
-# Architecture selection
 #
-CONFIG_ARCH="arm"
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+CONFIG_NUTTX_NEWCONFIG=y
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+# CONFIG_APPS_DIR="../apps"
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_SYMBOLS is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_8051 is not set
 CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_IMX is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+# CONFIG_ARCH_CHIP_LM3S is not set
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+CONFIG_ARCH_CHIP_LPC214X=y
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_SAM3U is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_ARM7TDMI=y
+CONFIG_ARCH_FAMILY="arm"
 CONFIG_ARCH_CHIP="lpc214x"
-CONFIG_ARCH_CHIP_LPC2148=y
-CONFIG_ARCH_BOARD="mcu123-lpc214x"
-CONFIG_ARCH_BOARD_MCU123=y
+CONFIG_ARCH_HAVE_LOWVECTORS=y
+# CONFIG_ARCH_LOWVECTORS is not set
 CONFIG_BOARD_LOOPSPERMSEC=3270
-CONFIG_ARCH_LEDS=y
-CONFIG_DRAM_SIZE=32768
-CONFIG_DRAM_START=0x40000000
-CONFIG_ARCH_INTERRUPTSTACK=0
-CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ARCH_CALIBRATION is not set
 
 #
-# LPC2148 specific chip initialization
+# ARM Configuration Options
+#
+# CONFIG_ARM_TOOLCHAIN_BUILDROOT is not set
+# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set
+CONFIG_ARM_TOOLCHAIN_GNU_EABI=y
+
+#
+# LPC214x Configuration Options
+#
+CONFIG_ARCH_CHIP_LPC2148=y
+
 #
-CONFIG_EXTMEM_MODE=n
-CONFIG_RAM_MODE=n
+# LPC214x Initialization Options
+#
+# CONFIG_EXTMEM_MODE is not set
+# CONFIG_RAM_MODE is not set
+CONFIG_DEFAULT_MODE=y
 CONFIG_CODE_BASE=0x00000000
 CONFIG_PLL_SETUP=y
 CONFIG_MAM_SETUP=y
 CONFIG_APBDIV_SETUP=y
-CONFIG_EMC_SETUP=n
-CONFIG_BCFG0_SETUP=n
-CONFIG_BCFG1_SETUP=n
-CONFIG_BCFG2_SETUP=n
-CONFIG_BCFG3_SETUP=n
+CONFIG_APBDIV_VALUE=1
+# CONFIG_EMC_SETUP is not set
+# CONFIG_BCFG0_SETUP is not set
+# CONFIG_BCFG1_SETUP is not set
+# CONFIG_BCFG2_SETUP is not set
+# CONFIG_BCFG3_SETUP is not set
 CONFIG_ADC_SETUP=y
 
 #
-# LPC214X specific device driver settings
+# LPC214x Peripheral Support
 #
-CONFIG_UART0_SERIAL_CONSOLE=y
-CONFIG_UART1_SERIAL_CONSOLE=n
-CONFIG_UART0_TXBUFSIZE=256
-CONFIG_UART1_TXBUFSIZE=256
-CONFIG_UART0_RXBUFSIZE=256
-CONFIG_UART1_RXBUFSIZE=256
-CONFIG_UART0_BAUD=38400
-CONFIG_UART1_BAUD=38400
-CONFIG_UART0_BITS=8
-CONFIG_UART1_BITS=8
-CONFIG_UART0_PARITY=0
-CONFIG_UART1_PARITY=0
-CONFIG_UART0_2STOP=0
-CONFIG_UART1_2STOP=0
+CONFIG_LPC214X_UART0=y
+CONFIG_LPC214X_UART1=y
+# CONFIG_LPC214x_FIO is not set
+# CONFIG_SDIO_DMA is not set
+# CONFIG_SDIO_WIDTH_D1_ONLY is not set
 
 #
-# General build options
+# Architecture Options
 #
-CONFIG_RRLOAD_BINARY=n
-CONFIG_INTELHEX_BINARY=n
-CONFIG_MOTOROLA_SREC=n
-CONFIG_RAW_BINARY=y
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_DMA is not set
+# CONFIG_ARCH_IRQPRIO is not set
+# CONFIG_CUSTOM_STACK is not set
+# CONFIG_ADDRENV is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
 
 #
-# General OS setup
+# Board Settings
 #
-CONFIG_USER_ENTRYPOINT="nsh_main"
-CONFIG_DEBUG=n
-CONFIG_DEBUG_VERBOSE=n
-CONFIG_DEBUG_SYMBOLS=n
-CONFIG_MM_REGIONS=1
-CONFIG_ARCH_LOWPUTC=y
+CONFIG_DRAM_START=0x40000000
+CONFIG_DRAM_SIZE=32768
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Board Selection
+#
+CONFIG_ARCH_BOARD_MCU123=y
+# CONFIG_ARCH_BOARD_ZP214XPA is not set
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="mcu123-lpc214x"
+
+#
+# Common Board Options
+#
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_NSH_MMCSDMINOR=0
+CONFIG_NSH_MMCSDSLOTNO=0
+CONFIG_NSH_MMCSDSPIPORTNO=1
+
+#
+# Board-Specific Options
+#
+
+#
+# RTOS Features
+#
+CONFIG_MSEC_PER_TICK=10
 CONFIG_RR_INTERVAL=0
-CONFIG_SCHED_INSTRUMENTATION=n
+# CONFIG_SCHED_INSTRUMENTATION is not set
 CONFIG_TASK_NAME_SIZE=0
+# CONFIG_JULIAN_TIME is not set
 CONFIG_START_YEAR=2008
 CONFIG_START_MONTH=10
 CONFIG_START_DAY=1
-CONFIG_JULIAN_TIME=n
 CONFIG_DEV_CONSOLE=y
-CONFIG_DEV_LOWCONSOLE=n
-CONFIG_MUTEX_TYPES=n
-CONFIG_PRIORITY_INHERITANCE=n
-CONFIG_SEM_PREALLOCHOLDERS=0
-CONFIG_SEM_NNESTPRIO=0
-CONFIG_FDCLONE_DISABLE=n
-CONFIG_FDCLONE_STDIO=n
+# CONFIG_MUTEX_TYPES is not set
+# CONFIG_PRIORITY_INHERITANCE is not set
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_NXFLAT=n
-
-#
-# The following can be used to disable categories of
-# APIs supported by the OS.  If the compiler supports
-# weak functions, then it should not be necessary to
-# disable functions unless you want to restrict usage
-# of those APIs.
-#
-# There are certain dependency relationships in these
-# features.
-#
-# o mq_notify logic depends on signals to awaken tasks
-#   waiting for queues to become full or empty.
-# o pthread_condtimedwait() depends on signals to wake
-#   up waiting tasks.
-#
-CONFIG_DISABLE_CLOCK=n
-CONFIG_DISABLE_POSIX_TIMERS=n
-CONFIG_DISABLE_PTHREAD=n
-CONFIG_DISABLE_SIGNALS=n
-CONFIG_DISABLE_MQUEUE=n
-CONFIG_DISABLE_MOUNTPOINT=n
-CONFIG_DISABLE_ENVIRON=n
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_WAITPID is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_CLOCK is not set
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_DISABLE_ENVIRON is not set
 CONFIG_DISABLE_POLL=y
 
-#
-# Misc libc settings
-#
-CONFIG_NOPRINTF_FIELDWIDTH=n
-
-#
-# Allow for architecture optimized implementations
-#
-# The architecture can provide optimized versions of the
-# following to improve system performance
-#
-CONFIG_ARCH_MEMCPY=n
-CONFIG_ARCH_MEMCMP=n
-CONFIG_ARCH_MEMMOVE=n
-CONFIG_ARCH_MEMSET=n
-CONFIG_ARCH_STRCMP=n
-CONFIG_ARCH_STRCPY=n
-CONFIG_ARCH_STRNCPY=n
-CONFIG_ARCH_STRLEN=n
-CONFIG_ARCH_STRNLEN=n
-CONFIG_ARCH_BZERO=n
-
 #
 # Sizes of configurable things (0 disables)
 #
@@ -173,8 +211,6 @@ CONFIG_NPTHREAD_KEYS=4
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NAME_MAX=32
-CONFIG_STDIO_BUFFER_SIZE=256
-CONFIG_NUNGET_CHARS=2
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_MQ_MAXMSGSIZE=32
 CONFIG_MAX_WDOGPARMS=2
@@ -182,168 +218,380 @@ CONFIG_PREALLOC_WDOGS=4
 CONFIG_PREALLOC_TIMERS=4
 
 #
-# Filesystem configuration
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+
+#
+# Device Drivers
+#
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_LOOP is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_PWM is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_OWNBUS is not set
+# CONFIG_SPI_EXCHANGE is not set
+# CONFIG_SPI_CMDDATA is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_LCD is not set
+CONFIG_MMCSD=y
+CONFIG_MMCSD_NSLOTS=1
+# CONFIG_MMCSD_READONLY is not set
+# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set
+CONFIG_MMCSD_MMCSUPPORT=y
+CONFIG_MMCSD_HAVECARDDETECT=y
+CONFIG_MMCSD_SPI=y
+CONFIG_MMCSD_SPICLOCK=20000000
+# CONFIG_MMCSD_SDIO is not set
+# CONFIG_SDIO_MUXBUS is not set
+# CONFIG_MTD is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+CONFIG_ARCH_HAVE_UART0=y
+CONFIG_ARCH_HAVE_UART1=y
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_UART1_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# UART0 Configuration
+#
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART0_BAUD=38400
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+
+#
+# UART1 Configuration
+#
+CONFIG_UART1_RXBUFSIZE=256
+CONFIG_UART1_TXBUFSIZE=256
+CONFIG_UART1_BAUD=38400
+CONFIG_UART1_BITS=8
+CONFIG_UART1_PARITY=0
+CONFIG_UART1_2STOP=0
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+
+#
+# Networking Support
+#
+# CONFIG_NET is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
 #
 CONFIG_FS_FAT=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FAT_MAXFNAME=32
-CONFIG_FS_NXFFS=n
-CONFIG_FS_ROMFS=n
+# CONFIG_FS_FATTIME is not set
+# CONFIG_FAT_DMAMEMORY is not set
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
 
 #
-# Maintain legacy build behavior (revisit)
+# System Logging
 #
+# CONFIG_SYSLOG is not set
 
-CONFIG_MMCSD=y
-CONFIG_MMCSD_SPI=y
-CONFIG_MMCSD_SDIO=y
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
 
 #
-# SPI-based MMC/SD driver
+# Memory Management
 #
-CONFIG_MMCSD_NSLOTS=1
-CONFIG_MMCSD_READONLY=n
-#CONFIG_MMCSD_SPICLOCK=20000000
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_GRAN is not set
 
 #
-# SPI-based MMC/SD driver
+# Binary Formats
 #
-CONFIG_MMCSD_NSLOTS=1
-CONFIG_MMCSD_READONLY=n
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
 
 #
-# TCP/IP and UDP support via uIP
+# Library Routines
 #
-CONFIG_NET=n
-CONFIG_NET_IPv6=n
-CONFIG_NSOCKET_DESCRIPTORS=0
-CONFIG_NET_SOCKOPTS=y
-CONFIG_NET_BUFSIZE=420
-CONFIG_NET_TCP=n
-CONFIG_NET_TCP_CONNS=40
-CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_UDP=n
-CONFIG_NET_UDP_CHECKSUMS=y
-#CONFIG_NET_UDP_CONNS=10
-CONFIG_NET_ICMP=n
-CONFIG_NET_ICMP_PING=n
-#CONFIG_NET_PINGADDRCONF=0
-CONFIG_NET_STATISTICS=y
-#CONFIG_NET_RECEIVE_WINDOW=
-#CONFIG_NET_ARPTAB_SIZE=8
-CONFIG_NET_BROADCAST=n
 
 #
-# UIP Network Utilities
+# Standard C Library Options
 #
-CONFIG_NET_DHCP_LIGHT=n
-CONFIG_NET_RESOLV_ENTRIES=4
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
 
 #
-# USB Device Configuration
+# Non-standard Helper Functions
 #
-CONFIG_USBDEV=n
-CONFIG_USBDEV_ISOCHRONOUS=n
-CONFIG_USBDEV_DUALSPEED=n
-CONFIG_USBDEV_SELFPOWERED=y
-CONFIG_USBDEV_REMOTEWAKEUP=n
-CONFIG_USBDEV_MAXPOWER=100
-CONFIG_USBDEV_TRACE=n
-CONFIG_USBDEV_TRACE_NRECORDS=128
+CONFIG_LIB_KBDCODEC=y
 
 #
-# LPC214X USB Configuration
+# Basic CXX Support
 #
-CONFIG_LPC214X_USBDEV_FRAME_INTERRUPT=n
-CONFIG_LPC214X_USBDEV_EPFAST_INTERRUPT=n
-CONFIG_LPC214X_USBDEV_DMA=n
-CONFIG_LPC214X_USBDEV_NDMADESCRIPTORS=0
-CONFIG_LPC214X_USBDEV_DMAINTMASK=0
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
 
 #
-# USB Serial Device Configuration
+# Application Configuration
 #
-CONFIG_PL2303=n
-CONFIG_PL2303_EPINTIN=1
-CONFIG_PL2303_EPBULKOUT=2
-CONFIG_PL2303_EPBULKIN=5
-CONFIG_PL2303_NWRREQS=4
-CONFIG_PL2303_NRDREQS=4
-CONFIG_PL2303_VENDORID=0x067b
-CONFIG_PL2303_PRODUCTID=0x2303
-CONFIG_PL2303_VENDORSTR="Nuttx"
-CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
-CONFIG_PL2303_RXBUFSIZE=512
-CONFIG_PL2303_TXBUFSIZE=512
 
 #
-# USB Storage Device Configuration
+# Built-In Applications
+#
+# CONFIG_BUILTIN is not set
+
 #
-CONFIG_USBMSC=n
-CONFIG_USBMSC_EP0MAXPACKET=64
-CONFIG_USBMSC_EPBULKOUT=2
-CONFIG_USBMSC_EPBULKIN=5
-CONFIG_USBMSC_NRDREQS=2
-CONFIG_USBMSC_NWRREQS=2
-CONFIG_USBMSC_BULKINREQLEN=256
-CONFIG_USBMSC_BULKOUTREQLEN=256
-CONFIG_USBMSC_VENDORID=0x584e
-CONFIG_USBMSC_VENDORSTR="NuttX"
-CONFIG_USBMSC_PRODUCTID=0x5342
-CONFIG_USBMSC_PRODUCTSTR="USBdev Storage"
-CONFIG_USBMSC_VERSIONNO=0x0399
-CONFIG_USBMSC_REMOVABLE=y
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CDCACM is not set
+# CONFIG_EXAMPLES_COMPOSITE is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_LCDRW is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_NETTEST is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXCONSOLE is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXFLAT is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PASHELLO is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_QENCODER is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UDP is not set
+# CONFIG_EXAMPLES_UIP is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBMSC is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+# CONFIG_EXAMPLES_WLAN is not set
 
 #
-# Settings for examples/ostest
-CONFIG_EXAMPLES_OSTEST_LOOPS=1
-CONFIG_EXAMPLES_OSTEST_STACKSIZE=4096
-CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3
+# Interpreters
+#
 
 #
-# Settings for apps/nshlib
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+
 #
+# Network Utilities
+#
+
+#
+# Networking Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_DHCPC is not set
+# CONFIG_NETUTILS_DHCPD is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_FTPD is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_RESOLV is not set
+# CONFIG_NETUTILS_SMTP is not set
+# CONFIG_NETUTILS_TELNETD is not set
+# CONFIG_NETUTILS_TFTPC is not set
+# CONFIG_NETUTILS_THTTPD is not set
+# CONFIG_NETUTILS_UIPLIB is not set
+# CONFIG_NETUTILS_WEBCLIENT is not set
+
+#
+# ModBus
+#
+
+#
+# FreeModbus
+#
+# CONFIG_MODBUS is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFATFS is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_NSFMOUNT is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PING is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+CONFIG_NSH_CODECS_BUFSIZE=128
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_STRERROR=n
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_NESTDEPTH=3
-CONFIG_NSH_DISABLESCRIPT=n
-CONFIG_NSH_DISABLEBG=n
-CONFIG_NSH_ROMFSETC=n
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLEBG is not set
 CONFIG_NSH_CONSOLE=y
-CONFIG_NSH_TELNET=n
+# CONFIG_NSH_CONDEV is not set
 CONFIG_NSH_ARCHINIT=y
-CONFIG_NSH_IOBUFFER_SIZE=512
-CONFIG_NSH_DHCPC=n
-CONFIG_NSH_NOMAC=n
-CONFIG_NSH_IPADDR=0x0a000002
-CONFIG_NSH_DRIPADDR=0x0a000001
-CONFIG_NSH_NETMASK=0xffffff00
-CONFIG_NSH_ROMFSMOUNTPT="/etc"
-CONFIG_NSH_INITSCRIPT="init.d/rcS"
-CONFIG_NSH_ROMFSDEVNO=0
-CONFIG_NSH_ROMFSSECTSIZE=64
-CONFIG_NSH_FATDEVNO=1
-CONFIG_NSH_FATSECTSIZE=512
-CONFIG_NSH_FATNSECTORS=1024
-CONFIG_NSH_FATMOUNTPT="/tmp"
-
-#
-# Architecture-specific NSH options
-CONFIG_NSH_MMCSDSPIPORTNO=1
-CONFIG_NSH_MMCSDSLOTNO=0
-CONFIG_NSH_MMCSDMINOR=0
 
 #
-# Stack and heap information
+# NxWidgets/NxWM
 #
-CONFIG_BOOT_RUNFROMFLASH=n
-CONFIG_BOOT_COPYTORAM=n
-CONFIG_CUSTOM_STACK=n
-CONFIG_IDLETHREAD_STACKSIZE=2048
-CONFIG_USERMAIN_STACKSIZE=2048
-CONFIG_PTHREAD_STACK_MIN=256
-CONFIG_PTHREAD_STACK_DEFAULT=2048
-CONFIG_HEAP_BASE=
-CONFIG_HEAP_SIZE=
+
+#
+# System NSH Add-Ons
+#
+
+#
+# Custom Free Memory Command
+#
+# CONFIG_SYSTEM_FREE is not set
+
+#
+# I2C tool
+#
+
+#
+# FLASH Program Installation
+#
+# CONFIG_SYSTEM_INSTALL is not set
+
+#
+# readline()
+#
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+
+#
+# Power Off
+#
+# CONFIG_SYSTEM_POWEROFF is not set
+
+#
+# RAMTRON
+#
+# CONFIG_SYSTEM_RAMTRON is not set
+
+#
+# SD Card
+#
+# CONFIG_SYSTEM_SDCARD is not set
+
+#
+# Sysinfo
+#
+# CONFIG_SYSTEM_SYSINFO is not set
diff --git a/nuttx/configs/mcu123-lpc214x/scripts/ld.script b/nuttx/configs/mcu123-lpc214x/scripts/ld.script
index 8ce83748f..bc025dfb7 100644
--- a/nuttx/configs/mcu123-lpc214x/scripts/ld.script
+++ b/nuttx/configs/mcu123-lpc214x/scripts/ld.script
@@ -35,12 +35,12 @@
 
 /* FLASH:
  *   The lpc2148 has 512Kb of non-volatile memory beginning at address
- *   0x00000000.  The OS entry point is via the reset vector at address
- *   0x00000000 (default MEMMAP mode assumed)
+ *   0x0000:0000.  The OS entry point is via the reset vector at address
+ *   0x0000:0000 (default MEMMAP mode assumed)
  *
  * SRAM:
  *   The lpc2148 has 32Kb of on-chip static RAM beginning at address
- *   0x40000000.  The .data section will be relocated from _eronly
+ *   0x4000:0000.  The .data section will be relocated from _eronly
  *   to _sdata at boot time.
  */
 
diff --git a/nuttx/configs/sim/nxlines/Make.defs b/nuttx/configs/sim/nxlines/Make.defs
new file mode 100644
index 000000000..18c8bf537
--- /dev/null
+++ b/nuttx/configs/sim/nxlines/Make.defs
@@ -0,0 +1,107 @@
+############################################################################
+# configs/sim/nxlines/Make.defs
+#
+#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+
+HOSTOS = ${shell uname -o 2>/dev/null || echo "Other"}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+else
+  ARCHOPTIMIZATION = -O2
+endif
+
+ARCHCPUFLAGS = -fno-builtin
+ARCHCPUFLAGSXX = -fno-builtin -fno-exceptions -fno-rtti
+ARCHPICFLAGS = -fpic
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
+ARCHWARNINGSXX = -Wall -Wshadow
+ARCHDEFINES =
+ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ARCHINCLUDESXX = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ARCHSCRIPT =
+
+ifeq ($(CONFIG_SIM_M32),y)
+  ARCHCPUFLAGS += -m32
+  ARCHCPUFLAGSXX += -m32
+endif
+
+CROSSDEV =
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXFLAGS = $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGSXX) $(ARCHINCLUDESXX) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+OBJEXT = .o
+LIBEXT = .a
+
+ifeq ($(HOSTOS),Cygwin)
+  EXEEXT = .exe
+else
+  EXEEXT =
+endif
+
+LDLINKFLAGS = $(ARCHSCRIPT) # Link flags used with $(LD)
+CCLINKFLAGS = $(ARCHSCRIPT) # Link flags used with $(CC)
+LDFLAGS = $(ARCHSCRIPT) # For backward compatibility, same as CCLINKFLAGS
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDLINKFLAGS += -g
+  CCLINKFLAGS += -g
+  LDFLAGS += -g
+endif
+
+ifeq ($(CONFIG_SIM_M32),y)
+  LDLINKFLAGS += -melf_i386
+  CCLINKFLAGS += -m32
+  LDFLAGS += -m32
+endif
+
+MKDEP = $(TOPDIR)/tools/mkdeps.sh
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+HOSTLDFLAGS =
diff --git a/nuttx/configs/sim/nxlines/defconfig b/nuttx/configs/sim/nxlines/defconfig
new file mode 100644
index 000000000..c023af674
--- /dev/null
+++ b/nuttx/configs/sim/nxlines/defconfig
@@ -0,0 +1,591 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+CONFIG_NUTTX_NEWCONFIG=y
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+# CONFIG_HOST_LINUX is not set
+# CONFIG_HOST_OSX is not set
+CONFIG_HOST_WINDOWS=y
+# CONFIG_HOST_OTHER is not set
+# CONFIG_WINDOWS_NATIVE is not set
+CONFIG_WINDOWS_CYGWIN=y
+# CONFIG_WINDOWS_MSYS is not set
+# CONFIG_WINDOWS_OTHER is not set
+
+#
+# Build Configuration
+#
+CONFIG_APPS_DIR="../apps"
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+# CONFIG_RAW_BINARY is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+CONFIG_DEBUG_SYMBOLS=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_8051 is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+CONFIG_ARCH_SIM=y
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="sim"
+CONFIG_BOARD_LOOPSPERMSEC=
+
+#
+# Simulation Configuration Options
+#
+# CONFIG_SIM_M32 is not set
+# CONFIG_SIM_WALLTIME is not set
+CONFIG_SIM_FRAMEBUFFER=y
+CONFIG_SIM_X11FB=y
+# CONFIG_SIM_X11NOSHM is not set
+CONFIG_SIM_FBHEIGHT=240
+CONFIG_SIM_FBWIDTH=480
+CONFIG_SIM_FBBPP=32
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_DMA is not set
+# CONFIG_ARCH_IRQPRIO is not set
+# CONFIG_CUSTOM_STACK is not set
+# CONFIG_ADDRENV is not set
+# CONFIG_ARCH_STACKDUMP is not set
+# CONFIG_ENDIAN_BIG is not set
+
+#
+# Board Settings
+#
+CONFIG_DRAM_START=
+CONFIG_DRAM_SIZE=
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Board Selection
+#
+CONFIG_ARCH_BOARD_SIM=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="sim"
+
+#
+# Common Board Options
+#
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Board-Specific Options
+#
+
+#
+# RTOS Features
+#
+CONFIG_MSEC_PER_TICK=10
+CONFIG_RR_INTERVAL=0
+# CONFIG_SCHED_INSTRUMENTATION is not set
+CONFIG_TASK_NAME_SIZE=32
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2012
+CONFIG_START_MONTH=5
+CONFIG_START_DAY=1
+CONFIG_DEV_CONSOLE=y
+# CONFIG_MUTEX_TYPES is not set
+# CONFIG_PRIORITY_INHERITANCE is not set
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+# CONFIG_SCHED_WORKQUEUE is not set
+CONFIG_SCHED_WAITPID=y
+# CONFIG_SCHED_ATEXIT is not set
+CONFIG_SCHED_ONEXIT=y
+CONFIG_SCHED_ONEXIT_MAX=1
+CONFIG_USER_ENTRYPOINT="nxlines_main"
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_CLOCK is not set
+CONFIG_DISABLE_POSIX_TIMERS=y
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_DISABLE_ENVIRON is not set
+CONFIG_DISABLE_POLL=y
+
+#
+# Sizes of configurable things (0 disables)
+#
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_TASK_ARGS=4
+CONFIG_NPTHREAD_KEYS=4
+CONFIG_NFILE_DESCRIPTORS=16
+CONFIG_NFILE_STREAMS=16
+CONFIG_NAME_MAX=32
+CONFIG_PREALLOC_MQ_MSGS=32
+CONFIG_MQ_MAXMSGSIZE=48
+CONFIG_MAX_WDOGPARMS=4
+CONFIG_PREALLOC_WDOGS=32
+CONFIG_PREALLOC_TIMERS=8
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=8192
+CONFIG_USERMAIN_STACKSIZE=16384
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=8192
+
+#
+# Device Drivers
+#
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_LOOP is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_PWM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_LCD is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MTD is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+# CONFIG_STANDARD_SERIAL is not set
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+
+#
+# Networking Support
+#
+# CONFIG_NET is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+CONFIG_FS_FAT=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FAT_LFN=y
+CONFIG_FAT_MAXFNAME=32
+# CONFIG_FS_FATTIME is not set
+# CONFIG_FAT_DMAMEMORY is not set
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_NXFFS is not set
+CONFIG_FS_ROMFS=y
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+
+#
+# Graphics Support
+#
+CONFIG_NX=y
+CONFIG_NX_NPLANES=1
+# CONFIG_NX_WRITEONLY is not set
+
+#
+# Supported Pixel Depths
+#
+CONFIG_NX_DISABLE_1BPP=y
+CONFIG_NX_DISABLE_2BPP=y
+CONFIG_NX_DISABLE_4BPP=y
+CONFIG_NX_DISABLE_8BPP=y
+CONFIG_NX_DISABLE_16BPP=y
+CONFIG_NX_DISABLE_24BPP=y
+# CONFIG_NX_DISABLE_32BPP is not set
+# CONFIG_NX_PACKEDMSFIRST is not set
+
+#
+# Input Devices
+#
+CONFIG_NX_MOUSE=y
+CONFIG_NX_KBD=y
+
+#
+# Framed Window Borders
+#
+CONFIG_NXTK_BORDERWIDTH=4
+CONFIG_NXTK_BORDERCOLOR1=0x005a96bd
+CONFIG_NXTK_BORDERCOLOR2=0x00233a49
+CONFIG_NXTK_BORDERCOLOR3=0x00f8f8f8
+# CONFIG_NXTK_AUTORAISE is not set
+
+#
+# Font Selections
+#
+CONFIG_NXFONTS_CHARBITS=7
+# CONFIG_NXFONT_SANS17X22 is not set
+# CONFIG_NXFONT_SANS20X26 is not set
+CONFIG_NXFONT_SANS23X27=y
+# CONFIG_NXFONT_SANS22X29 is not set
+# CONFIG_NXFONT_SANS28X37 is not set
+# CONFIG_NXFONT_SANS39X48 is not set
+# CONFIG_NXFONT_SANS17X23B is not set
+# CONFIG_NXFONT_SANS20X27B is not set
+# CONFIG_NXFONT_SANS22X29B is not set
+CONFIG_NXFONT_SANS28X37B=y
+# CONFIG_NXFONT_SANS40X49B is not set
+# CONFIG_NXFONT_SERIF22X29 is not set
+# CONFIG_NXFONT_SERIF29X37 is not set
+# CONFIG_NXFONT_SERIF38X48 is not set
+# CONFIG_NXFONT_SERIF22X28B is not set
+# CONFIG_NXFONT_SERIF27X38B is not set
+# CONFIG_NXFONT_SERIF38X49B is not set
+# CONFIG_NXCONSOLE is not set
+
+#
+# NX Multi-user only options
+#
+# CONFIG_NX_MULTIUSER is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_GRAN is not set
+
+#
+# Binary Formats
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+
+#
+# Non-standard Helper Functions
+#
+CONFIG_LIB_KBDCODEC=y
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+CONFIG_HAVE_CXX=y
+# CONFIG_HAVE_CXXINITIALIZE is not set
+# CONFIG_CXX_NEWLONG is not set
+
+#
+# uClibc++ Standard C++ Library
+#
+# CONFIG_UCLIBCXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# Built-In Applications
+#
+# CONFIG_BUILTIN is not set
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CDCACM is not set
+# CONFIG_EXAMPLES_COMPOSITE is not set
+# CONFIG_EXAMPLES_CXXTEST is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_LCDRW is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_NETTEST is not set
+# CONFIG_EXAMPLES_NSH is not set
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXCONSOLE is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXFLAT is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+CONFIG_EXAMPLES_NXLINES=y
+CONFIG_EXAMPLES_NXLINES_VPLANE=0
+CONFIG_EXAMPLES_NXLINES_DEVNO=0
+CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x00006400
+CONFIG_EXAMPLES_NXLINES_LINEWIDTH=16
+CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x00ffff00
+CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=16
+CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0x00ffff00
+CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x00f5f5dc
+CONFIG_EXAMPLES_NXLINES_BPP=32
+# CONFIG_EXAMPLES_NXLINES_EXTERNINIT is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PASHELLO is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_QENCODER is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UDP is not set
+# CONFIG_EXAMPLES_UIP is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBMSC is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+# CONFIG_EXAMPLES_WLAN is not set
+
+#
+# Interpreters
+#
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+
+#
+# Network Utilities
+#
+
+#
+# Networking Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_DHCPC is not set
+# CONFIG_NETUTILS_DHCPD is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_FTPD is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_RESOLV is not set
+# CONFIG_NETUTILS_SMTP is not set
+# CONFIG_NETUTILS_TELNETD is not set
+# CONFIG_NETUTILS_TFTPC is not set
+# CONFIG_NETUTILS_THTTPD is not set
+# CONFIG_NETUTILS_UIPLIB is not set
+# CONFIG_NETUTILS_WEBCLIENT is not set
+
+#
+# ModBus
+#
+
+#
+# FreeModbus
+#
+# CONFIG_MODBUS is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFATFS is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_NSFMOUNT is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PING is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+CONFIG_NSH_CODECS_BUFSIZE=128
+CONFIG_NSH_FILEIOSIZE=1024
+CONFIG_NSH_LINELEN=80
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLEBG is not set
+CONFIG_NSH_ROMFSETC=y
+CONFIG_NSH_ROMFSMOUNTPT="/etc"
+CONFIG_NSH_INITSCRIPT="init.d/rcS"
+CONFIG_NSH_ROMFSDEVNO=1
+CONFIG_NSH_ROMFSSECTSIZE=64
+CONFIG_NSH_FATDEVNO=2
+CONFIG_NSH_FATSECTSIZE=512
+CONFIG_NSH_FATNSECTORS=1024
+CONFIG_NSH_FATMOUNTPT="/tmp"
+CONFIG_NSH_CONSOLE=y
+# CONFIG_NSH_CONDEV is not set
+# CONFIG_NSH_ARCHINIT is not set
+
+#
+# NxWidgets/NxWM
+#
+# CONFIG_NXWIDGETS is not set
+
+#
+# System NSH Add-Ons
+#
+
+#
+# Custom Free Memory Command
+#
+# CONFIG_SYSTEM_FREE is not set
+
+#
+# I2C tool
+#
+
+#
+# FLASH Program Installation
+#
+# CONFIG_SYSTEM_INSTALL is not set
+
+#
+# readline()
+#
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+
+#
+# Power Off
+#
+# CONFIG_SYSTEM_POWEROFF is not set
+
+#
+# RAMTRON
+#
+# CONFIG_SYSTEM_RAMTRON is not set
+
+#
+# SD Card
+#
+# CONFIG_SYSTEM_SDCARD is not set
+
+#
+# Sysinfo
+#
+# CONFIG_SYSTEM_SYSINFO is not set
diff --git a/nuttx/configs/sim/nxlines/setenv.sh b/nuttx/configs/sim/nxlines/setenv.sh
new file mode 100755
index 000000000..0722cbc2e
--- /dev/null
+++ b/nuttx/configs/sim/nxlines/setenv.sh
@@ -0,0 +1,53 @@
+#!/bin/bash
+# sim/nxlines/setenv.sh
+#
+#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+#export NUTTX_BIN=
+#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+
+echo "PATH : ${PATH}"
diff --git a/nuttx/configs/zp214xpa/Kconfig b/nuttx/configs/zp214xpa/Kconfig
new file mode 100644
index 000000000..d8d04ca5c
--- /dev/null
+++ b/nuttx/configs/zp214xpa/Kconfig
@@ -0,0 +1,7 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+if ARCH_BOARD_ZP214XPA
+endif
diff --git a/nuttx/configs/zp214xpa/README.txt b/nuttx/configs/zp214xpa/README.txt
new file mode 100644
index 000000000..6fd7bfba9
--- /dev/null
+++ b/nuttx/configs/zp214xpa/README.txt
@@ -0,0 +1,136 @@
+zp214xpa README FILE
+====================
+
+The ZP213X/4XPA board from the0.net with LPC2148 installed.
+Includes support for the UG-2864AMBAG01 OLED from The0.net.
+
+Contents
+========
+
+  o MCU Connections
+  o Serial Console
+  o Configurations
+
+MCU Connections:
+================
+
+Module Socket:
+--------------
+PIN NAME  PIN NAME
+ 1  VBAT  56  VCC
+ 2  3V3   55  Vusb
+ 3  VREF  54  3V3
+ 4  P0.0  53  RESET
+ 5  P0.1  52  P1.31
+ 6  P0.2  51  P1.30
+ 7  P0.3  50  P1.29
+ 8  P0.4  49  P1.28
+ 9  P0.5  48  P1.27
+10  P0.6  47  P1.26
+11  P0.7  46  P1.25
+12  P0.8  45  P1.24
+13  P0.9  44  P1.23
+14  P0.10 43  P1.22
+15  P0.11 42  P1.21
+16  P0.12 41  P1.20
+17  P0.13 40  P1.19
+18  P0.14 39  P1.18
+19  P0.15 38  P1.17
+20  P0.16 37  P1.16
+21  P0.17 36  P0.31
+22  P0.18 35  P0.30
+23  P0.19 34  P0.29
+24  P0.20 33  P0.28
+25  P0.21 32  P0.27
+26  P0.22 31  P0.26
+27  P0.23 30  P0.25
+28  GND   29  GND
+
+JTAG Debug:
+-----------
+PIN NAME       PIN NAME
+ 1  VCC1        2  3V3
+ 3  P1.31 NTRST 4  GND
+ 5  P1.28 TDI   6  GND
+ 7  P1.30 TMS   8  GND
+ 9  P1.29 TCK  10  GND
+11  P1.26 RTCK 12  GND
+13  P1.27 TDO  14  GND
+15  RESET NRTS 16  GND
+17  N/C   NC0  18  GND
+19  N/C   NC1  20  GND
+
+Z28160 Net Module:
+------------------
+PIN NAME      PIN NAME
+ 1  P0.7  /CS 10  3V3   VCC
+ 2  P0.4  SCK  9  P1.24 RST
+ 3  P0.6  SI   8  N/C   CLKOUT
+ 4  P0.5  SO   7  INT   P1.25
+ 5  GND        6  N/C   WOL
+
+SPI LCD:
+--------
+PIN NAME
+ 1  3V3   3V3
+ 2  VCC   5V
+ 3  P0.18 RESET(DO)
+ 4  P0.19 DI
+ 5  P0.20 CS
+ 6  P0.17 SCK
+ 7  P0.23 A0(RESET)
+ 8  N/C   LED-
+ 9  N/C   LED+(BL)
+10  GND   GND
+
+USB Interface:
+--------------
+Vusb, P0.26, P0.27
+
+Serial Console:
+===============
+
+Both UART0 and UART1 are always enabled.  UART0 is configured to be the
+serial console in these configurations.
+
+P0.0/TXD0/PWM1        Module Socket, Pin 4
+P0.1/RxD0/PWM3/EINT0  Module Socket, Pin 5
+
+P0.8/TXD1/PWM4/AD1.1  Module Socket, Pin 12
+P0.9/RxD1/PWM6/EINT3  Module Socket, Pin 13
+
+Configurations:
+===============
+
+Each NXP LPC214x configuration is maintained in a sudirectory and
+can be selected as follow:
+
+    cd tools
+    ./configure.sh zp214xpa/<subdir>
+    cd -
+    . ./setenv.sh
+
+Where <subdir> is one of the following:
+
+nsh:
+----
+
+  Configures the NuttShell (nsh) located at examples/nsh.  The
+  Configuration enables only the serial NSH interfaces.
+
+    NOTES:
+ 
+    1. This configuration uses the mconf-based configuration tool.  To
+       change this configuration using that tool, you should:
+
+       a. Build and install the mconf tool.  See nuttx/README.txt and
+          misc/tools/
+
+       b. Execute 'make menuconfig' in nuttx/ in order to start the
+          reconfiguration process.
+
+    2. Default platform/toolchain:
+
+       CONFIG_HOST_LINUX=y             : Windows
+       CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc)
+       CONFIG_RAW_BINARY=y             : Output formats: ELF and raw binary
diff --git a/nuttx/configs/zp214xpa/include/board.h b/nuttx/configs/zp214xpa/include/board.h
new file mode 100644
index 000000000..111d8ad55
--- /dev/null
+++ b/nuttx/configs/zp214xpa/include/board.h
@@ -0,0 +1,68 @@
+/****************************************************************************
+ * configs/zp214xpa/include/board.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_ZP214XPA_INCLUDE_BOARD_H
+#define __CONFIGS_ZP214XPA_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+/* Oscillator frequency */
+
+#define LPC214X_FOSC      12000000
+
+/* PLL0 settings CCLK = PLL_M * FOSC PCLK = CCLK/APBDIV */
+
+#define LPC214X_PLL_M     5
+#define LPC214X_PLL_P     2
+#define LPC214X_APB_DIV   1
+
+/* USB Pll settings -- 48 MHz needed.  FUSB = PLL_M FOSC */
+
+#define LPC214X_USBPLL_M  4
+#define LPC214X_USBPLL_P  2
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#endif  /* __CONFIGS_ZP214XPA_INCLUDE_BOARD_H */
diff --git a/nuttx/configs/zp214xpa/nsh/Make.defs b/nuttx/configs/zp214xpa/nsh/Make.defs
new file mode 100644
index 000000000..f55e766d3
--- /dev/null
+++ b/nuttx/configs/zp214xpa/nsh/Make.defs
@@ -0,0 +1,128 @@
+##############################################################################
+# configs/zp214xpa/nsh/Make.defs
+#
+#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+##############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+
+# The default value for CROSSDEV can be overridden from the make command line:
+#   make                         -- Will build for the NuttX buildroot toolchain
+#   make CROSSDEV=arm-eabi-      -- Will build for the devkitARM toolchain
+#   make CROSSDEV=arm-none-eabi- -- Will build for the CodeSourcery toolchain
+#   make CROSSDEV=arm-nuttx-elf- -- Will build for the NuttX buildroot toolchain
+
+CROSSDEV = arm-nuttx-elf-
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+HOSTOS =  ${shell uname -o 2>/dev/null || echo "Other"}
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(ARCHCCMAJOR),4)
+ifneq ($(HOSTOS),Cygwin)
+OBJCOPYARGS = -R .note -R .note.gnu.build-id -R .comment
+endif
+endif
+
+ifeq ($(CROSSDEV),arm-nuttx-elf-)
+  MKDEP = $(TOPDIR)/tools/mkdeps.sh
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script
+  MAXOPTIMIZATION = -Os
+else
+  WINTOOL = y
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}"
+  MAXOPTIMIZATION = -O2
+endif
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+else
+  ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ifeq ($(ARCHCCMAJOR),4)
+  ARCHCPUFLAGS = -mcpu=arm7tdmi -mfloat-abi=soft
+else
+  ARCHCPUFLAGS = -mapcs-32 -mcpu=arm7tdmi -msoft-float
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
+ARCHWARNINGSXX = -Wall -Wshadow
+ARCHDEFINES =
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \
+   $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
+HOSTLDFLAGS =
diff --git a/nuttx/configs/zp214xpa/nsh/defconfig b/nuttx/configs/zp214xpa/nsh/defconfig
new file mode 100644
index 000000000..7c7d9d06c
--- /dev/null
+++ b/nuttx/configs/zp214xpa/nsh/defconfig
@@ -0,0 +1,574 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+CONFIG_NUTTX_NEWCONFIG=y
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+# CONFIG_APPS_DIR="../apps"
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_SYMBOLS is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_8051 is not set
+CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_IMX is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+# CONFIG_ARCH_CHIP_LM3S is not set
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+CONFIG_ARCH_CHIP_LPC214X=y
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_SAM3U is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
+CONFIG_ARCH_ARM7TDMI=y
+CONFIG_ARCH_FAMILY="arm"
+CONFIG_ARCH_CHIP="lpc214x"
+CONFIG_ARCH_HAVE_LOWVECTORS=y
+# CONFIG_ARCH_LOWVECTORS is not set
+CONFIG_BOARD_LOOPSPERMSEC=3270
+# CONFIG_ARCH_CALIBRATION is not set
+
+#
+# ARM Configuration Options
+#
+# CONFIG_ARM_TOOLCHAIN_BUILDROOT is not set
+# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set
+CONFIG_ARM_TOOLCHAIN_GNU_EABI=y
+
+#
+# LPC214x Configuration Options
+#
+CONFIG_ARCH_CHIP_LPC2148=y
+
+#
+# LPC214x Initialization Options
+#
+# CONFIG_EXTMEM_MODE is not set
+# CONFIG_RAM_MODE is not set
+CONFIG_DEFAULT_MODE=y
+CONFIG_CODE_BASE=0x00000000
+CONFIG_PLL_SETUP=y
+CONFIG_MAM_SETUP=y
+CONFIG_APBDIV_SETUP=y
+CONFIG_APBDIV_VALUE=1
+# CONFIG_EMC_SETUP is not set
+# CONFIG_BCFG0_SETUP is not set
+# CONFIG_BCFG1_SETUP is not set
+# CONFIG_BCFG2_SETUP is not set
+# CONFIG_BCFG3_SETUP is not set
+CONFIG_ADC_SETUP=y
+
+#
+# LPC214x Peripheral Support
+#
+CONFIG_LPC214X_UART0=y
+CONFIG_LPC214X_UART1=y
+# CONFIG_LPC214x_FIO is not set
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_DMA is not set
+# CONFIG_ARCH_IRQPRIO is not set
+# CONFIG_CUSTOM_STACK is not set
+# CONFIG_ADDRENV is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
+
+#
+# Board Settings
+#
+CONFIG_DRAM_START=0x40000000
+CONFIG_DRAM_SIZE=32768
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Board Selection
+#
+# CONFIG_ARCH_BOARD_MCU123 is not set
+CONFIG_ARCH_BOARD_ZP214XPA=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="zp214xpa"
+
+#
+# Common Board Options
+#
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Board-Specific Options
+#
+
+#
+# RTOS Features
+#
+CONFIG_MSEC_PER_TICK=10
+CONFIG_RR_INTERVAL=0
+# CONFIG_SCHED_INSTRUMENTATION is not set
+CONFIG_TASK_NAME_SIZE=0
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2008
+CONFIG_START_MONTH=10
+CONFIG_START_DAY=1
+CONFIG_DEV_CONSOLE=y
+# CONFIG_MUTEX_TYPES is not set
+# CONFIG_PRIORITY_INHERITANCE is not set
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_WAITPID is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_CLOCK is not set
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_DISABLE_ENVIRON is not set
+CONFIG_DISABLE_POLL=y
+
+#
+# Sizes of configurable things (0 disables)
+#
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_TASK_ARGS=4
+CONFIG_NPTHREAD_KEYS=4
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NAME_MAX=32
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_PREALLOC_TIMERS=4
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+
+#
+# Device Drivers
+#
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_LOOP is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_PWM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_LCD is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MTD is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+CONFIG_ARCH_HAVE_UART0=y
+CONFIG_ARCH_HAVE_UART1=y
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_UART1_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# UART0 Configuration
+#
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART0_BAUD=38400
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+
+#
+# UART1 Configuration
+#
+CONFIG_UART1_RXBUFSIZE=256
+CONFIG_UART1_TXBUFSIZE=256
+CONFIG_UART1_BAUD=38400
+CONFIG_UART1_BITS=8
+CONFIG_UART1_PARITY=0
+CONFIG_UART1_2STOP=0
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+
+#
+# Networking Support
+#
+# CONFIG_NET is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+# CONFIG_FS_FAT is not set
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_GRAN is not set
+
+#
+# Binary Formats
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+
+#
+# Non-standard Helper Functions
+#
+CONFIG_LIB_KBDCODEC=y
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# Built-In Applications
+#
+# CONFIG_BUILTIN is not set
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CDCACM is not set
+# CONFIG_EXAMPLES_COMPOSITE is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_LCDRW is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_NETTEST is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXCONSOLE is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXFLAT is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PASHELLO is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_QENCODER is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UDP is not set
+# CONFIG_EXAMPLES_UIP is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBMSC is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+# CONFIG_EXAMPLES_WLAN is not set
+
+#
+# Interpreters
+#
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+
+#
+# Network Utilities
+#
+
+#
+# Networking Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_DHCPC is not set
+# CONFIG_NETUTILS_DHCPD is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_FTPD is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_RESOLV is not set
+# CONFIG_NETUTILS_SMTP is not set
+# CONFIG_NETUTILS_TELNETD is not set
+# CONFIG_NETUTILS_TFTPC is not set
+# CONFIG_NETUTILS_THTTPD is not set
+# CONFIG_NETUTILS_UIPLIB is not set
+# CONFIG_NETUTILS_WEBCLIENT is not set
+
+#
+# ModBus
+#
+
+#
+# FreeModbus
+#
+# CONFIG_MODBUS is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFATFS is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_NSFMOUNT is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PING is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+CONFIG_NSH_CODECS_BUFSIZE=128
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLEBG is not set
+CONFIG_NSH_CONSOLE=y
+# CONFIG_NSH_CONDEV is not set
+# CONFIG_NSH_ARCHINIT is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# System NSH Add-Ons
+#
+
+#
+# Custom Free Memory Command
+#
+# CONFIG_SYSTEM_FREE is not set
+
+#
+# I2C tool
+#
+
+#
+# FLASH Program Installation
+#
+# CONFIG_SYSTEM_INSTALL is not set
+
+#
+# readline()
+#
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+
+#
+# Power Off
+#
+# CONFIG_SYSTEM_POWEROFF is not set
+
+#
+# RAMTRON
+#
+# CONFIG_SYSTEM_RAMTRON is not set
+
+#
+# SD Card
+#
+# CONFIG_SYSTEM_SDCARD is not set
+
+#
+# Sysinfo
+#
+# CONFIG_SYSTEM_SYSINFO is not set
diff --git a/nuttx/configs/zp214xpa/nsh/setenv.sh b/nuttx/configs/zp214xpa/nsh/setenv.sh
new file mode 100755
index 000000000..724dab706
--- /dev/null
+++ b/nuttx/configs/zp214xpa/nsh/setenv.sh
@@ -0,0 +1,65 @@
+#!/bin/bash
+# configs/zp214xpa/nsh/setenv.sh
+#
+#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# The zp214xpa/tools directory
+export LPCTOOL_DIR="${WD}/configs/zp214xpa/tools"
+
+# Add the path to the toolchain and tools directory to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/nuttx/configs/zp214xpa/scripts/ld.script b/nuttx/configs/zp214xpa/scripts/ld.script
new file mode 100644
index 000000000..ba6ff8f2c
--- /dev/null
+++ b/nuttx/configs/zp214xpa/scripts/ld.script
@@ -0,0 +1,120 @@
+/****************************************************************************
+ * configs/zp214xpa/scripts/ld.script
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* FLASH:
+ *   The lpc2148 has 512Kb of non-volatile memory beginning at address
+ *   0x0000:0000.  The OS entry point is via the reset vector at address
+ *   0x0000:0000 (default MEMMAP mode assumed)
+ *
+ * SRAM:
+ *   The lpc2148 has 32Kb of on-chip static RAM beginning at address
+ *   0x4000:0000.  The .data section will be relocated from _eronly
+ *   to _sdata at boot time.
+ */
+
+MEMORY
+{
+	flash (rx) : ORIGIN = 0x00000000, LENGTH = 500K
+	sram  (rw) : ORIGIN = 0x40000000, LENGTH = 32K - 32
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	.init_section : {
+		_sinit = ABSOLUTE(.);
+		*(.init_array .init_array.*)
+		_einit = ABSOLUTE(.);
+	} > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > flash
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > flash
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections.	*/
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/nuttx/configs/zp214xpa/src/Makefile b/nuttx/configs/zp214xpa/src/Makefile
new file mode 100644
index 000000000..8f1e1c05d
--- /dev/null
+++ b/nuttx/configs/zp214xpa/src/Makefile
@@ -0,0 +1,84 @@
+############################################################################
+# configs/zp214xpa/src/Makefile
+#
+#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+ARCH_SRCDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+  CFLAGS	+= -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
+  		   -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
+  		   -I "${shell cygpath -w $(ARCH_SRCDIR)/arm}" \
+  		   -I "${shell cygpath -w $(ARCH_SRCDIR)/sched}"
+else
+  CFLAGS	+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/arm -I$(TOPDIR)/sched
+endif
+
+ASRCS		= 
+AOBJS		= $(ASRCS:.S=$(OBJEXT))
+CSRCS		= 
+
+COBJS		= $(CSRCS:.c=$(OBJEXT))
+
+SRCS		= $(ASRCS) $(CSRCS)
+OBJS		= $(AOBJS) $(COBJS)
+
+CFLAGS		+= -I $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+
+all: libboard$(LIBEXT)
+
+$(AOBJS): %$(OBJEXT): %.S
+	$(call ASSEMBLE, $<, $@)
+
+$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+libboard$(LIBEXT): $(OBJS)
+	$(call ARCHIVE, $@, $(OBJS))
+
+.depend: Makefile $(SRCS)
+	$(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	$(Q) touch $@
+
+depend: .depend
+
+clean:
+	$(call DELFILE, libboard$(LIBEXT))
+	$(call CLEAN)
+
+distclean: clean
+	$(call DELFILE, Make.dep)
+	$(call DELFILE, .depend)
+
+-include Make.dep
diff --git a/nuttx/drivers/mmcsd/Kconfig b/nuttx/drivers/mmcsd/Kconfig
index c224f220a..f3a64be6c 100644
--- a/nuttx/drivers/mmcsd/Kconfig
+++ b/nuttx/drivers/mmcsd/Kconfig
@@ -2,6 +2,7 @@
 # For a description of the syntax of this configuration file,
 # see misc/tools/kconfig-language.txt.
 #
+
 config MMCSD_NSLOTS
 	int "Number of MMC/SD slots"
 	default 1
diff --git a/nuttx/drivers/usbhost/usbhost_hidkbd.c b/nuttx/drivers/usbhost/usbhost_hidkbd.c
index 0bab89c28..d6a9ceda3 100644
--- a/nuttx/drivers/usbhost/usbhost_hidkbd.c
+++ b/nuttx/drivers/usbhost/usbhost_hidkbd.c
@@ -421,7 +421,7 @@ static const uint8_t encoding[USBHID_NUMENCODINGS] =
 
   KEYCODE_ENTER,   0,                   KEYCODE_FWDDEL,     KEYCODE_BACKDEL,  0,                   0,             0,                0,
 
-  /* 0x30-0x37: },|,Non-US tilde,:,",grave tidle,<,> */
+  /* 0x30-0x37: },|,Non-US tilde,:,",grave tilde,<,> */
 
   0,               0,                   0,                 0,                0,                   0,             0,                0,
 
@@ -525,7 +525,7 @@ static const uint8_t ucmap[USBHID_NUMSCANCODES] =
   'U',  'V',    'W',    'X',     'Y',  'Z',  '!',    '@',  /* 0x18-0x1f: U-Z,!,@  */
   '#',  '$',    '%',    '^',     '&',  '*',  '(',    ')',  /* 0x20-0x27: #,$,%,^,&,*,(,) */
   '\n', '\033', '\177', 0,       ' ',  '_',  '+',    '{',  /* 0x28-0x2f: Enter,escape,del,back-tab,space,_,+,{ */
-  '}',  '|',    0,      ':',     '"',  0,    '<',    '>',  /* 0x30-0x37: },|,Non-US tilde,:,",grave tidle,<,> */
+  '}',  '|',    0,      ':',     '"',  '~',  '<',    '>',  /* 0x30-0x37: },|,Non-US tilde,:,",grave tilde,<,> */
   '?',  0,       0,      0,      0,    0,    0,      0,    /* 0x38-0x3f: /,CapsLock,F1,F2,F3,F4,F5,F6 */
   0,    0,       0,      0,      0,    0,    0,      0,    /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,ScrollLock */
   0,    0,       0,      0,      0,    0,    0,      0,    /* 0x48-0x4f: Pause,Insert,Home,PageUp,DeleteForward,End,PageDown,RightArrow */
@@ -560,7 +560,7 @@ static const uint8_t lcmap[USBHID_NUMSCANCODES] =
   'u',  'v',     'w',    'x',    'y',  'z', '1',     '2',  /* 0x18-0x1f: u-z,1-2  */
   '3',  '4',     '5',    '6',    '7',  '8', '9',     '0',  /* 0x20-0x27: 3-9,0 */
   '\n', '\033',  '\177', '\t',   ' ',  '-', '=',     '[',  /* 0x28-0x2f: Enter,escape,del,tab,space,-,=,[ */
-  ']',  '\\',    '\234', ';',    '\'', 0,   ',',     '.',  /* 0x30-0x37: ],\,Non-US pound,;,',grave accent,,,. */
+  ']',  '\\',    '\234', ';',    '\'', '`', ',',     '.',  /* 0x30-0x37: ],\,Non-US pound,;,',grave accent,,,. */
   '/',  0,       0,      0,      0,    0,   0,       0,    /* 0x38-0x3f: /,CapsLock,F1,F2,F3,F4,F5,F6 */
   0,    0,       0,      0,      0,    0,   0,       0,    /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,ScrollLock */
   0,    0,       0,      0,      0,    0,   0,       0,    /* 0x48-0x4f: Pause,Insert,Home,PageUp,DeleteForward,End,PageDown,RightArrow */
-- 
cgit v1.2.3


From 41731a71efe2bca6fdc3490eff7af1e6fbcb6a3c Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Tue, 1 Jan 2013 16:33:47 +0000
Subject: All lm3s6965-ek configurations converted to use kconfig-frontends

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5470 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                            |   2 +
 nuttx/arch/arm/src/lm3s/Kconfig            | 140 +++++
 nuttx/configs/lm3s6965-ek/README.txt       |  59 ++-
 nuttx/configs/lm3s6965-ek/nsh/appconfig    |  58 ---
 nuttx/configs/lm3s6965-ek/nsh/defconfig    | 800 ++++++++++++++++++++---------
 nuttx/configs/lm3s6965-ek/nx/appconfig     |  39 --
 nuttx/configs/lm3s6965-ek/nx/defconfig     | 788 +++++++++++++++++-----------
 nuttx/configs/lm3s6965-ek/ostest/appconfig |  39 --
 nuttx/configs/lm3s6965-ek/ostest/defconfig | 705 +++++++++++++++----------
 9 files changed, 1678 insertions(+), 952 deletions(-)
 delete mode 100644 nuttx/configs/lm3s6965-ek/nsh/appconfig
 delete mode 100644 nuttx/configs/lm3s6965-ek/nx/appconfig
 delete mode 100644 nuttx/configs/lm3s6965-ek/ostest/appconfig

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 9fd5619fd..7f2bda457 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3849,4 +3849,6 @@
 	  configuration.
 	* configs/stm32f4discovery/src and nuttx/drivers/lcd/ug-2864hsweg01.c:
 	  Updates and correctinos for the UG-2864HSWEG01 from Darcy Gong.
+	* configs/lm326965-ek:  All configurations converted to use the
+	  kconfig-frontends configuration tool.
 
diff --git a/nuttx/arch/arm/src/lm3s/Kconfig b/nuttx/arch/arm/src/lm3s/Kconfig
index 469ff1fc9..aaf8342fa 100644
--- a/nuttx/arch/arm/src/lm3s/Kconfig
+++ b/nuttx/arch/arm/src/lm3s/Kconfig
@@ -12,6 +12,7 @@ choice
 
 config ARCH_CHIP_LM3S6918
 	bool "LM3S6918"
+	select LM3S_HAVE_SSI1
 
 config ARCH_CHIP_LM3S9B96
 	bool "LM3S9B96"
@@ -27,33 +28,172 @@ config ARCH_CHIP_LM3S8962
 
 endchoice
 
+config LM3S_HAVE_SSI1
+	bool
+
+config LM3S_REVA2
+	bool "Rev A2"
+	default n
+	---help---
+		Some early silicon returned an increase LDO voltage or 2.75V to work
+		around a PLL bug
+
 config LM3S_DFU
 	bool "DFU"
 	default y
 
+menu "Select LM3S Peripheral Support"
+
+config LM3S_UART0
+	bool "UART0"
+	select ARCH_HAVE_UART0
+	default n
+
+config LM3S_UART1
+	bool "UART1"
+	select ARCH_HAVE_UART1
+	default n
+
+config SSI0_DISABLE
+	bool "Disable SSI0"
+	default y
+
+config SSI1_DISABLE
+	bool "Disable SSI1"
+	default y
+
+config LM3S_UART2
+	bool "UART2"
+	select ARCH_HAVE_UART2
+	default n
+
+config LM3S_ETHERNET
+	bool "LM3S Ethernet"
+	default n
+	---help---
+		This must be set (along with NET) to build the LM3S Ethernet driver.
+
+endmenu
+
+menu "Disable GPIO Interrupts"
+
 config LM3S_DISABLE_GPIOA_IRQS
 	bool "Disable GPIOA IRQs"
+	default n
 
 config LM3S_DISABLE_GPIOB_IRQS
 	bool "Disable GPIOB IRQs"
+	default n
 
 config LM3S_DISABLE_GPIOC_IRQS
 	bool "Disable GPIOC IRQs"
+	default n
 
 config LM3S_DISABLE_GPIOD_IRQS
 	bool "Disable GPIOD IRQs"
+	default n
 
 config LM3S_DISABLE_GPIOE_IRQS
 	bool "Disable GPIOE IRQs"
+	default n
 
 config LM3S_DISABLE_GPIOF_IRQS
 	bool "Disable GPIOF IRQs"
+	default n
 
 config LM3S_DISABLE_GPIOG_IRQS
 	bool "Disable GPIOG IRQs"
+	default n
 
 config LM3S_DISABLE_GPIOH_IRQS
 	bool "Disable GPIOH IRQs"
+	default n
 
 config LM3S_DISABLE_GPIOJ_IRQS
 	bool "Disable GPIOJ IRQs"
+	default n
+
+endmenu
+
+if LM3S_ETHERNET
+menu "LM3S Ethernet Configuration"
+
+config LM3S_ETHLEDS
+	bool "Ethernet LEDs"
+	default n
+	---help---
+	Enable to use Ethernet LEDs on the board.
+
+config LM3S_BOARDMAC
+	bool "Board MAC"
+	default n
+	---help---
+		If the board-specific logic can provide a MAC address (via
+		lm3s_ethernetmac()), then this should be selected.
+
+config LM3S_ETHHDUPLEX
+	bool "Force Half Duplex"
+	default n
+	---help---
+		Set to force half duplex operation
+
+config LM3S_ETHNOAUTOCRC
+	bool "Disable auto-CRC"
+	default n
+	---help---
+		Set to suppress auto-CRC generation
+
+config LM3S_ETHNOPAD
+	bool "Disable Tx Padding"
+	default n
+	---help---
+		Set to suppress Tx padding
+
+config LM3S_MULTICAST
+	bool "Enable Multicast"
+	default n
+	---help---
+		Set to enable multicast frames
+
+config LM3S_PROMISCUOUS
+	bool "Enable Promiscuous Mode"
+	default n
+	---help---
+		Set to enable promiscuous mode
+
+config LM3S_TIMESTAMP
+	bool "Enable Timestamping"
+	default n
+
+config LM3S_BADCRC
+	bool "Enable Bad CRC Rejection"
+	default n
+	---help---
+		Set to enable bad CRC rejection.
+
+config M3S_DUMPPACKET
+	bool "Dump Packets"
+	default n
+	---help---
+		Dump each packet received/sent to the console.
+
+endmenu
+endif
+
+if !SSI0_DISABLE || !SSI1_DISABLE
+menu "LM3S SSI Configuration"
+
+config SSI_POLLWAIT
+	bool "Poll Wait (No-Interrupt) Mode"
+	default y
+
+config SSI_TXLIMIT
+	int "Tx Limit"
+	default 4
+	---help---
+		Default of 4 assumes half of the 8 entry FIFO
+
+endmenu
+endif
+
+
diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt
index 1e3aed2d9..09a07ec68 100644
--- a/nuttx/configs/lm3s6965-ek/README.txt
+++ b/nuttx/configs/lm3s6965-ek/README.txt
@@ -478,21 +478,68 @@ Where <subdir> is one of the following:
     Configures the NuttShell (nsh) located at examples/nsh.  The
     Configuration enables both the serial and telnetd NSH interfaces.
 
-    NOTE: As it is configured now, you MUST have a network connected.
-    Otherwise, the NSH prompt will not come up because the Ethernet
-    driver is waiting for the network to come up.  That is probably
-    a bug in the Ethernet driver behavior!
+    NOTES:
+    1. This configuration uses the mconf-based configuration tool.  To
+       change this configuration using that tool, you should:
 
-    Network File System (NFS) support can be added by setting the
-    following in your configuration file:
+       a. Build and install the mconf tool.  See nuttx/README.txt and
+          misc/tools/
+
+       b. Execute 'make menuconfig' in nuttx/ in order to start the
+          reconfiguration process.
+
+    2. Default platform/toolchain:
+
+       CONFIG_HOST_LINUX=y                 : Linux (Cygwin under Windows okay too).
+       CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot (arm-nuttx-elf-gcc)
+       CONFIG_RAW_BINARY=y                 : Output formats: ELF and raw binary
+
+    3. As it is configured now, you MUST have a network connected.
+       Otherwise, the NSH prompt will not come up because the Ethernet
+       driver is waiting for the network to come up.  That is probably
+       a bug in the Ethernet driver behavior!
+
+    4. Network File System (NFS) support can be added by setting the
+      following in your configuration file:
 
       CONFIG_NFS=y
+
   nx:
     And example using the NuttX graphics system (NX).  This example
     uses the P14201 OLED driver.
 
+    NOTES:
+    1. This configuration uses the mconf-based configuration tool.  To
+       change this configuration using that tool, you should:
+
+       a. Build and install the mconf tool.  See nuttx/README.txt and
+          misc/tools/
+
+       b. Execute 'make menuconfig' in nuttx/ in order to start the
+          reconfiguration process.
+
+    2. Default platform/toolchain:
+
+       CONFIG_HOST_LINUX=y                 : Linux (Cygwin under Windows okay too).
+       CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot (arm-nuttx-elf-gcc)
+       CONFIG_RAW_BINARY=y                 : Output formats: ELF and raw binary
+
   ostest:
     This configuration directory, performs a simple OS test using
     examples/ostest.
 
+    NOTES:
+    1. This configuration uses the mconf-based configuration tool.  To
+       change this configuration using that tool, you should:
+
+       a. Build and install the mconf tool.  See nuttx/README.txt and
+          misc/tools/
+
+       b. Execute 'make menuconfig' in nuttx/ in order to start the
+          reconfiguration process.
+
+    2. Default platform/toolchain:
 
+       CONFIG_HOST_LINUX=y                 : Linux (Cygwin under Windows okay too).
+       CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot (arm-nuttx-elf-gcc)
+       CONFIG_RAW_BINARY=y                 : Output formats: ELF and raw binary
diff --git a/nuttx/configs/lm3s6965-ek/nsh/appconfig b/nuttx/configs/lm3s6965-ek/nsh/appconfig
deleted file mode 100644
index 6277056d0..000000000
--- a/nuttx/configs/lm3s6965-ek/nsh/appconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-############################################################################
-# configs/lm3s6965-ek/nsh/appconfig
-#
-#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-# Path to example in apps/examples containing the user_start entry point
-
-CONFIGURED_APPS += examples/nsh
-
-# NSH library
-
-CONFIGURED_APPS += system/readline
-CONFIGURED_APPS += nshlib
-
-# Networking support
-
-ifeq ($(CONFIG_NET),y)
-CONFIGURED_APPS += netutils/uiplib
-CONFIGURED_APPS += netutils/dhcpc
-CONFIGURED_APPS += netutils/resolv
-CONFIGURED_APPS += netutils/tftpc
-CONFIGURED_APPS += netutils/webclient
-ifeq ($(CONFIG_NSH_TELNET),y)
-CONFIGURED_APPS += netutils/telnetd
-endif
-endif
-
-
diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig
index 7b75178ea..84651012d 100755
--- a/nuttx/configs/lm3s6965-ek/nsh/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig
@@ -1,213 +1,231 @@
-############################################################################
-# configs/lm3s6965-ek/nsh/defconfig
-#
-#   Copyright (C) 2010 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-#
-# Architecture Selection
 #
-CONFIG_ARCH="arm"
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+CONFIG_NUTTX_NEWCONFIG=y
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+# CONFIG_APPS_DIR="../apps"
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_SYMBOLS is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_8051 is not set
 CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_IMX is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+CONFIG_ARCH_CHIP_LM3S=y
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_SAM3U is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM3=y
+CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="lm3s"
-CONFIG_ARCH_CHIP_LM3S=y
-CONFIG_ARCH_CHIP_LM3S6965=y
-CONFIG_ARCH_BOARD="lm3s6965-ek"
-CONFIG_ARCH_BOARD_LM3S6965EK=y
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARMV7M_MPU is not set
 CONFIG_BOARD_LOOPSPERMSEC=4531
-CONFIG_DRAM_SIZE=65536
-CONFIG_DRAM_START=0x20000000
-CONFIG_ARCH_IRQPRIO=y
-CONFIG_ARCH_INTERRUPTSTACK=0
-CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARCH_LEDS=y
-CONFIG_ARCH_CALIBRATION=n
+# CONFIG_ARCH_CALIBRATION is not set
 
 #
-# Identify toolchain and linker options
+# ARMV7M Configuration Options
+#
+CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set
+
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=n
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=y
+# LM3S Configuration Options
+#
+# CONFIG_ARCH_CHIP_LM3S6918 is not set
+# CONFIG_ARCH_CHIP_LM3S9B96 is not set
+# CONFIG_ARCH_CHIP_LM3S6432 is not set
+CONFIG_ARCH_CHIP_LM3S6965=y
+# CONFIG_ARCH_CHIP_LM3S8962 is not set
+# CONFIG_LM3S_REVA2 is not set
 CONFIG_LM3S_DFU=y
 
 #
-# Disable support for interrupts on GPIOH and GPIOJ which do not
-# exist on the LM3S6B96.  Additional interrupt support can be
-# disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
+# Select LM3S Peripheral Support
+#
+CONFIG_LM3S_UART0=y
+# CONFIG_LM3S_UART1 is not set
+# CONFIG_SSI0_DISABLE is not set
+CONFIG_SSI1_DISABLE=y
+# CONFIG_LM3S_UART2 is not set
+CONFIG_LM3S_ETHERNET=y
+
+#
+# Disable GPIO Interrupts
+#
+# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set
 CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
 CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
 
 #
-# LM3S6965 specific serial device driver settings
-#
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
-CONFIG_LM3S_UART2=n
-CONFIG_UART0_SERIAL_CONSOLE=y
-CONFIG_UART1_SERIAL_CONSOLE=n
-CONFIG_UART2_SERIAL_CONSOLE=n
-CONFIG_UART0_TXBUFSIZE=256
-CONFIG_UART1_TXBUFSIZE=256
-CONFIG_UART2_TXBUFSIZE=256
-CONFIG_UART0_RXBUFSIZE=256
-CONFIG_UART1_RXBUFSIZE=256
-CONFIG_UART2_RXBUFSIZE=256
-CONFIG_UART0_BAUD=115200
-CONFIG_UART1_BAUD=115200
-CONFIG_UART2_BAUD=115200
-CONFIG_UART0_BITS=8
-CONFIG_UART1_BITS=8
-CONFIG_UART2_BITS=8
-CONFIG_UART0_PARITY=0
-CONFIG_UART1_PARITY=0
-CONFIG_UART2_PARITY=0
-CONFIG_UART0_2STOP=0
-CONFIG_UART1_2STOP=0
-CONFIG_UART2_2STOP=0
+# LM3S Ethernet Configuration
+#
+# CONFIG_LM3S_ETHLEDS is not set
+# CONFIG_LM3S_BOARDMAC is not set
+# CONFIG_LM3S_ETHHDUPLEX is not set
+# CONFIG_LM3S_ETHNOAUTOCRC is not set
+# CONFIG_LM3S_ETHNOPAD is not set
+# CONFIG_LM3S_MULTICAST is not set
+# CONFIG_LM3S_PROMISCUOUS is not set
+# CONFIG_LM3S_TIMESTAMP is not set
+# CONFIG_LM3S_BADCRC is not set
+# CONFIG_M3S_DUMPPACKET is not set
 
 #
-# LM3S6965 specific SSI device driver settings
+# LM3S SSI Configuration
 #
-CONFIG_SSI0_DISABLE=n
-CONFIG_SSI1_DISABLE=y
 CONFIG_SSI_POLLWAIT=y
-#CONFIG_SSI_TXLIMIT=4
+CONFIG_SSI_TXLIMIT=4
+# CONFIG_NET_MULTICAST is not set
+# CONFIG_SDIO_DMA is not set
+# CONFIG_SDIO_WIDTH_D1_ONLY is not set
 
 #
-# LM3S6965 specific serial device driver settings
+# Architecture Options
 #
-CONFIG_LM3S_ETHERNET=y
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=n
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
-
-#
-# General build options
-#
-CONFIG_RRLOAD_BINARY=n
-CONFIG_INTELHEX_BINARY=n
-CONFIG_MOTOROLA_SREC=n
-CONFIG_RAW_BINARY=y
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_IRQPRIO=y
+# CONFIG_CUSTOM_STACK is not set
+# CONFIG_ADDRENV is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
 
 #
-# General OS setup
+# Board Settings
 #
-CONFIG_USER_ENTRYPOINT="nsh_main"
-CONFIG_DEBUG=n
-CONFIG_DEBUG_VERBOSE=n
-CONFIG_DEBUG_SYMBOLS=n
-CONFIG_DEBUG_NET=n
-CONFIG_MM_REGIONS=1
-CONFIG_ARCH_LOWPUTC=y
+CONFIG_DRAM_START=0x20000000
+CONFIG_DRAM_SIZE=65536
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Board Selection
+#
+CONFIG_ARCH_BOARD_LM3S6965EK=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="lm3s6965-ek"
+
+#
+# Common Board Options
+#
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_NSH_MMCSDMINOR=0
+CONFIG_NSH_MMCSDSLOTNO=0
+
+#
+# Board-Specific Options
+#
+
+#
+# RTOS Features
+#
+CONFIG_MSEC_PER_TICK=10
 CONFIG_RR_INTERVAL=200
-CONFIG_SCHED_INSTRUMENTATION=n
+# CONFIG_SCHED_INSTRUMENTATION is not set
 CONFIG_TASK_NAME_SIZE=0
+# CONFIG_JULIAN_TIME is not set
 CONFIG_START_YEAR=2010
 CONFIG_START_MONTH=5
 CONFIG_START_DAY=8
-CONFIG_GREGORIAN_TIME=n
-CONFIG_JULIAN_TIME=n
 CONFIG_DEV_CONSOLE=y
-CONFIG_DEV_LOWCONSOLE=n
-CONFIG_MUTEX_TYPES=n
-CONFIG_PRIORITY_INHERITANCE=n
-CONFIG_SEM_PREALLOCHOLDERS=0
-CONFIG_SEM_NNESTPRIO=0
-CONFIG_FDCLONE_DISABLE=n
-CONFIG_FDCLONE_STDIO=n
+# CONFIG_MUTEX_TYPES is not set
+# CONFIG_PRIORITY_INHERITANCE is not set
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_NXFLAT=n
-
-#
-# The following can be used to disable categories of
-# APIs supported by the OS.  If the compiler supports
-# weak functions, then it should not be necessary to
-# disable functions unless you want to restrict usage
-# of those APIs.
-#
-# There are certain dependency relationships in these
-# features.
-#
-# o mq_notify logic depends on signals to awaken tasks
-#   waiting for queues to become full or empty.
-# o pthread_condtimedwait() depends on signals to wake
-#   up waiting tasks.
-#
-CONFIG_DISABLE_CLOCK=n
-CONFIG_DISABLE_POSIX_TIMERS=n
-CONFIG_DISABLE_PTHREAD=n
-CONFIG_DISABLE_SIGNALS=n
-CONFIG_DISABLE_MQUEUE=n
-CONFIG_DISABLE_MOUNTPOINT=n
-CONFIG_DISABLE_ENVIRON=n
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_WAITPID is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_CLOCK is not set
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_DISABLE_ENVIRON is not set
 CONFIG_DISABLE_POLL=y
 
-#
-# Misc libc settings
-#
-CONFIG_NOPRINTF_FIELDWIDTH=n
-
-#
-# Allow for architecture optimized implementations
-#
-# The architecture can provide optimized versions of the
-# following to improve system performance
-#
-CONFIG_ARCH_MEMCPY=n
-CONFIG_ARCH_MEMCMP=n
-CONFIG_ARCH_MEMMOVE=n
-CONFIG_ARCH_MEMSET=n
-CONFIG_ARCH_STRCMP=n
-CONFIG_ARCH_STRCPY=n
-CONFIG_ARCH_STRNCPY=n
-CONFIG_ARCH_STRLEN=n
-CONFIG_ARCH_STRNLEN=n
-CONFIG_ARCH_BZERO=n
-
 #
 # Sizes of configurable things (0 disables)
 #
@@ -217,8 +235,6 @@ CONFIG_NPTHREAD_KEYS=4
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NAME_MAX=32
-CONFIG_STDIO_BUFFER_SIZE=256
-CONFIG_NUNGET_CHARS=2
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_MQ_MAXMSGSIZE=32
 CONFIG_MAX_WDOGPARMS=2
@@ -226,126 +242,414 @@ CONFIG_PREALLOC_WDOGS=4
 CONFIG_PREALLOC_TIMERS=4
 
 #
-# Filesystem configuration
+# Stack and heap information
 #
-CONFIG_FS_FAT=y
-CONFIG_FS_ROMFS=n
-CONFIG_NFS=n
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
 
 #
-# Maintain legacy build behavior (revisit)
-#
-
+# Device Drivers
+#
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_LOOP is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_PWM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_LCD is not set
 CONFIG_MMCSD=y
+CONFIG_MMCSD_NSLOTS=1
+# CONFIG_MMCSD_READONLY is not set
+# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set
+CONFIG_MMCSD_MMCSUPPORT=y
+CONFIG_MMCSD_HAVECARDDETECT=y
 CONFIG_MMCSD_SPI=y
+CONFIG_MMCSD_SPICLOCK=12500000
 CONFIG_MMCSD_SDIO=y
+# CONFIG_SDIO_MUXBUS is not set
+# CONFIG_MTD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_NET_SLIP is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+CONFIG_ARCH_HAVE_UART0=y
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_NO_SERIAL_CONSOLE is not set
 
 #
-# SPI-based MMC/SD driver
+# UART0 Configuration
 #
-CONFIG_MMCSD_NSLOTS=1
-CONFIG_MMCSD_READONLY=n
-CONFIG_MMCSD_SPICLOCK=12500000
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART0_BAUD=115200
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_WIRELESS is not set
 
 #
-# TCP/IP and UDP support via uIP
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+
+#
+# Networking Support
 #
 CONFIG_NET=y
-CONFIG_NET_IPv6=n
+# CONFIG_NET_NOINTS is not set
+# CONFIG_NET_MULTIBUFFER is not set
+# CONFIG_NET_IPv6 is not set
 CONFIG_NSOCKET_DESCRIPTORS=8
+CONFIG_NET_NACTIVESOCKETS=16
 CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_BUFSIZE=562
+# CONFIG_NET_TCPURGDATA is not set
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_CONNS=8
-CONFIG_NET_NTCP_READAHEAD_BUFFERS=16
-CONFIG_NET_TCPBACKLOG=n
 CONFIG_NET_MAX_LISTENPORTS=8
+CONFIG_NET_TCP_READAHEAD_BUFSIZE=562
+CONFIG_NET_NTCP_READAHEAD_BUFFERS=16
+CONFIG_NET_TCP_RECVDELAY=0
+# CONFIG_NET_TCPBACKLOG is not set
 CONFIG_NET_UDP=y
 CONFIG_NET_UDP_CHECKSUMS=y
-#CONFIG_NET_UDP_CONNS=8
+CONFIG_NET_UDP_CONNS=8
+# CONFIG_NET_BROADCAST is not set
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_PING=y
-#CONFIG_NET_PINGADDRCONF=0
+# CONFIG_NET_PINGADDRCONF is not set
+# CONFIG_NET_IGMP is not set
 CONFIG_NET_STATISTICS=y
-#CONFIG_NET_RECEIVE_WINDOW=
-#CONFIG_NET_ARPTAB_SIZE=8
-CONFIG_NET_BROADCAST=n
+CONFIG_NET_RECEIVE_WINDOW=562
+CONFIG_NET_ARPTAB_SIZE=16
+# CONFIG_NET_ARP_IPIN is not set
 
 #
-# UIP Network Utilities
+# File Systems
+#
+
+#
+# File system configuration
+#
+CONFIG_FS_FAT=y
+# CONFIG_FAT_LCNAMES is not set
+# CONFIG_FAT_LFN is not set
+# CONFIG_FS_FATTIME is not set
+# CONFIG_FAT_DMAMEMORY is not set
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_NFS is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_GRAN is not set
+
+#
+# Binary Formats
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+
+#
+# Non-standard Helper Functions
+#
+CONFIG_LIB_KBDCODEC=y
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
+
+#
+# Application Configuration
 #
-CONFIG_NET_DHCP_LIGHT=n
-CONFIG_NET_RESOLV_ENTRIES=4
 
 #
-# Settings for examples/uip
+# Built-In Applications
 #
-CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002
-CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00
-CONFIG_EXAMPLES_UIP_DHCPC=n
+# CONFIG_BUILTIN is not set
 
 #
-# Settings for examples/nettest
-CONFIG_EXAMPLES_NETTEST_SERVER=n
-CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n
-CONFIG_EXAMPLES_NETTEST_NOMAC=n
-CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
-CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
-CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CDCACM is not set
+# CONFIG_EXAMPLES_COMPOSITE is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_LCDRW is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_NETTEST is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXCONSOLE is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXFLAT is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PASHELLO is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_QENCODER is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UDP is not set
+# CONFIG_EXAMPLES_DISCOVER is not set
+# CONFIG_EXAMPLES_UIP is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBMSC is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+# CONFIG_EXAMPLES_WGET is not set
 
 #
-# Settings for examples/ostest
+# Interpreters
 #
-CONFIG_EXAMPLES_OSTEST_LOOPS=1
-CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048
-CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3
 
 #
-# Settings for apps/nshlib
+# Interpreters
 #
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+
+#
+# Network Utilities
+#
+
+#
+# Networking Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+CONFIG_NETUTILS_DHCPC=y
+# CONFIG_NETUTILS_DHCPD is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_FTPD is not set
+# CONFIG_NETUTILS_JSON is not set
+CONFIG_NETUTILS_RESOLV=y
+CONFIG_NET_RESOLV_ENTRIES=4
+CONFIG_NET_RESOLV_MAXRESPONSE=96
+# CONFIG_NETUTILS_SMTP is not set
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NETUTILS_TFTPC=y
+# CONFIG_NETUTILS_THTTPD is not set
+CONFIG_NETUTILS_UIPLIB=y
+CONFIG_NETUTILS_WEBCLIENT=y
+CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)"
+# CONFIG_NETUTILS_WEBSERVER is not set
+# CONFIG_NETUTILS_DISCOVER is not set
+# CONFIG_NETUTILS_XMLRPC is not set
+
+#
+# ModBus
+#
+
+#
+# FreeModbus
+#
+# CONFIG_MODBUS is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFATFS is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_NSFMOUNT is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PING is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+CONFIG_NSH_CODECS_BUFSIZE=128
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_STRERROR=n
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_NESTDEPTH=3
-CONFIG_NSH_DISABLESCRIPT=n
-CONFIG_NSH_DISABLEBG=n
-CONFIG_NSH_ROMFSETC=n
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLEBG is not set
 CONFIG_NSH_CONSOLE=y
-CONFIG_NSH_TELNET=y
+# CONFIG_NSH_CONDEV is not set
 CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_TELNET=y
+CONFIG_NSH_TELNETD_PORT=23
+CONFIG_NSH_TELNETD_DAEMONPRIO=100
+CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048
+CONFIG_NSH_TELNETD_CLIENTPRIO=100
+CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048
 CONFIG_NSH_IOBUFFER_SIZE=512
-CONFIG_NSH_DHCPC=n
-CONFIG_NSH_NOMAC=y
+# CONFIG_NSH_TELNET_LOGIN is not set
 CONFIG_NSH_IPADDR=0x0a000002
 CONFIG_NSH_DRIPADDR=0x0a000001
 CONFIG_NSH_NETMASK=0xffffff00
-CONFIG_NSH_ROMFSMOUNTPT="/etc"
-CONFIG_NSH_INITSCRIPT="init.d/rcS"
-CONFIG_NSH_ROMFSDEVNO=0
-CONFIG_NSH_ROMFSSECTSIZE=64
-CONFIG_NSH_FATDEVNO=1
-CONFIG_NSH_FATSECTSIZE=512
-CONFIG_NSH_FATNSECTORS=1024
-CONFIG_NSH_FATMOUNTPT="/tmp"
+CONFIG_NSH_NOMAC=y
+CONFIG_NSH_MAX_ROUNDTRIP=20
 
 #
-# Architecture-specific NSH options
+# NxWidgets/NxWM
 #
-CONFIG_NSH_MMCSDSPIPORTNO=0
-CONFIG_NSH_MMCSDSLOTNO=0
-CONFIG_NSH_MMCSDMINOR=0
 
 #
-# Stack and heap information
+# System NSH Add-Ons
 #
-CONFIG_BOOT_RUNFROMFLASH=n
-CONFIG_BOOT_COPYTORAM=n
-CONFIG_CUSTOM_STACK=n
-CONFIG_IDLETHREAD_STACKSIZE=1024
-CONFIG_USERMAIN_STACKSIZE=2048
-CONFIG_PTHREAD_STACK_MIN=256
-CONFIG_PTHREAD_STACK_DEFAULT=2048
-CONFIG_HEAP_BASE=
-CONFIG_HEAP_SIZE=
+
+#
+# Custom Free Memory Command
+#
+# CONFIG_SYSTEM_FREE is not set
+
+#
+# I2C tool
+#
+
+#
+# FLASH Program Installation
+#
+# CONFIG_SYSTEM_INSTALL is not set
+
+#
+# readline()
+#
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+
+#
+# Power Off
+#
+# CONFIG_SYSTEM_POWEROFF is not set
+
+#
+# RAMTRON
+#
+# CONFIG_SYSTEM_RAMTRON is not set
+
+#
+# SD Card
+#
+# CONFIG_SYSTEM_SDCARD is not set
+
+#
+# Sysinfo
+#
+# CONFIG_SYSTEM_SYSINFO is not set
diff --git a/nuttx/configs/lm3s6965-ek/nx/appconfig b/nuttx/configs/lm3s6965-ek/nx/appconfig
deleted file mode 100644
index 69f92ce3a..000000000
--- a/nuttx/configs/lm3s6965-ek/nx/appconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-############################################################################
-# configs/lm3s6965-ek/nx/appconfig
-#
-#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-# Path to example in apps/examples containing the user_start entry point
-
-CONFIGURED_APPS += examples/nx
-
diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig
index bca864013..5fb666e65 100755
--- a/nuttx/configs/lm3s6965-ek/nx/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nx/defconfig
@@ -1,219 +1,212 @@
-############################################################################
-# configs/lm3s6965-ek/nx/defconfig
-#
-#   Copyright (C) 2010 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-#
-# Architecture Selection
 #
-CONFIG_ARCH="arm"
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+CONFIG_NUTTX_NEWCONFIG=y
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+# CONFIG_APPS_DIR="../apps"
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_SYMBOLS is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_8051 is not set
 CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_IMX is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+CONFIG_ARCH_CHIP_LM3S=y
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_SAM3U is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM3=y
+CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="lm3s"
-CONFIG_ARCH_CHIP_LM3S=y
-CONFIG_ARCH_CHIP_LM3S6965=y
-CONFIG_ARCH_BOARD="lm3s6965-ek"
-CONFIG_ARCH_BOARD_LM3S6965EK=y
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARMV7M_MPU is not set
 CONFIG_BOARD_LOOPSPERMSEC=4531
-CONFIG_DRAM_SIZE=65536
-CONFIG_DRAM_START=0x20000000
-CONFIG_ARCH_IRQPRIO=y
-CONFIG_ARCH_INTERRUPTSTACK=0
-CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARCH_LEDS=y
-CONFIG_ARCH_CALIBRATION=n
+# CONFIG_ARCH_CALIBRATION is not set
+
+#
+# ARMV7M Configuration Options
+#
+CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set
 
 #
-# Identify toolchain and linker options
+# LM3S Configuration Options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=n
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=y
+# CONFIG_ARCH_CHIP_LM3S6918 is not set
+# CONFIG_ARCH_CHIP_LM3S9B96 is not set
+# CONFIG_ARCH_CHIP_LM3S6432 is not set
+CONFIG_ARCH_CHIP_LM3S6965=y
+# CONFIG_ARCH_CHIP_LM3S8962 is not set
+# CONFIG_LM3S_REVA2 is not set
 CONFIG_LM3S_DFU=y
 
 #
-# Disable support for interrupts on GPIOH and GPIOJ which do not
-# exist on the LM3S6B96.  Additional interrupt support can be
-# disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
+# Select LM3S Peripheral Support
+#
+CONFIG_LM3S_UART0=y
+# CONFIG_LM3S_UART1 is not set
+# CONFIG_SSI0_DISABLE is not set
+CONFIG_SSI1_DISABLE=y
+# CONFIG_LM3S_UART2 is not set
+# CONFIG_LM3S_ETHERNET is not set
+
+#
+# Disable GPIO Interrupts
+#
+# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set
 CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
 CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
 
 #
-# LM3S6965 specific serial device driver settings
+# LM3S SSI Configuration
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
-CONFIG_LM3S_UART2=n
-CONFIG_UART0_SERIAL_CONSOLE=y
-CONFIG_UART1_SERIAL_CONSOLE=n
-CONFIG_UART2_SERIAL_CONSOLE=n
-CONFIG_UART0_TXBUFSIZE=256
-CONFIG_UART1_TXBUFSIZE=256
-CONFIG_UART2_TXBUFSIZE=256
-CONFIG_UART0_RXBUFSIZE=256
-CONFIG_UART1_RXBUFSIZE=256
-CONFIG_UART2_RXBUFSIZE=256
-CONFIG_UART0_BAUD=115200
-CONFIG_UART1_BAUD=115200
-CONFIG_UART2_BAUD=115200
-CONFIG_UART0_BITS=8
-CONFIG_UART1_BITS=8
-CONFIG_UART2_BITS=8
-CONFIG_UART0_PARITY=0
-CONFIG_UART1_PARITY=0
-CONFIG_UART2_PARITY=0
-CONFIG_UART0_2STOP=0
-CONFIG_UART1_2STOP=0
-CONFIG_UART2_2STOP=0
+CONFIG_SSI_POLLWAIT=y
+CONFIG_SSI_TXLIMIT=4
 
 #
-# LM3S6965 specific SSI device driver settings
+# Architecture Options
 #
-CONFIG_SSI0_DISABLE=n
-CONFIG_SSI1_DISABLE=y
-CONFIG_SSI_POLLWAIT=y
-#CONFIG_SSI_TXLIMIT=4
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_IRQPRIO=y
+# CONFIG_CUSTOM_STACK is not set
+# CONFIG_ADDRENV is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
 
 #
-# LM3S6965 specific serial device driver settings
+# Board Settings
 #
-CONFIG_LM3S_ETHERNET=n
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_DRAM_START=0x20000000
+CONFIG_DRAM_SIZE=65536
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
 
 #
-# General build options
+# Boot options
 #
-CONFIG_RRLOAD_BINARY=n
-CONFIG_INTELHEX_BINARY=n
-CONFIG_MOTOROLA_SREC=n
-CONFIG_RAW_BINARY=y
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
 
 #
-# General SPI interface configuration
+# Board Selection
 #
-CONFIG_SPI_CMDDATA=y
+CONFIG_ARCH_BOARD_LM3S6965EK=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="lm3s6965-ek"
 
 #
-# General OS setup
+# Common Board Options
 #
-CONFIG_USER_ENTRYPOINT="nx_main"
-CONFIG_DEBUG=n
-CONFIG_DEBUG_VERBOSE=n
-CONFIG_DEBUG_SYMBOLS=n
-CONFIG_DEBUG_GRAPHICS=n
-CONFIG_LCD_RITDEBUG=n
-CONFIG_MM_REGIONS=1
-CONFIG_ARCH_LOWPUTC=y
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+
+#
+# Board-Specific Options
+#
+
+#
+# RTOS Features
+#
+CONFIG_MSEC_PER_TICK=10
 CONFIG_RR_INTERVAL=200
-CONFIG_SCHED_INSTRUMENTATION=n
+# CONFIG_SCHED_INSTRUMENTATION is not set
 CONFIG_TASK_NAME_SIZE=0
+# CONFIG_JULIAN_TIME is not set
 CONFIG_START_YEAR=2010
 CONFIG_START_MONTH=5
 CONFIG_START_DAY=12
-CONFIG_GREGORIAN_TIME=n
-CONFIG_JULIAN_TIME=n
 CONFIG_DEV_CONSOLE=y
-CONFIG_DEV_LOWCONSOLE=n
-CONFIG_MUTEX_TYPES=n
-CONFIG_PRIORITY_INHERITANCE=n
-CONFIG_SEM_PREALLOCHOLDERS=0
-CONFIG_SEM_NNESTPRIO=0
-CONFIG_FDCLONE_DISABLE=n
-CONFIG_FDCLONE_STDIO=n
+# CONFIG_MUTEX_TYPES is not set
+# CONFIG_PRIORITY_INHERITANCE is not set
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_NXFLAT=n
-
-#
-# The following can be used to disable categories of
-# APIs supported by the OS.  If the compiler supports
-# weak functions, then it should not be necessary to
-# disable functions unless you want to restrict usage
-# of those APIs.
-#
-# There are certain dependency relationships in these
-# features.
-#
-# o mq_notify logic depends on signals to awaken tasks
-#   waiting for queues to become full or empty.
-# o pthread_condtimedwait() depends on signals to wake
-#   up waiting tasks.
-#
-CONFIG_DISABLE_CLOCK=n
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_WAITPID is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+CONFIG_USER_ENTRYPOINT="nx_main"
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_CLOCK is not set
 CONFIG_DISABLE_POSIX_TIMERS=y
-CONFIG_DISABLE_PTHREAD=n
-CONFIG_DISABLE_SIGNALS=n
-CONFIG_DISABLE_MQUEUE=n
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_POLL=y
 
-#
-# Misc libc settings
-#
-CONFIG_NOPRINTF_FIELDWIDTH=n
-
-#
-# Allow for architecture optimized implementations
-#
-# The architecture can provide optimized versions of the
-# following to improve system performance
-#
-CONFIG_ARCH_MEMCPY=n
-CONFIG_ARCH_MEMCMP=n
-CONFIG_ARCH_MEMMOVE=n
-CONFIG_ARCH_MEMSET=n
-CONFIG_ARCH_STRCMP=n
-CONFIG_ARCH_STRCPY=n
-CONFIG_ARCH_STRNCPY=n
-CONFIG_ARCH_STRLEN=n
-CONFIG_ARCH_STRNLEN=n
-CONFIG_ARCH_BZERO=n
-
 #
 # Sizes of configurable things (0 disables)
 #
@@ -223,8 +216,6 @@ CONFIG_NPTHREAD_KEYS=4
 CONFIG_NFILE_DESCRIPTORS=12
 CONFIG_NFILE_STREAMS=12
 CONFIG_NAME_MAX=32
-CONFIG_STDIO_BUFFER_SIZE=256
-CONFIG_NUNGET_CHARS=2
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_MQ_MAXMSGSIZE=32
 CONFIG_MAX_WDOGPARMS=2
@@ -232,187 +223,382 @@ CONFIG_PREALLOC_WDOGS=4
 CONFIG_PREALLOC_TIMERS=4
 
 #
-# Framebuffer driver options
-CONFIG_FB_CMAP=n
-CONFIG_FB_HWCURSOR=n
-CONFIG_FB_HWCURSORIMAGE=n
-#CONFIG_FB_HWCURSORSIZE
-#CONFIG_FB_TRANSPARENCY
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
 
 #
-# Filesystem configuration
+# Device Drivers
+#
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_LOOP is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_PWM is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_OWNBUS is not set
+CONFIG_SPI_EXCHANGE=y
+CONFIG_SPI_CMDDATA=y
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+CONFIG_LCD=y
+# CONFIG_LCD_NOGETRUN is not set
+CONFIG_LCD_MAXCONTRAST=255
+CONFIG_LCD_MAXPOWER=1
+CONFIG_LCD_P14201=y
+CONFIG_P14201_NINTERFACES=1
+CONFIG_P14201_SPIMODE=2
+CONFIG_P14201_FREQUENCY=3500000
+CONFIG_P14201_FRAMEBUFFER=y
+# CONFIG_LCD_NOKIA6100 is not set
+# CONFIG_LCD_UG9664HSWAG01 is not set
+# CONFIG_LCD_UG2864AMBAG01 is not set
+# CONFIG_LCD_SSD1289 is not set
+CONFIG_LCD_LANDSCAPE=y
+# CONFIG_LCD_PORTRAIT is not set
+# CONFIG_LCD_RPORTRAIT is not set
+# CONFIG_LCD_RLANDSCAPE is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MTD is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+CONFIG_ARCH_HAVE_UART0=y
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# UART0 Configuration
+#
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART0_BAUD=115200
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_WIRELESS is not set
+
+#
+# System Logging Device Options
 #
-CONFIG_FS_FAT=n
-CONFIG_FS_ROMFS=n
 
 #
-# Maintain legacy build behavior (revisit)
+# System Logging
 #
+# CONFIG_RAMLOG is not set
 
-CONFIG_MMCSD=y
-CONFIG_MMCSD_SPI=y
-CONFIG_MMCSD_SDIO=y
+#
+# Networking Support
+#
+# CONFIG_NET is not set
 
 #
-# SPI-based MMC/SD driver
+# File Systems
 #
-CONFIG_MMCSD_NSLOTS=1
-CONFIG_MMCSD_READONLY=n
-CONFIG_MMCSD_SPICLOCK=12500000
 
 #
-# TCP/IP and UDP support via uIP
+# File system configuration
 #
-CONFIG_NET=n
-CONFIG_NET_IPv6=n
-CONFIG_NSOCKET_DESCRIPTORS=0
-CONFIG_NET_SOCKOPTS=y
-CONFIG_NET_BUFSIZE=420
-CONFIG_NET_TCP=n
-CONFIG_NET_TCP_CONNS=40
-CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_UDP=n
-CONFIG_NET_UDP_CHECKSUMS=y
-#CONFIG_NET_UDP_CONNS=10
-CONFIG_NET_ICMP=n
-CONFIG_NET_ICMP_PING=n
-#CONFIG_NET_PINGADDRCONF=0
-CONFIG_NET_STATISTICS=y
-#CONFIG_NET_RECEIVE_WINDOW=
-#CONFIG_NET_ARPTAB_SIZE=8
-CONFIG_NET_BROADCAST=n
+# CONFIG_FS_RAMMAP is not set
 
 #
-# UIP Network Utilities
+# System Logging
 #
-CONFIG_NET_DHCP_LIGHT=n
-CONFIG_NET_RESOLV_ENTRIES=4
+# CONFIG_SYSLOG is not set
 
 #
-# Graphics related configuration settings
+# Graphics Support
 #
 CONFIG_NX=y
-CONFIG_NX_MULTIUSER=n
+CONFIG_NX_LCDDRIVER=y
 CONFIG_NX_NPLANES=1
+# CONFIG_NX_WRITEONLY is not set
+
+#
+# Supported Pixel Depths
+#
 CONFIG_NX_DISABLE_1BPP=y
 CONFIG_NX_DISABLE_2BPP=y
-CONFIG_NX_DISABLE_4BPP=n
+# CONFIG_NX_DISABLE_4BPP is not set
 CONFIG_NX_DISABLE_8BPP=y
 CONFIG_NX_DISABLE_16BPP=y
 CONFIG_NX_DISABLE_24BPP=y
 CONFIG_NX_DISABLE_32BPP=y
 CONFIG_NX_PACKEDMSFIRST=y
-CONFIG_NX_LCDDRIVER=y
-CONFIG_LCD_MAXPOWER=1
-CONFIG_LCD_MAXCONTRAST=255
+
+#
+# Input Devices
+#
 CONFIG_NX_MOUSE=y
 CONFIG_NX_KBD=y
-#CONFIG_NXTK_BORDERWIDTH=4
-CONFIG_NXTK_BORDERCOLOR1=8
-CONFIG_NXTK_BORDERCOLOR2=4
-CONFIG_NXTK_AUTORAISE=n
-CONFIG_NXFONT_SANS23X27=y
+
+#
+# Framed Window Borders
+#
+CONFIG_NXTK_BORDERWIDTH=4
+CONFIG_NXTK_BORDERCOLOR1=0x08
+CONFIG_NXTK_BORDERCOLOR2=0x04
+CONFIG_NXTK_BORDERCOLOR3=0
+# CONFIG_NXTK_AUTORAISE is not set
+
+#
+# Font Selections
+#
 CONFIG_NXFONTS_CHARBITS=7
-CONFIG_NX_BLOCKING=y
-CONFIG_NX_MXSERVERMSGS=32
-CONFIG_NX_MXCLIENTMSGS=16
+# CONFIG_NXFONT_MONO5X8 is not set
+# CONFIG_NXFONT_SANS17X22 is not set
+# CONFIG_NXFONT_SANS20X26 is not set
+CONFIG_NXFONT_SANS23X27=y
+# CONFIG_NXFONT_SANS22X29 is not set
+# CONFIG_NXFONT_SANS28X37 is not set
+# CONFIG_NXFONT_SANS39X48 is not set
+# CONFIG_NXFONT_SANS17X23B is not set
+# CONFIG_NXFONT_SANS20X27B is not set
+# CONFIG_NXFONT_SANS22X29B is not set
+# CONFIG_NXFONT_SANS28X37B is not set
+# CONFIG_NXFONT_SANS40X49B is not set
+# CONFIG_NXFONT_SERIF22X29 is not set
+# CONFIG_NXFONT_SERIF29X37 is not set
+# CONFIG_NXFONT_SERIF38X48 is not set
+# CONFIG_NXFONT_SERIF22X28B is not set
+# CONFIG_NXFONT_SERIF27X38B is not set
+# CONFIG_NXFONT_SERIF38X49B is not set
+# CONFIG_NXCONSOLE is not set
 
 #
-# RiT P14201 OLED Driver Configuration
+# NX Multi-user only options
 #
-CONFIG_LCD_P14201=y
-CONFIG_P14201_SPIMODE=2
-CONFIG_P14201_FREQUENCY=3500000
-CONFIG_P14201_NINTERFACES=1
-CONFIG_P14201_FRAMEBUFFER=y
+# CONFIG_NX_MULTIUSER is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_GRAN is not set
 
 #
-# Settings for examples/uip
+# Binary Formats
 #
-CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002
-CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00
-CONFIG_EXAMPLES_UIP_DHCPC=n
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
 
 #
-# Settings for examples/nettest
-CONFIG_EXAMPLES_NETTEST_SERVER=n
-CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n
-CONFIG_EXAMPLES_NETTEST_NOMAC=n
-CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
-CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
-CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
+# Library Routines
+#
 
 #
-# Settings for examples/ostest
+# Standard C Library Options
 #
-CONFIG_EXAMPLES_OSTEST_LOOPS=1
-CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048
-CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
 
 #
-# Settings for apps/nshlib
+# Non-standard Helper Functions
 #
-CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_STRERROR=n
-CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NESTDEPTH=3
-CONFIG_NSH_DISABLESCRIPT=n
-CONFIG_NSH_DISABLEBG=n
-CONFIG_NSH_ROMFSETC=n
-CONFIG_NSH_CONSOLE=y
-CONFIG_NSH_TELNET=n
-CONFIG_NSH_ARCHINIT=n
-CONFIG_NSH_IOBUFFER_SIZE=512
-CONFIG_NSH_DHCPC=n
-CONFIG_NSH_NOMAC=n
-CONFIG_NSH_IPADDR=0x0a000002
-CONFIG_NSH_DRIPADDR=0x0a000001
-CONFIG_NSH_NETMASK=0xffffff00
-CONFIG_NSH_ROMFSMOUNTPT="/etc"
-CONFIG_NSH_INITSCRIPT="init.d/rcS"
-CONFIG_NSH_ROMFSDEVNO=0
-CONFIG_NSH_ROMFSSECTSIZE=64
-CONFIG_NSH_FATDEVNO=1
-CONFIG_NSH_FATSECTSIZE=512
-CONFIG_NSH_FATNSECTORS=1024
-CONFIG_NSH_FATMOUNTPT="/tmp"
+CONFIG_LIB_KBDCODEC=y
 
 #
-# Architecture-specific NSH options
+# Basic CXX Support
 #
-CONFIG_NSH_MMCSDSPIPORTNO=0
-CONFIG_NSH_MMCSDSLOTNO=0
-CONFIG_NSH_MMCSDMINOR=0
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
 
 #
-# Settings for examples/nx
+# Application Configuration
 #
+
+#
+# Built-In Applications
+#
+# CONFIG_BUILTIN is not set
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CDCACM is not set
+# CONFIG_EXAMPLES_COMPOSITE is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_LCDRW is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_NETTEST is not set
+# CONFIG_EXAMPLES_NSH is not set
+# CONFIG_EXAMPLES_NULL is not set
+CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_VPLANE=0
 CONFIG_EXAMPLES_NX_DEVNO=0
-CONFIG_EXAMPLES_NX_BGCOLOR=2
-CONFIG_EXAMPLES_NX_COLOR1=10
-CONFIG_EXAMPLES_NX_COLOR2=12
-CONFIG_EXAMPLES_NX_TBCOLOR=8
-CONFIG_EXAMPLES_NX_FONTCOLOR=0
+# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set
+CONFIG_EXAMPLES_NX_BGCOLOR=0x02
+CONFIG_EXAMPLES_NX_COLOR1=0x0a
+CONFIG_EXAMPLES_NX_COLOR2=0x0c
+CONFIG_EXAMPLES_NX_TBCOLOR=0x08
+CONFIG_EXAMPLES_NX_FONTCOLOR=0x00
+CONFIG_EXAMPLES_NX_DEFAULT_FONT=y
 CONFIG_EXAMPLES_NX_BPP=4
-CONFIG_EXAMPLES_NX_RAWWINDOWS=n
-CONFIG_EXAMPLES_NX_STACKSIZE=2048
-CONFIG_EXAMPLES_NX_CLIENTPRIO=80
-CONFIG_EXAMPLES_NX_SERVERPRIO=120
-CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4
+# CONFIG_EXAMPLES_NX_RAWWINDOWS is not set
 CONFIG_EXAMPLES_NX_EXTERNINIT=y
+# CONFIG_EXAMPLES_NXCONSOLE is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXFLAT is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PASHELLO is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_QENCODER is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UDP is not set
+# CONFIG_EXAMPLES_UIP is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBMSC is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
 
 #
-# Stack and heap information
+# Interpreters
 #
-CONFIG_BOOT_RUNFROMFLASH=n
-CONFIG_BOOT_COPYTORAM=n
-CONFIG_CUSTOM_STACK=n
-CONFIG_IDLETHREAD_STACKSIZE=1024
-CONFIG_USERMAIN_STACKSIZE=2048
-CONFIG_PTHREAD_STACK_MIN=256
-CONFIG_PTHREAD_STACK_DEFAULT=2048
-CONFIG_HEAP_BASE=
-CONFIG_HEAP_SIZE=
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+
+#
+# Network Utilities
+#
+
+#
+# Networking Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_DHCPC is not set
+# CONFIG_NETUTILS_DHCPD is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_FTPD is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_RESOLV is not set
+# CONFIG_NETUTILS_SMTP is not set
+# CONFIG_NETUTILS_TELNETD is not set
+# CONFIG_NETUTILS_TFTPC is not set
+# CONFIG_NETUTILS_THTTPD is not set
+# CONFIG_NETUTILS_UIPLIB is not set
+# CONFIG_NETUTILS_WEBCLIENT is not set
+
+#
+# ModBus
+#
+
+#
+# FreeModbus
+#
+# CONFIG_MODBUS is not set
+
+#
+# NSH Library
+#
+# CONFIG_NSH_LIBRARY is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# System NSH Add-Ons
+#
+
+#
+# Custom Free Memory Command
+#
+# CONFIG_SYSTEM_FREE is not set
+
+#
+# I2C tool
+#
+
+#
+# FLASH Program Installation
+#
+# CONFIG_SYSTEM_INSTALL is not set
+
+#
+# readline()
+#
+# CONFIG_SYSTEM_READLINE is not set
+
+#
+# Power Off
+#
+# CONFIG_SYSTEM_POWEROFF is not set
+
+#
+# RAMTRON
+#
+# CONFIG_SYSTEM_RAMTRON is not set
+
+#
+# SD Card
+#
+# CONFIG_SYSTEM_SDCARD is not set
+
+#
+# Sysinfo
+#
+# CONFIG_SYSTEM_SYSINFO is not set
diff --git a/nuttx/configs/lm3s6965-ek/ostest/appconfig b/nuttx/configs/lm3s6965-ek/ostest/appconfig
deleted file mode 100644
index dabf1f2b4..000000000
--- a/nuttx/configs/lm3s6965-ek/ostest/appconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-############################################################################
-# configs/lm3s6965-ek/ostest/appconfig
-#
-#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-# Path to example in apps/examples containing the user_start entry point
-
-CONFIGURED_APPS += examples/ostest
-
diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig
index fcee44433..d1168ad45 100755
--- a/nuttx/configs/lm3s6965-ek/ostest/defconfig
+++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig
@@ -1,211 +1,213 @@
-############################################################################
-# configs/lm3s6965-ek/ostest/defconfig
-#
-#   Copyright (C) 2010 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-#
-# Architecture Selection
 #
-CONFIG_ARCH="arm"
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+CONFIG_NUTTX_NEWCONFIG=y
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+# CONFIG_APPS_DIR="../apps"
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_SYMBOLS is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_8051 is not set
 CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_IMX is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+CONFIG_ARCH_CHIP_LM3S=y
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_SAM3U is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM3=y
+CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="lm3s"
-CONFIG_ARCH_CHIP_LM3S=y
-CONFIG_ARCH_CHIP_LM3S6965=y
-CONFIG_ARCH_BOARD="lm3s6965-ek"
-CONFIG_ARCH_BOARD_LM3S6965EK=y
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARMV7M_MPU is not set
 CONFIG_BOARD_LOOPSPERMSEC=4531
-CONFIG_DRAM_SIZE=65536
-CONFIG_DRAM_START=0x20000000
-CONFIG_ARCH_IRQPRIO=y
-CONFIG_ARCH_INTERRUPTSTACK=0
-CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARCH_LEDS=y
-CONFIG_ARCH_CALIBRATION=n
+# CONFIG_ARCH_CALIBRATION is not set
 
 #
-# Identify toolchain and linker options
+# ARMV7M Configuration Options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=n
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=y
-CONFIG_LM3S_DFU=y
+CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set
 
 #
-# Disable support for interrupts on GPIOH and GPIOJ which do not
-# exist on the LM3S6B96.  Additional interrupt support can be
-# disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+# LM3S Configuration Options
+#
+# CONFIG_ARCH_CHIP_LM3S6918 is not set
+# CONFIG_ARCH_CHIP_LM3S9B96 is not set
+# CONFIG_ARCH_CHIP_LM3S6432 is not set
+CONFIG_ARCH_CHIP_LM3S6965=y
+# CONFIG_ARCH_CHIP_LM3S8962 is not set
+# CONFIG_LM3S_REVA2 is not set
+CONFIG_LM3S_DFU=y
 
 #
-# LM3S6965 specific serial device driver settings
+# Select LM3S Peripheral Support
 #
 CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
-CONFIG_LM3S_UART2=n
-CONFIG_UART0_SERIAL_CONSOLE=y
-CONFIG_UART1_SERIAL_CONSOLE=n
-CONFIG_UART2_SERIAL_CONSOLE=n
-CONFIG_UART0_TXBUFSIZE=256
-CONFIG_UART1_TXBUFSIZE=256
-CONFIG_UART2_TXBUFSIZE=256
-CONFIG_UART0_RXBUFSIZE=256
-CONFIG_UART1_RXBUFSIZE=256
-CONFIG_UART2_RXBUFSIZE=256
-CONFIG_UART0_BAUD=115200
-CONFIG_UART1_BAUD=115200
-CONFIG_UART2_BAUD=115200
-CONFIG_UART0_BITS=8
-CONFIG_UART1_BITS=8
-CONFIG_UART2_BITS=8
-CONFIG_UART0_PARITY=0
-CONFIG_UART1_PARITY=0
-CONFIG_UART2_PARITY=0
-CONFIG_UART0_2STOP=0
-CONFIG_UART1_2STOP=0
-CONFIG_UART2_2STOP=0
+# CONFIG_LM3S_UART1 is not set
+# CONFIG_SSI0_DISABLE is not set
+CONFIG_SSI1_DISABLE=y
+# CONFIG_LM3S_UART2 is not set
+# CONFIG_LM3S_ETHERNET is not set
 
 #
-# LM3S6965 specific SSI device driver settings
+# Disable GPIO Interrupts
 #
-CONFIG_SSI0_DISABLE=n
-CONFIG_SSI1_DISABLE=y
-CONFIG_SSI_POLLWAIT=y
-#CONFIG_SSI_TXLIMIT=4
+# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set
+# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set
+CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
+CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
 
 #
-# LM3S6965 specific serial device driver settings
+# LM3S SSI Configuration
 #
-CONFIG_LM3S_ETHERNET=n
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_SSI_POLLWAIT=y
+CONFIG_SSI_TXLIMIT=4
+# CONFIG_SDIO_DMA is not set
+# CONFIG_SDIO_WIDTH_D1_ONLY is not set
 
 #
-# General build options
+# Architecture Options
 #
-CONFIG_RRLOAD_BINARY=n
-CONFIG_INTELHEX_BINARY=n
-CONFIG_MOTOROLA_SREC=n
-CONFIG_RAW_BINARY=y
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_IRQPRIO=y
+# CONFIG_CUSTOM_STACK is not set
+# CONFIG_ADDRENV is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
 
 #
-# General OS setup
+# Board Settings
 #
-CONFIG_USER_ENTRYPOINT="ostest_main"
-CONFIG_DEBUG=n
-CONFIG_DEBUG_VERBOSE=n
-CONFIG_DEBUG_SYMBOLS=n
-CONFIG_MM_REGIONS=1
-CONFIG_ARCH_LOWPUTC=y
-CONFIG_RR_INTERVAL=200
-CONFIG_SCHED_INSTRUMENTATION=n
-CONFIG_TASK_NAME_SIZE=0
-CONFIG_START_YEAR=2010
-CONFIG_START_MONTH=5
-CONFIG_START_DAY=6
-CONFIG_GREGORIAN_TIME=n
-CONFIG_JULIAN_TIME=n
-CONFIG_DEV_CONSOLE=y
-CONFIG_DEV_LOWCONSOLE=y
-CONFIG_MUTEX_TYPES=n
-CONFIG_PRIORITY_INHERITANCE=n
-CONFIG_SEM_PREALLOCHOLDERS=0
-CONFIG_SEM_NNESTPRIO=0
-CONFIG_FDCLONE_DISABLE=n
-CONFIG_FDCLONE_STDIO=n
-CONFIG_SDCLONE_DISABLE=y
-CONFIG_NXFLAT=n
+CONFIG_DRAM_START=0x20000000
+CONFIG_DRAM_SIZE=65536
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
 
 #
-# The following can be used to disable categories of
-# APIs supported by the OS.  If the compiler supports
-# weak functions, then it should not be necessary to
-# disable functions unless you want to restrict usage
-# of those APIs.
+# Boot options
 #
-# There are certain dependency relationships in these
-# features.
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
 #
-# o mq_notify logic depends on signals to awaken tasks
-#   waiting for queues to become full or empty.
-# o pthread_condtimedwait() depends on signals to wake
-#   up waiting tasks.
+# Board Selection
 #
-CONFIG_DISABLE_CLOCK=n
-CONFIG_DISABLE_POSIX_TIMERS=n
-CONFIG_DISABLE_PTHREAD=n
-CONFIG_DISABLE_SIGNALS=n
-CONFIG_DISABLE_MQUEUE=n
-CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
+CONFIG_ARCH_BOARD_LM3S6965EK=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="lm3s6965-ek"
 
 #
-# Misc libc settings
+# Common Board Options
 #
-CONFIG_NOPRINTF_FIELDWIDTH=n
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
 
 #
-# Allow for architecture optimized implementations
+# Board-Specific Options
 #
-# The architecture can provide optimized versions of the
-# following to improve system performance
+
+#
+# RTOS Features
 #
-CONFIG_ARCH_MEMCPY=n
-CONFIG_ARCH_MEMCMP=n
-CONFIG_ARCH_MEMMOVE=n
-CONFIG_ARCH_MEMSET=n
-CONFIG_ARCH_STRCMP=n
-CONFIG_ARCH_STRCPY=n
-CONFIG_ARCH_STRNCPY=n
-CONFIG_ARCH_STRLEN=n
-CONFIG_ARCH_STRNLEN=n
-CONFIG_ARCH_BZERO=n
+CONFIG_MSEC_PER_TICK=10
+CONFIG_RR_INTERVAL=200
+# CONFIG_SCHED_INSTRUMENTATION is not set
+CONFIG_TASK_NAME_SIZE=0
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2010
+CONFIG_START_MONTH=5
+CONFIG_START_DAY=6
+CONFIG_DEV_CONSOLE=y
+# CONFIG_MUTEX_TYPES is not set
+# CONFIG_PRIORITY_INHERITANCE is not set
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_WAITPID is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+CONFIG_USER_ENTRYPOINT="ostest_main"
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_CLOCK is not set
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+CONFIG_DISABLE_MOUNTPOINT=y
+CONFIG_DISABLE_ENVIRON=y
+CONFIG_DISABLE_POLL=y
 
 #
 # Sizes of configurable things (0 disables)
@@ -216,8 +218,6 @@ CONFIG_NPTHREAD_KEYS=4
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NAME_MAX=32
-CONFIG_STDIO_BUFFER_SIZE=256
-CONFIG_NUNGET_CHARS=2
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_MQ_MAXMSGSIZE=32
 CONFIG_MAX_WDOGPARMS=2
@@ -225,123 +225,306 @@ CONFIG_PREALLOC_WDOGS=4
 CONFIG_PREALLOC_TIMERS=4
 
 #
-# Filesystem configuration
+# Stack and heap information
 #
-CONFIG_FS_FAT=n
-CONFIG_FS_ROMFS=n
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
 
 #
-# Maintain legacy build behavior (revisit)
-#
-
+# Device Drivers
+#
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_LOOP is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_PWM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_LCD is not set
 CONFIG_MMCSD=y
+CONFIG_MMCSD_NSLOTS=1
+# CONFIG_MMCSD_READONLY is not set
+# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set
+CONFIG_MMCSD_MMCSUPPORT=y
+CONFIG_MMCSD_HAVECARDDETECT=y
 CONFIG_MMCSD_SPI=y
+CONFIG_MMCSD_SPICLOCK=12500000
 CONFIG_MMCSD_SDIO=y
+# CONFIG_SDIO_MUXBUS is not set
+# CONFIG_MTD is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+CONFIG_DEV_LOWCONSOLE=y
+# CONFIG_16550_UART is not set
+CONFIG_ARCH_HAVE_UART0=y
+CONFIG_MCU_SERIAL=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_NO_SERIAL_CONSOLE is not set
 
 #
-# SPI-based MMC/SD driver
+# UART0 Configuration
+#
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART0_BAUD=115200
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+
+#
+# Networking Support
+#
+# CONFIG_NET is not set
+
+#
+# File Systems
 #
-CONFIG_MMCSD_NSLOTS=1
-CONFIG_MMCSD_READONLY=n
-CONFIG_MMCSD_SPICLOCK=12500000
 
 #
-# TCP/IP and UDP support via uIP
+# File system configuration
 #
-CONFIG_NET=n
-CONFIG_NET_IPv6=n
-CONFIG_NSOCKET_DESCRIPTORS=0
-CONFIG_NET_SOCKOPTS=y
-CONFIG_NET_BUFSIZE=420
-CONFIG_NET_TCP=n
-CONFIG_NET_TCP_CONNS=40
-CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_UDP=n
-CONFIG_NET_UDP_CHECKSUMS=y
-#CONFIG_NET_UDP_CONNS=10
-CONFIG_NET_ICMP=n
-CONFIG_NET_ICMP_PING=n
-#CONFIG_NET_PINGADDRCONF=0
-CONFIG_NET_STATISTICS=y
-#CONFIG_NET_RECEIVE_WINDOW=
-#CONFIG_NET_ARPTAB_SIZE=8
-CONFIG_NET_BROADCAST=n
+# CONFIG_FS_RAMMAP is not set
 
 #
-# UIP Network Utilities
+# System Logging
 #
-CONFIG_NET_DHCP_LIGHT=n
-CONFIG_NET_RESOLV_ENTRIES=4
+# CONFIG_SYSLOG is not set
 
 #
-# Settings for examples/uip
+# Graphics Support
 #
-CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002
-CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00
-CONFIG_EXAMPLES_UIP_DHCPC=n
+# CONFIG_NX is not set
 
 #
-# Settings for examples/nettest
-CONFIG_EXAMPLES_NETTEST_SERVER=n
-CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n
-CONFIG_EXAMPLES_NETTEST_NOMAC=n
-CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
-CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
-CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_GRAN is not set
 
 #
-# Settings for examples/ostest
+# Binary Formats
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+
+#
+# Non-standard Helper Functions
+#
+CONFIG_LIB_KBDCODEC=y
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# Built-In Applications
+#
+# CONFIG_BUILTIN is not set
+
 #
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CDCACM is not set
+# CONFIG_EXAMPLES_COMPOSITE is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_LCDRW is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_NETTEST is not set
+# CONFIG_EXAMPLES_NSH is not set
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXCONSOLE is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXFLAT is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+CONFIG_EXAMPLES_OSTEST=y
+# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set
 CONFIG_EXAMPLES_OSTEST_LOOPS=1
 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048
 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3
+CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000
+CONFIG_EXAMPLES_OSTEST_RR_RUNS=10
+# CONFIG_EXAMPLES_PASHELLO is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_QENCODER is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UDP is not set
+# CONFIG_EXAMPLES_UIP is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBMSC is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
 
 #
-# Settings for apps/nshlib
-#
-CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_STRERROR=n
-CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NESTDEPTH=3
-CONFIG_NSH_DISABLESCRIPT=n
-CONFIG_NSH_DISABLEBG=n
-CONFIG_NSH_ROMFSETC=n
-CONFIG_NSH_CONSOLE=y
-CONFIG_NSH_TELNET=n
-CONFIG_NSH_ARCHINIT=n
-CONFIG_NSH_IOBUFFER_SIZE=512
-CONFIG_NSH_DHCPC=n
-CONFIG_NSH_NOMAC=n
-CONFIG_NSH_IPADDR=0x0a000002
-CONFIG_NSH_DRIPADDR=0x0a000001
-CONFIG_NSH_NETMASK=0xffffff00
-CONFIG_NSH_ROMFSMOUNTPT="/etc"
-CONFIG_NSH_INITSCRIPT="init.d/rcS"
-CONFIG_NSH_ROMFSDEVNO=0
-CONFIG_NSH_ROMFSSECTSIZE=64
-CONFIG_NSH_FATDEVNO=1
-CONFIG_NSH_FATSECTSIZE=512
-CONFIG_NSH_FATNSECTORS=1024
-CONFIG_NSH_FATMOUNTPT="/tmp"
-
-#
-# Architecture-specific NSH options
-#
-CONFIG_NSH_MMCSDSPIPORTNO=0
-CONFIG_NSH_MMCSDSLOTNO=0
-CONFIG_NSH_MMCSDMINOR=0
+# Interpreters
+#
 
 #
-# Stack and heap information
+# Interpreters
 #
-CONFIG_BOOT_RUNFROMFLASH=n
-CONFIG_BOOT_COPYTORAM=n
-CONFIG_CUSTOM_STACK=n
-CONFIG_IDLETHREAD_STACKSIZE=1024
-CONFIG_USERMAIN_STACKSIZE=2048
-CONFIG_PTHREAD_STACK_MIN=256
-CONFIG_PTHREAD_STACK_DEFAULT=2048
-CONFIG_HEAP_BASE=
-CONFIG_HEAP_SIZE=
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+
+#
+# Network Utilities
+#
+
+#
+# Networking Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_DHCPC is not set
+# CONFIG_NETUTILS_DHCPD is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_FTPD is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_RESOLV is not set
+# CONFIG_NETUTILS_SMTP is not set
+# CONFIG_NETUTILS_TELNETD is not set
+# CONFIG_NETUTILS_TFTPC is not set
+# CONFIG_NETUTILS_THTTPD is not set
+# CONFIG_NETUTILS_UIPLIB is not set
+# CONFIG_NETUTILS_WEBCLIENT is not set
+
+#
+# ModBus
+#
+
+#
+# FreeModbus
+#
+# CONFIG_MODBUS is not set
+
+#
+# NSH Library
+#
+# CONFIG_NSH_LIBRARY is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# System NSH Add-Ons
+#
+
+#
+# Custom Free Memory Command
+#
+# CONFIG_SYSTEM_FREE is not set
+
+#
+# I2C tool
+#
+
+#
+# FLASH Program Installation
+#
+# CONFIG_SYSTEM_INSTALL is not set
+
+#
+# readline()
+#
+# CONFIG_SYSTEM_READLINE is not set
+
+#
+# Power Off
+#
+# CONFIG_SYSTEM_POWEROFF is not set
+
+#
+# RAMTRON
+#
+# CONFIG_SYSTEM_RAMTRON is not set
+
+#
+# SD Card
+#
+# CONFIG_SYSTEM_SDCARD is not set
+
+#
+# Sysinfo
+#
+# CONFIG_SYSTEM_SYSINFO is not set
-- 
cgit v1.2.3


From d0d3328d9cec65a161330c29aa318d1a3ded63e3 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Wed, 2 Jan 2013 14:02:07 +0000
Subject: Misc fixes for LM3S kconfig-frontends build

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5472 42af7a65-404d-4744-a932-0658087f49c3
---
 misc/buildroot/configs/cortexm3-defconfig-4.3.3 |  7 +++++++
 nuttx/ChangeLog                                 |  5 ++++-
 nuttx/arch/arm/src/arm/Kconfig                  |  7 +++++++
 nuttx/arch/arm/src/arm/Toolchain.defs           |  5 +++++
 nuttx/arch/arm/src/armv7-m/Kconfig              |  8 ++++++++
 nuttx/arch/arm/src/armv7-m/Toolchain.defs       | 11 ++++++-----
 nuttx/configs/Kconfig                           |  2 +-
 nuttx/configs/lm3s6965-ek/nsh/defconfig         |  7 ++++++-
 nuttx/configs/lm3s6965-ek/nx/defconfig          |  1 +
 nuttx/configs/lm3s6965-ek/ostest/defconfig      |  1 +
 nuttx/drivers/Kconfig                           |  3 ++-
 nuttx/drivers/mmcsd/Kconfig                     |  3 ++-
 12 files changed, 50 insertions(+), 10 deletions(-)

(limited to 'nuttx/arch')

diff --git a/misc/buildroot/configs/cortexm3-defconfig-4.3.3 b/misc/buildroot/configs/cortexm3-defconfig-4.3.3
index 664000a16..a3371531b 100644
--- a/misc/buildroot/configs/cortexm3-defconfig-4.3.3
+++ b/misc/buildroot/configs/cortexm3-defconfig-4.3.3
@@ -14,6 +14,7 @@ BR2_arm=y
 # BR2_m68k is not set
 # BR2_m68hc11 is not set
 # BR2_m68hc12 is not set
+# BR2_m9s12x is not set
 # BR2_mips is not set
 # BR2_mipsel is not set
 # BR2_nios2 is not set
@@ -71,8 +72,11 @@ BR2_GNU_TARGET_SUFFIX="nuttx-elf"
 # Binutils Options
 #
 # BR2_BINUTILS_VERSION_2_17 is not set
+# BR2_BINUTILS_VERSION_2_18 is not set
 # BR2_BINUTILS_VERSION_2_19 is not set
 BR2_BINUTILS_VERSION_2_19_1=y
+# BR2_BINUTILS_VERSION_2_21_1 is not set
+# BR2_BINUTILS_VERSION_2_22 is not set
 BR2_BINUTILS_VERSION="2.19.1"
 BR2_EXTRA_BINUTILS_CONFIG_OPTIONS=""
 
@@ -80,9 +84,12 @@ BR2_EXTRA_BINUTILS_CONFIG_OPTIONS=""
 # GCC Options
 #
 BR2_PACKAGE_GCC=y
+# BR2_GCC_VERSION_3_3_6 is not set
 # BR2_GCC_VERSION_3_4_6 is not set
 # BR2_GCC_VERSION_4_2_4 is not set
 BR2_GCC_VERSION_4_3_3=y
+# BR2_GCC_VERSION_4_5_2 is not set
+# BR2_GCC_VERSION_4_6_3 is not set
 BR2_GCC_SUPPORTS_SYSROOT=y
 BR2_GCC_VERSION="4.3.3"
 # BR2_GCC_USE_SJLJ_EXCEPTIONS is not set
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 7f2bda457..ee43a897e 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3851,4 +3851,7 @@
 	  Updates and correctinos for the UG-2864HSWEG01 from Darcy Gong.
 	* configs/lm326965-ek:  All configurations converted to use the
 	  kconfig-frontends configuration tool.
-
+	* configs/Kconfig: NSH_MMCSDSPIPORTNO should depend on MMCSD_SPI,
+	  not just SPI (from Jose Pablo Carballo).
+	* arch/arm/src/arm/Kconfig and armv7m/Kconfig:  Add an option for
+	  buildroot toolchains:  They may be EABI or OABI.
diff --git a/nuttx/arch/arm/src/arm/Kconfig b/nuttx/arch/arm/src/arm/Kconfig
index 0d08d89a8..665fab575 100644
--- a/nuttx/arch/arm/src/arm/Kconfig
+++ b/nuttx/arch/arm/src/arm/Kconfig
@@ -33,3 +33,10 @@ config ARM_TOOLCHAIN_GNU_EABI
 		configured for arm-none-eabi.
 
 endchoice
+
+config ARM_OABI_TOOLCHAIN
+	bool "OABI (vs EABI)"
+	default y
+	depends on ARM_TOOLCHAIN_BUILDROOT
+	---help---
+		Most of the older buildroot toolchains are OABI and are named arm-nuttx-elf- vs. arm-nuttx-eabi-
diff --git a/nuttx/arch/arm/src/arm/Toolchain.defs b/nuttx/arch/arm/src/arm/Toolchain.defs
index defe30b51..ea11c4dc9 100644
--- a/nuttx/arch/arm/src/arm/Toolchain.defs
+++ b/nuttx/arch/arm/src/arm/Toolchain.defs
@@ -102,8 +102,13 @@ endif
 # NuttX buildroot under Linux or Cygwin
 
 ifeq ($(CONFIG_ARM_TOOLCHAIN),BUILDROOT)
+ifeq ($(CONFIG_ARMV_OABI_TOOLCHAIN),y)
   CROSSDEV = arm-nuttx-elf-
   ARCROSSDEV = arm-nuttx-elf-
+else
+  CROSSDEV = arm-nuttx-eabi-
+  ARCROSSDEV = arm-nuttx-eabi-
+endif
   MAXOPTIMIZATION = -Os
 endif
 
diff --git a/nuttx/arch/arm/src/armv7-m/Kconfig b/nuttx/arch/arm/src/armv7-m/Kconfig
index dc5aa3915..a154a4c5c 100644
--- a/nuttx/arch/arm/src/armv7-m/Kconfig
+++ b/nuttx/arch/arm/src/armv7-m/Kconfig
@@ -49,3 +49,11 @@ config ARMV7M_TOOLCHAIN_RAISONANCE
 	depends on HOST_WINDOWS
 
 endchoice
+
+config ARMV7M_OABI_TOOLCHAIN
+	bool "OABI (vs EABI)"
+	default y
+	depends on ARMV7M_TOOLCHAIN_BUILDROOT
+	---help---
+		Most of the older buildroot toolchains are OABI and are named arm-nuttx-elf- vs. arm-nuttx-eabi-
+
diff --git a/nuttx/arch/arm/src/armv7-m/Toolchain.defs b/nuttx/arch/arm/src/armv7-m/Toolchain.defs
index e214ce8bd..d7f2ed77f 100644
--- a/nuttx/arch/arm/src/armv7-m/Toolchain.defs
+++ b/nuttx/arch/arm/src/armv7-m/Toolchain.defs
@@ -160,14 +160,15 @@ endif
 # NuttX buildroot under Linux or Cygwin
 
 ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),BUILDROOT)
-  # OABI
-  # CROSSDEV = arm-nuttx-elf-
-  # ARCROSSDEV = arm-nuttx-elf-
-  # ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
-  # EABI
+ifeq ($(CONFIG_ARMV7M_OABI_TOOLCHAIN),y)
+  CROSSDEV = arm-nuttx-elf-
+  ARCROSSDEV = arm-nuttx-elf-
+  ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+else
   CROSSDEV = arm-nuttx-eabi-
   ARCROSSDEV = arm-nuttx-eabi-
   ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
   MAXOPTIMIZATION = -Os
 endif
 
diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig
index cda5aa7bc..d851eeccb 100644
--- a/nuttx/configs/Kconfig
+++ b/nuttx/configs/Kconfig
@@ -761,7 +761,7 @@ config NSH_MMCSDSLOTNO
 config NSH_MMCSDSPIPORTNO
 	int "MMC/SD SPI device number"
 	default 0
-	depends on NSH_LIBRARY && MMCSD && SPI
+	depends on NSH_LIBRARY && MMCSD && MMCSD_SPI
 	---help---
 		If board-specif NSH start-up logic will mount an SPI-based MMC/SD volume, then this setting may be needed to tell the board logic which SPI bus to use.  Default: 0 (meaning is board-specific).
 
diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig
index 84651012d..1213797a7 100755
--- a/nuttx/configs/lm3s6965-ek/nsh/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig
@@ -89,6 +89,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set
+CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 
 #
 # LM3S Configuration Options
@@ -189,6 +190,7 @@ CONFIG_ARCH_HAVE_LEDS=y
 CONFIG_ARCH_LEDS=y
 CONFIG_NSH_MMCSDMINOR=0
 CONFIG_NSH_MMCSDSLOTNO=0
+CONFIG_NSH_MMCSDSPIPORTNO=0
 
 #
 # Board-Specific Options
@@ -259,7 +261,10 @@ CONFIG_DEV_NULL=y
 # CONFIG_CAN is not set
 # CONFIG_PWM is not set
 # CONFIG_I2C is not set
-# CONFIG_SPI is not set
+CONFIG_SPI=y
+# CONFIG_SPI_OWNBUS is not set
+CONFIG_SPI_EXCHANGE=y
+# CONFIG_SPI_CMDDATA is not set
 # CONFIG_RTC is not set
 # CONFIG_WATCHDOG is not set
 # CONFIG_ANALOG is not set
diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig
index 5fb666e65..7fca4d735 100755
--- a/nuttx/configs/lm3s6965-ek/nx/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nx/defconfig
@@ -89,6 +89,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set
+CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 
 #
 # LM3S Configuration Options
diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig
index d1168ad45..abfdcc251 100755
--- a/nuttx/configs/lm3s6965-ek/ostest/defconfig
+++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig
@@ -89,6 +89,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set
+CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 
 #
 # LM3S Configuration Options
diff --git a/nuttx/drivers/Kconfig b/nuttx/drivers/Kconfig
index 8302d21b7..3ced01b58 100644
--- a/nuttx/drivers/Kconfig
+++ b/nuttx/drivers/Kconfig
@@ -140,7 +140,8 @@ menuconfig SPI
 	bool "SPI Driver Support"
 	default n
 	---help---
-		This selection enables building of the "upper-half" SPI driver.
+		This selection enables selection of common SPI options.  This option
+		should be enabled by all platforms that support SPI interfaces.
 		See include/nuttx/spi.h for further SPI driver information.
 
 if SPI
diff --git a/nuttx/drivers/mmcsd/Kconfig b/nuttx/drivers/mmcsd/Kconfig
index f3a64be6c..5cdc23bcf 100644
--- a/nuttx/drivers/mmcsd/Kconfig
+++ b/nuttx/drivers/mmcsd/Kconfig
@@ -39,8 +39,9 @@ config MMCSD_HAVECARDDETECT
 		100% accurate
 
 config MMCSD_SPI
-	bool "MMC/SD spi transfer support"
+	bool "MMC/SD SPI transfer support"
 	default y
+	depends on SPI
 
 config MMCSD_SPICLOCK
 	int "MMC/SD maximum SPI clock"
-- 
cgit v1.2.3


From 8d75785fad6f77f796655167bb9087266df2a117 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Thu, 3 Jan 2013 13:39:16 +0000
Subject: STM32 FLASH changes from Freddie Chopin

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5473 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                        |   3 +
 nuttx/README.txt                       | 110 +++++++++++++++++++++++++++++++++
 nuttx/arch/arm/src/stm32/stm32_flash.c |  37 ++++++-----
 nuttx/include/nuttx/progmem.h          |   4 +-
 4 files changed, 138 insertions(+), 16 deletions(-)

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index ee43a897e..0c7a4dcbf 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3855,3 +3855,6 @@
 	  not just SPI (from Jose Pablo Carballo).
 	* arch/arm/src/arm/Kconfig and armv7m/Kconfig:  Add an option for
 	  buildroot toolchains:  They may be EABI or OABI.
+	* include/nuttx/progmem and arch/arm/src/stm32/stm32_flash.c:
+	  Fix a counting bug plus change interface to use either relative
+	  or absolut FLASH addressing (from Freddie Chopin).
diff --git a/nuttx/README.txt b/nuttx/README.txt
index dc3c9fb67..c00f086a1 100644
--- a/nuttx/README.txt
+++ b/nuttx/README.txt
@@ -10,6 +10,8 @@ README
   o Configuring NuttX
     - Instantiating "Canned" Configurations
     - NuttX Configuration Tool
+    - Incompatibilities with Older Configurations
+    - Converting Older Configurations to use the Configuration Tool
     - NuttX Configuration Tool under DOS
   o Toolchains
     - Cross-Development Toolchains
@@ -292,6 +294,114 @@ NuttX Configuration Tool
      install 'mconf', make certain that your PATH variable includes
      a path to that installation directory.
 
+  The basic configuration order is "bottom-up":
+
+    - Select the build environment,
+    - Select the processor,
+    - Select the board,
+    - Select the supported peripherals
+    - Configure the device drivers,
+    - Configure the application options on top of this.
+
+  This is pretty straight forward for creating new configurations
+  but may be less intuitive for modifying existing configurations.
+
+Incompatibilities with Older Configurations
+-------------------------------------------
+
+  ***** WARNING *****
+
+  The old legacy, manual configurations and the new kconfig-frontends
+  configurations are not 100% compatible.  Old legacy configurations
+  can *not* be used with the kconfig-frontends tool:  If you run
+  'make menuconfig' with a legacy configuration the resulting
+  configuration will probably not be functional.
+
+  Q: How can I tell if a configuration is a new kconfig-frontends
+     configuration or an older, manual configuration?
+
+  A: a) New kcondfig-frontends configurations will have this setting
+        within the defconfig/.config file":
+
+          CONFIG_NUTTX_NEWCONFIG=y
+
+     b) Only old, manual configurations will have an appconfig file
+
+Converting Older Configurations to use the Configuration Tool
+-------------------------------------------------------------
+
+  Q: How can I convert a older, manual configuration into a new,
+     kconfig-frontends toolchain.
+
+  A: 1) Look at the appconfig file:  Each application path there
+        will now have to have an enabling setting.  For example,
+        if the old appconfig file had:
+
+          CONFIGURED_APPS = examples/ostest
+
+        Then the new configuration will need:
+
+          CONFIG_EXAMPLES_OSTEST=y
+
+        The appconfig file can then be deleted because it will not
+        be needed after the conversion.
+
+     2) Build the cmpconfig utility at tools:
+
+          cd tools
+          make -f Makefile.host cmpconfig
+
+     3) Perform these steps repeatedly until you are convinced that
+        the configurations are the same:
+
+        a) Repeat the following until you have account for all of the differences:
+
+             cp configs/<board>/<condfiguration>/defconfig .config
+             make menuconfig  (Just exit and save the new .config file)
+             tools/cmpconfig configs/<board>/<condfiguration>/defconfig .config | grep file1
+ 
+           The final grep will show settings in the old defconfig file that
+           do not appear in the new .config file (or have a different value
+           in the new .config file).  In the new configuration, you will
+           probably have to enable certain groups of features.  Such
+           hierarachical enabling options were not part of the older
+           configuration.
+
+        b) Then make sure these all make sense:
+
+             tools/cmpconfig configs/<board>/<condfiguration>/defconfig .config | grep file2
+
+           The final grep will show settings in the new .config file that
+           do not appear in the older defconfig file (or have a different value
+           in the new .config file).  Here you should see only the new
+           hierarachical enabling options (such as CONFIG_SPI or CONFIG_MMCSD)
+           plus some other internal configuration settings (like CONFIG_ARCH_HAVE_UART0).
+           You will have to convince yourself that these new settings all make sense.
+
+     4) Finally, update the configuration:
+
+          cp .config configs/<board>/<condfiguration>/defconfig
+          rm configs/<board>/<condfiguration>/appconfig
+
+        NOTE:  You should comment out the line containing the CONFIG_APPS_DIR
+        in the new defconfig file.  Why?  Because the application directory
+        may reside at a different location when the configuration is installed
+        at some later time.
+
+          # CONFIG_APPS_DIR="../apps"
+
+     5) The updated configuration can then be instantiated in the normal
+        fashion:
+
+          cd tools
+          ./configure.sh <board>/<condfiguration>
+
+        NOTE: If CONFIG_APPS_DIR is not defined in the defconfig file,
+        the configure.sh script will find and add the new, correct path to
+        the application directory (CONFIG_APPS_DIR) when it copies the
+        defconfig file to the .config file.  This is the setting that was
+        commented out in step 4.
+
 NuttX Configuration Tool under DOS
 ----------------------------------
 
diff --git a/nuttx/arch/arm/src/stm32/stm32_flash.c b/nuttx/arch/arm/src/stm32/stm32_flash.c
index 83fcc6172..20b0cfe10 100644
--- a/nuttx/arch/arm/src/stm32/stm32_flash.c
+++ b/nuttx/arch/arm/src/stm32/stm32_flash.c
@@ -35,7 +35,7 @@
 
 /* Provides standard flash access functions, to be used by the  flash mtd driver.
  * The interface is defined in the include/nuttx/progmem.h
- * 
+ *
  * Requirements during write/erase operations on FLASH:
  *  - HSI must be ON.
  *  - Low Power Modes are not permitted during write/erase
@@ -80,7 +80,7 @@ void stm32_flash_unlock(void)
   if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK)
     {
       /* Unlock sequence */
-        
+
       putreg32(FLASH_KEY1, STM32_FLASH_KEYR);
       putreg32(FLASH_KEY2, STM32_FLASH_KEYR);
     }
@@ -112,6 +112,11 @@ uint16_t up_progmem_pagesize(uint16_t page)
 
 int up_progmem_getpage(uint32_t addr)
 {
+  if (addr >= STM32_FLASH_BASE)
+    {
+      addr -= STM32_FLASH_BASE;
+    }
+
   if (addr >= STM32_FLASH_SIZE)
     {
       return -EFAULT;
@@ -131,14 +136,14 @@ int up_progmem_erasepage(uint16_t page)
     }
 
   /* Get flash ready and begin erasing single page */
-    
+
   if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
     {
       return -EPERM;
     }
-    
+
   stm32_flash_unlock();
-        
+
   modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PER);
   putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR);
   modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT);
@@ -146,10 +151,10 @@ int up_progmem_erasepage(uint16_t page)
   while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
 
   modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0);
-    
+
   /* Verify */
-    
-  for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; 
+
+  for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE;
        count; count-=4, addr += 4)
     {
       if (getreg32(addr) != 0xffffffff)
@@ -173,8 +178,8 @@ int up_progmem_ispageerased(uint16_t page)
     }
 
   /* Verify */
-    
-  for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; 
+
+  for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE;
        count; count--, addr++)
     {
       if (getreg8(addr) != 0xff)
@@ -200,6 +205,11 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count)
 
   /* Check for valid address range */
 
+  if (addr >= STM32_FLASH_BASE)
+    {
+      addr -= STM32_FLASH_BASE;
+    }
+
   if ((addr+count) >= STM32_FLASH_SIZE)
     {
       return -EFAULT;
@@ -213,10 +223,10 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count)
     }
 
   stm32_flash_unlock();
-    
+
   modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
-    
-  for (addr += STM32_FLASH_BASE; count; count--, hword++, addr+=2)
+
+  for (addr += STM32_FLASH_BASE; count; count-=2, hword++, addr+=2)
     {
       /* Write half-word and wait to complete */
 
@@ -237,7 +247,6 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count)
           modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
           return -EIO;
         }
-
     }
 
   modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
diff --git a/nuttx/include/nuttx/progmem.h b/nuttx/include/nuttx/progmem.h
index ac5a65940..2da59eab1 100644
--- a/nuttx/include/nuttx/progmem.h
+++ b/nuttx/include/nuttx/progmem.h
@@ -99,7 +99,7 @@ uint16_t up_progmem_pagesize(uint16_t page);
  *   Address to page conversion 
  *
  * Input Parameters:
- *   addr - Address without flash offet (aligned to page0)
+ *   addr - Address with of without flash offset (absolute or aligned to page0)
  *
  * Returned Value:
  *   Page or negative value on error.  The following errors are reported
@@ -165,7 +165,7 @@ int up_progmem_ispageerased(uint16_t page);
  *   the address be aligned inside the page boundaries.
  *
  * Input Parameters:
- *   addr  - Address without flash offet (aligned to page0)
+ *   addr  - Address with or without flash offset (absolute or aligned to page0)
  *   buf   - Pointer to buffer
  *   count - Number of bytes to write *
  *
-- 
cgit v1.2.3


From 470c2e71df47a3ad527afe4b20dbe8988c3f8575 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Sat, 5 Jan 2013 13:19:53 +0000
Subject: Correct some errors in the LPC17xx SYSCON register bit definitions
 (from Rommel Marcello)

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5479 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                            |  2 ++
 nuttx/Documentation/NuttX.html             |  2 +-
 nuttx/Documentation/NuttxPortingGuide.html |  2 +-
 nuttx/README.txt                           |  2 +-
 nuttx/TODO                                 |  2 +-
 nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h  | 16 ++++++++--------
 nuttx/tools/configure.c                    | 22 +++++++---------------
 nuttx/tools/configure.sh                   | 21 +++++++--------------
 8 files changed, 28 insertions(+), 41 deletions(-)

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 710ffdceb..cce091587 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3871,3 +3871,5 @@
 	  thin layer that execuates configure.exe if it is available. If
 	  configure.exe is not available, then configure.bat will attempt
 	  to build it first.
+	* arch/arm/src/lpc17xx/lpc17_syscon.h:  Correct some typos in bit
+	  definitions (from Rommel Marcelo).
diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html
index dc454c0b6..876aa2a0a 100644
--- a/nuttx/Documentation/NuttX.html
+++ b/nuttx/Documentation/NuttX.html
@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: December 28, 2012</p>
+      <p>Last Updated: January 4, 2012</p>
     </td>
   </tr>
 </table>
diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html
index 559253d45..24b4852e0 100644
--- a/nuttx/Documentation/NuttxPortingGuide.html
+++ b/nuttx/Documentation/NuttxPortingGuide.html
@@ -12,7 +12,7 @@
       <h1><big><font color="#3c34ec">
         <i>NuttX RTOS Porting Guide</i>
       </font></big></h1>
-      <p>Last Updated: December 18, 2012</p>
+      <p>Last Updated: January 4, 2012</p>
     </td>
   </tr>
 </table>
diff --git a/nuttx/README.txt b/nuttx/README.txt
index 717c129b0..0348f7f30 100644
--- a/nuttx/README.txt
+++ b/nuttx/README.txt
@@ -687,7 +687,7 @@ Native Windows Build
   Build Tools.  The build still relies on some Unix-like commands.  I use
   the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/.
 
-  Host Compiler:  I use the MingGW compiler which can be downloaded from
+  Host Compiler:  I use the MingGW GCC compiler which can be downloaded from
   http://www.mingw.org/.  If you are using GNUWin32, then it is recommended
   the you not install the optional MSYS components as there may be conflicts.
 
diff --git a/nuttx/TODO b/nuttx/TODO
index 4a70e577f..02100e97e 100644
--- a/nuttx/TODO
+++ b/nuttx/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated December 20, 2012)
+NuttX TODO List (Last updated January 4, 2013)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 This file summarizes known NuttX bugs, limitations, inconsistencies with 
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h
index ce8654645..3b9c32526 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h
@@ -242,29 +242,29 @@
 
 #define SYSCON_PLL0STAT_MSEL_SHIFT    (0)         /* Bit 0-14: PLL0 Multiplier value readback */
 #define SYSCON_PLL0STAT_MSEL_MASK     (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT)
-                                                  /* Bit 15:  Reserved */
+                                                  /* Bit 15: Reserved */
 #define SYSCON_PLL0STAT_NSEL_SHIFT    (16)        /* Bit 16-23: PLL0 Pre-Divider value readback */
 #define SYSCON_PLL0STAT_NSEL_MASK     (0xff << SYSCON_PLL0STAT_NSEL_SHIFT)
 #define SYSCON_PLL0STAT_PLLE          (1 << 24)   /* Bit 24: PLL0 enable readback */
 #define SYSCON_PLL0STAT_PLLC          (1 << 25)   /* Bit 25: PLL0 connect readback */
 #define SYSCON_PLL0STAT_PLOCK         (1 << 26)   /* Bit 26: PLL0 lock status */
-                                                  /* Bits 27-31:  Reserved */
+                                                  /* Bits 27-31: Reserved */
 /* PLL1 Status register */
 
-#define SYSCON_PLL1STAT_MSEL_SHIFT    (0)         /* Bit 0-4: PLL01Multiplier value readback */
+#define SYSCON_PLL1STAT_MSEL_SHIFT    (0)         /* Bit 0-4: PLL1 Multiplier value readback */
 #define SYSCON_PLL1STAT_MSEL_MASK     (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT)
 #define SYSCON_PLL1STAT_NSEL_SHIFT    (5)         /* Bit 5-6: PLL1 Pre-Divider value readback */
 #define SYSCON_PLL1STAT_NSEL_MASK     (3 << SYSCON_PLL1STAT_NSEL_SHIFT)
                                                   /* Bit 7:  Reserved */
-#define SYSCON_PLL1STAT_PLLE          (1 << 24)   /* Bit 8: PLL1 enable readback */
-#define SYSCON_PLL1STAT_PLLC          (1 << 25)   /* Bit 9: PLL1 connect readback */
-#define SYSCON_PLL1STAT_PLOCK         (1 << 26)   /* Bit 10: PLL1 lock status */
-                                                  /* Bits 11-31:  Reserved */
+#define SYSCON_PLL1STAT_PLLE          (1 << 8)    /* Bit 8:  PLL1 enable readback */
+#define SYSCON_PLL1STAT_PLLC          (1 << 9)    /* Bit 9:  PLL1 connect readback */
+#define SYSCON_PLL1STAT_PLOCK         (1 << 10)   /* Bit 10: PLL1 lock status */
+                                                  /* Bits 11-31: Reserved */
 /* PLL0/1 Feed register */
 
 #define SYSCON_PLLFEED_SHIFT          (0)         /* Bit 0-7: PLL0/1 feed sequence */
 #define SYSCON_PLLFEED_MASK           (0xff << SYSCON_PLLFEED_SHIFT)
-                                                  /* Bits 8-31:  Reserved */
+                                                  /* Bits 8-31: Reserved */
 /* Clocking and power control -- Clock dividers */
 /* CPU Clock Configuration register */
 
diff --git a/nuttx/tools/configure.c b/nuttx/tools/configure.c
index f189f5b98..eb8268f19 100644
--- a/nuttx/tools/configure.c
+++ b/nuttx/tools/configure.c
@@ -549,7 +549,7 @@ static void check_configuration(void)
     }
 }
 
-static void copy_file(const char *srcpath, const char *destpath)
+static void copy_file(const char *srcpath, const char *destpath, mode_t mode)
 {
   int nbytesread;
   int nbyteswritten;
@@ -567,7 +567,7 @@ static void copy_file(const char *srcpath, const char *destpath)
 
   /* Now open the destination for writing*/
 
-  wrfd = open(destpath, O_WRONLY|O_CREAT|O_TRUNC, 0666);
+  wrfd = open(destpath, O_WRONLY|O_CREAT|O_TRUNC, mode);
   if (wrfd < 0)
     {
       fprintf(stderr, "ERROR: Failed to open %s for writing: %s\n", destpath, strerror(errno));
@@ -638,13 +638,13 @@ static void configure(void)
   snprintf(g_buffer, BUFFER_SIZE, "%s%c.config", g_topdir, g_delim);
   destconfig = strdup(g_buffer);
   debug("configure: Copying from %s to %s\n", g_srcdefconfig, destconfig);
-  copy_file(g_srcdefconfig, destconfig);
+  copy_file(g_srcdefconfig, destconfig, 0644);
 
   /* Copy the Make.defs file as Make.defs */
 
   snprintf(g_buffer, BUFFER_SIZE, "%s%cMake.defs", g_topdir, g_delim);
   debug("configure: Copying from %s to %s\n", g_srcmakedefs, g_buffer);
-  copy_file(g_srcmakedefs, g_buffer);
+  copy_file(g_srcmakedefs, g_buffer, 0644);
 
   /* Copy the setenv.sh file if have one and need one */
 
@@ -652,15 +652,7 @@ static void configure(void)
     {
       snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.sh", g_topdir, g_delim);
       debug("configure: Copying from %s to %s\n", g_srcsetenvsh, g_buffer);
-      copy_file(g_srcsetenvsh, g_buffer);
-
-      /* Mark the file executable */
-
-      if (chmod(g_buffer, 0777) != 0)
-        {
-          fprintf(stderr, "ERROR: Failed to make setenv.sh executable: %s\n", strerror(errno));
-          exit(EXIT_FAILURE);
-        }
+      copy_file(g_srcsetenvsh, g_buffer, 0755);
     }
   
   /* Copy the setenv.bat file if have one and need one */
@@ -669,7 +661,7 @@ static void configure(void)
     {
       snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.bat", g_topdir, g_delim);
       debug("configure: Copying from %s to %s\n", g_srcsetenvbat, g_buffer);
-      copy_file(g_srcsetenvbat, g_buffer);
+      copy_file(g_srcsetenvbat, g_buffer, 0644);
     }
 
   /* Copy the appconfig file to ../apps/.config if have one and need one */
@@ -678,7 +670,7 @@ static void configure(void)
     {
       snprintf(g_buffer, BUFFER_SIZE, "%s%c.config", g_apppath, g_delim);
       debug("configure: Copying from %s to %s\n", g_srcappconfig, g_buffer);
-      copy_file(g_srcappconfig, g_buffer);
+      copy_file(g_srcappconfig, g_buffer, 0644);
     }
 
   /* If we did not use the CONFIG_APPS_DIR that was in the defconfig config file,
diff --git a/nuttx/tools/configure.sh b/nuttx/tools/configure.sh
index ffa997178..89f2e2fbc 100755
--- a/nuttx/tools/configure.sh
+++ b/nuttx/tools/configure.sh
@@ -125,7 +125,6 @@ else
 fi
 
 src_config="${configpath}/defconfig"
-tmp_config="${TOPDIR}/.configX"
 dest_config="${TOPDIR}/.config"
 
 if [ ! -r "${src_config}" ]; then
@@ -201,7 +200,7 @@ if [ "X${have_setenv}" = "Xy" ]; then
     { echo "Failed to copy ${src_setenv}" ; exit 8 ; }
   chmod 755 "${dest_setenv}"
 fi
-install "${src_config}" "${tmp_config}" || \
+install "${src_config}" "${dest_config}" || \
   { echo "Failed to copy \"${src_config}\"" ; exit 9 ; }
 
 # If we did not use the CONFIG_APPS_DIR that was in the defconfig config file,
@@ -209,14 +208,14 @@ install "${src_config}" "${tmp_config}" || \
 # file
 
 if [ "X${defappdir}" = "Xy" ]; then
-  sed -i -e "/^CONFIG_APPS_DIR/d" "${tmp_config}"
-  echo "" >> "${tmp_config}"
-  echo "# Application configuration" >> "${tmp_config}"
-  echo "" >> "${tmp_config}"
+  sed -i -e "/^CONFIG_APPS_DIR/d" "${dest_config}"
+  echo "" >> "${dest_config}"
+  echo "# Application configuration" >> "${dest_config}"
+  echo "" >> "${dest_config}"
   if [ "X${winnative}" = "Xy" ]; then
-    echo "CONFIG_APPS_DIR=\"$winappdir\"" >> "${tmp_config}"
+    echo "CONFIG_APPS_DIR=\"$winappdir\"" >> "${dest_config}"
   else
-    echo "CONFIG_APPS_DIR=\"$posappdir\"" >> "${tmp_config}"
+    echo "CONFIG_APPS_DIR=\"$posappdir\"" >> "${dest_config}"
   fi
 fi 
 
@@ -232,9 +231,3 @@ if [ ! -z "${appdir}" -a "X${newconfig}" != "Xy" ]; then
       { echo "Failed to copy ${configpath}/appconfig" ; exit 10 ; }
   fi
 fi
-
-# install the final .configX only if it differs from any existing
-# .config file.
-
-install "${tmp_config}" "${dest_config}"
-rm -f "${tmp_config}"
-- 
cgit v1.2.3


From 876062fe3a2b6273855b77c0ed1c9d0cbcfc43c6 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Mon, 7 Jan 2013 15:20:21 +0000
Subject: Implement a simple vfork().  ARM only for now

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5486 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                       |   3 +-
 nuttx/arch/arm/src/arm/up_vfork.S     |  92 +++++++++++++++++++++++
 nuttx/arch/arm/src/armv7-m/up_vfork.S |  96 ++++++++++++++++++++++++
 nuttx/arch/arm/src/c5471/Make.defs    |   6 +-
 nuttx/arch/arm/src/calypso/Make.defs  |   6 +-
 nuttx/arch/arm/src/common/up__vfork.c | 134 ++++++++++++++++++++++++++++++++++
 nuttx/arch/arm/src/dm320/Make.defs    |   6 +-
 nuttx/arch/arm/src/imx/Make.defs      |   6 +-
 nuttx/arch/arm/src/kinetis/Make.defs  |   8 +-
 nuttx/arch/arm/src/lm3s/Make.defs     |   8 +-
 nuttx/arch/arm/src/lpc17xx/Make.defs  |   7 +-
 nuttx/arch/arm/src/lpc214x/Make.defs  |   7 +-
 nuttx/arch/arm/src/lpc2378/Make.defs  |  15 ++--
 nuttx/arch/arm/src/lpc31xx/Make.defs  |   4 +-
 nuttx/arch/arm/src/lpc43xx/Make.defs  |  10 ++-
 nuttx/arch/arm/src/sam3u/Make.defs    |   7 +-
 nuttx/arch/arm/src/stm32/Make.defs    |   8 +-
 nuttx/arch/arm/src/str71x/Make.defs   |  15 ++--
 nuttx/include/unistd.h                |   3 +-
 19 files changed, 389 insertions(+), 52 deletions(-)
 create mode 100644 nuttx/arch/arm/src/arm/up_vfork.S
 create mode 100644 nuttx/arch/arm/src/armv7-m/up_vfork.S
 create mode 100644 nuttx/arch/arm/src/common/up__vfork.c

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index f4f697563..e2d8a586b 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3878,5 +3878,6 @@
 	* sched/os_bringup.c:  Remove support for CONFIG_BUILTIN_APP_START.
 	  This is not really a useful feature and creates a violation of the
 	  OS layered architecture.
-
+	* include/unistd.h, arch/arch/src/*:  Implement a simple vfork().
+	  On initial checkin, this API is available only for ARM platforms.
 
diff --git a/nuttx/arch/arm/src/arm/up_vfork.S b/nuttx/arch/arm/src/arm/up_vfork.S
new file mode 100644
index 000000000..23e975c30
--- /dev/null
+++ b/nuttx/arch/arm/src/arm/up_vfork.S
@@ -0,0 +1,92 @@
+/************************************************************************************
+ * arch/arm/src/arm/up_vfork.S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.file	"up_vfork.S"
+	.globl	__vfork
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: vfork
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the behavior is
+ *   undefined if the process created by vfork() either modifies any data other than
+ *   a variable of type pid_t used to store the return value from vfork(), or returns
+ *   from the function in which vfork() was called, or calls any other function before
+ *   successfully calling _exit() or one of the exec family of functions. 
+ *
+ *   This thin layer implements vfork by simply calling __vfork() with the vfork()
+ *   return address as an argument.
+ *
+ * Input Paremeters:
+ *   None
+ *
+ * Return:
+ *   Upon successful completion, vfork() returns 0 to the child process and returns
+ *   the process ID of the child process to the parent process. Otherwise, -1 is
+ *   returned to the parent, no child process is created, and errno is set to
+ *   indicate the error. 
+ *
+ ************************************************************************************/
+
+	.globl	vfork
+	.type	vfork, function
+vfork:
+
+    /* I know, I could have used the GCC's return address builtin and done this all
+     * in C.  But this works even if there is no builtin.
+     */
+
+	mov		r0, lr
+	b		__vfork
+	.size	vfork, .-vfork
+	.end
diff --git a/nuttx/arch/arm/src/armv7-m/up_vfork.S b/nuttx/arch/arm/src/armv7-m/up_vfork.S
new file mode 100644
index 000000000..65ccc4535
--- /dev/null
+++ b/nuttx/arch/arm/src/armv7-m/up_vfork.S
@@ -0,0 +1,96 @@
+/************************************************************************************
+ * arch/arm/src/armv7-m/up_vfork.S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.syntax	unified
+	.thumb
+	.file	"up_vfork.S"
+	.globl	__vfork
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: vfork
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the behavior is
+ *   undefined if the process created by vfork() either modifies any data other than
+ *   a variable of type pid_t used to store the return value from vfork(), or returns
+ *   from the function in which vfork() was called, or calls any other function before
+ *   successfully calling _exit() or one of the exec family of functions. 
+ *
+ *   This thin layer implements vfork by simply calling __vfork() with the vfork()
+ *   return address as an argument.
+ *
+ * Input Paremeters:
+ *   None
+ *
+ * Return:
+ *   Upon successful completion, vfork() returns 0 to the child process and returns
+ *   the process ID of the child process to the parent process. Otherwise, -1 is
+ *   returned to the parent, no child process is created, and errno is set to
+ *   indicate the error. 
+ *
+ ************************************************************************************/
+
+	.thumb_func
+	.globl	vfork
+	.type	vfork, function
+vfork:
+
+    /* I know, I could have used the GCC's return address builtin and done this all
+     * in C.  But this works even if there is no builtin.
+     */
+
+	mov		r0, lr
+	b		__vfork
+	.size	vfork, .-vfork
+	.end
+
diff --git a/nuttx/arch/arm/src/c5471/Make.defs b/nuttx/arch/arm/src/c5471/Make.defs
index 2bc396fd3..89c3aaf0b 100644
--- a/nuttx/arch/arm/src/c5471/Make.defs
+++ b/nuttx/arch/arm/src/c5471/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # c5471/Make.defs
 #
-#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -35,14 +35,14 @@
 
 HEAD_ASRC	= up_nommuhead.S
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 		  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \
 		  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
 		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
 		  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c
+		  up_undefinedinsn.c up_usestack.c up__vfork.c
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
diff --git a/nuttx/arch/arm/src/calypso/Make.defs b/nuttx/arch/arm/src/calypso/Make.defs
index 4b53c3b7c..957d4e677 100644
--- a/nuttx/arch/arm/src/calypso/Make.defs
+++ b/nuttx/arch/arm/src/calypso/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # calypso/Make.defs
 #
-#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 #   Copyright (C) 2011 Stefan Richter. All rights reserved.
@@ -39,14 +39,14 @@
 HEAD_ASRC = calypso_head.S
 
 CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
-            up_nommuhead.S
+            up_nommuhead.S up_vfork.S
 CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
             up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \
             up_exit.c up_idle.c up_initialstate.c up_initialize.c \
             up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
             up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
             up_sigdeliver.c up_syscall.c up_unblocktask.c \
-            up_undefinedinsn.c up_usestack.c calypso_power.c
+            up_undefinedinsn.c up_usestack.c calypso_power.c up__vfork.c
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
diff --git a/nuttx/arch/arm/src/common/up__vfork.c b/nuttx/arch/arm/src/common/up__vfork.c
new file mode 100644
index 000000000..a1081faa8
--- /dev/null
+++ b/nuttx/arch/arm/src/common/up__vfork.c
@@ -0,0 +1,134 @@
+/****************************************************************************
+ * arch/arm/src/common/up__vfork
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sched.h>
+
+#include <nuttx/sched.h>
+
+#include "os_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
+ * floating point, the stack must be aligned to 8-byte addresses.
+ */
+
+#ifndef CONFIG_STACK_ALIGNMENT
+
+/* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
+ * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
+ */
+
+#  ifdef __ARM_EABI__
+#    define CONFIG_STACK_ALIGNMENT 8
+#  else
+#    define CONFIG_STACK_ALIGNMENT 4
+#  endif
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: __vfork
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the
+ *   behavior is undefined if the process created by vfork() either modifies
+ *   any data other than a variable of type pid_t used to store the return
+ *   value from vfork(), or returns from the function in which vfork() was
+ *   called, or calls any other function before successfully calling _exit()
+ *   or one of the exec family of functions. 
+ *
+ *   This thin layer starts the vfork child by simply spawning a new thread
+ *   that begins at the return address of vfork().
+ *
+ * Input Paremeters:
+ *   retaddr - The return address of vfork()
+ *
+ * Return:
+ *   Upon successful completion, vfork() returns 0 to the child process and
+ *   returns the process ID of the child process to the parent process.
+ *   Otherwise, -1 is returned to the parent, no child process is created,
+ *   and errno is set to indicate the error. 
+ *
+ ****************************************************************************/
+
+pid_t __vfork(uint32_t retaddr)
+{
+  FAR _TCB *parent = (FAR _TCB *)g_readytorun.head;
+  size_t stacksize;
+  int priority;
+
+  /* Get the size of the parent task's stack.  Due to alignment operations,
+   * the adjusted stack size may be smaller than the stack size originally
+   * requrested.
+   */
+
+  stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1;
+
+  /* Get the current priority of the parent task */
+
+#ifdef CONFIG_PRIORITY_INHERITANCE
+  priority = parent->base_priority;  /* "Normal," unboosted priority */
+#else
+  priority = parent->sched_priority;  /* Current priority */
+#endif
+
+ /* Start the child thread at the vfork return address.  TASK_CREATE will
+  * return the PID of the new thread.  Otherwise a negative value will be
+  * returned and the errno will be set appropriately.
+  *
+  * When the registers are initialized, the return value in R0 should be
+  * cleared to zero, providing the indication to the newly started child
+  * thread.
+  */
+
+  return TASK_CREATE("init", priority, stacksize, (main_t)retaddr,
+                     (const char **)NULL);
+}
diff --git a/nuttx/arch/arm/src/dm320/Make.defs b/nuttx/arch/arm/src/dm320/Make.defs
index 9087708ef..52e65c0e8 100644
--- a/nuttx/arch/arm/src/dm320/Make.defs
+++ b/nuttx/arch/arm/src/dm320/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # dm320/Make.defs
 #
-#   Copyright (C) 2007, 2010 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007, 2010, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -36,14 +36,14 @@
 HEAD_ASRC	= up_head.S
 
 CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
-		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S
+		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \
 		  up_initialize.c up_initialstate.c up_interruptcontext.c \
 		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
 		  up_reprioritizertr.c up_schedulesigaction.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c
+		  up_undefinedinsn.c up_usestack.c up__vfork.c
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
diff --git a/nuttx/arch/arm/src/imx/Make.defs b/nuttx/arch/arm/src/imx/Make.defs
index a1c2e72e6..a7c0ceebd 100644
--- a/nuttx/arch/arm/src/imx/Make.defs
+++ b/nuttx/arch/arm/src/imx/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/imx/Make.defs
 #
-#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -36,14 +36,14 @@
 HEAD_ASRC	= up_head.S
 
 CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
-		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S
+		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \
 		  up_initialize.c up_initialstate.c up_interruptcontext.c \
 		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
 		  up_reprioritizertr.c up_schedulesigaction.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c
+		  up_undefinedinsn.c up_usestack.c up__vfork.c
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
diff --git a/nuttx/arch/arm/src/kinetis/Make.defs b/nuttx/arch/arm/src/kinetis/Make.defs
index 65bc7b465..bad2946e2 100644
--- a/nuttx/arch/arm/src/kinetis/Make.defs
+++ b/nuttx/arch/arm/src/kinetis/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/kinetis/Make.defs
 #
-#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -39,14 +39,16 @@ HEAD_ASRC	= kinetis_vectors.S
 
 # Common ARM and Cortex-M3 files
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
+			  up_vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c up_initialize.c \
 			  up_memfault.c up_initialstate.c up_interruptcontext.c \
 			  up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
 			  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
 			  up_releasepending.c up_sigdeliver.c up_unblocktask.c up_usestack.c \
-			  up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c
+			  up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c \
+			  up__vfork.c
 
 ifeq ($(CONFIG_ARCH_MEMCPY),y)
 CMN_ASRCS	+= up_memcpy.S
diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs
index 8d2918027..c745e1953 100644
--- a/nuttx/arch/arm/src/lm3s/Make.defs
+++ b/nuttx/arch/arm/src/lm3s/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/lm3s/Make.defs
 #
-#   Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -35,14 +35,16 @@
 
 HEAD_ASRC	= lm3s_vectors.S
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
+			  up_vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
 			  up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \
 			  up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
 			  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
 			  up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
-			  up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
+			  up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \
+			  up__vfork.c
 
 ifeq ($(CONFIG_ARCH_MEMCPY),y)
 CMN_ASRCS	+= up_memcpy.S
diff --git a/nuttx/arch/arm/src/lpc17xx/Make.defs b/nuttx/arch/arm/src/lpc17xx/Make.defs
index c7ef4a147..1ea0183a1 100644
--- a/nuttx/arch/arm/src/lpc17xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc17xx/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/lpc17xx/Make.defs
 #
-#   Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -39,14 +39,15 @@ HEAD_ASRC	= lpc17_vectors.S
 
 # Common ARM and Cortex-M3 files
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
+			  up_vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 			  up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c \
 			  up_initialstate.c up_interruptcontext.c up_modifyreg8.c \
 			  up_modifyreg16.c up_modifyreg32.c up_releasepending.c \
 			  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
 			  up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \
-			  up_hardfault.c up_svcall.c up_checkstack.c
+			  up_hardfault.c up_svcall.c up_checkstack.c up__vfork.c
 
 ifeq ($(CONFIG_ARCH_MEMCPY),y)
 CMN_ASRCS	+= up_memcpy.S
diff --git a/nuttx/arch/arm/src/lpc214x/Make.defs b/nuttx/arch/arm/src/lpc214x/Make.defs
index ae5ed15fb..6821d512b 100644
--- a/nuttx/arch/arm/src/lpc214x/Make.defs
+++ b/nuttx/arch/arm/src/lpc214x/Make.defs
@@ -1,7 +1,7 @@
 ##############################################################################
 # lpc214x/Make.defs
 #
-#   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007, 2008, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -35,13 +35,14 @@
 
 HEAD_ASRC	= lpc214x_head.S
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
+			  up_vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 		  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
 		  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
 		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
 		  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up_lowputs.c
+		  up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS	+= up_schedulesigaction.c up_sigdeliver.c
diff --git a/nuttx/arch/arm/src/lpc2378/Make.defs b/nuttx/arch/arm/src/lpc2378/Make.defs
index 4fe75d924..3d3c15926 100644
--- a/nuttx/arch/arm/src/lpc2378/Make.defs
+++ b/nuttx/arch/arm/src/lpc2378/Make.defs
@@ -1,7 +1,7 @@
 ##############################################################################
 # lpc23xx/Make.defs
 #
-#   Copyright (C) 2010 Rommel Marcelo. All rights reserved.
+#   Copyright (C) 2010, 2013 Rommel Marcelo. All rights reserved.
 #   Author: Rommel Marcelo
 #
 # This file is part of the NuttX RTOS and based on the lpc2148 port:
@@ -40,13 +40,14 @@
 
 HEAD_ASRC	= lpc23xx_head.S
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
+			  up_vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
-		  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
-		  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
-		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
-		  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up_lowputs.c
+			  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
+			  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
+			  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
+			  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
+			  up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS	+= up_schedulesigaction.c up_sigdeliver.c
diff --git a/nuttx/arch/arm/src/lpc31xx/Make.defs b/nuttx/arch/arm/src/lpc31xx/Make.defs
index db63563ef..b3a9746b4 100644
--- a/nuttx/arch/arm/src/lpc31xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc31xx/Make.defs
@@ -36,7 +36,7 @@
 HEAD_ASRC	= up_head.S
 
 CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
-		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S
+		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \
 		  up_initialize.c up_initialstate.c up_interruptcontext.c \
@@ -44,7 +44,7 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
 		  up_reprioritizertr.c up_schedulesigaction.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c
+		  up_undefinedinsn.c up_usestack.c up__vfork.c
 
 ifeq ($(CONFIG_PAGING),y)
 CMN_CSRCS	+= up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c
diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs
index cd78ddd5b..211f9bee3 100644
--- a/nuttx/arch/arm/src/lpc43xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc43xx/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/lpc43xx/Make.defs
 #
-#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -33,16 +33,18 @@
 #
 ############################################################################
 
-HEAD_ASRC  = 
+HEAD_ASRC  =
 
 CMN_ASRCS  = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c
+CMN_ASRCS += up_vfork.S
+
+CMN_CSRCS  = up_assert.c up_blocktask.c up_copystate.c
 CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
 CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
 CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
 CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
 CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c
-CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
+CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c up__vfork.c
 
 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 CMN_ASRCS += up_exception.S
diff --git a/nuttx/arch/arm/src/sam3u/Make.defs b/nuttx/arch/arm/src/sam3u/Make.defs
index daa129169..4682ea83d 100644
--- a/nuttx/arch/arm/src/sam3u/Make.defs
+++ b/nuttx/arch/arm/src/sam3u/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/sam3u/Make.defs
 #
-#   Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -39,14 +39,15 @@ HEAD_ASRC	= sam3u_vectors.S
 
 # Common ARM and Cortex-M3 files
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
+			  up_vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 			  up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c \
 			  up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c \
 			  up_modifyreg16.c up_modifyreg32.c up_releasepending.c \
 			  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
 			  up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \
-			  up_hardfault.c up_svcall.c
+			  up_hardfault.c up_svcall.c up__vfork.c
 
 # Configuration-dependent common files
 
diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs
index 1e6c0c401..89c291791 100644
--- a/nuttx/arch/arm/src/stm32/Make.defs
+++ b/nuttx/arch/arm/src/stm32/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/stm32/Make.defs
 #
-#   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -39,14 +39,16 @@ else
 HEAD_ASRC	= stm32_vectors.S
 endif
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
+			  up_vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c \
 			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
 			  up_initialize.c up_initialstate.c up_interruptcontext.c \
 			  up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
 			  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
 			  up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \
-			  up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
+			  up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c \
+			  up_svcall.c up__vfork.c
 
 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 CMN_ASRCS	+= up_exception.S
diff --git a/nuttx/arch/arm/src/str71x/Make.defs b/nuttx/arch/arm/src/str71x/Make.defs
index 32eaddcdb..3612950a6 100644
--- a/nuttx/arch/arm/src/str71x/Make.defs
+++ b/nuttx/arch/arm/src/str71x/Make.defs
@@ -1,7 +1,7 @@
 ##############################################################################
 # arch/arm/src/str71x/Make.defs
 #
-#   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2008, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -35,13 +35,14 @@
 
 HEAD_ASRC	= str71x_head.S
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
+			  up_vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
-		  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
-		  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
-		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
-		  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up_lowputs.c
+			  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
+			  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
+			  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
+			  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
+			  up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS	+= up_schedulesigaction.c up_sigdeliver.c
diff --git a/nuttx/include/unistd.h b/nuttx/include/unistd.h
index 681ce9e63..ddb6880f4 100644
--- a/nuttx/include/unistd.h
+++ b/nuttx/include/unistd.h
@@ -1,7 +1,7 @@
 /****************************************************************************
  * include/unistd.h
  *
- *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -129,6 +129,7 @@ EXTERN int       optopt; /* unrecognized option character */
 
 /* Task Control Interfaces */
 
+EXTERN pid_t   vfork(void);
 EXTERN pid_t   getpid(void);
 EXTERN void    _exit(int status) noreturn_function;
 EXTERN unsigned int sleep(unsigned int seconds);
-- 
cgit v1.2.3


From a5f001189e1a056be275e1d736e38893f96cd395 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Mon, 7 Jan 2013 19:35:47 +0000
Subject: This initial vfork() check-in was a little pollyanna-ish

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5487 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/arch/arm/src/arm/up_vfork.S     |  92 ------------
 nuttx/arch/arm/src/arm/vfork.S        | 134 +++++++++++++++++
 nuttx/arch/arm/src/armv7-m/up_vfork.S |  96 ------------
 nuttx/arch/arm/src/armv7-m/vfork.S    | 138 ++++++++++++++++++
 nuttx/arch/arm/src/c5471/Make.defs    |   4 +-
 nuttx/arch/arm/src/calypso/Make.defs  |   4 +-
 nuttx/arch/arm/src/common/up__vfork.c | 134 -----------------
 nuttx/arch/arm/src/common/up_vfork.c  | 196 +++++++++++++++++++++++++
 nuttx/arch/arm/src/common/up_vfork.h  |  82 +++++++++++
 nuttx/arch/arm/src/dm320/Make.defs    |   4 +-
 nuttx/arch/arm/src/imx/Make.defs      |   4 +-
 nuttx/arch/arm/src/kinetis/Make.defs  |   4 +-
 nuttx/arch/arm/src/lm3s/Make.defs     |   4 +-
 nuttx/arch/arm/src/lpc17xx/Make.defs  |   4 +-
 nuttx/arch/arm/src/lpc214x/Make.defs  |   4 +-
 nuttx/arch/arm/src/lpc2378/Make.defs  |   4 +-
 nuttx/arch/arm/src/lpc31xx/Make.defs  |   4 +-
 nuttx/arch/arm/src/lpc43xx/Make.defs  |   4 +-
 nuttx/arch/arm/src/sam3u/Make.defs    |   4 +-
 nuttx/arch/arm/src/stm32/Make.defs    |   4 +-
 nuttx/arch/arm/src/str71x/Make.defs   |   4 +-
 nuttx/include/nuttx/arch.h            |   2 +-
 nuttx/include/nuttx/sched.h           |  26 ++++
 nuttx/sched/Makefile                  |   2 +-
 nuttx/sched/sched_setuptaskfiles.c    |   3 +-
 nuttx/sched/task_create.c             |   2 +
 nuttx/sched/task_vfork.c              | 266 ++++++++++++++++++++++++++++++++++
 27 files changed, 876 insertions(+), 353 deletions(-)
 delete mode 100644 nuttx/arch/arm/src/arm/up_vfork.S
 create mode 100644 nuttx/arch/arm/src/arm/vfork.S
 delete mode 100644 nuttx/arch/arm/src/armv7-m/up_vfork.S
 create mode 100644 nuttx/arch/arm/src/armv7-m/vfork.S
 delete mode 100644 nuttx/arch/arm/src/common/up__vfork.c
 create mode 100644 nuttx/arch/arm/src/common/up_vfork.c
 create mode 100644 nuttx/arch/arm/src/common/up_vfork.h
 create mode 100644 nuttx/sched/task_vfork.c

(limited to 'nuttx/arch')

diff --git a/nuttx/arch/arm/src/arm/up_vfork.S b/nuttx/arch/arm/src/arm/up_vfork.S
deleted file mode 100644
index 23e975c30..000000000
--- a/nuttx/arch/arm/src/arm/up_vfork.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/************************************************************************************
- * arch/arm/src/arm/up_vfork.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Global Symbols
- ************************************************************************************/
-
-	.file	"up_vfork.S"
-	.globl	__vfork
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: vfork
- *
- * Description:
- *   The vfork() function has the same effect as fork(), except that the behavior is
- *   undefined if the process created by vfork() either modifies any data other than
- *   a variable of type pid_t used to store the return value from vfork(), or returns
- *   from the function in which vfork() was called, or calls any other function before
- *   successfully calling _exit() or one of the exec family of functions. 
- *
- *   This thin layer implements vfork by simply calling __vfork() with the vfork()
- *   return address as an argument.
- *
- * Input Paremeters:
- *   None
- *
- * Return:
- *   Upon successful completion, vfork() returns 0 to the child process and returns
- *   the process ID of the child process to the parent process. Otherwise, -1 is
- *   returned to the parent, no child process is created, and errno is set to
- *   indicate the error. 
- *
- ************************************************************************************/
-
-	.globl	vfork
-	.type	vfork, function
-vfork:
-
-    /* I know, I could have used the GCC's return address builtin and done this all
-     * in C.  But this works even if there is no builtin.
-     */
-
-	mov		r0, lr
-	b		__vfork
-	.size	vfork, .-vfork
-	.end
diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S
new file mode 100644
index 000000000..f0fe17f73
--- /dev/null
+++ b/nuttx/arch/arm/src/arm/vfork.S
@@ -0,0 +1,134 @@
+/************************************************************************************
+ * arch/arm/src/arm/vfork.S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "up_vfork.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.file	"vfork.S"
+	.globl	task_vfork
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: vfork
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the behavior is
+ *   undefined if the process created by vfork() either modifies any data other than
+ *   a variable of type pid_t used to store the return value from vfork(), or returns
+ *   from the function in which vfork() was called, or calls any other function before
+ *   successfully calling _exit() or one of the exec family of functions. 
+ *
+ *   This thin layer implements vfork by simply calling task_vfork() with the vfork()
+ *   context as an argument.  The overall sequence is:
+ *
+ *   1) User code calls vfork().  vfork() collects context information and
+ *      transfers control up up_vfork().
+ *   2) up_vfork()and calls task_vforksetup().
+ *   3) task_vforksetup() allocates and configures the child task's TCB.  This
+ *      consists of:
+ *      - Allocation of the child task's TCB.
+ *      - Initialization of file descriptors and streams
+ *      - Configuration of environment variables
+ *      - Setup the intput parameters for the task.
+ *      - Initialization of the TCB (including call to up_initial_state()
+ *   4) up_vfork() provides any additional operating context. up_vfork must:
+ *      - Allocate and initialize the stack
+ *      - Initialize special values in any CPU registers that were not
+ *        already configured by up_initial_state()
+ *   5) up_vfork() then calls task_vforkstart()
+ *   6) task_vforkstart() then executes the child thread.
+ *
+ * Input Paremeters:
+ *   None
+ *
+ * Return:
+ *   Upon successful completion, vfork() returns 0 to the child process and returns
+ *   the process ID of the child process to the parent process. Otherwise, -1 is
+ *   returned to the parent, no child process is created, and errno is set to
+ *   indicate the error. 
+ *
+ ************************************************************************************/
+
+	.globl	vfork
+	.type	vfork, function
+vfork:
+	/* Create a stack frame */
+
+	mov		r0, sp					/* Save the value of the stack frame on entry */
+	sub		sp, sp, #VFORK_SIZEOF	/* Allocate the structure on the stack */
+
+	/* Save the volatile registers */
+
+	str		r4, [sp, #VFORK_R4_OFFSET]
+	str		r5, [sp, #VFORK_R5_OFFSET]
+	str		r6, [sp, #VFORK_R6_OFFSET]
+	str		r7, [sp, #VFORK_R7_OFFSET]
+	str		r8, [sp, #VFORK_R8_OFFSET]
+	str		r9, [sp, #VFORK_R9_OFFSET]
+	str		r10, [sp, #VFORK_R10_OFFSET]
+
+	/* Save the frame pointer, stack pointer, and return address */
+
+	str		fp, [sp, #VFORK_FP_OFFSET]
+	str		r0, [sp, #VFORK_SP_OFFSET]
+	str		lr, [sp, #VFORK_LR_OFFSET]
+
+	/* Then, call task_vfork(), passing it a pointer to the stack structure */
+
+	mov		r0, sp
+	bl		task_vfork
+
+	/* Release the stack data and return the value returned by task_vfork */
+
+	add		sp, sp, #VFORK_SIZEOF
+	mov		pc, lr
+	.size	vfork, .-vfork
+	.end
diff --git a/nuttx/arch/arm/src/armv7-m/up_vfork.S b/nuttx/arch/arm/src/armv7-m/up_vfork.S
deleted file mode 100644
index 65ccc4535..000000000
--- a/nuttx/arch/arm/src/armv7-m/up_vfork.S
+++ /dev/null
@@ -1,96 +0,0 @@
-/************************************************************************************
- * arch/arm/src/armv7-m/up_vfork.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Global Symbols
- ************************************************************************************/
-
-	.syntax	unified
-	.thumb
-	.file	"up_vfork.S"
-	.globl	__vfork
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: vfork
- *
- * Description:
- *   The vfork() function has the same effect as fork(), except that the behavior is
- *   undefined if the process created by vfork() either modifies any data other than
- *   a variable of type pid_t used to store the return value from vfork(), or returns
- *   from the function in which vfork() was called, or calls any other function before
- *   successfully calling _exit() or one of the exec family of functions. 
- *
- *   This thin layer implements vfork by simply calling __vfork() with the vfork()
- *   return address as an argument.
- *
- * Input Paremeters:
- *   None
- *
- * Return:
- *   Upon successful completion, vfork() returns 0 to the child process and returns
- *   the process ID of the child process to the parent process. Otherwise, -1 is
- *   returned to the parent, no child process is created, and errno is set to
- *   indicate the error. 
- *
- ************************************************************************************/
-
-	.thumb_func
-	.globl	vfork
-	.type	vfork, function
-vfork:
-
-    /* I know, I could have used the GCC's return address builtin and done this all
-     * in C.  But this works even if there is no builtin.
-     */
-
-	mov		r0, lr
-	b		__vfork
-	.size	vfork, .-vfork
-	.end
-
diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S
new file mode 100644
index 000000000..aceded400
--- /dev/null
+++ b/nuttx/arch/arm/src/armv7-m/vfork.S
@@ -0,0 +1,138 @@
+/************************************************************************************
+ * arch/arm/src/armv7-m/vfork.S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "up_vfork.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.syntax	unified
+	.thumb
+	.file	"vfork.S"
+	.globl	task_vfork
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: vfork
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the behavior is
+ *   undefined if the process created by vfork() either modifies any data other than
+ *   a variable of type pid_t used to store the return value from vfork(), or returns
+ *   from the function in which vfork() was called, or calls any other function before
+ *   successfully calling _exit() or one of the exec family of functions. 
+ *
+ *   This thin layer implements vfork by simply calling task_vfork() with the vfork()
+ *   context as an argument.  The overall sequence is:
+ *
+ *   1) User code calls vfork().  vfork() collects context information and
+ *      transfers control up up_vfork().
+ *   2) up_vfork()and calls task_vforksetup().
+ *   3) task_vforksetup() allocates and configures the child task's TCB.  This
+ *      consists of:
+ *      - Allocation of the child task's TCB.
+ *      - Initialization of file descriptors and streams
+ *      - Configuration of environment variables
+ *      - Setup the intput parameters for the task.
+ *      - Initialization of the TCB (including call to up_initial_state()
+ *   4) up_vfork() provides any additional operating context. up_vfork must:
+ *      - Allocate and initialize the stack
+ *      - Initialize special values in any CPU registers that were not
+ *        already configured by up_initial_state()
+ *   5) up_vfork() then calls task_vforkstart()
+ *   6) task_vforkstart() then executes the child thread.
+ *
+ * Input Paremeters:
+ *   None
+ *
+ * Return:
+ *   Upon successful completion, vfork() returns 0 to the child process and returns
+ *   the process ID of the child process to the parent process. Otherwise, -1 is
+ *   returned to the parent, no child process is created, and errno is set to
+ *   indicate the error. 
+ *
+ ************************************************************************************/
+
+	.thumb_func
+	.globl	vfork
+	.type	vfork, function
+vfork:
+	/* Create a stack frame */
+
+	mov		r0, sp					/* Save the value of the stack frame on entry */
+	sub		sp, sp, #VFORK_SIZEOF	/* Allocate the structure on the stack */
+
+	/* Save the volatile registers */
+
+	str		r4, [sp, #VFORK_R4_OFFSET]
+	str		r5, [sp, #VFORK_R5_OFFSET]
+	str		r6, [sp, #VFORK_R6_OFFSET]
+	str		r7, [sp, #VFORK_R7_OFFSET]
+	str		r8, [sp, #VFORK_R8_OFFSET]
+	str		r9, [sp, #VFORK_R9_OFFSET]
+	str		r10, [sp, #VFORK_R10_OFFSET]
+
+	/* Save the frame pointer, stack pointer, and return address */
+
+	str		fp, [sp, #VFORK_FP_OFFSET]
+	str		r0, [sp, #VFORK_SP_OFFSET]
+	str		lr, [sp, #VFORK_LR_OFFSET]
+
+	/* Then, call task_vfork(), passing it a pointer to the stack structure */
+
+	mov		r0, sp
+	bl		task_vfork
+
+	/* Release the stack data and return the value returned by task_vfork */
+
+	add		sp, sp, #VFORK_SIZEOF
+	bx		lr
+	.size	vfork, .-vfork
+	.end
+
diff --git a/nuttx/arch/arm/src/c5471/Make.defs b/nuttx/arch/arm/src/c5471/Make.defs
index 89c3aaf0b..afa73cf6c 100644
--- a/nuttx/arch/arm/src/c5471/Make.defs
+++ b/nuttx/arch/arm/src/c5471/Make.defs
@@ -35,14 +35,14 @@
 
 HEAD_ASRC	= up_nommuhead.S
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vfork.S
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 		  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \
 		  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
 		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
 		  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up__vfork.c
+		  up_undefinedinsn.c up_usestack.c up_vfork.c
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
diff --git a/nuttx/arch/arm/src/calypso/Make.defs b/nuttx/arch/arm/src/calypso/Make.defs
index 957d4e677..1a1d14869 100644
--- a/nuttx/arch/arm/src/calypso/Make.defs
+++ b/nuttx/arch/arm/src/calypso/Make.defs
@@ -39,14 +39,14 @@
 HEAD_ASRC = calypso_head.S
 
 CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
-            up_nommuhead.S up_vfork.S
+            up_nommuhead.S vfork.S
 CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
             up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \
             up_exit.c up_idle.c up_initialstate.c up_initialize.c \
             up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
             up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
             up_sigdeliver.c up_syscall.c up_unblocktask.c \
-            up_undefinedinsn.c up_usestack.c calypso_power.c up__vfork.c
+            up_undefinedinsn.c up_usestack.c calypso_power.c up_vfork.c
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
diff --git a/nuttx/arch/arm/src/common/up__vfork.c b/nuttx/arch/arm/src/common/up__vfork.c
deleted file mode 100644
index a1081faa8..000000000
--- a/nuttx/arch/arm/src/common/up__vfork.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/****************************************************************************
- * arch/arm/src/common/up__vfork
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <sched.h>
-
-#include <nuttx/sched.h>
-
-#include "os_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
- */
-
-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-#  ifdef __ARM_EABI__
-#    define CONFIG_STACK_ALIGNMENT 8
-#  else
-#    define CONFIG_STACK_ALIGNMENT 4
-#  endif
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: __vfork
- *
- * Description:
- *   The vfork() function has the same effect as fork(), except that the
- *   behavior is undefined if the process created by vfork() either modifies
- *   any data other than a variable of type pid_t used to store the return
- *   value from vfork(), or returns from the function in which vfork() was
- *   called, or calls any other function before successfully calling _exit()
- *   or one of the exec family of functions. 
- *
- *   This thin layer starts the vfork child by simply spawning a new thread
- *   that begins at the return address of vfork().
- *
- * Input Paremeters:
- *   retaddr - The return address of vfork()
- *
- * Return:
- *   Upon successful completion, vfork() returns 0 to the child process and
- *   returns the process ID of the child process to the parent process.
- *   Otherwise, -1 is returned to the parent, no child process is created,
- *   and errno is set to indicate the error. 
- *
- ****************************************************************************/
-
-pid_t __vfork(uint32_t retaddr)
-{
-  FAR _TCB *parent = (FAR _TCB *)g_readytorun.head;
-  size_t stacksize;
-  int priority;
-
-  /* Get the size of the parent task's stack.  Due to alignment operations,
-   * the adjusted stack size may be smaller than the stack size originally
-   * requrested.
-   */
-
-  stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1;
-
-  /* Get the current priority of the parent task */
-
-#ifdef CONFIG_PRIORITY_INHERITANCE
-  priority = parent->base_priority;  /* "Normal," unboosted priority */
-#else
-  priority = parent->sched_priority;  /* Current priority */
-#endif
-
- /* Start the child thread at the vfork return address.  TASK_CREATE will
-  * return the PID of the new thread.  Otherwise a negative value will be
-  * returned and the errno will be set appropriately.
-  *
-  * When the registers are initialized, the return value in R0 should be
-  * cleared to zero, providing the indication to the newly started child
-  * thread.
-  */
-
-  return TASK_CREATE("init", priority, stacksize, (main_t)retaddr,
-                     (const char **)NULL);
-}
diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c
new file mode 100644
index 000000000..404abd1f8
--- /dev/null
+++ b/nuttx/arch/arm/src/common/up_vfork.c
@@ -0,0 +1,196 @@
+/****************************************************************************
+ * arch/arm/src/common/up_vfork.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "up_vfork.h"
+#include "os_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
+ * floating point, the stack must be aligned to 8-byte addresses.
+ */
+
+#ifndef CONFIG_STACK_ALIGNMENT
+
+/* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
+ * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
+ */
+
+#  ifdef __ARM_EABI__
+#    define CONFIG_STACK_ALIGNMENT 8
+#  else
+#    define CONFIG_STACK_ALIGNMENT 4
+#  endif
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_vfork
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the
+ *   behavior is undefined if the process created by vfork() either modifies
+ *   any data other than a variable of type pid_t used to store the return
+ *   value from vfork(), or returns from the function in which vfork() was
+ *   called, or calls any other function before successfully calling _exit()
+ *   or one of the exec family of functions. 
+ *
+ *   The overall sequence is:
+ *
+ *   1) User code calls vfork().  vfork() collects context information and
+ *      transfers control up up_vfork().
+ *   2) up_vfork()and calls task_vforksetup().
+ *   3) task_vforksetup() allocates and configures the child task's TCB.  This
+ *      consists of:
+ *      - Allocation of the child task's TCB.
+ *      - Initialization of file descriptors and streams
+ *      - Configuration of environment variables
+ *      - Setup the intput parameters for the task.
+ *      - Initialization of the TCB (including call to up_initial_state()
+ *   4) up_vfork() provides any additional operating context. up_vfork must:
+ *      - Allocate and initialize the stack
+ *      - Initialize special values in any CPU registers that were not
+ *        already configured by up_initial_state()
+ *   5) up_vfork() then calls task_vforkstart()
+ *   6) task_vforkstart() then executes the child thread.
+ *
+ * task_vforkabort() may be called if an error occurs between steps 3 and 6.
+ *
+ * Input Paremeters:
+ *   context - Caller context information saved by vfork()
+ *
+ * Return:
+ *   Upon successful completion, vfork() returns 0 to the child process and
+ *   returns the process ID of the child process to the parent process.
+ *   Otherwise, -1 is returned to the parent, no child process is created,
+ *   and errno is set to indicate the error. 
+ *
+ ****************************************************************************/
+
+pid_t up_vfork(struct vfork_s *context)
+{
+  _TCB *parent = (FAR _TCB *)g_readytorun.head;
+  _TCB *child;
+  size_t stacksize;
+  uint32_t newsp;
+  uint32_t stackutil;
+  int ret;
+
+  /* Allocate and initialize a TCB for the child task. */
+
+  child = task_vforksetup((start_t)context->lr);
+  if (!child)
+    {
+      return (pid_t)ERROR;
+    }
+
+  /* Get the size of the parent task's stack.  Due to alignment operations,
+   * the adjusted stack size may be smaller than the stack size originally
+   * requrested.
+   */
+
+  stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1;
+
+  /* Allocate the stack for the TCB */
+
+  ret = up_create_stack(child, stacksize);
+  if (ret != OK)
+    {
+      task_vforkabort(child, -ret);
+      return (pid_t)ERROR;
+    }
+
+  /* How much of the parent's stack was utilized? */
+
+  DEBUGASSERT(parent->adj_stack_ptr > context->sp);
+  stackutil = (uint32_t)parent->adj_stack_ptr - context->sp;
+
+  /* Make some feeble effort to perserve the stack contents.  This is
+   * feeble because the stack surely contains invalid pointer and other
+   * content that will not work in the child context.  However, if the
+   * user follows all of the caveats of vfor() usage, even this feeble
+   * effort is overkill.
+   */
+
+  newsp = (uint32_t)child->adj_stack_ptr - stackutil;
+  memcpy((void *)newsp, (const void *)context->sp, stackutil);
+  
+ /* Update the stack pointer, frame pointer, and voltile registers.  When
+  * the child TCB was initialized, all of the values were set to zero.
+  * up_initial_state() altered a few values, but the return value in R0
+  * should be cleared to zero, providing the indication to the newly started
+  * child thread.
+  */
+
+  child->xcp.regs[REG_R4]  = context->r4;  /* Volatile register r4 */
+  child->xcp.regs[REG_R5]  = context->r5;  /* Volatile register r5 */
+  child->xcp.regs[REG_R6]  = context->r6;  /* Volatile register r6 */
+  child->xcp.regs[REG_R7]  = context->r7;  /* Volatile register r7 */
+  child->xcp.regs[REG_R8]  = context->r8;  /* Volatile register r8 */
+  child->xcp.regs[REG_R9]  = context->r9;  /* Volatile register r9 */
+  child->xcp.regs[REG_R10] = context->r10; /* Volatile register r10 */
+  child->xcp.regs[REG_FP]  = context->fp;  /* Frame pointer */
+  child->xcp.regs[REG_SP]  = context->sp;  /* Stack pointer */
+
+  /* And, finally, start the child task.  On a failure, task_vforkstart()
+   * will discard the TCB by calling task_vforkabort().
+   */
+
+  return task_vforkstart(child);
+}
diff --git a/nuttx/arch/arm/src/common/up_vfork.h b/nuttx/arch/arm/src/common/up_vfork.h
new file mode 100644
index 000000000..a4505474a
--- /dev/null
+++ b/nuttx/arch/arm/src/common/up_vfork.h
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * arch/arm/src/common/arm-vfork.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_ARM_VFORK_H
+#define __ARCH_ARM_SRC_ARM_VFORK_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define VFORK_R4_OFFSET  (0*4)   /* Volatile register r4 */
+#define VFORK_R5_OFFSET  (1*4)   /* Volatile register r5 */
+#define VFORK_R6_OFFSET  (2*4)   /* Volatile register r6 */
+#define VFORK_R7_OFFSET  (3*4)   /* Volatile register r7 */
+#define VFORK_R8_OFFSET  (4*4)   /* Volatile register r8 */
+#define VFORK_R9_OFFSET  (5*4)   /* Volatile register r9 */
+#define VFORK_R10_OFFSET (6*4)   /* Volatile register r10 */
+#define VFORK_FP_OFFSET  (7*4)   /* Frame pointer */
+#define VFORK_SP_OFFSET  (8*4)   /* Stack pointer*/
+#define VFORK_LR_OFFSET  (9*4)   /* Return address*/
+
+#define VFORK_SIZEOF     (10*4)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+struct vfork_s
+{
+  uint32_t r4;   /* Volatile register r4 */
+  uint32_t r5;   /* Volatile register r5 */
+  uint32_t r6;   /* Volatile register r6 */
+  uint32_t r7;   /* Volatile register r7 */
+  uint32_t r8;   /* Volatile register r8 */
+  uint32_t r9;   /* Volatile register r9 */
+  uint32_t r10;  /* Volatile register r10 */
+  uint32_t fp;   /* Frame pointer */
+  uint32_t sp;   /* Stack pointer*/
+  uint32_t lr;   /* Return address*/
+};
+#endif
+
+#endif /* __ARCH_ARM_SRC_ARM_VFORK_H */
diff --git a/nuttx/arch/arm/src/dm320/Make.defs b/nuttx/arch/arm/src/dm320/Make.defs
index 52e65c0e8..651d9fea9 100644
--- a/nuttx/arch/arm/src/dm320/Make.defs
+++ b/nuttx/arch/arm/src/dm320/Make.defs
@@ -36,14 +36,14 @@
 HEAD_ASRC	= up_head.S
 
 CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
-		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S
+		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \
 		  up_initialize.c up_initialstate.c up_interruptcontext.c \
 		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
 		  up_reprioritizertr.c up_schedulesigaction.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up__vfork.c
+		  up_undefinedinsn.c up_usestack.c up_vfork.c
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
diff --git a/nuttx/arch/arm/src/imx/Make.defs b/nuttx/arch/arm/src/imx/Make.defs
index a7c0ceebd..3cea29b9b 100644
--- a/nuttx/arch/arm/src/imx/Make.defs
+++ b/nuttx/arch/arm/src/imx/Make.defs
@@ -36,14 +36,14 @@
 HEAD_ASRC	= up_head.S
 
 CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
-		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S
+		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \
 		  up_initialize.c up_initialstate.c up_interruptcontext.c \
 		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
 		  up_reprioritizertr.c up_schedulesigaction.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up__vfork.c
+		  up_undefinedinsn.c up_usestack.c up_vfork.c
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
diff --git a/nuttx/arch/arm/src/kinetis/Make.defs b/nuttx/arch/arm/src/kinetis/Make.defs
index bad2946e2..e41746547 100644
--- a/nuttx/arch/arm/src/kinetis/Make.defs
+++ b/nuttx/arch/arm/src/kinetis/Make.defs
@@ -40,7 +40,7 @@ HEAD_ASRC	= kinetis_vectors.S
 # Common ARM and Cortex-M3 files
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
-			  up_vfork.S
+			  vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c up_initialize.c \
 			  up_memfault.c up_initialstate.c up_interruptcontext.c \
@@ -48,7 +48,7 @@ CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
 			  up_releasepending.c up_sigdeliver.c up_unblocktask.c up_usestack.c \
 			  up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c \
-			  up__vfork.c
+			  up_vfork.c
 
 ifeq ($(CONFIG_ARCH_MEMCPY),y)
 CMN_ASRCS	+= up_memcpy.S
diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs
index c745e1953..66b8f5658 100644
--- a/nuttx/arch/arm/src/lm3s/Make.defs
+++ b/nuttx/arch/arm/src/lm3s/Make.defs
@@ -36,7 +36,7 @@
 HEAD_ASRC	= lm3s_vectors.S
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
-			  up_vfork.S
+			  vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
 			  up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \
@@ -44,7 +44,7 @@ CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
 			  up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
 			  up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \
-			  up__vfork.c
+			  up_vfork.c
 
 ifeq ($(CONFIG_ARCH_MEMCPY),y)
 CMN_ASRCS	+= up_memcpy.S
diff --git a/nuttx/arch/arm/src/lpc17xx/Make.defs b/nuttx/arch/arm/src/lpc17xx/Make.defs
index 1ea0183a1..ed05fff95 100644
--- a/nuttx/arch/arm/src/lpc17xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc17xx/Make.defs
@@ -40,14 +40,14 @@ HEAD_ASRC	= lpc17_vectors.S
 # Common ARM and Cortex-M3 files
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
-			  up_vfork.S
+			  vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 			  up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c \
 			  up_initialstate.c up_interruptcontext.c up_modifyreg8.c \
 			  up_modifyreg16.c up_modifyreg32.c up_releasepending.c \
 			  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
 			  up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \
-			  up_hardfault.c up_svcall.c up_checkstack.c up__vfork.c
+			  up_hardfault.c up_svcall.c up_checkstack.c up_vfork.c
 
 ifeq ($(CONFIG_ARCH_MEMCPY),y)
 CMN_ASRCS	+= up_memcpy.S
diff --git a/nuttx/arch/arm/src/lpc214x/Make.defs b/nuttx/arch/arm/src/lpc214x/Make.defs
index 6821d512b..34713b008 100644
--- a/nuttx/arch/arm/src/lpc214x/Make.defs
+++ b/nuttx/arch/arm/src/lpc214x/Make.defs
@@ -36,13 +36,13 @@
 HEAD_ASRC	= lpc214x_head.S
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
-			  up_vfork.S
+			  vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 		  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
 		  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
 		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
 		  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c
+		  up_undefinedinsn.c up_usestack.c up_lowputs.c up_vfork.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS	+= up_schedulesigaction.c up_sigdeliver.c
diff --git a/nuttx/arch/arm/src/lpc2378/Make.defs b/nuttx/arch/arm/src/lpc2378/Make.defs
index 3d3c15926..cfd9dc79f 100644
--- a/nuttx/arch/arm/src/lpc2378/Make.defs
+++ b/nuttx/arch/arm/src/lpc2378/Make.defs
@@ -41,13 +41,13 @@
 HEAD_ASRC	= lpc23xx_head.S
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
-			  up_vfork.S
+			  vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
 			  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
 			  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
 			  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
-			  up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c
+			  up_undefinedinsn.c up_usestack.c up_lowputs.c up_vfork.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS	+= up_schedulesigaction.c up_sigdeliver.c
diff --git a/nuttx/arch/arm/src/lpc31xx/Make.defs b/nuttx/arch/arm/src/lpc31xx/Make.defs
index b3a9746b4..4e6f69299 100644
--- a/nuttx/arch/arm/src/lpc31xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc31xx/Make.defs
@@ -36,7 +36,7 @@
 HEAD_ASRC	= up_head.S
 
 CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
-		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S
+		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \
 		  up_initialize.c up_initialstate.c up_interruptcontext.c \
@@ -44,7 +44,7 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
 		  up_reprioritizertr.c up_schedulesigaction.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up__vfork.c
+		  up_undefinedinsn.c up_usestack.c up_vfork.c
 
 ifeq ($(CONFIG_PAGING),y)
 CMN_CSRCS	+= up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c
diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs
index 211f9bee3..9674196c5 100644
--- a/nuttx/arch/arm/src/lpc43xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc43xx/Make.defs
@@ -36,7 +36,7 @@
 HEAD_ASRC  =
 
 CMN_ASRCS  = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_vfork.S
+CMN_ASRCS += vfork.S
 
 CMN_CSRCS  = up_assert.c up_blocktask.c up_copystate.c
 CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
@@ -44,7 +44,7 @@ CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
 CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
 CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
 CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c
-CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c up__vfork.c
+CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c up_vfork.c
 
 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 CMN_ASRCS += up_exception.S
diff --git a/nuttx/arch/arm/src/sam3u/Make.defs b/nuttx/arch/arm/src/sam3u/Make.defs
index 4682ea83d..58047af21 100644
--- a/nuttx/arch/arm/src/sam3u/Make.defs
+++ b/nuttx/arch/arm/src/sam3u/Make.defs
@@ -40,14 +40,14 @@ HEAD_ASRC	= sam3u_vectors.S
 # Common ARM and Cortex-M3 files
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
-			  up_vfork.S
+			  vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 			  up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c \
 			  up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c \
 			  up_modifyreg16.c up_modifyreg32.c up_releasepending.c \
 			  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
 			  up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \
-			  up_hardfault.c up_svcall.c up__vfork.c
+			  up_hardfault.c up_svcall.c up_vfork.c
 
 # Configuration-dependent common files
 
diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs
index 89c291791..fd19e3bf6 100644
--- a/nuttx/arch/arm/src/stm32/Make.defs
+++ b/nuttx/arch/arm/src/stm32/Make.defs
@@ -40,7 +40,7 @@ HEAD_ASRC	= stm32_vectors.S
 endif
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
-			  up_vfork.S
+			  vfork.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c \
 			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
 			  up_initialize.c up_initialstate.c up_interruptcontext.c \
@@ -48,7 +48,7 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c \
 			  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
 			  up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \
 			  up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c \
-			  up_svcall.c up__vfork.c
+			  up_svcall.c up_vfork.c
 
 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 CMN_ASRCS	+= up_exception.S
diff --git a/nuttx/arch/arm/src/str71x/Make.defs b/nuttx/arch/arm/src/str71x/Make.defs
index 3612950a6..bde5ca003 100644
--- a/nuttx/arch/arm/src/str71x/Make.defs
+++ b/nuttx/arch/arm/src/str71x/Make.defs
@@ -36,13 +36,13 @@
 HEAD_ASRC	= str71x_head.S
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
-			  up_vfork.S
+			  vfork.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
 			  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
 			  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
 			  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
-			  up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c
+			  up_undefinedinsn.c up_usestack.c up_lowputs.c up_vfork.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS	+= up_schedulesigaction.c up_sigdeliver.c
diff --git a/nuttx/include/nuttx/arch.h b/nuttx/include/nuttx/arch.h
index 8b4b10ade..958986472 100644
--- a/nuttx/include/nuttx/arch.h
+++ b/nuttx/include/nuttx/arch.h
@@ -1,7 +1,7 @@
 /****************************************************************************
  * include/nuttx/arch.h
  *
- *   Copyright (C) 2007-2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/nuttx/include/nuttx/sched.h b/nuttx/include/nuttx/sched.h
index 6eaba6e9c..940bf1f1b 100644
--- a/nuttx/include/nuttx/sched.h
+++ b/nuttx/include/nuttx/sched.h
@@ -382,6 +382,32 @@ EXTERN FAR struct streamlist *sched_getstreams(void);
 EXTERN FAR struct socketlist *sched_getsockets(void);
 #endif /* CONFIG_NSOCKET_DESCRIPTORS */
 
+/* Internal vfork support.The  overall sequence is:
+ *
+ * 1) User code calls vfork().  vfork() is provided in architecture-specific
+ *    code.
+ * 2) vfork()and calls task_vforksetup().
+ * 3) task_vforksetup() allocates and configures the child task's TCB.  This
+ *    consists of:
+ *    - Allocation of the child task's TCB.
+ *    - Initialization of file descriptors and streams
+ *    - Configuration of environment variables
+ *    - Setup the intput parameters for the task.
+ *    - Initialization of the TCB (including call to up_initial_state()
+ * 4) vfork() provides any additional operating context. vfork must:
+ *    - Allocate and initialize the stack
+ *    - Initialize special values in any CPU registers that were not
+ *      already configured by up_initial_state()
+ * 5) vfork() then calls task_vforkstart()
+ * 6) task_vforkstart() then executes the child thread.
+ *
+ * task_vforkabort() may be called if an error occurs between steps 3 and 6.
+ */
+
+FAR _TCB *task_vforksetup(start_t retaddr);
+pid_t task_vforkstart(FAR _TCB *child);
+void task_vforkabort(FAR _TCB *child, int errcode);
+
 /* sched_foreach will enumerate over each task and provide the
  * TCB of each task to a user callback functions.  Interrupts
  * will be disabled throughout this enumeration!
diff --git a/nuttx/sched/Makefile b/nuttx/sched/Makefile
index 82f74fc3c..23d1e9938 100644
--- a/nuttx/sched/Makefile
+++ b/nuttx/sched/Makefile
@@ -45,7 +45,7 @@ MISC_SRCS	= os_start.c os_bringup.c errno_getptr.c errno_get.c errno_set.c \
 
 TSK_SRCS	= prctl.c task_create.c task_init.c task_setup.c task_activate.c \
 		  task_start.c task_delete.c task_deletecurrent.c task_exithook.c \
-		  task_restart.c exit.c getpid.c sched_addreadytorun.c \
+		  task_restart.c task_vfork.c exit.c getpid.c sched_addreadytorun.c \
 		  sched_removereadytorun.c sched_addprioritized.c sched_mergepending.c \
 		  sched_addblocked.c sched_removeblocked.c sched_free.c sched_gettcb.c \
 		  sched_verifytcb.c sched_releasetcb.c
diff --git a/nuttx/sched/sched_setuptaskfiles.c b/nuttx/sched/sched_setuptaskfiles.c
index fe0b14143..d01b8d4cd 100644
--- a/nuttx/sched/sched_setuptaskfiles.c
+++ b/nuttx/sched/sched_setuptaskfiles.c
@@ -200,7 +200,8 @@ static inline void sched_dupsockets(FAR _TCB *tcb)
  *   tcb - tcb of the new task.
  *
  * Return Value:
- *   None
+ *   Zero (OK) is returned on success; A negated errno value is returned on
+ *   failure.
  *
  * Assumptions:
  *
diff --git a/nuttx/sched/task_create.c b/nuttx/sched/task_create.c
index 4d92c9bb0..801706cbf 100644
--- a/nuttx/sched/task_create.c
+++ b/nuttx/sched/task_create.c
@@ -169,6 +169,8 @@ static int thread_create(const char *name, uint8_t type, int priority,
   ret = task_activate(tcb);
   if (ret != OK)
     {
+      /* The TCB was added to the active task list by task_schedsetup() */
+
       dq_rem((FAR dq_entry_t*)tcb, (dq_queue_t*)&g_inactivetasks);
       goto errout_with_tcb;
     }
diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c
new file mode 100644
index 000000000..93fcb46da
--- /dev/null
+++ b/nuttx/sched/task_vfork.c
@@ -0,0 +1,266 @@
+/****************************************************************************
+ * sched/task_vfork
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <queue.h>
+#include <errno.h>
+
+#include <nuttx/sched.h>
+
+#include "os_internal.h"
+#include "env_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: task_vforksetup
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the
+ *   behavior is undefined if the process created by vfork() either modifies
+ *   any data other than a variable of type pid_t used to store the return
+ *   value from vfork(), or returns from the function in which vfork() was
+ *   called, or calls any other function before successfully calling _exit()
+ *   or one of the exec family of functions. 
+ *
+ *   This functin provides one step in the overall vfork() sequence:  It
+ *   Allocates and initializes the child task's TCB.  The overall sequence is:
+ *
+ *   1) User code calls vfork().  vfork() is provided in architecture-specific
+ *      code.
+ *   2) vfork()and calls task_vforksetup().
+ *   3) task_vforksetup() allocates and configures the child task's TCB.  This
+ *      consists of:
+ *      - Allocation of the child task's TCB.
+ *      - Initialization of file descriptors and streams
+ *      - Configuration of environment variables
+ *      - Setup the intput parameters for the task.
+ *      - Initialization of the TCB (including call to up_initial_state()
+ *   4) up_vfork() provides any additional operating context. up_vfork must:
+ *      - Allocate and initialize the stack
+ *      - Initialize special values in any CPU registers that were not
+ *        already configured by up_initial_state()
+ *   5) up_vfork() then calls task_vforkstart()
+ *   6) task_vforkstart() then executes the child thread.
+ *
+ * Input Paremeters:
+ *   retaddr - The return address from vfork() where the child task
+ *     will be started.
+ *
+ * Returned Value:
+ *   Upon successful completion, task_vforksetup() returns a pointer to
+ *   newly allocated and initalized child task's TCB.  NULL is returned
+ *   on any failure and the errno is set appropriately.
+ *
+ ****************************************************************************/
+
+FAR _TCB *task_vforksetup(start_t retaddr)
+{
+  _TCB *parent = (FAR _TCB *)g_readytorun.head;
+  _TCB *child;
+  int priority;
+  int ret;
+
+  DEBUGASSERT(retaddr);
+
+  /* Allocate a TCB for the child task. */
+
+  child = (FAR _TCB*)kzalloc(sizeof(_TCB));
+  if (!child)
+    {
+      set_errno(ENOMEM);
+      return NULL;
+    }
+
+  /* Associate file descriptors with the new task */
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 || CONFIG_NSOCKET_DESCRIPTORS > 0
+  ret = sched_setuptaskfiles(child);
+  if (ret != OK)
+    {
+      goto errout_with_tcb;
+    }
+#endif
+
+  /* Clone the parent's task environment */
+
+  (void)env_dup(child);
+
+  /* Mark the type of this thread (this setting will be needed in
+   * task_schedsetup() when up_initial_state() is called.
+   */
+
+  child->flags |= TCB_FLAG_TTYPE_TASK;
+
+  /* Get the priority of the parent task */
+
+#ifdef CONFIG_PRIORITY_INHERITANCE
+  priority = parent->base_priority;  /* "Normal," unboosted priority */
+#else
+  priority = parent->sched_priority;  /* Current priority */
+#endif
+
+  /* Initialize the task control block.  This calls up_initial_state() */
+
+  ret = task_schedsetup(child, priority, retaddr, parent->entry.main);
+  if (ret != OK)
+    {
+      goto errout_with_tcb;
+    }
+
+  return child;
+
+errout_with_tcb:
+  sched_releasetcb(child);
+  set_errno(-ret);
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: task_vforkstart
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the
+ *   behavior is undefined if the process created by vfork() either modifies
+ *   any data other than a variable of type pid_t used to store the return
+ *   value from vfork(), or returns from the function in which vfork() was
+ *   called, or calls any other function before successfully calling _exit()
+ *   or one of the exec family of functions. 
+ *
+ *   This functin provides one step in the overall vfork() sequence:  It
+ *   starts execution of the previously initialized TCB.  The overall
+ *   sequence is:
+ *
+ *   1) User code calls vfork()
+ *   2) Architecture-specific code provides vfork()and calls task_vforksetup().
+ *   3) task_vforksetup() allocates and configures the child task's TCB.  This
+ *      consists of:
+ *      - Allocation of the child task's TCB.
+ *      - Initialization of file descriptors and streams
+ *      - Configuration of environment variables
+ *      - Setup the intput parameters for the task.
+ *      - Initialization of the TCB (including call to up_initial_state()
+ *   4) vfork() provides any additional operating context. vfork must:
+ *      - Allocate and initialize the stack
+ *      - Initialize special values in any CPU registers that were not
+ *        already configured by up_initial_state()
+ *   5) vfork() then calls task_vforkstart()
+ *   6) task_vforkstart() then executes the child thread.
+ *
+ * Input Paremeters:
+ *   retaddr - The return address from vfork() where the child task
+ *     will be started.
+ *
+ * Returned Value:
+ *   Upon successful completion, vfork() returns 0 to the child process and
+ *   returns the process ID of the child process to the parent process.
+ *   Otherwise, -1 is returned to the parent, no child process is created,
+ *   and errno is set to indicate the error. 
+ *
+ ****************************************************************************/
+
+pid_t task_vforkstart(FAR _TCB *child)
+{
+  FAR const char *name;
+  pid_t pid;
+  int ret;
+
+  DEBUGASSERT(child);
+
+  /* Setup to pass parameters to the new task */
+
+#if CONFIG_TASK_NAME_SIZE > 0
+  name = parent->name;
+#else
+  name = "<noname>";
+#endif
+
+  (void)task_argsetup(child, name, (const char **)NULL);
+
+  /* Get the assigned pid before we start the task */
+
+  pid = (int)child->pid;
+
+  /* Activate the task */
+
+  ret = task_activate(child);
+  if (ret != OK)
+    {
+      task_vforkabort(child, -ret);
+      return ERROR;
+    }
+
+  return pid;
+}
+
+/****************************************************************************
+ * Name: task_vforkabort
+ *
+ * Description:
+ *   Recover from any errors after task_vforksetup() was called.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void task_vforkabort(FAR _TCB *child, int errcode)
+{
+  /* The TCB was added to the active task list by task_schedsetup() */
+
+  dq_rem((FAR dq_entry_t*)child, (dq_queue_t*)&g_inactivetasks);
+
+  /* Release the TCB */
+
+  sched_releasetcb(child);
+  set_errno(errcode);
+}
\ No newline at end of file
-- 
cgit v1.2.3


From 66cdd288ab6a4d19c67300a73a26e9ee5a958187 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Mon, 7 Jan 2013 21:41:20 +0000
Subject: Add ostest vfork test (does not work yet)

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5488 42af7a65-404d-4744-a932-0658087f49c3
---
 apps/examples/ostest/Makefile        |  4 ++
 apps/examples/ostest/ostest.h        |  6 +++
 apps/examples/ostest/ostest_main.c   |  6 +++
 apps/examples/ostest/vfork.c         | 99 ++++++++++++++++++++++++++++++++++++
 nuttx/arch/Kconfig                   |  5 ++
 nuttx/arch/arm/src/arm/vfork.S       | 10 ++--
 nuttx/arch/arm/src/armv7-m/vfork.S   | 10 ++--
 nuttx/arch/arm/src/common/up_vfork.c | 45 +++++++++++++---
 nuttx/sched/sched_addprioritized.c   |  2 +-
 nuttx/sched/sched_addreadytorun.c    |  8 +--
 nuttx/sched/task_vfork.c             |  9 +++-
 11 files changed, 182 insertions(+), 22 deletions(-)
 create mode 100644 apps/examples/ostest/vfork.c

(limited to 'nuttx/arch')

diff --git a/apps/examples/ostest/Makefile b/apps/examples/ostest/Makefile
index 3d19f6a78..b7ba9a9a8 100644
--- a/apps/examples/ostest/Makefile
+++ b/apps/examples/ostest/Makefile
@@ -84,6 +84,10 @@ ifneq ($(CONFIG_DISABLE_POSIX_TIMERS),y)
 CSRCS		+= posixtimer.c
 endif
 
+ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
+CSRCS		+= vfork.c
+endif
+
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 ifneq ($(CONFIG_DISABLE_PTHREAD),y)
 ifeq ($(CONFIG_PRIORITY_INHERITANCE),y)
diff --git a/apps/examples/ostest/ostest.h b/apps/examples/ostest/ostest.h
index a4af37f05..bc46a3860 100644
--- a/apps/examples/ostest/ostest.h
+++ b/apps/examples/ostest/ostest.h
@@ -163,6 +163,12 @@ extern void barrier_test(void);
 
 extern void priority_inheritance(void);
 
+/* vfork.c ******************************************************************/
+
+#ifdef CONFIG_ARCH_HAVE_VFORK
+extern int vfork_test(void);
+#endif
+
 /* APIs exported (conditionally) by the OS specifically for testing of
  * priority inheritance
  */
diff --git a/apps/examples/ostest/ostest_main.c b/apps/examples/ostest/ostest_main.c
index 46726d515..ca44353c3 100644
--- a/apps/examples/ostest/ostest_main.c
+++ b/apps/examples/ostest/ostest_main.c
@@ -409,6 +409,11 @@ static int user_main(int argc, char *argv[])
       check_test_memory_usage();
 #endif /* CONFIG_PRIORITY_INHERITANCE && !CONFIG_DISABLE_SIGNALS && !CONFIG_DISABLE_PTHREAD */
 
+#ifdef CONFIG_ARCH_HAVE_VFORK
+      printf("\nuser_main: vfork() test\n");
+      vfork_test();
+#endif
+
       /* Compare memory usage at time ostest_main started until
        * user_main exits.  These should not be identical, but should
        * be similar enough that we can detect any serious OS memory
@@ -428,6 +433,7 @@ static int user_main(int argc, char *argv[])
       show_memory_usage(&g_mmbefore, &g_mmafter);
 #endif
     }
+
   printf("user_main: Exitting\n");
   return 0;
 }
diff --git a/apps/examples/ostest/vfork.c b/apps/examples/ostest/vfork.c
new file mode 100644
index 000000000..6c83047e3
--- /dev/null
+++ b/apps/examples/ostest/vfork.c
@@ -0,0 +1,99 @@
+/****************************************************************************
+ * examples/ostest/vfork.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <errno.h>
+
+#include "ostest.h"
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_HAVE_VFORK) && !defined(CONFIG_DISABLE_SIGNALS)
+static volatile bool g_vforkchild;
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int vfork_test(void)
+{
+#if defined(CONFIG_ARCH_HAVE_VFORK) && !defined(CONFIG_DISABLE_SIGNALS)
+  pid_t pid;
+
+  g_vforkchild = false;
+  pid = vfork();
+  if (pid == 0)
+    {
+      /* There is not very much that the child is permitted to do.  Perhaps
+       * it can just set g_vforkchild.
+       */
+
+      g_vforkchild = true;
+      exit(0);
+    }
+  else if (pid < 0)
+    {
+      printf("vfork_test: vfork() failed: %d\n", errno);
+      return -1;
+    }
+  else
+    {
+      sleep(1);
+      if (g_vforkchild)
+        {
+          printf("vfork_test: Child %d ran successfully\n", pid);
+        }
+      else
+        {
+          printf("vfork_test: ERROR Child %d did not run\n", pid);
+          return -1;
+        }
+    }
+#endif
+
+  return 0;
+}
diff --git a/nuttx/arch/Kconfig b/nuttx/arch/Kconfig
index f19228143..7d34b56f4 100644
--- a/nuttx/arch/Kconfig
+++ b/nuttx/arch/Kconfig
@@ -16,6 +16,7 @@ config ARCH_8051
 config ARCH_ARM
 	bool "ARM"
 	select ARCH_HAVE_INTERRUPTSTACK
+	select ARCH_HAVE_VFORK
 	---help---
 		The ARM architectures
 
@@ -124,6 +125,10 @@ config ADDRENV
 	bool
 	default n
 
+config ARCH_HAVE_VFORK
+	bool
+	default n
+
 config ARCH_STACKDUMP
 	bool "Dump stack on assertions"
 	default n
diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S
index f0fe17f73..b498fd7f7 100644
--- a/nuttx/arch/arm/src/arm/vfork.S
+++ b/nuttx/arch/arm/src/arm/vfork.S
@@ -50,7 +50,7 @@
  ************************************************************************************/
 
 	.file	"vfork.S"
-	.globl	task_vfork
+	.globl	up_vfork
 
 /************************************************************************************
  * Public Functions
@@ -66,7 +66,7 @@
  *   from the function in which vfork() was called, or calls any other function before
  *   successfully calling _exit() or one of the exec family of functions. 
  *
- *   This thin layer implements vfork by simply calling task_vfork() with the vfork()
+ *   This thin layer implements vfork by simply calling up_vfork() with the vfork()
  *   context as an argument.  The overall sequence is:
  *
  *   1) User code calls vfork().  vfork() collects context information and
@@ -121,12 +121,12 @@ vfork:
 	str		r0, [sp, #VFORK_SP_OFFSET]
 	str		lr, [sp, #VFORK_LR_OFFSET]
 
-	/* Then, call task_vfork(), passing it a pointer to the stack structure */
+	/* Then, call up_vfork(), passing it a pointer to the stack structure */
 
 	mov		r0, sp
-	bl		task_vfork
+	bl		up_vfork
 
-	/* Release the stack data and return the value returned by task_vfork */
+	/* Release the stack data and return the value returned by up_vfork */
 
 	add		sp, sp, #VFORK_SIZEOF
 	mov		pc, lr
diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S
index aceded400..0d9e144cd 100644
--- a/nuttx/arch/arm/src/armv7-m/vfork.S
+++ b/nuttx/arch/arm/src/armv7-m/vfork.S
@@ -52,7 +52,7 @@
 	.syntax	unified
 	.thumb
 	.file	"vfork.S"
-	.globl	task_vfork
+	.globl	up_vfork
 
 /************************************************************************************
  * Public Functions
@@ -68,7 +68,7 @@
  *   from the function in which vfork() was called, or calls any other function before
  *   successfully calling _exit() or one of the exec family of functions. 
  *
- *   This thin layer implements vfork by simply calling task_vfork() with the vfork()
+ *   This thin layer implements vfork by simply calling up_vfork() with the vfork()
  *   context as an argument.  The overall sequence is:
  *
  *   1) User code calls vfork().  vfork() collects context information and
@@ -124,12 +124,12 @@ vfork:
 	str		r0, [sp, #VFORK_SP_OFFSET]
 	str		lr, [sp, #VFORK_LR_OFFSET]
 
-	/* Then, call task_vfork(), passing it a pointer to the stack structure */
+	/* Then, call up_vfork(), passing it a pointer to the stack structure */
 
 	mov		r0, sp
-	bl		task_vfork
+	bl		up_vfork
 
-	/* Release the stack data and return the value returned by task_vfork */
+	/* Release the stack data and return the value returned by up_vfork */
 
 	add		sp, sp, #VFORK_SIZEOF
 	bx		lr
diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c
index 404abd1f8..2e3c2d4a1 100644
--- a/nuttx/arch/arm/src/common/up_vfork.c
+++ b/nuttx/arch/arm/src/common/up_vfork.c
@@ -43,6 +43,7 @@
 #include <string.h>
 #include <assert.h>
 #include <errno.h>
+#include <debug.h>
 
 #include <nuttx/sched.h>
 #include <nuttx/arch.h>
@@ -129,17 +130,28 @@ pid_t up_vfork(struct vfork_s *context)
   _TCB *child;
   size_t stacksize;
   uint32_t newsp;
+  uint32_t newfp;
   uint32_t stackutil;
   int ret;
 
+  svdbg("r4:%08x r5:%08x r6:%08x r7:%08x\n",
+        context->r4, context->r5, context->r6, context->r7);
+  svdbg("r8:%08x r9:%08x r10:%08x\n",
+        context->r8, context->r9, context->r10);
+  svdbg("fp:%08x sp:%08x lr:%08x\n",
+        context->fp, context->sp, context->lr);
+
   /* Allocate and initialize a TCB for the child task. */
 
-  child = task_vforksetup((start_t)context->lr);
+  child = task_vforksetup((start_t)(context->lr & ~1));
   if (!child)
     {
+      sdbg("task_vforksetup failed\n");
       return (pid_t)ERROR;
     }
 
+  svdbg("Parent=%p Child=%p\n", parent, child);
+
   /* Get the size of the parent task's stack.  Due to alignment operations,
    * the adjusted stack size may be smaller than the stack size originally
    * requrested.
@@ -152,15 +164,18 @@ pid_t up_vfork(struct vfork_s *context)
   ret = up_create_stack(child, stacksize);
   if (ret != OK)
     {
+      sdbg("up_create_stack failed: %d\n", ret);
       task_vforkabort(child, -ret);
       return (pid_t)ERROR;
     }
 
   /* How much of the parent's stack was utilized? */
 
-  DEBUGASSERT(parent->adj_stack_ptr > context->sp);
+  DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp);
   stackutil = (uint32_t)parent->adj_stack_ptr - context->sp;
 
+  svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); 
+
   /* Make some feeble effort to perserve the stack contents.  This is
    * feeble because the stack surely contains invalid pointer and other
    * content that will not work in the child context.  However, if the
@@ -170,8 +185,26 @@ pid_t up_vfork(struct vfork_s *context)
 
   newsp = (uint32_t)child->adj_stack_ptr - stackutil;
   memcpy((void *)newsp, (const void *)context->sp, stackutil);
-  
- /* Update the stack pointer, frame pointer, and voltile registers.  When
+
+  /* Was there a frame pointer in place before? */
+
+  if (context->fp <= (uint32_t)parent->adj_stack_ptr &&
+      context->fp >= (uint32_t)parent->adj_stack_ptr - stacksize)
+    {
+      uint32_t frameutil = (uint32_t)parent->adj_stack_ptr - context->fp;
+      newfp = (uint32_t)child->adj_stack_ptr - frameutil;
+    }
+  else
+    {
+      newfp = context->fp;
+    }
+
+  svdbg("Old stack base:%08x SP:%08x FP:%08x\n",
+        parent->adj_stack_ptr, context->sp, context->fp);
+  svdbg("New stack base:%08x SP:%08x FP:%08x\n",
+        child->adj_stack_ptr, newsp, newfp);
+
+        /* Update the stack pointer, frame pointer, and voltile registers.  When
   * the child TCB was initialized, all of the values were set to zero.
   * up_initial_state() altered a few values, but the return value in R0
   * should be cleared to zero, providing the indication to the newly started
@@ -185,8 +218,8 @@ pid_t up_vfork(struct vfork_s *context)
   child->xcp.regs[REG_R8]  = context->r8;  /* Volatile register r8 */
   child->xcp.regs[REG_R9]  = context->r9;  /* Volatile register r9 */
   child->xcp.regs[REG_R10] = context->r10; /* Volatile register r10 */
-  child->xcp.regs[REG_FP]  = context->fp;  /* Frame pointer */
-  child->xcp.regs[REG_SP]  = context->sp;  /* Stack pointer */
+  child->xcp.regs[REG_FP]  = newfp;        /* Frame pointer */
+  child->xcp.regs[REG_SP]  = newsp;        /* Stack pointer */
 
   /* And, finally, start the child task.  On a failure, task_vforkstart()
    * will discard the TCB by calling task_vforkabort().
diff --git a/nuttx/sched/sched_addprioritized.c b/nuttx/sched/sched_addprioritized.c
index 8f19a4731..20178fb9c 100644
--- a/nuttx/sched/sched_addprioritized.c
+++ b/nuttx/sched/sched_addprioritized.c
@@ -114,7 +114,7 @@ bool sched_addprioritized(FAR _TCB *tcb, DSEG dq_queue_t *list)
       (next && sched_priority <= next->sched_priority);
       next = next->flink);
 
-  /* Add the tcb to the spot found in the list.  Check if the tcb 
+  /* Add the tcb to the spot found in the list.  Check if the tcb
    * goes at the end of the list. NOTE:  This could only happen if list
    * is the g_pendingtasks list!
    */
diff --git a/nuttx/sched/sched_addreadytorun.c b/nuttx/sched/sched_addreadytorun.c
index f6117b6ff..1e1829343 100644
--- a/nuttx/sched/sched_addreadytorun.c
+++ b/nuttx/sched/sched_addreadytorun.c
@@ -84,8 +84,8 @@
  *   btcb - Points to the blocked TCB that is ready-to-run
  *
  * Return Value:
- *   true if the currently active task (the head of the 
- *     g_readytorun list) has changed.
+ *   true if the currently active task (the head of the g_readytorun list)
+ *   has changed.
  *
  * Assumptions:
  * - The caller has established a critical section before
@@ -104,7 +104,7 @@ bool sched_addreadytorun(FAR _TCB *btcb)
   bool ret;
 
   /* Check if pre-emption is disabled for the current running task and if
-   * the new ready-to-run task  would cause the current running task to be
+   * the new ready-to-run task would cause the current running task to be
    * preempted.
    */
 
@@ -123,7 +123,7 @@ bool sched_addreadytorun(FAR _TCB *btcb)
 
   else if (sched_addprioritized(btcb, (FAR dq_queue_t*)&g_readytorun))
     {
-      /* Information the instrumentation logic that we are switching tasks */
+      /* Inform the instrumentation logic that we are switching tasks */
 
       sched_note_switch(rtcb, btcb);
 
diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c
index 93fcb46da..64f6f0636 100644
--- a/nuttx/sched/task_vfork.c
+++ b/nuttx/sched/task_vfork.c
@@ -43,6 +43,7 @@
 #include <assert.h>
 #include <queue.h>
 #include <errno.h>
+#include <debug.h>
 
 #include <nuttx/sched.h>
 
@@ -151,12 +152,14 @@ FAR _TCB *task_vforksetup(start_t retaddr)
 
   /* Initialize the task control block.  This calls up_initial_state() */
 
+  svdbg("Child priority=%d start=%p\n", priority, retaddr);
   ret = task_schedsetup(child, priority, retaddr, parent->entry.main);
   if (ret != OK)
     {
       goto errout_with_tcb;
     }
 
+  svdbg("parent=%p, returning child=%p\n", parent, child);
   return child;
 
 errout_with_tcb:
@@ -210,10 +213,14 @@ errout_with_tcb:
 
 pid_t task_vforkstart(FAR _TCB *child)
 {
+#if CONFIG_TASK_NAME_SIZE > 0
+  _TCB *parent = (FAR _TCB *)g_readytorun.head;
+#endif
   FAR const char *name;
   pid_t pid;
   int ret;
 
+  svdbg("Starting Child TCB=%p, parent=%p\n", child, g_readytorun.head);
   DEBUGASSERT(child);
 
   /* Setup to pass parameters to the new task */
@@ -221,7 +228,7 @@ pid_t task_vforkstart(FAR _TCB *child)
 #if CONFIG_TASK_NAME_SIZE > 0
   name = parent->name;
 #else
-  name = "<noname>";
+  name = NULL;
 #endif
 
   (void)task_argsetup(child, name, (const char **)NULL);
-- 
cgit v1.2.3


From 5a9162f017e457a5415eb0af7c41a7ef49d355c6 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Mon, 7 Jan 2013 23:09:09 +0000
Subject: Disable the vfork() OS test... it fails

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5489 42af7a65-404d-4744-a932-0658087f49c3
---
 apps/examples/ostest/vfork.c         | 10 ++++++++++
 nuttx/arch/arm/src/common/up_vfork.c | 10 +++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)

(limited to 'nuttx/arch')

diff --git a/apps/examples/ostest/vfork.c b/apps/examples/ostest/vfork.c
index 6c83047e3..8657f0ceb 100644
--- a/apps/examples/ostest/vfork.c
+++ b/apps/examples/ostest/vfork.c
@@ -47,6 +47,16 @@
 
 #include "ostest.h"
 
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Disabled this test for now.  There are some issues with the vfork
+ * implementation.
+*/
+
+#undef CONFIG_ARCH_HAVE_VFORK
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c
index 2e3c2d4a1..3da602679 100644
--- a/nuttx/arch/arm/src/common/up_vfork.c
+++ b/nuttx/arch/arm/src/common/up_vfork.c
@@ -169,7 +169,11 @@ pid_t up_vfork(struct vfork_s *context)
       return (pid_t)ERROR;
     }
 
-  /* How much of the parent's stack was utilized? */
+  /* How much of the parent's stack was utilized?  The ARM uses
+   * a push-down stack so that the current stack pointer should
+   * be lower than the initial, adjusted stack pointer.  The
+   * stack usage should be the difference between those two.
+   */
 
   DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp);
   stackutil = (uint32_t)parent->adj_stack_ptr - context->sp;
@@ -177,7 +181,7 @@ pid_t up_vfork(struct vfork_s *context)
   svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); 
 
   /* Make some feeble effort to perserve the stack contents.  This is
-   * feeble because the stack surely contains invalid pointer and other
+   * feeble because the stack surely contains invalid pointers and other
    * content that will not work in the child context.  However, if the
    * user follows all of the caveats of vfor() usage, even this feeble
    * effort is overkill.
@@ -204,7 +208,7 @@ pid_t up_vfork(struct vfork_s *context)
   svdbg("New stack base:%08x SP:%08x FP:%08x\n",
         child->adj_stack_ptr, newsp, newfp);
 
-        /* Update the stack pointer, frame pointer, and voltile registers.  When
+ /* Update the stack pointer, frame pointer, and voltile registers.  When
   * the child TCB was initialized, all of the values were set to zero.
   * up_initial_state() altered a few values, but the return value in R0
   * should be cleared to zero, providing the indication to the newly started
-- 
cgit v1.2.3


From a9f2c6fa8ae6936da9489e4acf2a2d2cd6c0f664 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Mon, 7 Jan 2013 23:50:25 +0000
Subject: Fixed ARM vfork; re-enabled vfork OS test

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5490 42af7a65-404d-4744-a932-0658087f49c3
---
 apps/examples/ostest/vfork.c         | 6 ------
 nuttx/arch/arm/src/arm/vfork.S       | 3 ++-
 nuttx/arch/arm/src/armv7-m/vfork.S   | 3 ++-
 nuttx/arch/arm/src/common/up_vfork.c | 2 +-
 4 files changed, 5 insertions(+), 9 deletions(-)

(limited to 'nuttx/arch')

diff --git a/apps/examples/ostest/vfork.c b/apps/examples/ostest/vfork.c
index 8657f0ceb..4e1b8c892 100644
--- a/apps/examples/ostest/vfork.c
+++ b/apps/examples/ostest/vfork.c
@@ -51,12 +51,6 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* Disabled this test for now.  There are some issues with the vfork
- * implementation.
-*/
-
-#undef CONFIG_ARCH_HAVE_VFORK
-
 /****************************************************************************
  * Private Data
  ****************************************************************************/
diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S
index b498fd7f7..226d9f7de 100644
--- a/nuttx/arch/arm/src/arm/vfork.S
+++ b/nuttx/arch/arm/src/arm/vfork.S
@@ -102,7 +102,7 @@
 vfork:
 	/* Create a stack frame */
 
-	mov		r0, sp					/* Save the value of the stack frame on entry */
+	mov		r0, sp					/* Save the value of the stack on entry */
 	sub		sp, sp, #VFORK_SIZEOF	/* Allocate the structure on the stack */
 
 	/* Save the volatile registers */
@@ -128,6 +128,7 @@ vfork:
 
 	/* Release the stack data and return the value returned by up_vfork */
 
+	ldr		lr, [sp, #VFORK_LR_OFFSET]
 	add		sp, sp, #VFORK_SIZEOF
 	mov		pc, lr
 	.size	vfork, .-vfork
diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S
index 0d9e144cd..386fca33c 100644
--- a/nuttx/arch/arm/src/armv7-m/vfork.S
+++ b/nuttx/arch/arm/src/armv7-m/vfork.S
@@ -105,7 +105,7 @@
 vfork:
 	/* Create a stack frame */
 
-	mov		r0, sp					/* Save the value of the stack frame on entry */
+	mov		r0, sp					/* Save the value of the stack on entry */
 	sub		sp, sp, #VFORK_SIZEOF	/* Allocate the structure on the stack */
 
 	/* Save the volatile registers */
@@ -131,6 +131,7 @@ vfork:
 
 	/* Release the stack data and return the value returned by up_vfork */
 
+	ldr		lr, [sp, #VFORK_LR_OFFSET]
 	add		sp, sp, #VFORK_SIZEOF
 	bx		lr
 	.size	vfork, .-vfork
diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c
index 3da602679..5349378bc 100644
--- a/nuttx/arch/arm/src/common/up_vfork.c
+++ b/nuttx/arch/arm/src/common/up_vfork.c
@@ -124,7 +124,7 @@
  *
  ****************************************************************************/
 
-pid_t up_vfork(struct vfork_s *context)
+pid_t up_vfork(const struct vfork_s *context)
 {
   _TCB *parent = (FAR _TCB *)g_readytorun.head;
   _TCB *child;
-- 
cgit v1.2.3


From 14f72f7a210648fe6eaaac3359ec76cab62c7278 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Tue, 8 Jan 2013 16:25:30 +0000
Subject: Add execv() and execl(); Move lm3s header files for compatibility

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5492 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                                |  12 +
 nuttx/Documentation/NuttxUserGuide.html        |  15 +-
 nuttx/arch/arm/include/lm3s/chip.h             | 123 ++++++
 nuttx/arch/arm/src/lm3s/chip.h                 |  79 +---
 nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h        | 113 ++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h   | 203 ++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h      | 128 +++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h       | 395 ++++++++++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h        | 247 ++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h  | 360 ++++++++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h        | 235 ++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h | 495 +++++++++++++++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h      | 125 +++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h       | 347 +++++++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h    |  69 ++++
 nuttx/arch/arm/src/lm3s/lm3s_epi.h             | 113 ------
 nuttx/arch/arm/src/lm3s/lm3s_ethernet.h        | 203 ----------
 nuttx/arch/arm/src/lm3s/lm3s_flash.h           | 128 -------
 nuttx/arch/arm/src/lm3s/lm3s_gpio.h            | 395 --------------------
 nuttx/arch/arm/src/lm3s/lm3s_i2c.h             | 247 ------------
 nuttx/arch/arm/src/lm3s/lm3s_memorymap.h       | 360 ------------------
 nuttx/arch/arm/src/lm3s/lm3s_ssi.h             | 235 ------------
 nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h      | 495 -------------------------
 nuttx/arch/arm/src/lm3s/lm3s_timer.h           | 125 -------
 nuttx/arch/arm/src/lm3s/lm3s_uart.h            | 347 -----------------
 nuttx/binfmt/binfmt_exec.c                     |  21 +-
 nuttx/include/nuttx/binfmt/binfmt.h            |   3 +-
 nuttx/include/unistd.h                         |   7 +
 nuttx/libc/Kconfig                             |  48 +++
 nuttx/libc/unistd/Make.defs                    |   4 +
 nuttx/libc/unistd/lib_execl.c                  | 146 ++++++++
 nuttx/libc/unistd/lib_execv.c                  | 168 +++++++++
 nuttx/tools/cfgdefine.c                        |   1 +
 33 files changed, 3269 insertions(+), 2723 deletions(-)
 create mode 100644 nuttx/arch/arm/include/lm3s/chip.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_epi.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_ethernet.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_flash.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_gpio.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_i2c.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_ssi.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_timer.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_uart.h
 create mode 100644 nuttx/libc/unistd/lib_execl.c
 create mode 100644 nuttx/libc/unistd/lib_execv.c

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index e2d8a586b..ee6b088cf 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3880,4 +3880,16 @@
 	  OS layered architecture.
 	* include/unistd.h, arch/arch/src/*:  Implement a simple vfork().
 	  On initial checkin, this API is available only for ARM platforms.
+	* binfmt/binfmt_exec.c: exec() now sets the priority of the new task
+	  to the same priority as the current task (instead of the arbirtrary
+	  value of 50).
+	* libc/unisted/lib_execv.c and lib_execl.c:  New, somewhat flawed,
+	  implementations of execv() and execl().
+	* tools/cfgdefine.c:  Strips quotes from CONFIG_EXECFUNCS_SYMTAB
+	  value.
+	* arch/arm/include/lm3s/chip.h:  Move chip definitions into
+	  public include area for compatibility with other architectures.
+	* arch/arm/src/lm3s/chip:  Move register definition header files
+	  into a new chip/ sub-directory.
+
 
diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html
index 5c76737e5..918b69d0f 100644
--- a/nuttx/Documentation/NuttxUserGuide.html
+++ b/nuttx/Documentation/NuttxUserGuide.html
@@ -202,6 +202,8 @@ paragraphs.
   <li><a href="#taskrestart">2.1.6 task_restart</a></li>
   <li><a href="#getpid">2.1.7 getpid</a></li>
   <li><a href="#vfork">2.1.8 vfork</a></li>
+  <li><a href="#execv">2.1.9 execv</a></li>
+  <li><a href="#execl">2.1.10 execl</a></li>
 </ul>
 
 <H3><a name="taskcreate">2.1.1 task_create</a></H3>
@@ -648,6 +650,9 @@ pid_t vfork(void);
   Compatible with the Unix interface of the same name.
 </p>
 
+<H3><a name="execv">2.1.9 execv</a></H3>
+<H3><a name="execl">2.1.10 execl</a></H3>
+
 <table width ="100%">
   <tr bgcolor="#e4e4e4">
   <td>
@@ -6798,6 +6803,12 @@ FAR char *getcwd(FAR char *buf, size_t size);
 
 int     unlink(FAR const char *pathname);
 int     rmdir(FAR const char *pathname);
+
+#ifdef CONFIG_LIBC_EXECFUNCS
+int     execl(FAR const char *path, ...);
+int     execv(FAR const char *path, FAR char *const argv[]);
+#endif
+
 int     getopt(int argc, FAR char *const argv[], FAR const char *optstring);
 </pre></ul>
 </a>
@@ -8198,7 +8209,9 @@ notify a task when a message is available on a queue.
   <li><a href="#driveroperations">Driver operations</a></li>
   <li><a href="#drvrunistdops">dup</a></li>
   <li><a href="#drvrunistdops">dup2</a></li>
+  <li><a href="#execl">execl</a></li>
   <li><a href="#mmapxip">eXecute In Place (XIP)</a></li>
+  <li><a href="#execv">execv</a></li>
   <li><a href="#exit">exit</a></li>
   <li><a href="#fatsupport">FAT File System Support</a></li>
   <li><a href="#standardio">fclose</a></li>
@@ -8333,9 +8346,9 @@ notify a task when a message is available on a queue.
   <li><a href="#mmapxip">ROMFS</a></li>
   <li><a href="#schedgetparam">sched_getparam</a></li>
   <li><a href="#schedgetprioritymax">sched_get_priority_max</a></li>
+  <li><a href="#schedgetprioritymin">sched_get_priority_min</a></li>
 </td>
 <td valign="top">
-  <li><a href="#schedgetprioritymin">sched_get_priority_min</a></li>
   <li><a href="#schedgetrrinterval">sched_get_rr_interval</a></li>
   <li><a href="#schedlockcount">sched_lockcount</a></li>
   <li><a href="#schedlock">sched_lock</a></li>
diff --git a/nuttx/arch/arm/include/lm3s/chip.h b/nuttx/arch/arm/include/lm3s/chip.h
new file mode 100644
index 000000000..d7e98a461
--- /dev/null
+++ b/nuttx/arch/arm/include/lm3s/chip.h
@@ -0,0 +1,123 @@
+/************************************************************************************
+ * arch/arm/include/lm3s/chip.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_LM3S_CHIP_H
+#define __ARCH_ARM_INCLUDE_LM3S_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM3S_ETHTS              /* No timestamp register */
+#  define LM3S_NSSI            2  /* Two SSI modules */
+#  define LM3S_NUARTS          2  /* Two UART modules */
+#  define LM3S_NI2C            2  /* Two I2C modules */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            0  /* No PWM generator modules */
+#  define LM3S_NQEI            0  /* No quadrature encoders */
+#  define LM3S_NPORTS          8  /* 8 Ports (GPIOA-H) 5-38 GPIOs */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+#  define LM3S_NTIMERS         3  /* Three general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM3S_ETHTS              /* No timestamp register */
+#  define LM3S_NSSI            1  /* One SSI module */
+#  define LM3S_NUARTS          2  /* Two UART modules */
+#  define LM3S_NI2C            1  /* Two I2C modules */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            1  /* One PWM generator module */
+#  define LM3S_NQEI            0  /* No quadrature encoders */
+#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM3S_ETHTS              /* No timestamp register */
+#  define LM3S_NSSI            1  /* One SSI module */
+#  define LM3S_NUARTS          3  /* Three UART modules */
+#  define LM3S_NI2C            2  /* Two I2C modules */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            3  /* Three PWM generator modules */
+#  define LM3S_NQEI            2  /* Two quadrature encoders */
+#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM3S_ETHTS              /* No timestamp register */
+#  define LM3S_NSSI            2  /* Two SSI modules */
+#  define LM3S_NUARTS          3  /* Three UART modules */
+#  define LM3S_NI2C            2  /* Two I2C modules */
+#  define LM3S_NADC            2  /* Two ADC module */
+#  define LM3S_CAN             2  /* Two CAN module */
+#  define LM3S_NPWM            4  /* Four PWM generator modules */
+#  define LM3S_NQEI            2  /* Two quadrature encoders */
+#  define LM3S_NPORTS          9  /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LM3S_NSSI            1  /* One SSI module */
+#  define LM3S_NUARTS          3  /* Two UART modules */
+#  define LM3S_NI2C            2  /* One I2C module */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            3  /* Three PWM generator modules */
+#  define LM3S_NQEI            2  /* Two quadrature encoders */
+#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 5-42 GPIOs */
+#  define LC3S_CANCONTROLLER   1  /* One CAN controller */
+#else
+#  error "Capabilities not specified for this LM3S chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_LM3S_CHIP_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h
index 1e22f6221..1e96b5222 100644
--- a/nuttx/arch/arm/src/lm3s/chip.h
+++ b/nuttx/arch/arm/src/lm3s/chip.h
@@ -41,83 +41,22 @@
  ************************************************************************************/
 
 #include <nuttx/config.h>
+#include <arch/lm3s/chip.h>
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
-/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            2  /* Two SSI modules */
-#  define LM3S_NUARTS          2  /* Two UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            0  /* No PWM generator modules */
-#  define LM3S_NQEI            0  /* No quadrature encoders */
-#  define LM3S_NPORTS          8  /* 8 Ports (GPIOA-H) 5-38 GPIOs */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-#  define LM3S_NTIMERS         3  /* Three general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          2  /* Two UART modules */
-#  define LM3S_NI2C            1  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            1  /* One PWM generator module */
-#  define LM3S_NQEI            0  /* No quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          3  /* Three UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            3  /* Three PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            2  /* Two SSI modules */
-#  define LM3S_NUARTS          3  /* Three UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            2  /* Two ADC module */
-#  define LM3S_CAN             2  /* Two CAN module */
-#  define LM3S_NPWM            4  /* Four PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          9  /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          3  /* Two UART modules */
-#  define LM3S_NI2C            2  /* One I2C module */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            3  /* Three PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 5-42 GPIOs */
-#  define LC3S_CANCONTROLLER   1  /* One CAN controller */
-#else
-#  error "Capabilities not specified for this LM3S chip"
-#endif
-
 /* Then get all of the register definitions */
 
-#include "lm3s_memorymap.h"      /* Memory map */
-#include "lm3s_syscontrol.h"     /* System control module */
-#include "lm3s_gpio.h"           /* GPIO modules */
-#include "lm3s_uart.h"           /* UART modules */
-#include "lm3s_i2c.h"            /* I2C modules */
-#include "lm3s_ssi.h"            /* SSI modules */
-#include "lm3s_ethernet.h"       /* Ethernet MAC and PHY */
-#include "lm3s_flash.h"          /* FLASH */
+#include "chip/lm_memorymap.h"    /* Memory map */
+#include "chip/lm3s_syscontrol.h" /* System control module */
+#include "chip/lm3s_gpio.h"       /* GPIO modules */
+#include "chip/lm3s_uart.h"       /* UART modules */
+#include "chip/lm3s_i2c.h"        /* I2C modules */
+#include "chip/lm3s_ssi.h"        /* SSI modules */
+#include "chip/lm3s_ethernet.h"   /* Ethernet MAC and PHY */
+#include "chip/lm3s_flash.h"      /* FLASH */
 
 /************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h
new file mode 100644
index 000000000..5b54d44ac
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h
@@ -0,0 +1,113 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_epi.h
+ *
+ *   Copyright (C) 2009-2013 Max Neklyudov. All rights reserved.
+ *   Author: Max Neklyudov <macscomp@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* External Peripheral Interface Register Offsets ***********************************/
+
+#define LM3S_EPI_CFG_OFFSET           0x000
+#define LM3S_EPI_SDRAMCFG_OFFSET      0x010
+#define LM3S_EPI_ADDRMAP_OFFSET       0x01C
+#define LM3S_EPI_STAT_OFFSET          0x060
+#define LM3S_EPI_BAUD_OFFSET          0x004
+
+/* External Peripheral Interface Register Addresses *********************************/
+
+#define LM3S_EPI0_CFG                 (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
+#define LM3S_EPI0_SDRAMCFG            (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
+#define LM3S_EPI0_ADDRMAP             (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
+#define LM3S_EPI0_STAT                (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
+#define LM3S_EPI0_BAUD                (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
+
+/* External Peripheral Interface Register Bit Definitions ***************************/
+
+/* EPI Configuration (EPICFG), offset 0x000 */
+
+#define EPI_CFG_MODE_SHIFT            0         /* Bits 3-0: Mode Select */
+#define EPI_CFG_MODE_MASK             (0x1f << EPI_CFG_MODE_SHIFT)
+#  define EPI_CFG_MODE_SDRAM          (0x11 << EPI_CFG_MODE_SHIFT)  /* SDRAM + BLKEN */
+
+/* EPI Address Map (EPIADDRMAP), offset 0x01C */
+
+#define EPI_ADDRMAP_ERADR_SHIFT       0       /* Bits 1-0: External RAM Address */
+#define EPI_ADDRMAP_ERADR_MASK        (0x3 << EPI_ADDRMAP_ERADR_SHIFT)
+#  define EPI_ADDRMAP_ERADR_6         (0x1 << EPI_ADDRMAP_ERADR_SHIFT)
+#  define EPI_ADDRMAP_ERADR_8         (0x2 << EPI_ADDRMAP_ERADR_SHIFT)
+#define EPI_ADDRMAP_ERSZ_SHIFT        2       /* Bits 3-2: External RAM Size */
+#define EPI_ADDRMAP_ERSZ_MASK         (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_256B       (0x0 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_64KB       (0x1 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_16MB       (0x2 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_512MB      (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
+
+/* EPI Status (EPISTAT), offset 0x060 */
+
+#define EPI_STAT_INITSEQ_SHIFT        6       /* Bits 6: Initialization Sequence */
+#define EPI_STAT_INITSEQ_MASK         (0x1 << EPI_STAT_INITSEQ_SHIFT)
+
+/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */
+
+#define EPI_SDRAMCFG_SIZE_SHIFT       0       /* Bits 1-0: Size of SDRAM */
+#define EPI_SDRAMCFG_SIZE_MASK        (3 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_8MB       (0x0 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_16MB      (0x1 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_32MB      (0x2 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_64MB      (0x3 << EPI_SDRAMCFG_SIZE_SHIFT)
+#define EPI_SDRAMCFG_RFSH_SHIFT       16      /* Bits 26-16: Refresh Counter */
+#define EPI_SDRAMCFG_RFSH_MASK        (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT)
+#  define EPI_SDRAMCFG_RFSH(n)        ((n) << EPI_SDRAMCFG_RFSH_SHIFT)
+#define EPI_SDRAMCFG_FREQ_SHIFT       30      /* EPI Frequency Range */
+#define EPI_SDRAMCFG_FREQ_MASK        (3 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_0_15MHZ   (0x0 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_15_30MHZ  (0x1 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_30_50MHZ  (0x2 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT)
+
+/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */
+
+#define EPI_BAUD_COUNT0_SHIFT         0
+#define EPI_BAUD_COUNT0_MASK          (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
+#  define EPI_BAUD_COUNT0(n)          ((n) << EPI_BAUD_COUNT0_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h
new file mode 100644
index 000000000..940686e7d
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h
@@ -0,0 +1,203 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_ethernet.h
+ *
+ *   Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/net/mii.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Ethernet Controller Register Offsets *********************************************/
+
+/* Ethernet MAC Register Offsets */
+
+#define LM3S_MAC_RIS_OFFSET   0x000 /* Ethernet MAC Raw Interrupt Status */
+#define LM3S_MAC_IACK_OFFSET  0x000 /* Ethernet MAC Acknowledge */
+#define LM3S_MAC_IM_OFFSET    0x004 /* Ethernet MAC Interrupt Mask */
+#define LM3S_MAC_RCTL_OFFSET  0x008 /* Ethernet MAC Receive Control */
+#define LM3S_MAC_TCTL_OFFSET  0x00c /* Ethernet MAC Transmit Control */
+#define LM3S_MAC_DATA_OFFSET  0x010 /* Ethernet MAC Data */
+#define LM3S_MAC_IA0_OFFSET   0x014 /* Ethernet MAC Individual Address 0 */
+#define LM3S_MAC_IA1_OFFSET   0x018 /* Ethernet MAC Individual Address 1 */
+#define LM3S_MAC_THR_OFFSET   0x01c /* Ethernet MAC Threshold */
+#define LM3S_MAC_MCTL_OFFSET  0x020 /* Ethernet MAC Management Control */
+#define LM3S_MAC_MDV_OFFSET   0x024 /* Ethernet MAC Management Divider */
+#define LM3S_MAC_MTXD_OFFSET  0x02c /* Ethernet MAC Management Transmit Data */
+#define LM3S_MAC_MRXD_OFFSET  0x030 /* Ethernet MAC Management Receive Data */
+#define LM3S_MAC_NP_OFFSET    0x034 /* Ethernet MAC Number of Packets */
+#define LM3S_MAC_TR_OFFSET    0x038 /* Ethernet MAC Transmission Request */
+#ifdef LM3S_ETHTS
+#  define LM3S_MAC_TS_OFFSET  0x03c /* Ethernet MAC Time Stamp Configuration */
+#endif
+
+/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
+
+/* Ethernet Controller Register Addresses *******************************************/
+
+#define LM3S_MAC_RIS          (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
+#define LM3S_MAC_IACK         (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
+#define LM3S_MAC_IM           (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
+#define LM3S_MAC_RCTL         (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
+#define LM3S_MAC_TCTL         (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
+#define LM3S_MAC_DATA         (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
+#define LM3S_MAC_IA0          (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
+#define LM3S_MAC_IA1          (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
+#define LM3S_MAC_THR          (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
+#define LM3S_MAC_MCTL         (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
+#define LM3S_MAC_MDV          (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
+#define LM3S_MAC_MTXD         (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
+#define LM3S_MAC_MRXD         (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
+#define LM3S_MAC_NP           (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
+#define LM3S_MAC_TR           (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
+#ifdef LM3S_ETHTS
+#  define LM3S_MAC_TS         (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
+#endif
+
+/* Memory Mapped MII Management Registers */
+
+#define MAC_MII_MCR           (LM3S_ETHCON_BASE + MII_MCR)
+#define MAC_MII_MSR           (LM3S_ETHCON_BASE + MII_MSR)
+#define MAC_MII_PHYID1        (LM3S_ETHCON_BASE + MII_PHYID1)
+#define MAC_MII_PHYID2        (LM3S_ETHCON_BASE + MII_PHYID2)
+#define MAC_MII_ADVERTISE     (LM3S_ETHCON_BASE + MII_ADVERTISE)
+#define MAC_MII_LPA           (LM3S_ETHCON_BASE + MII_LPA)
+#define MAC_MII_EXPANSION     (LM3S_ETHCON_BASE + MII_EXPANSION)
+#define MAC_MII_VSPECIFIC     (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
+#define MAC_MII_INTCS         (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
+#define MAC_MII_DIAGNOSTIC    (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
+#define MAC_MII_XCVRCONTROL   (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
+#define MAC_MII_LEDCONFIG     (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
+#define MAC_MII_MDICONTROL    (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
+
+/* Ethernet Controller Register Bit Definitions *************************************/
+
+/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
+
+#define MAC_RIS_RXINT         (1 << 0)  /* Bit 0:  Packet Received */
+#define MAC_RIS_TXER          (1 << 1)  /* Bit 1:  Transmit Error */
+#define MAC_RIS_TXEMP         (1 << 2)  /* Bit 2:  Transmit FIFO Empty */
+#define MAC_RIS_FOV           (1 << 3)  /* Bit 3:  FIFO Overrun */
+#define MAC_RIS_RXER          (1 << 4)  /* Bit 4:  Receive Error */
+#define MAC_RIS_MDINT         (1 << 5)  /* Bit 5:  MII Transaction Complete */
+#define MAC_RIS_PHYINT        (1 << 6)  /* Bit 6:  PHY Interrupt */
+
+#define MAC_IACK_RXINT        (1 << 0)  /* Bit 0:  Clear Packet Received */
+#define MAC_IACK_TXER         (1 << 1)  /* Bit 1:  Clear Transmit Error */
+#define MAC_IACK_TXEMP        (1 << 2)  /* Bit 2:  Clear Transmit FIFO Empty */
+#define MAC_IACK_FOV          (1 << 3)  /* Bit 3:  Clear FIFO Overrun */
+#define MAC_IACK_RXER         (1 << 4)  /* Bit 4:  Clear Receive Error */
+#define MAC_IACK_MDINT        (1 << 5)  /* Bit 5:  Clear MII Transaction Complete */
+#define MAC_IACK_PHYINT       (1 << 6)  /* Bit 6:  Clear PHY Interrupt */
+
+/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
+
+#define MAC_IM_RXINTM         (1 << 0)  /* Bit 0:  Mask Packet Received */
+#define MAC_IM_TXERM          (1 << 1)  /* Bit 1:  Mask Transmit Error */
+#define MAC_IM_TXEMPM         (1 << 2)  /* Bit 2:  Mask Transmit FIFO Empty */
+#define MAC_IM_FOVM           (1 << 3)  /* Bit 3:  Mask FIFO Overrun */
+#define MAC_IM_RXERM          (1 << 4)  /* Bit 4:  Mask Receive Error */
+#define MAC_IM_MDINTM         (1 << 5)  /* Bit 5:  Mask MII Transaction Complete */
+#define MAC_IM_PHYINTM        (1 << 6)  /* Bit 6:  Mask PHY Interrupt */
+#define MAC_IM_ALLINTS        0x7f
+
+/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
+
+#define MAC_RCTL_RXEN         (1 << 0)  /* Bit 0:  Enable Receiver */
+#define MAC_RCTL_AMUL         (1 << 1)  /* Bit 1:  Enable Multicast Frames */
+#define MAC_RCTL_PRMS         (1 << 2)  /* Bit 2:  Enable Promiscuous Mode */
+#define MAC_RCTL_BADCRC       (1 << 3)  /* Bit 3:  Enable Reject Bad CRC */
+#define MAC_RCTL_RSTFIFO      (1 << 4)  /* Bit 4:  Clear Receive FIFO */
+
+/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
+
+#define MAC_TCTL_TXEN         (1 << 0)  /* Bit 0:  Enable Transmitter */
+#define MAC_TCTL_PADEN        (1 << 1)  /* Bit 1:  Enable Packet Padding */
+#define MAC_TCTL_CRC          (1 << 2)  /* Bit 2:  Enable CRC Generation */
+#define MAC_TCTL_DUPLEX       (1 << 4)  /* Bit 4:  Enable Duplex Mode */
+
+/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
+
+#define MAC_THR_MASK          0x3f      /* Bits 5-0: Threshold Value */
+
+/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
+
+#define MAC_MCTL_START        (1 << 0)  /* Bit 0:  MII Register Transaction Enable */
+#define MAC_MCTL_WRITE        (1 << 1)  /* Bit 1:  MII Register Transaction Type */
+#define MAC_MCTL_REGADR_SHIFT 3         /* Bits 7-3: MII Register Address */
+#define MAC_MCTL_REGADR_MASK  (0x1f << MAC_MCTL_REGADR_SHIFT)
+
+/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
+
+#define MAC_MDV_MASK          0xff      /* Bits 7-0: Clock Divider */
+
+/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
+
+#define MAC_MTXD_MASK         0xffff    /* Bits 15-0: MII Register Transmit Data */
+
+/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
+
+#define MAC_MTRD_MASK         0xffff    /* Bits 15-0: MII Register Receive Data */
+
+/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
+
+#define MAC_NP_MASK           0x3f      /* Bits 5-0: Number of Packets in Receive FIFO */
+
+/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
+
+#define MAC_TR_NEWTX          (1 << 0)  /* Bit 0:  New Transmission */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h
new file mode 100644
index 000000000..2bd8956b0
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h
@@ -0,0 +1,128 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_flash.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* FLASH register offsets ***********************************************************/
+
+/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
+ * control base address of LM3S_FLASHCON_BASE.
+ */
+
+#define LM3S_FLASH_FMA_OFFSET       0x000 /* Flash memory address */
+#define LM3S_FLASH_FMD_OFFSET       0x004 /* Flash memory data */
+#define LM3S_FLASH_FMC_OFFSET       0x008 /* Flash memory control */
+#define LM3S_FLASH_FCRIS_OFFSET     0x00c /* Flash controller raw interrupt status */
+#define LM3S_FLASH_FCIM_OFFSET      0x010 /* Flash controller interrupt mask */
+#define LM3S_FLASH_FCMISC_OFFSET    0x014 /* Flash controller masked interrupt status and clear */ */
+
+/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
+ * System Control base address of LM3S_SYSCON_BASE
+ */
+
+#define LM3S_FLASH_FMPRE_OFFSET     0x130 /* Flash memory protection read enable */
+#define LM3S_FLASH_FMPPE_OFFSET     0x134 /* Flash memory protection program enable */
+#define LM3S_FLASH_USECRL_OFFSET    0x140 /* USec Reload */
+#define LM3S_FLASH_USERDBG_OFFSET   0x1d0 /* User Debug */
+#define LM3S_FLASH_USERREG0_OFFSET  0x1e0 /* User Register 0 */
+#define LM3S_FLASH_USERREG1_OFFSET  0x1e4 /* User Register 1 */
+#define LM3S_FLASH_FMPRE0_OFFSET    0x200 /* Flash Memory Protection Read Enable 0 */
+#define LM3S_FLASH_FMPRE1_OFFSET    0x204 /* Flash Memory Protection Read Enable 1 */
+#define LM3S_FLASH_FMPRE2_OFFSET    0x208 /* Flash Memory Protection Read Enable 2 */
+#define LM3S_FLASH_FMPRE3_OFFSET    0x20c /* Flash Memory Protection Read Enable 3 */
+#define LM3S_FLASH_FMPPE0_OFFSET    0x400 /* Flash Memory Protection Program Enable 0 */
+#define LM3S_FLASH_FMPPE1_OFFSET    0x404 /* Flash Memory Protection Program Enable 1 */
+#define LM3S_FLASH_FMPPE2_OFFSET    0x408 /* Flash Memory Protection Program Enable 2 */
+#define LM3S_FLASH_FMPPE3_OFFSET    0x40c /*  Flash Memory Protection Program Enable 3 */
+
+/* FLASH register addresses *********************************************************/
+
+/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
+ * control base address of LM3S_FLASHCON_BASE.
+ */
+
+#define LM3S_FLASH_FMA              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
+#define LM3S_FLASH_FMD              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
+#define LM3S_FLASH_FMC              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
+#define LM3S_FLASH_FCRIS            (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
+#define LM3S_FLASH_FCIM             (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
+#define LM3S_FLASH_FCMISC           (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
+
+/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
+ * System Control base address of LM3S_SYSCON_BASE
+ */
+
+#define LM3S_FLASH_FMPRE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
+#define LM3S_FLASH_FMPPE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
+#define LM3S_FLASH_USECRL           (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
+#define LM3S_FLASH_USERDBG          (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
+#define LM3S_FLASH_USERREG0         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
+#define LM3S_FLASH_USERREG1         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
+#define LM3S_FLASH_FMPRE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
+#define LM3S_FLASH_FMPRE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
+#define LM3S_FLASH_FMPRE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
+#define LM3S_FLASH_FMPRE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
+#define LM3S_FLASH_FMPPE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
+#define LM3S_FLASH_FMPPE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
+#define LM3S_FLASH_FMPPE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
+#define LM3S_FLASH_FMPPE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
+
+/* FLASH register bit defitiions ****************************************************/
+/* To be provided */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h
new file mode 100644
index 000000000..7253c1e7a
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h
@@ -0,0 +1,395 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_gpio.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* GPIO Register Offsets ************************************************************/
+
+#define LM3S_GPIO_DATA_OFFSET         0x000 /* GPIO Data */
+#define LM3S_GPIO_DIR_OFFSET          0x400 /* GPIO Direction */
+#define LM3S_GPIO_IS_OFFSET           0x404 /* GPIO Interrupt Sense */
+#define LM3S_GPIO_IBE_OFFSET          0x408 /* GPIO Interrupt Both Edges */
+#define LM3S_GPIO_IEV_OFFSET          0x40c /* GPIO Interrupt Event */
+#define LM3S_GPIO_IM_OFFSET           0x410 /* GPIO Interrupt Mask */
+#define LM3S_GPIO_RIS_OFFSET          0x414 /* GPIO Raw Interrupt Status */
+#define LM3S_GPIO_MIS_OFFSET          0x418 /* GPIO Masked Interrupt Status */
+#define LM3S_GPIO_ICR_OFFSET          0x41c /* GPIO Interrupt Clear */
+#define LM3S_GPIO_AFSEL_OFFSET        0x420 /* GPIO Alternate Function */
+#define LM3S_GPIO_DR2R_OFFSET         0x500 /* Select GPIO 2-mA Drive Select */
+#define LM3S_GPIO_DR4R_OFFSET         0x504 /* GPIO 4-mA Drive Select */
+#define LM3S_GPIO_DR8R_OFFSET         0x508 /* GPIO 8-mA Drive Select */
+#define LM3S_GPIO_ODR_OFFSET          0x50c /* GPIO Open Drain Select */
+#define LM3S_GPIO_PUR_OFFSET          0x510 /* GPIO Pull-Up Select */
+#define LM3S_GPIO_PDR_OFFSET          0x514 /* GPIO Pull-Down Select */
+#define LM3S_GPIO_SLR_OFFSET          0x518 /* GPIO Slew Rate Control Select */
+#define LM3S_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
+#define LM3S_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
+#define LM3S_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
+#define LM3S_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
+#define LM3S_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
+#define LM3S_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
+#define LM3S_GPIO_PERIPHID7_OFFSET    0xfdc /* GPIO Peripheral Identification 7 */
+#define LM3S_GPIO_PERIPHID0_OFFSET    0xfe0 /* GPIO Peripheral Identification 0 */
+#define LM3S_GPIO_PERIPHID1_OFFSET    0xfe4 /* GPIO Peripheral Identification 1 */
+#define LM3S_GPIO_PERIPHID2_OFFSET    0xfe8 /* GPIO Peripheral Identification 2 */
+#define LM3S_GPIO_PERIPHID3_OFFSET    0xfec /* GPIO Peripheral Identification 3 */
+#define LM3S_GPIO_PCELLID0_OFFSET     0xff0 /* GPIO PrimeCell Identification 0 */
+#define LM3S_GPIO_PCELLID1_OFFSET     0xff4 /* GPIO PrimeCell Identification 1 */
+#define LM3S_GPIO_PCELLID2_OFFSET     0xff8 /* GPIO PrimeCell Identification 2 */
+#define LM3S_GPIO_PCELLID3_OFFSET     0xffc /* GPIO PrimeCell Identification 3*/
+
+/* GPIO Register Addresses **********************************************************/
+
+#define LM3S_GPIOA_DATA               (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOA_DIR                (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOA_IS                 (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOA_IBE                (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOA_IEV                (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOA_IM                 (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOA_RIS                (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOA_MIS                (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOA_ICR                (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOA_AFSEL              (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOA_DR2R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOA_DR4R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOA_DR8R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOA_ODR                (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOA_PUR                (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOA_PDR                (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOA_SLR                (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOA_DEN                (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOA_LOCK               (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOA_CR                 (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOA_PERIPHID4          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOA_PERIPHID5          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOA_PERIPHID6          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOA_PERIPHID7          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOA_PERIPHID0          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOA_PERIPHID1          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOA_PERIPHID2          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOA_PERIPHID3          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOA_PCELLID0           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOA_PCELLID1           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOA_PCELLID2           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOA_PCELLID3           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOB_DATA               (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOB_DIR                (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOB_IS                 (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOB_IBE                (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOB_IEV                (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOB_IM                 (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOB_RIS                (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOB_MIS                (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOB_ICR                (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOB_AFSEL              (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOB_DR2R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOB_DR4R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOB_DR8R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOB_ODR                (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOB_PUR                (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOB_PDR                (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOB_SLR                (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOB_DEN                (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOB_LOCK               (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOB_CR                 (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOB_PERIPHID4          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOB_PERIPHID5          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOB_PERIPHID6          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOB_PERIPHID7          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOB_PERIPHID0          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOB_PERIPHID1          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOB_PERIPHID2          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOB_PERIPHID3          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOB_PCELLID0           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOB_PCELLID1           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOB_PCELLID2           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOB_PCELLID3           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOC_DATA               (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOC_DIR                (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOC_IS                 (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOC_IBE                (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOC_IEV                (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOC_IM                 (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOC_RIS                (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOC_MIS                (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOC_ICR                (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOC_AFSEL              (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOC_DR2R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOC_DR4R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOC_DR8R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOC_ODR                (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOC_PUR                (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOC_PDR                (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOC_SLR                (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOC_DEN                (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOC_LOCK               (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOC_CR                 (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOC_PERIPHID4          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOC_PERIPHID5          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOC_PERIPHID6          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOC_PERIPHID7          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOC_PERIPHID0          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOC_PERIPHID1          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOC_PERIPHID2          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOC_PERIPHID3          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOC_PCELLID0           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOC_PCELLID1           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOC_PCELLID2           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOC_PCELLID3           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOD_DATA               (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOD_DIR                (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOD_IS                 (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOD_IBE                (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOD_IEV                (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOD_IM                 (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOD_RIS                (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOD_MIS                (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOD_ICR                (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOD_AFSEL              (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOD_DR2R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOD_DR4R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOD_DR8R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOD_ODR                (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOD_PUR                (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOD_PDR                (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOD_SLR                (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOD_DEN                (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOD_LOCK               (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOD_CR                 (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOD_PERIPHID4          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOD_PERIPHID5          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOD_PERIPHID6          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOD_PERIPHID7          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOD_PERIPHID0          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOD_PERIPHID1          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOD_PERIPHID2          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOD_PERIPHID3          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOD_PCELLID0           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOD_PCELLID1           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOD_PCELLID2           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOD_PCELLID3           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOE_DATA               (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOE_DIR                (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOE_IS                 (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOE_IBE                (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOE_IEV                (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOE_IM                 (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOE_RIS                (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOE_MIS                (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOE_ICR                (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOE_AFSEL              (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOE_DR2R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOE_DR4R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOE_DR8R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOE_ODR                (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOE_PUR                (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOE_PDR                (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOE_SLR                (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOE_DEN                (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOE_LOCK               (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOE_CR                 (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOE_PERIPHID4          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOE_PERIPHID5          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOE_PERIPHID6          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOE_PERIPHID7          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOE_PERIPHID0          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOE_PERIPHID1          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOE_PERIPHID2          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOE_PERIPHID3          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOE_PCELLID0           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOE_PCELLID1           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOE_PCELLID2           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOE_PCELLID3           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOF_DATA               (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOF_DIR                (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOF_IS                 (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOF_IBE                (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOF_IEV                (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOF_IM                 (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOF_RIS                (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOF_MIS                (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOF_ICR                (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOF_AFSEL              (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOF_DR2R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOF_DR4R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOF_DR8R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOF_ODR                (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOF_PUR                (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOF_PDR                (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOF_SLR                (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOF_DEN                (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOF_LOCK               (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOF_CR                 (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOF_PERIPHID4          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOF_PERIPHID5          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOF_PERIPHID6          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOF_PERIPHID7          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOF_PERIPHID0          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOF_PERIPHID1          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOF_PERIPHID2          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOF_PERIPHID3          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOF_PCELLID0           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOF_PCELLID1           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOF_PCELLID2           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOF_PCELLID3           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOG_DATA               (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOG_DIR                (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOG_IS                 (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOG_IBE                (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOG_IEV                (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOG_IM                 (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOG_RIS                (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOG_MIS                (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOG_ICR                (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOG_AFSEL              (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOG_DR2R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOG_DR4R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOG_DR8R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOG_ODR                (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOG_PUR                (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOG_PDR                (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOG_SLR                (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOG_DEN                (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOG_LOCK               (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOG_CR                 (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOG_PERIPHID4          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOG_PERIPHID5          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOG_PERIPHID6          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOG_PERIPHID7          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOG_PERIPHID0          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOG_PERIPHID1          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOG_PERIPHID2          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOG_PERIPHID3          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOG_PCELLID0           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOG_PCELLID1           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOG_PCELLID2           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOG_PCELLID3           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOH_DATA               (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOH_DIR                (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOH_IS                 (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOH_IBE                (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOH_IEV                (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOH_IM                 (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOH_RIS                (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOH_MIS                (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOH_ICR                (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOH_AFSEL              (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOH_DR2R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOH_DR4R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOH_DR8R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOH_ODR                (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOH_PUR                (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOH_PDR                (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOH_SLR                (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOH_DEN                (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOH_LOCK               (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOH_CR                 (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOH_PERIPHID4          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOH_PERIPHID5          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOH_PERIPHID6          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOH_PERIPHID7          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOH_PERIPHID0          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOH_PERIPHID1          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOH_PERIPHID2          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOH_PERIPHID3          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOH_PCELLID0           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOH_PCELLID1           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOH_PCELLID2           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOH_PCELLID3           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOJ_DATA               (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOJ_DIR                (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOJ_IS                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOJ_IBE                (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOJ_IEV                (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOJ_IM                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOJ_RIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOJ_MIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOJ_ICR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOJ_AFSEL              (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOJ_DR2R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOJ_DR4R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOJ_DR8R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOJ_ODR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOJ_PUR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOJ_PDR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOJ_SLR                (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOJ_DEN                (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOJ_LOCK               (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOJ_CR                 (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOJ_PERIPHID4          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOJ_PERIPHID5          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOJ_PERIPHID6          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOJ_PERIPHID7          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOJ_PERIPHID0          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOJ_PERIPHID1          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOJ_PERIPHID2          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOJ_PERIPHID3          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOJ_PCELLID0           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOJ_PCELLID1           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOJ_PCELLID2           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOJ_PCELLID3           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h
new file mode 100644
index 000000000..71ebe8fcf
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h
@@ -0,0 +1,247 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_i2c.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* I2C Register Offsets *************************************************************/
+
+/* I2C Master */
+
+#define LM3S_I2CM_SA_OFFSET  0x000 /* I2C Master Slave Address */
+#define LM3S_I2CM_CS_OFFSET  0x004 /* I2C Master Control/Status */
+#define LM3S_I2CM_DR_OFFSET  0x008 /* I2C Master Data */
+#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
+#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
+#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
+#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
+#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
+#define LM3S_I2CM_CR_OFFSET  0x020 /* I2C Master Configuration */
+
+/* I2C Slave */
+
+#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
+#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
+#define LM3S_I2CS_DR_OFFSET  0x008 /* I2C Slave Data */
+#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
+#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
+#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
+#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
+
+/* I2C Register Addresses ***********************************************************/
+
+#if LM3S_NI2C > 0
+
+/* I2C Master */
+
+#define LM3S_I2CM_BASE(n)    (LM3S_I2CM0_BASE + (n)*0x1000)
+#define LM3S_I2CM_SA(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM_CS(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM_DR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM_TPR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM_IMR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM_RIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM_MIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM_ICR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM_CR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
+
+/* I2C Slave */
+
+#define LM3S_I2CS_BASE(n)    (LM3S_I2CS0_BASE + (n)*0x1000)
+#define LM3S_I2CS_OAR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS_CSR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS_DR(n)      (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS_IMR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS_RIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS_MIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS_ICR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
+
+/* I2C0 Master */
+
+#define LM3S_I2CM0_SA        (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM0_CS        (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM0_DR        (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM0_TPR       (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM0_IMR       (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM0_RIS       (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM0_MIS       (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM0_ICR       (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM0_CR        (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
+
+/* I2C0 Slave */
+
+#define LM3S_I2CS0_OAR       (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS0_CSR       (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS0_DR        (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS0_IMR       (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS0_RIS       (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS0_MIS       (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS0_ICR       (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
+
+#if LM3S_NI2C > 1
+
+/* I2C1 Master */
+
+#define LM3S_I2CM1_SA        (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM1_CS        (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM1_DR        (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM1_TPR       (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM1_IMR       (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM1_RIS       (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM1_MIS       (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM1_ICR       (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM1_CR        (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
+
+/* I2C1 Slave */
+
+#define LM3S_I2CS1_OAR       (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS1_CSR       (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS1_DR        (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS1_IMR       (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS1_RIS       (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS1_MIS       (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS1_ICR       (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
+
+#endif
+#endif
+
+/* I2C_Register Bit Definitions *****************************************************/
+
+/* I2C Master Slave Address (I2CM_SA), offset 0x000 */
+
+#define I2CM_SA_RS           (1 << 0)  /* Bit 0:  Receive/Send */
+#define I2CM_SA_SA_SHIFT     1         /* Bits 7-1: I2C Slave Address */
+#define I2CM_SA_SA_MASK      (0x7f << I2CM_SA_SA_SHIFT)
+
+/* I2C Master Control/Status (I2CM_CS), offset 0x004 */
+
+#define I2CM_CS_BUSY         (1 << 0)  /* Bit 0:  I2C Busy (read) */
+#define I2CM_CS_ERROR        (1 << 1)  /* Bit 1:  Error in last bus operation (read) */
+#define I2CM_CS_ADRACK       (1 << 2)  /* Bit 2:  Acknowledge Address (read) */
+#define I2CM_CS_DATACK       (1 << 3)  /* Bit 3:  Acknowledge Data (read) */
+#define I2CM_CS_ARBLST       (1 << 4)  /* Bit 4:  Arbitration Lost (read) */
+#define I2CM_CS_IDLE         (1 << 5)  /* Bit 5:  I2C Idle (read) */
+#define I2CM_CS_BUSBSY       (1 << 6)  /* Bit 6:  Bus Busy (read) */
+
+#define I2CM_CS_RUN          (1 << 0)  /* Bit 0:  I2C Master Enable (write) */
+#define I2CM_CS_START        (1 << 1)  /* Bit 1:  Generate START (write) */
+#define I2CM_CS_STOP         (1 << 2)  /* Bit 2:  Generate STOP (write) */
+#define I2CM_CS_ACK          (1 << 3)  /* Bit 3:  Data Acknowledge Enable (write) */
+
+/* I2C Master Data (I2CM_DR), offset 0x008 */
+
+#define I2CM_DR_MASK         0xff      /* Bits 7-0: Data transferred */
+
+/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */
+
+#define I2CM_TPR_MASK        0xff      /* Bits 7-0: SCL Clock Period */
+
+/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */
+
+#define I2CM_IMR_IM          (1 << 0)  /* Bit 0:  Interrupt Mask */
+
+/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */
+
+#define I2CM_RIS_RIS         (1 << 0)  /* Bit 0:  Raw Interrupt Status */
+
+/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */
+
+#define I2CM_MIS_MIS         (1 << 0)  /* Bit 0:  Masked Interrupt Status */
+
+/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */
+
+#define I2CM_ICR_IC          (1 << 0)  /* Bit 0:  Masked Interrupt Status */
+
+/* I2C Master Configuration (I2CM_CR), offset 0x020 */
+
+#define I2CM_CR_LPBK         (1 << 0)  /* Bit 0:: I2C Loopback */
+#define I2CM_CR_MFE          (1 << 4 ) /* Bit 4:  I2C Master Function Enable */
+#define I2CM_CR_SFE          (1 << 5)  /* Bit 5:  I2C Slave Function Enable */
+
+/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */
+
+#define I2CS_OAR_MASK        0xff      /* Bits 7-0: I2C Slave Own Address */
+
+/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */
+
+#define I2CS_CSR_RREQ        (1 << 0)  /* Bit 0:  Receive Request (read) */
+#define I2CS_CSR_TREQ        (1 << 1)  /* Bit 1:  Transmit Request (read) */
+#define I2CS_CSR_FBR         (1 << 2)  /* Bit 2:  First Byte Received (read) */
+
+#define I2CS_CSR_DA          (1 << 0)  /* Bit 0:  Device Active (write) */
+
+/* I2C Slave Data (I2CS_DR), offset 0x008 */
+
+#define I2CS_DR_MASK         0xff      /* Bits 7-0: Data for Transfer */
+
+/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */
+
+#define I2CM_IMR_DATAIM      (1 << 0)  /* Bit 0:  Data Interrupt Mask */
+
+/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */
+
+#define I2CM_RIS_DATARIS     (1 << 0)  /* Bit 0:  Data Raw Interrupt Status */
+
+/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */
+
+#define I2CM_MIS_DATAMIS     (1 << 0)  /* Bit 0:  Data Masked Interrupt Status */
+
+/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */
+
+#define I2CM_ICR_DATAIC      (1 << 0)  /* Bit 0:  Data Interrupt Clear */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h
new file mode 100644
index 000000000..31dc2b249
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h
@@ -0,0 +1,360 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_memorymap.h
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Memory map ***********************************************************************/
+ 
+#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
+    defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
+#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
+                                         /* -0x1fffffff: Reserved */
+#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
+                                         /* -0x21ffffff: Reserved */
+#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
+                                         /* -0x3fffffff: Reserved */
+#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
+                                         /* -0x41ffffff: Peripherals */
+#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
+                                         /* -0xdfffffff: Reserved */
+#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
+#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
+#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
+                                         /* -0xe000dfff: Reserved */
+#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
+                                         /* -0xe003ffff: Reserved */
+#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
+                                         /* -0xffffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
+                                         /* -0x1fffffff: Reserved */
+#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
+                                         /* -0x21ffffff: Reserved */
+#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
+                                         /* -0x3fffffff: Reserved */
+#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
+                                         /* -0x41ffffff: Peripherals */
+#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
+                                         /* -0x5fffffff: Reserved */
+#  define LM3S_EPI0RAM_BASE   0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */
+#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
+#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
+#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
+                                         /* -0xe000dfff: Reserved */
+#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
+                                         /* -0xe003ffff: Reserved */
+#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
+                                         /* -0xffffffff: Reserved */
+#else
+#  error "Memory map not specified for this LM3S chip"
+#endif
+
+/* Peripheral base addresses ********************************************************/
+/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt
+ * peripheral modules.  They could probably be combined into one peripheral memory
+ * map.  However, keeping them separate does also provide so early, compile-time
+ * error detection that makes the duplication worthwhile.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                            /* -0x27fff: Reserved */
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                            /* -0x27fff: Reserved */
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2bfff: Reserved */
+#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                            /* -0x27fff: Reserved */
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2bfff: Reserved */
+#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x3fffff: Reserved */
+#  define LM3S_CANCON_BASE    (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN Controller */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
+
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2bfff: Reserved */
+#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC0_BASE       (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
+#  define LM3S_ADC1_BASE       (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+#  define LM3S_GPIOJ_BASE     (LM3S_PERIPH_BASE + 0x3d000)  /* -0x3dfff: GPIO Port J */
+                                                            /* -0x3ffff: Reserved */
+#  define LM3S_CAN0_BASE      (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN 0 */
+#  define LM3S_CAN1_BASE      (LM3S_PERIPH_BASE + 0x41000)  /* -0x41fff: CAN 1 */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0x49fff: Reserved */
+#  define LM3S_USB_BASE       (LM3S_PERIPH_BASE + 0x50000)  /* -0x50fff: USB */
+                                                            /* -0x53fff: Reserved */
+#  define LM3S_I2S0_BASE      (LM3S_PERIPH_BASE + 0x54000)  /* -0x54fff: I2S 0 */
+                                                            /* -0x57fff: Reserved */
+#  define LM3S_GPIOAAHB_BASE  (LM3S_PERIPH_BASE + 0x58000)  /* -0x58fff: GPIO Port A (AHB aperture) */
+#  define LM3S_GPIOBAHB_BASE  (LM3S_PERIPH_BASE + 0x59000)  /* -0x59fff: GPIO Port B (AHB aperture) */
+#  define LM3S_GPIOCAHB_BASE  (LM3S_PERIPH_BASE + 0x5A000)  /* -0x5afff: GPIO Port C (AHB aperture) */
+#  define LM3S_GPIODAHB_BASE  (LM3S_PERIPH_BASE + 0x5B000)  /* -0x5bfff: GPIO Port D (AHB aperture) */
+#  define LM3S_GPIOEAHB_BASE  (LM3S_PERIPH_BASE + 0x5C000)  /* -0x5cfff: GPIO Port E (AHB aperture) */
+#  define LM3S_GPIOFAHB_BASE  (LM3S_PERIPH_BASE + 0x5D000)  /* -0x5dfff: GPIO Port F (AHB aperture) */
+#  define LM3S_GPIOGAHB_BASE  (LM3S_PERIPH_BASE + 0x5E000)  /* -0x5efff: GPIO Port G (AHB aperture) */
+#  define LM3S_GPIOHAHB_BASE  (LM3S_PERIPH_BASE + 0x5F000)  /* -0x5ffff: GPIO Port H (AHB aperture) */
+#  define LM3S_GPIOJAHB_BASE  (LM3S_PERIPH_BASE + 0x60000)  /* -0x60fff: GPIO Port J (AHB aperture) */
+                                                            /* -0xcffff: Reserved */
+#  define LM3S_EPI0_BASE      (LM3S_PERIPH_BASE + 0xD0000)  /* -0xd0fff: EPI 0 */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+#  define LM3S_UDMA_BASE      (LM3S_PERIPH_BASE + 0xff000)  /* -0xfffff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#else
+#  error "Peripheral base addresses not specified for this LM3S chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h
new file mode 100644
index 000000000..b56ca77cb
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h
@@ -0,0 +1,235 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_ssi.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#if LM3S_NSSI > 0
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* SSI register offsets *************************************************************/
+
+#define LM3S_SSI_CR0_OFFSET       0x000 /* SSI Control 0 */
+#define LM3S_SSI_CR1_OFFSET       0x004 /* SSI Control 1 */
+#define LM3S_SSI_DR_OFFSET        0x008 /* SSI Data */
+#define LM3S_SSI_SR_OFFSET        0x00c /* SSI Status */
+#define LM3S_SSI_CPSR_OFFSET      0x010 /* SSI Clock Prescale */
+#define LM3S_SSI_IM_OFFSET        0x014 /* SSI Interrupt Mask */
+#define LM3S_SSI_RIS_OFFSET       0x018 /* SSI Raw Interrupt Status */
+#define LM3S_SSI_MIS_OFFSET       0x01c /* SSI Masked Interrupt Status */
+#define LM3S_SSI_ICR_OFFSET       0x020 /* SSI Interrupt Clear */
+#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
+#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
+#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
+#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
+#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
+#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
+#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
+#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
+#define LM3S_SSI_PCELLID0_OFFSET  0xff0 /* SSI PrimeCell Identification 0 */
+#define LM3S_SSI_PCELLID1_OFFSET  0xff4 /* SSI PrimeCell Identification 1 */
+#define LM3S_SSI_PCELLID2_OFFSET  0xff8 /* SSI PrimeCell Identification 2 */
+#define LM3S_SSI_PCELLID3_OFFSET  0xffc /* SSI PrimeCell Identification 3 */
+
+/* SSI register addresses ***********************************************************/
+
+#define LM3S_SSI0_CR0             (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI0_CR1             (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI0_DR              (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI0_SR              (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI0_CPSR            (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI0_IM              (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI0_RIS             (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI0_MIS             (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI0_ICR             (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI0_PERIPHID4       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI0_PERIPHID5       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI0_PERIPHID6       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI0_PERIPHID7       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI0_PERIPHID0       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI0_PERIPHID1       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI0_PERIPHID2       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI0_PERIPHID3       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI0_PCELLID0        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI0_PCELLID1        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI0_PCELLID2        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI0_PCELLID3        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
+
+#if LM3S_NSSI > 1
+#define LM3S_SSI1_CR0             (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI1_CR1             (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI1_DR              (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI1_SR              (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI1_CPSR            (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI1_IM              (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI1_RIS             (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI1_MIS             (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI1_ICR             (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI1_PERIPHID4       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI1_PERIPHID5       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI1_PERIPHID6       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI1_PERIPHID7       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI1_PERIPHID0       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI1_PERIPHID1       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI1_PERIPHID2       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI1_PERIPHID3       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI1_PCELLID0        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI1_PCELLID1        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI1_PCELLID2        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI1_PCELLID3        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
+
+#define LM3S_SSI_BASE(n)          (LM3S_SSI0_BASE + (n)*0x01000)
+
+#define LM3S_SSI_CR0(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI_CR1(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI_DR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI_SR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI_CPSR(n)          (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI_IM(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI_RIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI_MIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI_ICR(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI_PERIPHID4(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI_PERIPHID5(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI_PERIPHID6(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI_PERIPHID7(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI_PERIPHID0(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI_PERIPHID1(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI_PERIPHID2(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI_PERIPHID3(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI_PCELLID0(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI_PCELLID1(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI_PCELLID2(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI_PCELLID3(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
+#endif /* LM3S_NSSI > 1 */
+
+/* SSI register bit defitiions ******************************************************/
+
+/* SSI Control 0 (SSICR0), offset 0x000 */
+
+#define SSI_CR0_DSS_SHIFT         0         /* Bits 3-0: SSI Data Size Select */
+#define SSI_CR0_DSS_MASK          (0x0f << SSI_CR0_DSS_SHIFT)
+#define   SSI_CR0_DSS(n)          ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
+#define SSI_CR0_FRF_SHIFT         4         /* Bits 5-4: SSI Frame Format Select */
+#define SSI_CR0_FRF_MASK          (3 << SSI_CR0_FRF_SHIFT)
+#define   SSI_CR0_FRF_SPI         (0 << SSI_CR0_FRF_SHIFT)     /* Freescale SPI format */
+#define   SSI_CR0_FRF_SSFF        (1 << SSI_CR0_FRF_SHIFT)     /* TI synchronous serial fram format */
+#define   SSI_CR0_FRF_UWIRE       (2 << SSI_CR0_FRF_SHIFT)     /* MICROWIRE frame format */
+#define SSI_CR0_SPO               (1 << 6)  /* Bit 6:  SSI Serial Clock Polarity */
+#define SSI_CR0_SPH               (1 << 7)  /* Bit 7:  SSI Serial Clock Phase */
+#define SSI_CR0_SCR_SHIFT         8         /* Bits 15-8: SSI Serial Clock Rate */
+#define SSI_CR0_SCR_MASK          (0xff << SSI_CR0_SCR_SHIFT)
+
+/* SSI Control 1 (SSICR1), offset 0x004 */
+
+#define SSI_CR1_LBM               (1 << 0)  /* Bit 0:  SSI Loopback Mode */
+#define SSI_CR1_SSE               (1 << 1)  /* Bit 1:  SSI Synchronous Serial Port Enable */
+#define SSI_CR1_MS                (1 << 2)  /* Bit 2:  SSI Master/Slave Select slave */
+#define SSI_CR1_SOD               (1 << 3)  /* Bit 3:  SSI Slave Mode Output Disable */
+
+/* SSI Data (SSIDR), offset 0x008 */
+
+#define SSI_DR_MASK               0xffff    /* Bits 15-0: SSI data */
+
+/* SSI Status (SSISR), offset 0x00c */
+
+#define SSI_SR_TFE                (1 << 0)  /* Bit 0:  SSI Transmit FIFO Empty */
+#define SSI_SR_TNF                (1 << 1)  /* Bit 1:  SSI Transmit FIFO Not Full */
+#define SSI_SR_RNE                (1 << 2)  /* Bit 2:  SSI Receive FIFO Not Empty */
+#define SSI_SR_RFF                (1 << 3)  /* Bit 3:  SSI Receive FIFO Full */
+#define SSI_SR_BSY                (1 << 4)  /* Bit 4:  SSI Busy Bit */
+
+/* SSI Clock Prescale (SSICPSR), offset 0x010 */
+
+#define SSI_CPSR_DIV_MASK         0xff      /* Bits 7-0: SSI Clock Prescale Divisor */
+
+/* SSI Interrupt Mask (SSIIM), offset 0x014 */
+
+#define SSI_IM_ROR                (1 << 0)  /* Bit 0:  SSI Receive Overrun Interrupt Mask */
+#define SSI_IM_RT                 (1 << 1)  /* Bit 1:  SSI Receive Time-Out Interrupt Mask */
+#define SSI_IM_RX                 (1 << 2)  /* Bit 2:  SSI Receive FIFO Interrupt Mask */
+#define SSI_IM_TX                 (1 << 3)  /* Bit 3:  SSI Transmit FIFO Interrupt Mask */
+
+/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
+
+#define SSI_RIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Raw Interrupt Status */
+#define SSI_RIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Raw Interrupt Status */
+#define SSI_RIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Raw Interrupt Status */
+#define SSI_RIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Raw Interrupt Status */
+
+/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
+
+#define SSI_MIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Masked Interrupt Status */
+#define SSI_MIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Masked Interrupt Status */
+#define SSI_MIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Masked Interrupt Status */
+#define SSI_MIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Masked Interrupt Status */
+
+/* SSI Interrupt Clear (SSIICR), offset 0x020 */
+
+#define SSI_ICR_ROR               (1 << 0)  /* Bit 0: SSI Receive Overrun Interrupt Clear */
+#define SSI_ICR_RT                (1 << 1)  /* Bit 1: SSI Receive Time-Out Interrupt Clear */
+
+/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
+
+#define SSI_PERIPHID_MASK         0xff      /* Bits 7-0: SSI Peripheral ID n */
+
+/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
+
+#define SSI_PCELLID_MASK          0xff      /* Bits 7-0: SSI Prime cell ID */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* LM3S_NSSI > 0 */
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h
new file mode 100644
index 000000000..d66cfeb47
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h
@@ -0,0 +1,495 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_syscontrol.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* System Control Register Offsets **************************************************/
+
+#define LM3S_SYSCON_DID0_OFFSET       0x000 /* Device Identification 0 */
+#define LM3S_SYSCON_DID1_OFFSET       0x004 /* Device Identification 1 */
+#define LM3S_SYSCON_DC0_OFFSET        0x008 /* Device Capabilities 0 */
+#define LM3S_SYSCON_DC1_OFFSET        0x010 /* Device Capabilities 1 */
+#define LM3S_SYSCON_DC2_OFFSET        0x014 /* Device Capabilities 2 */
+#define LM3S_SYSCON_DC3_OFFSET        0x018 /* Device Capabilities 3 */
+#define LM3S_SYSCON_DC4_OFFSET        0x01c /* Device Capabilities 4 */
+#define LM3S_SYSCON_PBORCTL_OFFSET    0x030 /* Brown-Out Reset Control */
+#define LM3S_SYSCON_LDOPCTL_OFFSET    0x034 /* LDO Power Control */
+#define LM3S_SYSCON_SRCR0_OFFSET      0x040 /* Software Reset Control 0 */
+#define LM3S_SYSCON_SRCR1_OFFSET      0x044 /* Software Reset Control 1 */
+#define LM3S_SYSCON_SRCR2_OFFSET      0x048 /* Software Reset Control 2*/
+#define LM3S_SYSCON_RIS_OFFSET        0x050 /* Raw Interrupt Status */
+#define LM3S_SYSCON_IMC_OFFSET        0x054 /* Interrupt Mask Control */
+#define LM3S_SYSCON_MISC_OFFSET       0x058 /* Masked Interrupt Status and Clear */
+#define LM3S_SYSCON_RESC_OFFSET       0x05c /* Reset Cause */
+#define LM3S_SYSCON_RCC_OFFSET        0x060 /* Run-Mode Clock Configuration */
+#define LM3S_SYSCON_PLLCFG_OFFSET     0x064 /* XTAL to PLL Translation */
+#define LM3S_SYSCON_RCC2_OFFSET       0x070 /* Run-Mode Clock Configuration 2 */
+#define LM3S_SYSCON_RCGC0_OFFSET      0x100 /* Run Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_RCGC1_OFFSET      0x104 /* Run Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_RCGC2_OFFSET      0x108 /* Run Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_SCGC0_OFFSET      0x110 /* Sleep Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_SCGC1_OFFSET      0x114 /* Sleep Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_SCGC2_OFFSET      0x118 /* Sleep Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_DCGC0_OFFSET      0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_DCGC1_OFFSET      0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_DCGC2_OFFSET      0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
+
+/* System Control Register Addresses ************************************************/
+
+#define LM3S_SYSCON_DID0              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
+#define LM3S_SYSCON_DID1              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
+#define LM3S_SYSCON_DC0               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
+#define LM3S_SYSCON_DC1               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
+#define LM3S_SYSCON_DC2               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
+#define LM3S_SYSCON_DC3               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
+#define LM3S_SYSCON_DC4               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
+#define LM3S_SYSCON_PBORCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
+#define LM3S_SYSCON_LDOPCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
+#define LM3S_SYSCON_SRCR0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
+#define LM3S_SYSCON_SRCR1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
+#define LM3S_SYSCON_SRCR2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
+#define LM3S_SYSCON_RIS               (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
+#define LM3S_SYSCON_IMC               (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
+#define LM3S_SYSCON_MISC              (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
+#define LM3S_SYSCON_RESC              (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
+#define LM3S_SYSCON_RCC               (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
+#define LM3S_SYSCON_PLLCFG            (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
+#define LM3S_SYSCON_RCC2              (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
+#define LM3S_SYSCON_RCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
+#define LM3S_SYSCON_RCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
+#define LM3S_SYSCON_RCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
+#define LM3S_SYSCON_SCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
+#define LM3S_SYSCON_SCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
+#define LM3S_SYSCON_SCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
+#define LM3S_SYSCON_DCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
+#define LM3S_SYSCON_DCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
+#define LM3S_SYSCON_DCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
+#define LM3S_SYSCON_DSLPCLKCFG        (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
+
+/* System Control Register Bit Definitions ******************************************/
+
+/* Device Identification 0 (DID0), offset 0x000 */
+
+#define SYSCON_DID0_MINOR_SHIFT       0         /* Bits 7-0: Minor Revision of the device */
+#define SYSCON_DID0_MINOR_MASK        (0xff << SYSCON_DID0_MINOR_SHIFT)
+#define SYSCON_DID0_MAJOR_SHIFT       8         /* Bits 15-8: Major Revision of the device */
+#define SYSCON_DID0_MAJOR_MASK        (0xff << SYSCON_DID0_MAJOR_SHIFT)
+#define SYSCON_DID0_CLASS_SHIFT       16        /* Bits 23-16: Device Class */
+#define SYSCON_DID0_CLASS_MASK        (0xff << SYSCON_DID0_CLASS_SHIFT)
+#define SYSCON_DID0_VER_SHIFT         28        /* Bits 30-28: DID0 Version */
+#define SYSCON_DID0_VER_MASK          (7 << SYSCON_DID0_VER_SHIFT)
+
+/* Device Identification 1 (DID1), offset 0x004 */
+
+#define SYSCON_DID1_QUAL_SHIFT        0         /* Bits 1-0: Qualification Status */
+#define SYSCON_DID1_QUAL_MASK         (0x03 << SYSCON_DID1_QUAL_SHIFT)
+#define SYSCON_DID1_ROHS              (1 << 2)  /* Bit 2: RoHS-Compliance */
+#define SYSCON_DID1_PKG_SHIFT         3 /* Bits 4-3: Package Type */
+#define SYSCON_DID1_PKG_MASK          (0x03 << SYSCON_DID1_PKG_SHIFT)
+#define SYSCON_DID1_TEMP_SHIFT        5         /* Bits 7-5: Temperature Range */
+#define SYSCON_DID1_TEMP_MASK         (0x07 << SYSCON_DID1_TEMP_SHIFT)
+#define SYSCON_DID1_PINCOUNT_SHIFT    13        /* Bits 15-13: Package Pin Count */
+#define SYSCON_DID1_PINCOUNT_MASK     (0x07 << SYSCON_DID1_PINCOUNT_SHIFT)
+#define SYSCON_DID1_PARTNO_SHIFT      16        /* Bits 23-16: Part Number */
+#define SYSCON_DID1_PARTNO_MASK       (0xff << SYSCON_DID1_PARTNO_SHIFT)
+#define SYSCON_DID1_FAM_SHIFT         24        /* Bits 27-24: Family */
+#define SYSCON_DID1_FAM_MASK          (0x0f << SYSCON_DID1_FAM_SHIFT)
+#define SYSCON_DID1_VER_SHIFT         28        /* Bits 31-28:  DID1 Version */
+#define SYSCON_DID1_VER_MASK          (0x0f << SYSCON_DID1_VER_SHIFT)
+
+/* Device Capabilities 0 (DC0), offset 0x008 */
+
+#define SYSCON_DC0_FLASHSZ_SHIFT      0         /* Bits 15-0: FLASH Size */
+#define SYSCON_DC0_FLASHSZ_MASK       (0xffff << SYSCON_DC0_FLASHSZ_SHIFT)
+#define SYSCON_DC0_SRAMSZ_SHIFT       16        /* Bits 31-16: SRAM Size */
+#define SYSCON_DC0_SRAMSZ_MASK        (0xffff << SYSCON_DC0_SRAMSZ_SHIFT)
+
+/* Device Capabilities 1 (DC1), offset 0x010 */
+
+#define SYSCON_DC1_JTAG               (1 << 0)  /* Bit 0: JTAG Present */
+#define SYSCON_DC1_SWD                (1 << 1)  /* Bit 1: SWD Present */
+#define SYSCON_DC1_SWO                (1 << 2)  /* Bit 2: SWO Trace Port Present */
+#define SYSCON_DC1_WDT                (1 << 3)  /* Bit 3: Watchdog Timer Present */
+#define SYSCON_DC1_PLL                (1 << 4)  /* Bit 4: PLL Present */
+#define SYSCON_DC1_TEMPSNS            (1 << 5)  /* Bit 5: Temp Sensor Present */
+#define SYSCON_DC1_HIB                (1 << 6)  /* Bit 6: Hibernation Module Present */
+#define SYSCON_DC1_MPU                (1 << 7)  /* Bit 7: MPU Present */
+#define SYSCON_DC1_MAXADCSPD_SHIFT    8         /* Bits 9-8: Max ADC Speed */
+#define SYSCON_DC1_MAXADCSPD_MASK     (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT)
+#define SYSCON_DC1_ADC                (1 << 16) /* Bit 16: ADC Module Present */
+#define SYSCON_DC1_MINSYSDIV_SHIFT    12        /* Bits 15-12: System Clock Divider Minimum */
+#define SYSCON_DC1_MINSYSDIV_MASK     (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT)
+
+/* Device Capabilities 2 (DC2), offset 0x014 */
+
+#define SYSCON_DC2_UART0              (1 << 0)  /* Bit 0: UART0 Present */
+#define SYSCON_DC2_UART1              (1 << 1)  /* Bit 1: UART1 Present */
+#define SYSCON_DC2_SSI0               (1 << 4)  /* Bit 4: SSI0 Present */
+#define SYSCON_DC2_SSI1               (1 << 5)  /* Bit 5: SSI1 Present */
+#define SYSCON_DC2_I2C0               (1 << 12) /* Bit 12: I2C Module 0 Present */
+#define SYSCON_DC2_I2C1               (1 << 14) /* Bit 14: I2C Module 1 Present */
+#define SYSCON_DC2_TIMER0             (1 << 16) /* Bit 16: Timer 0 Present */
+#define SYSCON_DC2_TIMER1             (1 << 17) /* Bit 17: Timer 1 Present */
+#define SYSCON_DC2_TIMER2             (1 << 18) /* Bit 18: Timer 2 Present */
+#define SYSCON_DC2_TIMER3             (1 << 19) /* Bit 19: Timer 3 Present */
+#define SYSCON_DC2_COMP0              (1 << 24) /* Bit 24: Analog Comparator 0 Present */
+#define SYSCON_DC2_COMP1              (1 << 25) /* Bit 25: Analog Comparator 1 Present */
+
+/* Device Capabilities 3 (DC3), offset 0x018 */
+
+#define SYSCON_DC3_C0MINUS            (1 << 6)  /* Bit 6: C0- Pin Present */
+#define SYSCON_DC3_C0PLUS             (1 << 7)  /* Bit 7: C0+ Pin Present */
+#define SYSCON_DC3_C0O                (1 << 8)  /* Bit 8: C0o Pin Present */
+#define SYSCON_DC3_C1MINUS            (1 << 9)  /* Bit 9: C1- Pin Present */
+#define SYSCON_DC3_C1PLUS             (1 << 10) /* Bit 10: C1+ Pin Present */
+#define SYSCON_DC3_ADC0               (1 << 16) /* Bit 16: ADC0 Pin Present */
+#define SYSCON_DC3_ADC1               (1 << 17) /* Bit 17: ADC1 Pin Present */
+#define SYSCON_DC3_ADC2               (1 << 18) /* Bit 18: ADC2 Pin Present */
+#define SYSCON_DC3_ADC3               (1 << 19) /* Bit 19: ADC3 Pin Present */
+#define SYSCON_DC3_ADC4               (1 << 20) /* Bit 20: ADC4 Pin Present */
+#define SYSCON_DC3_ADC5               (1 << 21) /* Bit 21: ADC5 Pin Present */
+#define SYSCON_DC3_ADC6               (1 << 22) /* Bit 22: ADC6 Pin Present */
+#define SYSCON_DC3_ADC7               (1 << 23) /* Bit 23: ADC7 Pin Present */
+#define SYSCON_DC3_CCP0               (1 << 24) /* Bit 24: CCP0 Pin Present */
+#define SYSCON_DC3_CCP1               (1 << 25) /* Bit 25: CCP1 Pin Present */
+#define SYSCON_DC3_CCP2               (1 << 26) /* Bit 26: CCP2 Pin Present */
+#define SYSCON_DC3_CCP3               (1 << 27) /* Bit 27: CCP3 Pin Present */
+#define SYSCON_DC3_CCP4               (1 << 28) /* Bit 28: CCP4 Pin Present */
+#define SYSCON_DC3_CCP5               (1 << 29) /* Bit 29: CCP5 Pin Present */
+#define SYSCON_DC3_32KHZ              (1 << 31) /* Bit 31: 32KHz Input Clock Available */
+
+/* Device Capabilities 4 (DC4), offset 0x01c */
+
+#define SYSCON_DC4_GPIO(n)            (1 << (n))
+#define SYSCON_DC4_GPIOA              (1 << 0)  /* Bit 0: GPIO Port A Present */
+#define SYSCON_DC4_GPIOB              (1 << 1)  /* Bit 1: GPIO Port B Present */
+#define SYSCON_DC4_GPIOC              (1 << 2)  /* Bit 2: GPIO Port C Present */
+#define SYSCON_DC4_GPIOD              (1 << 3)  /* Bit 3: GPIO Port D Present */
+#define SYSCON_DC4_GPIOE              (1 << 4)  /* Bit 4: GPIO Port E Present */
+#define SYSCON_DC4_GPIOF              (1 << 5)  /* Bit 5: GPIO Port F Present */
+#define SYSCON_DC4_GPIOG              (1 << 6)  /* Bit 6: GPIO Port G Present */
+#define SYSCON_DC4_GPIOH              (1 << 7)  /* Bit 7: GPIO Port H Present */
+#define SYSCON_DC4_EMAC0              (1 << 28) /* Bit 28: Ethernet MAC0 Present */
+#define SYSCON_DC4_EPHY0              (1 << 30) /* Bit 30: Ethernet PHY0 Present */
+
+/* Brown-Out Reset Control (PBORCTL), offset 0x030 */
+
+#define SYSCON_PBORCTL_BORIOR         (1 << 1)  /* Bit 1: BOR Interrupt or Reset */
+
+/* LDO Power Control (LDOPCTL), offset 0x034 */
+
+#define SYSCON_LDOPCTL_VADJ_SHIFT     0         /* Bits 5-0: LDO Output Voltage */
+#define SYSCON_LDOPCTL_VADJ_MASK      (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT)
+#  define SYSCON_LPDOPCTL_2500MV      (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/
+#  define SYSCON_LPDOPCTL_2450MV      (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */
+#  define SYSCON_LPDOPCTL_2400MV      (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */
+#  define SYSCON_LPDOPCTL_2350MV      (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */
+#  define SYSCON_LPDOPCTL_2300MV      (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */
+#  define SYSCON_LPDOPCTL_2250MV      (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */
+#  define SYSCON_LPDOPCTL_2750MV      (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */
+#  define SYSCON_LPDOPCTL_2700MV      (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */
+#  define SYSCON_LPDOPCTL_2650MV      (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */
+#  define SYSCON_LPDOPCTL_2600MV      (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */
+#  define SYSCON_LPDOPCTL_2550MV      (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */
+
+/* Software Reset Control 0 (SRCR0), offset 0x040 */
+
+#define SYSCON_SRCR0_WDT              (1 << 3)  /* Bit 3: WDT Reset Control */
+#define SYSCON_SRCR0_HIB              (1 << 6)  /* Bit 6: HIB Reset Control */
+#define SYSCON_SRCR0_ADC              (1 << 16) /* Bit 16: ADC0 Reset Control */
+
+/* Software Reset Control 1 (SRCR1), offset 0x044 */
+
+#define SYSCON_SRCR1_UART0            (1 << 0)  /* Bit 0: UART0 Reset Control */
+#define SYSCON_SRCR1_UART1            (1 << 1)  /* Bit 1: UART1 Reset Control */
+#define SYSCON_SRCR1_SSI0             (1 << 4)  /* Bit 4: SSI0 Reset Control1 */
+#define SYSCON_SRCR1_SSI1             (1 << 5)  /* Bit 5: SSI1 Reset Control */
+#define SYSCON_SRCR1_I2C0             (1 << 12) /* Bit 12: I2C0 Reset Control */
+#define SYSCON_SRCR1_I2C1             (1 << 14) /* Bit 14: I2C1 Reset Control */
+#define SYSCON_SRCR1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Reset Control */
+#define SYSCON_SRCR1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Reset Control */
+#define SYSCON_SRCR1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Reset Control */
+#define SYSCON_SRCR1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Reset Control */
+#define SYSCON_SRCR1_COMP0            (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */
+#define SYSCON_SRCR1_COMP1            (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */
+
+/* Software Reset Control 2 (SRCR2), offset 0x048 */
+
+#define SYSCON_SRCR2_GPIO(n)          (1 << (n))
+#define SYSCON_SRCR2_GPIOA            (1 << 0)  /* Bit 0: Port A Reset Control */
+#define SYSCON_SRCR2_GPIOB            (1 << 1)  /* Bit 1: Port B Reset Control */
+#define SYSCON_SRCR2_GPIOC            (1 << 2)  /* Bit 2: Port C Reset Control */
+#define SYSCON_SRCR2_GPIOD            (1 << 3)  /* Bit 3: Port D Reset Control */
+#define SYSCON_SRCR2_GPIOE            (1 << 4)  /* Bit 4: Port E Reset Control */
+#define SYSCON_SRCR2_GPIOF            (1 << 5)  /* Bit 5: Port F Reset Control */
+#define SYSCON_SRCR2_GPIOG            (1 << 6)  /* Bit 6: Port G Reset Control */
+#define SYSCON_SRCR2_GPIOH            (1 << 7)  /* Bit 7: Port H Reset Control */
+#define SYSCON_SRCR2_EMAC0            (1 << 28) /* Bit 28: MAC0 Reset Control */
+#define SYSCON_SRCR2_EPHY0            (1 << 30) /* Bit 30: PHY0 Reset Control */
+
+/* Raw Interrupt Status (RIS), offset 0x050 */
+
+#define SYSCON_RIS_BORRIS             (1 << 1)  /* Bit 1: Brown-Out Reset Raw Interrupt Status */
+#define SYSCON_RIS_PLLLRIS            (1 << 6)  /* Bit 6: PLL Lock Raw Interrupt Status */
+
+/* Interrupt Mask Control (IMC), offset 0x054 */
+
+#define SYSCON_IMC_BORIM              (1 << 1)  /* Bit 1: Brown-Out Reset Interrupt Mask */
+#define SYSCON_IMC_PLLLIM             (1 << 6)  /* Bit 6: PLL Lock Interrupt Mask */
+
+/* Masked Interrupt Status and Clear (MISC), offset 0x058 */
+
+#define SYSCON_MISC_BORMIS            (1 << 1)  /* Bit 1: BOR Masked Interrupt Status */
+#define SYSCON_MISC_PLLLMIS           (1 << 6)  /* Bit 6: PLL Lock Masked Interrupt Status */
+
+/* Reset Cause (RESC), offset 0x05C */
+
+#define SYSCON_RESC_EXT               (1 << 0)  /* Bit 0: External Reset */
+#define SYSCON_RESC_POR               (1 << 1)  /* Bit 1: Power-On Reset */
+#define SYSCON_RESC_BOR               (1 << 2)  /* Bit 2: Brown-Out Reset */
+#define SYSCON_RESC_WDT               (1 << 3)  /* Bit 3: Watchdog Timer Reset */
+#define SYSCON_RESC_SW                (1 << 4)  /* Bit 4: Software Reset */
+
+/* Run-Mode Clock Configuration (RCC), offset 0x060 */
+
+#define SYSCON_RCC_MOSCDIS            (1 << 0)  /* Bit 0: Main Oscillator Disable */
+#define SYSCON_RCC_IOSCDIS            (1 << 1)  /* Bit 1: Internal Oscillator Disable */
+#define SYSCON_RCC_OSCSRC_SHIFT       4         /* Bits 5-4: Oscillator Source */
+#define SYSCON_RCC_OSCSRC_MASK        (0x03 << SYSCON_RCC_OSCSRC_SHIFT)
+#  define SYSCON_RCC_OSCSRC_MOSC      (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */
+#  define SYSCON_RCC_OSCSRC_IOSC      (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */
+#  define SYSCON_RCC_OSCSRC_IOSC4     (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */
+#  define SYSCON_RCC_OSCSRC_30KHZ     (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */
+#define SYSCON_RCC_XTAL_SHIFT         6         /* Bits 10-6: Crystal Value */
+#define SYSCON_RCC_XTAL_MASK          (0x1f << SYSCON_RCC_XTAL_SHIFT)
+#  define SYSCON_RCC_XTAL1000KHZ      ( 0 << SYSCON_RCC_XTAL_SHIFT)  /* 1.0000MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL1843KHZ      ( 1 << SYSCON_RCC_XTAL_SHIFT)  /* 1.8432MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL2000KHZ      ( 2 << SYSCON_RCC_XTAL_SHIFT)  /* 2.0000MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL2580KHZ      ( 3 << SYSCON_RCC_XTAL_SHIFT)  /* 2.4576MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL3580KHZ      ( 4 << SYSCON_RCC_XTAL_SHIFT)  /* 3.5795MHz */
+#  define SYSCON_RCC_XTAL3686KHZ      ( 5 << SYSCON_RCC_XTAL_SHIFT)  /* 3.6864MHz */
+#  define SYSCON_RCC_XTAL4000KHZ      ( 6 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0000MHz */
+#  define SYSCON_RCC_XTAL4096KHZ      ( 7 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0960MHz */
+#  define SYSCON_RCC_XTAL4915KHZ      ( 8 << SYSCON_RCC_XTAL_SHIFT)  /* 4.9152MHz */
+#  define SYSCON_RCC_XTAL5000KHZ      ( 9 << SYSCON_RCC_XTAL_SHIFT)  /* 5.0000MHz */
+#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT)  /* 5.1200MHz */
+#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT)  /* 6.0000MHz (reset value) */
+#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT)  /* 6.1440MHz */
+#  define SYSCON_RCC_XTAL7373KHZ      (13 << SYSCON_RCC_XTAL_SHIFT)  /* 7.3728MHz */
+#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT)  /* 8.0000MHz */
+#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT)  /* 8.1920MHz */
+#ifdef CONFIG_ARCH_CHIP_LM3S9B96
+#  define SYSCON_RCC_XTAL10000KHZ     (16 << SYSCON_RCC_XTAL_SHIFT)  /* 10.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL12000KHZ     (17 << SYSCON_RCC_XTAL_SHIFT)  /* 12.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL12888KHZ     (18 << SYSCON_RCC_XTAL_SHIFT)  /* 12.288 MHz */
+#  define SYSCON_RCC_XTAL13560KHZ     (19 << SYSCON_RCC_XTAL_SHIFT)  /* 13.56 MHz */
+#  define SYSCON_RCC_XTAL14318KHZ     (20 << SYSCON_RCC_XTAL_SHIFT)  /* 14.31818 MHz */
+#  define SYSCON_RCC_XTAL16000KHZ     (21 << SYSCON_RCC_XTAL_SHIFT)  /* 16.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL16384KHZ     (22 << SYSCON_RCC_XTAL_SHIFT)  /* 16.384 MHz */
+#endif
+#define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
+#define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
+#define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */
+#define SYSCON_RCC_SYSDIV_SHIFT       23        /* Bits 26-23: System Clock Divisor */
+#define SYSCON_RCC_SYSDIV_MASK        (0x0f << SYSCON_RCC_SYSDIV_SHIFT)
+#  define SYSCON_RCC_SYSDIV(n)        (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT)
+#define SYSCON_RCC_ACG                (1 << 27) /* Bit 27: Auto Clock Gating */
+
+/* XTAL to PLL Translation (PLLCFG), offset 0x064 */
+
+#define SYSCON_PLLCFG_F_SHIFT         5         /* Bits 13-5: PLL F Value */
+#define SYSCON_PLLCFG_F_MASK          (0x1ff << SYSCON_PLLCFG_F_SHIFT)
+#define SYSCON_PLLCFG_R_SHIFT         0         /* Bits 4-0: PLL R Value  */
+#define SYSCON_PLLCFG_R_MASK          (0x1f << SYSCON_PLLCFG_R_SHIFT)
+
+/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */
+
+#define SYSCON_RCC2_OSCSRC2_SHIFT     4         /* Bits 6-4: Oscillator Source */
+#define SYSCON_RCC2_OSCSRC2_MASK      (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT)
+#  define SYSCON_RCC2_OSCSRC2_MOSC    (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */
+#  define SYSCON_RCC2_OSCSRC2_IOSC    (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */
+#  define SYSCON_RCC2_OSCSRC2_IOSC4   (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */
+#  define SYSCON_RCC2_OSCSRC2_30KHZ   (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */
+#  define SYSCON_RCC2_OSCSRC2_32KHZ   (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */
+#define SYSCON_RCC2_BYPASS2           (1 << 11) /* Bit 11: Bypass PLL */
+#define SYSCON_RCC2_PWRDN2            (1 << 13) /* Bit 13: Power-Down PLL */
+#define SYSCON_RCC2_SYSDIV2_SHIFT     23        /* Bits 28-23: System Clock Divisor */
+#define SYSCON_RCC2_SYSDIV2_MASK      (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT)
+#  define SYSCON_RCC2_SYSDIV(n)       ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT)
+#define SYSCON_RCC2_USERCC2           (1 << 31) /* Bit 31: Use RCC2 When set */
+
+/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */
+
+#define SYSCON_RCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_RCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_RCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_RCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_RCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */
+
+#define SYSCON_RCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_RCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_RCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_RCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_RCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_RCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_RCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_RCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */
+
+#define SYSCON_RCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_RCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_RCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_RCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_RCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_RCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_RCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_RCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_RCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_RCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_RCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */
+
+#define SYSCON_SCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_SCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_SCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_SCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_SCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */
+
+#define SYSCON_SCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_SCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_SCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_SCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_SCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_SCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_SCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_SCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */
+
+#define SYSCON_SCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_SCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_SCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_SCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_SCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_SCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_SCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_SCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_SCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_SCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_SCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */
+
+#define SYSCON_DCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_DCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_DCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_DCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_DCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */
+
+#define SYSCON_DCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_DCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_DCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_DCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_DCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_DCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_DCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_DCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */
+
+#define SYSCON_DCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_DCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_DCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_DCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_DCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_DCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_DCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_DCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_DCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_DCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_DCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */
+
+#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */
+#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK  (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT)
+#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT   4 /* Bits 6-4: Clock Source */
+#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK    (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h
new file mode 100644
index 000000000..649737f13
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h
@@ -0,0 +1,125 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_timer.h
+ *
+ *   Copyright (C) 2012 Max Nekludov. All rights reserved.
+ *   Author: Max Nekludov <macscomp@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Timer register offsets ***********************************************************/
+
+#define TIMER_GPTMCFG_OFFSET             0x000
+#define TIMER_GPTMTAMR_OFFSET            0x004
+#define TIMER_GPTMCTL_OFFSET             0x00C
+#define TIMER_GPTMIMR_OFFSET             0x018
+#define TIMER_GPTMRIS_OFFSET             0x01C
+#define TIMER_GPTMICR_OFFSET             0x024
+#define TIMER_GPTMTAILR_OFFSET           0x028
+#define TIMER_GPTMTAR_OFFSET             0x048
+
+/* SSI register addresses ***********************************************************/
+
+#define LM3S_TIMER_BASE(n)               (LM3S_TIMER0_BASE + (n)*0x01000)
+
+#define LM3S_TIMER_GPTMCFG(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
+#define LM3S_TIMER_GPTMTAMR(n)           (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
+#define LM3S_TIMER_GPTMCTL(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
+#define LM3S_TIMER_GPTMIMR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
+#define LM3S_TIMER_GPTMRIS(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
+#define LM3S_TIMER_GPTMICR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
+#define LM3S_TIMER_GPTMTAILR(n)          (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
+#define LM3S_TIMER_GPTMTAR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
+
+/* SSI register bit defitiions ******************************************************/
+
+/* GPTM Configuration (GPTMCFG), offset 0x000 */
+
+#define TIMER_GPTMCFG_CFG_SHIFT          0    /* Bits 2-0: GPTM Configuration */
+#define TIMER_GPTM_CFG_MASK              (0x07 << TIMER_GPTMCFG_CFG_SHIFT)
+#define   TIMER_GPTMCFG_CFG_32           (0 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit timer configuration */
+#define   TIMER_GPTMCFG_CFG_RTC          (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit real-time clock (RTC) counter configuration */
+#define   TIMER_GPTMCFG_CFG_16           (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 16-bit timer configuration */
+
+/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */
+
+#define TIMER_GPTMTAMR_TAMR_SHIFT        0    /* Bits 1-0: GPTM Timer A Mode */
+#define TIMER_GPTMTAMR_TAMR_MASK         (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT)
+#define   TIMER_GPTMTAMR_TAMR_ONESHOT    (1 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* One-Shot Timer mode */
+#define   TIMER_GPTMTAMR_TAMR_PERIODIC   (2 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Periodic Timer mode */
+#define   TIMER_GPTMTAMR_TAMR_CAPTURE    (3 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Capture mode */
+#define TIMER_GPTMTAMR_TACMR_SHIFT       2    /* Bits 2:   GPTM Timer A Capture Mode */
+#define TIMER_GPTMTAMR_TACMR_MASK        (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT)
+#define   TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Count mode */
+#define   TIMER_GPTMTAMR_TACMR_EDGETIME  (1 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Time mode */
+#define TIMER_GPTMTAMR_TAAMS_SHIFT       3    /* Bits 3:   GPTM Timer A Alternate Mode Select */
+#define TIMER_GPTMTAMR_TAAMS_MASK        (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT)
+#define   TIMER_GPTMTAMR_TAAMS_CAPTURE   (0 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* Capture mode is enabled */
+#define   TIMER_GPTMTAMR_TAAMS_PWM       (1 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* PWM mode is enabled */
+#define TIMER_GPTMTAMR_TACDIR_SHIFT      4    /* Bits 4:   GPTM Timer A Count Direction */
+#define TIMER_GPTMTAMR_TACDIR_MASK       (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT)
+#define   TIMER_GPTMTAMR_TACDIR_DOWN     (0 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* The timer counts down */
+#define   TIMER_GPTMTAMR_TACDIR_UP       (1 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* When in one-shot or periodic mode, the timer counts up */
+#define TIMER_GPTMTAMR_TAMIE_SHIFT       5    /* Bits 5:   GPTM Timer A Match Interrupt Enable */
+#define TIMER_GPTMTAMR_TAMIE_MASK        (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT)
+
+/* GPTM Control (GPTMCTL), offset 0x00C */
+
+#define TIMER_GPTMCTL_TAEN_SHIFT         0    /* Bits 0:   GPTM Timer A Enable */
+#define TIMER_GPTMCTL_TAEN_MASK          (0x01 << TIMER_GPTMCTL_TAEN_SHIFT)
+#define TIMER_GPTMCTL_TASTALL_SHIFT      1    /* Bits 1:   GPTM Timer A Stall Enable */
+#define TIMER_GPTMCTL_TASTALL_MASK       (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT)
+
+/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */
+
+#define TIMER_GPTMIMR_TATOIM_SHIFT       0    /* Bits 0:   GPTM Timer A Time-Out Interrupt Mask */
+#define TIMER_GPTMIMR_TATOIM_MASK        (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT)
+
+/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */
+
+#define TIMER_GPTMRIS_TATORIS_SHIFT      0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt */
+#define TIMER_GPTMRIS_TATORIS_MASK       (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT)
+
+/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */
+
+#define TIMER_GPTMICR_TATOCINT_SHIFT     0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt Clear*/
+#define TIMER_GPTMICR_TATOCINT_MASK      (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h
new file mode 100644
index 000000000..0fef5ccf7
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h
@@ -0,0 +1,347 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_uart.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* UART register offsets ************************************************************/
+
+#define LM3S_UART_DR_OFFSET        0x000 /* UART Data */
+#define LM3S_UART_RSR_OFFSET       0x004 /* UART Receive Status */
+#define LM3S_UART_ECR_OFFSET       0x004 /* UART Error Clear */
+#define LM3S_UART_FR_OFFSET        0x018 /* UART Flag */
+#define LM3S_UART_ILPR_OFFSET      0x020 /* UART IrDA Low-Power Register */
+#define LM3S_UART_IBRD_OFFSET      0x024 /* UART Integer Baud-Rate Divisor*/
+#define LM3S_UART_FBRD_OFFSET      0x028 /* UART Fractional Baud-Rate Divisor */
+#define LM3S_UART_LCRH_OFFSET      0x02c /* UART Line Control */
+#define LM3S_UART_CTL_OFFSET       0x030 /* UART Control */
+#define LM3S_UART_IFLS_OFFSET      0x034 /* UART Interrupt FIFO Level Select */
+#define LM3S_UART_IM_OFFSET        0x038 /* UART Interrupt Mask */
+#define LM3S_UART_RIS_OFFSET       0x03c /* UART Raw Interrupt Status */
+#define LM3S_UART_MIS_OFFSET       0x040 /* UART Masked Interrupt Status */
+#define LM3S_UART_ICR_OFFSET       0x044 /* UART Interrupt Clear */
+#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
+#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
+#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
+#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
+#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
+#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
+#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
+#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
+#define LM3S_UART_PCELLID0_OFFSET  0xff0 /* UART PrimeCell Identification 0 */
+#define LM3S_UART_PCELLID1_OFFSET  0xff4 /* UART PrimeCell Identification 1 */
+#define LM3S_UART_PCELLID2_OFFSET  0xff8 /* UART PrimeCell Identification 2 */
+#define LM3S_UART_PCELLID3_OFFSET  0xffc /* UART PrimeCell Identification 3 */
+
+/* UART register addresses **********************************************************/
+
+#define LM3S_UART_BASE(n)          (LM3S_UART0_BASE + (n)*0x01000)
+
+#define LM3S_UART_DR(n)            (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
+#define LM3S_UART_RSR(n)           (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART_ECR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART_FR(n)            (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
+#define LM3S_UART_ILPR(n)          (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART_IBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART_FBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART_LCRH(n)          (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART_CTL(n)           (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART_IFLS(n)          (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART_IM(n)            (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
+#define LM3S_UART_RIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART_MIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART_ICR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART_PERIPHID4(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART_PERIPHID5(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART_PERIPHID6(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART_PERIPHID7(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART_PERIPHID0(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART_PERIPHID1(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART_PERIPHID2(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART_PERIPHID3(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART_PCELLID0(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART_PCELLID1(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART_PCELLID2(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART_PCELLID3(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
+
+#define LM3S_UART0_DR              (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
+#define LM3S_UART0_RSR             (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART0_ECR             (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART0_FR              (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
+#define LM3S_UART0_ILPR            (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART0_IBRD            (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART0_FBRD            (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART0_LCRH            (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART0_CTL             (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART0_IFLS            (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART0_IM              (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
+#define LM3S_UART0_RIS             (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART0_MIS             (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART0_ICR             (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART0_PERIPHID4       (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART0_PERIPHID5       (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART0_PERIPHID6       (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART0_PERIPHID7       (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART0_PERIPHID0       (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART0_PERIPHID1       (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART0_PERIPHID2       (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART0_PERIPHID3       (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART0_PCELLID0        (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART0_PCELLID1        (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART0_PCELLID2        (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART0_PCELLID3        (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
+
+#define LM3S_UART1_DR              (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
+#define LM3S_UART1_RSR             (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART1_ECR             (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART1_FR              (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
+#define LM3S_UART1_ILPR            (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART1_IBRD            (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART1_FBRD            (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART1_LCRH            (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART1_CTL             (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART1_IFLS            (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART1_IM              (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
+#define LM3S_UART1_RIS             (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART1_MIS             (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART1_ICR             (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART1_PERIPHID4       (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART1_PERIPHID5       (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART1_PERIPHID6       (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART1_PERIPHID7       (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART1_PERIPHID0       (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART1_PERIPHID1       (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART1_PERIPHID2       (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART1_PERIPHID3       (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART1_PCELLID0        (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART1_PCELLID1        (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART1_PCELLID2        (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART1_PCELLID3        (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
+
+/* UART register bit settings *******************************************************/
+
+/* UART Data (DR), offset 0x000 */
+
+#define UART_DR_DATA_SHIFT         0         /* Bits 7-0: Data Transmitted or Received */
+#define UART_DR_DATA_MASK          (0xff << UART_DR_DATA_SHIFT)
+#define UART_DR_FE                 (1 << 8)  /* Bit 8:  UART Framing Error */
+#define UART_DR_PE                 (1 << 9)  /* Bit 9:  UART Parity Error */
+#define UART_DR_BE                 (1 << 10) /* Bit 10: UART Break Error */
+#define UART_DR_OE                 (1 << 11) /* Bit 11: UART Overrun Error */
+
+/* UART Receive Status (RSR), offset 0x004 */
+
+#define UART_RSR_FE                (1 << 0)  /* Bit 0:  UART Framing Error */
+#define UART_RSR_PE                (1 << 1)  /* Bit 1:  UART Parity Error */
+#define UART_RSR_BE                (1 << 2)  /* Bit 2:  UART Break Error */
+#define UART_RSR_OE                (1 << 3)  /* Bit 3:  UART Overrun Error */
+
+/* UART Error Clear (ECR), offset 0x004 */
+/* Writing any value to this register clears pending error indications */
+
+/* UART Flag (FR), offset 0x018 */
+
+#define UART_FR_BUSY               (1 << 3)  /* Bit 3:  UART Busy */
+#define UART_FR_RXFE               (1 << 4)  /* Bit 4:  UART Receive FIFO Empty */
+#define UART_FR_TXFF               (1 << 5)  /* Bit 5:  UART Transmit FIFO Full */
+#define UART_FR_RXFF               (1 << 6)  /* Bit 6:  UART Receive FIFO Full */
+#define UART_FR_TXFE               (1 << 7)  /* Bit 7:  UART Transmit FIFO Empty */
+
+/* UART IrDA Low-Power Register (ILPR), offset 0x020 */
+
+#define UART_ILPR_DVSR_MASK        (0xff)    /* Bits 7-0: IrDA Low-Power Divisor */
+
+/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */
+
+#define UART_IBRD_DIVINT_MASK      (0xffff)  /* Bits 15-0: Integer Baud-Rate Divisor */
+
+/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */
+
+#define UART_FBRD_DIVFRAC_MASK     (0x3f)    /* Bits 5-0: Fractional Baud-Rate Divisor */
+
+/* Register 7: UART Line Control (LCRH), offset 0x02C */
+
+#define UART_LCRH_BRK              (1 << 0)  /* Bit 0:  UART Send Break */
+#define UART_LCRH_PEN              (1 << 1)  /* Bit 1:  UART Parity Enable */
+#define UART_LCRH_EPS              (1 << 2)  /* Bit 2:  UART Even Parity Select */
+#define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
+#define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
+#define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
+#define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
+#  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
+#  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
+#  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
+#  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
+#define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
+
+/* UART Control (CTL), offset 0x030 */
+
+#define UART_CTL_UARTEN            (1 << 0)  /* Bit 0:  UART Enable */
+#define UART_CTL_SIREN             (1 << 1)  /* Bit 1:  UART SIR Enable */
+#define UART_CTL_SIRLP             (1 << 2)  /* Bit 2:  UART SIR Low Power Mode */
+#define UART_CTL_LBE               (1 << 7)  /* Bit 7:  UART Loop Back Enable */
+#define UART_CTL_TXE               (1 << 8)  /* Bit 8:  UART Transmit Enable */
+#define UART_CTL_RXE               (1 << 9)  /* Bit 9:  UART Receive Enable */
+
+/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */
+
+#define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */
+#define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
+#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+#define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 5-3: UART Receive Interrupt FIFO Level Select */
+#define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
+#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
+
+/* UART Interrupt Mask (IM), offset 0x038 */
+
+#define UART_IM_RXIM               (1 << 4)  /* Bit 4:  UART Receive Interrupt Mask */
+#define UART_IM_TXIM               (1 << 5)  /* Bit 5:  UART Transmit Interrupt Mask */
+#define UART_IM_RTIM               (1 << 6)  /* Bit 6:  UART Receive Time-Out Interrupt Mask */
+#define UART_IM_FEIM               (1 << 7)  /* Bit 7:  UART Framing Error Interrupt Mask */
+#define UART_IM_PEIM               (1 << 8)  /* Bit 8:  UART Parity Error Interrupt Mask */
+#define UART_IM_BEIM               (1 << 9)  /* Bit 9:  UART Break Error Interrupt Mask */
+#define UART_IM_OEIM               (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */
+
+
+/* UART Raw Interrupt Status (RIS), offset 0x03c */
+
+#define UART_RIS_RXRIS             (1 << 4)  /* Bit 4:  UART Receive Raw Interrupt Status */
+#define UART_RIS_TXRIS             (1 << 5)  /* Bit 5:  UART Transmit Raw Interrupt Status */
+#define UART_RIS_RTRIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Raw Interrupt Status */
+#define UART_RIS_FERIS             (1 << 7)  /* Bit 7:  UART Framing Error Raw Interrupt Status */
+#define UART_RIS_PERIS             (1 << 8)  /* Bit 8:  UART Parity Error Raw Interrupt Status */
+#define UART_RIS_BERIS             (1 << 9)  /* Bit 9:  UART Break Error Raw Interrupt Status */
+#define UART_RIS_OERIS             (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */
+
+/* UART Masked Interrupt Status (MIS), offset 0x040 */
+
+#define UART_MIS_RXMIS             (1 << 4)  /* Bit 4:  UART Receive Masked Interrupt Status */
+#define UART_MIS_TXMIS             (1 << 5)  /* Bit 5:  UART Transmit Masked Interrupt Status */
+#define UART_MIS_RTMIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Masked Interrupt Status */
+#define UART_MIS_FEMIS             (1 << 7)  /* Bit 7:  UART Framing Error Masked Interrupt Status */
+#define UART_MIS_PEMIS             (1 << 8)  /* Bit 8:  UART Parity Error Masked Interrupt Status */
+#define UART_MIS_BEMIS             (1 << 9)  /* Bit 9:  UART Break Error Masked Interrupt Status */
+#define UART_MIS_OEMIS             (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */
+
+/* UART Interrupt Clear (ICR), offset 0x044 */
+
+#define UART_ICR_RXIC             (1 << 4)  /* Bit 4:  Receive Interrupt Clear */
+#define UART_ICR_TXIC             (1 << 5)  /* Bit 5:  Transmit Interrupt Clear */
+#define UART_ICR_RTIC             (1 << 6)  /* Bit 6:  Receive Time-Out Interrupt Clear */
+#define UART_ICR_FEIC             (1 << 7)  /* Bit 7:  Framing Error Interrupt Clear */
+#define UART_ICR_PEIC             (1 << 8)  /* Bit 8:  Parity Error Interrupt Clear */
+#define UART_ICR_BEIC             (1 << 9)  /* Bit 9:  Break Error Interrupt Clear */
+#define UART_ICR_OEIC             (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
+ */
+
+/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
+
+#define UART_PERIPHID4_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
+
+/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
+
+#define UART_PERIPHID5_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
+
+/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
+
+#define UART_PERIPHID6_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
+
+/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
+
+#define UART_PERIPHID7_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
+
+/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
+
+#define UART_PERIPHID0_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
+
+/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
+
+#define UART_PERIPHID1_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
+
+/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
+
+#define UART_PERIPHID2_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
+
+/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
+
+#define UART_PERIPHID3_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
+
+/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
+
+#define UART_CELLID0_MASK         (0xff)    /* UART PrimeCell ID Register[7:0] */
+
+/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
+
+#define UART_CELLID1_MASK         (0xff)    /* UART PrimeCell ID Register[15:8] */
+
+/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
+
+#define UART_CELLID02MASK         (0xff)    /* UART PrimeCell ID Register[23:16] */
+
+/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
+
+#define UART_CELLID3_MASK         (0xff)    /* UART PrimeCell ID Register[31:24] */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h
new file mode 100644
index 000000000..c52857847
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h
@@ -0,0 +1,69 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm_memorymap.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the memory map file for the specific Stellaris chip */
+
+#ifdef CONFIG_ARCH_CHIP_LM3S
+#  include "chip/lm3s_memorymap.h"
+#else
+#  error "Unsupported Stellaris memory map"
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_epi.h b/nuttx/arch/arm/src/lm3s/lm3s_epi.h
deleted file mode 100644
index 90c9bfb7f..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_epi.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_epi.h
- *
- *   Copyright (C) 2009-2012 Max Neklyudov. All rights reserved.
- *   Author: Max Neklyudov <macscomp@gmail.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_EPI_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_EPI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* External Peripheral Interface Register Offsets ***********************************/
-
-#define LM3S_EPI_CFG_OFFSET           0x000
-#define LM3S_EPI_SDRAMCFG_OFFSET      0x010
-#define LM3S_EPI_ADDRMAP_OFFSET       0x01C
-#define LM3S_EPI_STAT_OFFSET          0x060
-#define LM3S_EPI_BAUD_OFFSET          0x004
-
-/* External Peripheral Interface Register Addresses *********************************/
-
-#define LM3S_EPI0_CFG                 (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
-#define LM3S_EPI0_SDRAMCFG            (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
-#define LM3S_EPI0_ADDRMAP             (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
-#define LM3S_EPI0_STAT                (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
-#define LM3S_EPI0_BAUD                (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
-
-/* External Peripheral Interface Register Bit Definitions ***************************/
-
-/* EPI Configuration (EPICFG), offset 0x000 */
-
-#define EPI_CFG_MODE_SHIFT            0         /* Bits 3-0: Mode Select */
-#define EPI_CFG_MODE_MASK             (0x1f << EPI_CFG_MODE_SHIFT)
-#  define EPI_CFG_MODE_SDRAM          (0x11 << EPI_CFG_MODE_SHIFT)  /* SDRAM + BLKEN */
-
-/* EPI Address Map (EPIADDRMAP), offset 0x01C */
-
-#define EPI_ADDRMAP_ERADR_SHIFT       0       /* Bits 1-0: External RAM Address */
-#define EPI_ADDRMAP_ERADR_MASK        (0x3 << EPI_ADDRMAP_ERADR_SHIFT)
-#  define EPI_ADDRMAP_ERADR_6         (0x1 << EPI_ADDRMAP_ERADR_SHIFT)
-#  define EPI_ADDRMAP_ERADR_8         (0x2 << EPI_ADDRMAP_ERADR_SHIFT)
-#define EPI_ADDRMAP_ERSZ_SHIFT        2       /* Bits 3-2: External RAM Size */
-#define EPI_ADDRMAP_ERSZ_MASK         (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_256B       (0x0 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_64KB       (0x1 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_16MB       (0x2 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_512MB      (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
-
-/* EPI Status (EPISTAT), offset 0x060 */
-
-#define EPI_STAT_INITSEQ_SHIFT        6       /* Bits 6: Initialization Sequence */
-#define EPI_STAT_INITSEQ_MASK         (0x1 << EPI_STAT_INITSEQ_SHIFT)
-
-/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */
-
-#define EPI_SDRAMCFG_SIZE_SHIFT       0       /* Bits 1-0: Size of SDRAM */
-#define EPI_SDRAMCFG_SIZE_MASK        (3 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_8MB       (0x0 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_16MB      (0x1 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_32MB      (0x2 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_64MB      (0x3 << EPI_SDRAMCFG_SIZE_SHIFT)
-#define EPI_SDRAMCFG_RFSH_SHIFT       16      /* Bits 26-16: Refresh Counter */
-#define EPI_SDRAMCFG_RFSH_MASK        (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT)
-#  define EPI_SDRAMCFG_RFSH(n)        ((n) << EPI_SDRAMCFG_RFSH_SHIFT)
-#define EPI_SDRAMCFG_FREQ_SHIFT       30      /* EPI Frequency Range */
-#define EPI_SDRAMCFG_FREQ_MASK        (3 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_0_15MHZ   (0x0 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_15_30MHZ  (0x1 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_30_50MHZ  (0x2 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT)
-
-/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */
-
-#define EPI_BAUD_COUNT0_SHIFT         0
-#define EPI_BAUD_COUNT0_MASK          (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
-#  define EPI_BAUD_COUNT0(n)          ((n) << EPI_BAUD_COUNT0_SHIFT)
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_EPI_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h
deleted file mode 100644
index 71833b271..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_ethernet.h
- *
- *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/net/mii.h>
-
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Ethernet Controller Register Offsets *********************************************/
-
-/* Ethernet MAC Register Offsets */
-
-#define LM3S_MAC_RIS_OFFSET   0x000 /* Ethernet MAC Raw Interrupt Status */
-#define LM3S_MAC_IACK_OFFSET  0x000 /* Ethernet MAC Acknowledge */
-#define LM3S_MAC_IM_OFFSET    0x004 /* Ethernet MAC Interrupt Mask */
-#define LM3S_MAC_RCTL_OFFSET  0x008 /* Ethernet MAC Receive Control */
-#define LM3S_MAC_TCTL_OFFSET  0x00c /* Ethernet MAC Transmit Control */
-#define LM3S_MAC_DATA_OFFSET  0x010 /* Ethernet MAC Data */
-#define LM3S_MAC_IA0_OFFSET   0x014 /* Ethernet MAC Individual Address 0 */
-#define LM3S_MAC_IA1_OFFSET   0x018 /* Ethernet MAC Individual Address 1 */
-#define LM3S_MAC_THR_OFFSET   0x01c /* Ethernet MAC Threshold */
-#define LM3S_MAC_MCTL_OFFSET  0x020 /* Ethernet MAC Management Control */
-#define LM3S_MAC_MDV_OFFSET   0x024 /* Ethernet MAC Management Divider */
-#define LM3S_MAC_MTXD_OFFSET  0x02c /* Ethernet MAC Management Transmit Data */
-#define LM3S_MAC_MRXD_OFFSET  0x030 /* Ethernet MAC Management Receive Data */
-#define LM3S_MAC_NP_OFFSET    0x034 /* Ethernet MAC Number of Packets */
-#define LM3S_MAC_TR_OFFSET    0x038 /* Ethernet MAC Transmission Request */
-#ifdef LM3S_ETHTS
-#  define LM3S_MAC_TS_OFFSET  0x03c /* Ethernet MAC Time Stamp Configuration */
-#endif
-
-/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
-
-/* Ethernet Controller Register Addresses *******************************************/
-
-#define LM3S_MAC_RIS          (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
-#define LM3S_MAC_IACK         (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
-#define LM3S_MAC_IM           (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
-#define LM3S_MAC_RCTL         (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
-#define LM3S_MAC_TCTL         (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
-#define LM3S_MAC_DATA         (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
-#define LM3S_MAC_IA0          (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
-#define LM3S_MAC_IA1          (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
-#define LM3S_MAC_THR          (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
-#define LM3S_MAC_MCTL         (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
-#define LM3S_MAC_MDV          (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
-#define LM3S_MAC_MTXD         (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
-#define LM3S_MAC_MRXD         (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
-#define LM3S_MAC_NP           (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
-#define LM3S_MAC_TR           (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
-#ifdef LM3S_ETHTS
-#  define LM3S_MAC_TS         (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
-#endif
-
-/* Memory Mapped MII Management Registers */
-
-#define MAC_MII_MCR           (LM3S_ETHCON_BASE + MII_MCR)
-#define MAC_MII_MSR           (LM3S_ETHCON_BASE + MII_MSR)
-#define MAC_MII_PHYID1        (LM3S_ETHCON_BASE + MII_PHYID1)
-#define MAC_MII_PHYID2        (LM3S_ETHCON_BASE + MII_PHYID2)
-#define MAC_MII_ADVERTISE     (LM3S_ETHCON_BASE + MII_ADVERTISE)
-#define MAC_MII_LPA           (LM3S_ETHCON_BASE + MII_LPA)
-#define MAC_MII_EXPANSION     (LM3S_ETHCON_BASE + MII_EXPANSION)
-#define MAC_MII_VSPECIFIC     (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
-#define MAC_MII_INTCS         (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
-#define MAC_MII_DIAGNOSTIC    (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
-#define MAC_MII_XCVRCONTROL   (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
-#define MAC_MII_LEDCONFIG     (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
-#define MAC_MII_MDICONTROL    (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
-
-/* Ethernet Controller Register Bit Definitions *************************************/
-
-/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
-
-#define MAC_RIS_RXINT         (1 << 0)  /* Bit 0:  Packet Received */
-#define MAC_RIS_TXER          (1 << 1)  /* Bit 1:  Transmit Error */
-#define MAC_RIS_TXEMP         (1 << 2)  /* Bit 2:  Transmit FIFO Empty */
-#define MAC_RIS_FOV           (1 << 3)  /* Bit 3:  FIFO Overrun */
-#define MAC_RIS_RXER          (1 << 4)  /* Bit 4:  Receive Error */
-#define MAC_RIS_MDINT         (1 << 5)  /* Bit 5:  MII Transaction Complete */
-#define MAC_RIS_PHYINT        (1 << 6)  /* Bit 6:  PHY Interrupt */
-
-#define MAC_IACK_RXINT        (1 << 0)  /* Bit 0:  Clear Packet Received */
-#define MAC_IACK_TXER         (1 << 1)  /* Bit 1:  Clear Transmit Error */
-#define MAC_IACK_TXEMP        (1 << 2)  /* Bit 2:  Clear Transmit FIFO Empty */
-#define MAC_IACK_FOV          (1 << 3)  /* Bit 3:  Clear FIFO Overrun */
-#define MAC_IACK_RXER         (1 << 4)  /* Bit 4:  Clear Receive Error */
-#define MAC_IACK_MDINT        (1 << 5)  /* Bit 5:  Clear MII Transaction Complete */
-#define MAC_IACK_PHYINT       (1 << 6)  /* Bit 6:  Clear PHY Interrupt */
-
-/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
-
-#define MAC_IM_RXINTM         (1 << 0)  /* Bit 0:  Mask Packet Received */
-#define MAC_IM_TXERM          (1 << 1)  /* Bit 1:  Mask Transmit Error */
-#define MAC_IM_TXEMPM         (1 << 2)  /* Bit 2:  Mask Transmit FIFO Empty */
-#define MAC_IM_FOVM           (1 << 3)  /* Bit 3:  Mask FIFO Overrun */
-#define MAC_IM_RXERM          (1 << 4)  /* Bit 4:  Mask Receive Error */
-#define MAC_IM_MDINTM         (1 << 5)  /* Bit 5:  Mask MII Transaction Complete */
-#define MAC_IM_PHYINTM        (1 << 6)  /* Bit 6:  Mask PHY Interrupt */
-#define MAC_IM_ALLINTS        0x7f
-
-/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
-
-#define MAC_RCTL_RXEN         (1 << 0)  /* Bit 0:  Enable Receiver */
-#define MAC_RCTL_AMUL         (1 << 1)  /* Bit 1:  Enable Multicast Frames */
-#define MAC_RCTL_PRMS         (1 << 2)  /* Bit 2:  Enable Promiscuous Mode */
-#define MAC_RCTL_BADCRC       (1 << 3)  /* Bit 3:  Enable Reject Bad CRC */
-#define MAC_RCTL_RSTFIFO      (1 << 4)  /* Bit 4:  Clear Receive FIFO */
-
-/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
-
-#define MAC_TCTL_TXEN         (1 << 0)  /* Bit 0:  Enable Transmitter */
-#define MAC_TCTL_PADEN        (1 << 1)  /* Bit 1:  Enable Packet Padding */
-#define MAC_TCTL_CRC          (1 << 2)  /* Bit 2:  Enable CRC Generation */
-#define MAC_TCTL_DUPLEX       (1 << 4)  /* Bit 4:  Enable Duplex Mode */
-
-/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
-
-#define MAC_THR_MASK          0x3f      /* Bits 5-0: Threshold Value */
-
-/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
-
-#define MAC_MCTL_START        (1 << 0)  /* Bit 0:  MII Register Transaction Enable */
-#define MAC_MCTL_WRITE        (1 << 1)  /* Bit 1:  MII Register Transaction Type */
-#define MAC_MCTL_REGADR_SHIFT 3         /* Bits 7-3: MII Register Address */
-#define MAC_MCTL_REGADR_MASK  (0x1f << MAC_MCTL_REGADR_SHIFT)
-
-/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
-
-#define MAC_MDV_MASK          0xff      /* Bits 7-0: Clock Divider */
-
-/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
-
-#define MAC_MTXD_MASK         0xffff    /* Bits 15-0: MII Register Transmit Data */
-
-/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
-
-#define MAC_MTRD_MASK         0xffff    /* Bits 15-0: MII Register Receive Data */
-
-/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
-
-#define MAC_NP_MASK           0x3f      /* Bits 5-0: Number of Packets in Receive FIFO */
-
-/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
-
-#define MAC_TR_NEWTX          (1 << 0)  /* Bit 0:  New Transmission */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_flash.h b/nuttx/arch/arm/src/lm3s/lm3s_flash.h
deleted file mode 100644
index 83e388921..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_flash.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_flash.h
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* FLASH register offsets ***********************************************************/
-
-/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
- * control base address of LM3S_FLASHCON_BASE.
- */
-
-#define LM3S_FLASH_FMA_OFFSET       0x000 /* Flash memory address */
-#define LM3S_FLASH_FMD_OFFSET       0x004 /* Flash memory data */
-#define LM3S_FLASH_FMC_OFFSET       0x008 /* Flash memory control */
-#define LM3S_FLASH_FCRIS_OFFSET     0x00c /* Flash controller raw interrupt status */
-#define LM3S_FLASH_FCIM_OFFSET      0x010 /* Flash controller interrupt mask */
-#define LM3S_FLASH_FCMISC_OFFSET    0x014 /* Flash controller masked interrupt status and clear */ */
-
-/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
- * System Control base address of LM3S_SYSCON_BASE
- */
-
-#define LM3S_FLASH_FMPRE_OFFSET     0x130 /* Flash memory protection read enable */
-#define LM3S_FLASH_FMPPE_OFFSET     0x134 /* Flash memory protection program enable */
-#define LM3S_FLASH_USECRL_OFFSET    0x140 /* USec Reload */
-#define LM3S_FLASH_USERDBG_OFFSET   0x1d0 /* User Debug */
-#define LM3S_FLASH_USERREG0_OFFSET  0x1e0 /* User Register 0 */
-#define LM3S_FLASH_USERREG1_OFFSET  0x1e4 /* User Register 1 */
-#define LM3S_FLASH_FMPRE0_OFFSET    0x200 /* Flash Memory Protection Read Enable 0 */
-#define LM3S_FLASH_FMPRE1_OFFSET    0x204 /* Flash Memory Protection Read Enable 1 */
-#define LM3S_FLASH_FMPRE2_OFFSET    0x208 /* Flash Memory Protection Read Enable 2 */
-#define LM3S_FLASH_FMPRE3_OFFSET    0x20c /* Flash Memory Protection Read Enable 3 */
-#define LM3S_FLASH_FMPPE0_OFFSET    0x400 /* Flash Memory Protection Program Enable 0 */
-#define LM3S_FLASH_FMPPE1_OFFSET    0x404 /* Flash Memory Protection Program Enable 1 */
-#define LM3S_FLASH_FMPPE2_OFFSET    0x408 /* Flash Memory Protection Program Enable 2 */
-#define LM3S_FLASH_FMPPE3_OFFSET    0x40c /*  Flash Memory Protection Program Enable 3 */
-
-/* FLASH register addresses *********************************************************/
-
-/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
- * control base address of LM3S_FLASHCON_BASE.
- */
-
-#define LM3S_FLASH_FMA              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
-#define LM3S_FLASH_FMD              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
-#define LM3S_FLASH_FMC              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
-#define LM3S_FLASH_FCRIS            (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
-#define LM3S_FLASH_FCIM             (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
-#define LM3S_FLASH_FCMISC           (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
-
-/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
- * System Control base address of LM3S_SYSCON_BASE
- */
-
-#define LM3S_FLASH_FMPRE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
-#define LM3S_FLASH_FMPPE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
-#define LM3S_FLASH_USECRL           (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
-#define LM3S_FLASH_USERDBG          (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
-#define LM3S_FLASH_USERREG0         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
-#define LM3S_FLASH_USERREG1         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
-#define LM3S_FLASH_FMPRE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
-#define LM3S_FLASH_FMPRE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
-#define LM3S_FLASH_FMPRE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
-#define LM3S_FLASH_FMPRE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
-#define LM3S_FLASH_FMPPE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
-#define LM3S_FLASH_FMPPE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
-#define LM3S_FLASH_FMPPE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
-#define LM3S_FLASH_FMPPE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
-
-/* FLASH register bit defitiions ****************************************************/
-/* To be provided */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.h b/nuttx/arch/arm/src/lm3s/lm3s_gpio.h
deleted file mode 100644
index 066666432..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_gpio.h
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_GPIO_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_GPIO_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* GPIO Register Offsets ************************************************************/
-
-#define LM3S_GPIO_DATA_OFFSET         0x000 /* GPIO Data */
-#define LM3S_GPIO_DIR_OFFSET          0x400 /* GPIO Direction */
-#define LM3S_GPIO_IS_OFFSET           0x404 /* GPIO Interrupt Sense */
-#define LM3S_GPIO_IBE_OFFSET          0x408 /* GPIO Interrupt Both Edges */
-#define LM3S_GPIO_IEV_OFFSET          0x40c /* GPIO Interrupt Event */
-#define LM3S_GPIO_IM_OFFSET           0x410 /* GPIO Interrupt Mask */
-#define LM3S_GPIO_RIS_OFFSET          0x414 /* GPIO Raw Interrupt Status */
-#define LM3S_GPIO_MIS_OFFSET          0x418 /* GPIO Masked Interrupt Status */
-#define LM3S_GPIO_ICR_OFFSET          0x41c /* GPIO Interrupt Clear */
-#define LM3S_GPIO_AFSEL_OFFSET        0x420 /* GPIO Alternate Function */
-#define LM3S_GPIO_DR2R_OFFSET         0x500 /* Select GPIO 2-mA Drive Select */
-#define LM3S_GPIO_DR4R_OFFSET         0x504 /* GPIO 4-mA Drive Select */
-#define LM3S_GPIO_DR8R_OFFSET         0x508 /* GPIO 8-mA Drive Select */
-#define LM3S_GPIO_ODR_OFFSET          0x50c /* GPIO Open Drain Select */
-#define LM3S_GPIO_PUR_OFFSET          0x510 /* GPIO Pull-Up Select */
-#define LM3S_GPIO_PDR_OFFSET          0x514 /* GPIO Pull-Down Select */
-#define LM3S_GPIO_SLR_OFFSET          0x518 /* GPIO Slew Rate Control Select */
-#define LM3S_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
-#define LM3S_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
-#define LM3S_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
-#define LM3S_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
-#define LM3S_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
-#define LM3S_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
-#define LM3S_GPIO_PERIPHID7_OFFSET    0xfdc /* GPIO Peripheral Identification 7 */
-#define LM3S_GPIO_PERIPHID0_OFFSET    0xfe0 /* GPIO Peripheral Identification 0 */
-#define LM3S_GPIO_PERIPHID1_OFFSET    0xfe4 /* GPIO Peripheral Identification 1 */
-#define LM3S_GPIO_PERIPHID2_OFFSET    0xfe8 /* GPIO Peripheral Identification 2 */
-#define LM3S_GPIO_PERIPHID3_OFFSET    0xfec /* GPIO Peripheral Identification 3 */
-#define LM3S_GPIO_PCELLID0_OFFSET     0xff0 /* GPIO PrimeCell Identification 0 */
-#define LM3S_GPIO_PCELLID1_OFFSET     0xff4 /* GPIO PrimeCell Identification 1 */
-#define LM3S_GPIO_PCELLID2_OFFSET     0xff8 /* GPIO PrimeCell Identification 2 */
-#define LM3S_GPIO_PCELLID3_OFFSET     0xffc /* GPIO PrimeCell Identification 3*/
-
-/* GPIO Register Addresses **********************************************************/
-
-#define LM3S_GPIOA_DATA               (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOA_DIR                (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOA_IS                 (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOA_IBE                (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOA_IEV                (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOA_IM                 (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOA_RIS                (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOA_MIS                (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOA_ICR                (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOA_AFSEL              (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOA_DR2R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOA_DR4R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOA_DR8R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOA_ODR                (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOA_PUR                (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOA_PDR                (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOA_SLR                (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOA_DEN                (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOA_LOCK               (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOA_CR                 (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOA_PERIPHID4          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOA_PERIPHID5          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOA_PERIPHID6          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOA_PERIPHID7          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOA_PERIPHID0          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOA_PERIPHID1          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOA_PERIPHID2          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOA_PERIPHID3          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOA_PCELLID0           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOA_PCELLID1           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOA_PCELLID2           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOA_PCELLID3           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOB_DATA               (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOB_DIR                (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOB_IS                 (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOB_IBE                (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOB_IEV                (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOB_IM                 (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOB_RIS                (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOB_MIS                (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOB_ICR                (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOB_AFSEL              (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOB_DR2R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOB_DR4R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOB_DR8R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOB_ODR                (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOB_PUR                (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOB_PDR                (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOB_SLR                (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOB_DEN                (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOB_LOCK               (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOB_CR                 (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOB_PERIPHID4          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOB_PERIPHID5          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOB_PERIPHID6          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOB_PERIPHID7          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOB_PERIPHID0          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOB_PERIPHID1          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOB_PERIPHID2          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOB_PERIPHID3          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOB_PCELLID0           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOB_PCELLID1           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOB_PCELLID2           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOB_PCELLID3           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOC_DATA               (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOC_DIR                (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOC_IS                 (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOC_IBE                (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOC_IEV                (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOC_IM                 (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOC_RIS                (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOC_MIS                (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOC_ICR                (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOC_AFSEL              (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOC_DR2R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOC_DR4R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOC_DR8R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOC_ODR                (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOC_PUR                (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOC_PDR                (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOC_SLR                (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOC_DEN                (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOC_LOCK               (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOC_CR                 (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOC_PERIPHID4          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOC_PERIPHID5          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOC_PERIPHID6          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOC_PERIPHID7          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOC_PERIPHID0          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOC_PERIPHID1          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOC_PERIPHID2          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOC_PERIPHID3          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOC_PCELLID0           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOC_PCELLID1           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOC_PCELLID2           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOC_PCELLID3           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOD_DATA               (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOD_DIR                (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOD_IS                 (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOD_IBE                (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOD_IEV                (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOD_IM                 (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOD_RIS                (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOD_MIS                (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOD_ICR                (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOD_AFSEL              (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOD_DR2R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOD_DR4R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOD_DR8R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOD_ODR                (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOD_PUR                (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOD_PDR                (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOD_SLR                (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOD_DEN                (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOD_LOCK               (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOD_CR                 (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOD_PERIPHID4          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOD_PERIPHID5          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOD_PERIPHID6          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOD_PERIPHID7          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOD_PERIPHID0          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOD_PERIPHID1          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOD_PERIPHID2          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOD_PERIPHID3          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOD_PCELLID0           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOD_PCELLID1           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOD_PCELLID2           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOD_PCELLID3           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOE_DATA               (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOE_DIR                (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOE_IS                 (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOE_IBE                (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOE_IEV                (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOE_IM                 (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOE_RIS                (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOE_MIS                (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOE_ICR                (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOE_AFSEL              (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOE_DR2R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOE_DR4R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOE_DR8R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOE_ODR                (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOE_PUR                (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOE_PDR                (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOE_SLR                (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOE_DEN                (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOE_LOCK               (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOE_CR                 (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOE_PERIPHID4          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOE_PERIPHID5          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOE_PERIPHID6          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOE_PERIPHID7          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOE_PERIPHID0          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOE_PERIPHID1          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOE_PERIPHID2          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOE_PERIPHID3          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOE_PCELLID0           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOE_PCELLID1           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOE_PCELLID2           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOE_PCELLID3           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOF_DATA               (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOF_DIR                (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOF_IS                 (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOF_IBE                (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOF_IEV                (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOF_IM                 (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOF_RIS                (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOF_MIS                (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOF_ICR                (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOF_AFSEL              (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOF_DR2R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOF_DR4R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOF_DR8R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOF_ODR                (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOF_PUR                (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOF_PDR                (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOF_SLR                (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOF_DEN                (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOF_LOCK               (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOF_CR                 (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOF_PERIPHID4          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOF_PERIPHID5          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOF_PERIPHID6          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOF_PERIPHID7          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOF_PERIPHID0          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOF_PERIPHID1          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOF_PERIPHID2          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOF_PERIPHID3          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOF_PCELLID0           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOF_PCELLID1           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOF_PCELLID2           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOF_PCELLID3           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOG_DATA               (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOG_DIR                (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOG_IS                 (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOG_IBE                (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOG_IEV                (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOG_IM                 (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOG_RIS                (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOG_MIS                (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOG_ICR                (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOG_AFSEL              (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOG_DR2R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOG_DR4R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOG_DR8R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOG_ODR                (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOG_PUR                (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOG_PDR                (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOG_SLR                (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOG_DEN                (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOG_LOCK               (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOG_CR                 (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOG_PERIPHID4          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOG_PERIPHID5          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOG_PERIPHID6          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOG_PERIPHID7          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOG_PERIPHID0          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOG_PERIPHID1          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOG_PERIPHID2          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOG_PERIPHID3          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOG_PCELLID0           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOG_PCELLID1           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOG_PCELLID2           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOG_PCELLID3           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOH_DATA               (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOH_DIR                (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOH_IS                 (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOH_IBE                (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOH_IEV                (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOH_IM                 (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOH_RIS                (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOH_MIS                (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOH_ICR                (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOH_AFSEL              (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOH_DR2R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOH_DR4R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOH_DR8R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOH_ODR                (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOH_PUR                (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOH_PDR                (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOH_SLR                (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOH_DEN                (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOH_LOCK               (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOH_CR                 (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOH_PERIPHID4          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOH_PERIPHID5          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOH_PERIPHID6          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOH_PERIPHID7          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOH_PERIPHID0          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOH_PERIPHID1          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOH_PERIPHID2          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOH_PERIPHID3          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOH_PCELLID0           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOH_PCELLID1           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOH_PCELLID2           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOH_PCELLID3           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOJ_DATA               (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOJ_DIR                (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOJ_IS                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOJ_IBE                (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOJ_IEV                (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOJ_IM                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOJ_RIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOJ_MIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOJ_ICR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOJ_AFSEL              (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOJ_DR2R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOJ_DR4R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOJ_DR8R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOJ_ODR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOJ_PUR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOJ_PDR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOJ_SLR                (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOJ_DEN                (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOJ_LOCK               (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOJ_CR                 (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOJ_PERIPHID4          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOJ_PERIPHID5          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOJ_PERIPHID6          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOJ_PERIPHID7          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOJ_PERIPHID0          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOJ_PERIPHID1          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOJ_PERIPHID2          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOJ_PERIPHID3          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOJ_PCELLID0           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOJ_PCELLID1           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOJ_PCELLID2           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOJ_PCELLID3           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_i2c.h b/nuttx/arch/arm/src/lm3s/lm3s_i2c.h
deleted file mode 100644
index a5f0567b9..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_i2c.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_i2c.h
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_I2C_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_I2C_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* I2C Register Offsets *************************************************************/
-
-/* I2C Master */
-
-#define LM3S_I2CM_SA_OFFSET  0x000 /* I2C Master Slave Address */
-#define LM3S_I2CM_CS_OFFSET  0x004 /* I2C Master Control/Status */
-#define LM3S_I2CM_DR_OFFSET  0x008 /* I2C Master Data */
-#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
-#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
-#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
-#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
-#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
-#define LM3S_I2CM_CR_OFFSET  0x020 /* I2C Master Configuration */
-
-/* I2C Slave */
-
-#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
-#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
-#define LM3S_I2CS_DR_OFFSET  0x008 /* I2C Slave Data */
-#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
-#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
-#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
-#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
-
-/* I2C Register Addresses ***********************************************************/
-
-#if LM3S_NI2C > 0
-
-/* I2C Master */
-
-#define LM3S_I2CM_BASE(n)    (LM3S_I2CM0_BASE + (n)*0x1000)
-#define LM3S_I2CM_SA(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM_CS(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM_DR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM_TPR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM_IMR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM_RIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM_MIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM_ICR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM_CR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
-
-/* I2C Slave */
-
-#define LM3S_I2CS_BASE(n)    (LM3S_I2CS0_BASE + (n)*0x1000)
-#define LM3S_I2CS_OAR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS_CSR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS_DR(n)      (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS_IMR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS_RIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS_MIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS_ICR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
-
-/* I2C0 Master */
-
-#define LM3S_I2CM0_SA        (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM0_CS        (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM0_DR        (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM0_TPR       (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM0_IMR       (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM0_RIS       (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM0_MIS       (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM0_ICR       (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM0_CR        (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
-
-/* I2C0 Slave */
-
-#define LM3S_I2CS0_OAR       (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS0_CSR       (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS0_DR        (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS0_IMR       (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS0_RIS       (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS0_MIS       (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS0_ICR       (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
-
-#if LM3S_NI2C > 1
-
-/* I2C1 Master */
-
-#define LM3S_I2CM1_SA        (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM1_CS        (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM1_DR        (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM1_TPR       (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM1_IMR       (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM1_RIS       (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM1_MIS       (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM1_ICR       (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM1_CR        (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
-
-/* I2C1 Slave */
-
-#define LM3S_I2CS1_OAR       (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS1_CSR       (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS1_DR        (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS1_IMR       (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS1_RIS       (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS1_MIS       (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS1_ICR       (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
-
-#endif
-#endif
-
-/* I2C_Register Bit Definitions *****************************************************/
-
-/* I2C Master Slave Address (I2CM_SA), offset 0x000 */
-
-#define I2CM_SA_RS           (1 << 0)  /* Bit 0:  Receive/Send */
-#define I2CM_SA_SA_SHIFT     1         /* Bits 7-1: I2C Slave Address */
-#define I2CM_SA_SA_MASK      (0x7f << I2CM_SA_SA_SHIFT)
-
-/* I2C Master Control/Status (I2CM_CS), offset 0x004 */
-
-#define I2CM_CS_BUSY         (1 << 0)  /* Bit 0:  I2C Busy (read) */
-#define I2CM_CS_ERROR        (1 << 1)  /* Bit 1:  Error in last bus operation (read) */
-#define I2CM_CS_ADRACK       (1 << 2)  /* Bit 2:  Acknowledge Address (read) */
-#define I2CM_CS_DATACK       (1 << 3)  /* Bit 3:  Acknowledge Data (read) */
-#define I2CM_CS_ARBLST       (1 << 4)  /* Bit 4:  Arbitration Lost (read) */
-#define I2CM_CS_IDLE         (1 << 5)  /* Bit 5:  I2C Idle (read) */
-#define I2CM_CS_BUSBSY       (1 << 6)  /* Bit 6:  Bus Busy (read) */
-
-#define I2CM_CS_RUN          (1 << 0)  /* Bit 0:  I2C Master Enable (write) */
-#define I2CM_CS_START        (1 << 1)  /* Bit 1:  Generate START (write) */
-#define I2CM_CS_STOP         (1 << 2)  /* Bit 2:  Generate STOP (write) */
-#define I2CM_CS_ACK          (1 << 3)  /* Bit 3:  Data Acknowledge Enable (write) */
-
-/* I2C Master Data (I2CM_DR), offset 0x008 */
-
-#define I2CM_DR_MASK         0xff      /* Bits 7-0: Data transferred */
-
-/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */
-
-#define I2CM_TPR_MASK        0xff      /* Bits 7-0: SCL Clock Period */
-
-/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */
-
-#define I2CM_IMR_IM          (1 << 0)  /* Bit 0:  Interrupt Mask */
-
-/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */
-
-#define I2CM_RIS_RIS         (1 << 0)  /* Bit 0:  Raw Interrupt Status */
-
-/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */
-
-#define I2CM_MIS_MIS         (1 << 0)  /* Bit 0:  Masked Interrupt Status */
-
-/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */
-
-#define I2CM_ICR_IC          (1 << 0)  /* Bit 0:  Masked Interrupt Status */
-
-/* I2C Master Configuration (I2CM_CR), offset 0x020 */
-
-#define I2CM_CR_LPBK         (1 << 0)  /* Bit 0:: I2C Loopback */
-#define I2CM_CR_MFE          (1 << 4 ) /* Bit 4:  I2C Master Function Enable */
-#define I2CM_CR_SFE          (1 << 5)  /* Bit 5:  I2C Slave Function Enable */
-
-/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */
-
-#define I2CS_OAR_MASK        0xff      /* Bits 7-0: I2C Slave Own Address */
-
-/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */
-
-#define I2CS_CSR_RREQ        (1 << 0)  /* Bit 0:  Receive Request (read) */
-#define I2CS_CSR_TREQ        (1 << 1)  /* Bit 1:  Transmit Request (read) */
-#define I2CS_CSR_FBR         (1 << 2)  /* Bit 2:  First Byte Received (read) */
-
-#define I2CS_CSR_DA          (1 << 0)  /* Bit 0:  Device Active (write) */
-
-/* I2C Slave Data (I2CS_DR), offset 0x008 */
-
-#define I2CS_DR_MASK         0xff      /* Bits 7-0: Data for Transfer */
-
-/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */
-
-#define I2CM_IMR_DATAIM      (1 << 0)  /* Bit 0:  Data Interrupt Mask */
-
-/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */
-
-#define I2CM_RIS_DATARIS     (1 << 0)  /* Bit 0:  Data Raw Interrupt Status */
-
-/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */
-
-#define I2CM_MIS_DATAMIS     (1 << 0)  /* Bit 0:  Data Masked Interrupt Status */
-
-/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */
-
-#define I2CM_ICR_DATAIC      (1 << 0)  /* Bit 0:  Data Interrupt Clear */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_I2C_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
deleted file mode 100644
index be0d8b58d..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_memorymap.h
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_MEMORYMAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Memory map ***********************************************************************/
- 
-#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
-    defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
-                                         /* -0x1fffffff: Reserved */
-#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
-                                         /* -0x21ffffff: Reserved */
-#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
-                                         /* -0x3fffffff: Reserved */
-#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
-                                         /* -0x41ffffff: Peripherals */
-#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
-                                         /* -0xdfffffff: Reserved */
-#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
-#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
-#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
-                                         /* -0xe000dfff: Reserved */
-#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
-                                         /* -0xe003ffff: Reserved */
-#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
-                                         /* -0xffffffff: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
-                                         /* -0x1fffffff: Reserved */
-#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
-                                         /* -0x21ffffff: Reserved */
-#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
-                                         /* -0x3fffffff: Reserved */
-#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
-                                         /* -0x41ffffff: Peripherals */
-#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
-                                         /* -0x5fffffff: Reserved */
-#  define LM3S_EPI0RAM_BASE   0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */
-#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
-#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
-#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
-                                         /* -0xe000dfff: Reserved */
-#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
-                                         /* -0xe003ffff: Reserved */
-#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
-                                         /* -0xffffffff: Reserved */
-#else
-#  error "Memory map not specified for this LM3S chip"
-#endif
-
-/* Peripheral base addresses ********************************************************/
-/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt
- * peripheral modules.  They could probably be combined into one peripheral memory
- * map.  However, keeping them separate does also provide so early, compile-time
- * error detection that makes the duplication worthwhile.
- */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x3fffff: Reserved */
-#  define LM3S_CANCON_BASE    (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN Controller */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
-
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC0_BASE       (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
-#  define LM3S_ADC1_BASE       (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-#  define LM3S_GPIOJ_BASE     (LM3S_PERIPH_BASE + 0x3d000)  /* -0x3dfff: GPIO Port J */
-                                                            /* -0x3ffff: Reserved */
-#  define LM3S_CAN0_BASE      (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN 0 */
-#  define LM3S_CAN1_BASE      (LM3S_PERIPH_BASE + 0x41000)  /* -0x41fff: CAN 1 */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0x49fff: Reserved */
-#  define LM3S_USB_BASE       (LM3S_PERIPH_BASE + 0x50000)  /* -0x50fff: USB */
-                                                            /* -0x53fff: Reserved */
-#  define LM3S_I2S0_BASE      (LM3S_PERIPH_BASE + 0x54000)  /* -0x54fff: I2S 0 */
-                                                            /* -0x57fff: Reserved */
-#  define LM3S_GPIOAAHB_BASE  (LM3S_PERIPH_BASE + 0x58000)  /* -0x58fff: GPIO Port A (AHB aperture) */
-#  define LM3S_GPIOBAHB_BASE  (LM3S_PERIPH_BASE + 0x59000)  /* -0x59fff: GPIO Port B (AHB aperture) */
-#  define LM3S_GPIOCAHB_BASE  (LM3S_PERIPH_BASE + 0x5A000)  /* -0x5afff: GPIO Port C (AHB aperture) */
-#  define LM3S_GPIODAHB_BASE  (LM3S_PERIPH_BASE + 0x5B000)  /* -0x5bfff: GPIO Port D (AHB aperture) */
-#  define LM3S_GPIOEAHB_BASE  (LM3S_PERIPH_BASE + 0x5C000)  /* -0x5cfff: GPIO Port E (AHB aperture) */
-#  define LM3S_GPIOFAHB_BASE  (LM3S_PERIPH_BASE + 0x5D000)  /* -0x5dfff: GPIO Port F (AHB aperture) */
-#  define LM3S_GPIOGAHB_BASE  (LM3S_PERIPH_BASE + 0x5E000)  /* -0x5efff: GPIO Port G (AHB aperture) */
-#  define LM3S_GPIOHAHB_BASE  (LM3S_PERIPH_BASE + 0x5F000)  /* -0x5ffff: GPIO Port H (AHB aperture) */
-#  define LM3S_GPIOJAHB_BASE  (LM3S_PERIPH_BASE + 0x60000)  /* -0x60fff: GPIO Port J (AHB aperture) */
-                                                            /* -0xcffff: Reserved */
-#  define LM3S_EPI0_BASE      (LM3S_PERIPH_BASE + 0xD0000)  /* -0xd0fff: EPI 0 */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-#  define LM3S_UDMA_BASE      (LM3S_PERIPH_BASE + 0xff000)  /* -0xfffff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-#else
-#  error "Peripheral base addresses not specified for this LM3S chip"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.h b/nuttx/arch/arm/src/lm3s/lm3s_ssi.h
deleted file mode 100644
index 482dab326..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_ssi.h
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_SSI_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_SSI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <sys/types.h>
-
-#if LM3S_NSSI > 0
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* SSI register offsets *************************************************************/
-
-#define LM3S_SSI_CR0_OFFSET       0x000 /* SSI Control 0 */
-#define LM3S_SSI_CR1_OFFSET       0x004 /* SSI Control 1 */
-#define LM3S_SSI_DR_OFFSET        0x008 /* SSI Data */
-#define LM3S_SSI_SR_OFFSET        0x00c /* SSI Status */
-#define LM3S_SSI_CPSR_OFFSET      0x010 /* SSI Clock Prescale */
-#define LM3S_SSI_IM_OFFSET        0x014 /* SSI Interrupt Mask */
-#define LM3S_SSI_RIS_OFFSET       0x018 /* SSI Raw Interrupt Status */
-#define LM3S_SSI_MIS_OFFSET       0x01c /* SSI Masked Interrupt Status */
-#define LM3S_SSI_ICR_OFFSET       0x020 /* SSI Interrupt Clear */
-#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
-#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
-#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
-#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
-#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
-#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
-#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
-#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
-#define LM3S_SSI_PCELLID0_OFFSET  0xff0 /* SSI PrimeCell Identification 0 */
-#define LM3S_SSI_PCELLID1_OFFSET  0xff4 /* SSI PrimeCell Identification 1 */
-#define LM3S_SSI_PCELLID2_OFFSET  0xff8 /* SSI PrimeCell Identification 2 */
-#define LM3S_SSI_PCELLID3_OFFSET  0xffc /* SSI PrimeCell Identification 3 */
-
-/* SSI register addresses ***********************************************************/
-
-#define LM3S_SSI0_CR0             (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI0_CR1             (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI0_DR              (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI0_SR              (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI0_CPSR            (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI0_IM              (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI0_RIS             (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI0_MIS             (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI0_ICR             (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI0_PERIPHID4       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI0_PERIPHID5       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI0_PERIPHID6       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI0_PERIPHID7       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI0_PERIPHID0       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI0_PERIPHID1       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI0_PERIPHID2       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI0_PERIPHID3       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI0_PCELLID0        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI0_PCELLID1        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI0_PCELLID2        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI0_PCELLID3        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
-
-#if LM3S_NSSI > 1
-#define LM3S_SSI1_CR0             (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI1_CR1             (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI1_DR              (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI1_SR              (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI1_CPSR            (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI1_IM              (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI1_RIS             (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI1_MIS             (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI1_ICR             (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI1_PERIPHID4       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI1_PERIPHID5       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI1_PERIPHID6       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI1_PERIPHID7       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI1_PERIPHID0       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI1_PERIPHID1       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI1_PERIPHID2       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI1_PERIPHID3       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI1_PCELLID0        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI1_PCELLID1        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI1_PCELLID2        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI1_PCELLID3        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
-
-#define LM3S_SSI_BASE(n)          (LM3S_SSI0_BASE + (n)*0x01000)
-
-#define LM3S_SSI_CR0(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI_CR1(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI_DR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI_SR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI_CPSR(n)          (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI_IM(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI_RIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI_MIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI_ICR(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI_PERIPHID4(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI_PERIPHID5(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI_PERIPHID6(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI_PERIPHID7(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI_PERIPHID0(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI_PERIPHID1(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI_PERIPHID2(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI_PERIPHID3(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI_PCELLID0(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI_PCELLID1(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI_PCELLID2(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI_PCELLID3(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
-#endif /* LM3S_NSSI > 1 */
-
-/* SSI register bit defitiions ******************************************************/
-
-/* SSI Control 0 (SSICR0), offset 0x000 */
-
-#define SSI_CR0_DSS_SHIFT         0         /* Bits 3-0: SSI Data Size Select */
-#define SSI_CR0_DSS_MASK          (0x0f << SSI_CR0_DSS_SHIFT)
-#define   SSI_CR0_DSS(n)          ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
-#define SSI_CR0_FRF_SHIFT         4         /* Bits 5-4: SSI Frame Format Select */
-#define SSI_CR0_FRF_MASK          (3 << SSI_CR0_FRF_SHIFT)
-#define   SSI_CR0_FRF_SPI         (0 << SSI_CR0_FRF_SHIFT)     /* Freescale SPI format */
-#define   SSI_CR0_FRF_SSFF        (1 << SSI_CR0_FRF_SHIFT)     /* TI synchronous serial fram format */
-#define   SSI_CR0_FRF_UWIRE       (2 << SSI_CR0_FRF_SHIFT)     /* MICROWIRE frame format */
-#define SSI_CR0_SPO               (1 << 6)  /* Bit 6:  SSI Serial Clock Polarity */
-#define SSI_CR0_SPH               (1 << 7)  /* Bit 7:  SSI Serial Clock Phase */
-#define SSI_CR0_SCR_SHIFT         8         /* Bits 15-8: SSI Serial Clock Rate */
-#define SSI_CR0_SCR_MASK          (0xff << SSI_CR0_SCR_SHIFT)
-
-/* SSI Control 1 (SSICR1), offset 0x004 */
-
-#define SSI_CR1_LBM               (1 << 0)  /* Bit 0:  SSI Loopback Mode */
-#define SSI_CR1_SSE               (1 << 1)  /* Bit 1:  SSI Synchronous Serial Port Enable */
-#define SSI_CR1_MS                (1 << 2)  /* Bit 2:  SSI Master/Slave Select slave */
-#define SSI_CR1_SOD               (1 << 3)  /* Bit 3:  SSI Slave Mode Output Disable */
-
-/* SSI Data (SSIDR), offset 0x008 */
-
-#define SSI_DR_MASK               0xffff    /* Bits 15-0: SSI data */
-
-/* SSI Status (SSISR), offset 0x00c */
-
-#define SSI_SR_TFE                (1 << 0)  /* Bit 0:  SSI Transmit FIFO Empty */
-#define SSI_SR_TNF                (1 << 1)  /* Bit 1:  SSI Transmit FIFO Not Full */
-#define SSI_SR_RNE                (1 << 2)  /* Bit 2:  SSI Receive FIFO Not Empty */
-#define SSI_SR_RFF                (1 << 3)  /* Bit 3:  SSI Receive FIFO Full */
-#define SSI_SR_BSY                (1 << 4)  /* Bit 4:  SSI Busy Bit */
-
-/* SSI Clock Prescale (SSICPSR), offset 0x010 */
-
-#define SSI_CPSR_DIV_MASK         0xff      /* Bits 7-0: SSI Clock Prescale Divisor */
-
-/* SSI Interrupt Mask (SSIIM), offset 0x014 */
-
-#define SSI_IM_ROR                (1 << 0)  /* Bit 0:  SSI Receive Overrun Interrupt Mask */
-#define SSI_IM_RT                 (1 << 1)  /* Bit 1:  SSI Receive Time-Out Interrupt Mask */
-#define SSI_IM_RX                 (1 << 2)  /* Bit 2:  SSI Receive FIFO Interrupt Mask */
-#define SSI_IM_TX                 (1 << 3)  /* Bit 3:  SSI Transmit FIFO Interrupt Mask */
-
-/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
-
-#define SSI_RIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Raw Interrupt Status */
-#define SSI_RIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Raw Interrupt Status */
-#define SSI_RIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Raw Interrupt Status */
-#define SSI_RIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Raw Interrupt Status */
-
-/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
-
-#define SSI_MIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Masked Interrupt Status */
-#define SSI_MIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Masked Interrupt Status */
-#define SSI_MIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Masked Interrupt Status */
-#define SSI_MIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Masked Interrupt Status */
-
-/* SSI Interrupt Clear (SSIICR), offset 0x020 */
-
-#define SSI_ICR_ROR               (1 << 0)  /* Bit 0: SSI Receive Overrun Interrupt Clear */
-#define SSI_ICR_RT                (1 << 1)  /* Bit 1: SSI Receive Time-Out Interrupt Clear */
-
-/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
-
-#define SSI_PERIPHID_MASK         0xff      /* Bits 7-0: SSI Peripheral ID n */
-
-/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
-
-#define SSI_PCELLID_MASK          0xff      /* Bits 7-0: SSI Prime cell ID */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* LM3S_NSSI > 0 */
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_SSI_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
deleted file mode 100644
index c59b921c4..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_syscontrol.h
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_SYSCONTROL_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_SYSCONTROL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* System Control Register Offsets **************************************************/
-
-#define LM3S_SYSCON_DID0_OFFSET       0x000 /* Device Identification 0 */
-#define LM3S_SYSCON_DID1_OFFSET       0x004 /* Device Identification 1 */
-#define LM3S_SYSCON_DC0_OFFSET        0x008 /* Device Capabilities 0 */
-#define LM3S_SYSCON_DC1_OFFSET        0x010 /* Device Capabilities 1 */
-#define LM3S_SYSCON_DC2_OFFSET        0x014 /* Device Capabilities 2 */
-#define LM3S_SYSCON_DC3_OFFSET        0x018 /* Device Capabilities 3 */
-#define LM3S_SYSCON_DC4_OFFSET        0x01c /* Device Capabilities 4 */
-#define LM3S_SYSCON_PBORCTL_OFFSET    0x030 /* Brown-Out Reset Control */
-#define LM3S_SYSCON_LDOPCTL_OFFSET    0x034 /* LDO Power Control */
-#define LM3S_SYSCON_SRCR0_OFFSET      0x040 /* Software Reset Control 0 */
-#define LM3S_SYSCON_SRCR1_OFFSET      0x044 /* Software Reset Control 1 */
-#define LM3S_SYSCON_SRCR2_OFFSET      0x048 /* Software Reset Control 2*/
-#define LM3S_SYSCON_RIS_OFFSET        0x050 /* Raw Interrupt Status */
-#define LM3S_SYSCON_IMC_OFFSET        0x054 /* Interrupt Mask Control */
-#define LM3S_SYSCON_MISC_OFFSET       0x058 /* Masked Interrupt Status and Clear */
-#define LM3S_SYSCON_RESC_OFFSET       0x05c /* Reset Cause */
-#define LM3S_SYSCON_RCC_OFFSET        0x060 /* Run-Mode Clock Configuration */
-#define LM3S_SYSCON_PLLCFG_OFFSET     0x064 /* XTAL to PLL Translation */
-#define LM3S_SYSCON_RCC2_OFFSET       0x070 /* Run-Mode Clock Configuration 2 */
-#define LM3S_SYSCON_RCGC0_OFFSET      0x100 /* Run Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_RCGC1_OFFSET      0x104 /* Run Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_RCGC2_OFFSET      0x108 /* Run Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_SCGC0_OFFSET      0x110 /* Sleep Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_SCGC1_OFFSET      0x114 /* Sleep Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_SCGC2_OFFSET      0x118 /* Sleep Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_DCGC0_OFFSET      0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_DCGC1_OFFSET      0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_DCGC2_OFFSET      0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
-
-/* System Control Register Addresses ************************************************/
-
-#define LM3S_SYSCON_DID0              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
-#define LM3S_SYSCON_DID1              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
-#define LM3S_SYSCON_DC0               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
-#define LM3S_SYSCON_DC1               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
-#define LM3S_SYSCON_DC2               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
-#define LM3S_SYSCON_DC3               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
-#define LM3S_SYSCON_DC4               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
-#define LM3S_SYSCON_PBORCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
-#define LM3S_SYSCON_LDOPCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
-#define LM3S_SYSCON_SRCR0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
-#define LM3S_SYSCON_SRCR1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
-#define LM3S_SYSCON_SRCR2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
-#define LM3S_SYSCON_RIS               (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
-#define LM3S_SYSCON_IMC               (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
-#define LM3S_SYSCON_MISC              (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
-#define LM3S_SYSCON_RESC              (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
-#define LM3S_SYSCON_RCC               (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
-#define LM3S_SYSCON_PLLCFG            (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
-#define LM3S_SYSCON_RCC2              (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
-#define LM3S_SYSCON_RCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
-#define LM3S_SYSCON_RCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
-#define LM3S_SYSCON_RCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
-#define LM3S_SYSCON_SCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
-#define LM3S_SYSCON_SCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
-#define LM3S_SYSCON_SCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
-#define LM3S_SYSCON_DCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
-#define LM3S_SYSCON_DCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
-#define LM3S_SYSCON_DCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
-#define LM3S_SYSCON_DSLPCLKCFG        (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
-
-/* System Control Register Bit Definitions ******************************************/
-
-/* Device Identification 0 (DID0), offset 0x000 */
-
-#define SYSCON_DID0_MINOR_SHIFT       0         /* Bits 7-0: Minor Revision of the device */
-#define SYSCON_DID0_MINOR_MASK        (0xff << SYSCON_DID0_MINOR_SHIFT)
-#define SYSCON_DID0_MAJOR_SHIFT       8         /* Bits 15-8: Major Revision of the device */
-#define SYSCON_DID0_MAJOR_MASK        (0xff << SYSCON_DID0_MAJOR_SHIFT)
-#define SYSCON_DID0_CLASS_SHIFT       16        /* Bits 23-16: Device Class */
-#define SYSCON_DID0_CLASS_MASK        (0xff << SYSCON_DID0_CLASS_SHIFT)
-#define SYSCON_DID0_VER_SHIFT         28        /* Bits 30-28: DID0 Version */
-#define SYSCON_DID0_VER_MASK          (7 << SYSCON_DID0_VER_SHIFT)
-
-/* Device Identification 1 (DID1), offset 0x004 */
-
-#define SYSCON_DID1_QUAL_SHIFT        0         /* Bits 1-0: Qualification Status */
-#define SYSCON_DID1_QUAL_MASK         (0x03 << SYSCON_DID1_QUAL_SHIFT)
-#define SYSCON_DID1_ROHS              (1 << 2)  /* Bit 2: RoHS-Compliance */
-#define SYSCON_DID1_PKG_SHIFT         3 /* Bits 4-3: Package Type */
-#define SYSCON_DID1_PKG_MASK          (0x03 << SYSCON_DID1_PKG_SHIFT)
-#define SYSCON_DID1_TEMP_SHIFT        5         /* Bits 7-5: Temperature Range */
-#define SYSCON_DID1_TEMP_MASK         (0x07 << SYSCON_DID1_TEMP_SHIFT)
-#define SYSCON_DID1_PINCOUNT_SHIFT    13        /* Bits 15-13: Package Pin Count */
-#define SYSCON_DID1_PINCOUNT_MASK     (0x07 << SYSCON_DID1_PINCOUNT_SHIFT)
-#define SYSCON_DID1_PARTNO_SHIFT      16        /* Bits 23-16: Part Number */
-#define SYSCON_DID1_PARTNO_MASK       (0xff << SYSCON_DID1_PARTNO_SHIFT)
-#define SYSCON_DID1_FAM_SHIFT         24        /* Bits 27-24: Family */
-#define SYSCON_DID1_FAM_MASK          (0x0f << SYSCON_DID1_FAM_SHIFT)
-#define SYSCON_DID1_VER_SHIFT         28        /* Bits 31-28:  DID1 Version */
-#define SYSCON_DID1_VER_MASK          (0x0f << SYSCON_DID1_VER_SHIFT)
-
-/* Device Capabilities 0 (DC0), offset 0x008 */
-
-#define SYSCON_DC0_FLASHSZ_SHIFT      0         /* Bits 15-0: FLASH Size */
-#define SYSCON_DC0_FLASHSZ_MASK       (0xffff << SYSCON_DC0_FLASHSZ_SHIFT)
-#define SYSCON_DC0_SRAMSZ_SHIFT       16        /* Bits 31-16: SRAM Size */
-#define SYSCON_DC0_SRAMSZ_MASK        (0xffff << SYSCON_DC0_SRAMSZ_SHIFT)
-
-/* Device Capabilities 1 (DC1), offset 0x010 */
-
-#define SYSCON_DC1_JTAG               (1 << 0)  /* Bit 0: JTAG Present */
-#define SYSCON_DC1_SWD                (1 << 1)  /* Bit 1: SWD Present */
-#define SYSCON_DC1_SWO                (1 << 2)  /* Bit 2: SWO Trace Port Present */
-#define SYSCON_DC1_WDT                (1 << 3)  /* Bit 3: Watchdog Timer Present */
-#define SYSCON_DC1_PLL                (1 << 4)  /* Bit 4: PLL Present */
-#define SYSCON_DC1_TEMPSNS            (1 << 5)  /* Bit 5: Temp Sensor Present */
-#define SYSCON_DC1_HIB                (1 << 6)  /* Bit 6: Hibernation Module Present */
-#define SYSCON_DC1_MPU                (1 << 7)  /* Bit 7: MPU Present */
-#define SYSCON_DC1_MAXADCSPD_SHIFT    8         /* Bits 9-8: Max ADC Speed */
-#define SYSCON_DC1_MAXADCSPD_MASK     (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT)
-#define SYSCON_DC1_ADC                (1 << 16) /* Bit 16: ADC Module Present */
-#define SYSCON_DC1_MINSYSDIV_SHIFT    12        /* Bits 15-12: System Clock Divider Minimum */
-#define SYSCON_DC1_MINSYSDIV_MASK     (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT)
-
-/* Device Capabilities 2 (DC2), offset 0x014 */
-
-#define SYSCON_DC2_UART0              (1 << 0)  /* Bit 0: UART0 Present */
-#define SYSCON_DC2_UART1              (1 << 1)  /* Bit 1: UART1 Present */
-#define SYSCON_DC2_SSI0               (1 << 4)  /* Bit 4: SSI0 Present */
-#define SYSCON_DC2_SSI1               (1 << 5)  /* Bit 5: SSI1 Present */
-#define SYSCON_DC2_I2C0               (1 << 12) /* Bit 12: I2C Module 0 Present */
-#define SYSCON_DC2_I2C1               (1 << 14) /* Bit 14: I2C Module 1 Present */
-#define SYSCON_DC2_TIMER0             (1 << 16) /* Bit 16: Timer 0 Present */
-#define SYSCON_DC2_TIMER1             (1 << 17) /* Bit 17: Timer 1 Present */
-#define SYSCON_DC2_TIMER2             (1 << 18) /* Bit 18: Timer 2 Present */
-#define SYSCON_DC2_TIMER3             (1 << 19) /* Bit 19: Timer 3 Present */
-#define SYSCON_DC2_COMP0              (1 << 24) /* Bit 24: Analog Comparator 0 Present */
-#define SYSCON_DC2_COMP1              (1 << 25) /* Bit 25: Analog Comparator 1 Present */
-
-/* Device Capabilities 3 (DC3), offset 0x018 */
-
-#define SYSCON_DC3_C0MINUS            (1 << 6)  /* Bit 6: C0- Pin Present */
-#define SYSCON_DC3_C0PLUS             (1 << 7)  /* Bit 7: C0+ Pin Present */
-#define SYSCON_DC3_C0O                (1 << 8)  /* Bit 8: C0o Pin Present */
-#define SYSCON_DC3_C1MINUS            (1 << 9)  /* Bit 9: C1- Pin Present */
-#define SYSCON_DC3_C1PLUS             (1 << 10) /* Bit 10: C1+ Pin Present */
-#define SYSCON_DC3_ADC0               (1 << 16) /* Bit 16: ADC0 Pin Present */
-#define SYSCON_DC3_ADC1               (1 << 17) /* Bit 17: ADC1 Pin Present */
-#define SYSCON_DC3_ADC2               (1 << 18) /* Bit 18: ADC2 Pin Present */
-#define SYSCON_DC3_ADC3               (1 << 19) /* Bit 19: ADC3 Pin Present */
-#define SYSCON_DC3_ADC4               (1 << 20) /* Bit 20: ADC4 Pin Present */
-#define SYSCON_DC3_ADC5               (1 << 21) /* Bit 21: ADC5 Pin Present */
-#define SYSCON_DC3_ADC6               (1 << 22) /* Bit 22: ADC6 Pin Present */
-#define SYSCON_DC3_ADC7               (1 << 23) /* Bit 23: ADC7 Pin Present */
-#define SYSCON_DC3_CCP0               (1 << 24) /* Bit 24: CCP0 Pin Present */
-#define SYSCON_DC3_CCP1               (1 << 25) /* Bit 25: CCP1 Pin Present */
-#define SYSCON_DC3_CCP2               (1 << 26) /* Bit 26: CCP2 Pin Present */
-#define SYSCON_DC3_CCP3               (1 << 27) /* Bit 27: CCP3 Pin Present */
-#define SYSCON_DC3_CCP4               (1 << 28) /* Bit 28: CCP4 Pin Present */
-#define SYSCON_DC3_CCP5               (1 << 29) /* Bit 29: CCP5 Pin Present */
-#define SYSCON_DC3_32KHZ              (1 << 31) /* Bit 31: 32KHz Input Clock Available */
-
-/* Device Capabilities 4 (DC4), offset 0x01c */
-
-#define SYSCON_DC4_GPIO(n)            (1 << (n))
-#define SYSCON_DC4_GPIOA              (1 << 0)  /* Bit 0: GPIO Port A Present */
-#define SYSCON_DC4_GPIOB              (1 << 1)  /* Bit 1: GPIO Port B Present */
-#define SYSCON_DC4_GPIOC              (1 << 2)  /* Bit 2: GPIO Port C Present */
-#define SYSCON_DC4_GPIOD              (1 << 3)  /* Bit 3: GPIO Port D Present */
-#define SYSCON_DC4_GPIOE              (1 << 4)  /* Bit 4: GPIO Port E Present */
-#define SYSCON_DC4_GPIOF              (1 << 5)  /* Bit 5: GPIO Port F Present */
-#define SYSCON_DC4_GPIOG              (1 << 6)  /* Bit 6: GPIO Port G Present */
-#define SYSCON_DC4_GPIOH              (1 << 7)  /* Bit 7: GPIO Port H Present */
-#define SYSCON_DC4_EMAC0              (1 << 28) /* Bit 28: Ethernet MAC0 Present */
-#define SYSCON_DC4_EPHY0              (1 << 30) /* Bit 30: Ethernet PHY0 Present */
-
-/* Brown-Out Reset Control (PBORCTL), offset 0x030 */
-
-#define SYSCON_PBORCTL_BORIOR         (1 << 1)  /* Bit 1: BOR Interrupt or Reset */
-
-/* LDO Power Control (LDOPCTL), offset 0x034 */
-
-#define SYSCON_LDOPCTL_VADJ_SHIFT     0         /* Bits 5-0: LDO Output Voltage */
-#define SYSCON_LDOPCTL_VADJ_MASK      (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT)
-#  define SYSCON_LPDOPCTL_2500MV      (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/
-#  define SYSCON_LPDOPCTL_2450MV      (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */
-#  define SYSCON_LPDOPCTL_2400MV      (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */
-#  define SYSCON_LPDOPCTL_2350MV      (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */
-#  define SYSCON_LPDOPCTL_2300MV      (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */
-#  define SYSCON_LPDOPCTL_2250MV      (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */
-#  define SYSCON_LPDOPCTL_2750MV      (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */
-#  define SYSCON_LPDOPCTL_2700MV      (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */
-#  define SYSCON_LPDOPCTL_2650MV      (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */
-#  define SYSCON_LPDOPCTL_2600MV      (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */
-#  define SYSCON_LPDOPCTL_2550MV      (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */
-
-/* Software Reset Control 0 (SRCR0), offset 0x040 */
-
-#define SYSCON_SRCR0_WDT              (1 << 3)  /* Bit 3: WDT Reset Control */
-#define SYSCON_SRCR0_HIB              (1 << 6)  /* Bit 6: HIB Reset Control */
-#define SYSCON_SRCR0_ADC              (1 << 16) /* Bit 16: ADC0 Reset Control */
-
-/* Software Reset Control 1 (SRCR1), offset 0x044 */
-
-#define SYSCON_SRCR1_UART0            (1 << 0)  /* Bit 0: UART0 Reset Control */
-#define SYSCON_SRCR1_UART1            (1 << 1)  /* Bit 1: UART1 Reset Control */
-#define SYSCON_SRCR1_SSI0             (1 << 4)  /* Bit 4: SSI0 Reset Control1 */
-#define SYSCON_SRCR1_SSI1             (1 << 5)  /* Bit 5: SSI1 Reset Control */
-#define SYSCON_SRCR1_I2C0             (1 << 12) /* Bit 12: I2C0 Reset Control */
-#define SYSCON_SRCR1_I2C1             (1 << 14) /* Bit 14: I2C1 Reset Control */
-#define SYSCON_SRCR1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Reset Control */
-#define SYSCON_SRCR1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Reset Control */
-#define SYSCON_SRCR1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Reset Control */
-#define SYSCON_SRCR1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Reset Control */
-#define SYSCON_SRCR1_COMP0            (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */
-#define SYSCON_SRCR1_COMP1            (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */
-
-/* Software Reset Control 2 (SRCR2), offset 0x048 */
-
-#define SYSCON_SRCR2_GPIO(n)          (1 << (n))
-#define SYSCON_SRCR2_GPIOA            (1 << 0)  /* Bit 0: Port A Reset Control */
-#define SYSCON_SRCR2_GPIOB            (1 << 1)  /* Bit 1: Port B Reset Control */
-#define SYSCON_SRCR2_GPIOC            (1 << 2)  /* Bit 2: Port C Reset Control */
-#define SYSCON_SRCR2_GPIOD            (1 << 3)  /* Bit 3: Port D Reset Control */
-#define SYSCON_SRCR2_GPIOE            (1 << 4)  /* Bit 4: Port E Reset Control */
-#define SYSCON_SRCR2_GPIOF            (1 << 5)  /* Bit 5: Port F Reset Control */
-#define SYSCON_SRCR2_GPIOG            (1 << 6)  /* Bit 6: Port G Reset Control */
-#define SYSCON_SRCR2_GPIOH            (1 << 7)  /* Bit 7: Port H Reset Control */
-#define SYSCON_SRCR2_EMAC0            (1 << 28) /* Bit 28: MAC0 Reset Control */
-#define SYSCON_SRCR2_EPHY0            (1 << 30) /* Bit 30: PHY0 Reset Control */
-
-/* Raw Interrupt Status (RIS), offset 0x050 */
-
-#define SYSCON_RIS_BORRIS             (1 << 1)  /* Bit 1: Brown-Out Reset Raw Interrupt Status */
-#define SYSCON_RIS_PLLLRIS            (1 << 6)  /* Bit 6: PLL Lock Raw Interrupt Status */
-
-/* Interrupt Mask Control (IMC), offset 0x054 */
-
-#define SYSCON_IMC_BORIM              (1 << 1)  /* Bit 1: Brown-Out Reset Interrupt Mask */
-#define SYSCON_IMC_PLLLIM             (1 << 6)  /* Bit 6: PLL Lock Interrupt Mask */
-
-/* Masked Interrupt Status and Clear (MISC), offset 0x058 */
-
-#define SYSCON_MISC_BORMIS            (1 << 1)  /* Bit 1: BOR Masked Interrupt Status */
-#define SYSCON_MISC_PLLLMIS           (1 << 6)  /* Bit 6: PLL Lock Masked Interrupt Status */
-
-/* Reset Cause (RESC), offset 0x05C */
-
-#define SYSCON_RESC_EXT               (1 << 0)  /* Bit 0: External Reset */
-#define SYSCON_RESC_POR               (1 << 1)  /* Bit 1: Power-On Reset */
-#define SYSCON_RESC_BOR               (1 << 2)  /* Bit 2: Brown-Out Reset */
-#define SYSCON_RESC_WDT               (1 << 3)  /* Bit 3: Watchdog Timer Reset */
-#define SYSCON_RESC_SW                (1 << 4)  /* Bit 4: Software Reset */
-
-/* Run-Mode Clock Configuration (RCC), offset 0x060 */
-
-#define SYSCON_RCC_MOSCDIS            (1 << 0)  /* Bit 0: Main Oscillator Disable */
-#define SYSCON_RCC_IOSCDIS            (1 << 1)  /* Bit 1: Internal Oscillator Disable */
-#define SYSCON_RCC_OSCSRC_SHIFT       4         /* Bits 5-4: Oscillator Source */
-#define SYSCON_RCC_OSCSRC_MASK        (0x03 << SYSCON_RCC_OSCSRC_SHIFT)
-#  define SYSCON_RCC_OSCSRC_MOSC      (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */
-#  define SYSCON_RCC_OSCSRC_IOSC      (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */
-#  define SYSCON_RCC_OSCSRC_IOSC4     (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */
-#  define SYSCON_RCC_OSCSRC_30KHZ     (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */
-#define SYSCON_RCC_XTAL_SHIFT         6         /* Bits 10-6: Crystal Value */
-#define SYSCON_RCC_XTAL_MASK          (0x1f << SYSCON_RCC_XTAL_SHIFT)
-#  define SYSCON_RCC_XTAL1000KHZ      ( 0 << SYSCON_RCC_XTAL_SHIFT)  /* 1.0000MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL1843KHZ      ( 1 << SYSCON_RCC_XTAL_SHIFT)  /* 1.8432MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL2000KHZ      ( 2 << SYSCON_RCC_XTAL_SHIFT)  /* 2.0000MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL2580KHZ      ( 3 << SYSCON_RCC_XTAL_SHIFT)  /* 2.4576MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL3580KHZ      ( 4 << SYSCON_RCC_XTAL_SHIFT)  /* 3.5795MHz */
-#  define SYSCON_RCC_XTAL3686KHZ      ( 5 << SYSCON_RCC_XTAL_SHIFT)  /* 3.6864MHz */
-#  define SYSCON_RCC_XTAL4000KHZ      ( 6 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0000MHz */
-#  define SYSCON_RCC_XTAL4096KHZ      ( 7 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0960MHz */
-#  define SYSCON_RCC_XTAL4915KHZ      ( 8 << SYSCON_RCC_XTAL_SHIFT)  /* 4.9152MHz */
-#  define SYSCON_RCC_XTAL5000KHZ      ( 9 << SYSCON_RCC_XTAL_SHIFT)  /* 5.0000MHz */
-#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT)  /* 5.1200MHz */
-#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT)  /* 6.0000MHz (reset value) */
-#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT)  /* 6.1440MHz */
-#  define SYSCON_RCC_XTAL7373KHZ      (13 << SYSCON_RCC_XTAL_SHIFT)  /* 7.3728MHz */
-#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT)  /* 8.0000MHz */
-#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT)  /* 8.1920MHz */
-#ifdef CONFIG_ARCH_CHIP_LM3S9B96
-#  define SYSCON_RCC_XTAL10000KHZ     (16 << SYSCON_RCC_XTAL_SHIFT)  /* 10.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL12000KHZ     (17 << SYSCON_RCC_XTAL_SHIFT)  /* 12.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL12888KHZ     (18 << SYSCON_RCC_XTAL_SHIFT)  /* 12.288 MHz */
-#  define SYSCON_RCC_XTAL13560KHZ     (19 << SYSCON_RCC_XTAL_SHIFT)  /* 13.56 MHz */
-#  define SYSCON_RCC_XTAL14318KHZ     (20 << SYSCON_RCC_XTAL_SHIFT)  /* 14.31818 MHz */
-#  define SYSCON_RCC_XTAL16000KHZ     (21 << SYSCON_RCC_XTAL_SHIFT)  /* 16.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL16384KHZ     (22 << SYSCON_RCC_XTAL_SHIFT)  /* 16.384 MHz */
-#endif
-#define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
-#define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
-#define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */
-#define SYSCON_RCC_SYSDIV_SHIFT       23        /* Bits 26-23: System Clock Divisor */
-#define SYSCON_RCC_SYSDIV_MASK        (0x0f << SYSCON_RCC_SYSDIV_SHIFT)
-#  define SYSCON_RCC_SYSDIV(n)        (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT)
-#define SYSCON_RCC_ACG                (1 << 27) /* Bit 27: Auto Clock Gating */
-
-/* XTAL to PLL Translation (PLLCFG), offset 0x064 */
-
-#define SYSCON_PLLCFG_F_SHIFT         5         /* Bits 13-5: PLL F Value */
-#define SYSCON_PLLCFG_F_MASK          (0x1ff << SYSCON_PLLCFG_F_SHIFT)
-#define SYSCON_PLLCFG_R_SHIFT         0         /* Bits 4-0: PLL R Value  */
-#define SYSCON_PLLCFG_R_MASK          (0x1f << SYSCON_PLLCFG_R_SHIFT)
-
-/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */
-
-#define SYSCON_RCC2_OSCSRC2_SHIFT     4         /* Bits 6-4: Oscillator Source */
-#define SYSCON_RCC2_OSCSRC2_MASK      (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT)
-#  define SYSCON_RCC2_OSCSRC2_MOSC    (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */
-#  define SYSCON_RCC2_OSCSRC2_IOSC    (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */
-#  define SYSCON_RCC2_OSCSRC2_IOSC4   (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */
-#  define SYSCON_RCC2_OSCSRC2_30KHZ   (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */
-#  define SYSCON_RCC2_OSCSRC2_32KHZ   (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */
-#define SYSCON_RCC2_BYPASS2           (1 << 11) /* Bit 11: Bypass PLL */
-#define SYSCON_RCC2_PWRDN2            (1 << 13) /* Bit 13: Power-Down PLL */
-#define SYSCON_RCC2_SYSDIV2_SHIFT     23        /* Bits 28-23: System Clock Divisor */
-#define SYSCON_RCC2_SYSDIV2_MASK      (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT)
-#  define SYSCON_RCC2_SYSDIV(n)       ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT)
-#define SYSCON_RCC2_USERCC2           (1 << 31) /* Bit 31: Use RCC2 When set */
-
-/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */
-
-#define SYSCON_RCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_RCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_RCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_RCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_RCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */
-
-#define SYSCON_RCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_RCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_RCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_RCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_RCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_RCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_RCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_RCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */
-
-#define SYSCON_RCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_RCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_RCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_RCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_RCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_RCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_RCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_RCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_RCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_RCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_RCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */
-
-#define SYSCON_SCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_SCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_SCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_SCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_SCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */
-
-#define SYSCON_SCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_SCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_SCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_SCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_SCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_SCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_SCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_SCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */
-
-#define SYSCON_SCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_SCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_SCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_SCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_SCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_SCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_SCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_SCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_SCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_SCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_SCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */
-
-#define SYSCON_DCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_DCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_DCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_DCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_DCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */
-
-#define SYSCON_DCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_DCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_DCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_DCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_DCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_DCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_DCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_DCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */
-
-#define SYSCON_DCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_DCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_DCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_DCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_DCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_DCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_DCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_DCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_DCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_DCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_DCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */
-
-#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */
-#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK  (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT)
-#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT   4 /* Bits 6-4: Clock Source */
-#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK    (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timer.h b/nuttx/arch/arm/src/lm3s/lm3s_timer.h
deleted file mode 100644
index 7c4166293..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_timer.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_timer.h
- *
- *   Copyright (C) 2012 Max Nekludov. All rights reserved.
- *   Author: Max Nekludov <macscomp@gmail.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Timer register offsets ***********************************************************/
-
-#define TIMER_GPTMCFG_OFFSET             0x000
-#define TIMER_GPTMTAMR_OFFSET            0x004
-#define TIMER_GPTMCTL_OFFSET             0x00C
-#define TIMER_GPTMIMR_OFFSET             0x018
-#define TIMER_GPTMRIS_OFFSET             0x01C
-#define TIMER_GPTMICR_OFFSET             0x024
-#define TIMER_GPTMTAILR_OFFSET           0x028
-#define TIMER_GPTMTAR_OFFSET             0x048
-
-/* SSI register addresses ***********************************************************/
-
-#define LM3S_TIMER_BASE(n)               (LM3S_TIMER0_BASE + (n)*0x01000)
-
-#define LM3S_TIMER_GPTMCFG(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
-#define LM3S_TIMER_GPTMTAMR(n)           (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
-#define LM3S_TIMER_GPTMCTL(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
-#define LM3S_TIMER_GPTMIMR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
-#define LM3S_TIMER_GPTMRIS(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
-#define LM3S_TIMER_GPTMICR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
-#define LM3S_TIMER_GPTMTAILR(n)          (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
-#define LM3S_TIMER_GPTMTAR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
-
-/* SSI register bit defitiions ******************************************************/
-
-/* GPTM Configuration (GPTMCFG), offset 0x000 */
-
-#define TIMER_GPTMCFG_CFG_SHIFT          0    /* Bits 2-0: GPTM Configuration */
-#define TIMER_GPTM_CFG_MASK              (0x07 << TIMER_GPTMCFG_CFG_SHIFT)
-#define   TIMER_GPTMCFG_CFG_32           (0 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit timer configuration */
-#define   TIMER_GPTMCFG_CFG_RTC          (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit real-time clock (RTC) counter configuration */
-#define   TIMER_GPTMCFG_CFG_16           (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 16-bit timer configuration */
-
-/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */
-
-#define TIMER_GPTMTAMR_TAMR_SHIFT        0    /* Bits 1-0: GPTM Timer A Mode */
-#define TIMER_GPTMTAMR_TAMR_MASK         (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT)
-#define   TIMER_GPTMTAMR_TAMR_ONESHOT    (1 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* One-Shot Timer mode */
-#define   TIMER_GPTMTAMR_TAMR_PERIODIC   (2 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Periodic Timer mode */
-#define   TIMER_GPTMTAMR_TAMR_CAPTURE    (3 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Capture mode */
-#define TIMER_GPTMTAMR_TACMR_SHIFT       2    /* Bits 2:   GPTM Timer A Capture Mode */
-#define TIMER_GPTMTAMR_TACMR_MASK        (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT)
-#define   TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Count mode */
-#define   TIMER_GPTMTAMR_TACMR_EDGETIME  (1 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Time mode */
-#define TIMER_GPTMTAMR_TAAMS_SHIFT       3    /* Bits 3:   GPTM Timer A Alternate Mode Select */
-#define TIMER_GPTMTAMR_TAAMS_MASK        (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT)
-#define   TIMER_GPTMTAMR_TAAMS_CAPTURE   (0 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* Capture mode is enabled */
-#define   TIMER_GPTMTAMR_TAAMS_PWM       (1 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* PWM mode is enabled */
-#define TIMER_GPTMTAMR_TACDIR_SHIFT      4    /* Bits 4:   GPTM Timer A Count Direction */
-#define TIMER_GPTMTAMR_TACDIR_MASK       (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT)
-#define   TIMER_GPTMTAMR_TACDIR_DOWN     (0 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* The timer counts down */
-#define   TIMER_GPTMTAMR_TACDIR_UP       (1 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* When in one-shot or periodic mode, the timer counts up */
-#define TIMER_GPTMTAMR_TAMIE_SHIFT       5    /* Bits 5:   GPTM Timer A Match Interrupt Enable */
-#define TIMER_GPTMTAMR_TAMIE_MASK        (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT)
-
-/* GPTM Control (GPTMCTL), offset 0x00C */
-
-#define TIMER_GPTMCTL_TAEN_SHIFT         0    /* Bits 0:   GPTM Timer A Enable */
-#define TIMER_GPTMCTL_TAEN_MASK          (0x01 << TIMER_GPTMCTL_TAEN_SHIFT)
-#define TIMER_GPTMCTL_TASTALL_SHIFT      1    /* Bits 1:   GPTM Timer A Stall Enable */
-#define TIMER_GPTMCTL_TASTALL_MASK       (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT)
-
-/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */
-
-#define TIMER_GPTMIMR_TATOIM_SHIFT       0    /* Bits 0:   GPTM Timer A Time-Out Interrupt Mask */
-#define TIMER_GPTMIMR_TATOIM_MASK        (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT)
-
-/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */
-
-#define TIMER_GPTMRIS_TATORIS_SHIFT      0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt */
-#define TIMER_GPTMRIS_TATORIS_MASK       (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT)
-
-/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */
-
-#define TIMER_GPTMICR_TATOCINT_SHIFT     0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt Clear*/
-#define TIMER_GPTMICR_TATOCINT_MASK      (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_uart.h b/nuttx/arch/arm/src/lm3s/lm3s_uart.h
deleted file mode 100644
index 91bfb2266..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_uart.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_uart.h
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_UART_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_UART_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* UART register offsets ************************************************************/
-
-#define LM3S_UART_DR_OFFSET        0x000 /* UART Data */
-#define LM3S_UART_RSR_OFFSET       0x004 /* UART Receive Status */
-#define LM3S_UART_ECR_OFFSET       0x004 /* UART Error Clear */
-#define LM3S_UART_FR_OFFSET        0x018 /* UART Flag */
-#define LM3S_UART_ILPR_OFFSET      0x020 /* UART IrDA Low-Power Register */
-#define LM3S_UART_IBRD_OFFSET      0x024 /* UART Integer Baud-Rate Divisor*/
-#define LM3S_UART_FBRD_OFFSET      0x028 /* UART Fractional Baud-Rate Divisor */
-#define LM3S_UART_LCRH_OFFSET      0x02c /* UART Line Control */
-#define LM3S_UART_CTL_OFFSET       0x030 /* UART Control */
-#define LM3S_UART_IFLS_OFFSET      0x034 /* UART Interrupt FIFO Level Select */
-#define LM3S_UART_IM_OFFSET        0x038 /* UART Interrupt Mask */
-#define LM3S_UART_RIS_OFFSET       0x03c /* UART Raw Interrupt Status */
-#define LM3S_UART_MIS_OFFSET       0x040 /* UART Masked Interrupt Status */
-#define LM3S_UART_ICR_OFFSET       0x044 /* UART Interrupt Clear */
-#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
-#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
-#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
-#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
-#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
-#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
-#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
-#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
-#define LM3S_UART_PCELLID0_OFFSET  0xff0 /* UART PrimeCell Identification 0 */
-#define LM3S_UART_PCELLID1_OFFSET  0xff4 /* UART PrimeCell Identification 1 */
-#define LM3S_UART_PCELLID2_OFFSET  0xff8 /* UART PrimeCell Identification 2 */
-#define LM3S_UART_PCELLID3_OFFSET  0xffc /* UART PrimeCell Identification 3 */
-
-/* UART register addresses **********************************************************/
-
-#define LM3S_UART_BASE(n)          (LM3S_UART0_BASE + (n)*0x01000)
-
-#define LM3S_UART_DR(n)            (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
-#define LM3S_UART_RSR(n)           (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART_ECR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART_FR(n)            (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
-#define LM3S_UART_ILPR(n)          (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART_IBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART_FBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART_LCRH(n)          (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART_CTL(n)           (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART_IFLS(n)          (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART_IM(n)            (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
-#define LM3S_UART_RIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART_MIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART_ICR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART_PERIPHID4(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART_PERIPHID5(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART_PERIPHID6(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART_PERIPHID7(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART_PERIPHID0(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART_PERIPHID1(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART_PERIPHID2(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART_PERIPHID3(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART_PCELLID0(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART_PCELLID1(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART_PCELLID2(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART_PCELLID3(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
-
-#define LM3S_UART0_DR              (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
-#define LM3S_UART0_RSR             (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART0_ECR             (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART0_FR              (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
-#define LM3S_UART0_ILPR            (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART0_IBRD            (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART0_FBRD            (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART0_LCRH            (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART0_CTL             (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART0_IFLS            (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART0_IM              (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
-#define LM3S_UART0_RIS             (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART0_MIS             (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART0_ICR             (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART0_PERIPHID4       (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART0_PERIPHID5       (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART0_PERIPHID6       (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART0_PERIPHID7       (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART0_PERIPHID0       (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART0_PERIPHID1       (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART0_PERIPHID2       (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART0_PERIPHID3       (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART0_PCELLID0        (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART0_PCELLID1        (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART0_PCELLID2        (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART0_PCELLID3        (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
-
-#define LM3S_UART1_DR              (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
-#define LM3S_UART1_RSR             (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART1_ECR             (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART1_FR              (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
-#define LM3S_UART1_ILPR            (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART1_IBRD            (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART1_FBRD            (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART1_LCRH            (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART1_CTL             (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART1_IFLS            (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART1_IM              (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
-#define LM3S_UART1_RIS             (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART1_MIS             (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART1_ICR             (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART1_PERIPHID4       (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART1_PERIPHID5       (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART1_PERIPHID6       (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART1_PERIPHID7       (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART1_PERIPHID0       (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART1_PERIPHID1       (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART1_PERIPHID2       (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART1_PERIPHID3       (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART1_PCELLID0        (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART1_PCELLID1        (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART1_PCELLID2        (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART1_PCELLID3        (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
-
-/* UART register bit settings *******************************************************/
-
-/* UART Data (DR), offset 0x000 */
-
-#define UART_DR_DATA_SHIFT         0         /* Bits 7-0: Data Transmitted or Received */
-#define UART_DR_DATA_MASK          (0xff << UART_DR_DATA_SHIFT)
-#define UART_DR_FE                 (1 << 8)  /* Bit 8:  UART Framing Error */
-#define UART_DR_PE                 (1 << 9)  /* Bit 9:  UART Parity Error */
-#define UART_DR_BE                 (1 << 10) /* Bit 10: UART Break Error */
-#define UART_DR_OE                 (1 << 11) /* Bit 11: UART Overrun Error */
-
-/* UART Receive Status (RSR), offset 0x004 */
-
-#define UART_RSR_FE                (1 << 0)  /* Bit 0:  UART Framing Error */
-#define UART_RSR_PE                (1 << 1)  /* Bit 1:  UART Parity Error */
-#define UART_RSR_BE                (1 << 2)  /* Bit 2:  UART Break Error */
-#define UART_RSR_OE                (1 << 3)  /* Bit 3:  UART Overrun Error */
-
-/* UART Error Clear (ECR), offset 0x004 */
-/* Writing any value to this register clears pending error indications */
-
-/* UART Flag (FR), offset 0x018 */
-
-#define UART_FR_BUSY               (1 << 3)  /* Bit 3:  UART Busy */
-#define UART_FR_RXFE               (1 << 4)  /* Bit 4:  UART Receive FIFO Empty */
-#define UART_FR_TXFF               (1 << 5)  /* Bit 5:  UART Transmit FIFO Full */
-#define UART_FR_RXFF               (1 << 6)  /* Bit 6:  UART Receive FIFO Full */
-#define UART_FR_TXFE               (1 << 7)  /* Bit 7:  UART Transmit FIFO Empty */
-
-/* UART IrDA Low-Power Register (ILPR), offset 0x020 */
-
-#define UART_ILPR_DVSR_MASK        (0xff)    /* Bits 7-0: IrDA Low-Power Divisor */
-
-/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */
-
-#define UART_IBRD_DIVINT_MASK      (0xffff)  /* Bits 15-0: Integer Baud-Rate Divisor */
-
-/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */
-
-#define UART_FBRD_DIVFRAC_MASK     (0x3f)    /* Bits 5-0: Fractional Baud-Rate Divisor */
-
-/* Register 7: UART Line Control (LCRH), offset 0x02C */
-
-#define UART_LCRH_BRK              (1 << 0)  /* Bit 0:  UART Send Break */
-#define UART_LCRH_PEN              (1 << 1)  /* Bit 1:  UART Parity Enable */
-#define UART_LCRH_EPS              (1 << 2)  /* Bit 2:  UART Even Parity Select */
-#define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
-#define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
-#define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
-#define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
-#  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
-#  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
-#  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
-#  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
-#define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
-
-/* UART Control (CTL), offset 0x030 */
-
-#define UART_CTL_UARTEN            (1 << 0)  /* Bit 0:  UART Enable */
-#define UART_CTL_SIREN             (1 << 1)  /* Bit 1:  UART SIR Enable */
-#define UART_CTL_SIRLP             (1 << 2)  /* Bit 2:  UART SIR Low Power Mode */
-#define UART_CTL_LBE               (1 << 7)  /* Bit 7:  UART Loop Back Enable */
-#define UART_CTL_TXE               (1 << 8)  /* Bit 8:  UART Transmit Enable */
-#define UART_CTL_RXE               (1 << 9)  /* Bit 9:  UART Receive Enable */
-
-/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */
-
-#define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */
-#define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
-#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
-#define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 5-3: UART Receive Interrupt FIFO Level Select */
-#define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
-#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
-
-/* UART Interrupt Mask (IM), offset 0x038 */
-
-#define UART_IM_RXIM               (1 << 4)  /* Bit 4:  UART Receive Interrupt Mask */
-#define UART_IM_TXIM               (1 << 5)  /* Bit 5:  UART Transmit Interrupt Mask */
-#define UART_IM_RTIM               (1 << 6)  /* Bit 6:  UART Receive Time-Out Interrupt Mask */
-#define UART_IM_FEIM               (1 << 7)  /* Bit 7:  UART Framing Error Interrupt Mask */
-#define UART_IM_PEIM               (1 << 8)  /* Bit 8:  UART Parity Error Interrupt Mask */
-#define UART_IM_BEIM               (1 << 9)  /* Bit 9:  UART Break Error Interrupt Mask */
-#define UART_IM_OEIM               (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */
-
-
-/* UART Raw Interrupt Status (RIS), offset 0x03c */
-
-#define UART_RIS_RXRIS             (1 << 4)  /* Bit 4:  UART Receive Raw Interrupt Status */
-#define UART_RIS_TXRIS             (1 << 5)  /* Bit 5:  UART Transmit Raw Interrupt Status */
-#define UART_RIS_RTRIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Raw Interrupt Status */
-#define UART_RIS_FERIS             (1 << 7)  /* Bit 7:  UART Framing Error Raw Interrupt Status */
-#define UART_RIS_PERIS             (1 << 8)  /* Bit 8:  UART Parity Error Raw Interrupt Status */
-#define UART_RIS_BERIS             (1 << 9)  /* Bit 9:  UART Break Error Raw Interrupt Status */
-#define UART_RIS_OERIS             (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */
-
-/* UART Masked Interrupt Status (MIS), offset 0x040 */
-
-#define UART_MIS_RXMIS             (1 << 4)  /* Bit 4:  UART Receive Masked Interrupt Status */
-#define UART_MIS_TXMIS             (1 << 5)  /* Bit 5:  UART Transmit Masked Interrupt Status */
-#define UART_MIS_RTMIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Masked Interrupt Status */
-#define UART_MIS_FEMIS             (1 << 7)  /* Bit 7:  UART Framing Error Masked Interrupt Status */
-#define UART_MIS_PEMIS             (1 << 8)  /* Bit 8:  UART Parity Error Masked Interrupt Status */
-#define UART_MIS_BEMIS             (1 << 9)  /* Bit 9:  UART Break Error Masked Interrupt Status */
-#define UART_MIS_OEMIS             (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */
-
-/* UART Interrupt Clear (ICR), offset 0x044 */
-
-#define UART_ICR_RXIC             (1 << 4)  /* Bit 4:  Receive Interrupt Clear */
-#define UART_ICR_TXIC             (1 << 5)  /* Bit 5:  Transmit Interrupt Clear */
-#define UART_ICR_RTIC             (1 << 6)  /* Bit 6:  Receive Time-Out Interrupt Clear */
-#define UART_ICR_FEIC             (1 << 7)  /* Bit 7:  Framing Error Interrupt Clear */
-#define UART_ICR_PEIC             (1 << 8)  /* Bit 8:  Parity Error Interrupt Clear */
-#define UART_ICR_BEIC             (1 << 9)  /* Bit 9:  Break Error Interrupt Clear */
-#define UART_ICR_OEIC             (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
- */
-
-/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
-
-#define UART_PERIPHID4_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
-
-/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
-
-#define UART_PERIPHID5_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
-
-/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
-
-#define UART_PERIPHID6_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
-
-/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
-
-#define UART_PERIPHID7_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
-
-/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
-
-#define UART_PERIPHID0_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
-
-/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
-
-#define UART_PERIPHID1_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
-
-/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
-
-#define UART_PERIPHID2_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
-
-/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
-
-#define UART_PERIPHID3_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
-
-/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
-
-#define UART_CELLID0_MASK         (0xff)    /* UART PrimeCell ID Register[7:0] */
-
-/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
-
-#define UART_CELLID1_MASK         (0xff)    /* UART PrimeCell ID Register[15:8] */
-
-/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
-
-#define UART_CELLID02MASK         (0xff)    /* UART PrimeCell ID Register[23:16] */
-
-/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
-
-#define UART_CELLID3_MASK         (0xff)    /* UART PrimeCell ID Register[31:24] */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_UART_H */
diff --git a/nuttx/binfmt/binfmt_exec.c b/nuttx/binfmt/binfmt_exec.c
index 60e8d8efd..d5e274710 100644
--- a/nuttx/binfmt/binfmt_exec.c
+++ b/nuttx/binfmt/binfmt_exec.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * binfmt/binfmt_exec.c
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -75,7 +75,8 @@
  *
  * Description:
  *   This is a convenience function that wraps load_ and exec_module into
- *   one call.
+ *   one call.  The priority of the executed program is set to be the
+ *   same as the priority of the calling thread.
  *
  * Input Parameter:
  *   filename - Fulll path to the binary to be loaded
@@ -94,8 +95,20 @@ int exec(FAR const char *filename, FAR const char **argv,
          FAR const struct symtab_s *exports, int nexports)
 {
   struct binary_s bin;
+  struct sched_param param;
   int ret;
 
+  /* Get the priority of this thread */
+
+  ret = sched_getparam(0, &param);
+  if (ret < 0)
+    {
+      bdbg("ERROR: sched_getparam failed: %d\n", errno);
+      return ERROR;
+    }
+  
+  /* Load the module into memory */
+
   memset(&bin, 0, sizeof(struct binary_s));
   bin.filename = filename;
   bin.exports  = exports;
@@ -108,7 +121,9 @@ int exec(FAR const char *filename, FAR const char **argv,
       return ERROR;
     }
 
-  ret = exec_module(&bin, 50);
+  /* Then start the module at the priority of this thread */
+
+  ret = exec_module(&bin, param.sched_priority);
   if (ret < 0)
     {
       bdbg("ERROR: Failed to execute program '%s'\n", filename);
diff --git a/nuttx/include/nuttx/binfmt/binfmt.h b/nuttx/include/nuttx/binfmt/binfmt.h
index 6df5190d2..480e82c09 100644
--- a/nuttx/include/nuttx/binfmt/binfmt.h
+++ b/nuttx/include/nuttx/binfmt/binfmt.h
@@ -228,7 +228,8 @@ int exec_module(FAR const struct binary_s *bin, int priority);
  *
  * Description:
  *   This is a convenience function that wraps load_ and exec_module into
- *   one call.
+ *   one call.  The priority of the executed program is set to be the
+ *   same as the priority of the calling thread.
  *
  * Input Parameter:
  *   filename - Fulll path to the binary to be loaded
diff --git a/nuttx/include/unistd.h b/nuttx/include/unistd.h
index ddb6880f4..d2ace79fa 100644
--- a/nuttx/include/unistd.h
+++ b/nuttx/include/unistd.h
@@ -160,6 +160,13 @@ EXTERN FAR char *getcwd(FAR char *buf, size_t size);
 EXTERN int     unlink(FAR const char *pathname);
 EXTERN int     rmdir(FAR const char *pathname);
 
+/* Execution of programs from files */
+
+#ifdef CONFIG_LIBC_EXECFUNCS
+EXTERN int     execl(FAR const char *path, ...);
+EXTERN int     execv(FAR const char *path, FAR char *const argv[]);
+#endif
+
 /* Other */
 
 EXTERN int     getopt(int argc, FAR char *const argv[], FAR const char *optstring);
diff --git a/nuttx/libc/Kconfig b/nuttx/libc/Kconfig
index 0ae56ac57..699b3ebb2 100644
--- a/nuttx/libc/Kconfig
+++ b/nuttx/libc/Kconfig
@@ -71,6 +71,54 @@ config EOL_IS_EITHER_CRLF
 
 endchoice
 
+config LIBC_EXECFUNCS
+	bool "Enable exec[l|v] Support"
+	default n
+	depends on !BINFMT_DISABLE
+	---help---
+		Enable support for the exec[l|v] family of functions that can be
+		used to start other programs, terminating the current program.
+		Typical usage is (1) first call vfork() to create a new thread, then
+		(2) call exec[l|v] to replace the new thread with a program from the
+		file system.
+
+		NOTE 1: This two step process start is completely unnecessary in
+		NuttX and is provided only for compatibily with Unix systems.  These
+		functions are essentially just wrapper functions that (1) call the
+		non-standard binfmt function 'exec', and then (2) exit(0).  Since
+		the new thread will be terminated by the exec[l|v] call, it really
+		served no purpose other than to suport Unix compatility.
+
+		NOTE 2: Support for exec[l|v] is conditional because is requires
+		additional support for symbol tables that will not be available in
+		the typical system.
+
+if LIBC_EXECFUNCS
+
+config EXECFUNCS_SYMTAB
+	string "Symbol table used by exec[l|v]"
+	default "g_symtab"
+	---help---
+		The exec[l|v] functions are wrapper functions that (1) call the non-
+		standard binfmt function 'exec', and then (2) exit(0).  The binfmt
+		function 'exec' needs to have (1) a symbol table that provides the
+		list of symbols exported by the base code, and (2) the number of
+		symbols in that table.  This selection provides the name of that
+		symbol table.
+
+config EXECFUNCS_NSYMBOLS
+	int "Number of Symbols in the Table"
+	default 0
+	---help---
+		The exec[l|v] functions are wrapper functions that (1) call the non-
+		standard binfmt function 'exec', and then (2) exit(0).  The binfmt
+		function 'exec' needs to have (1) a symbol table that provides the
+		list of symbols exported by the base code, and (2) the number of
+		symbols in that table.  This selection provides the number of
+		symbols in the symbol table.
+
+endif
+
 config LIBC_STRERROR
 	bool "Enable strerror"
 	default n
diff --git a/nuttx/libc/unistd/Make.defs b/nuttx/libc/unistd/Make.defs
index 67fce9b1d..3811673bf 100644
--- a/nuttx/libc/unistd/Make.defs
+++ b/nuttx/libc/unistd/Make.defs
@@ -41,6 +41,10 @@ ifneq ($(CONFIG_NFILE_DESCRIPTORS),0)
 ifneq ($(CONFIG_DISABLE_ENVIRON),y)
 CSRCS +=  lib_chdir.c lib_getcwd.c
 endif
+
+ifeq ($(CONFIG_LIBC_EXECFUNCS),y)
+CSRCS +=  lib_execl.c lib_execv.c
+endif
 endif
 
 # Add the unistd directory to the build
diff --git a/nuttx/libc/unistd/lib_execl.c b/nuttx/libc/unistd/lib_execl.c
new file mode 100644
index 000000000..ac3147343
--- /dev/null
+++ b/nuttx/libc/unistd/lib_execl.c
@@ -0,0 +1,146 @@
+/****************************************************************************
+ * libc/unistd/lib_execl.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdarg.h>
+#include <unistd.h>
+
+#ifdef CONFIG_LIBC_EXECFUNCS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: execl
+ *
+ * Description:
+ *   The standard 'exec' family of functions will replace the current process
+ *   image with a new process image. The new image will be constructed from a
+ *   regular, executable file called the new process image file. There will
+ *   be no return from a successful exec, because the calling process image
+ *   is overlaid by the new process image.
+ *
+ *   Simplified 'execl()' and 'execv()' functions are provided by NuttX for
+ *   compatibility.  NuttX is a tiny embedded RTOS that does not support
+ *   processes and hence the concept of overlaying a tasks process image with
+ *   a new process image does not make any sense.  In NuttX, these functions
+ *   are wrapper functions that:
+ *
+ *     1. Call the non-standard binfmt function 'exec', and then
+ *     2. exit(0).
+ *
+ *   Note the inefficiency when 'exec[l|v]()' is called in the normal, two-
+ *   step process:  (1) first call vfork() to create a new thread, then (2)
+ *   call 'exec[l|v]()' to replace the new thread with a program from the
+ *   file system.  Since the new thread will be terminated by the
+ *   'exec[l|v]()' call, it really served no purpose other than to suport
+ *   Unix compatility.
+ *
+ *   The non-standard binfmt function 'exec()' needs to have (1) a symbol
+ *   table that provides the list of symbols exported by the base code, and
+ *   (2) the number of symbols in that table.  This information is currently
+ *   provided to 'exec()' from 'exec[l|v]()' via NuttX configuration settings:
+ *
+ *     CONFIG_LIBC_EXECFUNCS     : Enable exec[l|v] Support
+ *     CONFIG_EXECFUNCS_SYMTAB   : Symbol table used by exec[l|v]
+ *     CONFIG_EXECFUNCS_NSYMBOLS : Number of Symbols in the Table
+ *
+ *   As a result of the above, the current implementations of 'execl()' and
+ *   'execv()' suffer from some incompatibilities that may or may not be
+ *   addressed in a future version of NuttX.  Other than just being an
+ *   inefficient use of MCU resource, the most serious of these is that
+ *   the exec'ed task will not have the same task ID as the vfork'ed
+ *   function.  So the parent function cannot know the ID of the exec'ed
+ *   task.
+ *
+ * Input Parameters:
+ *   path - The path to the program to be executed.  If CONFIG_BINFMT_EXEPATH
+ *     is defined in the configuration, then this may be a relative path
+ *     from the current working directory.  Otherwise, path must be the
+ *     absolute path to the program.
+ *   arg0,... - A list of the string arguments to be recevied by the
+ *     program.  Zero indicates the end of the list.
+ *
+ * Returned Value:
+ *   This function does not return on success.  On failure, it will return
+ *   -1 (ERROR) and will set the 'errno' value appropriately.
+ *
+ ****************************************************************************/
+
+int execl(FAR const char *path, ...)
+{
+  FAR char *argv[CONFIG_MAX_TASK_ARGS+1];
+  va_list ap;
+  int argc;
+
+  /* Collect the arguments into the argv[] array */
+
+  va_start(ap, path);
+  for (argc = 0; argc < CONFIG_MAX_TASK_ARGS; argc++)
+    {
+      argv[argc] = va_arg(ap, FAR char *);
+      if (argv[argc] == NULL)
+        {
+          break;
+        }
+    }
+
+  argv[CONFIG_MAX_TASK_ARGS] = NULL;
+  va_end(ap);
+
+  /* Then let execv() do the real work */
+
+  return execv(path, (char * const *)&argv);
+}
+
+#endif /* CONFIG_LIBC_EXECFUNCS */
\ No newline at end of file
diff --git a/nuttx/libc/unistd/lib_execv.c b/nuttx/libc/unistd/lib_execv.c
new file mode 100644
index 000000000..cad8ee307
--- /dev/null
+++ b/nuttx/libc/unistd/lib_execv.c
@@ -0,0 +1,168 @@
+/****************************************************************************
+ * libc/unistd/lib_execv.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdlib.h>
+#include <unistd.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/binfmt/binfmt.h>
+
+#ifdef CONFIG_LIBC_EXECFUNCS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* If CONFIG_LIBC_EXECFUNCS is defined in the configuration, then the
+ * following must also be defined:
+ */
+
+/* Symbol table used by exec[l|v] */
+
+#ifndef CONFIG_EXECFUNCS_SYMTAB
+#  error "CONFIG_EXECFUNCS_SYMTAB must be defined"
+#endif
+
+/* Number of Symbols in the Table */
+
+#ifndef CONFIG_EXECFUNCS_NSYMBOLS
+#  error "CONFIG_EXECFUNCS_NSYMBOLS must be defined"
+#endif
+
+/****************************************************************************
+ * Global Variables
+ ****************************************************************************/
+
+extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB;
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: execv
+ *
+ * Description:
+ *   The standard 'exec' family of functions will replace the current process
+ *   image with a new process image. The new image will be constructed from a
+ *   regular, executable file called the new process image file. There will
+ *   be no return from a successful exec, because the calling process image
+ *   is overlaid by the new process image.
+ *
+ *   Simplified 'execl()' and 'execv()' functions are provided by NuttX for
+ *   compatibility.  NuttX is a tiny embedded RTOS that does not support
+ *   processes and hence the concept of overlaying a tasks process image with
+ *   a new process image does not make any sense.  In NuttX, these functions
+ *   are wrapper functions that:
+ *
+ *     1. Call the non-standard binfmt function 'exec', and then
+ *     2. exit(0).
+ *
+ *   Note the inefficiency when 'exec[l|v]()' is called in the normal, two-
+ *   step process:  (1) first call vfork() to create a new thread, then (2)
+ *   call 'exec[l|v]()' to replace the new thread with a program from the
+ *   file system.  Since the new thread will be terminated by the
+ *   'exec[l|v]()' call, it really served no purpose other than to suport
+ *   Unix compatility.
+ *
+ *   The non-standard binfmt function 'exec()' needs to have (1) a symbol
+ *   table that provides the list of symbols exported by the base code, and
+ *   (2) the number of symbols in that table.  This information is currently
+ *   provided to 'exec()' from 'exec[l|v]()' via NuttX configuration settings:
+ *
+ *     CONFIG_LIBC_EXECFUNCS     : Enable exec[l|v] Support
+ *     CONFIG_EXECFUNCS_SYMTAB   : Symbol table used by exec[l|v]
+ *     CONFIG_EXECFUNCS_NSYMBOLS : Number of Symbols in the Table
+ *
+ *   As a result of the above, the current implementations of 'execl()' and
+ *   'execv()' suffer from some incompatibilities that may or may not be
+ *   addressed in a future version of NuttX.  Other than just being an
+ *   inefficient use of MCU resource, the most serious of these is that
+ *   the exec'ed task will not have the same task ID as the vfork'ed
+ *   function.  So the parent function cannot know the ID of the exec'ed
+ *   task.
+ *
+ * Input Parameters:
+ *   path - The path to the program to be executed.  If CONFIG_BINFMT_EXEPATH
+ *     is defined in the configuration, then this may be a relative path
+ *     from the current working directory.  Otherwise, path must be the
+ *     absolute path to the program.
+ *   argv - A pointer to an array of string arguments.  The end of the
+ *     array is indicated with a NULL entry.
+ *
+ * Returned Value:
+ *   This function does not return on success.  On failure, it will return
+ *   -1 (ERROR) and will set the 'errno' value appropriately.
+ *
+ ****************************************************************************/
+
+int execv(FAR const char *path, FAR char *const argv[])
+{
+  int ret;
+
+  /* Start the task */
+
+  ret = exec(path, (FAR const char **)argv,
+             &CONFIG_EXECFUNCS_SYMTAB, CONFIG_EXECFUNCS_NSYMBOLS);
+
+  if (ret < 0)
+    {
+      sdbg("exec failed: %d\n", errno);
+      return ERROR;
+    }
+
+  /* Then exit */
+
+  exit(0);
+
+  /* We should not get here, but might be needed by some compilers.  Other,
+   * smarter compilers might complain that this code is unreachable.  You just
+   * can't win.
+   */
+
+  return ERROR;
+}
+
+#endif /* CONFIG_LIBC_EXECFUNCS */
\ No newline at end of file
diff --git a/nuttx/tools/cfgdefine.c b/nuttx/tools/cfgdefine.c
index ee1dd4003..f026a186f 100644
--- a/nuttx/tools/cfgdefine.c
+++ b/nuttx/tools/cfgdefine.c
@@ -64,6 +64,7 @@ static const char *dequote_list[] =
   /* NuttX */
 
   "CONFIG_USER_ENTRYPOINT",            /* Name of entry point function */
+  "CONFIG_EXECFUNCS_SYMTAB",           /* Symbol table used by exec[l|v] */
 
   /* NxWidgets/NxWM */
 
-- 
cgit v1.2.3


From 23cc9f459cba8e90faf59922616f1c0975b389f3 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Tue, 8 Jan 2013 19:27:38 +0000
Subject: Eliminate arch/arc/src/lm3s/lm3s_internal.h; replace with several
 header files

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5494 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                                    |   3 +-
 nuttx/TODO                                         |  29 +-
 nuttx/arch/arm/src/arm/Toolchain.defs              |   2 +-
 nuttx/arch/arm/src/lm3s/chip.h                     |  10 +
 nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h         | 281 +++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h           |  69 +++
 nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c            |   2 +-
 nuttx/arch/arm/src/lm3s/lm3s_ethernet.c            |   4 +-
 nuttx/arch/arm/src/lm3s/lm3s_gpio.c                |   2 +-
 nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c             |   3 +-
 nuttx/arch/arm/src/lm3s/lm3s_internal.h            | 546 ---------------------
 nuttx/arch/arm/src/lm3s/lm3s_irq.c                 |   4 +-
 nuttx/arch/arm/src/lm3s/lm3s_lowputc.c             |   5 +-
 nuttx/arch/arm/src/lm3s/lm3s_ssi.c                 |   4 +-
 nuttx/arch/arm/src/lm3s/lm3s_start.c               |   4 +-
 nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c          |   3 +-
 nuttx/arch/arm/src/lm3s/lm3s_timerisr.c            |   1 -
 nuttx/arch/arm/src/lm3s/lm_ethernet.h              | 103 ++++
 nuttx/arch/arm/src/lm3s/lm_gpio.h                  | 223 +++++++++
 nuttx/arch/arm/src/lm3s/lm_lowputc.h               |  87 ++++
 nuttx/arch/arm/src/lm3s/lm_ssi.h                   | 114 +++++
 nuttx/arch/arm/src/lm3s/lm_syscontrol.h            | 100 ++++
 nuttx/configs/eagle100/httpd/defconfig             |   1 +
 nuttx/configs/eagle100/nettest/defconfig           |   1 +
 nuttx/configs/eagle100/nsh/defconfig               |   1 +
 nuttx/configs/eagle100/nxflat/defconfig            |   1 +
 nuttx/configs/eagle100/ostest/defconfig            |   1 +
 nuttx/configs/eagle100/src/eagle100_internal.h     |   1 +
 nuttx/configs/eagle100/src/up_leds.c               |   2 +-
 nuttx/configs/eagle100/src/up_ssi.c                |   2 +-
 nuttx/configs/eagle100/thttpd/defconfig            |   1 +
 nuttx/configs/ekk-lm3s9b96/nsh/defconfig           |   1 +
 nuttx/configs/ekk-lm3s9b96/ostest/defconfig        |   1 +
 .../ekk-lm3s9b96/src/ekklm3s9b96_internal.h        |   1 +
 nuttx/configs/ekk-lm3s9b96/src/up_leds.c           |   2 +-
 nuttx/configs/ekk-lm3s9b96/src/up_ssi.c            |   2 +-
 nuttx/configs/lm3s6432-s2e/nsh/defconfig           |   1 +
 nuttx/configs/lm3s6432-s2e/ostest/defconfig        |   1 +
 .../lm3s6432-s2e/src/lm3s6432s2e_internal.h        |   1 +
 nuttx/configs/lm3s6432-s2e/src/up_boot.c           |   2 +-
 nuttx/configs/lm3s6432-s2e/src/up_leds.c           |   2 +-
 nuttx/configs/lm3s6432-s2e/src/up_ssi.c            |   2 +-
 .../configs/lm3s6965-ek/src/lm3s6965ek_internal.h  |   1 +
 nuttx/configs/lm3s6965-ek/src/up_leds.c            |   2 +-
 nuttx/configs/lm3s6965-ek/src/up_oled.c            |   2 +-
 nuttx/configs/lm3s6965-ek/src/up_ssi.c             |   2 +-
 nuttx/configs/lm3s8962-ek/nsh/defconfig            |   1 +
 nuttx/configs/lm3s8962-ek/nx/defconfig             |   1 +
 nuttx/configs/lm3s8962-ek/ostest/defconfig         |   1 +
 .../configs/lm3s8962-ek/src/lm3s8962ek_internal.h  |   1 +
 nuttx/configs/lm3s8962-ek/src/up_leds.c            |   2 +-
 nuttx/configs/lm3s8962-ek/src/up_oled.c            |   2 +-
 nuttx/configs/lm3s8962-ek/src/up_ssi.c             |   2 +-
 53 files changed, 1069 insertions(+), 574 deletions(-)
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_internal.h
 create mode 100644 nuttx/arch/arm/src/lm3s/lm_ethernet.h
 create mode 100644 nuttx/arch/arm/src/lm3s/lm_gpio.h
 create mode 100644 nuttx/arch/arm/src/lm3s/lm_lowputc.h
 create mode 100644 nuttx/arch/arm/src/lm3s/lm_ssi.h
 create mode 100644 nuttx/arch/arm/src/lm3s/lm_syscontrol.h

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index ee6b088cf..edf500df6 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3891,5 +3891,6 @@
 	  public include area for compatibility with other architectures.
 	* arch/arm/src/lm3s/chip:  Move register definition header files
 	  into a new chip/ sub-directory.
-
+	* arch/arm/src/lm3s/lm3s_internal.h:  Broke up into several
+	  smaller header files.
 
diff --git a/nuttx/TODO b/nuttx/TODO
index 02100e97e..c0b00d497 100644
--- a/nuttx/TODO
+++ b/nuttx/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated January 4, 2013)
+NuttX TODO List (Last updated January 8, 2013)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 This file summarizes known NuttX bugs, limitations, inconsistencies with 
@@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements.
 
 nuttx/
 
- (10)  Task/Scheduler (sched/)
+ (11)  Task/Scheduler (sched/)
   (1)  Memory Managment (mm/)
   (2)  Signals (sched/, arch/)
   (2)  pthreads (sched/)
@@ -31,7 +31,7 @@ nuttx/
   (0)  ARM/LPC43x (arch/arm/src/lpc43xx/)
   (3)  ARM/STR71x (arch/arm/src/str71x/)
   (3)  ARM/LM3S6918 (arch/arm/src/lm3s/)
-  (4)  ARM/STM32 (arch/arm/src/stm32/)
+  (5)  ARM/STM32 (arch/arm/src/stm32/)
   (3)  AVR (arch/avr)
   (0)  Intel x86 (arch/x86)
   (5)  8051 / MCS51 (arch/8051/)
@@ -171,6 +171,24 @@ o Task/Scheduler (sched/)
                that includes NxWisges::CNxTimer is needed.
   Priority:    Medium Low for now
 
+  Title:       INCOMPATIBILITES WITH execv() AND execl()
+  Description: Simplified 'execl()' and 'execv()' functions are provided by
+               NuttX.  NuttX does not support processes and hence the concept
+               of overlaying a tasks process image with a new process image
+               does not make any sense.  In NuttX, these functions are
+               wrapper functions that:
+
+               1. Call the non-standard binfmt function 'exec', and then
+               2. exit(0).
+
+               As a result, the current implementations of 'execl()' and
+               'execv()' suffer from some incompatibilities, the most
+               serious of these is that the exec'ed task will not have
+               the same task ID as the vfork'ed function.  So the parent
+               function cannot know the ID of the exec'ed task.
+  Status:      Open
+  Priority:    Medium Low for now
+
 o Memory Managment (mm/)
   ^^^^^^^^^^^^^^^^^^^^^^
 
@@ -1481,6 +1499,11 @@ o ARM/STM32 (arch/arm/src/stm32/)
   Status:      Open
   Priority:    Low
 
+  Title:       STM32 F4 USB OTG FS DEVICE-SIDE DRIVER
+  Description: This driver is reported to be buggy and to need some TLC.
+  Status:      Open
+  Priority:    High
+
 o AVR (arch/avr)
   ^^^^^^^^^^^^^^
 
diff --git a/nuttx/arch/arm/src/arm/Toolchain.defs b/nuttx/arch/arm/src/arm/Toolchain.defs
index ea11c4dc9..daa825842 100644
--- a/nuttx/arch/arm/src/arm/Toolchain.defs
+++ b/nuttx/arch/arm/src/arm/Toolchain.defs
@@ -102,7 +102,7 @@ endif
 # NuttX buildroot under Linux or Cygwin
 
 ifeq ($(CONFIG_ARM_TOOLCHAIN),BUILDROOT)
-ifeq ($(CONFIG_ARMV_OABI_TOOLCHAIN),y)
+ifeq ($(CONFIG_ARM_OABI_TOOLCHAIN),y)
   CROSSDEV = arm-nuttx-elf-
   ARCROSSDEV = arm-nuttx-elf-
 else
diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h
index 1e96b5222..481a9be15 100644
--- a/nuttx/arch/arm/src/lm3s/chip.h
+++ b/nuttx/arch/arm/src/lm3s/chip.h
@@ -58,6 +58,16 @@
 #include "chip/lm3s_ethernet.h"   /* Ethernet MAC and PHY */
 #include "chip/lm3s_flash.h"      /* FLASH */
 
+/* The LM3S69xx only supports 8 priority levels.  The hardware priority mechanism
+ * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
+ * the Stellaris family), so any prioritization must be performed in those bits.
+ * The default priority level is set to the middle value
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN     0xe0 /* All bits set in minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h
new file mode 100644
index 000000000..62a4a03fd
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h
@@ -0,0 +1,281 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm3s_pinmap.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* The following lists the input value to lm3s_configgpio to setup the alternate,
+ * hardware function for each pin.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTA | 6)     /* PA6: Capture/Compare/PWM1 (CCP1) */
+#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 0)     /* PB0: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 1)     /* PB1: Capture/Compare/PWM2 (CCP2) */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_TMR5_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 4)     /* PC4: Capture/Compare/PWM5 (CCP5) */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
+#  define GPIO_TMR4_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 7)     /* PC7: Capture/Compare/PWM4 (CCP4) */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
+#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
+#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
+#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT  | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO     | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO     | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT  | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO   | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO     | GPIO_PORTC | 1) /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO     | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 2) /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */
+#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT  | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT  | GPIO_PORTD | 6) /* PD6: PWM Fault */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO     | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */
+#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
+#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
+#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
+#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
+#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
+#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
+#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
+#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
+#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
+#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
+#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
+#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
+#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
+#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
+#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
+#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFODIO | GPIO_PORTA | 6)   /* PA6: I2C1 clock (I2C1SCL) */
+#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
+#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
+#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFODIO  | GPIO_PORTB | 2)  /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1)  /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
+#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
+#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
+#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
+#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
+#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
+#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
+#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
+#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
+#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
+#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
+#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
+#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
+#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT   | GPIO_PORTA | 0)       /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTA | 1)       /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO      | GPIO_PORTA | 2)       /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO      | GPIO_PORTA | 3)       /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT   | GPIO_PORTA | 4)       /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTA | 5)       /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO      | GPIO_PORTA | 6)       /* PA6: Capture/Compare/PWM0 (CCP1) */
+#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 0)       /* PB0: PWM Generator 1, PWM2 */
+#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 1)       /* PB1: PWM Generator 1, PWM3 */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 2)       /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO    | GPIO_PORTB | 3)       /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 4)       /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 5)       /* PB5: Analog comparator 0 output (C0o) (differs) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 6)       /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 7)       /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 0)       /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 0)       /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO      | GPIO_PORTC | 1)       /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO      | GPIO_PORTC | 1)       /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 2)       /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTC | 3)       /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTC | 3)       /* PC3: JTAG SWO */
+#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 4)       /* PC4: QEI module 0 phase A. */
+#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 6)       /* PC6: QEI module 0 phase B. */
+#  define GPIO_CAN0_RX     (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 0)       /* PD0: CAN module  RX */
+#  define GPIO_CAN0_TX     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTD | 1)       /* PD1: CAN module TX */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 2)       /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTD | 3)       /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO      | GPIO_PORTD | 4)       /* PD4: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 6)       /* PD6: PWM Fault */
+#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFIO      | GPIO_PORTD | 7)       /* PC7: QEI module 0 index */
+#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTE | 0)       /* PE0: PWM Generator 2, PWM4 */
+#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTE | 1)       /* PE1: PWM Generator 1, PWM5 */
+#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 2)       /* PE2: QEI module 1 phase B. */
+#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 3)       /* PE3: QEI module 1 phase A. */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 0)       /* PF0: PWM Generator 0, PWM0 */
+#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 1)       /* PF1: QEI module 1 index. ) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 2)       /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 3)       /* PF3: LED0 */
+#  define GPIO_PWM0_1     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTG | 1)       /* PG1:PWM Generator 0, PWM1 */
+#else
+#  error "Unknown LM3S chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h
new file mode 100644
index 000000000..b00a6e794
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h
@@ -0,0 +1,69 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/chip/lm_pinmap.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H
+#define __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the memory map file for the specific Stellaris chip */
+
+#ifdef CONFIG_ARCH_CHIP_LM3S
+#  include "chip/lm3s_pinmap.h"
+#else
+#  error "Unsupported Stellaris PIN mapping"
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c
index 334a3930f..9d205b763 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c
@@ -48,7 +48,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c
index f7bbedb20..f44b6654f 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c
@@ -58,7 +58,9 @@
 #include "chip.h"
 #include "up_arch.h"
 
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
+#include "lm_ethernet.h"
+#include "chip/lm_pinmap.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c
index c345d113c..dd005fdd1 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c
@@ -50,7 +50,7 @@
 
 #include "up_arch.h"
 #include "os_internal.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c
index 7cc5fea40..511195f2d 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c
@@ -50,7 +50,8 @@
 #include "up_arch.h"
 #include "os_internal.h"
 #include "irq_internal.h"
-#include "lm3s_internal.h"
+
+#include "lm_gpio.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_internal.h b/nuttx/arch/arm/src/lm3s/lm3s_internal.h
deleted file mode 100644
index 9bfd67a5e..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_internal.h
+++ /dev/null
@@ -1,546 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_internal.h
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM3S_INTERNAL_H
-#define __ARCH_ARM_SRC_LM3S_LM3S_INTERNAL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "up_internal.h"
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* The LM3S69xx only supports 8 priority levels.  The hardware priority mechanism
- * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
- * the Stellaris family), so any prioritization must be performed in those bits.
- * The default priority level is set to the middle value
- */
-
-#define NVIC_SYSH_PRIORITY_MIN     0xe0 /* All bits set in minimum priority */
-#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
-#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
-
-/* Bit-encoded input to lm3s_configgpio() *******************************************/
-
-/* Encoding:
- * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB
- *
- * These bits set the primary function of the pin:
- * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn
- */
-
-#define GPIO_FUNC_SHIFT               29                         /* Bit 31-29: GPIO function */
-#define GPIO_FUNC_MASK                (7 << GPIO_FUNC_SHIFT)     /* (See table 9-1 in data sheet) */
-#define GPIO_FUNC_INPUT               (0 << GPIO_FUNC_SHIFT)     /*   Digital GPIO input */
-#define GPIO_FUNC_OUTPUT              (1 << GPIO_FUNC_SHIFT)     /*   Digital GPIO output */
-#define GPIO_FUNC_ODINPUT             (2 << GPIO_FUNC_SHIFT)     /*   Open-drain GPIO input */
-#define GPIO_FUNC_ODOUTPUT            (3 << GPIO_FUNC_SHIFT)     /*   Open-drain GPIO output */
-#define GPIO_FUNC_PFODIO              (4 << GPIO_FUNC_SHIFT)     /*   Open-drain input/output (I2C) */
-#define GPIO_FUNC_PFINPUT             (5 << GPIO_FUNC_SHIFT)     /*   Digital input (Timer, CCP) */
-#define GPIO_FUNC_PFOUTPUT            (5 << GPIO_FUNC_SHIFT)     /*   Digital output (Timer, PWM, Comparator) */
-#define GPIO_FUNC_PFIO                (5 << GPIO_FUNC_SHIFT)     /*   Digital input/output (SSI, UART) */
-#define GPIO_FUNC_ANINPUT             (6 << GPIO_FUNC_SHIFT)     /*   Analog input (Comparator) */
-#define GPIO_FUNC_INTERRUPT           (7 << GPIO_FUNC_SHIFT)     /*   Interrupt function */
-#define GPIO_FUNC_MAX                 GPIO_FUNC_INTERRUPT
-
-/* That primary may be modified by the following options
- * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn
- */
-
-#define GPIO_STRENGTH_SHIFT           27                         /* Bits 28-27: Pad drive strength */
-#define GPIO_STRENGTH_MASK            (3 << GPIO_STRENGTH_SHIFT)
-#define GPIO_STRENGTH_2MA             (0 << GPIO_STRENGTH_SHIFT) /*   2mA pad drive strength */
-#define GPIO_STRENGTH_4MA             (1 << GPIO_STRENGTH_SHIFT) /*   4mA pad drive strength */
-#define GPIO_STRENGTH_8MA             (2 << GPIO_STRENGTH_SHIFT) /*   8mA pad drive strength */
-#define GPIO_STRENGTH_8MASC           (3 << GPIO_STRENGTH_SHIFT) /*   8mA Pad drive with slew rate control */
-#define GPIO_STRENGTH_MAX             GPIO_STRENGTH_8MASC
-
-#define GPIO_PADTYPE_SHIFT            24                         /* Bits 26-24: Pad type */
-#define GPIO_PADTYPE_MASK             (7 << GPIO_PADTYPE_SHIFT)
-#define GPIO_PADTYPE_STD              (0 << GPIO_PADTYPE_SHIFT)  /*   Push-pull */
-#define GPIO_PADTYPE_STDWPU           (1 << GPIO_PADTYPE_SHIFT)  /*   Push-pull with weak pull-up */
-#define GPIO_PADTYPE_STDWPD           (2 << GPIO_PADTYPE_SHIFT)  /*   Push-pull with weak pull-down */
-#define GPIO_PADTYPE_OD               (3 << GPIO_PADTYPE_SHIFT)  /*   Open-drain */
-#define GPIO_PADTYPE_ODWPU            (4 << GPIO_PADTYPE_SHIFT)  /*   Open-drain with weak pull-up */
-#define GPIO_PADTYPE_ODWPD            (5 << GPIO_PADTYPE_SHIFT)  /*   Open-drain with weak pull-down */
-#define GPIO_PADTYPE_ANALOG           (6 << GPIO_PADTYPE_SHIFT)  /*   Analog comparator */
-
-/* If the pin is an interrupt, then the following options apply
- * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn
- */
-
-#define GPIO_INT_SHIFT                21                         /* Bits 23-21: Interrupt type */
-#define GPIO_INT_MASK                 (7 << GPIO_INT_SHIFT)
-#define GPIO_INT_FALLINGEDGE          (0 << GPIO_INT_SHIFT)      /*   Interrupt on falling edge */
-#define GPIO_INT_RISINGEDGE           (1 << GPIO_INT_SHIFT)      /*   Interrupt on rising edge */
-#define GPIO_INT_BOTHEDGES            (2 << GPIO_INT_SHIFT)      /*   Interrupt on both edges */
-#define GPIO_INT_LOWLEVEL             (3 << GPIO_INT_SHIFT)      /*   Interrupt on low level */
-#define GPIO_INT_HIGHLEVEL            (4 << GPIO_INT_SHIFT)      /*   Interrupt on high level */
-
-/* If the pin is an GPIO digital output, then this identifies the initial output value:
- * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn
- */
-
-#define GPIO_VALUE_SHIFT              7                          /* Bit 7: If output, inital value of output */
-#define GPIO_VALUE_MASK               (1 << GPIO_VALUE_SHIFT)
-#define GPIO_VALUE_ZERO               (0 << GPIO_VALUE_SHIFT)    /*   Initial value is zero */
-#define GPIO_VALUE_ONE                (1 << GPIO_VALUE_SHIFT)    /*   Initial value is one */
-
-/* This identifies the GPIO port
- * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn
- */
-
-#define GPIO_PORT_SHIFT               3                          /* Bit 3-6:  Port number */
-#define GPIO_PORT_MASK                (15 << GPIO_PORT_SHIFT)
-#define GPIO_PORTA                    (0 << GPIO_PORT_SHIFT)     /*   GPIOA */
-#define GPIO_PORTB                    (1 << GPIO_PORT_SHIFT)     /*   GPIOB */
-#define GPIO_PORTC                    (2 << GPIO_PORT_SHIFT)     /*   GPIOC */
-#define GPIO_PORTD                    (3 << GPIO_PORT_SHIFT)     /*   GPIOD */
-#define GPIO_PORTE                    (4 << GPIO_PORT_SHIFT)     /*   GPIOE */
-#define GPIO_PORTF                    (5 << GPIO_PORT_SHIFT)     /*   GPIOF */
-#define GPIO_PORTG                    (6 << GPIO_PORT_SHIFT)     /*   GPIOG */
-#define GPIO_PORTH                    (7 << GPIO_PORT_SHIFT)     /*   GPIOH */
-#define GPIO_PORTJ                    (8 << GPIO_PORT_SHIFT)     /*   GPIOJ */
-
-/* This identifies the bit in the port:
- * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB
- */
-
-#define GPIO_NUMBER_SHIFT             0                           /* Bits 0-2: GPIO number: 0-7 */
-#define GPIO_NUMBER_MASK              (7 << GPIO_NUMBER_SHIFT)
-
-/* The following lists the input value to lm3s_configgpio to setup the alternate,
- * hardware function for each pin.
- */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTA | 6)     /* PA6: Capture/Compare/PWM1 (CCP1) */
-#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
-#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 0)     /* PB0: Capture/Compare/PWM0 (CCP0) */
-#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 1)     /* PB1: Capture/Compare/PWM2 (CCP2) */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
-#  define GPIO_TMR5_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 4)     /* PC4: Capture/Compare/PWM5 (CCP5) */
-#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
-#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
-#  define GPIO_TMR4_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 7)     /* PC7: Capture/Compare/PWM4 (CCP4) */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
-#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
-#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
-#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
-#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT  | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO     | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO     | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT  | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO   | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO     | GPIO_PORTC | 1) /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO     | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 2) /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
-#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
-#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */
-#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT  | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT  | GPIO_PORTD | 6) /* PD6: PWM Fault */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO     | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */
-#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
-#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
-#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
-#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
-#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
-#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
-#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
-#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
-#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
-#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
-#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
-#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
-#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
-#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
-#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
-#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
-#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
-#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
-#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
-#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
-#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
-#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
-#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFODIO | GPIO_PORTA | 6)   /* PA6: I2C1 clock (I2C1SCL) */
-#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
-#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
-#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFODIO  | GPIO_PORTB | 2)  /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1)  /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
-#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
-#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
-#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
-#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
-#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
-#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
-#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
-#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
-#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
-#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
-#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
-#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
-#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
-#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
-#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
-#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
-#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
-#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
-#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
-#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
-
-
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT   | GPIO_PORTA | 0)       /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTA | 1)       /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO      | GPIO_PORTA | 2)       /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO      | GPIO_PORTA | 3)       /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT   | GPIO_PORTA | 4)       /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTA | 5)       /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO      | GPIO_PORTA | 6)       /* PA6: Capture/Compare/PWM0 (CCP1) */
-#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 0)       /* PB0: PWM Generator 1, PWM2 */
-#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 1)       /* PB1: PWM Generator 1, PWM3 */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 2)       /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO    | GPIO_PORTB | 3)       /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 4)       /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 5)       /* PB5: Analog comparator 0 output (C0o) (differs) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 6)       /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 7)       /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 0)       /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 0)       /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO      | GPIO_PORTC | 1)       /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO      | GPIO_PORTC | 1)       /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 2)       /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTC | 3)       /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTC | 3)       /* PC3: JTAG SWO */
-#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 4)       /* PC4: QEI module 0 phase A. */
-#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 6)       /* PC6: QEI module 0 phase B. */
-#  define GPIO_CAN0_RX     (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 0)       /* PD0: CAN module  RX */
-#  define GPIO_CAN0_TX     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTD | 1)       /* PD1: CAN module TX */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 2)       /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTD | 3)       /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO      | GPIO_PORTD | 4)       /* PD4: Capture/Compare/PWM0 (CCP0) */
-#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 6)       /* PD6: PWM Fault */
-#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFIO      | GPIO_PORTD | 7)       /* PC7: QEI module 0 index */
-#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTE | 0)       /* PE0: PWM Generator 2, PWM4 */
-#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTE | 1)       /* PE1: PWM Generator 1, PWM5 */
-#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 2)       /* PE2: QEI module 1 phase B. */
-#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 3)       /* PE3: QEI module 1 phase A. */
-#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 0)       /* PF0: PWM Generator 0, PWM0 */
-#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 1)       /* PF1: QEI module 1 index. ) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 2)       /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 3)       /* PF3: LED0 */
-#  define GPIO_PWM0_1     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTG | 1)       /* PG1:PWM Generator 0, PWM1 */
-#else
-#  error "Unknown LM3S chip"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_lowsetup
- *
- * Description:
- *   Called at the very beginning of _start.  Performs low level initialization.
- *
- ****************************************************************************/
-
-EXTERN void up_lowsetup(void);
-
-/****************************************************************************
- * Name: lm3s_clockconfig
- *
- * Description:
- *   Called to change to new clock based on desired rcc and rcc2 settings.
- *   This is use to set up the initial clocking but can be used later to
- *   support slow clocked, low power consumption modes.
- *
- ****************************************************************************/
-
-EXTERN void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2);
-
-/****************************************************************************
- * Name: up_clockconfig
- *
- * Description:
- *   Called early in the bootsequence (before .data and .bss are available)
- *   in order to configure initial clocking.
- *
- ****************************************************************************/
-
-EXTERN void up_clockconfig(void);
-
-/****************************************************************************
- * Name: lm3s_configgpio
- *
- * Description:
- *   Configure a GPIO pin based on bit-encoded description of the pin.
- *
- ****************************************************************************/
-
-EXTERN int lm3s_configgpio(uint32_t cfgset);
-
-/****************************************************************************
- * Name: lm3s_gpiowrite
- *
- * Description:
- *   Write one or zero to the selected GPIO pin
- *
- ****************************************************************************/
-
-EXTERN void lm3s_gpiowrite(uint32_t pinset, bool value);
-
-/****************************************************************************
- * Name: lm3s_gpioread
- *
- * Description:
- *   Read one or zero from the selected GPIO pin
- *
- ****************************************************************************/
-
-EXTERN bool lm3s_gpioread(uint32_t pinset, bool value);
-
-/****************************************************************************
- * Function:  lm3s_dumpgpio
- *
- * Description:
- *   Dump all GPIO registers associated with the provided base address
- *
- ****************************************************************************/
-
-EXTERN int lm3s_dumpgpio(uint32_t pinset, const char *msg);
-
-/****************************************************************************
- * Name: gpio_irqinitialize
- *
- * Description:
- *   Initialize all vectors to the unexpected interrupt handler
- *
- ****************************************************************************/
-
-EXTERN int weak_function gpio_irqinitialize(void);
-
-/****************************************************************************
- * Function: lm3s_ethinitialize
- *
- * Description:
- *   Initialize the Ethernet driver for one interface.  If the LM3S chip
- *   supports multiple Ethernet controllers, then bould specific logic
- *   must implement up_netinitialize() and call this function to initialize
- *   the desiresed interfaces.
- *
- * Parameters:
- *   None
- *
- * Returned Value:
- *   OK on success; Negated errno on failure.
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#if LM3S_NETHCONTROLLERS > 1
-EXTERN int lm3s_ethinitialize(int intf);
-#endif
-
-/****************************************************************************
- * The external functions, lm3s_spiselect, lm3s_spistatus, and
- * lm3s_spicmddata must be provided by board-specific logic.  These are
- * implementations of the select, status, and cmddata methods of the SPI
- * interface defined by struct spi_ops_s (see include/nuttx/spi.h).
- * All other methods (including up_spiinitialize()) are provided by common
- * logic.  To use this common SPI logic on your board:
- *
- *   1. Provide logic in lm3s_boardinitialize() to configure SPI chip select
- *      pins.
- *   2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
- *      board-specific logic.  These functions will perform chip selection and
- *      status operations using GPIOs in the way your board is configured.
- *   3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide
- *      the lm3s_spicmddata() function in your board-specific logic.  This
- *      functions will perform cmd/data selection operations using GPIOs in
- *      the way your board is configured.
- *   4. Add a call to up_spiinitialize() in your low level application
- *      initialization logic
- *   5. The handle returned by up_spiinitialize() may then be used to bind the
- *      SPI driver to higher level logic (e.g., calling 
- *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
- *      the SPI MMC/SD driver).
- *
- ****************************************************************************/
-
-struct spi_dev_s;
-enum spi_dev_e;
-EXTERN void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-EXTERN uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-#ifdef CONFIG_SPI_CMDDATA
-EXTERN int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
-#endif
-
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_LM3S_LM3S_INTERNAL_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_irq.c b/nuttx/arch/arm/src/lm3s/lm3s_irq.c
index aa0ed6c87..2f0b9fa72 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_irq.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_irq.c
@@ -51,7 +51,9 @@
 #include "up_arch.h"
 #include "os_internal.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+
+#include "chip.h"
+#include "lm_gpio.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
index b1cb21b2c..bdbd5a906 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
@@ -46,7 +46,10 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
+#include "chip/lm_pinmap.h"
+
+#include "lm_lowputc.h"
 
 /**************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c
index 8d1987992..8cd1cee07 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c
@@ -56,7 +56,9 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
+#include "lm_ssi.h"
+#include "chip/lm_pinmap.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_start.c b/nuttx/arch/arm/src/lm3s/lm3s_start.c
index f3f762b52..341b82e50 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_start.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_start.c
@@ -49,7 +49,9 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+
+#include "lm_lowputc.h"
+#include "lm_syscontrol.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
index e26789d32..3ad0cacb5 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
@@ -49,7 +49,8 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+#include "chip.h"
+#include "lm_syscontrol.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c
index 4d42af597..9cd912249 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c
@@ -51,7 +51,6 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "lm3s_internal.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm_ethernet.h b/nuttx/arch/arm/src/lm3s/lm_ethernet.h
new file mode 100644
index 000000000..600955b95
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/lm_ethernet.h
@@ -0,0 +1,103 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/lm_ethernet.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H
+#define __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+#if LM3S_NETHCONTROLLERS > 1
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: lm3s_ethinitialize
+ *
+ * Description:
+ *   Initialize the Ethernet driver for one interface.  If the LM3S chip
+ *   supports multiple Ethernet controllers, then bould specific logic
+ *   must implement up_netinitialize() and call this function to initialize
+ *   the desiresed interfaces.
+ *
+ * Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+int lm3s_ethinitialize(int intf);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* LM3S_NETHCONTROLLERS > 1 */
+#endif /* __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm_gpio.h b/nuttx/arch/arm/src/lm3s/lm_gpio.h
new file mode 100644
index 000000000..1bfb79fc9
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/lm_gpio.h
@@ -0,0 +1,223 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/lm_gpio.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_LM_GPIO_H
+#define __ARCH_ARM_SRC_LM3S_LM_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Bit-encoded input to lm3s_configgpio() *******************************************/
+
+/* Encoding:
+ * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB
+ *
+ * These bits set the primary function of the pin:
+ * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn
+ */
+
+#define GPIO_FUNC_SHIFT               29                         /* Bit 31-29: GPIO function */
+#define GPIO_FUNC_MASK                (7 << GPIO_FUNC_SHIFT)     /* (See table 9-1 in data sheet) */
+#define GPIO_FUNC_INPUT               (0 << GPIO_FUNC_SHIFT)     /*   Digital GPIO input */
+#define GPIO_FUNC_OUTPUT              (1 << GPIO_FUNC_SHIFT)     /*   Digital GPIO output */
+#define GPIO_FUNC_ODINPUT             (2 << GPIO_FUNC_SHIFT)     /*   Open-drain GPIO input */
+#define GPIO_FUNC_ODOUTPUT            (3 << GPIO_FUNC_SHIFT)     /*   Open-drain GPIO output */
+#define GPIO_FUNC_PFODIO              (4 << GPIO_FUNC_SHIFT)     /*   Open-drain input/output (I2C) */
+#define GPIO_FUNC_PFINPUT             (5 << GPIO_FUNC_SHIFT)     /*   Digital input (Timer, CCP) */
+#define GPIO_FUNC_PFOUTPUT            (5 << GPIO_FUNC_SHIFT)     /*   Digital output (Timer, PWM, Comparator) */
+#define GPIO_FUNC_PFIO                (5 << GPIO_FUNC_SHIFT)     /*   Digital input/output (SSI, UART) */
+#define GPIO_FUNC_ANINPUT             (6 << GPIO_FUNC_SHIFT)     /*   Analog input (Comparator) */
+#define GPIO_FUNC_INTERRUPT           (7 << GPIO_FUNC_SHIFT)     /*   Interrupt function */
+#define GPIO_FUNC_MAX                 GPIO_FUNC_INTERRUPT
+
+/* That primary may be modified by the following options
+ * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn
+ */
+
+#define GPIO_STRENGTH_SHIFT           27                         /* Bits 28-27: Pad drive strength */
+#define GPIO_STRENGTH_MASK            (3 << GPIO_STRENGTH_SHIFT)
+#define GPIO_STRENGTH_2MA             (0 << GPIO_STRENGTH_SHIFT) /*   2mA pad drive strength */
+#define GPIO_STRENGTH_4MA             (1 << GPIO_STRENGTH_SHIFT) /*   4mA pad drive strength */
+#define GPIO_STRENGTH_8MA             (2 << GPIO_STRENGTH_SHIFT) /*   8mA pad drive strength */
+#define GPIO_STRENGTH_8MASC           (3 << GPIO_STRENGTH_SHIFT) /*   8mA Pad drive with slew rate control */
+#define GPIO_STRENGTH_MAX             GPIO_STRENGTH_8MASC
+
+#define GPIO_PADTYPE_SHIFT            24                         /* Bits 26-24: Pad type */
+#define GPIO_PADTYPE_MASK             (7 << GPIO_PADTYPE_SHIFT)
+#define GPIO_PADTYPE_STD              (0 << GPIO_PADTYPE_SHIFT)  /*   Push-pull */
+#define GPIO_PADTYPE_STDWPU           (1 << GPIO_PADTYPE_SHIFT)  /*   Push-pull with weak pull-up */
+#define GPIO_PADTYPE_STDWPD           (2 << GPIO_PADTYPE_SHIFT)  /*   Push-pull with weak pull-down */
+#define GPIO_PADTYPE_OD               (3 << GPIO_PADTYPE_SHIFT)  /*   Open-drain */
+#define GPIO_PADTYPE_ODWPU            (4 << GPIO_PADTYPE_SHIFT)  /*   Open-drain with weak pull-up */
+#define GPIO_PADTYPE_ODWPD            (5 << GPIO_PADTYPE_SHIFT)  /*   Open-drain with weak pull-down */
+#define GPIO_PADTYPE_ANALOG           (6 << GPIO_PADTYPE_SHIFT)  /*   Analog comparator */
+
+/* If the pin is an interrupt, then the following options apply
+ * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn
+ */
+
+#define GPIO_INT_SHIFT                21                         /* Bits 23-21: Interrupt type */
+#define GPIO_INT_MASK                 (7 << GPIO_INT_SHIFT)
+#define GPIO_INT_FALLINGEDGE          (0 << GPIO_INT_SHIFT)      /*   Interrupt on falling edge */
+#define GPIO_INT_RISINGEDGE           (1 << GPIO_INT_SHIFT)      /*   Interrupt on rising edge */
+#define GPIO_INT_BOTHEDGES            (2 << GPIO_INT_SHIFT)      /*   Interrupt on both edges */
+#define GPIO_INT_LOWLEVEL             (3 << GPIO_INT_SHIFT)      /*   Interrupt on low level */
+#define GPIO_INT_HIGHLEVEL            (4 << GPIO_INT_SHIFT)      /*   Interrupt on high level */
+
+/* If the pin is an GPIO digital output, then this identifies the initial output value:
+ * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn
+ */
+
+#define GPIO_VALUE_SHIFT              7                          /* Bit 7: If output, inital value of output */
+#define GPIO_VALUE_MASK               (1 << GPIO_VALUE_SHIFT)
+#define GPIO_VALUE_ZERO               (0 << GPIO_VALUE_SHIFT)    /*   Initial value is zero */
+#define GPIO_VALUE_ONE                (1 << GPIO_VALUE_SHIFT)    /*   Initial value is one */
+
+/* This identifies the GPIO port
+ * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn
+ */
+
+#define GPIO_PORT_SHIFT               3                          /* Bit 3-6:  Port number */
+#define GPIO_PORT_MASK                (15 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA                    (0 << GPIO_PORT_SHIFT)     /*   GPIOA */
+#define GPIO_PORTB                    (1 << GPIO_PORT_SHIFT)     /*   GPIOB */
+#define GPIO_PORTC                    (2 << GPIO_PORT_SHIFT)     /*   GPIOC */
+#define GPIO_PORTD                    (3 << GPIO_PORT_SHIFT)     /*   GPIOD */
+#define GPIO_PORTE                    (4 << GPIO_PORT_SHIFT)     /*   GPIOE */
+#define GPIO_PORTF                    (5 << GPIO_PORT_SHIFT)     /*   GPIOF */
+#define GPIO_PORTG                    (6 << GPIO_PORT_SHIFT)     /*   GPIOG */
+#define GPIO_PORTH                    (7 << GPIO_PORT_SHIFT)     /*   GPIOH */
+#define GPIO_PORTJ                    (8 << GPIO_PORT_SHIFT)     /*   GPIOJ */
+
+/* This identifies the bit in the port:
+ * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB
+ */
+
+#define GPIO_NUMBER_SHIFT             0                           /* Bits 0-2: GPIO number: 0-7 */
+#define GPIO_NUMBER_MASK              (7 << GPIO_NUMBER_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int lm3s_configgpio(uint32_t cfgset);
+
+/****************************************************************************
+ * Name: lm3s_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void lm3s_gpiowrite(uint32_t pinset, bool value);
+
+/****************************************************************************
+ * Name: lm3s_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool lm3s_gpioread(uint32_t pinset, bool value);
+
+/****************************************************************************
+ * Function:  lm3s_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the provided base address
+ *
+ ****************************************************************************/
+
+int lm3s_dumpgpio(uint32_t pinset, const char *msg);
+
+/****************************************************************************
+ * Name: gpio_irqinitialize
+ *
+ * Description:
+ *   Initialize all vectors to the unexpected interrupt handler
+ *
+ ****************************************************************************/
+
+int weak_function gpio_irqinitialize(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LM3S_LM_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm_lowputc.h b/nuttx/arch/arm/src/lm3s/lm_lowputc.h
new file mode 100644
index 000000000..8e2858ebf
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/lm_lowputc.h
@@ -0,0 +1,87 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/lm3s_lowputc.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H
+#define __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Performs low level initialization.
+ *
+ ****************************************************************************/
+
+void up_lowsetup(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm_ssi.h b/nuttx/arch/arm/src/lm3s/lm_ssi.h
new file mode 100644
index 000000000..dd1e30817
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/lm_ssi.h
@@ -0,0 +1,114 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/lm_ssi.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_LM_SSI_H
+#define __ARCH_ARM_SRC_LM3S_LM_SSI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * The external functions, lm3s_spiselect, lm3s_spistatus, and
+ * lm3s_spicmddata must be provided by board-specific logic.  These are
+ * implementations of the select, status, and cmddata methods of the SPI
+ * interface defined by struct spi_ops_s (see include/nuttx/spi.h).
+ * All other methods (including up_spiinitialize()) are provided by common
+ * logic.  To use this common SPI logic on your board:
+ *
+ *   1. Provide logic in lm3s_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
+ *      board-specific logic.  These functions will perform chip selection and
+ *      status operations using GPIOs in the way your board is configured.
+ *   3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide
+ *      the lm3s_spicmddata() function in your board-specific logic.  This
+ *      functions will perform cmd/data selection operations using GPIOs in
+ *      the way your board is configured.
+ *   4. Add a call to up_spiinitialize() in your low level application
+ *      initialization logic
+ *   5. The handle returned by up_spiinitialize() may then be used to bind the
+ *      SPI driver to higher level logic (e.g., calling 
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+struct spi_dev_s;
+enum spi_dev_e;
+void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+#ifdef CONFIG_SPI_CMDDATA
+int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LM3S_LM_SSI_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm_syscontrol.h
new file mode 100644
index 000000000..7c49da565
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/lm_syscontrol.h
@@ -0,0 +1,100 @@
+/************************************************************************************
+ * arch/arm/src/lm3s/lm3s_syscontrol.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H
+#define __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_clockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on desired rcc and rcc2 settings.
+ *   This is use to set up the initial clocking but can be used later to
+ *   support slow clocked, low power consumption modes.
+ *
+ ****************************************************************************/
+
+void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2);
+
+/****************************************************************************
+ * Name: up_clockconfig
+ *
+ * Description:
+ *   Called early in the bootsequence (before .data and .bss are available)
+ *   in order to configure initial clocking.
+ *
+ ****************************************************************************/
+
+void up_clockconfig(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H */
diff --git a/nuttx/configs/eagle100/httpd/defconfig b/nuttx/configs/eagle100/httpd/defconfig
index 2d8f82180..c2ea86bed 100644
--- a/nuttx/configs/eagle100/httpd/defconfig
+++ b/nuttx/configs/eagle100/httpd/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
 CONFIG_ARCH_BOARD_EAGLE100=y
diff --git a/nuttx/configs/eagle100/nettest/defconfig b/nuttx/configs/eagle100/nettest/defconfig
index fa0740208..2dab94846 100644
--- a/nuttx/configs/eagle100/nettest/defconfig
+++ b/nuttx/configs/eagle100/nettest/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
 CONFIG_ARCH_BOARD_EAGLE100=y
diff --git a/nuttx/configs/eagle100/nsh/defconfig b/nuttx/configs/eagle100/nsh/defconfig
index d8041c299..fd141bc80 100644
--- a/nuttx/configs/eagle100/nsh/defconfig
+++ b/nuttx/configs/eagle100/nsh/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
 CONFIG_ARCH_BOARD_EAGLE100=y
diff --git a/nuttx/configs/eagle100/nxflat/defconfig b/nuttx/configs/eagle100/nxflat/defconfig
index 756902bb0..20cd50432 100644
--- a/nuttx/configs/eagle100/nxflat/defconfig
+++ b/nuttx/configs/eagle100/nxflat/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
 CONFIG_ARCH_BOARD_EAGLE100=y
diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig
index 43c77fe07..01f3be334 100644
--- a/nuttx/configs/eagle100/ostest/defconfig
+++ b/nuttx/configs/eagle100/ostest/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
 CONFIG_ARCH_BOARD_EAGLE100=y
diff --git a/nuttx/configs/eagle100/src/eagle100_internal.h b/nuttx/configs/eagle100/src/eagle100_internal.h
index 88d2bf3b0..d8bcd6a81 100644
--- a/nuttx/configs/eagle100/src/eagle100_internal.h
+++ b/nuttx/configs/eagle100/src/eagle100_internal.h
@@ -45,6 +45,7 @@
 #include <nuttx/compiler.h>
 
 #include "chip.h"
+#include "lm_gpio.h"
 
 /************************************************************************************
  * Definitions
diff --git a/nuttx/configs/eagle100/src/up_leds.c b/nuttx/configs/eagle100/src/up_leds.c
index 59b489c11..0124b964b 100644
--- a/nuttx/configs/eagle100/src/up_leds.c
+++ b/nuttx/configs/eagle100/src/up_leds.c
@@ -48,7 +48,7 @@
 #include "chip.h"
 #include "up_arch.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "eagle100_internal.h"
 
 /****************************************************************************
diff --git a/nuttx/configs/eagle100/src/up_ssi.c b/nuttx/configs/eagle100/src/up_ssi.c
index fb5f99df3..b78a0d67c 100644
--- a/nuttx/configs/eagle100/src/up_ssi.c
+++ b/nuttx/configs/eagle100/src/up_ssi.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "eagle100_internal.h"
 
 /* The Eagle100 microSD CS is on SSI0 */
diff --git a/nuttx/configs/eagle100/thttpd/defconfig b/nuttx/configs/eagle100/thttpd/defconfig
index dceac0990..460bd64b3 100644
--- a/nuttx/configs/eagle100/thttpd/defconfig
+++ b/nuttx/configs/eagle100/thttpd/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
 CONFIG_ARCH_BOARD_EAGLE100=y
diff --git a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
index 82ad3ce5d..d8ae63cff 100644
--- a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
+++ b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
@@ -40,6 +40,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S9B96=y
 CONFIG_ARCH_BOARD="ekk-lm3s9b96"
 CONFIG_ARCH_BOARD_EKKLM3S9B96=y
diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
index bcf2a9426..62a092d1f 100644
--- a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
+++ b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
@@ -40,6 +40,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S9B96=y
 CONFIG_ARCH_BOARD="ekk-lm3s9b96"
 CONFIG_ARCH_BOARD_EKKLM3S9B96=y
diff --git a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
index fd8ff3adb..bb3315f5b 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
+++ b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
@@ -46,6 +46,7 @@
 #include <nuttx/compiler.h>
 
 #include "chip.h"
+#include "lm_gpio.h"
 
 /************************************************************************************
  * Definitions
diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_leds.c b/nuttx/configs/ekk-lm3s9b96/src/up_leds.c
index 5ed84c2d2..7628fcfe0 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/up_leds.c
+++ b/nuttx/configs/ekk-lm3s9b96/src/up_leds.c
@@ -49,7 +49,7 @@
 #include "chip.h"
 #include "up_arch.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "ekklm3s9b96_internal.h"
 
 /****************************************************************************
diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c b/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c
index 2fe3b81c8..8f297e7a7 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c
+++ b/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c
@@ -50,7 +50,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "ekklm3s9b96_internal.h"
 
 #if !defined(CONFIG_SSI0_DISABLE)  || !defined(CONFIG_SSI1_DISABLE) 
diff --git a/nuttx/configs/lm3s6432-s2e/nsh/defconfig b/nuttx/configs/lm3s6432-s2e/nsh/defconfig
index 704d8ad91..7d1657cda 100644
--- a/nuttx/configs/lm3s6432-s2e/nsh/defconfig
+++ b/nuttx/configs/lm3s6432-s2e/nsh/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6432=y
 CONFIG_ARCH_BOARD="lm3s6432-s2e"
 CONFIG_ARCH_BOARD_LM3S6432S2E=y
diff --git a/nuttx/configs/lm3s6432-s2e/ostest/defconfig b/nuttx/configs/lm3s6432-s2e/ostest/defconfig
index 0be2cfd4c..90357ce7f 100644
--- a/nuttx/configs/lm3s6432-s2e/ostest/defconfig
+++ b/nuttx/configs/lm3s6432-s2e/ostest/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6432=y
 CONFIG_ARCH_BOARD="lm3s6432-s2e"
 CONFIG_ARCH_BOARD_LM3S6432S2E=y
diff --git a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
index bd4cff77f..f54403c7a 100644
--- a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
+++ b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
@@ -44,6 +44,7 @@
 #include <nuttx/compiler.h>
 
 #include "chip.h"
+#include "lm_gpio.h"
 
 /************************************************************************************
  * Definitions
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_boot.c b/nuttx/configs/lm3s6432-s2e/src/up_boot.c
index 5bb7b670f..184529638 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_boot.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_boot.c
@@ -47,7 +47,7 @@
 #include "up_arch.h"
 #include "chip.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s6432s2e_internal.h"
 
 /************************************************************************************
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_leds.c b/nuttx/configs/lm3s6432-s2e/src/up_leds.c
index 80fea934f..81610db34 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_leds.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_leds.c
@@ -48,7 +48,7 @@
 #include "chip.h"
 #include "up_arch.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s6432s2e_internal.h"
 
 /****************************************************************************
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_ssi.c b/nuttx/configs/lm3s6432-s2e/src/up_ssi.c
index d20e1d978..a7844a979 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_ssi.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_ssi.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s6432s2e_internal.h"
 
 #if !defined(CONFIG_SSI0_DISABLE)
diff --git a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
index 621f00148..8ebd4cf65 100644
--- a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
+++ b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
@@ -45,6 +45,7 @@
 #include <nuttx/compiler.h>
 
 #include "chip.h"
+#include "lm_gpio.h"
 
 /************************************************************************************
  * Definitions
diff --git a/nuttx/configs/lm3s6965-ek/src/up_leds.c b/nuttx/configs/lm3s6965-ek/src/up_leds.c
index 933c11446..efa1eb738 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_leds.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_leds.c
@@ -48,7 +48,7 @@
 #include "chip.h"
 #include "up_arch.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s6965ek_internal.h"
 
 /****************************************************************************
diff --git a/nuttx/configs/lm3s6965-ek/src/up_oled.c b/nuttx/configs/lm3s6965-ek/src/up_oled.c
index 586927d53..23ce7e036 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_oled.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_oled.c
@@ -48,7 +48,7 @@
 #include <nuttx/lcd/lcd.h>
 #include <nuttx/lcd/p14201.h>
 
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s6965ek_internal.h"
 
 /****************************************************************************
diff --git a/nuttx/configs/lm3s6965-ek/src/up_ssi.c b/nuttx/configs/lm3s6965-ek/src/up_ssi.c
index 16111fcda..b52116f14 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_ssi.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_ssi.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s6965ek_internal.h"
 
 /* The LM3S6965 Eval Kit microSD CS is on SSI0 */
diff --git a/nuttx/configs/lm3s8962-ek/nsh/defconfig b/nuttx/configs/lm3s8962-ek/nsh/defconfig
index 573ea582e..79f90d5f9 100755
--- a/nuttx/configs/lm3s8962-ek/nsh/defconfig
+++ b/nuttx/configs/lm3s8962-ek/nsh/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S8962=y
 CONFIG_ARCH_BOARD="lm3s8962-ek"
 CONFIG_ARCH_BOARD_LM3S8962EK=y
diff --git a/nuttx/configs/lm3s8962-ek/nx/defconfig b/nuttx/configs/lm3s8962-ek/nx/defconfig
index 30c3b8952..8424b6623 100755
--- a/nuttx/configs/lm3s8962-ek/nx/defconfig
+++ b/nuttx/configs/lm3s8962-ek/nx/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S8962=y
 CONFIG_ARCH_BOARD="lm3s8962-ek"
 CONFIG_ARCH_BOARD_LM3S8962EK=y
diff --git a/nuttx/configs/lm3s8962-ek/ostest/defconfig b/nuttx/configs/lm3s8962-ek/ostest/defconfig
index e19cab1cc..73fbff29f 100755
--- a/nuttx/configs/lm3s8962-ek/ostest/defconfig
+++ b/nuttx/configs/lm3s8962-ek/ostest/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S8962=y
 CONFIG_ARCH_BOARD="lm3s8962-ek"
 CONFIG_ARCH_BOARD_LM3S8962EK=y
diff --git a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
index 3b6175661..689472f15 100644
--- a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
+++ b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
@@ -45,6 +45,7 @@
 #include <nuttx/compiler.h>
 
 #include "chip.h"
+#include "lm_gpio.h"
 
 /************************************************************************************
  * Definitions
diff --git a/nuttx/configs/lm3s8962-ek/src/up_leds.c b/nuttx/configs/lm3s8962-ek/src/up_leds.c
index bff920434..d5000d037 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_leds.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_leds.c
@@ -48,7 +48,7 @@
 #include "chip.h"
 #include "up_arch.h"
 #include "up_internal.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s8962ek_internal.h"
 
 /****************************************************************************
diff --git a/nuttx/configs/lm3s8962-ek/src/up_oled.c b/nuttx/configs/lm3s8962-ek/src/up_oled.c
index 761187279..3324b3897 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_oled.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_oled.c
@@ -48,7 +48,7 @@
 #include <nuttx/lcd/lcd.h>
 #include <nuttx/lcd/p14201.h>
 
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s8962ek_internal.h"
 
 /****************************************************************************
diff --git a/nuttx/configs/lm3s8962-ek/src/up_ssi.c b/nuttx/configs/lm3s8962-ek/src/up_ssi.c
index 00e07c85d..7f78b3477 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_ssi.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_ssi.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "lm3s_internal.h"
+#include "lm_gpio.h"
 #include "lm3s8962ek_internal.h"
 
 /* The LM3S8962 Eval Kit microSD CS is on SSI0 */
-- 
cgit v1.2.3


From 3f4d20628887f3d76705262fcbf18315bc31ea18 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Tue, 8 Jan 2013 20:56:40 +0000
Subject: Rename arch/arm/src/lm3s to arch/arm/src/lm to allow a namespace that
 will include the lm4f

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5495 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                                    |    3 +
 nuttx/TODO                                         |    4 +-
 nuttx/arch/README.txt                              |   12 +-
 nuttx/arch/arm/Kconfig                             |    9 +-
 nuttx/arch/arm/include/lm/chip.h                   |  123 ++
 nuttx/arch/arm/include/lm/irq.h                    |  497 ++++++
 nuttx/arch/arm/include/lm3s/chip.h                 |  123 --
 nuttx/arch/arm/include/lm3s/irq.h                  |  497 ------
 nuttx/arch/arm/src/lm/Kconfig                      |  217 +++
 nuttx/arch/arm/src/lm/Make.defs                    |   64 +
 nuttx/arch/arm/src/lm/chip.h                       |   83 +
 nuttx/arch/arm/src/lm/chip/lm3s_epi.h              |  113 ++
 nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h         |  203 +++
 nuttx/arch/arm/src/lm/chip/lm3s_flash.h            |  128 ++
 nuttx/arch/arm/src/lm/chip/lm3s_gpio.h             |  395 +++++
 nuttx/arch/arm/src/lm/chip/lm3s_i2c.h              |  247 +++
 nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h        |  360 +++++
 nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h           |  281 ++++
 nuttx/arch/arm/src/lm/chip/lm3s_ssi.h              |  235 +++
 nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h       |  495 ++++++
 nuttx/arch/arm/src/lm/chip/lm3s_timer.h            |  125 ++
 nuttx/arch/arm/src/lm/chip/lm3s_uart.h             |  347 +++++
 nuttx/arch/arm/src/lm/chip/lm_memorymap.h          |   69 +
 nuttx/arch/arm/src/lm/chip/lm_pinmap.h             |   69 +
 nuttx/arch/arm/src/lm/lm3s_dumpgpio.c              |  167 +++
 nuttx/arch/arm/src/lm/lm3s_ethernet.c              | 1472 ++++++++++++++++++
 nuttx/arch/arm/src/lm/lm3s_gpio.c                  |  854 +++++++++++
 nuttx/arch/arm/src/lm/lm3s_gpioirq.c               |  434 ++++++
 nuttx/arch/arm/src/lm/lm3s_irq.c                   |  458 ++++++
 nuttx/arch/arm/src/lm/lm3s_lowputc.c               |  309 ++++
 nuttx/arch/arm/src/lm/lm3s_serial.c                | 1064 +++++++++++++
 nuttx/arch/arm/src/lm/lm3s_ssi.c                   | 1580 ++++++++++++++++++++
 nuttx/arch/arm/src/lm/lm3s_start.c                 |  154 ++
 nuttx/arch/arm/src/lm/lm3s_syscontrol.c            |  315 ++++
 nuttx/arch/arm/src/lm/lm3s_timerisr.c              |  142 ++
 nuttx/arch/arm/src/lm/lm3s_vectors.S               |  805 ++++++++++
 nuttx/arch/arm/src/lm/lm_ethernet.h                |  103 ++
 nuttx/arch/arm/src/lm/lm_gpio.h                    |  223 +++
 nuttx/arch/arm/src/lm/lm_lowputc.h                 |   87 ++
 nuttx/arch/arm/src/lm/lm_ssi.h                     |  114 ++
 nuttx/arch/arm/src/lm/lm_syscontrol.h              |  100 ++
 nuttx/arch/arm/src/lm3s/Kconfig                    |  199 ---
 nuttx/arch/arm/src/lm3s/Make.defs                  |   64 -
 nuttx/arch/arm/src/lm3s/chip.h                     |   83 -
 nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h            |  113 --
 nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h       |  203 ---
 nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h          |  128 --
 nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h           |  395 -----
 nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h            |  247 ---
 nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h      |  360 -----
 nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h         |  281 ----
 nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h            |  235 ---
 nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h     |  495 ------
 nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h          |  125 --
 nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h           |  347 -----
 nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h        |   69 -
 nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h           |   69 -
 nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c            |  167 ---
 nuttx/arch/arm/src/lm3s/lm3s_ethernet.c            | 1472 ------------------
 nuttx/arch/arm/src/lm3s/lm3s_gpio.c                |  854 -----------
 nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c             |  434 ------
 nuttx/arch/arm/src/lm3s/lm3s_irq.c                 |  458 ------
 nuttx/arch/arm/src/lm3s/lm3s_lowputc.c             |  309 ----
 nuttx/arch/arm/src/lm3s/lm3s_serial.c              | 1064 -------------
 nuttx/arch/arm/src/lm3s/lm3s_ssi.c                 | 1580 --------------------
 nuttx/arch/arm/src/lm3s/lm3s_start.c               |  154 --
 nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c          |  315 ----
 nuttx/arch/arm/src/lm3s/lm3s_timerisr.c            |  142 --
 nuttx/arch/arm/src/lm3s/lm3s_vectors.S             |  805 ----------
 nuttx/arch/arm/src/lm3s/lm_ethernet.h              |  103 --
 nuttx/arch/arm/src/lm3s/lm_gpio.h                  |  223 ---
 nuttx/arch/arm/src/lm3s/lm_lowputc.h               |   87 --
 nuttx/arch/arm/src/lm3s/lm_ssi.h                   |  114 --
 nuttx/arch/arm/src/lm3s/lm_syscontrol.h            |  100 --
 nuttx/configs/eagle100/README.txt                  |    4 +-
 nuttx/configs/eagle100/httpd/defconfig             |    3 +-
 nuttx/configs/eagle100/nettest/defconfig           |    3 +-
 nuttx/configs/eagle100/nsh/defconfig               |    3 +-
 nuttx/configs/eagle100/nxflat/defconfig            |    3 +-
 nuttx/configs/eagle100/ostest/defconfig            |    3 +-
 nuttx/configs/eagle100/thttpd/defconfig            |    3 +-
 nuttx/configs/ekk-lm3s9b96/README.txt              |    8 +-
 nuttx/configs/ekk-lm3s9b96/nsh/defconfig           |    3 +-
 nuttx/configs/ekk-lm3s9b96/ostest/defconfig        |    3 +-
 .../ekk-lm3s9b96/src/ekklm3s9b96_internal.h        |    2 +-
 nuttx/configs/lm3s6432-s2e/README.txt              |    6 +-
 nuttx/configs/lm3s6432-s2e/nsh/defconfig           |    3 +-
 nuttx/configs/lm3s6432-s2e/ostest/defconfig        |    3 +-
 nuttx/configs/lm3s6965-ek/README.txt               |    8 +-
 nuttx/configs/lm3s6965-ek/nsh/defconfig            |    3 +-
 nuttx/configs/lm3s6965-ek/nx/defconfig             |    3 +-
 nuttx/configs/lm3s6965-ek/ostest/defconfig         |    3 +-
 .../configs/lm3s6965-ek/src/lm3s6965ek_internal.h  |    2 +-
 nuttx/configs/lm3s8962-ek/README.txt               |    8 +-
 nuttx/configs/lm3s8962-ek/nsh/defconfig            |    3 +-
 nuttx/configs/lm3s8962-ek/nx/defconfig             |    3 +-
 nuttx/configs/lm3s8962-ek/ostest/defconfig         |    3 +-
 97 files changed, 12498 insertions(+), 12462 deletions(-)
 create mode 100644 nuttx/arch/arm/include/lm/chip.h
 create mode 100644 nuttx/arch/arm/include/lm/irq.h
 delete mode 100644 nuttx/arch/arm/include/lm3s/chip.h
 delete mode 100644 nuttx/arch/arm/include/lm3s/irq.h
 create mode 100644 nuttx/arch/arm/src/lm/Kconfig
 create mode 100644 nuttx/arch/arm/src/lm/Make.defs
 create mode 100644 nuttx/arch/arm/src/lm/chip.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_epi.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_flash.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_gpio.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_i2c.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_ssi.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_timer.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_uart.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_memorymap.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_pinmap.h
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_dumpgpio.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_ethernet.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_gpio.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_gpioirq.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_irq.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_lowputc.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_serial.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_ssi.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_start.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_syscontrol.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_timerisr.c
 create mode 100644 nuttx/arch/arm/src/lm/lm3s_vectors.S
 create mode 100644 nuttx/arch/arm/src/lm/lm_ethernet.h
 create mode 100644 nuttx/arch/arm/src/lm/lm_gpio.h
 create mode 100644 nuttx/arch/arm/src/lm/lm_lowputc.h
 create mode 100644 nuttx/arch/arm/src/lm/lm_ssi.h
 create mode 100644 nuttx/arch/arm/src/lm/lm_syscontrol.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/Kconfig
 delete mode 100644 nuttx/arch/arm/src/lm3s/Make.defs
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_ethernet.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_gpio.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_irq.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_serial.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_ssi.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_start.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_timerisr.c
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_vectors.S
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm_ethernet.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm_gpio.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm_lowputc.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm_ssi.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm_syscontrol.h

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index edf500df6..35bf42253 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3893,4 +3893,7 @@
 	  into a new chip/ sub-directory.
 	* arch/arm/src/lm3s/lm3s_internal.h:  Broke up into several
 	  smaller header files.
+	* arch/arm/src/lm:  Rename the arch/arm/src/lm3s directory to
+	  arch/arm/src/lm so that is can support other members of the
+	  Stellaris family.
 
diff --git a/nuttx/TODO b/nuttx/TODO
index c0b00d497..72eb845bc 100644
--- a/nuttx/TODO
+++ b/nuttx/TODO
@@ -30,7 +30,7 @@ nuttx/
   (2)  ARM/LPC313x (arch/arm/src/lpc313x/)
   (0)  ARM/LPC43x (arch/arm/src/lpc43xx/)
   (3)  ARM/STR71x (arch/arm/src/str71x/)
-  (3)  ARM/LM3S6918 (arch/arm/src/lm3s/)
+  (3)  ARM/LM3S6918 (arch/arm/src/lm/)
   (5)  ARM/STM32 (arch/arm/src/stm32/)
   (3)  AVR (arch/avr)
   (0)  Intel x86 (arch/x86)
@@ -1409,7 +1409,7 @@ o ARM/STR71x (arch/arm/src/str71x/)
   Status:      Open
   Priority:    Medium -- Will be very high if you do SPI access from multiple threads.
 
-o ARM/LM3S6918 (arch/arm/src/lm3s/)
+o ARM/LM3S6918 (arch/arm/src/lm/)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
   Title:       I2C DRIVER
diff --git a/nuttx/arch/README.txt b/nuttx/arch/README.txt
index 67b99b255..14704aa76 100644
--- a/nuttx/arch/README.txt
+++ b/nuttx/arch/README.txt
@@ -170,12 +170,12 @@ arch/arm - ARM-based micro-controllers
         STATUS: This port has stalled because of development tool issues. Coding
         is complete on the basic port (timer, serial console, SPI).
 
-    arch/arm/include/lm3s and arch/arm/src/lm3s
-        These directories contain support for the Luminary LMS family, particularly
-        for the LM3S6918. The initial, release of this port was included in NuttX version
-        0.4.6. The current port includes timer, serial console, Ethernet, SSI, and microSD
-        support. There are working configurations the NuttX OS test, to run the NuttShell
-        (NSH), the NuttX networking test, and the uIP web server.
+    arch/arm/include/lm and arch/arm/src/lm
+        These directories contain support for the Luminary LM3S/4F family. The 
+        initial, release of this port was included in NuttX version 0.4.6.  The
+        current port includes timer, serial console, Ethernet, SSI, and microSD
+        support. There are working configurations the NuttX OS test, to run the
+        NuttShell (NSH), the NuttX networking test, and the uIP web server.
 
     arch/arm/include/lpc214x and arch/arm/src/lpc214x
         These directories provide support for NXP LPC214x family of
diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig
index 4fce8efbf..bc7634695 100644
--- a/nuttx/arch/arm/Kconfig
+++ b/nuttx/arch/arm/Kconfig
@@ -50,9 +50,8 @@ config ARCH_CHIP_KINETIS
 	---help---
 		Freescale Kinetis Architectures (ARM Cortex-M4)
 
-config ARCH_CHIP_LM3S
+config ARCH_CHIP_LM
 	bool "TI Stellaris"
-	select ARCH_CORTEXM3
 	select ARCH_HAVE_MPU
 	select ARCH_IRQPRIO
 	---help---
@@ -151,7 +150,7 @@ config ARCH_CHIP
 	default "dm320"		if ARCH_CHIP_DM320
 	default "imx"		if ARCH_CHIP_IMX
 	default "kinetis"	if ARCH_CHIP_KINETIS
-	default "lm3s"		if ARCH_CHIP_LM3S
+	default "lm"		if ARCH_CHIP_LM
 	default "lpc17xx"	if ARCH_CHIP_LPC17XX
 	default "lpc214x"	if ARCH_CHIP_LPC214X
 	default "lpc2378"	if ARCH_CHIP_LPC2378
@@ -274,8 +273,8 @@ endif
 if ARCH_CHIP_KINETIS
 source arch/arm/src/kinetis/Kconfig
 endif
-if ARCH_CHIP_LM3S
-source arch/arm/src/lm3s/Kconfig
+if ARCH_CHIP_LM
+source arch/arm/src/lm/Kconfig
 endif
 if ARCH_CHIP_LPC17XX
 source arch/arm/src/lpc17xx/Kconfig
diff --git a/nuttx/arch/arm/include/lm/chip.h b/nuttx/arch/arm/include/lm/chip.h
new file mode 100644
index 000000000..9eee51922
--- /dev/null
+++ b/nuttx/arch/arm/include/lm/chip.h
@@ -0,0 +1,123 @@
+/************************************************************************************
+ * arch/arm/include/lm/chip.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_LM_CHIP_H
+#define __ARCH_ARM_INCLUDE_LM_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM3S_ETHTS              /* No timestamp register */
+#  define LM3S_NSSI            2  /* Two SSI modules */
+#  define LM3S_NUARTS          2  /* Two UART modules */
+#  define LM3S_NI2C            2  /* Two I2C modules */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            0  /* No PWM generator modules */
+#  define LM3S_NQEI            0  /* No quadrature encoders */
+#  define LM3S_NPORTS          8  /* 8 Ports (GPIOA-H) 5-38 GPIOs */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+#  define LM3S_NTIMERS         3  /* Three general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM3S_ETHTS              /* No timestamp register */
+#  define LM3S_NSSI            1  /* One SSI module */
+#  define LM3S_NUARTS          2  /* Two UART modules */
+#  define LM3S_NI2C            1  /* Two I2C modules */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            1  /* One PWM generator module */
+#  define LM3S_NQEI            0  /* No quadrature encoders */
+#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM3S_ETHTS              /* No timestamp register */
+#  define LM3S_NSSI            1  /* One SSI module */
+#  define LM3S_NUARTS          3  /* Three UART modules */
+#  define LM3S_NI2C            2  /* Two I2C modules */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            3  /* Three PWM generator modules */
+#  define LM3S_NQEI            2  /* Two quadrature encoders */
+#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM3S_ETHTS              /* No timestamp register */
+#  define LM3S_NSSI            2  /* Two SSI modules */
+#  define LM3S_NUARTS          3  /* Three UART modules */
+#  define LM3S_NI2C            2  /* Two I2C modules */
+#  define LM3S_NADC            2  /* Two ADC module */
+#  define LM3S_CAN             2  /* Two CAN module */
+#  define LM3S_NPWM            4  /* Four PWM generator modules */
+#  define LM3S_NQEI            2  /* Two quadrature encoders */
+#  define LM3S_NPORTS          9  /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LM3S_NSSI            1  /* One SSI module */
+#  define LM3S_NUARTS          3  /* Two UART modules */
+#  define LM3S_NI2C            2  /* One I2C module */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            3  /* Three PWM generator modules */
+#  define LM3S_NQEI            2  /* Two quadrature encoders */
+#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 5-42 GPIOs */
+#  define LC3S_CANCONTROLLER   1  /* One CAN controller */
+#else
+#  error "Capabilities not specified for this LM3S chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_LM_CHIP_H */
diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h
new file mode 100644
index 000000000..a80517e40
--- /dev/null
+++ b/nuttx/arch/arm/include/lm/irq.h
@@ -0,0 +1,497 @@
+/************************************************************************************
+ * arch/arm/include/lm/irq.h
+ *
+ *   Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_LM_IRQ_H
+#define __ARCH_ARM_INCLUDE_LM_IRQ_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define LM3S_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+                                  /* Vector  0: Reset stack pointer value */
+                                  /* Vector  1: Reset (not handler as an IRQ) */
+#define LM3S_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define LM3S_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
+#define LM3S_IRQ_MEMFAULT     (4) /* Vector  4: Memory management (MPU) */
+#define LM3S_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
+#define LM3S_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
+#define LM3S_IRQ_SVCALL      (11) /* Vector 11: SVC call */
+#define LM3S_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
+                                  /* Vector 13: Reserved */
+#define LM3S_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
+#define LM3S_IRQ_SYSTICK     (15) /* Vector 15: System tick */
+
+/* External interrupts (vectors >= 16) */
+
+#define LM3S_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+
+#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+                                  /* Vector 25-29: Reserved */
+#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+                                  /* Vector 43: Reserved */
+#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM3S_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
+                                  /* Vector 49: Reserved */
+#  define LM3S_IRQ_SSI1      (50) /* Vector 50: SSI 1 */
+#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+                                  /* Vectors 54-57: Reserved */
+#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+                                  /* Vectors 60-70: Reserved */
+#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+                                  /* Vector 25: Reserved */
+#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+                                  /* Vectors 27-29: Reserved */
+#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+                                  /* Vector 43: Reserved */
+#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+                                  /* Vectors 48-57: Reserved */
+#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+                                  /* Vectors 59-70: Reserved */
+#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+                                  /* Vector 43: Reserved */
+#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+                                  /* Vector 48: Reserved */
+#  define LM3S_IRQ_UART2     (49) /* Vector 49: UART 2 */
+                                  /* Vector 50: Reserved */
+#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+                                  /* Vectors 55-57: Reserved */
+#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+                                  /* Vectors 60-70: Reserved */
+#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC0 Sequence 0 */
+#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC0 Sequence 1 */
+#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC0 Sequence 2 */
+#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC0 Sequence 3 */
+#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+#  define LM3S_IRQ_COMPARE2  (43) /* Vector 43: Analog Comparator 3 */
+#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM3S_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
+#  define LM3S_IRQ_UART2     (49) /* Vector 49: UART 2 */
+#  define LM3S_IRQ_SSI1      (50) /* Vector 50: SSI 1  */
+#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+#  define LM3S_IRQ_CAN0      (55) /* Vector 55: CAN 1 */
+#  define LM3S_IRQ_CAN1      (56) /* Vector 56: CAN 2 */
+                                  /* Vector 57: Reserved */
+#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+                                  /* Vector 59: Reserved */
+#  define LM3S_IRQ_USB       (60) /* Vector 60: USB */
+#  define LM3S_IRQ_PWM3      (61) /* Vector 61: PWM Generator 3 */
+#  define LM3S_IRQ_UDMASOFT  (62) /* Vector 62: uDMA Software */
+#  define LM3S_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
+#  define LM3S_IRQ_ADC1_0    (64) /* Vector 64: ADC1 Sequence 0 */
+#  define LM3S_IRQ_ADC1_1    (65) /* Vector 65: ADC1 Sequence 1 */
+#  define LM3S_IRQ_ADC1_2    (66) /* Vector 66: ADC1 Sequence 2 */
+#  define LM3S_IRQ_ADC1_3    (67) /* Vector 67: ADC1 Sequence 3 */
+#  define LM3S_IRQ_I2S0      (68) /* Vector 68: I2S0 */
+#  define LM3S_IRQ_EPI       (69) /* Vector 69: EPI */
+#  define LM3S_IRQ_GPIOJ     (70) /* Vector 70: GPIO Port J */
+                                  /* Vector 71: Reserved */
+#  define NR_IRQS            (71) /* (Really less because of reserved vectors) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+                                  /* Vector 42: Reserved */
+                                  /* Vector 43: Reserved */
+#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+                                  /* Vector 48: Reserved */
+                                  /* Vector 49: Reserved */
+                                  /* Vector 50: Reserved */
+#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+#  define LM3S_IRQ_CAN0      (54) /* Vector 55: CAN0 */
+                                  /* Vectors 56-57: Reserved */
+#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+                                  /* Vectors 60-70: Reserved */
+#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
+#else
+#  error "IRQ Numbers not specified for this LM3S chip"
+#endif
+
+/* GPIO IRQs -- Note that support for individual GPIO ports can
+ * be disabled in order to reduce the size of the implemenation.
+ */
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
+#  define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0)
+#  define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1)
+#  define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2)
+#  define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3)
+#  define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4)
+#  define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5)
+#  define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6)
+#  define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7)
+#  define _NGPIOAIRQS      (NR_IRQS + 8)
+#else
+#  define _NGPIOAIRQS      NR_IRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
+#  define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
+#  define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
+#  define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
+#  define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
+#  define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
+#  define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
+#  define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
+#  define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
+#  define _NGPIOBIRQS      (_NGPIOAIRQS + 8)
+#else
+#  define _NGPIOBIRQS      _NGPIOAIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
+#  define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
+#  define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
+#  define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
+#  define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
+#  define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
+#  define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
+#  define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
+#  define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
+#  define _NGPIOCIRQS      (_NGPIOBIRQS + 8)
+#else
+#  define _NGPIOCIRQS      _NGPIOBIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
+#  define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
+#  define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
+#  define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
+#  define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
+#  define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
+#  define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
+#  define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
+#  define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
+#  define _NGPIODIRQS      (_NGPIOCIRQS + 8)
+#else
+#  define _NGPIODIRQS      _NGPIOCIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
+#  define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
+#  define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
+#  define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
+#  define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
+#  define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
+#  define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
+#  define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
+#  define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
+#  define _NGPIOEIRQS      (_NGPIODIRQS + 8)
+#else
+#  define _NGPIOEIRQS      _NGPIODIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
+#  define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
+#  define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
+#  define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
+#  define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
+#  define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
+#  define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
+#  define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
+#  define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
+#  define _NGPIOFIRQS      (_NGPIOEIRQS + 8)
+#else
+#  define _NGPIOFIRQS      _NGPIOEIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
+#  define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
+#  define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
+#  define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
+#  define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
+#  define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
+#  define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
+#  define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
+#  define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
+#  define _NGPIOGIRQS      (_NGPIOFIRQS + 8)
+#else
+#  define _NGPIOGIRQS      _NGPIOFIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
+#  define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
+#  define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
+#  define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
+#  define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
+#  define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
+#  define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
+#  define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
+#  define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
+#  define _NGPIOHIRQS      (_NGPIOGIRQS + 8)
+#else
+#  define _NGPIOHIRQS      _NGPIOGIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
+#  define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
+#  define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
+#  define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
+#  define LM3S_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
+#  define LM3S_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
+#  define LM3S_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
+#  define LM3S_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
+#  define LM3S_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
+#  define _NGPIOJIRQS      (_NGPIOHIRQS + 8)
+#else
+#  define _NGPIOJIRQS      _NGPIOHIRQS
+#endif
+
+#define NR_GPIO_IRQS       (_NGPIOJIRQS - NR_IRQS)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: gpio_irqattach
+ *
+ * Description:
+ *   Attach the interrupt handler 'isr' to the GPIO IRQ 'irq'
+ *
+ ****************************************************************************/
+
+EXTERN int gpio_irqattach(int irq, xcpt_t isr);
+#define gpio_irqdetach(isr) gpio_irqattach(isr, NULL)
+
+/****************************************************************************
+ * Name: gpio_irqenable
+ *
+ * Description:
+ *   Enable the GPIO IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+EXTERN void gpio_irqenable(int irq);
+
+/****************************************************************************
+ * Name: gpio_irqdisable
+ *
+ * Description:
+ *   Disable the GPIO IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+EXTERN void gpio_irqdisable(int irq);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_LM_IRQ_H */
+
diff --git a/nuttx/arch/arm/include/lm3s/chip.h b/nuttx/arch/arm/include/lm3s/chip.h
deleted file mode 100644
index d7e98a461..000000000
--- a/nuttx/arch/arm/include/lm3s/chip.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/************************************************************************************
- * arch/arm/include/lm3s/chip.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_LM3S_CHIP_H
-#define __ARCH_ARM_INCLUDE_LM3S_CHIP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            2  /* Two SSI modules */
-#  define LM3S_NUARTS          2  /* Two UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            0  /* No PWM generator modules */
-#  define LM3S_NQEI            0  /* No quadrature encoders */
-#  define LM3S_NPORTS          8  /* 8 Ports (GPIOA-H) 5-38 GPIOs */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-#  define LM3S_NTIMERS         3  /* Three general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          2  /* Two UART modules */
-#  define LM3S_NI2C            1  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            1  /* One PWM generator module */
-#  define LM3S_NQEI            0  /* No quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          3  /* Three UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            3  /* Three PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            2  /* Two SSI modules */
-#  define LM3S_NUARTS          3  /* Three UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            2  /* Two ADC module */
-#  define LM3S_CAN             2  /* Two CAN module */
-#  define LM3S_NPWM            4  /* Four PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          9  /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          3  /* Two UART modules */
-#  define LM3S_NI2C            2  /* One I2C module */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            3  /* Three PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 5-42 GPIOs */
-#  define LC3S_CANCONTROLLER   1  /* One CAN controller */
-#else
-#  error "Capabilities not specified for this LM3S chip"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_INCLUDE_LM3S_CHIP_H */
diff --git a/nuttx/arch/arm/include/lm3s/irq.h b/nuttx/arch/arm/include/lm3s/irq.h
deleted file mode 100644
index 6ffc7dec0..000000000
--- a/nuttx/arch/arm/include/lm3s/irq.h
+++ /dev/null
@@ -1,497 +0,0 @@
-/************************************************************************************
- * arch/arm/include/lm3s/irq.h
- *
- *   Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_LM3S_IRQ_H
-#define __ARCH_ARM_INCLUDE_LM3S_IRQ_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/irq.h>
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
- * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
- */
-
-/* Processor Exceptions (vectors 0-15) */
-
-#define LM3S_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
-                                  /* Vector  0: Reset stack pointer value */
-                                  /* Vector  1: Reset (not handler as an IRQ) */
-#define LM3S_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define LM3S_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
-#define LM3S_IRQ_MEMFAULT     (4) /* Vector  4: Memory management (MPU) */
-#define LM3S_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
-#define LM3S_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
-#define LM3S_IRQ_SVCALL      (11) /* Vector 11: SVC call */
-#define LM3S_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
-                                  /* Vector 13: Reserved */
-#define LM3S_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
-#define LM3S_IRQ_SYSTICK     (15) /* Vector 15: System tick */
-
-/* External interrupts (vectors >= 16) */
-
-#define LM3S_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-                                  /* Vector 25-29: Reserved */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                  /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-#  define LM3S_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
-                                  /* Vector 49: Reserved */
-#  define LM3S_IRQ_SSI1      (50) /* Vector 50: SSI 1 */
-#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-                                  /* Vectors 54-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                  /* Vectors 60-70: Reserved */
-#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-                                  /* Vector 25: Reserved */
-#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-                                  /* Vectors 27-29: Reserved */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                  /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                  /* Vectors 48-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-                                  /* Vectors 59-70: Reserved */
-#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                  /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                  /* Vector 48: Reserved */
-#  define LM3S_IRQ_UART2     (49) /* Vector 49: UART 2 */
-                                  /* Vector 50: Reserved */
-#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-                                  /* Vectors 55-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                  /* Vectors 60-70: Reserved */
-#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC0 Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC0 Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC0 Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC0 Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-#  define LM3S_IRQ_COMPARE2  (43) /* Vector 43: Analog Comparator 3 */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-#  define LM3S_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
-#  define LM3S_IRQ_UART2     (49) /* Vector 49: UART 2 */
-#  define LM3S_IRQ_SSI1      (50) /* Vector 50: SSI 1  */
-#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-#  define LM3S_IRQ_CAN0      (55) /* Vector 55: CAN 1 */
-#  define LM3S_IRQ_CAN1      (56) /* Vector 56: CAN 2 */
-                                  /* Vector 57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-                                  /* Vector 59: Reserved */
-#  define LM3S_IRQ_USB       (60) /* Vector 60: USB */
-#  define LM3S_IRQ_PWM3      (61) /* Vector 61: PWM Generator 3 */
-#  define LM3S_IRQ_UDMASOFT  (62) /* Vector 62: uDMA Software */
-#  define LM3S_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
-#  define LM3S_IRQ_ADC1_0    (64) /* Vector 64: ADC1 Sequence 0 */
-#  define LM3S_IRQ_ADC1_1    (65) /* Vector 65: ADC1 Sequence 1 */
-#  define LM3S_IRQ_ADC1_2    (66) /* Vector 66: ADC1 Sequence 2 */
-#  define LM3S_IRQ_ADC1_3    (67) /* Vector 67: ADC1 Sequence 3 */
-#  define LM3S_IRQ_I2S0      (68) /* Vector 68: I2S0 */
-#  define LM3S_IRQ_EPI       (69) /* Vector 69: EPI */
-#  define LM3S_IRQ_GPIOJ     (70) /* Vector 70: GPIO Port J */
-                                  /* Vector 71: Reserved */
-#  define NR_IRQS            (71) /* (Really less because of reserved vectors) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-                                  /* Vector 42: Reserved */
-                                  /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                  /* Vector 48: Reserved */
-                                  /* Vector 49: Reserved */
-                                  /* Vector 50: Reserved */
-#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-#  define LM3S_IRQ_CAN0      (54) /* Vector 55: CAN0 */
-                                  /* Vectors 56-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                  /* Vectors 60-70: Reserved */
-#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
-#else
-#  error "IRQ Numbers not specified for this LM3S chip"
-#endif
-
-/* GPIO IRQs -- Note that support for individual GPIO ports can
- * be disabled in order to reduce the size of the implemenation.
- */
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
-#  define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0)
-#  define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1)
-#  define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2)
-#  define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3)
-#  define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4)
-#  define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5)
-#  define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6)
-#  define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7)
-#  define _NGPIOAIRQS      (NR_IRQS + 8)
-#else
-#  define _NGPIOAIRQS      NR_IRQS
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
-#  define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
-#  define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
-#  define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
-#  define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
-#  define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
-#  define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
-#  define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
-#  define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
-#  define _NGPIOBIRQS      (_NGPIOAIRQS + 8)
-#else
-#  define _NGPIOBIRQS      _NGPIOAIRQS
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
-#  define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
-#  define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
-#  define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
-#  define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
-#  define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
-#  define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
-#  define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
-#  define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
-#  define _NGPIOCIRQS      (_NGPIOBIRQS + 8)
-#else
-#  define _NGPIOCIRQS      _NGPIOBIRQS
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
-#  define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
-#  define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
-#  define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
-#  define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
-#  define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
-#  define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
-#  define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
-#  define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
-#  define _NGPIODIRQS      (_NGPIOCIRQS + 8)
-#else
-#  define _NGPIODIRQS      _NGPIOCIRQS
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
-#  define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
-#  define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
-#  define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
-#  define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
-#  define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
-#  define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
-#  define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
-#  define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
-#  define _NGPIOEIRQS      (_NGPIODIRQS + 8)
-#else
-#  define _NGPIOEIRQS      _NGPIODIRQS
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
-#  define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
-#  define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
-#  define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
-#  define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
-#  define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
-#  define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
-#  define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
-#  define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
-#  define _NGPIOFIRQS      (_NGPIOEIRQS + 8)
-#else
-#  define _NGPIOFIRQS      _NGPIOEIRQS
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
-#  define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
-#  define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
-#  define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
-#  define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
-#  define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
-#  define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
-#  define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
-#  define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
-#  define _NGPIOGIRQS      (_NGPIOFIRQS + 8)
-#else
-#  define _NGPIOGIRQS      _NGPIOFIRQS
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
-#  define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
-#  define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
-#  define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
-#  define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
-#  define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
-#  define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
-#  define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
-#  define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
-#  define _NGPIOHIRQS      (_NGPIOGIRQS + 8)
-#else
-#  define _NGPIOHIRQS      _NGPIOGIRQS
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
-#  define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
-#  define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
-#  define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
-#  define LM3S_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
-#  define LM3S_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
-#  define LM3S_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
-#  define LM3S_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
-#  define LM3S_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
-#  define _NGPIOJIRQS      (_NGPIOHIRQS + 8)
-#else
-#  define _NGPIOJIRQS      _NGPIOHIRQS
-#endif
-
-#define NR_GPIO_IRQS       (_NGPIOJIRQS - NR_IRQS)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/****************************************************************************
- * Name: gpio_irqattach
- *
- * Description:
- *   Attach the interrupt handler 'isr' to the GPIO IRQ 'irq'
- *
- ****************************************************************************/
-
-EXTERN int gpio_irqattach(int irq, xcpt_t isr);
-#define gpio_irqdetach(isr) gpio_irqattach(isr, NULL)
-
-/****************************************************************************
- * Name: gpio_irqenable
- *
- * Description:
- *   Enable the GPIO IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-EXTERN void gpio_irqenable(int irq);
-
-/****************************************************************************
- * Name: gpio_irqdisable
- *
- * Description:
- *   Disable the GPIO IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-EXTERN void gpio_irqdisable(int irq);
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif /* __ARCH_ARM_INCLUDE_LM3S_IRQ_H */
-
diff --git a/nuttx/arch/arm/src/lm/Kconfig b/nuttx/arch/arm/src/lm/Kconfig
new file mode 100644
index 000000000..74d1712f3
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/Kconfig
@@ -0,0 +1,217 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+comment "Stellaris Configuration Options"
+
+choice
+	prompt "Stellaris Chip Selection"
+	default ARCH_CHIP_LM3S6965
+	depends on ARCH_CHIP_LM
+
+config ARCH_CHIP_LM3S6918
+	bool "LM3S6918"
+	select ARCH_CORTEXM3
+	select ARCH_CHIP_LM3S
+	select LM3S_HAVE_SSI1
+
+config ARCH_CHIP_LM3S9B96
+	bool "LM3S9B96"
+	select ARCH_CORTEXM3
+	select ARCH_CHIP_LM3S
+
+config ARCH_CHIP_LM3S6432
+	bool "LM3S6432"
+	select ARCH_CORTEXM3
+	select ARCH_CHIP_LM3S
+
+config ARCH_CHIP_LM3S6965
+	bool "LM3S6965"
+	select ARCH_CORTEXM3
+	select ARCH_CHIP_LM3S
+
+config ARCH_CHIP_LM3S8962
+	bool "LM3S8962"
+	select ARCH_CORTEXM3
+	select ARCH_CHIP_LM3S
+
+endchoice
+
+# Chip families
+
+config ARCH_CHIP_LM3S
+	bool
+
+config ARCH_CHIP_LM4F
+	bool
+
+config LM3S_HAVE_SSI1
+	bool
+
+config LM3S_REVA2
+	bool "Rev A2"
+	default n
+	---help---
+		Some early silicon returned an increase LDO voltage or 2.75V to work
+		around a PLL bug
+
+config LM3S_DFU
+	bool "DFU"
+	default y
+
+menu "Select LM3S Peripheral Support"
+
+config LM3S_UART0
+	bool "UART0"
+	select ARCH_HAVE_UART0
+	default n
+
+config LM3S_UART1
+	bool "UART1"
+	select ARCH_HAVE_UART1
+	default n
+
+config SSI0_DISABLE
+	bool "Disable SSI0"
+	default y
+
+config SSI1_DISABLE
+	bool "Disable SSI1"
+	default y
+
+config LM3S_UART2
+	bool "UART2"
+	select ARCH_HAVE_UART2
+	default n
+
+config LM3S_ETHERNET
+	bool "LM3S Ethernet"
+	default n
+	---help---
+		This must be set (along with NET) to build the LM3S Ethernet driver.
+
+endmenu
+
+menu "Disable GPIO Interrupts"
+
+config LM3S_DISABLE_GPIOA_IRQS
+	bool "Disable GPIOA IRQs"
+	default n
+
+config LM3S_DISABLE_GPIOB_IRQS
+	bool "Disable GPIOB IRQs"
+	default n
+
+config LM3S_DISABLE_GPIOC_IRQS
+	bool "Disable GPIOC IRQs"
+	default n
+
+config LM3S_DISABLE_GPIOD_IRQS
+	bool "Disable GPIOD IRQs"
+	default n
+
+config LM3S_DISABLE_GPIOE_IRQS
+	bool "Disable GPIOE IRQs"
+	default n
+
+config LM3S_DISABLE_GPIOF_IRQS
+	bool "Disable GPIOF IRQs"
+	default n
+
+config LM3S_DISABLE_GPIOG_IRQS
+	bool "Disable GPIOG IRQs"
+	default n
+
+config LM3S_DISABLE_GPIOH_IRQS
+	bool "Disable GPIOH IRQs"
+	default n
+
+config LM3S_DISABLE_GPIOJ_IRQS
+	bool "Disable GPIOJ IRQs"
+	default n
+
+endmenu
+
+if LM3S_ETHERNET
+menu "LM3S Ethernet Configuration"
+
+config LM3S_ETHLEDS
+	bool "Ethernet LEDs"
+	default n
+	---help---
+	Enable to use Ethernet LEDs on the board.
+
+config LM3S_BOARDMAC
+	bool "Board MAC"
+	default n
+	---help---
+		If the board-specific logic can provide a MAC address (via
+		lm3s_ethernetmac()), then this should be selected.
+
+config LM3S_ETHHDUPLEX
+	bool "Force Half Duplex"
+	default n
+	---help---
+		Set to force half duplex operation
+
+config LM3S_ETHNOAUTOCRC
+	bool "Disable auto-CRC"
+	default n
+	---help---
+		Set to suppress auto-CRC generation
+
+config LM3S_ETHNOPAD
+	bool "Disable Tx Padding"
+	default n
+	---help---
+		Set to suppress Tx padding
+
+config LM3S_MULTICAST
+	bool "Enable Multicast"
+	default n
+	---help---
+		Set to enable multicast frames
+
+config LM3S_PROMISCUOUS
+	bool "Enable Promiscuous Mode"
+	default n
+	---help---
+		Set to enable promiscuous mode
+
+config LM3S_TIMESTAMP
+	bool "Enable Timestamping"
+	default n
+
+config LM3S_BADCRC
+	bool "Enable Bad CRC Rejection"
+	default n
+	---help---
+		Set to enable bad CRC rejection.
+
+config M3S_DUMPPACKET
+	bool "Dump Packets"
+	default n
+	---help---
+		Dump each packet received/sent to the console.
+
+endmenu
+endif
+
+if !SSI0_DISABLE || !SSI1_DISABLE
+menu "LM3S SSI Configuration"
+
+config SSI_POLLWAIT
+	bool "Poll Wait (No-Interrupt) Mode"
+	default y
+
+config SSI_TXLIMIT
+	int "Tx Limit"
+	default 4
+	---help---
+		Default of 4 assumes half of the 8 entry FIFO
+
+endmenu
+endif
+
+
diff --git a/nuttx/arch/arm/src/lm/Make.defs b/nuttx/arch/arm/src/lm/Make.defs
new file mode 100644
index 000000000..aacbb1c83
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/Make.defs
@@ -0,0 +1,64 @@
+############################################################################
+# arch/arm/src/lm/Make.defs
+#
+#   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC	= lm3s_vectors.S
+
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
+			  vfork.S
+CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
+			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
+			  up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \
+			  up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
+			  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
+			  up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
+			  up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \
+			  up_vfork.c
+
+ifeq ($(CONFIG_ARCH_MEMCPY),y)
+CMN_ASRCS	+= up_memcpy.S
+endif
+
+ifeq ($(CONFIG_ELF),y)
+CMN_CSRCS += up_elf.c
+endif
+
+CHIP_ASRCS	= 
+CHIP_CSRCS	= lm3s_start.c lm3s_syscontrol.c lm3s_irq.c \
+			  lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \
+			  lm3s_serial.c lm3s_ssi.c lm3s_dumpgpio.c
+
+ifdef CONFIG_NET
+CHIP_CSRCS	+= lm3s_ethernet.c
+endif
diff --git a/nuttx/arch/arm/src/lm/chip.h b/nuttx/arch/arm/src/lm/chip.h
new file mode 100644
index 000000000..5857b3094
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip.h
@@ -0,0 +1,83 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip.h
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_H
+#define __ARCH_ARM_SRC_LM_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/lm/chip.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Then get all of the register definitions */
+
+#include "chip/lm_memorymap.h"    /* Memory map */
+#include "chip/lm3s_syscontrol.h" /* System control module */
+#include "chip/lm3s_gpio.h"       /* GPIO modules */
+#include "chip/lm3s_uart.h"       /* UART modules */
+#include "chip/lm3s_i2c.h"        /* I2C modules */
+#include "chip/lm3s_ssi.h"        /* SSI modules */
+#include "chip/lm3s_ethernet.h"   /* Ethernet MAC and PHY */
+#include "chip/lm3s_flash.h"      /* FLASH */
+
+/* The LM3S69xx only supports 8 priority levels.  The hardware priority mechanism
+ * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
+ * the Stellaris family), so any prioritization must be performed in those bits.
+ * The default priority level is set to the middle value
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN     0xe0 /* All bits set in minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm/chip/lm3s_epi.h
new file mode 100644
index 000000000..82fc94f4c
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_epi.h
@@ -0,0 +1,113 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_epi.h
+ *
+ *   Copyright (C) 2009-2013 Max Neklyudov. All rights reserved.
+ *   Author: Max Neklyudov <macscomp@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* External Peripheral Interface Register Offsets ***********************************/
+
+#define LM3S_EPI_CFG_OFFSET           0x000
+#define LM3S_EPI_SDRAMCFG_OFFSET      0x010
+#define LM3S_EPI_ADDRMAP_OFFSET       0x01C
+#define LM3S_EPI_STAT_OFFSET          0x060
+#define LM3S_EPI_BAUD_OFFSET          0x004
+
+/* External Peripheral Interface Register Addresses *********************************/
+
+#define LM3S_EPI0_CFG                 (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
+#define LM3S_EPI0_SDRAMCFG            (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
+#define LM3S_EPI0_ADDRMAP             (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
+#define LM3S_EPI0_STAT                (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
+#define LM3S_EPI0_BAUD                (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
+
+/* External Peripheral Interface Register Bit Definitions ***************************/
+
+/* EPI Configuration (EPICFG), offset 0x000 */
+
+#define EPI_CFG_MODE_SHIFT            0         /* Bits 3-0: Mode Select */
+#define EPI_CFG_MODE_MASK             (0x1f << EPI_CFG_MODE_SHIFT)
+#  define EPI_CFG_MODE_SDRAM          (0x11 << EPI_CFG_MODE_SHIFT)  /* SDRAM + BLKEN */
+
+/* EPI Address Map (EPIADDRMAP), offset 0x01C */
+
+#define EPI_ADDRMAP_ERADR_SHIFT       0       /* Bits 1-0: External RAM Address */
+#define EPI_ADDRMAP_ERADR_MASK        (0x3 << EPI_ADDRMAP_ERADR_SHIFT)
+#  define EPI_ADDRMAP_ERADR_6         (0x1 << EPI_ADDRMAP_ERADR_SHIFT)
+#  define EPI_ADDRMAP_ERADR_8         (0x2 << EPI_ADDRMAP_ERADR_SHIFT)
+#define EPI_ADDRMAP_ERSZ_SHIFT        2       /* Bits 3-2: External RAM Size */
+#define EPI_ADDRMAP_ERSZ_MASK         (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_256B       (0x0 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_64KB       (0x1 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_16MB       (0x2 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_512MB      (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
+
+/* EPI Status (EPISTAT), offset 0x060 */
+
+#define EPI_STAT_INITSEQ_SHIFT        6       /* Bits 6: Initialization Sequence */
+#define EPI_STAT_INITSEQ_MASK         (0x1 << EPI_STAT_INITSEQ_SHIFT)
+
+/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */
+
+#define EPI_SDRAMCFG_SIZE_SHIFT       0       /* Bits 1-0: Size of SDRAM */
+#define EPI_SDRAMCFG_SIZE_MASK        (3 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_8MB       (0x0 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_16MB      (0x1 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_32MB      (0x2 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_64MB      (0x3 << EPI_SDRAMCFG_SIZE_SHIFT)
+#define EPI_SDRAMCFG_RFSH_SHIFT       16      /* Bits 26-16: Refresh Counter */
+#define EPI_SDRAMCFG_RFSH_MASK        (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT)
+#  define EPI_SDRAMCFG_RFSH(n)        ((n) << EPI_SDRAMCFG_RFSH_SHIFT)
+#define EPI_SDRAMCFG_FREQ_SHIFT       30      /* EPI Frequency Range */
+#define EPI_SDRAMCFG_FREQ_MASK        (3 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_0_15MHZ   (0x0 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_15_30MHZ  (0x1 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_30_50MHZ  (0x2 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT)
+
+/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */
+
+#define EPI_BAUD_COUNT0_SHIFT         0
+#define EPI_BAUD_COUNT0_MASK          (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
+#  define EPI_BAUD_COUNT0(n)          ((n) << EPI_BAUD_COUNT0_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h
new file mode 100644
index 000000000..512e96221
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h
@@ -0,0 +1,203 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_ethernet.h
+ *
+ *   Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/net/mii.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Ethernet Controller Register Offsets *********************************************/
+
+/* Ethernet MAC Register Offsets */
+
+#define LM3S_MAC_RIS_OFFSET   0x000 /* Ethernet MAC Raw Interrupt Status */
+#define LM3S_MAC_IACK_OFFSET  0x000 /* Ethernet MAC Acknowledge */
+#define LM3S_MAC_IM_OFFSET    0x004 /* Ethernet MAC Interrupt Mask */
+#define LM3S_MAC_RCTL_OFFSET  0x008 /* Ethernet MAC Receive Control */
+#define LM3S_MAC_TCTL_OFFSET  0x00c /* Ethernet MAC Transmit Control */
+#define LM3S_MAC_DATA_OFFSET  0x010 /* Ethernet MAC Data */
+#define LM3S_MAC_IA0_OFFSET   0x014 /* Ethernet MAC Individual Address 0 */
+#define LM3S_MAC_IA1_OFFSET   0x018 /* Ethernet MAC Individual Address 1 */
+#define LM3S_MAC_THR_OFFSET   0x01c /* Ethernet MAC Threshold */
+#define LM3S_MAC_MCTL_OFFSET  0x020 /* Ethernet MAC Management Control */
+#define LM3S_MAC_MDV_OFFSET   0x024 /* Ethernet MAC Management Divider */
+#define LM3S_MAC_MTXD_OFFSET  0x02c /* Ethernet MAC Management Transmit Data */
+#define LM3S_MAC_MRXD_OFFSET  0x030 /* Ethernet MAC Management Receive Data */
+#define LM3S_MAC_NP_OFFSET    0x034 /* Ethernet MAC Number of Packets */
+#define LM3S_MAC_TR_OFFSET    0x038 /* Ethernet MAC Transmission Request */
+#ifdef LM3S_ETHTS
+#  define LM3S_MAC_TS_OFFSET  0x03c /* Ethernet MAC Time Stamp Configuration */
+#endif
+
+/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
+
+/* Ethernet Controller Register Addresses *******************************************/
+
+#define LM3S_MAC_RIS          (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
+#define LM3S_MAC_IACK         (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
+#define LM3S_MAC_IM           (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
+#define LM3S_MAC_RCTL         (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
+#define LM3S_MAC_TCTL         (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
+#define LM3S_MAC_DATA         (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
+#define LM3S_MAC_IA0          (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
+#define LM3S_MAC_IA1          (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
+#define LM3S_MAC_THR          (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
+#define LM3S_MAC_MCTL         (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
+#define LM3S_MAC_MDV          (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
+#define LM3S_MAC_MTXD         (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
+#define LM3S_MAC_MRXD         (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
+#define LM3S_MAC_NP           (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
+#define LM3S_MAC_TR           (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
+#ifdef LM3S_ETHTS
+#  define LM3S_MAC_TS         (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
+#endif
+
+/* Memory Mapped MII Management Registers */
+
+#define MAC_MII_MCR           (LM3S_ETHCON_BASE + MII_MCR)
+#define MAC_MII_MSR           (LM3S_ETHCON_BASE + MII_MSR)
+#define MAC_MII_PHYID1        (LM3S_ETHCON_BASE + MII_PHYID1)
+#define MAC_MII_PHYID2        (LM3S_ETHCON_BASE + MII_PHYID2)
+#define MAC_MII_ADVERTISE     (LM3S_ETHCON_BASE + MII_ADVERTISE)
+#define MAC_MII_LPA           (LM3S_ETHCON_BASE + MII_LPA)
+#define MAC_MII_EXPANSION     (LM3S_ETHCON_BASE + MII_EXPANSION)
+#define MAC_MII_VSPECIFIC     (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
+#define MAC_MII_INTCS         (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
+#define MAC_MII_DIAGNOSTIC    (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
+#define MAC_MII_XCVRCONTROL   (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
+#define MAC_MII_LEDCONFIG     (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
+#define MAC_MII_MDICONTROL    (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
+
+/* Ethernet Controller Register Bit Definitions *************************************/
+
+/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
+
+#define MAC_RIS_RXINT         (1 << 0)  /* Bit 0:  Packet Received */
+#define MAC_RIS_TXER          (1 << 1)  /* Bit 1:  Transmit Error */
+#define MAC_RIS_TXEMP         (1 << 2)  /* Bit 2:  Transmit FIFO Empty */
+#define MAC_RIS_FOV           (1 << 3)  /* Bit 3:  FIFO Overrun */
+#define MAC_RIS_RXER          (1 << 4)  /* Bit 4:  Receive Error */
+#define MAC_RIS_MDINT         (1 << 5)  /* Bit 5:  MII Transaction Complete */
+#define MAC_RIS_PHYINT        (1 << 6)  /* Bit 6:  PHY Interrupt */
+
+#define MAC_IACK_RXINT        (1 << 0)  /* Bit 0:  Clear Packet Received */
+#define MAC_IACK_TXER         (1 << 1)  /* Bit 1:  Clear Transmit Error */
+#define MAC_IACK_TXEMP        (1 << 2)  /* Bit 2:  Clear Transmit FIFO Empty */
+#define MAC_IACK_FOV          (1 << 3)  /* Bit 3:  Clear FIFO Overrun */
+#define MAC_IACK_RXER         (1 << 4)  /* Bit 4:  Clear Receive Error */
+#define MAC_IACK_MDINT        (1 << 5)  /* Bit 5:  Clear MII Transaction Complete */
+#define MAC_IACK_PHYINT       (1 << 6)  /* Bit 6:  Clear PHY Interrupt */
+
+/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
+
+#define MAC_IM_RXINTM         (1 << 0)  /* Bit 0:  Mask Packet Received */
+#define MAC_IM_TXERM          (1 << 1)  /* Bit 1:  Mask Transmit Error */
+#define MAC_IM_TXEMPM         (1 << 2)  /* Bit 2:  Mask Transmit FIFO Empty */
+#define MAC_IM_FOVM           (1 << 3)  /* Bit 3:  Mask FIFO Overrun */
+#define MAC_IM_RXERM          (1 << 4)  /* Bit 4:  Mask Receive Error */
+#define MAC_IM_MDINTM         (1 << 5)  /* Bit 5:  Mask MII Transaction Complete */
+#define MAC_IM_PHYINTM        (1 << 6)  /* Bit 6:  Mask PHY Interrupt */
+#define MAC_IM_ALLINTS        0x7f
+
+/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
+
+#define MAC_RCTL_RXEN         (1 << 0)  /* Bit 0:  Enable Receiver */
+#define MAC_RCTL_AMUL         (1 << 1)  /* Bit 1:  Enable Multicast Frames */
+#define MAC_RCTL_PRMS         (1 << 2)  /* Bit 2:  Enable Promiscuous Mode */
+#define MAC_RCTL_BADCRC       (1 << 3)  /* Bit 3:  Enable Reject Bad CRC */
+#define MAC_RCTL_RSTFIFO      (1 << 4)  /* Bit 4:  Clear Receive FIFO */
+
+/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
+
+#define MAC_TCTL_TXEN         (1 << 0)  /* Bit 0:  Enable Transmitter */
+#define MAC_TCTL_PADEN        (1 << 1)  /* Bit 1:  Enable Packet Padding */
+#define MAC_TCTL_CRC          (1 << 2)  /* Bit 2:  Enable CRC Generation */
+#define MAC_TCTL_DUPLEX       (1 << 4)  /* Bit 4:  Enable Duplex Mode */
+
+/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
+
+#define MAC_THR_MASK          0x3f      /* Bits 5-0: Threshold Value */
+
+/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
+
+#define MAC_MCTL_START        (1 << 0)  /* Bit 0:  MII Register Transaction Enable */
+#define MAC_MCTL_WRITE        (1 << 1)  /* Bit 1:  MII Register Transaction Type */
+#define MAC_MCTL_REGADR_SHIFT 3         /* Bits 7-3: MII Register Address */
+#define MAC_MCTL_REGADR_MASK  (0x1f << MAC_MCTL_REGADR_SHIFT)
+
+/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
+
+#define MAC_MDV_MASK          0xff      /* Bits 7-0: Clock Divider */
+
+/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
+
+#define MAC_MTXD_MASK         0xffff    /* Bits 15-0: MII Register Transmit Data */
+
+/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
+
+#define MAC_MTRD_MASK         0xffff    /* Bits 15-0: MII Register Receive Data */
+
+/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
+
+#define MAC_NP_MASK           0x3f      /* Bits 5-0: Number of Packets in Receive FIFO */
+
+/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
+
+#define MAC_TR_NEWTX          (1 << 0)  /* Bit 0:  New Transmission */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm/chip/lm3s_flash.h
new file mode 100644
index 000000000..2f6dc78fa
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_flash.h
@@ -0,0 +1,128 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_flash.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* FLASH register offsets ***********************************************************/
+
+/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
+ * control base address of LM3S_FLASHCON_BASE.
+ */
+
+#define LM3S_FLASH_FMA_OFFSET       0x000 /* Flash memory address */
+#define LM3S_FLASH_FMD_OFFSET       0x004 /* Flash memory data */
+#define LM3S_FLASH_FMC_OFFSET       0x008 /* Flash memory control */
+#define LM3S_FLASH_FCRIS_OFFSET     0x00c /* Flash controller raw interrupt status */
+#define LM3S_FLASH_FCIM_OFFSET      0x010 /* Flash controller interrupt mask */
+#define LM3S_FLASH_FCMISC_OFFSET    0x014 /* Flash controller masked interrupt status and clear */ */
+
+/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
+ * System Control base address of LM3S_SYSCON_BASE
+ */
+
+#define LM3S_FLASH_FMPRE_OFFSET     0x130 /* Flash memory protection read enable */
+#define LM3S_FLASH_FMPPE_OFFSET     0x134 /* Flash memory protection program enable */
+#define LM3S_FLASH_USECRL_OFFSET    0x140 /* USec Reload */
+#define LM3S_FLASH_USERDBG_OFFSET   0x1d0 /* User Debug */
+#define LM3S_FLASH_USERREG0_OFFSET  0x1e0 /* User Register 0 */
+#define LM3S_FLASH_USERREG1_OFFSET  0x1e4 /* User Register 1 */
+#define LM3S_FLASH_FMPRE0_OFFSET    0x200 /* Flash Memory Protection Read Enable 0 */
+#define LM3S_FLASH_FMPRE1_OFFSET    0x204 /* Flash Memory Protection Read Enable 1 */
+#define LM3S_FLASH_FMPRE2_OFFSET    0x208 /* Flash Memory Protection Read Enable 2 */
+#define LM3S_FLASH_FMPRE3_OFFSET    0x20c /* Flash Memory Protection Read Enable 3 */
+#define LM3S_FLASH_FMPPE0_OFFSET    0x400 /* Flash Memory Protection Program Enable 0 */
+#define LM3S_FLASH_FMPPE1_OFFSET    0x404 /* Flash Memory Protection Program Enable 1 */
+#define LM3S_FLASH_FMPPE2_OFFSET    0x408 /* Flash Memory Protection Program Enable 2 */
+#define LM3S_FLASH_FMPPE3_OFFSET    0x40c /*  Flash Memory Protection Program Enable 3 */
+
+/* FLASH register addresses *********************************************************/
+
+/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
+ * control base address of LM3S_FLASHCON_BASE.
+ */
+
+#define LM3S_FLASH_FMA              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
+#define LM3S_FLASH_FMD              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
+#define LM3S_FLASH_FMC              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
+#define LM3S_FLASH_FCRIS            (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
+#define LM3S_FLASH_FCIM             (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
+#define LM3S_FLASH_FCMISC           (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
+
+/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
+ * System Control base address of LM3S_SYSCON_BASE
+ */
+
+#define LM3S_FLASH_FMPRE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
+#define LM3S_FLASH_FMPPE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
+#define LM3S_FLASH_USECRL           (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
+#define LM3S_FLASH_USERDBG          (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
+#define LM3S_FLASH_USERREG0         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
+#define LM3S_FLASH_USERREG1         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
+#define LM3S_FLASH_FMPRE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
+#define LM3S_FLASH_FMPRE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
+#define LM3S_FLASH_FMPRE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
+#define LM3S_FLASH_FMPRE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
+#define LM3S_FLASH_FMPPE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
+#define LM3S_FLASH_FMPPE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
+#define LM3S_FLASH_FMPPE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
+#define LM3S_FLASH_FMPPE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
+
+/* FLASH register bit defitiions ****************************************************/
+/* To be provided */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h
new file mode 100644
index 000000000..2c199dae9
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h
@@ -0,0 +1,395 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_gpio.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* GPIO Register Offsets ************************************************************/
+
+#define LM3S_GPIO_DATA_OFFSET         0x000 /* GPIO Data */
+#define LM3S_GPIO_DIR_OFFSET          0x400 /* GPIO Direction */
+#define LM3S_GPIO_IS_OFFSET           0x404 /* GPIO Interrupt Sense */
+#define LM3S_GPIO_IBE_OFFSET          0x408 /* GPIO Interrupt Both Edges */
+#define LM3S_GPIO_IEV_OFFSET          0x40c /* GPIO Interrupt Event */
+#define LM3S_GPIO_IM_OFFSET           0x410 /* GPIO Interrupt Mask */
+#define LM3S_GPIO_RIS_OFFSET          0x414 /* GPIO Raw Interrupt Status */
+#define LM3S_GPIO_MIS_OFFSET          0x418 /* GPIO Masked Interrupt Status */
+#define LM3S_GPIO_ICR_OFFSET          0x41c /* GPIO Interrupt Clear */
+#define LM3S_GPIO_AFSEL_OFFSET        0x420 /* GPIO Alternate Function */
+#define LM3S_GPIO_DR2R_OFFSET         0x500 /* Select GPIO 2-mA Drive Select */
+#define LM3S_GPIO_DR4R_OFFSET         0x504 /* GPIO 4-mA Drive Select */
+#define LM3S_GPIO_DR8R_OFFSET         0x508 /* GPIO 8-mA Drive Select */
+#define LM3S_GPIO_ODR_OFFSET          0x50c /* GPIO Open Drain Select */
+#define LM3S_GPIO_PUR_OFFSET          0x510 /* GPIO Pull-Up Select */
+#define LM3S_GPIO_PDR_OFFSET          0x514 /* GPIO Pull-Down Select */
+#define LM3S_GPIO_SLR_OFFSET          0x518 /* GPIO Slew Rate Control Select */
+#define LM3S_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
+#define LM3S_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
+#define LM3S_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
+#define LM3S_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
+#define LM3S_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
+#define LM3S_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
+#define LM3S_GPIO_PERIPHID7_OFFSET    0xfdc /* GPIO Peripheral Identification 7 */
+#define LM3S_GPIO_PERIPHID0_OFFSET    0xfe0 /* GPIO Peripheral Identification 0 */
+#define LM3S_GPIO_PERIPHID1_OFFSET    0xfe4 /* GPIO Peripheral Identification 1 */
+#define LM3S_GPIO_PERIPHID2_OFFSET    0xfe8 /* GPIO Peripheral Identification 2 */
+#define LM3S_GPIO_PERIPHID3_OFFSET    0xfec /* GPIO Peripheral Identification 3 */
+#define LM3S_GPIO_PCELLID0_OFFSET     0xff0 /* GPIO PrimeCell Identification 0 */
+#define LM3S_GPIO_PCELLID1_OFFSET     0xff4 /* GPIO PrimeCell Identification 1 */
+#define LM3S_GPIO_PCELLID2_OFFSET     0xff8 /* GPIO PrimeCell Identification 2 */
+#define LM3S_GPIO_PCELLID3_OFFSET     0xffc /* GPIO PrimeCell Identification 3*/
+
+/* GPIO Register Addresses **********************************************************/
+
+#define LM3S_GPIOA_DATA               (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOA_DIR                (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOA_IS                 (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOA_IBE                (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOA_IEV                (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOA_IM                 (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOA_RIS                (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOA_MIS                (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOA_ICR                (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOA_AFSEL              (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOA_DR2R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOA_DR4R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOA_DR8R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOA_ODR                (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOA_PUR                (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOA_PDR                (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOA_SLR                (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOA_DEN                (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOA_LOCK               (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOA_CR                 (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOA_PERIPHID4          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOA_PERIPHID5          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOA_PERIPHID6          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOA_PERIPHID7          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOA_PERIPHID0          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOA_PERIPHID1          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOA_PERIPHID2          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOA_PERIPHID3          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOA_PCELLID0           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOA_PCELLID1           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOA_PCELLID2           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOA_PCELLID3           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOB_DATA               (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOB_DIR                (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOB_IS                 (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOB_IBE                (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOB_IEV                (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOB_IM                 (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOB_RIS                (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOB_MIS                (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOB_ICR                (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOB_AFSEL              (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOB_DR2R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOB_DR4R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOB_DR8R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOB_ODR                (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOB_PUR                (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOB_PDR                (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOB_SLR                (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOB_DEN                (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOB_LOCK               (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOB_CR                 (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOB_PERIPHID4          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOB_PERIPHID5          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOB_PERIPHID6          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOB_PERIPHID7          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOB_PERIPHID0          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOB_PERIPHID1          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOB_PERIPHID2          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOB_PERIPHID3          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOB_PCELLID0           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOB_PCELLID1           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOB_PCELLID2           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOB_PCELLID3           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOC_DATA               (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOC_DIR                (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOC_IS                 (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOC_IBE                (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOC_IEV                (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOC_IM                 (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOC_RIS                (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOC_MIS                (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOC_ICR                (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOC_AFSEL              (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOC_DR2R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOC_DR4R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOC_DR8R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOC_ODR                (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOC_PUR                (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOC_PDR                (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOC_SLR                (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOC_DEN                (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOC_LOCK               (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOC_CR                 (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOC_PERIPHID4          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOC_PERIPHID5          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOC_PERIPHID6          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOC_PERIPHID7          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOC_PERIPHID0          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOC_PERIPHID1          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOC_PERIPHID2          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOC_PERIPHID3          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOC_PCELLID0           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOC_PCELLID1           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOC_PCELLID2           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOC_PCELLID3           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOD_DATA               (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOD_DIR                (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOD_IS                 (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOD_IBE                (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOD_IEV                (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOD_IM                 (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOD_RIS                (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOD_MIS                (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOD_ICR                (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOD_AFSEL              (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOD_DR2R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOD_DR4R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOD_DR8R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOD_ODR                (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOD_PUR                (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOD_PDR                (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOD_SLR                (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOD_DEN                (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOD_LOCK               (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOD_CR                 (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOD_PERIPHID4          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOD_PERIPHID5          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOD_PERIPHID6          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOD_PERIPHID7          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOD_PERIPHID0          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOD_PERIPHID1          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOD_PERIPHID2          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOD_PERIPHID3          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOD_PCELLID0           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOD_PCELLID1           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOD_PCELLID2           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOD_PCELLID3           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOE_DATA               (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOE_DIR                (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOE_IS                 (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOE_IBE                (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOE_IEV                (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOE_IM                 (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOE_RIS                (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOE_MIS                (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOE_ICR                (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOE_AFSEL              (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOE_DR2R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOE_DR4R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOE_DR8R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOE_ODR                (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOE_PUR                (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOE_PDR                (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOE_SLR                (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOE_DEN                (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOE_LOCK               (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOE_CR                 (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOE_PERIPHID4          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOE_PERIPHID5          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOE_PERIPHID6          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOE_PERIPHID7          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOE_PERIPHID0          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOE_PERIPHID1          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOE_PERIPHID2          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOE_PERIPHID3          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOE_PCELLID0           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOE_PCELLID1           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOE_PCELLID2           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOE_PCELLID3           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOF_DATA               (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOF_DIR                (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOF_IS                 (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOF_IBE                (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOF_IEV                (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOF_IM                 (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOF_RIS                (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOF_MIS                (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOF_ICR                (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOF_AFSEL              (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOF_DR2R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOF_DR4R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOF_DR8R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOF_ODR                (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOF_PUR                (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOF_PDR                (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOF_SLR                (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOF_DEN                (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOF_LOCK               (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOF_CR                 (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOF_PERIPHID4          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOF_PERIPHID5          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOF_PERIPHID6          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOF_PERIPHID7          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOF_PERIPHID0          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOF_PERIPHID1          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOF_PERIPHID2          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOF_PERIPHID3          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOF_PCELLID0           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOF_PCELLID1           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOF_PCELLID2           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOF_PCELLID3           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOG_DATA               (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOG_DIR                (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOG_IS                 (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOG_IBE                (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOG_IEV                (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOG_IM                 (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOG_RIS                (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOG_MIS                (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOG_ICR                (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOG_AFSEL              (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOG_DR2R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOG_DR4R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOG_DR8R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOG_ODR                (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOG_PUR                (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOG_PDR                (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOG_SLR                (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOG_DEN                (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOG_LOCK               (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOG_CR                 (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOG_PERIPHID4          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOG_PERIPHID5          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOG_PERIPHID6          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOG_PERIPHID7          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOG_PERIPHID0          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOG_PERIPHID1          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOG_PERIPHID2          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOG_PERIPHID3          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOG_PCELLID0           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOG_PCELLID1           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOG_PCELLID2           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOG_PCELLID3           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOH_DATA               (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOH_DIR                (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOH_IS                 (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOH_IBE                (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOH_IEV                (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOH_IM                 (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOH_RIS                (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOH_MIS                (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOH_ICR                (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOH_AFSEL              (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOH_DR2R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOH_DR4R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOH_DR8R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOH_ODR                (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOH_PUR                (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOH_PDR                (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOH_SLR                (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOH_DEN                (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOH_LOCK               (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOH_CR                 (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOH_PERIPHID4          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOH_PERIPHID5          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOH_PERIPHID6          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOH_PERIPHID7          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOH_PERIPHID0          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOH_PERIPHID1          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOH_PERIPHID2          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOH_PERIPHID3          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOH_PCELLID0           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOH_PCELLID1           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOH_PCELLID2           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOH_PCELLID3           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOJ_DATA               (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOJ_DIR                (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOJ_IS                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOJ_IBE                (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOJ_IEV                (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOJ_IM                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOJ_RIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOJ_MIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOJ_ICR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOJ_AFSEL              (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOJ_DR2R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOJ_DR4R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOJ_DR8R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOJ_ODR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOJ_PUR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOJ_PDR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOJ_SLR                (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOJ_DEN                (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOJ_LOCK               (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOJ_CR                 (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOJ_PERIPHID4          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOJ_PERIPHID5          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOJ_PERIPHID6          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOJ_PERIPHID7          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOJ_PERIPHID0          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOJ_PERIPHID1          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOJ_PERIPHID2          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOJ_PERIPHID3          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOJ_PCELLID0           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOJ_PCELLID1           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOJ_PCELLID2           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOJ_PCELLID3           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h
new file mode 100644
index 000000000..e029c4f3f
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h
@@ -0,0 +1,247 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_i2c.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* I2C Register Offsets *************************************************************/
+
+/* I2C Master */
+
+#define LM3S_I2CM_SA_OFFSET  0x000 /* I2C Master Slave Address */
+#define LM3S_I2CM_CS_OFFSET  0x004 /* I2C Master Control/Status */
+#define LM3S_I2CM_DR_OFFSET  0x008 /* I2C Master Data */
+#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
+#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
+#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
+#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
+#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
+#define LM3S_I2CM_CR_OFFSET  0x020 /* I2C Master Configuration */
+
+/* I2C Slave */
+
+#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
+#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
+#define LM3S_I2CS_DR_OFFSET  0x008 /* I2C Slave Data */
+#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
+#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
+#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
+#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
+
+/* I2C Register Addresses ***********************************************************/
+
+#if LM3S_NI2C > 0
+
+/* I2C Master */
+
+#define LM3S_I2CM_BASE(n)    (LM3S_I2CM0_BASE + (n)*0x1000)
+#define LM3S_I2CM_SA(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM_CS(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM_DR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM_TPR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM_IMR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM_RIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM_MIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM_ICR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM_CR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
+
+/* I2C Slave */
+
+#define LM3S_I2CS_BASE(n)    (LM3S_I2CS0_BASE + (n)*0x1000)
+#define LM3S_I2CS_OAR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS_CSR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS_DR(n)      (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS_IMR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS_RIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS_MIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS_ICR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
+
+/* I2C0 Master */
+
+#define LM3S_I2CM0_SA        (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM0_CS        (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM0_DR        (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM0_TPR       (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM0_IMR       (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM0_RIS       (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM0_MIS       (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM0_ICR       (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM0_CR        (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
+
+/* I2C0 Slave */
+
+#define LM3S_I2CS0_OAR       (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS0_CSR       (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS0_DR        (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS0_IMR       (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS0_RIS       (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS0_MIS       (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS0_ICR       (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
+
+#if LM3S_NI2C > 1
+
+/* I2C1 Master */
+
+#define LM3S_I2CM1_SA        (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM1_CS        (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM1_DR        (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM1_TPR       (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM1_IMR       (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM1_RIS       (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM1_MIS       (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM1_ICR       (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM1_CR        (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
+
+/* I2C1 Slave */
+
+#define LM3S_I2CS1_OAR       (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS1_CSR       (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS1_DR        (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS1_IMR       (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS1_RIS       (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS1_MIS       (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS1_ICR       (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
+
+#endif
+#endif
+
+/* I2C_Register Bit Definitions *****************************************************/
+
+/* I2C Master Slave Address (I2CM_SA), offset 0x000 */
+
+#define I2CM_SA_RS           (1 << 0)  /* Bit 0:  Receive/Send */
+#define I2CM_SA_SA_SHIFT     1         /* Bits 7-1: I2C Slave Address */
+#define I2CM_SA_SA_MASK      (0x7f << I2CM_SA_SA_SHIFT)
+
+/* I2C Master Control/Status (I2CM_CS), offset 0x004 */
+
+#define I2CM_CS_BUSY         (1 << 0)  /* Bit 0:  I2C Busy (read) */
+#define I2CM_CS_ERROR        (1 << 1)  /* Bit 1:  Error in last bus operation (read) */
+#define I2CM_CS_ADRACK       (1 << 2)  /* Bit 2:  Acknowledge Address (read) */
+#define I2CM_CS_DATACK       (1 << 3)  /* Bit 3:  Acknowledge Data (read) */
+#define I2CM_CS_ARBLST       (1 << 4)  /* Bit 4:  Arbitration Lost (read) */
+#define I2CM_CS_IDLE         (1 << 5)  /* Bit 5:  I2C Idle (read) */
+#define I2CM_CS_BUSBSY       (1 << 6)  /* Bit 6:  Bus Busy (read) */
+
+#define I2CM_CS_RUN          (1 << 0)  /* Bit 0:  I2C Master Enable (write) */
+#define I2CM_CS_START        (1 << 1)  /* Bit 1:  Generate START (write) */
+#define I2CM_CS_STOP         (1 << 2)  /* Bit 2:  Generate STOP (write) */
+#define I2CM_CS_ACK          (1 << 3)  /* Bit 3:  Data Acknowledge Enable (write) */
+
+/* I2C Master Data (I2CM_DR), offset 0x008 */
+
+#define I2CM_DR_MASK         0xff      /* Bits 7-0: Data transferred */
+
+/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */
+
+#define I2CM_TPR_MASK        0xff      /* Bits 7-0: SCL Clock Period */
+
+/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */
+
+#define I2CM_IMR_IM          (1 << 0)  /* Bit 0:  Interrupt Mask */
+
+/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */
+
+#define I2CM_RIS_RIS         (1 << 0)  /* Bit 0:  Raw Interrupt Status */
+
+/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */
+
+#define I2CM_MIS_MIS         (1 << 0)  /* Bit 0:  Masked Interrupt Status */
+
+/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */
+
+#define I2CM_ICR_IC          (1 << 0)  /* Bit 0:  Masked Interrupt Status */
+
+/* I2C Master Configuration (I2CM_CR), offset 0x020 */
+
+#define I2CM_CR_LPBK         (1 << 0)  /* Bit 0:: I2C Loopback */
+#define I2CM_CR_MFE          (1 << 4 ) /* Bit 4:  I2C Master Function Enable */
+#define I2CM_CR_SFE          (1 << 5)  /* Bit 5:  I2C Slave Function Enable */
+
+/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */
+
+#define I2CS_OAR_MASK        0xff      /* Bits 7-0: I2C Slave Own Address */
+
+/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */
+
+#define I2CS_CSR_RREQ        (1 << 0)  /* Bit 0:  Receive Request (read) */
+#define I2CS_CSR_TREQ        (1 << 1)  /* Bit 1:  Transmit Request (read) */
+#define I2CS_CSR_FBR         (1 << 2)  /* Bit 2:  First Byte Received (read) */
+
+#define I2CS_CSR_DA          (1 << 0)  /* Bit 0:  Device Active (write) */
+
+/* I2C Slave Data (I2CS_DR), offset 0x008 */
+
+#define I2CS_DR_MASK         0xff      /* Bits 7-0: Data for Transfer */
+
+/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */
+
+#define I2CM_IMR_DATAIM      (1 << 0)  /* Bit 0:  Data Interrupt Mask */
+
+/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */
+
+#define I2CM_RIS_DATARIS     (1 << 0)  /* Bit 0:  Data Raw Interrupt Status */
+
+/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */
+
+#define I2CM_MIS_DATAMIS     (1 << 0)  /* Bit 0:  Data Masked Interrupt Status */
+
+/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */
+
+#define I2CM_ICR_DATAIC      (1 << 0)  /* Bit 0:  Data Interrupt Clear */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h
new file mode 100644
index 000000000..51de04a2b
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h
@@ -0,0 +1,360 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_memorymap.h
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Memory map ***********************************************************************/
+ 
+#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
+    defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
+#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
+                                         /* -0x1fffffff: Reserved */
+#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
+                                         /* -0x21ffffff: Reserved */
+#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
+                                         /* -0x3fffffff: Reserved */
+#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
+                                         /* -0x41ffffff: Peripherals */
+#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
+                                         /* -0xdfffffff: Reserved */
+#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
+#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
+#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
+                                         /* -0xe000dfff: Reserved */
+#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
+                                         /* -0xe003ffff: Reserved */
+#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
+                                         /* -0xffffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
+                                         /* -0x1fffffff: Reserved */
+#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
+                                         /* -0x21ffffff: Reserved */
+#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
+                                         /* -0x3fffffff: Reserved */
+#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
+                                         /* -0x41ffffff: Peripherals */
+#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
+                                         /* -0x5fffffff: Reserved */
+#  define LM3S_EPI0RAM_BASE   0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */
+#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
+#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
+#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
+                                         /* -0xe000dfff: Reserved */
+#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
+                                         /* -0xe003ffff: Reserved */
+#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
+                                         /* -0xffffffff: Reserved */
+#else
+#  error "Memory map not specified for this LM3S chip"
+#endif
+
+/* Peripheral base addresses ********************************************************/
+/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt
+ * peripheral modules.  They could probably be combined into one peripheral memory
+ * map.  However, keeping them separate does also provide so early, compile-time
+ * error detection that makes the duplication worthwhile.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                            /* -0x27fff: Reserved */
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                            /* -0x27fff: Reserved */
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2bfff: Reserved */
+#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                            /* -0x27fff: Reserved */
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2bfff: Reserved */
+#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x3fffff: Reserved */
+#  define LM3S_CANCON_BASE    (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN Controller */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
+
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2bfff: Reserved */
+#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC0_BASE       (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
+#  define LM3S_ADC1_BASE       (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+#  define LM3S_GPIOJ_BASE     (LM3S_PERIPH_BASE + 0x3d000)  /* -0x3dfff: GPIO Port J */
+                                                            /* -0x3ffff: Reserved */
+#  define LM3S_CAN0_BASE      (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN 0 */
+#  define LM3S_CAN1_BASE      (LM3S_PERIPH_BASE + 0x41000)  /* -0x41fff: CAN 1 */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0x49fff: Reserved */
+#  define LM3S_USB_BASE       (LM3S_PERIPH_BASE + 0x50000)  /* -0x50fff: USB */
+                                                            /* -0x53fff: Reserved */
+#  define LM3S_I2S0_BASE      (LM3S_PERIPH_BASE + 0x54000)  /* -0x54fff: I2S 0 */
+                                                            /* -0x57fff: Reserved */
+#  define LM3S_GPIOAAHB_BASE  (LM3S_PERIPH_BASE + 0x58000)  /* -0x58fff: GPIO Port A (AHB aperture) */
+#  define LM3S_GPIOBAHB_BASE  (LM3S_PERIPH_BASE + 0x59000)  /* -0x59fff: GPIO Port B (AHB aperture) */
+#  define LM3S_GPIOCAHB_BASE  (LM3S_PERIPH_BASE + 0x5A000)  /* -0x5afff: GPIO Port C (AHB aperture) */
+#  define LM3S_GPIODAHB_BASE  (LM3S_PERIPH_BASE + 0x5B000)  /* -0x5bfff: GPIO Port D (AHB aperture) */
+#  define LM3S_GPIOEAHB_BASE  (LM3S_PERIPH_BASE + 0x5C000)  /* -0x5cfff: GPIO Port E (AHB aperture) */
+#  define LM3S_GPIOFAHB_BASE  (LM3S_PERIPH_BASE + 0x5D000)  /* -0x5dfff: GPIO Port F (AHB aperture) */
+#  define LM3S_GPIOGAHB_BASE  (LM3S_PERIPH_BASE + 0x5E000)  /* -0x5efff: GPIO Port G (AHB aperture) */
+#  define LM3S_GPIOHAHB_BASE  (LM3S_PERIPH_BASE + 0x5F000)  /* -0x5ffff: GPIO Port H (AHB aperture) */
+#  define LM3S_GPIOJAHB_BASE  (LM3S_PERIPH_BASE + 0x60000)  /* -0x60fff: GPIO Port J (AHB aperture) */
+                                                            /* -0xcffff: Reserved */
+#  define LM3S_EPI0_BASE      (LM3S_PERIPH_BASE + 0xD0000)  /* -0xd0fff: EPI 0 */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+#  define LM3S_UDMA_BASE      (LM3S_PERIPH_BASE + 0xff000)  /* -0xfffff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#else
+#  error "Peripheral base addresses not specified for this LM3S chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
new file mode 100644
index 000000000..85ec1369a
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
@@ -0,0 +1,281 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_pinmap.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* The following lists the input value to lm3s_configgpio to setup the alternate,
+ * hardware function for each pin.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTA | 6)     /* PA6: Capture/Compare/PWM1 (CCP1) */
+#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 0)     /* PB0: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 1)     /* PB1: Capture/Compare/PWM2 (CCP2) */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_TMR5_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 4)     /* PC4: Capture/Compare/PWM5 (CCP5) */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
+#  define GPIO_TMR4_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 7)     /* PC7: Capture/Compare/PWM4 (CCP4) */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
+#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
+#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
+#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT  | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO     | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO     | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT  | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO   | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO     | GPIO_PORTC | 1) /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO     | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 2) /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */
+#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT  | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT  | GPIO_PORTD | 6) /* PD6: PWM Fault */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO     | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */
+#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
+#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
+#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
+#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
+#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
+#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
+#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
+#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
+#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
+#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
+#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
+#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
+#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
+#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
+#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
+#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFODIO | GPIO_PORTA | 6)   /* PA6: I2C1 clock (I2C1SCL) */
+#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
+#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
+#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFODIO  | GPIO_PORTB | 2)  /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1)  /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
+#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
+#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
+#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
+#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
+#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
+#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
+#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
+#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
+#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
+#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
+#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
+#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
+#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT   | GPIO_PORTA | 0)       /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTA | 1)       /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO      | GPIO_PORTA | 2)       /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO      | GPIO_PORTA | 3)       /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT   | GPIO_PORTA | 4)       /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTA | 5)       /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO      | GPIO_PORTA | 6)       /* PA6: Capture/Compare/PWM0 (CCP1) */
+#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 0)       /* PB0: PWM Generator 1, PWM2 */
+#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 1)       /* PB1: PWM Generator 1, PWM3 */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 2)       /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO    | GPIO_PORTB | 3)       /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 4)       /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 5)       /* PB5: Analog comparator 0 output (C0o) (differs) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 6)       /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 7)       /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 0)       /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 0)       /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO      | GPIO_PORTC | 1)       /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO      | GPIO_PORTC | 1)       /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 2)       /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTC | 3)       /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTC | 3)       /* PC3: JTAG SWO */
+#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 4)       /* PC4: QEI module 0 phase A. */
+#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 6)       /* PC6: QEI module 0 phase B. */
+#  define GPIO_CAN0_RX     (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 0)       /* PD0: CAN module  RX */
+#  define GPIO_CAN0_TX     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTD | 1)       /* PD1: CAN module TX */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 2)       /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTD | 3)       /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO      | GPIO_PORTD | 4)       /* PD4: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 6)       /* PD6: PWM Fault */
+#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFIO      | GPIO_PORTD | 7)       /* PC7: QEI module 0 index */
+#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTE | 0)       /* PE0: PWM Generator 2, PWM4 */
+#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTE | 1)       /* PE1: PWM Generator 1, PWM5 */
+#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 2)       /* PE2: QEI module 1 phase B. */
+#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 3)       /* PE3: QEI module 1 phase A. */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 0)       /* PF0: PWM Generator 0, PWM0 */
+#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 1)       /* PF1: QEI module 1 index. ) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 2)       /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 3)       /* PF3: LED0 */
+#  define GPIO_PWM0_1     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTG | 1)       /* PG1:PWM Generator 0, PWM1 */
+#else
+#  error "Unknown LM3S chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h
new file mode 100644
index 000000000..be5a766e5
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h
@@ -0,0 +1,235 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_ssi.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#if LM3S_NSSI > 0
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* SSI register offsets *************************************************************/
+
+#define LM3S_SSI_CR0_OFFSET       0x000 /* SSI Control 0 */
+#define LM3S_SSI_CR1_OFFSET       0x004 /* SSI Control 1 */
+#define LM3S_SSI_DR_OFFSET        0x008 /* SSI Data */
+#define LM3S_SSI_SR_OFFSET        0x00c /* SSI Status */
+#define LM3S_SSI_CPSR_OFFSET      0x010 /* SSI Clock Prescale */
+#define LM3S_SSI_IM_OFFSET        0x014 /* SSI Interrupt Mask */
+#define LM3S_SSI_RIS_OFFSET       0x018 /* SSI Raw Interrupt Status */
+#define LM3S_SSI_MIS_OFFSET       0x01c /* SSI Masked Interrupt Status */
+#define LM3S_SSI_ICR_OFFSET       0x020 /* SSI Interrupt Clear */
+#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
+#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
+#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
+#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
+#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
+#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
+#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
+#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
+#define LM3S_SSI_PCELLID0_OFFSET  0xff0 /* SSI PrimeCell Identification 0 */
+#define LM3S_SSI_PCELLID1_OFFSET  0xff4 /* SSI PrimeCell Identification 1 */
+#define LM3S_SSI_PCELLID2_OFFSET  0xff8 /* SSI PrimeCell Identification 2 */
+#define LM3S_SSI_PCELLID3_OFFSET  0xffc /* SSI PrimeCell Identification 3 */
+
+/* SSI register addresses ***********************************************************/
+
+#define LM3S_SSI0_CR0             (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI0_CR1             (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI0_DR              (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI0_SR              (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI0_CPSR            (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI0_IM              (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI0_RIS             (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI0_MIS             (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI0_ICR             (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI0_PERIPHID4       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI0_PERIPHID5       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI0_PERIPHID6       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI0_PERIPHID7       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI0_PERIPHID0       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI0_PERIPHID1       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI0_PERIPHID2       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI0_PERIPHID3       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI0_PCELLID0        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI0_PCELLID1        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI0_PCELLID2        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI0_PCELLID3        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
+
+#if LM3S_NSSI > 1
+#define LM3S_SSI1_CR0             (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI1_CR1             (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI1_DR              (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI1_SR              (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI1_CPSR            (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI1_IM              (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI1_RIS             (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI1_MIS             (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI1_ICR             (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI1_PERIPHID4       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI1_PERIPHID5       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI1_PERIPHID6       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI1_PERIPHID7       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI1_PERIPHID0       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI1_PERIPHID1       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI1_PERIPHID2       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI1_PERIPHID3       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI1_PCELLID0        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI1_PCELLID1        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI1_PCELLID2        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI1_PCELLID3        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
+
+#define LM3S_SSI_BASE(n)          (LM3S_SSI0_BASE + (n)*0x01000)
+
+#define LM3S_SSI_CR0(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI_CR1(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI_DR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI_SR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI_CPSR(n)          (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI_IM(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI_RIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI_MIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI_ICR(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI_PERIPHID4(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI_PERIPHID5(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI_PERIPHID6(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI_PERIPHID7(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI_PERIPHID0(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI_PERIPHID1(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI_PERIPHID2(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI_PERIPHID3(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI_PCELLID0(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI_PCELLID1(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI_PCELLID2(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI_PCELLID3(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
+#endif /* LM3S_NSSI > 1 */
+
+/* SSI register bit defitiions ******************************************************/
+
+/* SSI Control 0 (SSICR0), offset 0x000 */
+
+#define SSI_CR0_DSS_SHIFT         0         /* Bits 3-0: SSI Data Size Select */
+#define SSI_CR0_DSS_MASK          (0x0f << SSI_CR0_DSS_SHIFT)
+#define   SSI_CR0_DSS(n)          ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
+#define SSI_CR0_FRF_SHIFT         4         /* Bits 5-4: SSI Frame Format Select */
+#define SSI_CR0_FRF_MASK          (3 << SSI_CR0_FRF_SHIFT)
+#define   SSI_CR0_FRF_SPI         (0 << SSI_CR0_FRF_SHIFT)     /* Freescale SPI format */
+#define   SSI_CR0_FRF_SSFF        (1 << SSI_CR0_FRF_SHIFT)     /* TI synchronous serial fram format */
+#define   SSI_CR0_FRF_UWIRE       (2 << SSI_CR0_FRF_SHIFT)     /* MICROWIRE frame format */
+#define SSI_CR0_SPO               (1 << 6)  /* Bit 6:  SSI Serial Clock Polarity */
+#define SSI_CR0_SPH               (1 << 7)  /* Bit 7:  SSI Serial Clock Phase */
+#define SSI_CR0_SCR_SHIFT         8         /* Bits 15-8: SSI Serial Clock Rate */
+#define SSI_CR0_SCR_MASK          (0xff << SSI_CR0_SCR_SHIFT)
+
+/* SSI Control 1 (SSICR1), offset 0x004 */
+
+#define SSI_CR1_LBM               (1 << 0)  /* Bit 0:  SSI Loopback Mode */
+#define SSI_CR1_SSE               (1 << 1)  /* Bit 1:  SSI Synchronous Serial Port Enable */
+#define SSI_CR1_MS                (1 << 2)  /* Bit 2:  SSI Master/Slave Select slave */
+#define SSI_CR1_SOD               (1 << 3)  /* Bit 3:  SSI Slave Mode Output Disable */
+
+/* SSI Data (SSIDR), offset 0x008 */
+
+#define SSI_DR_MASK               0xffff    /* Bits 15-0: SSI data */
+
+/* SSI Status (SSISR), offset 0x00c */
+
+#define SSI_SR_TFE                (1 << 0)  /* Bit 0:  SSI Transmit FIFO Empty */
+#define SSI_SR_TNF                (1 << 1)  /* Bit 1:  SSI Transmit FIFO Not Full */
+#define SSI_SR_RNE                (1 << 2)  /* Bit 2:  SSI Receive FIFO Not Empty */
+#define SSI_SR_RFF                (1 << 3)  /* Bit 3:  SSI Receive FIFO Full */
+#define SSI_SR_BSY                (1 << 4)  /* Bit 4:  SSI Busy Bit */
+
+/* SSI Clock Prescale (SSICPSR), offset 0x010 */
+
+#define SSI_CPSR_DIV_MASK         0xff      /* Bits 7-0: SSI Clock Prescale Divisor */
+
+/* SSI Interrupt Mask (SSIIM), offset 0x014 */
+
+#define SSI_IM_ROR                (1 << 0)  /* Bit 0:  SSI Receive Overrun Interrupt Mask */
+#define SSI_IM_RT                 (1 << 1)  /* Bit 1:  SSI Receive Time-Out Interrupt Mask */
+#define SSI_IM_RX                 (1 << 2)  /* Bit 2:  SSI Receive FIFO Interrupt Mask */
+#define SSI_IM_TX                 (1 << 3)  /* Bit 3:  SSI Transmit FIFO Interrupt Mask */
+
+/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
+
+#define SSI_RIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Raw Interrupt Status */
+#define SSI_RIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Raw Interrupt Status */
+#define SSI_RIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Raw Interrupt Status */
+#define SSI_RIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Raw Interrupt Status */
+
+/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
+
+#define SSI_MIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Masked Interrupt Status */
+#define SSI_MIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Masked Interrupt Status */
+#define SSI_MIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Masked Interrupt Status */
+#define SSI_MIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Masked Interrupt Status */
+
+/* SSI Interrupt Clear (SSIICR), offset 0x020 */
+
+#define SSI_ICR_ROR               (1 << 0)  /* Bit 0: SSI Receive Overrun Interrupt Clear */
+#define SSI_ICR_RT                (1 << 1)  /* Bit 1: SSI Receive Time-Out Interrupt Clear */
+
+/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
+
+#define SSI_PERIPHID_MASK         0xff      /* Bits 7-0: SSI Peripheral ID n */
+
+/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
+
+#define SSI_PCELLID_MASK          0xff      /* Bits 7-0: SSI Prime cell ID */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* LM3S_NSSI > 0 */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h
new file mode 100644
index 000000000..00a222ee3
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h
@@ -0,0 +1,495 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_syscontrol.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* System Control Register Offsets **************************************************/
+
+#define LM3S_SYSCON_DID0_OFFSET       0x000 /* Device Identification 0 */
+#define LM3S_SYSCON_DID1_OFFSET       0x004 /* Device Identification 1 */
+#define LM3S_SYSCON_DC0_OFFSET        0x008 /* Device Capabilities 0 */
+#define LM3S_SYSCON_DC1_OFFSET        0x010 /* Device Capabilities 1 */
+#define LM3S_SYSCON_DC2_OFFSET        0x014 /* Device Capabilities 2 */
+#define LM3S_SYSCON_DC3_OFFSET        0x018 /* Device Capabilities 3 */
+#define LM3S_SYSCON_DC4_OFFSET        0x01c /* Device Capabilities 4 */
+#define LM3S_SYSCON_PBORCTL_OFFSET    0x030 /* Brown-Out Reset Control */
+#define LM3S_SYSCON_LDOPCTL_OFFSET    0x034 /* LDO Power Control */
+#define LM3S_SYSCON_SRCR0_OFFSET      0x040 /* Software Reset Control 0 */
+#define LM3S_SYSCON_SRCR1_OFFSET      0x044 /* Software Reset Control 1 */
+#define LM3S_SYSCON_SRCR2_OFFSET      0x048 /* Software Reset Control 2*/
+#define LM3S_SYSCON_RIS_OFFSET        0x050 /* Raw Interrupt Status */
+#define LM3S_SYSCON_IMC_OFFSET        0x054 /* Interrupt Mask Control */
+#define LM3S_SYSCON_MISC_OFFSET       0x058 /* Masked Interrupt Status and Clear */
+#define LM3S_SYSCON_RESC_OFFSET       0x05c /* Reset Cause */
+#define LM3S_SYSCON_RCC_OFFSET        0x060 /* Run-Mode Clock Configuration */
+#define LM3S_SYSCON_PLLCFG_OFFSET     0x064 /* XTAL to PLL Translation */
+#define LM3S_SYSCON_RCC2_OFFSET       0x070 /* Run-Mode Clock Configuration 2 */
+#define LM3S_SYSCON_RCGC0_OFFSET      0x100 /* Run Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_RCGC1_OFFSET      0x104 /* Run Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_RCGC2_OFFSET      0x108 /* Run Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_SCGC0_OFFSET      0x110 /* Sleep Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_SCGC1_OFFSET      0x114 /* Sleep Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_SCGC2_OFFSET      0x118 /* Sleep Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_DCGC0_OFFSET      0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_DCGC1_OFFSET      0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_DCGC2_OFFSET      0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
+
+/* System Control Register Addresses ************************************************/
+
+#define LM3S_SYSCON_DID0              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
+#define LM3S_SYSCON_DID1              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
+#define LM3S_SYSCON_DC0               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
+#define LM3S_SYSCON_DC1               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
+#define LM3S_SYSCON_DC2               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
+#define LM3S_SYSCON_DC3               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
+#define LM3S_SYSCON_DC4               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
+#define LM3S_SYSCON_PBORCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
+#define LM3S_SYSCON_LDOPCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
+#define LM3S_SYSCON_SRCR0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
+#define LM3S_SYSCON_SRCR1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
+#define LM3S_SYSCON_SRCR2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
+#define LM3S_SYSCON_RIS               (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
+#define LM3S_SYSCON_IMC               (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
+#define LM3S_SYSCON_MISC              (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
+#define LM3S_SYSCON_RESC              (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
+#define LM3S_SYSCON_RCC               (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
+#define LM3S_SYSCON_PLLCFG            (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
+#define LM3S_SYSCON_RCC2              (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
+#define LM3S_SYSCON_RCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
+#define LM3S_SYSCON_RCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
+#define LM3S_SYSCON_RCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
+#define LM3S_SYSCON_SCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
+#define LM3S_SYSCON_SCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
+#define LM3S_SYSCON_SCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
+#define LM3S_SYSCON_DCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
+#define LM3S_SYSCON_DCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
+#define LM3S_SYSCON_DCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
+#define LM3S_SYSCON_DSLPCLKCFG        (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
+
+/* System Control Register Bit Definitions ******************************************/
+
+/* Device Identification 0 (DID0), offset 0x000 */
+
+#define SYSCON_DID0_MINOR_SHIFT       0         /* Bits 7-0: Minor Revision of the device */
+#define SYSCON_DID0_MINOR_MASK        (0xff << SYSCON_DID0_MINOR_SHIFT)
+#define SYSCON_DID0_MAJOR_SHIFT       8         /* Bits 15-8: Major Revision of the device */
+#define SYSCON_DID0_MAJOR_MASK        (0xff << SYSCON_DID0_MAJOR_SHIFT)
+#define SYSCON_DID0_CLASS_SHIFT       16        /* Bits 23-16: Device Class */
+#define SYSCON_DID0_CLASS_MASK        (0xff << SYSCON_DID0_CLASS_SHIFT)
+#define SYSCON_DID0_VER_SHIFT         28        /* Bits 30-28: DID0 Version */
+#define SYSCON_DID0_VER_MASK          (7 << SYSCON_DID0_VER_SHIFT)
+
+/* Device Identification 1 (DID1), offset 0x004 */
+
+#define SYSCON_DID1_QUAL_SHIFT        0         /* Bits 1-0: Qualification Status */
+#define SYSCON_DID1_QUAL_MASK         (0x03 << SYSCON_DID1_QUAL_SHIFT)
+#define SYSCON_DID1_ROHS              (1 << 2)  /* Bit 2: RoHS-Compliance */
+#define SYSCON_DID1_PKG_SHIFT         3 /* Bits 4-3: Package Type */
+#define SYSCON_DID1_PKG_MASK          (0x03 << SYSCON_DID1_PKG_SHIFT)
+#define SYSCON_DID1_TEMP_SHIFT        5         /* Bits 7-5: Temperature Range */
+#define SYSCON_DID1_TEMP_MASK         (0x07 << SYSCON_DID1_TEMP_SHIFT)
+#define SYSCON_DID1_PINCOUNT_SHIFT    13        /* Bits 15-13: Package Pin Count */
+#define SYSCON_DID1_PINCOUNT_MASK     (0x07 << SYSCON_DID1_PINCOUNT_SHIFT)
+#define SYSCON_DID1_PARTNO_SHIFT      16        /* Bits 23-16: Part Number */
+#define SYSCON_DID1_PARTNO_MASK       (0xff << SYSCON_DID1_PARTNO_SHIFT)
+#define SYSCON_DID1_FAM_SHIFT         24        /* Bits 27-24: Family */
+#define SYSCON_DID1_FAM_MASK          (0x0f << SYSCON_DID1_FAM_SHIFT)
+#define SYSCON_DID1_VER_SHIFT         28        /* Bits 31-28:  DID1 Version */
+#define SYSCON_DID1_VER_MASK          (0x0f << SYSCON_DID1_VER_SHIFT)
+
+/* Device Capabilities 0 (DC0), offset 0x008 */
+
+#define SYSCON_DC0_FLASHSZ_SHIFT      0         /* Bits 15-0: FLASH Size */
+#define SYSCON_DC0_FLASHSZ_MASK       (0xffff << SYSCON_DC0_FLASHSZ_SHIFT)
+#define SYSCON_DC0_SRAMSZ_SHIFT       16        /* Bits 31-16: SRAM Size */
+#define SYSCON_DC0_SRAMSZ_MASK        (0xffff << SYSCON_DC0_SRAMSZ_SHIFT)
+
+/* Device Capabilities 1 (DC1), offset 0x010 */
+
+#define SYSCON_DC1_JTAG               (1 << 0)  /* Bit 0: JTAG Present */
+#define SYSCON_DC1_SWD                (1 << 1)  /* Bit 1: SWD Present */
+#define SYSCON_DC1_SWO                (1 << 2)  /* Bit 2: SWO Trace Port Present */
+#define SYSCON_DC1_WDT                (1 << 3)  /* Bit 3: Watchdog Timer Present */
+#define SYSCON_DC1_PLL                (1 << 4)  /* Bit 4: PLL Present */
+#define SYSCON_DC1_TEMPSNS            (1 << 5)  /* Bit 5: Temp Sensor Present */
+#define SYSCON_DC1_HIB                (1 << 6)  /* Bit 6: Hibernation Module Present */
+#define SYSCON_DC1_MPU                (1 << 7)  /* Bit 7: MPU Present */
+#define SYSCON_DC1_MAXADCSPD_SHIFT    8         /* Bits 9-8: Max ADC Speed */
+#define SYSCON_DC1_MAXADCSPD_MASK     (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT)
+#define SYSCON_DC1_ADC                (1 << 16) /* Bit 16: ADC Module Present */
+#define SYSCON_DC1_MINSYSDIV_SHIFT    12        /* Bits 15-12: System Clock Divider Minimum */
+#define SYSCON_DC1_MINSYSDIV_MASK     (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT)
+
+/* Device Capabilities 2 (DC2), offset 0x014 */
+
+#define SYSCON_DC2_UART0              (1 << 0)  /* Bit 0: UART0 Present */
+#define SYSCON_DC2_UART1              (1 << 1)  /* Bit 1: UART1 Present */
+#define SYSCON_DC2_SSI0               (1 << 4)  /* Bit 4: SSI0 Present */
+#define SYSCON_DC2_SSI1               (1 << 5)  /* Bit 5: SSI1 Present */
+#define SYSCON_DC2_I2C0               (1 << 12) /* Bit 12: I2C Module 0 Present */
+#define SYSCON_DC2_I2C1               (1 << 14) /* Bit 14: I2C Module 1 Present */
+#define SYSCON_DC2_TIMER0             (1 << 16) /* Bit 16: Timer 0 Present */
+#define SYSCON_DC2_TIMER1             (1 << 17) /* Bit 17: Timer 1 Present */
+#define SYSCON_DC2_TIMER2             (1 << 18) /* Bit 18: Timer 2 Present */
+#define SYSCON_DC2_TIMER3             (1 << 19) /* Bit 19: Timer 3 Present */
+#define SYSCON_DC2_COMP0              (1 << 24) /* Bit 24: Analog Comparator 0 Present */
+#define SYSCON_DC2_COMP1              (1 << 25) /* Bit 25: Analog Comparator 1 Present */
+
+/* Device Capabilities 3 (DC3), offset 0x018 */
+
+#define SYSCON_DC3_C0MINUS            (1 << 6)  /* Bit 6: C0- Pin Present */
+#define SYSCON_DC3_C0PLUS             (1 << 7)  /* Bit 7: C0+ Pin Present */
+#define SYSCON_DC3_C0O                (1 << 8)  /* Bit 8: C0o Pin Present */
+#define SYSCON_DC3_C1MINUS            (1 << 9)  /* Bit 9: C1- Pin Present */
+#define SYSCON_DC3_C1PLUS             (1 << 10) /* Bit 10: C1+ Pin Present */
+#define SYSCON_DC3_ADC0               (1 << 16) /* Bit 16: ADC0 Pin Present */
+#define SYSCON_DC3_ADC1               (1 << 17) /* Bit 17: ADC1 Pin Present */
+#define SYSCON_DC3_ADC2               (1 << 18) /* Bit 18: ADC2 Pin Present */
+#define SYSCON_DC3_ADC3               (1 << 19) /* Bit 19: ADC3 Pin Present */
+#define SYSCON_DC3_ADC4               (1 << 20) /* Bit 20: ADC4 Pin Present */
+#define SYSCON_DC3_ADC5               (1 << 21) /* Bit 21: ADC5 Pin Present */
+#define SYSCON_DC3_ADC6               (1 << 22) /* Bit 22: ADC6 Pin Present */
+#define SYSCON_DC3_ADC7               (1 << 23) /* Bit 23: ADC7 Pin Present */
+#define SYSCON_DC3_CCP0               (1 << 24) /* Bit 24: CCP0 Pin Present */
+#define SYSCON_DC3_CCP1               (1 << 25) /* Bit 25: CCP1 Pin Present */
+#define SYSCON_DC3_CCP2               (1 << 26) /* Bit 26: CCP2 Pin Present */
+#define SYSCON_DC3_CCP3               (1 << 27) /* Bit 27: CCP3 Pin Present */
+#define SYSCON_DC3_CCP4               (1 << 28) /* Bit 28: CCP4 Pin Present */
+#define SYSCON_DC3_CCP5               (1 << 29) /* Bit 29: CCP5 Pin Present */
+#define SYSCON_DC3_32KHZ              (1 << 31) /* Bit 31: 32KHz Input Clock Available */
+
+/* Device Capabilities 4 (DC4), offset 0x01c */
+
+#define SYSCON_DC4_GPIO(n)            (1 << (n))
+#define SYSCON_DC4_GPIOA              (1 << 0)  /* Bit 0: GPIO Port A Present */
+#define SYSCON_DC4_GPIOB              (1 << 1)  /* Bit 1: GPIO Port B Present */
+#define SYSCON_DC4_GPIOC              (1 << 2)  /* Bit 2: GPIO Port C Present */
+#define SYSCON_DC4_GPIOD              (1 << 3)  /* Bit 3: GPIO Port D Present */
+#define SYSCON_DC4_GPIOE              (1 << 4)  /* Bit 4: GPIO Port E Present */
+#define SYSCON_DC4_GPIOF              (1 << 5)  /* Bit 5: GPIO Port F Present */
+#define SYSCON_DC4_GPIOG              (1 << 6)  /* Bit 6: GPIO Port G Present */
+#define SYSCON_DC4_GPIOH              (1 << 7)  /* Bit 7: GPIO Port H Present */
+#define SYSCON_DC4_EMAC0              (1 << 28) /* Bit 28: Ethernet MAC0 Present */
+#define SYSCON_DC4_EPHY0              (1 << 30) /* Bit 30: Ethernet PHY0 Present */
+
+/* Brown-Out Reset Control (PBORCTL), offset 0x030 */
+
+#define SYSCON_PBORCTL_BORIOR         (1 << 1)  /* Bit 1: BOR Interrupt or Reset */
+
+/* LDO Power Control (LDOPCTL), offset 0x034 */
+
+#define SYSCON_LDOPCTL_VADJ_SHIFT     0         /* Bits 5-0: LDO Output Voltage */
+#define SYSCON_LDOPCTL_VADJ_MASK      (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT)
+#  define SYSCON_LPDOPCTL_2500MV      (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/
+#  define SYSCON_LPDOPCTL_2450MV      (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */
+#  define SYSCON_LPDOPCTL_2400MV      (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */
+#  define SYSCON_LPDOPCTL_2350MV      (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */
+#  define SYSCON_LPDOPCTL_2300MV      (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */
+#  define SYSCON_LPDOPCTL_2250MV      (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */
+#  define SYSCON_LPDOPCTL_2750MV      (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */
+#  define SYSCON_LPDOPCTL_2700MV      (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */
+#  define SYSCON_LPDOPCTL_2650MV      (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */
+#  define SYSCON_LPDOPCTL_2600MV      (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */
+#  define SYSCON_LPDOPCTL_2550MV      (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */
+
+/* Software Reset Control 0 (SRCR0), offset 0x040 */
+
+#define SYSCON_SRCR0_WDT              (1 << 3)  /* Bit 3: WDT Reset Control */
+#define SYSCON_SRCR0_HIB              (1 << 6)  /* Bit 6: HIB Reset Control */
+#define SYSCON_SRCR0_ADC              (1 << 16) /* Bit 16: ADC0 Reset Control */
+
+/* Software Reset Control 1 (SRCR1), offset 0x044 */
+
+#define SYSCON_SRCR1_UART0            (1 << 0)  /* Bit 0: UART0 Reset Control */
+#define SYSCON_SRCR1_UART1            (1 << 1)  /* Bit 1: UART1 Reset Control */
+#define SYSCON_SRCR1_SSI0             (1 << 4)  /* Bit 4: SSI0 Reset Control1 */
+#define SYSCON_SRCR1_SSI1             (1 << 5)  /* Bit 5: SSI1 Reset Control */
+#define SYSCON_SRCR1_I2C0             (1 << 12) /* Bit 12: I2C0 Reset Control */
+#define SYSCON_SRCR1_I2C1             (1 << 14) /* Bit 14: I2C1 Reset Control */
+#define SYSCON_SRCR1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Reset Control */
+#define SYSCON_SRCR1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Reset Control */
+#define SYSCON_SRCR1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Reset Control */
+#define SYSCON_SRCR1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Reset Control */
+#define SYSCON_SRCR1_COMP0            (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */
+#define SYSCON_SRCR1_COMP1            (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */
+
+/* Software Reset Control 2 (SRCR2), offset 0x048 */
+
+#define SYSCON_SRCR2_GPIO(n)          (1 << (n))
+#define SYSCON_SRCR2_GPIOA            (1 << 0)  /* Bit 0: Port A Reset Control */
+#define SYSCON_SRCR2_GPIOB            (1 << 1)  /* Bit 1: Port B Reset Control */
+#define SYSCON_SRCR2_GPIOC            (1 << 2)  /* Bit 2: Port C Reset Control */
+#define SYSCON_SRCR2_GPIOD            (1 << 3)  /* Bit 3: Port D Reset Control */
+#define SYSCON_SRCR2_GPIOE            (1 << 4)  /* Bit 4: Port E Reset Control */
+#define SYSCON_SRCR2_GPIOF            (1 << 5)  /* Bit 5: Port F Reset Control */
+#define SYSCON_SRCR2_GPIOG            (1 << 6)  /* Bit 6: Port G Reset Control */
+#define SYSCON_SRCR2_GPIOH            (1 << 7)  /* Bit 7: Port H Reset Control */
+#define SYSCON_SRCR2_EMAC0            (1 << 28) /* Bit 28: MAC0 Reset Control */
+#define SYSCON_SRCR2_EPHY0            (1 << 30) /* Bit 30: PHY0 Reset Control */
+
+/* Raw Interrupt Status (RIS), offset 0x050 */
+
+#define SYSCON_RIS_BORRIS             (1 << 1)  /* Bit 1: Brown-Out Reset Raw Interrupt Status */
+#define SYSCON_RIS_PLLLRIS            (1 << 6)  /* Bit 6: PLL Lock Raw Interrupt Status */
+
+/* Interrupt Mask Control (IMC), offset 0x054 */
+
+#define SYSCON_IMC_BORIM              (1 << 1)  /* Bit 1: Brown-Out Reset Interrupt Mask */
+#define SYSCON_IMC_PLLLIM             (1 << 6)  /* Bit 6: PLL Lock Interrupt Mask */
+
+/* Masked Interrupt Status and Clear (MISC), offset 0x058 */
+
+#define SYSCON_MISC_BORMIS            (1 << 1)  /* Bit 1: BOR Masked Interrupt Status */
+#define SYSCON_MISC_PLLLMIS           (1 << 6)  /* Bit 6: PLL Lock Masked Interrupt Status */
+
+/* Reset Cause (RESC), offset 0x05C */
+
+#define SYSCON_RESC_EXT               (1 << 0)  /* Bit 0: External Reset */
+#define SYSCON_RESC_POR               (1 << 1)  /* Bit 1: Power-On Reset */
+#define SYSCON_RESC_BOR               (1 << 2)  /* Bit 2: Brown-Out Reset */
+#define SYSCON_RESC_WDT               (1 << 3)  /* Bit 3: Watchdog Timer Reset */
+#define SYSCON_RESC_SW                (1 << 4)  /* Bit 4: Software Reset */
+
+/* Run-Mode Clock Configuration (RCC), offset 0x060 */
+
+#define SYSCON_RCC_MOSCDIS            (1 << 0)  /* Bit 0: Main Oscillator Disable */
+#define SYSCON_RCC_IOSCDIS            (1 << 1)  /* Bit 1: Internal Oscillator Disable */
+#define SYSCON_RCC_OSCSRC_SHIFT       4         /* Bits 5-4: Oscillator Source */
+#define SYSCON_RCC_OSCSRC_MASK        (0x03 << SYSCON_RCC_OSCSRC_SHIFT)
+#  define SYSCON_RCC_OSCSRC_MOSC      (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */
+#  define SYSCON_RCC_OSCSRC_IOSC      (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */
+#  define SYSCON_RCC_OSCSRC_IOSC4     (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */
+#  define SYSCON_RCC_OSCSRC_30KHZ     (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */
+#define SYSCON_RCC_XTAL_SHIFT         6         /* Bits 10-6: Crystal Value */
+#define SYSCON_RCC_XTAL_MASK          (0x1f << SYSCON_RCC_XTAL_SHIFT)
+#  define SYSCON_RCC_XTAL1000KHZ      ( 0 << SYSCON_RCC_XTAL_SHIFT)  /* 1.0000MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL1843KHZ      ( 1 << SYSCON_RCC_XTAL_SHIFT)  /* 1.8432MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL2000KHZ      ( 2 << SYSCON_RCC_XTAL_SHIFT)  /* 2.0000MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL2580KHZ      ( 3 << SYSCON_RCC_XTAL_SHIFT)  /* 2.4576MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL3580KHZ      ( 4 << SYSCON_RCC_XTAL_SHIFT)  /* 3.5795MHz */
+#  define SYSCON_RCC_XTAL3686KHZ      ( 5 << SYSCON_RCC_XTAL_SHIFT)  /* 3.6864MHz */
+#  define SYSCON_RCC_XTAL4000KHZ      ( 6 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0000MHz */
+#  define SYSCON_RCC_XTAL4096KHZ      ( 7 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0960MHz */
+#  define SYSCON_RCC_XTAL4915KHZ      ( 8 << SYSCON_RCC_XTAL_SHIFT)  /* 4.9152MHz */
+#  define SYSCON_RCC_XTAL5000KHZ      ( 9 << SYSCON_RCC_XTAL_SHIFT)  /* 5.0000MHz */
+#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT)  /* 5.1200MHz */
+#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT)  /* 6.0000MHz (reset value) */
+#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT)  /* 6.1440MHz */
+#  define SYSCON_RCC_XTAL7373KHZ      (13 << SYSCON_RCC_XTAL_SHIFT)  /* 7.3728MHz */
+#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT)  /* 8.0000MHz */
+#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT)  /* 8.1920MHz */
+#ifdef CONFIG_ARCH_CHIP_LM3S9B96
+#  define SYSCON_RCC_XTAL10000KHZ     (16 << SYSCON_RCC_XTAL_SHIFT)  /* 10.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL12000KHZ     (17 << SYSCON_RCC_XTAL_SHIFT)  /* 12.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL12888KHZ     (18 << SYSCON_RCC_XTAL_SHIFT)  /* 12.288 MHz */
+#  define SYSCON_RCC_XTAL13560KHZ     (19 << SYSCON_RCC_XTAL_SHIFT)  /* 13.56 MHz */
+#  define SYSCON_RCC_XTAL14318KHZ     (20 << SYSCON_RCC_XTAL_SHIFT)  /* 14.31818 MHz */
+#  define SYSCON_RCC_XTAL16000KHZ     (21 << SYSCON_RCC_XTAL_SHIFT)  /* 16.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL16384KHZ     (22 << SYSCON_RCC_XTAL_SHIFT)  /* 16.384 MHz */
+#endif
+#define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
+#define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
+#define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */
+#define SYSCON_RCC_SYSDIV_SHIFT       23        /* Bits 26-23: System Clock Divisor */
+#define SYSCON_RCC_SYSDIV_MASK        (0x0f << SYSCON_RCC_SYSDIV_SHIFT)
+#  define SYSCON_RCC_SYSDIV(n)        (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT)
+#define SYSCON_RCC_ACG                (1 << 27) /* Bit 27: Auto Clock Gating */
+
+/* XTAL to PLL Translation (PLLCFG), offset 0x064 */
+
+#define SYSCON_PLLCFG_F_SHIFT         5         /* Bits 13-5: PLL F Value */
+#define SYSCON_PLLCFG_F_MASK          (0x1ff << SYSCON_PLLCFG_F_SHIFT)
+#define SYSCON_PLLCFG_R_SHIFT         0         /* Bits 4-0: PLL R Value  */
+#define SYSCON_PLLCFG_R_MASK          (0x1f << SYSCON_PLLCFG_R_SHIFT)
+
+/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */
+
+#define SYSCON_RCC2_OSCSRC2_SHIFT     4         /* Bits 6-4: Oscillator Source */
+#define SYSCON_RCC2_OSCSRC2_MASK      (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT)
+#  define SYSCON_RCC2_OSCSRC2_MOSC    (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */
+#  define SYSCON_RCC2_OSCSRC2_IOSC    (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */
+#  define SYSCON_RCC2_OSCSRC2_IOSC4   (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */
+#  define SYSCON_RCC2_OSCSRC2_30KHZ   (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */
+#  define SYSCON_RCC2_OSCSRC2_32KHZ   (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */
+#define SYSCON_RCC2_BYPASS2           (1 << 11) /* Bit 11: Bypass PLL */
+#define SYSCON_RCC2_PWRDN2            (1 << 13) /* Bit 13: Power-Down PLL */
+#define SYSCON_RCC2_SYSDIV2_SHIFT     23        /* Bits 28-23: System Clock Divisor */
+#define SYSCON_RCC2_SYSDIV2_MASK      (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT)
+#  define SYSCON_RCC2_SYSDIV(n)       ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT)
+#define SYSCON_RCC2_USERCC2           (1 << 31) /* Bit 31: Use RCC2 When set */
+
+/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */
+
+#define SYSCON_RCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_RCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_RCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_RCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_RCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */
+
+#define SYSCON_RCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_RCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_RCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_RCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_RCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_RCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_RCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_RCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */
+
+#define SYSCON_RCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_RCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_RCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_RCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_RCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_RCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_RCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_RCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_RCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_RCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_RCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */
+
+#define SYSCON_SCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_SCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_SCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_SCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_SCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */
+
+#define SYSCON_SCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_SCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_SCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_SCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_SCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_SCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_SCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_SCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */
+
+#define SYSCON_SCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_SCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_SCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_SCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_SCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_SCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_SCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_SCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_SCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_SCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_SCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */
+
+#define SYSCON_DCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_DCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_DCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_DCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_DCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */
+
+#define SYSCON_DCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_DCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_DCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_DCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_DCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_DCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_DCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_DCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */
+
+#define SYSCON_DCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_DCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_DCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_DCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_DCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_DCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_DCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_DCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_DCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_DCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_DCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */
+
+#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */
+#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK  (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT)
+#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT   4 /* Bits 6-4: Clock Source */
+#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK    (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm/chip/lm3s_timer.h
new file mode 100644
index 000000000..6be963cc3
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_timer.h
@@ -0,0 +1,125 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_timer.h
+ *
+ *   Copyright (C) 2012 Max Nekludov. All rights reserved.
+ *   Author: Max Nekludov <macscomp@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Timer register offsets ***********************************************************/
+
+#define TIMER_GPTMCFG_OFFSET             0x000
+#define TIMER_GPTMTAMR_OFFSET            0x004
+#define TIMER_GPTMCTL_OFFSET             0x00C
+#define TIMER_GPTMIMR_OFFSET             0x018
+#define TIMER_GPTMRIS_OFFSET             0x01C
+#define TIMER_GPTMICR_OFFSET             0x024
+#define TIMER_GPTMTAILR_OFFSET           0x028
+#define TIMER_GPTMTAR_OFFSET             0x048
+
+/* SSI register addresses ***********************************************************/
+
+#define LM3S_TIMER_BASE(n)               (LM3S_TIMER0_BASE + (n)*0x01000)
+
+#define LM3S_TIMER_GPTMCFG(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
+#define LM3S_TIMER_GPTMTAMR(n)           (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
+#define LM3S_TIMER_GPTMCTL(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
+#define LM3S_TIMER_GPTMIMR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
+#define LM3S_TIMER_GPTMRIS(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
+#define LM3S_TIMER_GPTMICR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
+#define LM3S_TIMER_GPTMTAILR(n)          (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
+#define LM3S_TIMER_GPTMTAR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
+
+/* SSI register bit defitiions ******************************************************/
+
+/* GPTM Configuration (GPTMCFG), offset 0x000 */
+
+#define TIMER_GPTMCFG_CFG_SHIFT          0    /* Bits 2-0: GPTM Configuration */
+#define TIMER_GPTM_CFG_MASK              (0x07 << TIMER_GPTMCFG_CFG_SHIFT)
+#define   TIMER_GPTMCFG_CFG_32           (0 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit timer configuration */
+#define   TIMER_GPTMCFG_CFG_RTC          (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit real-time clock (RTC) counter configuration */
+#define   TIMER_GPTMCFG_CFG_16           (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 16-bit timer configuration */
+
+/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */
+
+#define TIMER_GPTMTAMR_TAMR_SHIFT        0    /* Bits 1-0: GPTM Timer A Mode */
+#define TIMER_GPTMTAMR_TAMR_MASK         (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT)
+#define   TIMER_GPTMTAMR_TAMR_ONESHOT    (1 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* One-Shot Timer mode */
+#define   TIMER_GPTMTAMR_TAMR_PERIODIC   (2 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Periodic Timer mode */
+#define   TIMER_GPTMTAMR_TAMR_CAPTURE    (3 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Capture mode */
+#define TIMER_GPTMTAMR_TACMR_SHIFT       2    /* Bits 2:   GPTM Timer A Capture Mode */
+#define TIMER_GPTMTAMR_TACMR_MASK        (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT)
+#define   TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Count mode */
+#define   TIMER_GPTMTAMR_TACMR_EDGETIME  (1 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Time mode */
+#define TIMER_GPTMTAMR_TAAMS_SHIFT       3    /* Bits 3:   GPTM Timer A Alternate Mode Select */
+#define TIMER_GPTMTAMR_TAAMS_MASK        (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT)
+#define   TIMER_GPTMTAMR_TAAMS_CAPTURE   (0 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* Capture mode is enabled */
+#define   TIMER_GPTMTAMR_TAAMS_PWM       (1 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* PWM mode is enabled */
+#define TIMER_GPTMTAMR_TACDIR_SHIFT      4    /* Bits 4:   GPTM Timer A Count Direction */
+#define TIMER_GPTMTAMR_TACDIR_MASK       (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT)
+#define   TIMER_GPTMTAMR_TACDIR_DOWN     (0 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* The timer counts down */
+#define   TIMER_GPTMTAMR_TACDIR_UP       (1 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* When in one-shot or periodic mode, the timer counts up */
+#define TIMER_GPTMTAMR_TAMIE_SHIFT       5    /* Bits 5:   GPTM Timer A Match Interrupt Enable */
+#define TIMER_GPTMTAMR_TAMIE_MASK        (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT)
+
+/* GPTM Control (GPTMCTL), offset 0x00C */
+
+#define TIMER_GPTMCTL_TAEN_SHIFT         0    /* Bits 0:   GPTM Timer A Enable */
+#define TIMER_GPTMCTL_TAEN_MASK          (0x01 << TIMER_GPTMCTL_TAEN_SHIFT)
+#define TIMER_GPTMCTL_TASTALL_SHIFT      1    /* Bits 1:   GPTM Timer A Stall Enable */
+#define TIMER_GPTMCTL_TASTALL_MASK       (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT)
+
+/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */
+
+#define TIMER_GPTMIMR_TATOIM_SHIFT       0    /* Bits 0:   GPTM Timer A Time-Out Interrupt Mask */
+#define TIMER_GPTMIMR_TATOIM_MASK        (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT)
+
+/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */
+
+#define TIMER_GPTMRIS_TATORIS_SHIFT      0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt */
+#define TIMER_GPTMRIS_TATORIS_MASK       (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT)
+
+/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */
+
+#define TIMER_GPTMICR_TATOCINT_SHIFT     0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt Clear*/
+#define TIMER_GPTMICR_TATOCINT_MASK      (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm/chip/lm3s_uart.h
new file mode 100644
index 000000000..98dcbce12
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_uart.h
@@ -0,0 +1,347 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_uart.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* UART register offsets ************************************************************/
+
+#define LM3S_UART_DR_OFFSET        0x000 /* UART Data */
+#define LM3S_UART_RSR_OFFSET       0x004 /* UART Receive Status */
+#define LM3S_UART_ECR_OFFSET       0x004 /* UART Error Clear */
+#define LM3S_UART_FR_OFFSET        0x018 /* UART Flag */
+#define LM3S_UART_ILPR_OFFSET      0x020 /* UART IrDA Low-Power Register */
+#define LM3S_UART_IBRD_OFFSET      0x024 /* UART Integer Baud-Rate Divisor*/
+#define LM3S_UART_FBRD_OFFSET      0x028 /* UART Fractional Baud-Rate Divisor */
+#define LM3S_UART_LCRH_OFFSET      0x02c /* UART Line Control */
+#define LM3S_UART_CTL_OFFSET       0x030 /* UART Control */
+#define LM3S_UART_IFLS_OFFSET      0x034 /* UART Interrupt FIFO Level Select */
+#define LM3S_UART_IM_OFFSET        0x038 /* UART Interrupt Mask */
+#define LM3S_UART_RIS_OFFSET       0x03c /* UART Raw Interrupt Status */
+#define LM3S_UART_MIS_OFFSET       0x040 /* UART Masked Interrupt Status */
+#define LM3S_UART_ICR_OFFSET       0x044 /* UART Interrupt Clear */
+#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
+#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
+#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
+#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
+#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
+#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
+#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
+#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
+#define LM3S_UART_PCELLID0_OFFSET  0xff0 /* UART PrimeCell Identification 0 */
+#define LM3S_UART_PCELLID1_OFFSET  0xff4 /* UART PrimeCell Identification 1 */
+#define LM3S_UART_PCELLID2_OFFSET  0xff8 /* UART PrimeCell Identification 2 */
+#define LM3S_UART_PCELLID3_OFFSET  0xffc /* UART PrimeCell Identification 3 */
+
+/* UART register addresses **********************************************************/
+
+#define LM3S_UART_BASE(n)          (LM3S_UART0_BASE + (n)*0x01000)
+
+#define LM3S_UART_DR(n)            (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
+#define LM3S_UART_RSR(n)           (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART_ECR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART_FR(n)            (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
+#define LM3S_UART_ILPR(n)          (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART_IBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART_FBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART_LCRH(n)          (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART_CTL(n)           (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART_IFLS(n)          (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART_IM(n)            (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
+#define LM3S_UART_RIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART_MIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART_ICR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART_PERIPHID4(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART_PERIPHID5(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART_PERIPHID6(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART_PERIPHID7(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART_PERIPHID0(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART_PERIPHID1(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART_PERIPHID2(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART_PERIPHID3(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART_PCELLID0(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART_PCELLID1(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART_PCELLID2(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART_PCELLID3(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
+
+#define LM3S_UART0_DR              (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
+#define LM3S_UART0_RSR             (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART0_ECR             (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART0_FR              (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
+#define LM3S_UART0_ILPR            (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART0_IBRD            (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART0_FBRD            (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART0_LCRH            (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART0_CTL             (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART0_IFLS            (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART0_IM              (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
+#define LM3S_UART0_RIS             (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART0_MIS             (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART0_ICR             (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART0_PERIPHID4       (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART0_PERIPHID5       (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART0_PERIPHID6       (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART0_PERIPHID7       (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART0_PERIPHID0       (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART0_PERIPHID1       (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART0_PERIPHID2       (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART0_PERIPHID3       (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART0_PCELLID0        (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART0_PCELLID1        (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART0_PCELLID2        (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART0_PCELLID3        (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
+
+#define LM3S_UART1_DR              (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
+#define LM3S_UART1_RSR             (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART1_ECR             (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART1_FR              (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
+#define LM3S_UART1_ILPR            (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART1_IBRD            (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART1_FBRD            (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART1_LCRH            (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART1_CTL             (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART1_IFLS            (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART1_IM              (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
+#define LM3S_UART1_RIS             (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART1_MIS             (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART1_ICR             (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART1_PERIPHID4       (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART1_PERIPHID5       (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART1_PERIPHID6       (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART1_PERIPHID7       (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART1_PERIPHID0       (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART1_PERIPHID1       (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART1_PERIPHID2       (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART1_PERIPHID3       (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART1_PCELLID0        (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART1_PCELLID1        (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART1_PCELLID2        (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART1_PCELLID3        (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
+
+/* UART register bit settings *******************************************************/
+
+/* UART Data (DR), offset 0x000 */
+
+#define UART_DR_DATA_SHIFT         0         /* Bits 7-0: Data Transmitted or Received */
+#define UART_DR_DATA_MASK          (0xff << UART_DR_DATA_SHIFT)
+#define UART_DR_FE                 (1 << 8)  /* Bit 8:  UART Framing Error */
+#define UART_DR_PE                 (1 << 9)  /* Bit 9:  UART Parity Error */
+#define UART_DR_BE                 (1 << 10) /* Bit 10: UART Break Error */
+#define UART_DR_OE                 (1 << 11) /* Bit 11: UART Overrun Error */
+
+/* UART Receive Status (RSR), offset 0x004 */
+
+#define UART_RSR_FE                (1 << 0)  /* Bit 0:  UART Framing Error */
+#define UART_RSR_PE                (1 << 1)  /* Bit 1:  UART Parity Error */
+#define UART_RSR_BE                (1 << 2)  /* Bit 2:  UART Break Error */
+#define UART_RSR_OE                (1 << 3)  /* Bit 3:  UART Overrun Error */
+
+/* UART Error Clear (ECR), offset 0x004 */
+/* Writing any value to this register clears pending error indications */
+
+/* UART Flag (FR), offset 0x018 */
+
+#define UART_FR_BUSY               (1 << 3)  /* Bit 3:  UART Busy */
+#define UART_FR_RXFE               (1 << 4)  /* Bit 4:  UART Receive FIFO Empty */
+#define UART_FR_TXFF               (1 << 5)  /* Bit 5:  UART Transmit FIFO Full */
+#define UART_FR_RXFF               (1 << 6)  /* Bit 6:  UART Receive FIFO Full */
+#define UART_FR_TXFE               (1 << 7)  /* Bit 7:  UART Transmit FIFO Empty */
+
+/* UART IrDA Low-Power Register (ILPR), offset 0x020 */
+
+#define UART_ILPR_DVSR_MASK        (0xff)    /* Bits 7-0: IrDA Low-Power Divisor */
+
+/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */
+
+#define UART_IBRD_DIVINT_MASK      (0xffff)  /* Bits 15-0: Integer Baud-Rate Divisor */
+
+/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */
+
+#define UART_FBRD_DIVFRAC_MASK     (0x3f)    /* Bits 5-0: Fractional Baud-Rate Divisor */
+
+/* Register 7: UART Line Control (LCRH), offset 0x02C */
+
+#define UART_LCRH_BRK              (1 << 0)  /* Bit 0:  UART Send Break */
+#define UART_LCRH_PEN              (1 << 1)  /* Bit 1:  UART Parity Enable */
+#define UART_LCRH_EPS              (1 << 2)  /* Bit 2:  UART Even Parity Select */
+#define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
+#define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
+#define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
+#define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
+#  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
+#  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
+#  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
+#  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
+#define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
+
+/* UART Control (CTL), offset 0x030 */
+
+#define UART_CTL_UARTEN            (1 << 0)  /* Bit 0:  UART Enable */
+#define UART_CTL_SIREN             (1 << 1)  /* Bit 1:  UART SIR Enable */
+#define UART_CTL_SIRLP             (1 << 2)  /* Bit 2:  UART SIR Low Power Mode */
+#define UART_CTL_LBE               (1 << 7)  /* Bit 7:  UART Loop Back Enable */
+#define UART_CTL_TXE               (1 << 8)  /* Bit 8:  UART Transmit Enable */
+#define UART_CTL_RXE               (1 << 9)  /* Bit 9:  UART Receive Enable */
+
+/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */
+
+#define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */
+#define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
+#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+#define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 5-3: UART Receive Interrupt FIFO Level Select */
+#define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
+#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
+
+/* UART Interrupt Mask (IM), offset 0x038 */
+
+#define UART_IM_RXIM               (1 << 4)  /* Bit 4:  UART Receive Interrupt Mask */
+#define UART_IM_TXIM               (1 << 5)  /* Bit 5:  UART Transmit Interrupt Mask */
+#define UART_IM_RTIM               (1 << 6)  /* Bit 6:  UART Receive Time-Out Interrupt Mask */
+#define UART_IM_FEIM               (1 << 7)  /* Bit 7:  UART Framing Error Interrupt Mask */
+#define UART_IM_PEIM               (1 << 8)  /* Bit 8:  UART Parity Error Interrupt Mask */
+#define UART_IM_BEIM               (1 << 9)  /* Bit 9:  UART Break Error Interrupt Mask */
+#define UART_IM_OEIM               (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */
+
+
+/* UART Raw Interrupt Status (RIS), offset 0x03c */
+
+#define UART_RIS_RXRIS             (1 << 4)  /* Bit 4:  UART Receive Raw Interrupt Status */
+#define UART_RIS_TXRIS             (1 << 5)  /* Bit 5:  UART Transmit Raw Interrupt Status */
+#define UART_RIS_RTRIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Raw Interrupt Status */
+#define UART_RIS_FERIS             (1 << 7)  /* Bit 7:  UART Framing Error Raw Interrupt Status */
+#define UART_RIS_PERIS             (1 << 8)  /* Bit 8:  UART Parity Error Raw Interrupt Status */
+#define UART_RIS_BERIS             (1 << 9)  /* Bit 9:  UART Break Error Raw Interrupt Status */
+#define UART_RIS_OERIS             (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */
+
+/* UART Masked Interrupt Status (MIS), offset 0x040 */
+
+#define UART_MIS_RXMIS             (1 << 4)  /* Bit 4:  UART Receive Masked Interrupt Status */
+#define UART_MIS_TXMIS             (1 << 5)  /* Bit 5:  UART Transmit Masked Interrupt Status */
+#define UART_MIS_RTMIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Masked Interrupt Status */
+#define UART_MIS_FEMIS             (1 << 7)  /* Bit 7:  UART Framing Error Masked Interrupt Status */
+#define UART_MIS_PEMIS             (1 << 8)  /* Bit 8:  UART Parity Error Masked Interrupt Status */
+#define UART_MIS_BEMIS             (1 << 9)  /* Bit 9:  UART Break Error Masked Interrupt Status */
+#define UART_MIS_OEMIS             (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */
+
+/* UART Interrupt Clear (ICR), offset 0x044 */
+
+#define UART_ICR_RXIC             (1 << 4)  /* Bit 4:  Receive Interrupt Clear */
+#define UART_ICR_TXIC             (1 << 5)  /* Bit 5:  Transmit Interrupt Clear */
+#define UART_ICR_RTIC             (1 << 6)  /* Bit 6:  Receive Time-Out Interrupt Clear */
+#define UART_ICR_FEIC             (1 << 7)  /* Bit 7:  Framing Error Interrupt Clear */
+#define UART_ICR_PEIC             (1 << 8)  /* Bit 8:  Parity Error Interrupt Clear */
+#define UART_ICR_BEIC             (1 << 9)  /* Bit 9:  Break Error Interrupt Clear */
+#define UART_ICR_OEIC             (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
+ */
+
+/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
+
+#define UART_PERIPHID4_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
+
+/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
+
+#define UART_PERIPHID5_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
+
+/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
+
+#define UART_PERIPHID6_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
+
+/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
+
+#define UART_PERIPHID7_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
+
+/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
+
+#define UART_PERIPHID0_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
+
+/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
+
+#define UART_PERIPHID1_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
+
+/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
+
+#define UART_PERIPHID2_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
+
+/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
+
+#define UART_PERIPHID3_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
+
+/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
+
+#define UART_CELLID0_MASK         (0xff)    /* UART PrimeCell ID Register[7:0] */
+
+/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
+
+#define UART_CELLID1_MASK         (0xff)    /* UART PrimeCell ID Register[15:8] */
+
+/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
+
+#define UART_CELLID02MASK         (0xff)    /* UART PrimeCell ID Register[23:16] */
+
+/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
+
+#define UART_CELLID3_MASK         (0xff)    /* UART PrimeCell ID Register[31:24] */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h
new file mode 100644
index 000000000..530ecdf64
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h
@@ -0,0 +1,69 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_memorymap.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the memory map file for the specific Stellaris chip */
+
+#ifdef CONFIG_ARCH_CHIP_LM3S
+#  include "chip/lm3s_memorymap.h"
+#else
+#  error "Unsupported Stellaris memory map"
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h
new file mode 100644
index 000000000..b8154dd9f
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h
@@ -0,0 +1,69 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_pinmap.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the memory map file for the specific Stellaris chip */
+
+#ifdef CONFIG_ARCH_CHIP_LM3S
+#  include "chip/lm3s_pinmap.h"
+#else
+#  error "Unsupported Stellaris PIN mapping"
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H */
diff --git a/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c
new file mode 100644
index 000000000..a84dc59dd
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c
@@ -0,0 +1,167 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_dumpgpio.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lm_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* NOTE: this is duplicated in lm3s_gpio.c */
+
+#ifdef LM3S_GPIOH_BASE
+static const uint32_t g_gpiobase[8] =
+{
+  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
+  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
+};
+
+static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#else
+static const uint32_t g_gpiobase[8] =
+{
+  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
+  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
+};
+
+static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_gpiobaseaddress
+ *
+ * Description:
+ *   Given a GPIO enumeration value, return the base address of the
+ *   associated GPIO registers.
+ *
+ ****************************************************************************/
+
+static inline uint32_t lm3s_gpiobaseaddress(int port)
+{
+  return g_gpiobase[port & 7];
+}
+
+/****************************************************************************
+ * Name: lm3s_gpioport
+ *
+ * Description:
+ *   Given a GPIO enumeration value, return the base address of the
+ *   associated GPIO registers.
+ *
+ ****************************************************************************/
+
+static inline uint8_t lm3s_gpioport(int port)
+{
+  return g_portchar[port & 7];
+}
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  lm3s_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the provided base address
+ *
+ ****************************************************************************/
+
+int lm3s_dumpgpio(uint32_t pinset, const char *msg)
+{
+  irqstate_t   flags;
+  unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  uint32_t     base;
+  uint32_t     rcgc2;
+  bool         enabled;
+
+  /* Get the base address associated with the GPIO port */
+
+  base = lm3s_gpiobaseaddress(port);
+  DEBUGASSERT(base != 0);
+
+  /* The following requires exclusive access to the GPIO registers */
+
+  flags   = irqsave();
+  rcgc2   = getreg32(LM3S_SYSCON_RCGC2);
+  enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
+
+  lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
+        lm3s_gpioport(port), pinset, base, msg);
+  lldbg("  RCGC2: %08x (%s)\n",
+        rcgc2, enabled ? "enabled" : "disabled" );
+
+  /* Don't bother with the rest unless the port is enabled */
+
+  if (enabled)
+    {
+      lldbg("  AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
+            getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET),
+            getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc));
+      lldbg("  IS:    %02x IBE: %02x IEV: %02x IM:  %02x RIS: %08x MIS: %08x\n",
+            getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET),
+            getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET));
+      lldbg("  2MA:   %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
+            getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET),
+            getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET),
+            getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET),
+            getreg32(base + LM3S_GPIO_SLR_OFFSET));
+    }
+  irqrestore(flags);
+  return OK;
+}
diff --git a/nuttx/arch/arm/src/lm/lm3s_ethernet.c b/nuttx/arch/arm/src/lm/lm3s_ethernet.c
new file mode 100644
index 000000000..f6edab5ae
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_ethernet.c
@@ -0,0 +1,1472 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_ethernet.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#if defined(CONFIG_NET) && defined(CONFIG_LM3S_ETHERNET)
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <time.h>
+#include <string.h>
+#include <debug.h>
+#include <wdog.h>
+#include <errno.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+#include <nuttx/net/uip/uip.h>
+#include <nuttx/net/uip/uip-arp.h>
+#include <nuttx/net/uip/uip-arch.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "lm_gpio.h"
+#include "lm_ethernet.h"
+#include "chip/lm_pinmap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Half duplex can be forced if CONFIG_LM3S_ETHHDUPLEX is defined. */
+
+#ifdef CONFIG_LM3S_ETHHDUPLEX
+#  define LM3S_DUPLEX_SETBITS 0
+#  define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
+#else 
+#  define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX
+#  define LM3S_DUPLEX_CLRBITS 0
+#endif
+
+/* Auto CRC generation can be suppressed if CONFIG_LM3S_ETHNOAUTOCRC is definde */
+
+#ifdef CONFIG_LM3S_ETHNOAUTOCRC
+#  define LM3S_CRC_SETBITS 0
+#  define LM3S_CRC_CLRBITS MAC_TCTL_CRC
+#else 
+#  define LM3S_CRC_SETBITS MAC_TCTL_CRC
+#  define LM3S_CRC_CLRBITS 0
+#endif
+
+/* Tx padding can be suppressed if CONFIG_LM3S_ETHNOPAD is defined */
+
+#ifdef CONFIG_LM3S_ETHNOPAD
+#  define LM3S_PADEN_SETBITS 0
+#  define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN
+#else 
+#  define LM3S_PADEN_SETBITS MAC_TCTL_PADEN
+#  define LM3S_PADEN_CLRBITS 0
+#endif
+
+#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS)
+#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS)
+
+/* Multicast frames can be enabled by defining CONFIG_LM3S_MULTICAST */
+
+#ifdef CONFIG_LM3S_MULTICAST
+#  define LM3S_AMUL_SETBITS MAC_RCTL_AMUL
+#  define LM3S_AMUL_CLRBITS 0
+#else 
+#  define LM3S_AMUL_SETBITS 0
+#  define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL
+#endif
+
+/* Promiscuous mode can be enabled by defining CONFIG_LM3S_PROMISCUOUS */
+
+#ifdef CONFIG_LM3S_PROMISCUOUS
+#  define LM3S_PRMS_SETBITS MAC_RCTL_PRMS
+#  define LM3S_PRMS_CLRBITS 0
+#else 
+#  define LM3S_PRMS_SETBITS 0
+#  define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS
+#endif
+
+/* Bad CRC rejection can be enabled by define CONFIG_LM3S_BADCRC */
+
+#ifdef CONFIG_LM3S_BADCRC
+#  define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC
+#  define LM3S_BADCRC_CLRBITS 0
+#else 
+#  define LM3S_BADCRC_SETBITS 0
+#  define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC
+#endif
+
+#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS)
+#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS)
+
+/* CONFIG_LM3S_DUMPPACKET will dump the contents of each packet to the console. */
+
+#ifdef CONFIG_LM3S_DUMPPACKET
+#  define lm3s_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
+#else
+#  define lm3s_dumppacket(m,a,n)
+#endif
+
+/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
+
+#define LM3S_WDDELAY   (1*CLK_TCK)
+#define LM3S_POLLHSEC  (1*2)
+
+/* TX timeout = 1 minute */
+
+#define LM3S_TXTIMEOUT (60*CLK_TCK)
+
+/* This is a helper pointer for accessing the contents of the Ethernet header */
+
+#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf)
+
+#define LM32S_MAX_MDCCLK 2500000
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* EMAC statistics (debug only) */
+
+#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
+struct lm3s_statistics_s
+{
+  uint32_t rx_int;         /* Number of Rx interrupts received */
+  uint32_t rx_packets;     /* Number of packets received (sum of the following): */
+  uint32_t rx_ip;          /*   Number of Rx IP packets received */
+  uint32_t rx_arp;         /*   Number of Rx ARP packets received */
+  uint32_t rx_dropped;     /*   Number of dropped, unsupported Rx packets */
+  uint32_t rx_pktsize;     /*   Number of dropped, too small or too big */
+  uint32_t rx_errors;      /* Number of Rx errors (reception error) */
+  uint32_t rx_ovrerrors;   /* Number of Rx FIFO overrun errors */
+  uint32_t tx_int;         /* Number of Tx interrupts received */
+  uint32_t tx_packets;     /* Number of Tx packets queued */
+  uint32_t tx_errors;      /* Number of Tx errors (transmission error)*/
+  uint32_t tx_timeouts;    /* Number of Tx timeout errors */
+};
+#  define EMAC_STAT(priv,name) priv->ld_stat.name++
+#else
+#  define EMAC_STAT(priv,name)
+#endif
+
+/* The lm3s_driver_s encapsulates all state information for a single hardware
+ * interface
+ */
+
+struct lm3s_driver_s
+{
+  /* The following fields would only be necessary on chips that support
+   * multiple Ethernet controllers.
+   */
+
+#if LM3S_NETHCONTROLLERS > 1
+  uint32_t ld_base;             /* Ethernet controller base address */
+  int      ld_irq;              /* Ethernet controller IRQ */
+#endif
+
+  bool     ld_bifup;           /* true:ifup false:ifdown */
+  WDOG_ID  ld_txpoll;          /* TX poll timer */
+  WDOG_ID  ld_txtimeout;       /* TX timeout timer */
+
+#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
+  struct lm3s_statistics_s ld_stat;
+#endif
+
+  /* This holds the information visible to uIP/NuttX */
+
+  struct uip_driver_s ld_dev;  /* Interface understood by uIP */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct lm3s_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS];
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Miscellaneous low level helpers */
+
+#if LM3S_NETHCONTROLLERS > 1
+static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset);
+static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value);
+#else
+static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset);
+static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value);
+#endif
+static void lm3s_ethreset(struct lm3s_driver_s *priv);
+#if 0 /* Not used */
+static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value);
+#endif
+static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr);
+
+/* Common TX logic */
+
+static int  lm3s_transmit(struct lm3s_driver_s *priv);
+static int  lm3s_uiptxpoll(struct uip_driver_s *dev);
+
+/* Interrupt handling */
+
+static void lm3s_receive(struct lm3s_driver_s *priv);
+static void lm3s_txdone(struct lm3s_driver_s *priv);
+static int  lm3s_interrupt(int irq, FAR void *context);
+
+/* Watchdog timer expirations */
+
+static void lm3s_polltimer(int argc, uint32_t arg, ...);
+static void lm3s_txtimeout(int argc, uint32_t arg, ...);
+
+/* NuttX callback functions */
+
+static int  lm3s_ifup(struct uip_driver_s *dev);
+static int  lm3s_ifdown(struct uip_driver_s *dev);
+static int  lm3s_txavail(struct uip_driver_s *dev);
+#ifdef CONFIG_NET_IGMP
+static int  lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
+static int  lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: lm3s_ethin
+ *
+ * Description:
+ *   Read a register from the Ethernet module
+ *
+ * Parameters:
+ *   priv   - Reference to the driver state structure
+ *   offset - Byte offset of the register from the ethernet base address
+ *
+ * Returned Value:
+ *   Register value
+ *
+ ****************************************************************************/
+
+#if LM3S_NETHCONTROLLERS > 1
+static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset)
+{
+  return getreg32(priv->ld_base + offset);
+}
+#else
+static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset)
+{
+  return getreg32(LM3S_ETHCON_BASE + offset);
+}
+#endif
+
+/****************************************************************************
+ * Function: lm3s_ethout
+ *
+ * Description:
+ *   Write a register to the Ethernet module
+ *
+ * Parameters:
+ *   priv   - Reference to the driver state structure
+ *   offset - Byte offset of the register from the ethernet base address
+ *   value  - The value to write the Ethernet register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if LM3S_NETHCONTROLLERS > 1
+static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, priv->ld_base + offset);
+}
+#else
+static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, LM3S_ETHCON_BASE + offset);
+}
+#endif
+
+/****************************************************************************
+ * Function: lm3s_ethreset
+ *
+ * Description:
+ *   Configure and reset the Ethernet module, leaving it in a disabled state.
+ *
+ * Parameters:
+ *   priv   - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm3s_ethreset(struct lm3s_driver_s *priv)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+#if LM3S_NETHCONTROLLERS > 1
+#  error "If multiple interfaces are supported, this function would have to be redesigned"
+#endif
+
+  /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
+
+  flags   = irqsave();
+  regval  = getreg32(LM3S_SYSCON_RCGC2);
+  regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
+  putreg32(regval, LM3S_SYSCON_RCGC2);
+  nllvdbg("RCGC2: %08x\n", regval);
+
+  /* Put the Ethernet controller into the reset state */
+
+  regval = getreg32(LM3S_SYSCON_SRCR2);
+  regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
+  putreg32(regval, LM3S_SYSCON_SRCR2);
+
+  /* Wait just a bit.  This is a much longer delay than necessary */
+
+  up_mdelay(2);
+
+  /* Then take the Ethernet controller out of the reset state */
+
+  regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
+  putreg32(regval, LM3S_SYSCON_SRCR2);
+  nllvdbg("SRCR2: %08x\n", regval);
+
+  /* Wait just a bit, again.  If we touch the ethernet too soon, we may busfault. */
+
+  up_mdelay(2);
+
+  /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */
+
+#ifdef CONFIG_LM3S_ETHLEDS
+  /* Configure the pins for the peripheral function */
+
+  lm3s_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
+  lm3s_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
+#endif
+
+  /* Disable all Ethernet controller interrupts */
+
+  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval &= ~MAC_IM_ALLINTS;
+  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+
+  /* Clear any pending interrupts (shouldn't be any) */
+
+  regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
+  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Function: lm3s_phywrite
+ *
+ * Description:
+ *   Write a 16-bit word to a PHY register
+ *
+ * Parameters:
+ *   priv    - Reference to the driver state structure
+ *   regaddr - Address of the PHY register to write
+ *   value   - The value to write to the register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if 0 /* Not used */
+static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value)
+{
+  /* Wait for any MII transactions in progress to complete */
+
+  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+
+  /* Set up the data to be written */
+
+  DEBUGASSERT(value < MAC_MTXD_MASK);
+  lm3s_ethout(priv, LM3S_MAC_MTXD_OFFSET, value);
+
+  /* Set up the PHY register address and start the write operation */
+
+  regaddr <<= MAC_MCTL_REGADR_SHIFT;
+  DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
+  lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
+
+  /* Wait for the write transaction to complete */
+
+  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+}
+#endif
+
+/****************************************************************************
+ * Function: lm3s_phyread
+ *
+ * Description:
+ *   Write a 16-bit word to a PHY register
+ *
+ * Parameters:
+ *   priv    - Reference to the driver state structure
+ *   regaddr - Address of the PHY register to write
+ *   value   - The value to write to the register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr)
+{
+  /* Wait for any MII transactions in progress to complete */
+
+  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+
+  /* Set up the PHY register address and start the read operation */
+
+  regaddr <<= MAC_MCTL_REGADR_SHIFT;
+  DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
+  lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
+
+  /* Wait for the write transaction to complete */
+
+  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+
+  /* Read and return the PHY data */
+
+  return (uint16_t)(lm3s_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
+}
+
+/****************************************************************************
+ * Function: lm3s_transmit
+ *
+ * Description:
+ *   Start hardware transmission.  Called either from the txdone interrupt
+ *   handling or from watchdog based polling.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int lm3s_transmit(struct lm3s_driver_s *priv)
+{
+  irqstate_t flags;
+  uint32_t   regval;
+  uint8_t   *dbuf;
+  int        pktlen;
+  int        bytesleft;
+  int        ret = -EBUSY;
+
+  /* Verify that the hardware is ready to send another packet */
+
+  flags = irqsave();
+  if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+    {
+      /* Increment statistics */
+
+      EMAC_STAT(priv, tx_packets);
+      lm3s_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
+
+      /* Transfer the packet into the Tx FIFO.  The LS 16-bits of the first
+       * 32-bit word written to the Tx FIFO contains the Ethernet payload
+       * data length.  That is the full length of the message (d_len) minus
+       * the size of the Ethernet header (14).
+       */
+
+      pktlen     = priv->ld_dev.d_len;
+      nllvdbg("Sending packet, pktlen: %d\n", pktlen);
+      DEBUGASSERT(pktlen > UIP_LLH_LEN);
+
+      dbuf       = priv->ld_dev.d_buf;
+      regval     = (uint32_t)(pktlen - 14);
+      regval    |= ((uint32_t)(*dbuf++) << 16);
+      regval    |= ((uint32_t)(*dbuf++) << 24);
+      lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
+
+      /* Write all of the whole, 32-bit values in the middle of the packet */
+
+      for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4)
+        {
+          /* Transfer a whole word from the user buffer.  Note, the user
+           * buffer may be un-aligned.
+           */
+
+          lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
+        }
+
+      /* Write the last, partial word in the FIFO */
+
+      if (bytesleft > 0)
+        {
+          /* Write the last word */
+
+          regval = 0;
+          switch (bytesleft)
+            {
+              case 0:
+              default:
+                break;
+
+              case 3:
+                regval |= ((uint32_t)dbuf[2] << 16);
+              case 2:
+                regval |= ((uint32_t)dbuf[1] << 8);
+              case 1:
+                regval |= (uint32_t)dbuf[0];
+                break;
+            }
+          lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
+        }
+
+      /* Activate the transmitter */
+
+      lm3s_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX);
+
+      /* Setup the TX timeout watchdog (perhaps restarting the timer) */
+
+      (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32_t)priv);
+      ret = OK;
+    }
+
+  irqrestore(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Function: lm3s_uiptxpoll
+ *
+ * Description:
+ *   The transmitter is available, check if uIP has any outgoing packets ready
+ *   to send.  This is a callback from uip_poll().  uip_poll() may be called:
+ *
+ *   1. When the preceding TX packet send is complete,
+ *   2. When the preceding TX packet send timesout and the interface is reset
+ *   3. During normal TX polling
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int lm3s_uiptxpoll(struct uip_driver_s *dev)
+{
+  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
+  int ret = OK;
+
+  /* If the polling resulted in data that should be sent out on the network,
+   * the field d_len is set to a value > 0.
+   */
+
+  nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len);
+  if (priv->ld_dev.d_len > 0)
+    {
+      /* Send the packet.  lm3s_transmit() will return zero if the
+       * packet was successfully handled.
+       */
+
+      DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+      uip_arp_out(&priv->ld_dev);
+      ret = lm3s_transmit(priv);
+    }
+
+  /* If zero is returned, the polling will continue until all connections have
+   * been examined.
+   */
+
+  return ret;
+}
+
+/****************************************************************************
+ * Function: lm3s_receive
+ *
+ * Description:
+ *   An interrupt was received indicating the availability of a new RX packet
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm3s_receive(struct lm3s_driver_s *priv)
+{
+  uint32_t regval;
+  uint8_t *dbuf;
+  int      pktlen;
+  int      bytesleft;
+
+  /* Loop while there are incoming packets to be processed */
+
+  while ((lm3s_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
+    {
+      /* Update statistics */
+
+      EMAC_STAT(priv, rx_packets);
+
+      /* Copy the data data from the hardware to priv->ld_dev.d_buf.  Set
+       * amount of data in priv->ld_dev.d_len
+       */
+
+      dbuf = priv->ld_dev.d_buf;
+
+      /* The packet frame length begins in the LS 16-bits of the first
+       * word from the FIFO followed by the Ethernet header beginning
+       * in the MS 16-bits of the first word.
+       *
+       * Pick off the packet length from the first word.  This packet length
+       * includes the len/type field (size 2) and the FCS (size 4).
+       */
+
+      regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
+      pktlen = (int)(regval & 0x0000ffff);
+      nllvdbg("Receiving packet, pktlen: %d\n", pktlen);
+
+      /* Check if the pktlen is valid.  It should be large enough to hold
+       * an Ethernet header and small enough to fit entirely in the I/O
+       * buffer.  Six is subtracted to acount for the 2-byte length/type
+       * and 4 byte FCS that are not copied into the uIP packet.
+       */
+
+      if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6))
+        {
+          int wordlen;
+
+          /* We will have to drop this packet */
+
+          nlldbg("Bad packet size dropped (%d)\n", pktlen);
+          EMAC_STAT(priv, rx_pktsize);
+
+          /* The number of bytes and words left to read is pktlen - 4 (including,
+           * the final, possibly partial word) because we've already read 4 bytes.
+           */
+
+          wordlen = (pktlen - 1) >> 2;
+
+          /* Read and discard the remaining words in the FIFO */
+
+          while (wordlen--)
+            {
+              (void)lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
+            }
+
+          /* Check for another packet */
+
+          continue;
+        }
+
+      /* Save the first two bytes from the first word */
+
+      *dbuf++   = (uint8_t)((regval >> 16) & 0xff);
+      *dbuf++   = (uint8_t)((regval >> 24) & 0xff);
+
+      /* Read all of the whole, 32-bit values in the middle of the packet.
+       * We've already read the length (2 bytes) plus the first two bytes
+       * of data.
+       */
+
+      for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4)
+        {
+          /* Transfer a whole word to the user buffer.  Note, the user
+           * buffer may be un-aligned.
+           */
+
+          *(uint32_t*)dbuf = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
+        }
+
+      /* Handle the last, partial word in the FIFO (0-3 bytes) and discard
+       * the 4-byte FCS.
+       */
+
+      for (; bytesleft > 0; bytesleft -= 4)
+        {
+          /* Read the last word.  And transfer all but the last four
+           * bytes of the FCS into the user buffer.
+           */
+
+          regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
+          switch (bytesleft)
+            {
+              default:
+                break;
+
+              case 7:
+                dbuf[2] = (regval >> 16) & 0xff;
+              case 6:
+                dbuf[1] = (regval >> 8) & 0xff;
+              case 5:
+                dbuf[0] = regval & 0xff;
+                break;
+            }
+        }
+
+      /* Pass the packet length to uIP MINUS 2 bytes for the length and
+       * 4 bytes for the FCS.
+       */
+
+      priv->ld_dev.d_len = pktlen - 6;
+      lm3s_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
+
+      /* We only accept IP packets of the configured type and ARP packets */
+
+#ifdef CONFIG_NET_IPv6
+      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6))
+#else
+      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP))
+#endif
+        {
+          nllvdbg("IP packet received (%02x)\n", ETHBUF->type);
+          EMAC_STAT(priv, rx_ip);
+
+          uip_arp_ipin(&priv->ld_dev);
+          uip_input(&priv->ld_dev);
+
+          /* If the above function invocation resulted in data that should be
+           * sent out on the network, the field  d_len will set to a value > 0.
+           */
+
+          if (priv->ld_dev.d_len > 0)
+            {
+              uip_arp_out(&priv->ld_dev);
+              lm3s_transmit(priv);
+            }
+        }
+      else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP))
+        {
+          nllvdbg("ARP packet received (%02x)\n", ETHBUF->type);
+          EMAC_STAT(priv, rx_arp);
+
+          uip_arp_arpin(&priv->ld_dev);
+
+          /* If the above function invocation resulted in data that should be
+           * sent out on the network, the field  d_len will set to a value > 0.
+           */
+
+           if (priv->ld_dev.d_len > 0)
+             {
+               lm3s_transmit(priv);
+             }
+        }
+#ifdef CONFIG_DEBUG
+      else
+        {
+          nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type));
+          EMAC_STAT(priv, rx_dropped);
+        }
+#endif
+    }
+}
+
+/****************************************************************************
+ * Function: lm3s_txdone
+ *
+ * Description:
+ *   An interrupt was received indicating that the last TX packet(s) is done
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm3s_txdone(struct lm3s_driver_s *priv)
+{
+  /* Cancel the TX timeout */
+
+  wd_cancel(priv->ld_txtimeout);
+
+  /* Verify that the Tx FIFO is not in use.  The NEWTX bit initiates an
+   * Ethernet transmission once the packet has been placed in the TX FIFO.
+   * This bit is cleared once the transmission has been completed.  Since
+   * we get here because of of TXEMP which indicates that the packet was
+   * transmitted and that the TX FIFO is empty, NEWTX should always be zero
+   * at this point.
+   */
+
+  DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+
+  /* Then poll uIP for new XMIT data */
+
+  (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
+}
+
+/****************************************************************************
+ * Function: lm3s_interrupt
+ *
+ * Description:
+ *   Hardware interrupt handler
+ *
+ * Parameters:
+ *   irq     - Number of the IRQ that generated the interrupt
+ *   context - Interrupt register state save info (architecture-specific)
+ *
+ * Returned Value:
+ *   OK on success
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int lm3s_interrupt(int irq, FAR void *context)
+{
+  register struct lm3s_driver_s *priv;
+  uint32_t ris;
+
+#if LM3S_NETHCONTROLLERS > 1
+# error "A mechanism to associate and interface with an IRQ is needed"
+#else
+  priv = &g_lm3sdev[0];
+#endif
+
+  /* Read the raw interrupt status register */
+
+  ris = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
+
+  /* Clear all pending interrupts */
+
+  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, ris);
+
+  /* Check for errors */
+
+#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
+  if ((ris & MAC_RIS_TXER) != 0)
+    {
+      EMAC_STAT(priv, tx_errors);      /* Number of Tx errors */
+    }
+
+  if ((ris & MAC_RIS_FOV) != 0)
+    {
+      EMAC_STAT(priv, rx_ovrerrors);   /* Number of Rx FIFO overrun errors */
+    }
+
+  if ((ris & MAC_RIS_RXER) != 0)
+    {
+      EMAC_STAT(priv, rx_errors);      /* Number of Rx errors */
+    }
+#endif
+
+  /* Handle (unmasked) interrupts according to status bit settings */
+
+  ris &= lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
+
+  /* Is this an Rx interrupt (meaning that a packet has been received)? */
+
+  if ((ris & MAC_RIS_RXINT) != 0)
+    {
+      /* Handle the incoming packet */
+
+      EMAC_STAT(priv, rx_int);
+      lm3s_receive(priv);
+    }
+
+  /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */
+
+  if ((ris & MAC_RIS_TXEMP) != 0)
+    {
+       /* Handle the complete of the transmission */
+
+      EMAC_STAT(priv, tx_int);
+      lm3s_txdone(priv);
+    }
+
+  /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if 
+   * there are no pending transmissions).
+   */
+
+  return OK;
+}
+
+/****************************************************************************
+ * Function: lm3s_txtimeout
+ *
+ * Description:
+ *   Our TX watchdog timed out.  Called from the timer interrupt handler.
+ *   The last TX never completed.  Reset the hardware and start again.
+ *
+ * Parameters:
+ *   argc - The number of available arguments
+ *   arg  - The first argument
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm3s_txtimeout(int argc, uint32_t arg, ...)
+{
+  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg;
+
+  /* Increment statistics */
+
+  nlldbg("Tx timeout\n");
+  EMAC_STAT(priv, tx_timeouts);
+
+  /* Then reset the hardware */
+
+  DEBUGASSERT(priv->ld_bifup);
+  lm3s_ifdown(&priv->ld_dev);
+  lm3s_ifup(&priv->ld_dev);
+
+  /* Then poll uIP for new XMIT data */
+
+  (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
+}
+
+/****************************************************************************
+ * Function: lm3s_polltimer
+ *
+ * Description:
+ *   Periodic timer handler.  Called from the timer interrupt handler.
+ *
+ * Parameters:
+ *   argc - The number of available arguments
+ *   arg  - The first argument
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm3s_polltimer(int argc, uint32_t arg, ...)
+{
+  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg;
+
+  /* Check if we can send another Tx packet now.  The NEWTX bit initiates an
+   * Ethernet transmission once the packet has been placed in the TX FIFO.
+   * This bit is cleared once the transmission has been completed.
+   *
+   * NOTE: This can cause missing poll cycles and, hence, some timing
+   * inaccuracies.
+   */
+
+  if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+    {
+      /* If so, update TCP timing states and poll uIP for new XMIT data */
+
+      (void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC);
+
+      /* Setup the watchdog poll timer again */
+
+      (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg);
+    }
+}
+
+/****************************************************************************
+ * Function: lm3s_ifup
+ *
+ * Description:
+ *   NuttX Callback: Bring up the Ethernet interface when an IP address is
+ *   provided 
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int lm3s_ifup(struct uip_driver_s *dev)
+{
+  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
+  irqstate_t flags;
+  uint32_t regval;
+  uint32_t div;
+  uint16_t phyreg;
+
+  nlldbg("Bringing up: %d.%d.%d.%d\n",
+       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
+
+  /* Enable and reset the Ethernet controller */
+
+  flags = irqsave();
+  lm3s_ethreset(priv);
+
+  /* Set the management clock divider register for access to the PHY
+   * register set. The MDC clock is divided down from the system clock per:
+   *
+   *   MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1))
+   *   div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1
+   *
+   * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000.  We will
+   * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded.
+   */
+
+  div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK;
+  lm3s_ethout(priv, LM3S_MAC_MDV_OFFSET, div);
+  nllvdbg("MDV:   %08x\n", div);
+
+  /* Then configure the Ethernet Controller for normal operation 
+   *
+   * Setup the transmit control register (Full duplex, TX CRC Auto Generation,
+   * TX Padding Enabled).
+   */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET);
+  regval &= ~LM3S_TCTCL_CLRBITS;
+  regval |= LM3S_TCTCL_SETBITS;
+  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+  nllvdbg("TCTL:  %08x\n", regval);
+
+  /* Setup the receive control register (Disable multicast frames, disable
+   * promiscuous mode, disable bad CRC rejection).
+   */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval &= ~LM3S_RCTCL_CLRBITS;
+  regval |= LM3S_RCTCL_SETBITS;
+  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  nllvdbg("RCTL:  %08x\n", regval);
+
+  /* Setup the time stamp configuration register */
+
+#ifdef LM3S_ETHTS
+  regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET);
+#ifdef CONFIG_LM3S_TIMESTAMP
+  regval |= MAC_TS_EN;
+#else
+  regval &= ~(MAC_TS_EN);
+#endif
+  lm3s_ethout(priv, LM3S_MAC_TS_OFFSET, regval);
+  nllvdbg("TS:    %08x\n", regval);
+#endif
+
+  /* Wait for the link to come up.  This following is not very conservative
+   * of system resources -- it really should wait gracefully on a semaphore
+   * and the interrupt handler should post the semaphore when LINKSTATUS is
+   * set
+   */
+
+  nlldbg("Waiting for link\n");
+  do
+    {
+      phyreg = lm3s_phyread(priv, MII_MSR);
+    }
+  while ((phyreg & MII_MSR_LINKSTATUS) == 0);
+  nlldbg("Link established\n");
+
+  /* Reset the receive FIFO */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RSTFIFO;
+  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Enable the Ethernet receiver */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RXEN;
+  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Enable the Ethernet transmitter */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET);
+  regval |= MAC_TCTL_TXEN;
+  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+
+  /* Reset the receive FIFO (again) */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RSTFIFO;
+  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Enable the Ethernet interrupt */
+
+#if LM3S_NETHCONTROLLERS > 1
+  up_enable_irq(priv->irq);
+#else
+  up_enable_irq(LM3S_IRQ_ETHCON);
+#endif
+
+  /* Enable the Ethernet RX packet receipt interrupt */
+
+  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval |= MAC_IM_RXINTM;
+  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+
+  /* Program the hardware with it's MAC address (for filtering) */
+
+  regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 |
+           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 |
+           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 |
+           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0];
+  lm3s_ethout(priv, LM3S_MAC_IA0_OFFSET, regval);
+
+  regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 |
+           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4];
+  lm3s_ethout(priv, LM3S_MAC_IA1_OFFSET, regval);
+
+  /* Set and activate a timer process */
+
+  (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, (uint32_t)priv);
+
+  priv->ld_bifup = true;
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: lm3s_ifdown
+ *
+ * Description:
+ *   NuttX Callback: Stop the interface.  The only way to restore normal
+ *   behavior is to call lm3s_ifup().
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int lm3s_ifdown(struct uip_driver_s *dev)
+{
+  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
+  irqstate_t flags;
+  uint32_t regval;
+
+  nlldbg("Taking down: %d.%d.%d.%d\n",
+       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
+
+  /* Cancel the TX poll timer and TX timeout timers */
+
+  flags = irqsave();
+  wd_cancel(priv->ld_txpoll);
+  wd_cancel(priv->ld_txtimeout);
+
+  /* Disable the Ethernet interrupt */
+
+#if LM3S_NETHCONTROLLERS > 1
+  up_disable_irq(priv->irq);
+#else
+  up_disable_irq(LM3S_IRQ_ETHCON);
+#endif
+
+  /* Disable all Ethernet controller interrupt sources */
+
+  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval &= ~MAC_IM_ALLINTS;
+  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+
+  /* Reset the receive FIFO */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RSTFIFO;
+  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Disable the Ethernet receiver */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval &= ~MAC_RCTL_RXEN;
+  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Disable the Ethernet transmitter */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval &= ~MAC_TCTL_TXEN;
+  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+
+  /* Reset the receive FIFO (again) */
+
+  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RSTFIFO;
+  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Clear any pending interrupts */
+
+  regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
+  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
+
+  /* The interface is now DOWN */
+
+  priv->ld_bifup = false;
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: lm3s_txavail
+ *
+ * Description:
+ *   Driver callback invoked when new TX data is available.  This is a 
+ *   stimulus perform an out-of-cycle poll and, thereby, reduce the TX
+ *   latency.
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Called in normal user mode
+ *
+ ****************************************************************************/
+
+static int lm3s_txavail(struct uip_driver_s *dev)
+{
+  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
+  irqstate_t flags;
+
+  /* Ignore the notification if the interface is not yet up or if the Tx FIFO
+   * hardware is not available at this time.  The NEWTX bit initiates an
+   * Ethernet transmission once the packet has been placed in the TX FIFO.
+   * This bit is cleared once the transmission has been completed.  When the
+   * transmission completes, lm3s_txdone() will be called and the Tx polling
+   * will occur at that time.
+   */
+
+  flags = irqsave();
+  if (priv->ld_bifup && (lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+    {
+      /* If the interface is up and we can use the Tx FIFO, then poll uIP
+       * for new Tx data
+       */
+
+      (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
+    }
+
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: lm3s_addmac
+ *
+ * Description:
+ *   NuttX Callback: Add the specified MAC address to the hardware multicast
+ *   address filtering
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *   mac  - The MAC address to be added 
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_IGMP
+static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
+{
+  FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private;
+
+  /* Add the MAC address to the hardware multicast routing table */
+
+#warning "Multicast MAC support not implemented"
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Function: lm3s_rmmac
+ *
+ * Description:
+ *   NuttX Callback: Remove the specified MAC address from the hardware multicast
+ *   address filtering
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *   mac  - The MAC address to be removed 
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_IGMP
+static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
+{
+  FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private;
+
+  /* Add the MAC address to the hardware multicast routing table */
+
+#warning "Multicast MAC support not implemented"
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: lm3s_ethinitialize
+ *
+ * Description:
+ *   Initialize the Ethernet driver for one interface
+ *
+ * Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#if LM3S_NETHCONTROLLERS > 1
+int lm3s_ethinitialize(int intf)
+#else
+static inline int lm3s_ethinitialize(int intf)
+#endif
+{
+  struct lm3s_driver_s *priv = &g_lm3sdev[intf];
+  int ret;
+
+  /* Check if the Ethernet module is present */
+
+  ndbg("Setting up eth%d\n", intf);
+
+#if LM3S_NETHCONTROLLERS > 1
+# error "This debug check only works with one interface"
+#else
+  DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
+#endif
+  DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS);
+
+  /* Initialize the driver structure */
+
+  memset(priv, 0, sizeof(struct lm3s_driver_s));
+  priv->ld_dev.d_ifup    = lm3s_ifup;     /* I/F down callback */
+  priv->ld_dev.d_ifdown  = lm3s_ifdown;   /* I/F up (new IP address) callback */
+  priv->ld_dev.d_txavail = lm3s_txavail;  /* New TX data callback */
+#ifdef CONFIG_NET_IGMP
+  priv->ld_dev.d_addmac  = lm3s_addmac;   /* Add multicast MAC address */
+  priv->ld_dev.d_rmmac   = lm3s_rmmac;    /* Remove multicast MAC address */
+#endif
+  priv->ld_dev.d_private = (void*)priv;   /* Used to recover private state from dev */
+
+  /* Create a watchdog for timing polling for and timing of transmisstions */
+
+#if LM3S_NETHCONTROLLERS > 1
+# error "A mechanism to associate base address an IRQ with an interface is needed"
+  priv->ld_base          = ??;            /* Ethernet controller base address */
+  priv->ld_irq           = ??;            /* Ethernet controller IRQ number */
+#endif
+  priv->ld_txpoll        = wd_create();   /* Create periodic poll timer */
+  priv->ld_txtimeout     = wd_create();   /* Create TX timeout timer */
+
+  /* If the board can provide us with a MAC address, get the address
+   * from the board now.  The MAC will not be applied until lm3s_ifup()
+   * is caleld (and the MAC can be overwritten with a netdev ioctl call). 
+   */
+
+#ifdef CONFIG_LM3S_BOARDMAC
+   lm3s_ethernetmac(&priv->ld_dev.d_mac);
+#endif
+
+  /* Perform minimal, one-time initialization -- just reset the controller and
+   * leave it disabled.  The Ethernet controller will be reset and properly
+   * re-initialized each time lm3s_ifup() is called.
+   */
+
+  lm3s_ethreset(priv);
+  lm3s_ifdown(&priv->ld_dev);
+
+  /* Attach the IRQ to the driver */
+
+#if LM3S_NETHCONTROLLERS > 1
+  ret = irq_attach(priv->irq, lm3s_interrupt);
+#else
+  ret = irq_attach(LM3S_IRQ_ETHCON, lm3s_interrupt);
+#endif
+  if (ret != 0)
+    {
+      /* We could not attach the ISR to the IRQ */
+
+      return -EAGAIN;
+    }
+
+  /* Register the device with the OS so that socket IOCTLs can be performed */
+
+  (void)netdev_register(&priv->ld_dev);
+  return OK;
+}
+
+
+/************************************************************************************
+ * Name: up_netinitialize
+ *
+ * Description:
+ *   Initialize the first network interface.  If there are more than one interface
+ *   in the chip, then board-specific logic will have to provide this function to
+ *   determine which, if any, Ethernet controllers should be initialized.
+ *
+ ************************************************************************************/
+
+#if LM3S_NETHCONTROLLERS == 1
+void up_netinitialize(void)
+{
+  (void)lm3s_ethinitialize(0);
+}
+#endif
+
+#endif /* CONFIG_NET && CONFIG_LM3S_ETHERNET */
+
diff --git a/nuttx/arch/arm/src/lm/lm3s_gpio.c b/nuttx/arch/arm/src/lm/lm3s_gpio.c
new file mode 100644
index 000000000..48cbefabf
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_gpio.c
@@ -0,0 +1,854 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_gpio.c
+ * arch/arm/src/chip/lm3s_gpio.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "lm_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* These definitions are part of the implementation of the  GPIO pad
+ * configuration of Table 9-1 in the LM3S6918 data sheet.
+ */
+
+#define AFSEL_SHIFT            5
+#define AFSEL_1                (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */
+#define AFSEL_0                0
+#define AFSEL_X                0
+
+#define DIR_SHIFT              4
+#define DIR_1                  (1 << DIR_SHIFT)   /* Set/clear bit in GPIO DIR register */
+#define DIR_0                  0
+#define DIR_X                  0
+
+#define ODR_SHIFT              3
+#define ODR_1                  (1 << ODR_SHIFT)   /* Set/clear bit in GPIO ODR register */
+#define ODR_0                  0
+#define ODR_X                  0
+
+#define DEN_SHIFT              2
+#define DEN_1                  (1 << DEN_SHIFT)   /* Set/clear bit in GPIO DEN register */
+#define DEN_0                  0
+#define DEN_X                  0
+
+#define PUR_SHIFT              1
+#define PUR_1                  (1 << PUR_SHIFT)   /* Set/clear bit in GPIO PUR register */
+#define PUR_0                  0
+#define PUR_X                  0
+
+#define PDR_SHIFT              0
+#define PDR_1                  (1 << PDR_SHIFT)   /* Set/clear bit in GPIO PDR register */
+#define PDR_0                  0
+#define PDR_X                  0
+
+#define GPIO_INPUT_SETBITS     (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_INPUT_CLRBITS     (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_OUTPUT_SETBITS    (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_OUTPUT_CLRBITS    (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_ODINPUT_SETBITS   (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_ODINPUT_CLRBITS   (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_ODOUTPUT_SETBITS  (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_ODOUTPUT_CLRBITS  (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_PFODIO_SETBITS    (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_PFODIO_CLRBITS    (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_PFIO_SETBITS      (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_PFIO_CLRBITS      (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_ANINPUT_SETBITS   (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0)
+#define GPIO_ANINPUT_CLRBITS   (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1)
+
+#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct gpio_func_s
+{
+  uint8_t setbits;  /* A set of GPIO register bits to set */
+  uint8_t clrbits;  /* A set of GPIO register bits to clear */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct gpio_func_s g_funcbits[] =
+{
+  {GPIO_INPUT_SETBITS,     GPIO_INPUT_CLRBITS},     /* GPIO_FUNC_INPUT */
+  {GPIO_OUTPUT_SETBITS,    GPIO_OUTPUT_CLRBITS},    /* GPIO_FUNC_OUTPUT */
+  {GPIO_ODINPUT_SETBITS,   GPIO_ODINPUT_CLRBITS},   /* GPIO_FUNC_ODINPUT */
+  {GPIO_ODOUTPUT_SETBITS,  GPIO_ODOUTPUT_CLRBITS},  /* GPIO_FUNC_ODOUTPUT */
+  {GPIO_PFODIO_SETBITS,    GPIO_PFODIO_CLRBITS},    /* GPIO_FUNC_PFODIO */
+  {GPIO_PFIO_SETBITS,      GPIO_PFIO_CLRBITS},      /* GPIO_FUNC_PFIO */
+  {GPIO_ANINPUT_SETBITS,   GPIO_ANINPUT_CLRBITS},   /* GPIO_FUNC_ANINPUT */
+  {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
+};
+
+static const uint32_t g_gpiobase[LM3S_NPORTS] =
+{
+  /* All support LM3S parts have at least 7 ports, GPIOA-G */
+
+  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
+  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE,
+
+  /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
+
+#if LM3S_NPORTS > 7
+  LM3S_GPIOH_BASE,
+#endif
+
+  /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
+
+#if LM3S_NPORTS > 8
+  LM3S_GPIOJ_BASE,
+#endif
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_gpiobaseaddress
+ *
+ * Description:
+ *   Given a GPIO enumeration value, return the base address of the
+ *   associated GPIO registers.
+ *
+ ****************************************************************************/
+
+static uint32_t lm3s_gpiobaseaddress(unsigned int port)
+{
+  uint32_t gpiobase = 0;
+  if (port < LM3S_NPORTS)
+    {
+      gpiobase = g_gpiobase[port];
+    }
+  return gpiobase;
+}
+
+/****************************************************************************
+ * Name: lm3s_gpiofunc
+ *
+ * Description:
+ *   Configure GPIO registers for a specific function
+ *
+ ****************************************************************************/
+
+static void lm3s_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func)
+{
+  uint32_t setbit;
+  uint32_t clrbit;
+  uint32_t regval;
+
+  /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain
+   * control register. Setting a bit in this register enables the open drain
+   * configuration of the corresponding GPIO pad. When open drain mode is enabled,
+   * the corresponding bit should also be set in the GPIO Digital Input Enable
+   * (GPIO DEN) register ... Corresponding bits in the drive strength registers
+   * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the
+   * desired rise and fall times. The GPIO acts as an open drain input if the
+   * corresponding bit in the GPIO DIR register is set to 0; and as an open
+   * drain output when set to 1."
+   */
+
+  setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
+
+  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
+  regval &= ~clrbit;
+  regval |= setbit;
+  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
+
+  /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
+   * register. When a bit is set to 1, it enables a weak pull-up resistor on the
+   * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
+   * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
+   */
+
+  setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno;
+
+  if (setbit || clrbit)
+    {
+      regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
+      regval &= ~clrbit;
+      regval |= setbit;
+      putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
+    }
+
+  /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
+   * register. When a bit is set to 1, it enables a weak pull-down resistor on the
+   * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
+   * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
+   */
+
+  setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno;
+
+  if (setbit || clrbit)
+    {
+      regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
+      regval &= ~clrbit;
+      regval |= setbit;
+      putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
+    }
+
+  /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
+   * register. By default, with the exception of the GPIO signals used for JTAG/SWD
+   * function, all other GPIO signals are configured out of reset to be undriven
+   * (tristate). Their digital function is disabled; they do not drive a logic
+   * value on the pin and they do not allow the pin voltage into the GPIO receiver.
+   * To use the pin in a digital function (either GPIO or alternate function), the
+   * corresponding GPIODEN bit must be set."
+   */
+
+  setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
+
+  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
+  regval &= ~clrbit;
+  regval |= setbit;
+  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
+
+  /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
+   * direction register. Bits set to 1 in the GPIODIR register configure
+   * the corresponding pin to be an output, while bits set to 0 configure the
+   * pins to be inputs. All bits are cleared by a reset, meaning all GPIO
+   * pins are inputs by default.
+   */
+
+  setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
+
+  regval = getreg32(base + LM3S_GPIO_DIR_OFFSET);
+  regval &= ~clrbit;
+  regval |= setbit;
+  putreg32(regval, base + LM3S_GPIO_DIR_OFFSET);
+
+  /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
+   * control select register. Writing a 1 to any bit in this register selects
+   * the hardware control for the corresponding GPIO line. All bits are cleared
+   * by a reset, therefore no GPIO line is set to hardware control by default."
+   *
+   * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit
+   * and unlock the GPIO.  That is not implemented here.
+   */
+
+  setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
+
+  regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET);
+  regval &= ~clrbit;
+  regval |= setbit;
+  putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET);
+}
+
+/****************************************************************************
+ * Name: lm3s_gpiopadstrength
+ *
+ * Description:
+ *   Set up pad strength and pull-ups
+ *
+ ****************************************************************************/
+
+static inline void lm3s_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset)
+{
+  int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT;
+  uint32_t regoffset;
+  uint32_t regval;
+  uint32_t slrset;
+  uint32_t slrclr;
+
+  /* Prepare bits to disable slew */
+
+  slrset = 0;
+  slrclr = pin;
+
+  switch (strength)
+    {
+      case 0: /* 2mA pad drive strength */
+        {
+          /* "The GPIODR2R register is the 2-mA drive control register. It
+           * allows for each GPIO signal in the port to be individually configured
+           * without affecting the other pads. When writing a DRV2 bit for a GPIO
+           * signal, the corresponding DRV4 bit in the GPIO DR4R register and the
+           * DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
+           */
+
+          regoffset = LM3S_GPIO_DR2R_OFFSET;
+        }
+        break;
+
+      case 1: /* 4mA pad drive strength */
+        {
+          /* "The GPIODR4R register is the 4-mA drive control register. It allows
+           * for each GPIO signal in the port to be individually configured without
+           * affecting the other pads. When writing the DRV4 bit for a GPIO signal,
+           * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit
+           * in the GPIO DR8R register are automatically cleared by hardware."
+           */
+
+          regoffset = LM3S_GPIO_DR4R_OFFSET;
+        }
+        break;
+
+      case 3: /* 8mA Pad drive with slew rate control */
+        {
+          /* "The GPIOSLR register is the slew rate control register. Slew rate
+           * control is only available when using the 8-mA drive strength option
+           * via the GPIO 8-mA Drive Select (GPIODR8R) register..."
+           */
+
+          slrset = pin;
+          slrclr = 0;
+        }
+        /* Fall through */
+
+      case 2: /* 8mA pad drive strength (without slew rate control) */
+        {
+          /* "The GPIODR8R register is the 8-mA drive control register. It
+           * allows for each GPIO signal in the port to be individually configured
+           * without affecting the other pads. When writing the DRV8 bit for a GPIO
+           * signal, the corresponding DRV2 bit in the GPIO DR2R register and the
+           * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
+           */
+
+          regoffset = LM3S_GPIO_DR8R_OFFSET;
+        }
+        break;
+    }
+
+  /* Set the selected pad strength and set/clear optional slew rate control */
+
+  regval = getreg32(base + regoffset);
+  regval |= pin;
+  putreg32(regval, base + regoffset);
+
+  regval  = getreg32(base + LM3S_GPIO_SLR_OFFSET);
+  regval &= slrclr;
+  regval |= slrset;
+  putreg32(regval, base + LM3S_GPIO_SLR_OFFSET);
+}
+
+/****************************************************************************
+ * Name: lm3s_gpiopadtype
+ *
+ * Description:
+ *   Set up pad strength and pull-ups.  Some of these values may be over-
+ *   written by lm3s_gpiofunc, depending on the function selection.  Others
+ *   are optional for different function selections.
+ *
+ ****************************************************************************/
+
+static inline void lm3s_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
+{
+  int padtype  = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT;
+#if 0 /* always overwritten by lm3s_gpiofunc */
+  uint32_t odrset;
+  uint32_t odrclr;
+#endif
+  uint32_t purset;
+  uint32_t purclr;
+  uint32_t pdrset;
+  uint32_t pdrclr;
+#if 0 /* always overwritten by lm3s_gpiofunc */
+  uint32_t denset;
+  uint32_t denclr;
+#endif
+  uint32_t regval;
+
+  /* Assume digital GPIO function, push-pull with no pull-up or pull-down */
+
+#if 0 /* always overwritten by lm3s_gpiofunc */
+  odrset = 0;
+  odrclr = pin;
+#endif
+  purset = 0;
+  purclr = pin;
+  pdrset = 0;
+  pdrclr = pin;
+#if 0 /* always overwritten by lm3s_gpiofunc */
+  denset = pin;
+  denclr = 0;
+#endif
+
+  switch (padtype)
+    {
+      case 0: /* Push-pull */
+      default:
+        {
+        }
+        break;
+
+      case 1: /* Push-pull with weak pull-up */
+        {
+          purset = pin;
+          purclr = 0;
+        }
+        break;
+      case 2: /* Push-pull with weak pull-down */
+        {
+          pdrset = pin;
+          pdrclr = 0;
+        }
+        break;
+      case 3: /* Open-drain */
+        {
+#if 0 /* always overwritten by lm3s_gpiofunc */
+          odrset = pin;
+          odrclr = 0;
+#endif
+        }
+        break;
+      case 4: /* Open-drain with weak pull-up */
+        {
+#if 0 /* always overwritten by lm3s_gpiofunc */
+          odrset = pin;
+          odrclr = 0;
+#endif
+          purset = pin;
+          purclr = 0;
+        }
+        break;
+      case 5: /* Open-drain with weak pull-down */
+        {
+#if 0 /* always overwritten by lm3s_gpiofunc */
+          odrset = pin;
+          odrclr = 0;
+#endif
+          pdrset = pin;
+          pdrclr = 0;
+        }
+        break;
+      case 6: /* Analog comparator */
+        {
+#if 0 /* always overwritten by lm3s_gpiofunc */
+          denset = 0;
+          denclr = pin;
+#endif
+        }
+        break;
+    }
+
+  /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain
+   * control register. Setting a bit in this register enables the open drain
+   * configuration of the corresponding GPIO pad. When open drain mode is enabled,
+   * the corresponding bit should also be set in the GPIO Digital Input Enable
+   * (GPIO DEN) register ... Corresponding bits in the drive strength registers
+   * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the
+   * desired rise and fall times. The GPIO acts as an open drain input if the
+   * corresponding bit in the GPIO DIR register is set to 0; and as an open
+   * drain output when set to 1."
+   */
+
+#if 0 /* always overwritten by lm3s_gpiofunc */
+  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
+  regval &= ~odrclr;
+  regval |= odrset;
+  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
+#endif
+
+  /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
+   * register. When a bit is set to 1, it enables a weak pull-up resistor on the
+   * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
+   * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
+   */
+
+  regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
+  regval &= ~purclr;
+  regval |= purset;
+  putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
+
+  /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
+   * register. When a bit is set to 1, it enables a weak pull-down resistor on the
+   * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
+   * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
+   */
+
+  regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
+  regval &= ~pdrclr;
+  regval |= pdrset;
+  putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
+
+  /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
+   * register. By default, with the exception of the GPIO signals used for JTAG/SWD
+   * function, all other GPIO signals are configured out of reset to be undriven
+   * (tristate). Their digital function is disabled; they do not drive a logic
+   * value on the pin and they do not allow the pin voltage into the GPIO receiver.
+   * To use the pin in a digital function (either GPIO or alternate function), the
+   * corresponding GPIODEN bit must be set."
+   */
+
+#if 0 /* always overwritten by lm3s_gpiofunc */
+  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
+  regval &= ~denclr;
+  regval |= denset;
+  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
+#endif
+}
+
+/****************************************************************************
+ * Name: lm3s_initoutput
+ *
+ * Description:
+ *   Set the GPIO output value
+ *
+ ****************************************************************************/
+
+static inline void lm3s_initoutput(uint32_t cfgset)
+{
+  bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO);
+  lm3s_gpiowrite(cfgset, value);
+}
+
+/****************************************************************************
+ * Name: lm3s_interrupt
+ *
+ * Description:
+ *   Configure the interrupt pin.
+ *
+ ****************************************************************************/
+
+static inline void lm3s_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
+{
+  int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT;
+  uint32_t regval;
+  uint32_t isset;
+  uint32_t isclr;
+  uint32_t ibeset;
+  uint32_t ibeclr;
+  uint32_t iveset;
+  uint32_t iveclr;
+
+  /* Mask and clear the GPIO interrupt
+   *
+   * "The GPIOIM register is the interrupt mask register. Bits set to High in
+   * GPIO IM allow the corresponding pins to trigger their individual interrupts
+   * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering
+   * on that pin. All bits are cleared by a reset."
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+  regval &= ~pin;
+  putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+
+  /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
+   * in this register clears the corresponding interrupt edge detection logic
+   * register. Writing a 0 has no effect."
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_ICR_OFFSET);
+  regval |= pin;
+  putreg32(regval, base + LM3S_GPIO_ICR_OFFSET);
+
+  /* Assume rising edge */
+
+  isset  = 0;            /* Not level sensed */
+  isclr  = pin;
+  ibeset = 0;            /* Single edge */
+  ibeclr = pin;
+  iveset = pin;          /* Rising edge or high levels*/
+  iveclr = 0;
+
+  /* Then handle according to the selected interrupt type */
+
+  switch (inttype)
+    {
+      case 0:            /* Interrupt on falling edge */
+        {
+          iveset = 0;    /* Falling edge or low levels*/
+          iveclr = pin;
+        }
+        break;
+
+      case 1:           /* Interrupt on rising edge */
+      default:
+        break;
+
+      case 2:           /* Interrupt on both edges */
+        {
+          ibeset = pin; /* Both edges */
+          ibeclr = 0;
+        }
+        break;
+
+      case 3:           /* Interrupt on low level */
+        {
+          isset = pin;  /* Level sensed */
+          isclr = 0;
+          iveset = 0;   /* Falling edge or low levels*/
+          iveclr = pin;
+        }
+        break;
+
+      case 4:           /* Interrupt on high level */
+        {
+          isset = pin;  /* Level sensed */
+          isclr = 0;
+        }
+        break;
+    }
+
+  /* "The GPIO IS register is the interrupt sense register. Bits set to
+   * 1 in GPIOIS configure the corresponding pins to detect levels, while
+   * bits set to 0 configure the pins to detect edges. All bits are cleared
+   * by a reset.
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_IS_OFFSET);
+  regval &= isclr;
+  regval |= isset;
+  putreg32(regval, base + LM3S_GPIO_IS_OFFSET);
+
+  /* "The GPIO IBE register is the interrupt both-edges register. When the
+   * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
+   * set to detect edges, bits set to High in GPIO IBE configure the
+   * corresponding pin to detect both rising and falling edges, regardless
+   * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ...
+   * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits
+   * are cleared by a reset.
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_IBE_OFFSET);
+  regval &= ibeclr;
+  regval |= ibeset;
+  putreg32(regval, base + LM3S_GPIO_IBE_OFFSET);
+
+  /* "The GPIOIEV register is the interrupt event register. Bits set to
+   * High in GPIO IEV configure the corresponding pin to detect rising edges
+   * or high levels, depending on the corresponding bit value in the GPIO
+   * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to
+   * detect falling edges or low levels, depending on the corresponding bit
+   * value in GPIOIS. All bits are cleared by a reset.
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_IEV_OFFSET);
+  regval &= iveclr;
+  regval |= iveset;
+  putreg32(regval, base + LM3S_GPIO_IEV_OFFSET);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int lm3s_configgpio(uint32_t cfgset)
+{
+  irqstate_t   flags;
+  unsigned int func;
+  unsigned int port;
+  unsigned int pinno;
+  uint32_t     pin;
+  uint32_t     base;
+  uint32_t     regval;
+
+  /* Decode the basics */
+
+  func  = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT;
+  port  = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  pinno = (cfgset & GPIO_NUMBER_MASK);
+  pin   = (1 <<pinno);
+
+  DEBUGASSERT(func <= GPIO_FUNC_MAX);
+
+  /* Get the base address associated with the GPIO port */
+
+  base = lm3s_gpiobaseaddress(port);
+  DEBUGASSERT(base != 0);
+
+  /* The following requires exclusive access to the GPIO registers */
+
+  flags = irqsave();
+
+  /* Enable clocking for this GPIO peripheral. "To use the GPIO, the peripheral
+   * clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn)
+   * in the RCGC2 register."
+   */
+
+  regval = getreg32(LM3S_SYSCON_RCGC2);
+  regval |= SYSCON_RCGC2_GPIO(port);
+  putreg32(regval, LM3S_SYSCON_RCGC2);
+
+  /* First, set the port to digital input.  This is the safest state in which
+   * to perform reconfiguration.
+   */
+
+  lm3s_gpiofunc(base, pinno, &g_funcbits[0]);
+
+  /* Then set up pad strengths and pull-ups.  These setups should be done before
+   * setting up the function because some function settings will over-ride these
+   * user options.
+   */
+
+  lm3s_gpiopadstrength(base, pin, cfgset);
+  lm3s_gpiopadtype(base, pin, cfgset);
+
+  /* Then set up the real pin function */
+
+  lm3s_gpiofunc(base, pinno, &g_funcbits[func]);
+
+  /* Special GPIO digital output pins */
+
+  if (func == 1 || func == 3)
+    {
+      lm3s_initoutput(cfgset);
+    }
+
+
+  /* Special setup for interrupt GPIO pins */
+
+  else if (func == 7)
+    {
+      lm3s_interrupt(base, pin, cfgset);
+    }
+
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: lm3s_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void lm3s_gpiowrite(uint32_t pinset, bool value)
+{
+  unsigned int port;
+  unsigned int pinno;
+  uint32_t     base;
+
+  /* Decode the basics */
+
+  port  = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  pinno = (pinset & GPIO_NUMBER_MASK);
+
+  /* Get the base address associated with the GPIO port */
+
+  base  = lm3s_gpiobaseaddress(port);
+
+  /* "The GPIO DATA register is the data register. In software control mode,
+   *  values written in the GPIO DATA register are transferred onto the GPIO
+   *  port pins if the respective pins have been configured as outputs through
+   *  the GPIO Direction (GPIO DIR) register ...
+   *
+   * "In order to write to GPIO DATA, the corresponding bits in the mask,
+   *  resulting from the address bus bits [9:2], must be High. Otherwise, the
+   *  bit values remain unchanged by the write. 
+   *
+   * "... All bits are cleared by a reset."
+   */
+
+  putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
+}
+
+/****************************************************************************
+ * Name: lm3s_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool lm3s_gpioread(uint32_t pinset, bool value)
+{
+  unsigned int port;
+  unsigned int pinno;
+  uint32_t     base;
+
+  /* Decode the basics */
+
+  port  = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  pinno = (pinset & GPIO_NUMBER_MASK);
+
+  /* Get the base address associated with the GPIO port */
+
+  base = lm3s_gpiobaseaddress(port);
+
+  /* "... the values read from this register are determined for each bit
+   *  by the mask bit derived from the address used to access the data register,
+   *  bits [9:2]. Bits that are 1 in the address mask cause the corresponding
+   *  bits in GPIODATA to be read, and bits that are 0 in the address mask cause
+   *  the corresponding bits in GPIO DATA to be read as 0, regardless of their
+   *  value.
+   *
+   * "A read from GPIO DATA returns the last bit value written if the respective
+   *  pins are configured as outputs, or it returns the value on the
+   *  corresponding input pin when these are configured as inputs. All bits
+   *  are cleared by a reset."
+   */
+
+  return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
+}
+
diff --git a/nuttx/arch/arm/src/lm/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm/lm3s_gpioirq.c
new file mode 100644
index 000000000..a54bfe335
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_gpioirq.c
@@ -0,0 +1,434 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_gpioirq.c
+ * arch/arm/src/chip/lm3s_gpioirq.c
+ *
+ *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "irq_internal.h"
+
+#include "lm_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* A table of handlers for each GPIO interrupt */
+
+static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
+
+/* A table that maps a GPIO group to a GPIO base address.  Overly complicated
+ * because we support disabling interrupt support for arbitrary ports.  This
+ * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h
+ */
+
+static const uint32_t g_gpiobase[] =
+{
+#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
+   LM3S_GPIOA_BASE,
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
+  LM3S_GPIOB_BASE,
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
+  LM3S_GPIOC_BASE,
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
+  LM3S_GPIOD_BASE,
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
+  LM3S_GPIOE_BASE,
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
+  LM3S_GPIOF_BASE,
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
+  LM3S_GPIOG_BASE,
+#endif
+
+  /* NOTE: Not all LM3S architectures support GPIOs above GPIOG.  If the chip
+   * does not support these higher ports, then they must be disabled in the
+   * configuration.  Otherwise, the following will likely cause compilation
+   * errors!
+   */
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
+  LM3S_GPIOH_BASE,
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
+  LM3S_GPIOJ_BASE,
+#endif
+};
+
+#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t))
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_gpiobaseaddress
+ *
+ * Input:
+ *   gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS.
+ *
+ * Description:
+ *   Given a GPIO enumeration value, return the base address of the
+ *   associated GPIO registers.  NOTE that range checking was provided by
+ *   callee
+ *
+ ****************************************************************************/
+
+static uint32_t lm3s_gpiobaseaddress(unsigned int gpioirq)
+{
+  unsigned int ndx = gpioirq >> 3;
+  if (ndx < GPIO_NADDRS)
+    {
+      return g_gpiobase[ndx];
+    }
+  return 0;
+}
+
+/****************************************************************************
+ * Name: lm3s_gpio*handler
+ *
+ * Description:
+ *   Handle interrupts on each enabled GPIO port
+ *
+ ****************************************************************************/
+
+static int lm3s_gpiohandler(uint32_t regbase, int irqbase, void *context)
+{
+  uint32_t mis;
+  int irq;
+  int pin;
+
+  /* Handle each pending GPIO interrupt.  "The GPIO MIS register is the masked
+   * interrupt status register. Bits read High in GPIO MIS reflect the status
+   * of input lines triggering an interrupt. Bits read as Low indicate that
+   * either no interrupt has been generated, or the interrupt is masked."
+   */
+
+  mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff;
+
+  /* Clear all GPIO interrupts that we are going to process.  "The GPIO ICR
+   * register is the interrupt clear register. Writing a 1 to a bit in this
+   * register clears the corresponding interrupt edge detection logic register.
+   * Writing a 0 has no effect."
+   */
+
+  putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET);
+
+  /* Now process each IRQ pending in the MIS */
+
+  for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1)
+    {
+      if ((mis & 1) != 0)
+        {
+          irq = irqbase + pin;
+          g_gpioirqvector[irq - NR_IRQS](irq, context);
+        }
+    }
+  return OK;
+}
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
+static int lm3s_gpioahandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
+static int lm3s_gpiobhandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
+static int lm3s_gpiochandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
+static int lm3s_gpiodhandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
+static int lm3s_gpioehandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
+static int lm3s_gpiofhandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
+static int lm3s_gpioghandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
+static int lm3s_gpiohhandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
+static int lm3s_gpiojhandler(int irq, FAR void *context)
+{
+  return lm3s_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: gpio_irqinitialize
+ *
+ * Description:
+ *   Initialize all vectors to the unexpected interrupt handler
+ *
+ ****************************************************************************/
+
+int gpio_irqinitialize(void)
+{
+  int i;
+
+  /* Point all interrupt vectors to the unexpected interrupt */
+
+  for (i = 0; i < NR_GPIO_IRQS; i++)
+    {
+      g_gpioirqvector[i] = irq_unexpected_isr;
+    }
+
+  /* Then attach each GPIO interrupt handlers and enable corresponding GPIO
+   * interrupts
+   */
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
+  irq_attach(LM3S_IRQ_GPIOA, lm3s_gpioahandler);
+  up_enable_irq(LM3S_IRQ_GPIOA);
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
+  irq_attach(LM3S_IRQ_GPIOB, lm3s_gpiobhandler);
+  up_enable_irq(LM3S_IRQ_GPIOB);
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
+  irq_attach(LM3S_IRQ_GPIOC, lm3s_gpiochandler);
+  up_enable_irq(LM3S_IRQ_GPIOC);
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
+  irq_attach(LM3S_IRQ_GPIOD, lm3s_gpiodhandler);
+  up_enable_irq(LM3S_IRQ_GPIOD);
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
+  irq_attach(LM3S_IRQ_GPIOE, lm3s_gpioehandler);
+  up_enable_irq(LM3S_IRQ_GPIOE);
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
+  irq_attach(LM3S_IRQ_GPIOF, lm3s_gpiofhandler);
+  up_enable_irq(LM3S_IRQ_GPIOF);
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
+  irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler);
+  up_enable_irq(LM3S_IRQ_GPIOG);
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
+  irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler);
+  up_enable_irq(LM3S_IRQ_GPIOH);
+#endif
+#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
+  irq_attach(LM3S_IRQ_GPIOJ, lm3s_gpiojhandler);
+  up_enable_irq(LM3S_IRQ_GPIOJ);
+#endif
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: gpio_irqattach
+ *
+ * Description:
+ *   Attach in GPIO interrupt to the provide 'isr'
+ *
+ ****************************************************************************/
+
+int gpio_irqattach(int irq, xcpt_t isr)
+{
+  irqstate_t flags;
+  int        gpioirq = irq - NR_IRQS;
+  int        ret     = ERROR;
+
+  if ((unsigned)gpioirq < NR_GPIO_IRQS)
+    {
+      flags = irqsave();
+
+      /* If the new ISR is NULL, then the ISR is being detached.
+       * In this case, disable the ISR and direct any interrupts
+       * to the unexpected interrupt handler.
+       */
+
+      if (isr == NULL)
+        {
+#ifndef CONFIG_ARCH_NOINTC
+           gpio_irqdisable(gpioirq);
+#endif
+           isr = irq_unexpected_isr;
+        }
+
+      /* Save the new ISR in the table. */
+
+      g_irqvector[gpioirq] = isr;
+      irqrestore(flags);
+      ret = OK;
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: gpio_irqenable
+ *
+ * Description:
+ *   Enable the GPIO IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void gpio_irqenable(int irq)
+{
+  irqstate_t flags;
+  int        gpioirq = irq - NR_IRQS;
+  uint32_t   base;
+  uint32_t   regval;
+  int        pin;
+
+  if ((unsigned)gpioirq < NR_GPIO_IRQS)
+    {
+      /* Get the base address of the GPIO module associated with this IRQ */
+
+      base = lm3s_gpiobaseaddress(gpioirq);
+      DEBUGASSERT(base != 0);
+      pin  = (1 << (gpioirq & 7));
+
+      /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
+       * mask register. Bits set to High in GPIO IM allow the corresponding
+       * pins to trigger their individual interrupts and the combined GPIO INTR
+       * line. Clearing a bit disables interrupt triggering on that pin. All
+       * bits are cleared by a reset.
+       */
+
+      flags   = irqsave();
+      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+      regval |= pin;
+      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+      irqrestore(flags);
+    }
+}
+
+/****************************************************************************
+ * Name: gpio_irqdisable
+ *
+ * Description:
+ *   Disable the GPIO IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void gpio_irqdisable(int irq)
+{
+  irqstate_t flags;
+  int        gpioirq = irq - NR_IRQS;
+  uint32_t   base;
+  uint32_t   regval;
+  int        pin;
+
+  if ((unsigned)gpioirq < NR_GPIO_IRQS)
+    {
+      /* Get the base address of the GPIO module associated with this IRQ */
+
+      base = lm3s_gpiobaseaddress(gpioirq);
+      DEBUGASSERT(base != 0);
+      pin  = (1 << (gpioirq & 7));
+
+      /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
+       * mask register. Bits set to High in GPIO IM allow the corresponding
+       * pins to trigger their individual interrupts and the combined GPIO INTR
+       * line. Clearing a bit disables interrupt triggering on that pin. All
+       * bits are cleared by a reset.
+       */
+
+      flags   = irqsave();
+      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+      regval &= ~pin;
+      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+      irqrestore(flags);
+    }
+}
+
diff --git a/nuttx/arch/arm/src/lm/lm3s_irq.c b/nuttx/arch/arm/src/lm/lm3s_irq.c
new file mode 100644
index 000000000..2039d84a8
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_irq.c
@@ -0,0 +1,458 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_irq.c
+ * arch/arm/src/chip/lm3s_irq.c
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "nvic.h"
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+#include "chip.h"
+#include "lm_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Enable NVIC debug features that are probably only desireable during
+ * bringup
+ */
+
+#undef LM3S_IRQ_DEBUG
+
+/* Get a 32-bit version of the default priority */
+
+#define DEFPRIORITY32 \
+  (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
+   NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
+   NVIC_SYSH_PRIORITY_DEFAULT << 8  |\
+   NVIC_SYSH_PRIORITY_DEFAULT)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+volatile uint32_t *current_regs;
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_dumpnvic
+ *
+ * Description:
+ *   Dump some interesting NVIC registers
+ *
+ ****************************************************************************/
+
+#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
+static void lm3s_dumpnvic(const char *msg, int irq)
+{
+  irqstate_t flags;
+
+  flags = irqsave();
+  slldbg("NVIC (%s, irq=%d):\n", msg, irq);
+  slldbg("  INTCTRL:    %08x VECTAB: %08x\n",
+         getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+#if 0
+  slldbg("  SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+         getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+         getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+#endif
+  slldbg("  IRQ ENABLE: %08x %08x\n",
+         getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
+  slldbg("  SYSH_PRIO:  %08x %08x %08x\n",
+         getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+         getreg32(NVIC_SYSH12_15_PRIORITY));
+  slldbg("  IRQ PRIO:   %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+        getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+        getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+        getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+  irqrestore(flags);
+}
+#else
+#  define lm3s_dumpnvic(msg, irq)
+#endif
+
+/****************************************************************************
+ * Name: lm3s_nmi, lm3s_busfault, lm3s_usagefault, lm3s_pendsv,
+ *       lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved
+ *
+ * Description:
+ *   Handlers for various execptions.  None are handled and all are fatal
+ *   error conditions.  The only advantage these provided over the default
+ *   unexpected interrupt handler is that they provide a diagnostic output.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+static int lm3s_nmi(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! NMI received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm3s_busfault(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Bus fault recived\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm3s_usagefault(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Usage fault received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm3s_pendsv(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! PendSV received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm3s_dbgmonitor(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Debug Monitor receieved\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm3s_reserved(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Reserved interrupt\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: lm3s_irqinfo
+ *
+ * Description:
+ *   Given an IRQ number, provide the register and bit setting to enable or
+ *   disable the irq.
+ *
+ ****************************************************************************/
+
+static int lm3s_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
+{
+  DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS);
+
+  /* Check for external interrupt */
+
+  if (irq >= LM3S_IRQ_INTERRUPTS)
+    {
+      if (irq < LM3S_IRQ_INTERRUPTS + 32)
+        {
+           *regaddr = NVIC_IRQ0_31_ENABLE;
+           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS);
+        }
+      else if (irq < NR_IRQS)
+        {
+           *regaddr = NVIC_IRQ32_63_ENABLE;
+           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
+        }
+      else
+        {
+          return ERROR; /* Invalid interrupt */
+        }
+    }
+
+  /* Handler processor exceptions.  Only a few can be disabled */
+
+  else
+    {
+       *regaddr = NVIC_SYSHCON;
+       if (irq == LM3S_IRQ_MEMFAULT)
+        {
+          *bit = NVIC_SYSHCON_MEMFAULTENA;
+        }
+      else if (irq == LM3S_IRQ_BUSFAULT)
+        {
+          *bit = NVIC_SYSHCON_BUSFAULTENA;
+        }
+      else if (irq == LM3S_IRQ_USAGEFAULT)
+        {
+          *bit = NVIC_SYSHCON_USGFAULTENA;
+        }
+      else if (irq == LM3S_IRQ_SYSTICK)
+        {
+          *regaddr = NVIC_SYSTICK_CTRL;
+          *bit = NVIC_SYSTICK_CTRL_ENABLE;
+        }
+      else
+        {
+          return ERROR; /* Invalid or unsupported exception */
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  /* Disable all interrupts */
+
+  putreg32(0, NVIC_IRQ0_31_ENABLE);
+  putreg32(0, NVIC_IRQ32_63_ENABLE);
+
+  /* Set all interrrupts (and exceptions) to the default priority */
+
+  putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
+
+  putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* Initialize support for GPIO interrupts if included in this build */
+
+#ifndef CONFIG_LM3S_DISABLE_GPIO_IRQS
+#ifdef CONFIG_HAVE_WEAKFUNCTIONS
+  if (gpio_irqinitialize != NULL)
+#endif
+    {
+      gpio_irqinitialize();
+    }
+#endif
+
+  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
+   * exception is used for performing context switches; The Hard Fault
+   * must also be caught because a SVCall may show up as a Hard Fault
+   * under certain conditions.
+   */
+
+  irq_attach(LM3S_IRQ_SVCALL, up_svcall);
+  irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault);
+
+  /* Set the priority of the SVCall interrupt */
+
+#ifdef CONFIG_ARCH_IRQPRIO
+/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
+#endif
+
+  /* If the MPU is enabled, then attach and enable the Memory Management
+   * Fault handler.
+   */
+
+#ifdef CONFIG_ARMV7M_MPU
+  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
+  up_enable_irq(LM3S_IRQ_MEMFAULT);
+#endif
+
+  /* Attach all other processor exceptions (except reset and sys tick) */
+
+#ifdef CONFIG_DEBUG
+  irq_attach(LM3S_IRQ_NMI, lm3s_nmi);
+#ifndef CONFIG_ARMV7M_MPU
+  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
+#endif
+  irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault);
+  irq_attach(LM3S_IRQ_USAGEFAULT, lm3s_usagefault);
+  irq_attach(LM3S_IRQ_PENDSV, lm3s_pendsv);
+  irq_attach(LM3S_IRQ_DBGMONITOR, lm3s_dbgmonitor);
+  irq_attach(LM3S_IRQ_RESERVED, lm3s_reserved);
+#endif
+
+  lm3s_dumpnvic("initial", NR_IRQS);
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+
+  /* And finally, enable interrupts */
+
+  setbasepri(NVIC_SYSH_PRIORITY_MAX);
+  irqrestore(0);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  uint32_t bit;
+
+  if (lm3s_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Clear the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval &= ~bit;
+      putreg32(regval, regaddr);
+    }
+  lm3s_dumpnvic("disable", irq);
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  uint32_t bit;
+
+  if (lm3s_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Set the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval |= bit;
+      putreg32(regval, regaddr);
+    }
+  lm3s_dumpnvic("enable", irq);
+}
+
+/****************************************************************************
+ * Name: up_maskack_irq
+ *
+ * Description:
+ *   Mask the IRQ and acknowledge it
+ *
+ ****************************************************************************/
+
+void up_maskack_irq(int irq)
+{
+  up_disable_irq(irq);
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   Set the priority of an IRQ.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  int shift;
+
+  DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
+
+  if (irq < LM3S_IRQ_INTERRUPTS)
+    {
+      irq    -= 4;
+      regaddr = NVIC_SYSH_PRIORITY(irq);
+    }
+  else
+    {
+      irq    -= LM3S_IRQ_INTERRUPTS;
+      regaddr = NVIC_IRQ_PRIORITY(irq);
+    }
+
+  regval      = getreg32(regaddr);
+  shift       = ((irq & 3) << 3);
+  regval     &= ~(0xff << shift);
+  regval     |= (priority << shift);
+  putreg32(regval, regaddr);
+
+  lm3s_dumpnvic("prioritize", irq);
+  return OK;
+}
+#endif
diff --git a/nuttx/arch/arm/src/lm/lm3s_lowputc.c b/nuttx/arch/arm/src/lm/lm3s_lowputc.c
new file mode 100644
index 000000000..7f9a826c8
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_lowputc.c
@@ -0,0 +1,309 @@
+/**************************************************************************
+ * arch/arm/src/lm/lm3s_lowputc.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "lm_gpio.h"
+#include "chip/lm_pinmap.h"
+
+#include "lm_lowputc.h"
+
+/**************************************************************************
+ * Pre-processor Definitions
+ **************************************************************************/
+
+/* Configuration **********************************************************/
+
+#if LM3S_NUARTS < 2
+#  undef  CONFIG_LM3S_UART1
+#  undef  CONFIG_UART1_SERIAL_CONSOLE
+#endif
+
+#if LM3S_NUARTS < 3
+#  undef  CONFIG_LM3S_UART2
+#  undef  CONFIG_UART2_SERIAL_CONSOLE
+#endif
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* Select UART parameters for the selected console */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define LM3S_CONSOLE_BASE     LM3S_UART0_BASE
+#  define LM3S_CONSOLE_BAUD     CONFIG_UART0_BAUD
+#  define LM3S_CONSOLE_BITS     CONFIG_UART0_BITS
+#  define LM3S_CONSOLE_PARITY   CONFIG_UART0_PARITY
+#  define LM3S_CONSOLE_2STOP    CONFIG_UART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define LM3S_CONSOLE_BASE     LM3S_UART1_BASE
+#  define LM3S_CONSOLE_BAUD     CONFIG_UART1_BAUD
+#  define LM3S_CONSOLE_BITS     CONFIG_UART1_BITS
+#  define LM3S_CONSOLE_PARITY   CONFIG_UART1_PARITY
+#  define LM3S_CONSOLE_2STOP    CONFIG_UART1_2STOP
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define LM3S_CONSOLE_BASE     LM3S_UART2_BASE
+#  define LM3S_CONSOLE_BAUD     CONFIG_UART2_BAUD
+#  define LM3S_CONSOLE_BITS     CONFIG_UART2_BITS
+#  define LM3S_CONSOLE_PARITY   CONFIG_UART2_PARITY
+#  define LM3S_CONSOLE_2STOP    CONFIG_UART2_2STOP
+#else
+#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Get LCRH settings */
+
+#if LM3S_CONSOLE_BITS == 5
+#  define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
+#elif LM3S_CONSOLE_BITS == 6
+#  define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
+#elif LM3S_CONSOLE_BITS == 7
+#  define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
+#elif LM3S_CONSOLE_BITS == 8
+#  define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
+#else
+#  error "Number of bits not supported"
+#endif
+
+#if LM3S_CONSOLE_PARITY == 0
+#  define UART_LCRH_PARITY (0)
+#elif LM3S_CONSOLE_PARITY == 1
+#  define UART_LCRH_PARITY UART_LCRH_PEN
+#elif LM3S_CONSOLE_PARITY == 2
+#  define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
+#else
+#  error "Invalid parity selection"
+#endif
+
+#if LM3S_CONSOLE_2STOP != 0
+#  define UART_LCRH_NSTOP UART_LCRH_STP2
+#else
+#  define UART_LCRH_NSTOP (0)
+#endif
+
+#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN)
+
+/* Calculate BAUD rate from the SYS clock:
+ *
+ * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit
+ *  fractional part. The number formed by these two values is used by the baud-rate generator
+ *  to determine the bit period. Having a fractional baud-rate divider allows the UART to
+ *  generate all the standard baud rates.
+ *
+ * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD)
+ *  register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
+ *  Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship
+ *  to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional
+ *  part, separated by a decimal place.):
+ *
+ *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
+ *
+ * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number
+ *  (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated
+ *  by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5
+ *  to account for rounding errors:
+ *
+ *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
+ *
+ * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred
+ *  to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is
+ *  used for error detection during receive operations.
+ *
+ * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and
+ *  UARTFBRD registers form an internal 30-bit register. This internal register is only
+ *  updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
+ *  divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
+ */
+
+#define LM3S_BRDDEN     (16 * LM3S_CONSOLE_BAUD)
+#define LM3S_BRDI       (SYSCLK_FREQUENCY / LM3S_BRDDEN)
+#define LM3S_REMAINDER  (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
+#define LM3S_DIVFRAC    ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
+
+/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
+ *
+ * LM3S_BRDDEN    = (16 * 115,200)                           = 1,843,200
+ * LM3S_BRDI      = 50,000,000 / 1,843,200                   = 27
+ * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27              = 233,600
+ * LM3S_DIVFRAC   = (233,600 * 64 + 921,600) / 1,843,200     = 8
+ *
+ * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
+ */
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ **************************************************************************/
+
+void up_lowputc(char ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Wait until the TX FIFO is not full */
+
+  while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
+
+  /* Then send the character */
+
+  putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET);
+#endif
+}
+
+/**************************************************************************
+ * Name: up_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ **************************************************************************/
+
+void up_lowsetup(void)
+{
+  uint32_t regval;
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  uint32_t ctl;
+#endif
+
+  /* Enable the selected UARTs and configure GPIO pins to need by the
+   * the selected UARTs.  NOTE: The serial driver later depends on
+   * this pin configuration -- whether or not a serial console is selected.
+   */
+
+#ifdef CONFIG_LM3S_UART0
+  regval  = getreg32(LM3S_SYSCON_RCGC1);
+  regval |= SYSCON_RCGC1_UART0;
+  putreg32(regval, LM3S_SYSCON_RCGC1);
+
+  lm3s_configgpio(GPIO_UART0_RX);
+  lm3s_configgpio(GPIO_UART0_TX);
+#endif
+
+#ifdef CONFIG_LM3S_UART1
+  regval  = getreg32(LM3S_SYSCON_RCGC1);
+  regval |= SYSCON_RCGC1_UART1;
+  putreg32(regval, LM3S_SYSCON_RCGC1);
+
+  lm3s_configgpio(GPIO_UART1_RX);
+  lm3s_configgpio(GPIO_UART1_TX);
+#endif
+
+  /* Enable the selected console device */
+
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
+
+  ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+  ctl &= ~UART_CTL_UARTEN;
+  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+
+  /* Write the integer portion of the BRD to the UART IBRD register */
+
+  putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
+
+  /* Write the fractional portion of the BRD to the UART FBRD register */
+
+  putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
+
+  /* Write the desired serial parameters to the UART LCRH register */
+
+  putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
+
+  /* Enable the UART by setting the UARTEN bit in the UART CTL register */
+
+  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
+  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+#endif
+
+}
+
+
diff --git a/nuttx/arch/arm/src/lm/lm3s_serial.c b/nuttx/arch/arm/src/lm/lm3s_serial.c
new file mode 100644
index 000000000..79628c765
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_serial.c
@@ -0,0 +1,1064 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_serial.c
+ *
+ *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial/serial.h>
+
+#include <arch/serial.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "os_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Some sanity checks *******************************************************/
+
+#if LM3S_NUARTS < 2
+#  undef  CONFIG_LM3S_UART1
+#  undef  CONFIG_UART1_SERIAL_CONSOLE
+#endif
+
+#if LM3S_NUARTS < 3
+#  undef  CONFIG_LM3S_UART2
+#  undef  CONFIG_UART2_SERIAL_CONSOLE
+#endif
+
+/* Is there a UART enabled? */
+
+#if !defined(CONFIG_LM3S_UART0) && !defined(CONFIG_LM3S_UART1) && !defined(CONFIG_LM3S_UART2)
+#  error "No UARTs enabled"
+#endif
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* If we are not using the serial driver for the console, then we
+ * still must provide some minimal implementation of up_putc.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart0port     /* UART0 is console */
+#  define TTYS0_DEV       g_uart0port     /* UART0 is ttyS0 */
+#  ifdef CONFIG_LM3S_UART1
+#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
+#    ifdef CONFIG_LM3S_UART2
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifdef CONFIG_LM3S_UART2
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart1port     /* UART1 is console */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  ifdef CONFIG_LM3S_UART0
+#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
+#    ifdef CONFIG_LM3S_UART2
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifdef CONFIG_LM3S_UART2
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart2port     /* UART2 is console */
+#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
+#  ifdef CONFIG_LM3S_UART0
+#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
+#    ifdef CONFIG_LM3S_UART2
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifdef CONFIG_LM3S_UART2
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elifdefined(CONFIG_LM3S_UART0)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  ifdef CONFIG_LM3S_UART1
+#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
+#    ifdef CONFIG_LM3S_UART2
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifdef CONFIG_LM3S_UART2
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elifdefined(CONFIG_LM3S_UART1)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  undef TTYS2_DEV                        /* No ttyS2 */
+#  ifdef CONFIG_LM3S_UART2
+#    define TTYS1_DEV     g_uart2port     /* UART2 is ttyS1 */
+#  else
+#    undef TTYS1_DEV                      /* No ttyS1 */
+#  endif
+#elifdefined(CONFIG_LM3S_UART2)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
+#  undef  TTYS1_DEV                       /* No ttyS1 */
+#  undef  TTYS2_DEV                       /* No ttyS2 */
+#else
+#  error "No valid TTY devices"
+#  undef  CONSOLE_DEV                     /* No console device */
+#  undef  TTYS0_DEV                       /* No ttyS0 */
+#  undef  TTYS1_DEV                       /* No ttyS1 */
+#  undef  TTYS2_DEV                       /* No ttyS2 */
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uint32_t uartbase; /* Base address of UART registers */
+  uint32_t baud;     /* Configured baud */
+  uint32_t im;       /* Saved IM value */
+  uint8_t  irq;      /* IRQ associated with this UART */
+  uint8_t  parity;   /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;     /* Number of bits (7 or 8) */
+  bool    stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int  up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int  up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int  up_interrupt(int irq, void *context);
+static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+static bool up_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .attach         = up_attach,
+  .detach         = up_detach,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxavailable    = up_rxavailable,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txready        = up_txready,
+  .txempty        = up_txempty,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_LM3S_UART0
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+#endif
+#ifdef CONFIG_LM3S_UART1
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+#endif
+#ifdef CONFIG_LM3S_UART2
+static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
+static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
+#endif
+
+/* This describes the state of the LM3S uart0 port. */
+
+#ifdef CONFIG_LM3S_UART0
+static struct up_dev_s g_uart0priv =
+{
+  .uartbase       = LM3S_UART0_BASE,
+  .baud           = CONFIG_UART0_BAUD,
+  .irq            = LM3S_IRQ_UART0,
+  .parity         = CONFIG_UART0_PARITY,
+  .bits           = CONFIG_UART0_BITS,
+  .stopbits2      = CONFIG_UART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+#endif
+
+/* This describes the state of the LM3S uart1 port. */
+
+#ifdef CONFIG_LM3S_UART1
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase       = LM3S_UART1_BASE,
+  .baud           = CONFIG_UART1_BAUD,
+  .irq            = LM3S_IRQ_UART1,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+#endif
+
+/* This describes the state of the LM3S uart1 port. */
+
+#ifdef CONFIG_LM3S_UART2
+static struct up_dev_s g_uart2priv =
+{
+  .uartbase       = LM3S_UART2_BASE,
+  .baud           = CONFIG_UART2_BAUD,
+  .irq            = LM3S_IRQ_UART2,
+  .parity         = CONFIG_UART2_PARITY,
+  .bits           = CONFIG_UART2_BITS,
+  .stopbits2      = CONFIG_UART2_2STOP,
+};
+
+static uart_dev_t g_uart2port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART2_RXBUFSIZE,
+    .buffer = g_uart2rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART2_TXBUFSIZE,
+    .buffer = g_uart2txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart2priv,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg32(priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disableuartint
+ ****************************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
+{
+  /* Return the current interrupt mask value */
+
+  if (im)
+    {
+      *im = priv->im;
+    }
+
+  /* Disable all interrupts */
+
+  priv->im = 0;
+  up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
+}
+
+/****************************************************************************
+ * Name: up_restoreuartint
+ ****************************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
+{
+  priv->im = im;
+  up_serialout(priv, LM3S_UART_IM_OFFSET, im);
+}
+
+/****************************************************************************
+ * Name: up_waittxnotfull
+ ****************************************************************************/
+
+#ifdef HAVE_CONSOLE
+static inline void up_waittxnotfull(struct up_dev_s *priv)
+{
+  int tmp;
+
+  /* Limit how long we will wait for the TX available condition */
+
+  for (tmp = 1000 ; tmp > 0 ; tmp--)
+    {
+      /* Check Tx FIFO is full */
+
+      if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
+        {
+          /* The Tx FIFO is not full... return */
+
+          break;
+        }
+    }
+
+  /* If we get here, then the wait has timed out and the Tx FIFO remains
+   * full.
+   */
+}
+#endif
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This
+ *   method is called the first time that the serial port is
+ *   opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32_t lcrh;
+  uint32_t ctl;
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+  uint32_t den;
+  uint32_t brdi;
+  uint32_t remainder;
+  uint32_t divfrac;
+
+  /* Note:  The logic here depends on the fact that that the UART module
+   * was enabled and the GPIOs were configured in up_lowsetup().
+   */
+
+  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
+
+  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
+  ctl &= ~UART_CTL_UARTEN;
+  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
+
+  /* Calculate BAUD rate from the SYS clock:
+   *
+   * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer
+   *  and a 6-bit fractional part. The number formed by these two values is
+   *  used by the baud-rate generator to determine the bit period. Having a
+   *  fractional baud-rate divider allows the UART to generate all the standard
+   *  baud rates.
+   *
+   * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor
+   *  (UARTIBRD) register ... and the 6-bit fractional part is loaded with the
+   *  UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate
+   *  divisor (BRD) has the following relationship to the system clock (where
+   *  BRDI is the integer part of the BRD and BRDF is the fractional part,
+   *  separated by a decimal place.):
+   *
+   *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
+   *
+   * "where UARTSysClk is the system clock connected to the UART. The 6-bit
+   *  fractional number (that is to be loaded into the DIVFRAC bit field in the
+   *  UARTFBRD register) can be calculated by taking the fractional part of the
+   *  baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
+   *  rounding errors:
+   *
+   *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
+   *
+   * "The UART generates an internal baud-rate reference clock at 16x the baud-
+   *  rate (referred to as Baud16). This reference clock is divided by 16 to
+   *  generate the transmit clock, and is used for error detection during receive
+   *  operations.
+   *
+   * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the
+   *  UARTIBRD and UARTFBRD registers form an internal 30-bit register. This
+   *  internal register is only updated when a write operation to UARTLCRH is
+   *  performed, so any changes to the baud-rate divisor must be followed by a
+   *  write to the UARTLCRH register for the changes to take effect. ..."
+   */
+
+  den       = priv->baud << 4;
+  brdi      = SYSCLK_FREQUENCY / den;
+  remainder = SYSCLK_FREQUENCY - den * brdi;
+  divfrac   = ((remainder << 6) + (den >> 1)) / den;
+
+  up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
+  up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
+
+  /* Set up the LCRH register */
+
+  lcrh = 0;
+  switch (priv->bits)
+    {
+      case 5:
+        lcrh |= UART_LCRH_WLEN_5BITS;
+        break;
+      case 6:
+        lcrh |= UART_LCRH_WLEN_6BITS;
+        break;
+      case 7:
+        lcrh |= UART_LCRH_WLEN_7BITS;
+        break;
+      case 8:
+      default:
+        lcrh |= UART_LCRH_WLEN_8BITS;
+        break;
+    }
+
+  switch (priv->parity)
+    {
+      case 0:
+      default:
+        break;
+      case 1:
+        lcrh |= UART_LCRH_PEN;
+        break;
+      case 2:
+        lcrh |= UART_LCRH_PEN|UART_LCRH_EPS;
+        break;
+    }
+
+  if (priv->stopbits2)
+    {
+      lcrh |= UART_LCRH_STP2;
+    }
+
+  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
+#endif
+
+  /* Set the UART to interrupt whenever the TX FIFO is almost empty or when
+   * any character is received.
+   */
+
+  up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
+
+  /* Flush the Rx and Tx FIFOs -- How do you do that?*/
+
+  /* Enable Rx interrupts from the UART except for Tx interrupts.  We don't want
+   * Tx interrupts until we have something to send.  We will check for serial
+   * errors as part of Rx interrupt processing (no interrupts will be received
+   * yet because the interrupt is still disabled at the interrupt controller.
+   */
+
+  up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
+
+  /* Enable the FIFOs */
+
+#ifdef CONFIG_SUPPRESS_UART_CONFIG
+  lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
+#endif
+  lcrh |= UART_LCRH_FEN;
+  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
+
+  /* Enable Rx, Tx, and the UART */
+
+#ifdef CONFIG_SUPPRESS_UART_CONFIG
+  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
+#endif
+  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
+  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
+
+  /* Set up the cache IM value */
+
+  priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial
+ *   port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disableuartint(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the UART to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless the
+ *   hardware supports multiple levels of interrupt enabling).  The RX and TX
+ *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  int ret;
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, up_interrupt);
+  if (ret == OK)
+    {
+       /* Enable the interrupt (RX and TX interrupts are still disabled
+        * in the UART
+        */
+
+       up_enable_irq(priv->irq);
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach UART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception is
+ *   the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked
+ *   when an interrupt received on the 'irq'  It should call
+ *   uart_transmitchars or uart_receivechar to perform the
+ *   appropriate data transfers.  The interrupt handling logic\
+ *   must be able to map the 'irq' number into the approprite
+ *   uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  uint32_t           mis;
+  int                passes;
+  bool               handled;
+
+#ifdef CONFIG_LM3S_UART0
+  if (g_uart0priv.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+#endif
+#ifdef CONFIG_LM3S_UART1
+  if (g_uart1priv.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else
+#endif
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  handled = true;
+  for (passes = 0; passes < 256 && handled; passes++)
+    {
+      handled = false;
+
+      /* Get the masked UART status and clear the pending interrupts. */
+
+       mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
+       up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
+
+      /* Handle incoming, receive bytes (with or without timeout) */
+
+      if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0)
+        {
+           /* Rx buffer not empty ... process incoming bytes */
+
+           uart_recvchars(dev);
+           handled = true;
+        }
+
+      /* Handle outgoing, transmit bytes */
+
+      if ((mis & UART_MIS_TXMIS) != 0)
+        {
+           /* Tx FIFO not full ... process outgoing bytes */
+
+           uart_xmitchars(dev);
+           handled = true;
+        }
+    }
+    return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             ret = -EINVAL;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+
+    default:
+      ret = -ENOTTY;
+      break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32_t *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32_t rxd;
+
+  /* Get the Rx byte + 4 bits of error information.  Return those in status */
+
+  rxd     = up_serialin(priv, LM3S_UART_DR_OFFSET);
+  *status = rxd;
+
+  /* The lower 8bits of the Rx data is the actual recevied byte */
+
+  return rxd & 0xff;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+      /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx
+       * timeout occurs.
+       */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->im |= (UART_IM_RXIM|UART_IM_RTIM);
+#endif
+    }
+  else
+    {
+      priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
+    }
+  up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return true if the receive fifo is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  irqstate_t flags;
+
+  flags = irqsave();
+  if (enable)
+    {
+      /* Set to receive an interrupt when the TX fifo is half emptied */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->im |= UART_IM_TXIM;
+      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+
+      /* The serial driver wants an interrupt here, but will not get get
+       * one unless we "prime the pump."  I believe that this is because
+       * behave like a level interrupt and the LM3S interrupts behave
+       * (at least by default) like edge interrupts.
+       *
+       * In any event, faking a TX interrupt here solves the problem;
+       * Call uart_xmitchars() just as would have been done if we recieved
+       * the TX interrupt.
+       */
+
+      uart_xmitchars(dev);
+#endif
+    }
+  else
+    {
+      /* Disable the TX interrupt */
+
+      priv->im &= ~UART_IM_TXIM;
+      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+    }
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return true if the tranmsit fifo is not full
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
+}
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ *   Return true if the transmit fifo is empty
+ *
+ ****************************************************************************/
+
+static bool up_txempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in 
+ *   debug so that the serial console will be available
+ *   during bootup.  This must be called before up_serialinit.
+ *
+ ****************************************************************************/
+
+void up_earlyserialinit(void)
+{
+  /* NOTE:  All GPIO configuration for the UARTs was performed in
+   * up_lowsetup
+   */
+
+  /* Disable all UARTS */
+
+  up_disableuartint(TTYS0_DEV.priv, NULL);
+#ifdef TTYS1_DEV
+  up_disableuartint(TTYS1_DEV.priv, NULL);
+#endif
+#ifdef TTYS2_DEV
+  up_disableuartint(TTYS2_DEV.priv, NULL);
+#endif
+
+  /* Configuration whichever one is the console */
+
+#ifdef HAVE_CONSOLE
+  CONSOLE_DEV.isconsole = true;
+  up_setup(&CONSOLE_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+  /* Register the console */
+
+#ifdef HAVE_CONSOLE
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+  /* Register all UARTs */
+
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+#ifdef TTYS1_DEV
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+#ifdef TTYS2_DEV
+  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint32_t im;
+
+  up_disableuartint(priv, &im);
+  up_waittxnotfull(priv);
+  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_waittxnotfull(priv);
+      up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r');
+    }
+
+  up_waittxnotfull(priv);
+  up_restoreuartint(priv, im);
+#endif
+  return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
diff --git a/nuttx/arch/arm/src/lm/lm3s_ssi.c b/nuttx/arch/arm/src/lm/lm3s_ssi.c
new file mode 100644
index 000000000..8cd1cee07
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_ssi.c
@@ -0,0 +1,1580 @@
+/****************************************************************************
+ * arch/arm/src/lm32/lm3s_ssi.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/spi.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lm_gpio.h"
+#include "lm_ssi.h"
+#include "chip/lm_pinmap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Enables debug output from this file (needs CONFIG_DEBUG with
+ * CONFIG_DEBUG_VERBOSE too)
+ */
+
+#undef SSI_DEBUG  /* Define to enable debug */
+
+#ifdef SSI_DEBUG
+#  define ssidbg  lldbg
+#  define ssivdbg llvdbg
+#else
+#  define ssidbg(x...)
+#  define ssivdbg(x...)
+#endif
+
+/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI
+ * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in
+ * such case, the following must be expanded).
+ */
+
+#if LM3S_NSSI == 0
+#  undef CONFIG_SSI0_DISABLE
+#  define CONFIG_SSI0_DISABLE 1
+#  undef CONFIG_SSI1_DISABLE
+#  define CONFIG_SSI1_DISABLE 1
+#elif LM3S_NSSI == 1
+#  undef CONFIG_SSI1_DISABLE
+#  define CONFIG_SSI1_DISABLE 1
+#endif
+
+/* Which SSI modules have been enabled? */
+
+#ifndef CONFIG_SSI0_DISABLE
+#  define SSI0_NDX 0             /* Index to SSI0 in g_ssidev[] */
+#  ifndef CONFIG_SSI1_DISABLE
+#   define SSI1_NDX 1            /* Index to SSI1 in g_ssidev[] */
+#   define NSSI_ENABLED 2        /* Two SSI interfaces: SSI0 & SSI1 */
+#  else
+#   define NSSI_ENABLED 1        /* One SSI interface: SSI0 */
+#   define SSI_BASE          LM3S_SSI0_BASE
+#   define SSI_IRQ           LM3S_IRQ_SSI0
+#  endif
+#else
+#  ifndef CONFIG_SSI1_DISABLE
+#   define SSI1_NDX 0            /* Index to SSI1 in g_ssidev[] */
+#   define NSSI_ENABLED 1        /* One SSI interface: SSI1 */
+#   define SSI_BASE          LM3S_SSI1_BASE
+#   define SSI_IRQ           LM3S_IRQ_SSI1
+#  else
+#   define NSSI_ENABLED 0        /* No SSI interfaces */
+#  endif
+#endif
+
+/* Compile the rest of the file only if at least one SSI interface has been
+ * enabled.
+ */
+
+#if NSSI_ENABLED > 0
+
+/* The number of (16-bit) words that will fit in the Tx FIFO */
+
+#define LM3S_TXFIFO_WORDS 8
+
+/* Configuration settings */
+
+#ifndef CONFIG_SSI_TXLIMIT
+#  define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2)
+#endif
+
+#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS
+#  error "Invalid range for CONFIG_SSI_TXLIMIT"
+#endif
+
+#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2)
+#  error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
+#endif
+
+/****************************************************************************
+ * Private Type Definitions
+ ****************************************************************************/
+
+struct lm3s_ssidev_s
+{
+  const struct spi_ops_s *ops;  /* Common SPI operations */
+#ifndef CONFIG_SSI_POLLWAIT
+  sem_t  xfrsem;                /* Wait for transfer to complete */
+#endif
+
+  /* These following are the source and destination buffers of the transfer.
+   * they are retained in this structure so that they will be accessible
+   * from an interrupt handler.  The actual type of the buffer is uint8_t if
+   * nbits <=8 and uint16_t if nbits >8.
+   */
+
+  void  *txbuffer;              /* Source buffer */
+  void  *rxbuffer;              /* Destination buffer */
+
+  /* These are functions pointers that are configured to perform the
+   * appropriate transfer for the particular kind of exchange that is
+   * occurring.  Differnt functions may be selected depending on (1)
+   * if the tx or txbuffer is NULL and depending on the number of bits
+   * per word.
+   */
+
+  void  (*txword)(struct lm3s_ssidev_s *priv);
+  void  (*rxword)(struct lm3s_ssidev_s *priv);
+
+#if NSSI_ENABLED > 1
+  uint32_t base;                /* SSI register base address */
+#endif
+
+  int      ntxwords;            /* Number of words left to transfer on the Tx FIFO */
+  int      nrxwords;            /* Number of words received on the Rx FIFO */
+  int      nwords;              /* Number of words to be exchanged */
+  uint8_t  nbits;               /* Current number of bits per word */
+
+#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
+  uint8_t  irq;                 /* SSI IRQ number */
+#endif
+
+  /* If there is more than one device on the SPI bus, then we have to enforce
+   * mutual exclusion and remember some configuration settings to reduce the
+   * overhead of constant SPI re-configuration.
+   */
+
+#ifndef CONFIG_SPI_OWNBUS
+  sem_t    exclsem;             /* For exclusive access to the SSI bus */
+  uint32_t frequency;           /* Current desired SCLK frequency */
+  uint32_t actual;              /* Current actual SCLK frequency */
+  uint8_t  mode;                /* Current mode 0,1,2,3 */
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SSI register access */
+
+static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv,
+              unsigned int offset);
+static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset,
+              uint32_t value);
+
+/* Misc helpers */
+
+static uint32_t ssi_disable(struct lm3s_ssidev_s *priv);
+static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable);
+
+#ifndef CONFIG_SSI_POLLWAIT
+static void ssi_semtake(sem_t *sem);
+#define ssi_semgive(s) sem_post(s);
+#endif
+
+/* SSI data transfer */
+
+static void ssi_txnull(struct lm3s_ssidev_s *priv);
+static void ssi_txuint16(struct lm3s_ssidev_s *priv);
+static void ssi_txuint8(struct lm3s_ssidev_s *priv);
+static void ssi_rxnull(struct lm3s_ssidev_s *priv);
+static void ssi_rxuint16(struct lm3s_ssidev_s *priv);
+static void ssi_rxuint8(struct lm3s_ssidev_s *priv);
+static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv);
+static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv);
+#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT)
+static inline int ssi_performtx(struct lm3s_ssidev_s *priv);
+#else
+static int  ssi_performtx(struct lm3s_ssidev_s *priv);
+#endif
+static inline void ssi_performrx(struct lm3s_ssidev_s *priv);
+static int  ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer,
+                         void *rxbuffer, unsigned int nwords);
+
+/* Interrupt handling */
+
+#ifndef CONFIG_SSI_POLLWAIT
+static inline struct lm3s_ssidev_s *ssi_mapirq(int irq);
+static int  ssi_interrupt(int irq, void *context);
+#endif
+
+/* SPI methods */
+
+#ifndef CONFIG_SPI_OWNBUS
+static int  ssi_lock(FAR struct spi_dev_s *dev, bool lock);
+#endif
+static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv,
+              uint32_t frequency);
+static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev,
+              uint32_t frequency);
+static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv,
+              enum spi_mode_e mode);
+static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
+static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits);
+static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits);
+static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd);
+#ifdef CONFIG_SPI_EXCHANGE
+static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+                         FAR void *rxbuffer, size_t nwords);
+#else
+static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
+              size_t nwords);
+static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
+              size_t nwords);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Common SSI operations */
+
+static const struct spi_ops_s g_spiops =
+{
+#ifndef CONFIG_SPI_OWNBUS
+  .lock         = ssi_lock,
+#endif
+  .select       = lm3s_spiselect,    /* Provided externally by board logic */
+  .setfrequency = ssi_setfrequency,
+  .setmode      = ssi_setmode,
+  .setbits      = ssi_setbits,
+  .status       = lm3s_spistatus,    /* Provided externally by board logic */
+#ifdef CONFIG_SPI_CMDDATA
+  .cmddata      = lm3s_spicmddata,
+#endif
+  .send         = ssi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+  .exchange     = ssi_exchange,
+#else
+  .sndblock     = ssi_sndblock,
+  .recvblock    = ssi_recvblock,
+#endif
+};
+
+/* This supports is up to two SSI busses/ports */
+
+static struct lm3s_ssidev_s g_ssidev[] =
+{
+#ifndef CONFIG_SSI0_DISABLE
+  {
+    .ops  = &g_spiops,
+#if NSSI_ENABLED > 1
+    .base = LM3S_SSI0_BASE,
+#endif
+#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
+    .irq  = LM3S_IRQ_SSI0,
+#endif
+  },
+#endif
+#ifndef CONFIG_SSI1_DISABLE
+  {
+    .ops  = &g_spiops,
+#if NSSI_ENABLED > 1
+    .base = LM3S_SSI1_BASE,
+#endif
+#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
+    .irq  = LM3S_IRQ_SSI1,
+#endif
+  },
+#endif
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ssi_getreg
+ *
+ * Description:
+ *   Read the SSI register at this offeset
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   offset - Offset to the SSI register from the register base address
+ *
+ * Returned Value:
+ *   Value of the register at this offset
+ *
+ ****************************************************************************/
+
+static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, unsigned int offset)
+{
+#if NSSI_ENABLED > 1
+  return getreg32(priv->base + offset);
+#else
+  return getreg32(SSI_BASE + offset);
+#endif
+}
+
+/****************************************************************************
+ * Name: ssi_putreg
+ *
+ * Description:
+ *   Write the value to the SSI register at this offeset
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   offset - Offset to the SSI register from the register base address
+ *   value  - Value to write
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, uint32_t value)
+{
+#if NSSI_ENABLED > 1
+  putreg32(value, priv->base + offset);
+#else
+  putreg32(value, SSI_BASE + offset);
+#endif
+}
+
+/****************************************************************************
+ * Name: ssi_disable
+ *
+ * Description:
+ *   Disable SSI operation.  NOTE: The SSI must be disabled before any control
+ *   registers can be re-programmed.
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   State of the SSI before the SSE was disabled
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static uint32_t ssi_disable(struct lm3s_ssidev_s *priv)
+{
+  uint32_t retval;
+  uint32_t regval;
+
+  retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
+  regval = (retval & ~SSI_CR1_SSE);
+  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
+  ssivdbg("CR1: %08x\n", regval);
+  return retval;
+}
+
+/****************************************************************************
+ * Name: ssi_enable
+ *
+ * Description:
+ *   Restore the SSI operational state
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   enable - The previous operational state
+ *
+ * Returned Value:
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable)
+{
+  uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
+  regval &= ~SSI_CR1_SSE;
+  regval  |= (enable & SSI_CR1_SSE);
+  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
+  ssivdbg("CR1: %08x\n", regval);
+}
+
+/****************************************************************************
+ * Name: ssi_semtake
+ *
+ * Description:
+ *   Wait for a semaphore (handling interruption by signals);
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   enable - The previous operational state
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SSI_POLLWAIT
+static void ssi_semtake(sem_t *sem)
+{
+  int ret;
+  do
+    {
+      ret = sem_wait(sem);
+    }
+  while (ret < 0 && errno == EINTR);
+  DEBUGASSERT(ret == 0);
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8
+ *
+ * Description:
+ *   Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer
+ *   pointer appropriately.  The selected function dependes on (1) if there
+ *   is a source txbuffer provided, and (2) if the number of bits per
+ *   word is <=8 or >8.
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void ssi_txnull(struct lm3s_ssidev_s *priv)
+{
+  ssivdbg("TX: ->0xffff\n");
+  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff);
+}
+
+static void ssi_txuint16(struct lm3s_ssidev_s *priv)
+{
+  uint16_t *ptr    = (uint16_t*)priv->txbuffer;
+  ssivdbg("TX: %p->%04x\n", ptr, *ptr);
+  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
+  priv->txbuffer = (void*)ptr;
+}
+
+static void ssi_txuint8(struct lm3s_ssidev_s *priv)
+{
+  uint8_t *ptr   = (uint8_t*)priv->txbuffer;
+  ssivdbg("TX: %p->%02x\n", ptr, *ptr);
+  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
+  priv->txbuffer = (void*)ptr;
+}
+
+/****************************************************************************
+ * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8
+ *
+ * Description:
+ *   Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the
+ *   user rxvbuffer and update the rxbuffer pointer appropriately.  The
+ *   selected function dependes on (1) if there is a desination rxbuffer
+ *   provided, and (2) if the number of bits per word is <=8 or >8.
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void ssi_rxnull(struct lm3s_ssidev_s *priv)
+{
+#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
+  uint32_t regval  = ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  ssivdbg("RX: discard %04x\n", regval);
+#else
+  (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+#endif
+}
+
+static void ssi_rxuint16(struct lm3s_ssidev_s *priv)
+{
+  uint16_t *ptr    = (uint16_t*)priv->rxbuffer;
+  *ptr           = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
+  priv->rxbuffer = (void*)(++ptr);
+}
+
+static void ssi_rxuint8(struct lm3s_ssidev_s *priv)
+{
+  uint8_t *ptr   = (uint8_t*)priv->rxbuffer;
+  *ptr           = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
+  priv->rxbuffer = (void*)(++ptr);
+}
+
+/****************************************************************************
+ * Name: ssi_txfifofull
+ *
+ * Description:
+ *   Return true if the Tx FIFO is full
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   true: Not full
+ *
+ ****************************************************************************/
+
+static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv)
+{
+  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
+}
+
+/****************************************************************************
+ * Name: ssi_rxfifoempty
+ *
+ * Description:
+ *   Return true if the Rx FIFO is empty
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   true: Not empty
+ *
+ ****************************************************************************/
+
+static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv)
+{
+  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
+}
+
+/****************************************************************************
+ * Name: ssi_performtx
+ *
+ * Description:
+ *   If the Tx FIFO is empty, then transfer as many words as we can to
+ *   the FIFO.
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   The number of words written to the Tx FIFO (a value from 0 to 8,
+ *   inclusive).
+ *
+ ****************************************************************************/
+
+#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT)
+static inline int ssi_performtx(struct lm3s_ssidev_s *priv)
+{
+  /* Check if the Tx FIFO is full and more data to transfer */
+
+  if (!ssi_txfifofull(priv) && priv->ntxwords > 0)
+    {
+      /* Transfer one word to the Tx FIFO */
+
+      priv->txword(priv);
+      priv->ntxwords--;
+      return 1;
+    }
+  return 0;
+}
+
+#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */
+
+static int ssi_performtx(struct lm3s_ssidev_s *priv)
+{
+#ifndef CONFIG_SSI_POLLWAIT
+  uint32_t regval;
+#endif
+  int ntxd = 0;  /* Number of words written to Tx FIFO */
+
+  /* Check if the Tx FIFO is full */
+
+  if (!ssi_txfifofull(priv))
+    {
+      /* Not full.. Check if all of the Tx words have been sent */
+
+      if (priv->ntxwords > 0)
+        {
+          /* No.. Transfer more words until either the Tx FIFO is full or
+           * until all of the user provided data has been sent.
+           */
+#ifdef CONFIG_SSI_TXLIMIT
+          /* Further limit the number of words that we put into the Tx
+           * FIFO to CONFIG_SSI_TXLIMIT.  Otherwise, we could
+           * overrun the Rx FIFO on a very fast SSI bus.
+           */
+          for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++)
+#else
+          for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++)
+#endif
+            {
+               priv->txword(priv);
+            }
+
+          /* Update the count of words to to transferred */
+
+          priv->ntxwords -= ntxd;
+        }
+
+      /* Check again... Now have all of the Tx words been sent? */
+
+#ifndef CONFIG_SSI_POLLWAIT
+      regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
+      if (priv->ntxwords > 0)
+        {
+          /* No.. Enable the Tx FIFO interrupt.  This interrupt occurs
+           * when the Tx FIFO is 1/2 full or less.
+           */
+
+#ifdef CONFIG_DEBUG
+          regval |= (SSI_IM_TX|SSI_RIS_ROR);
+#else
+          regval |= SSI_IM_TX;
+#endif
+        }
+      else
+        {
+          /* Yes.. Disable the Tx FIFO interrupt.  The final stages of
+           * the transfer will be driven by Rx FIFO interrupts.
+           */
+
+          regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
+        }
+      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
+#endif /* CONFIG_SSI_POLLWAIT */
+    }
+  return ntxd;
+}
+
+#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */
+
+/****************************************************************************
+ * Name: ssi_performrx
+ *
+ * Description:
+ *   Transfer as many bytes as possible from the Rx FIFO to the user Rx
+ *   buffer (if one was provided).
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void ssi_performrx(struct lm3s_ssidev_s *priv)
+{
+#ifndef CONFIG_SSI_POLLWAIT
+  uint32_t regval;
+#endif
+
+  /* Loop while data is available in the Rx FIFO */
+
+  while (!ssi_rxfifoempty(priv))
+    {
+      /* Have all of the requested words been transferred from the Rx FIFO? */
+
+      if (priv->nrxwords < priv->nwords)
+        {
+          /* No.. Read more data from Rx FIFO */
+
+          priv->rxword(priv);
+          priv->nrxwords++;
+        }
+    }
+
+  /* The Rx FIFO is now empty.  While there is Tx data to be sent, the
+   * transfer will be driven by Tx FIFO interrupts.  The final part
+   * of the transfer is driven by Rx FIFO interrupts only.
+   */
+
+#ifndef CONFIG_SSI_POLLWAIT
+  regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
+  if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
+    {
+       /* There are no more outgoing words to send, but there are
+        * additional incoming words expected (I would think that this
+        * a real corner case, be we will handle it with an extra 
+        * interrupt, probably an Rx timeout).
+        */
+
+#ifdef CONFIG_DEBUG
+      regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR);
+#else
+      regval |= (SSI_IM_RX|SSI_IM_RT);
+#endif
+    }
+  else
+    {
+      /* No.. there are either more Tx words to send or all Rx words
+       * have received.  Disable Rx FIFO interrupts.
+       */
+
+      regval &= ~(SSI_IM_RX|SSI_IM_RT);
+    }
+  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
+#endif /* CONFIG_SSI_POLLWAIT */
+}
+
+/****************************************************************************
+ * Name: ssi_transfer
+ *
+ * Description:
+ *   Exchange a block data with the SPI device
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   txbuffer - The buffer of data to send to the device (may be NULL).
+ *   rxbuffer - The buffer to receive data from the device (may be NULL).
+ *   nwords   - The total number of words to be exchanged.  If the interface
+ *              uses <= 8 bits per word, then this is the number of uint8_t's;
+ *              if the interface uses >8 bits per word, then this is the
+ *              number of uint16_t's
+ *
+ * Returned Value:
+ *   0: success, <0:Negated error number on failure
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer,
+                        void *rxbuffer, unsigned int nwords)
+{
+#ifndef CONFIG_SSI_POLLWAIT
+  irqstate_t flags;
+#endif
+  int ntxd;
+
+  ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords);
+
+  /* Set up to perform the transfer */
+
+  priv->txbuffer     = (uint8_t*)txbuffer; /* Source buffer */
+  priv->rxbuffer     = (uint8_t*)rxbuffer; /* Destination buffer */
+  priv->ntxwords     = nwords;             /* Number of words left to send */
+  priv->nrxwords     = 0;                  /* Number of words received */
+  priv->nwords       = nwords;             /* Total number of exchanges */
+
+  /* Set up the low-level data transfer function pointers */
+
+  if (priv->nbits > 8)
+    {
+      priv->txword = ssi_txuint16;
+      priv->rxword = ssi_rxuint16;
+    }
+  else
+    {
+      priv->txword = ssi_txuint8;
+      priv->rxword = ssi_rxuint8;
+    }
+
+  if (!txbuffer)
+    {
+      priv->txword = ssi_txnull;
+    }
+
+  if (!rxbuffer)
+    {
+      priv->rxword = ssi_rxnull;
+    }
+
+  /* Prime the Tx FIFO to start the sequence (saves one interrupt).
+   * At this point, all SSI interrupts should be disabled, but the
+   * operation of ssi_performtx() will set up the interrupts
+   * approapriately (if nwords > TxFIFO size).
+   */
+
+#ifndef CONFIG_SSI_POLLWAIT
+  flags = irqsave();
+  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
+          priv->ntxwords, priv->nrxwords, priv->nwords,
+          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
+
+  ntxd  = ssi_performtx(priv);
+
+  /* For the case where nwords < Tx FIFO size, ssi_performrx will
+   * configure interrupts correctly for the final phase of the
+   * the transfer.
+   */
+
+  ssi_performrx(priv);
+
+  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
+          priv->ntxwords, priv->nrxwords, priv->nwords,
+          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
+          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
+
+  /* Wait for the transfer to complete.  Since there is no handshake
+   * with SPI, the following should complete even if there are problems
+   * with the transfer, so it should be safe with no timeout.
+   */
+
+  ssivdbg("Waiting for transfer complete\n");
+  irqrestore(flags);
+  do
+    {
+      ssi_semtake(&priv->xfrsem);
+    }
+  while (priv->nrxwords < priv->nwords);
+  ssidbg("Transfer complete\n");
+
+#else
+  /* Perform the transfer using polling logic.  This will totally
+   * dominate the CPU until the transfer is complete.  Only recommended
+   * if (1) your SPI is very fast, and (2) if you only use very short
+   * transfers.
+   */
+
+  do
+    {
+      /* Handle outgoing Tx FIFO transfers */
+
+      ntxd = ssi_performtx(priv);
+
+      /* Handle incoming Rx FIFO transfers */
+
+      ssi_performrx(priv);
+
+      /* If there are other threads at this same priority level,
+       * the following may help:
+       */
+
+      sched_yield();
+    }
+  while (priv->nrxwords < priv->nwords);
+#endif
+  return OK;
+}
+
+/****************************************************************************
+ * Name: ssi_mapirq
+ *
+ * Description:
+ *   Map an IRQ number into the appropriate SSI device
+ *
+ * Input Parameters:
+ *   irq   - The IRQ number to be mapped
+ *
+ * Returned Value:
+ *   On success, a reference to the private data structgure for this IRQ.
+ *   NULL on failure.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SSI_POLLWAIT
+static inline struct lm3s_ssidev_s *ssi_mapirq(int irq)
+{
+  switch (irq)
+    {
+#ifndef CONFIG_SSI0_DISABLE
+      case LM3S_IRQ_SSI0:
+        return &g_ssidev[SSI0_NDX];
+#endif
+#ifndef CONFIG_SSI1_DISABLE
+      case LM3S_IRQ_SSI1:
+        return &g_ssidev[SSI1_NDX];
+#endif
+      default:
+        return NULL;
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_interrupt
+ *
+ * Description:
+ *   Exchange a block data with the SSI device
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   txbuffer - The buffer of data to send to the device (may be NULL).
+ *   rxbuffer - The buffer to receive data from the device (may be NULL).
+ *   nwords   - The total number of words to be exchanged.  If the interface
+ *              uses <= 8 bits per word, then this is the number of uint8_t's;
+ *              if the interface uses >8 bits per word, then this is the
+ *              number of uint16_t's
+ *
+ * Returned Value:
+ *   0: success, <0:Negated error number on failure
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SSI_POLLWAIT
+static int ssi_interrupt(int irq, void *context)
+{
+  struct lm3s_ssidev_s *priv = ssi_mapirq(irq);
+  uint32_t regval;
+  int ntxd;
+
+  DEBUGASSERT(priv != NULL);
+
+  /* Clear pending interrupts */
+
+  regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET);
+  ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval);
+
+  /* Check for Rx FIFO overruns */
+
+#ifdef CONFIG_DEBUG
+  if ((regval & SSI_RIS_ROR) != 0)
+    {
+      lldbg("Rx FIFO Overrun!\n");
+    }
+#endif
+
+  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
+          priv->ntxwords, priv->nrxwords, priv->nwords,
+          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
+
+  /* Handle outgoing Tx FIFO transfers */
+
+  ntxd = ssi_performtx(priv);
+
+  /* Handle incoming Rx FIFO transfers */
+
+  ssi_performrx(priv);
+
+  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
+          priv->ntxwords, priv->nrxwords, priv->nwords,
+          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
+          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
+
+  /* Check if the transfer is complete */
+
+  if (priv->nrxwords >= priv->nwords)
+    {
+      /* Yes.. Disable all SSI interrupt sources */
+
+      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
+
+      /* Wake up the waiting thread */
+
+      ssidbg("Transfer complete\n");
+      ssi_semgive(&priv->xfrsem);
+    }
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_lock
+ *
+ * Description:
+ *   On SPI busses where there are multiple devices, it will be necessary to
+ *   lock SPI to have exclusive access to the busses for a sequence of
+ *   transfers.  The bus should be locked before the chip is selected. After
+ *   locking the SPI bus, the caller should then also call the setfrequency,
+ *   setbits, and setmode methods to make sure that the SPI is properly
+ *   configured for the device.  If the SPI buss is being shared, then it
+ *   may have been left in an incompatible state.
+ *
+ * Input Parameters:
+ *   dev  - Device-specific state data
+ *   lock - true: Lock spi bus, false: unlock SPI bus
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_OWNBUS
+static int ssi_lock(FAR struct spi_dev_s *dev, bool lock)
+{
+  FAR struct lm3s_ssidev_s *priv = (FAR struct lm3s_ssidev_s *)dev;
+
+  if (lock)
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      while (sem_wait(&priv->exclsem) != 0)
+        {
+          /* The only case that an error should occur here is if the wait was awakened
+           * by a signal.
+           */
+
+          ASSERT(errno == EINTR);
+        }
+    }
+  else
+    {
+      (void)sem_post(&priv->exclsem);
+    }
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_setfrequency
+ *
+ * Description:
+ *   Set the SPI frequency.
+ *
+ * Input Parameters:
+ *   dev -       Device-specific state data
+ *   frequency - The SPI frequency requested
+ *
+ * Returned Value:
+ *   Returns the actual frequency selected
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, uint32_t frequency)
+{
+  uint32_t maxdvsr;
+  uint32_t cpsdvsr;
+  uint32_t regval;
+  uint32_t scr;
+  uint32_t actual;
+
+  ssidbg("frequency: %d\n", frequency);
+  DEBUGASSERT(frequency);
+
+  /* Has the frequency changed? */
+
+#ifndef CONFIG_SPI_OWNBUS
+  if (frequency != priv->frequency)
+    {
+#endif
+      /* "The serial bit rate is derived by dividing down the input clock
+       *  (FSysClk). The clock is first divided by an even prescale value
+       *  CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
+       *  (SSI_CPSR) register ... The clock is further divided by a value
+       *  from 1 to 256, which is 1 + SCR, where SCR is the value programmed 
+       *  i n the SSI Control0 (SSICR0) register ...
+       *
+       * "The frequency of the output clock SSIClk is defined by:
+       *
+       *    "SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
+       *
+       * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz,
+       *  the module may not be able to operate at that speed. For master mode,
+       *  the system clock must be at least two times faster than the SSIClk.
+       *  For slave mode, the system clock must be at least 12 times faster
+       *  than the SSIClk."
+       */
+
+      if (frequency > SYSCLK_FREQUENCY/2)
+        {
+          frequency = SYSCLK_FREQUENCY/2;
+        }
+
+      /* Find optimal values for CPSDVSR and SCR.  This loop is inefficient,
+       * but should not have to execute many times.
+       *
+       * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000.
+       *
+       *   maxcvsr = 125
+       *   1. cpsdvsr = 2, scr = 61 -> DONE
+       *
+       *   This would correspond to an actual frequency of:
+       *   50,000,000 / (2 * (62)) = 403,226
+       *
+       * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000.
+       *
+       *   maxcvsr = 2
+       *   1. cpsdvsr = 2, scr = 0 -> DONE
+       *
+       *   This would correspond to an actual frequency of:
+       *   50,000,000 / (2 * (1)) = 25,000,000
+       */
+
+      maxdvsr = SYSCLK_FREQUENCY / frequency;
+      cpsdvsr = 0;
+      do
+        {
+          cpsdvsr += 2;
+          scr = (maxdvsr / cpsdvsr) - 1;
+        }
+      while (scr > 255);
+
+      /* Set CPDVSR */
+
+      DEBUGASSERT(cpsdvsr < 255);
+      ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr);
+
+      /* Set SCR */
+
+      regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval &= ~SSI_CR0_SCR_MASK;
+      regval |= (scr << SSI_CR0_SCR_SHIFT);
+      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
+
+      /* Calcluate the actual frequency */
+
+      actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1));
+
+      /* Save the frequency selection so that subsequent reconfigurations will be
+       * faster.
+       */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->frequency = frequency;
+      priv->actual    = actual;
+    }
+  return priv->actual;
+#else
+  return actual;
+#endif
+}
+
+static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
+{
+  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
+  uint32_t enable;
+  uint32_t actual;
+
+  /* NOTE that the SSI must be disabled when setting any configuration registers. */
+
+  enable = ssi_disable(priv);
+  actual = ssi_setfrequencyinternal(priv, frequency);
+  ssi_enable(priv, enable);
+  return actual;
+}
+
+/****************************************************************************
+ * Name: ssi_setmode
+ *
+ * Description:
+ *   Set the SPI mode. Optional.  See enum spi_mode_e for mode definitions
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   mode - The SPI mode requested
+ *
+ * Returned Value:
+ *   none
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, enum spi_mode_e mode)
+{
+  uint32_t modebits;
+  uint32_t regval;
+
+  ssidbg("mode: %d\n", mode);
+  DEBUGASSERT(priv);
+
+  /* Has the number of bits per word changed? */
+
+#ifndef CONFIG_SPI_OWNBUS
+  if (mode != priv->mode)
+    {
+#endif
+      /* Select the CTL register bits based on the selected mode */
+
+      switch (mode)
+        {
+        case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
+          modebits = 0;
+          break;
+
+        case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
+          modebits = SSI_CR0_SPH;
+          break;
+
+        case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
+          modebits = SSI_CR0_SPO;
+         break;
+
+        case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
+          modebits = SSI_CR0_SPH|SSI_CR0_SPO;
+          break;
+
+        default:
+          return;
+        }
+
+      /* Then set the selected mode: Freescale SPI format, mode0-3 */
+
+      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
+      regval |= modebits;
+      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssivdbg("CR0: %08x\n", regval);
+
+      /* Save the mode so that subsequent re-configuratins will be faster */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->mode = mode;
+    }
+#endif
+}
+
+static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
+{
+  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
+  uint32_t enable;
+
+  /* NOTE that the SSI must be disabled when setting any configuration registers. */
+
+  enable = ssi_disable(priv);
+  ssi_setmodeinternal(priv, mode);
+  ssi_enable(priv, enable);
+}
+
+/****************************************************************************
+ * Name: ssi_setbits
+ *
+ * Description:
+ *   Set the number if bits per word.
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   nbits - The number of bits requests
+ *
+ * Returned Value:
+ *   none
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits)
+{
+  uint32_t regval;
+
+  ssidbg("nbits: %d\n", nbits);
+  DEBUGASSERT(priv);
+  if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
+    {
+      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval &= ~SSI_CR0_DSS_MASK;
+      regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
+      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssivdbg("CR0: %08x\n", regval);
+
+      priv->nbits = nbits;
+    }
+}
+
+static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits)
+{
+  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
+  uint32_t enable;
+
+  /* NOTE that the SSI must be disabled when setting any configuration registers. */
+
+  enable = ssi_disable(priv);
+  ssi_setbitsinternal(priv, nbits);
+  ssi_enable(priv, enable);
+}
+
+/****************************************************************************
+ * Name: ssi_send
+ *
+ * Description:
+ *   Exchange one word on SPI
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *   wd  - The word to send.  the size of the data is determined by the
+ *         number of bits selected for the SPI interface.
+ *
+ * Returned Value:
+ *   response
+ *
+ ****************************************************************************/
+
+static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd)
+{
+  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s*)dev;
+  uint16_t response = 0;
+
+  (void)ssi_transfer(priv, &wd, &response, 1);
+  return response;
+}
+
+/****************************************************************************
+ * Name: SPI_EXCHANGE
+ *
+ * Description:
+ *   Exahange a block of data from SPI. Required.
+ *
+ * Input Parameters:
+ *   dev      - Device-specific state data
+ *   buffer   - A pointer to the buffer of data to be sent
+ *   rxbuffer - A pointer to the buffer in which to recieve data
+ *   nwords   - the length of data that to be exchanged in units of words.
+ *              The wordsize is determined by the number of bits-per-word
+ *              selected for the SPI interface.  If nbits <= 8, the data is
+ *              packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_EXCHANGE
+static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+                         FAR void *rxbuffer, size_t nwords)
+{
+  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
+  (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords);
+}
+#endif
+
+/*************************************************************************
+ * Name: ssi_sndblock
+ *
+ * Description:
+ *   Send a block of data on SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer of data to be sent
+ *   nwords - the length of data to send from the buffer in number of words.
+ *            The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_EXCHANGE
+static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
+{
+  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
+  (void)ssi_transfer(priv, buffer, NULL, nwords);
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_recvblock
+ *
+ * Description:
+ *   Revice a block of data from SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer in which to recieve data
+ *   nwords - the length of data that can be received in the buffer in number
+ *            of words.  The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_EXCHANGE
+static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
+{
+  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
+  (void)ssi_transfer(priv, NULL, buffer, nwords);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_spiinitialize
+ *
+ * Description:
+ *   Initialize common parts the selected SPI port.  Initialization of
+ *   chip select GPIOs must have been performed by board specific logic
+ *   prior to calling this function.  Specifically:  GPIOs should have
+ *   been configured for output, and all chip selects disabled.
+ *
+ *   One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select.  However,
+ *   If multiple devices on on the bus, then multiple chip selects will be
+ *   required.  Theregore, all GPIO chip management is deferred to board-
+ *   specific logic.
+ *
+ * Input Parameter:
+ *   Port number (for hardware that has mutiple SSI interfaces)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *up_spiinitialize(int port)
+{
+  struct lm3s_ssidev_s *priv;
+  irqstate_t flags;
+  uint8_t regval;
+
+  ssidbg("port: %d\n", port);
+ 
+  /* Set up for the selected port */
+
+  flags = irqsave();
+  switch (port)
+    {
+#ifndef CONFIG_SSI0_DISABLE
+    case 0:
+      /* Select SSI0 */
+
+      priv = &g_ssidev[SSI0_NDX];
+
+      /* Enable the SSI0 peripheral */
+
+      regval = getreg32(LM3S_SYSCON_RCGC1);
+      regval |= SYSCON_RCGC1_SSI0;
+      putreg32(regval, LM3S_SYSCON_RCGC1);
+      ssivdbg("RCGC1: %08x\n", regval);
+
+      /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
+       * logic in this file makes no assumptions about chip select)
+       */
+
+      lm3s_configgpio(GPIO_SSI0_CLK);  /* PA2: SSI0 clock (SSI0Clk) */
+   /* lm3s_configgpio(GPIO_SSI0_FSS);     PA3: SSI0 frame (SSI0Fss) */
+      lm3s_configgpio(GPIO_SSI0_RX);   /* PA4: SSI0 receive (SSI0Rx) */
+      lm3s_configgpio(GPIO_SSI0_TX);   /* PA5: SSI0 transmit (SSI0Tx) */
+      break;
+#endif /* CONFIG_SSI0_DISABLE */
+
+#ifndef CONFIG_SSI1_DISABLE
+    case 1:
+      /* Select SSI0 */
+
+      priv = &g_ssidev[SSI1_NDX];
+
+      /* Enable the SSI1 peripheral */
+
+      regval = getreg32(LM3S_SYSCON_RCGC1);
+      regval |= SYSCON_RCGC1_SSI1;
+      putreg32(regval, LM3S_SYSCON_RCGC1);
+      ssivdbg("RCGC1: %08x\n", regval);
+
+      /* Configure SSI1 GPIOs */
+
+      lm3s_configgpio(GPIO_SSI1_CLK);  /* PE0: SSI1 clock (SSI1Clk) */
+   /* lm3s_configgpio(GPIO_SSI1_FSS);     PE1: SSI1 frame (SSI1Fss) */
+      lm3s_configgpio(GPIO_SSI1_RX);   /* PE2: SSI1 receive (SSI1Rx) */
+      lm3s_configgpio(GPIO_SSI1_TX);   /* PE3: SSI1 transmit (SSI1Tx) */
+      break;
+#endif /* CONFIG_SSI1_DISABLE */
+
+    default:
+      irqrestore(flags);
+      return NULL;
+    }
+
+  /* Initialize the state structure */
+
+#ifndef CONFIG_SSI_POLLWAIT
+  sem_init(&priv->xfrsem, 0, 0);
+#endif
+#ifndef CONFIG_SPI_OWNBUS
+  sem_init(&priv->exclsem, 0, 1);
+#endif
+
+  /* Set all CR1 fields to reset state.  This will be master mode. */
+
+  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0);
+
+  /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
+
+  ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0);
+
+  /* Set the initial mode to mode 0.  The application may override
+   * this initial setting using the setmode() method.
+   */
+
+  ssi_setmodeinternal(priv, SPIDEV_MODE0);
+
+  /* Set the initial data width to 8-bits.  The application may
+   * override this initial setting using the setbits() method.
+   */
+
+  ssi_setbitsinternal(priv, 8);
+
+  /* Pick some initialize clock frequency. 400,000Hz is the startup
+   * MMC/SD frequency used for card detection.  The application may
+   * override this setting using the setfrequency() method.
+   */
+
+  ssi_setfrequencyinternal(priv, 400000);
+
+  /* Disable all SSI interrupt sources.  They will be enabled only
+   * while there is an SSI transfer in progress.
+   */
+
+  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
+
+  /* Attach the interrupt */
+
+#ifndef CONFIG_SSI_POLLWAIT
+#if NSSI_ENABLED > 1
+  irq_attach(priv->irq, (xcpt_t)ssi_interrupt);
+#else
+  irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt);
+#endif
+#endif /* CONFIG_SSI_POLLWAIT */
+
+  /* Enable the SSI for operation */
+
+  ssi_enable(priv, SSI_CR1_SSE);
+
+  /* Enable SSI interrupts (They are still disabled at the source). */
+
+#ifndef CONFIG_SSI_POLLWAIT
+#if NSSI_ENABLED > 1
+  up_enable_irq(priv->irq);
+#else
+  up_enable_irq(SSI_IRQ);
+#endif
+#endif /* CONFIG_SSI_POLLWAIT */
+
+  irqrestore(flags);
+  return (FAR struct spi_dev_s *)priv;
+}
+
+#endif /* NSSI_ENABLED > 0 */
diff --git a/nuttx/arch/arm/src/lm/lm3s_start.c b/nuttx/arch/arm/src/lm/lm3s_start.c
new file mode 100644
index 000000000..4dfe92844
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_start.c
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_start.c
+ * arch/arm/src/chip/lm3s_start.c
+ *
+ *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "lm_lowputc.h"
+#include "lm_syscontrol.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern void lm3s_vectors(void);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ *   Print a character on the UART to show boot status.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+#  define showprogress(c) up_lowputc(c)
+#else
+#  define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _start
+ *
+ * Description:
+ *   This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+  const uint32_t *src;
+  uint32_t *dest;
+
+  /* Configure the uart so that we can get debug output as soon as possible */
+
+  up_clockconfig();
+  up_lowsetup();
+  showprogress('A');
+
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+   * certain that there are no issues with the state of global variables.
+   */
+
+  for (dest = &_sbss; dest < &_ebss; )
+    {
+      *dest++ = 0;
+    }
+  showprogress('B');
+
+  /* Move the intialized data section from his temporary holding spot in
+   * FLASH into the correct place in SRAM.  The correct place in SRAM is
+   * give by _sdata and _edata.  The temporary location is in FLASH at the
+   * end of all of the other read-only data (.text, .rodata) at _eronly.
+   */
+
+  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
+    {
+      *dest++ = *src++;
+    }
+  showprogress('C');
+
+  /* Perform early serial initialization */
+
+#ifdef USE_EARLYSERIALINIT
+  up_earlyserialinit();
+#endif
+  showprogress('D');
+
+  /* Initialize onboard resources */
+
+  lm3s_boardinitialize();
+  showprogress('E');
+
+  /* Then start NuttX */
+
+  showprogress('\r');
+  showprogress('\n');
+  os_start();
+
+  /* Shoulnd't get here */
+
+  for(;;);
+}
diff --git a/nuttx/arch/arm/src/lm/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm/lm3s_syscontrol.c
new file mode 100644
index 000000000..87545bec7
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_syscontrol.c
@@ -0,0 +1,315 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_syscontrol.c
+ * arch/arm/src/chip/lm3s_syscontrol.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "chip.h"
+#include "lm_syscontrol.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define RCC_OSCMASK   (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
+#define RCC_XTALMASK  (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN)
+#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2)
+#define RCC_DIVMASK   (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
+#define RCC2_DIVMASK  (SYSCON_RCC2_SYSDIV2_MASK)
+#define FAST_OSCDELAY (512*1024)
+#define SLOW_OSCDELAY (4*1024)
+#define PLLLOCK_DELAY (32*1024)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_delay
+ *
+ * Description:
+ *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
+ *   the time that we wait can be significant and is determined by the previous
+ *   clock setting, not the one that we are configuring.
+ *
+ ****************************************************************************/
+
+static inline void lm3s_delay(uint32_t delay)
+{
+  __asm__ __volatile__("1:\n"
+                       "\tsubs  %0, #1\n"
+                       "\tbne   1b\n"
+                       : "=r"(delay) : "r"(delay));
+}
+
+/****************************************************************************
+ * Name: lm3s_oscdelay
+ *
+ * Description:
+ *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
+ *   the time that we wait can be significant and is determined by the previous
+ *   clock setting, not the one that we are configuring.
+ *
+ ****************************************************************************/
+
+static inline void lm3s_oscdelay(uint32_t rcc, uint32_t rcc2)
+{
+  /* Wait for the oscillator  to stabilize.  A smaller delay is used if the
+   * current clock rate is very slow.
+   */
+
+  uint32_t delay = FAST_OSCDELAY;
+
+  /* Are we currently using RCC2? */
+
+  if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
+    {
+      uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK;
+      if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) ||
+          (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ))
+        {
+          delay = SLOW_OSCDELAY;
+        }
+    }
+
+  /* No.. using srce in RCC */
+
+  else
+    {
+      uint32_t rccsrc  = rcc  & SYSCON_RCC_OSCSRC_MASK;
+      if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ)
+        {
+          delay = SLOW_OSCDELAY;
+        }
+    }
+
+  /* Then delay that number of loops */
+
+  lm3s_delay(delay);
+}
+
+/****************************************************************************
+ * Name: lm3s_plllock
+ *
+ * Description:
+ *   The new RCC values have been selected... wait for the PLL to lock on
+ *
+ ****************************************************************************/
+
+static inline void lm3s_plllock(void)
+{
+  volatile uint32_t delay;
+
+  /* Loop until the lock is achieved or until a timeout occurs */
+
+  for (delay = PLLLOCK_DELAY; delay > 0; delay--)
+    {
+      /* Check if the PLL is locked on */
+
+      if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
+        {
+          /* Yes.. return now */
+
+          return;
+        }
+    }
+
+  /* If we get here, then PLL lock was not achieved */
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_clockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on desired rcc and rcc2 settings.
+ *   This is use to set up the initial clocking but can be used later to
+ *   support slow clocked, low power consumption modes.
+ *
+ ****************************************************************************/
+
+void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2)
+{
+  uint32_t rcc;
+  uint32_t rcc2;
+
+  /* Get the current values of the RCC and RCC2 registers */
+
+  rcc  = getreg32(LM3S_SYSCON_RCC);
+  rcc2 = getreg32(LM3S_SYSCON_RCC2);
+
+  /* Temporarily bypass the PLL and system clock dividers */
+
+  rcc |= SYSCON_RCC_BYPASS;
+  rcc &= ~(SYSCON_RCC_USESYSDIV);
+  putreg32(rcc, LM3S_SYSCON_RCC);
+
+  rcc2 |= SYSCON_RCC2_BYPASS2;
+  putreg32(rcc2, LM3S_SYSCON_RCC2);
+
+  /* We are probably using the main oscillator.  The main oscillator is disabled on
+   * reset and so probably must be enabled here.  The internal oscillator is enabled
+   * on rest and if that is selected, most likely nothing needs to be done.
+   */
+
+  if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) ||
+      ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS)))
+    {
+      /* Enable any selected osciallators (but don't disable any yet) */
+
+      rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
+      putreg32(rcc, LM3S_SYSCON_RCC);
+
+      /* Wait for the newly selected oscillator(s) to settle.  This is tricky because
+       * the time that we wait can be significant and is determined by the previous
+       * clock setting, not the one that we are configuring.
+       */
+
+      lm3s_oscdelay(rcc, rcc2);
+    }
+
+  /* Set the new crystal value, oscillator source and PLL configuration */
+
+  rcc  &= ~RCC_XTALMASK;
+  rcc  |= newrcc & RCC_XTALMASK;
+
+  rcc2 &= ~RCC2_XTALMASK;
+  rcc2 |= newrcc2 & RCC2_XTALMASK;
+
+  /* Clear the PLL lock interrupt */
+
+  putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC);
+
+  /* Write the new RCC/RCC2 values.  Order depends upon whether RCC2 or RCC
+   * is currently enabled.
+   */
+
+  if (rcc2 & SYSCON_RCC2_USERCC2)
+    {
+      putreg32(rcc2, LM3S_SYSCON_RCC2);
+      putreg32(rcc, LM3S_SYSCON_RCC);
+    }
+    else
+    {
+      putreg32(rcc, LM3S_SYSCON_RCC);
+      putreg32(rcc2, LM3S_SYSCON_RCC2);
+    }
+
+  /* Wait for the new crystal value and oscillator source to take effect */
+
+  lm3s_delay(16);
+
+  /* Set the requested system divider and disable the non-selected osciallators */
+
+  rcc &= ~RCC_DIVMASK;
+  rcc |= newrcc & RCC_DIVMASK;
+
+  rcc2 &= ~RCC2_DIVMASK;
+  rcc2 |= newrcc2 & RCC2_DIVMASK;
+
+  /* Will the PLL output be used to clock the system? */
+
+  if ((newrcc & SYSCON_RCC_BYPASS) == 0)
+    {
+      /* Yes, wail untill the PLL is locked */
+
+      lm3s_plllock();
+
+      /* Then enable the PLL */
+
+      rcc  &= ~SYSCON_RCC_BYPASS;
+      rcc2 &= ~SYSCON_RCC2_BYPASS2;
+    }
+
+  /* Now we can set the final RCC/RCC2 values */
+
+  putreg32(rcc, LM3S_SYSCON_RCC);
+  putreg32(rcc2, LM3S_SYSCON_RCC2);
+
+  /* Wait for the system divider to be effective */
+
+  lm3s_delay(6);
+}
+
+/****************************************************************************
+ * Name: up_clockconfig
+ *
+ * Description:
+ *   Called early in the bootsequence (before .data and .bss are available)
+ *   in order to configure initial clocking.
+ *
+ ****************************************************************************/
+
+void up_clockconfig(void)
+{
+#ifdef CONFIG_LM3S_REVA2
+  /* Some early silicon returned an increase LDO voltage or 2.75V to work
+   * around a PLL bug
+   */
+
+  putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL);
+#endif
+
+  /* Set the clocking to run with the default settings provided in the board.h
+   * header file
+   */
+
+  lm3s_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE);
+}
+
diff --git a/nuttx/arch/arm/src/lm/lm3s_timerisr.c b/nuttx/arch/arm/src/lm/lm3s_timerisr.c
new file mode 100644
index 000000000..823d810da
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_timerisr.c
@@ -0,0 +1,142 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm3s_timerisr.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "nvic.h"
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ *
+ * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h
+ * header file.
+ */
+
+#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1)
+
+/* The size of the reload field is 24 bits.  Verify taht the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32_t *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+  uint32_t regval;
+
+  /* Set the SysTick interrupt to the default priority */
+
+  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
+  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
+  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
+  putreg32(regval, NVIC_SYSH12_15_PRIORITY);
+
+  /* Configure SysTick to interrupt at the requested rate */
+
+  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr);
+
+  /* Enable SysTick interrupts */
+
+  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(LM3S_IRQ_SYSTICK);
+}
diff --git a/nuttx/arch/arm/src/lm/lm3s_vectors.S b/nuttx/arch/arm/src/lm/lm3s_vectors.S
new file mode 100644
index 000000000..fe92fc954
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm3s_vectors.S
@@ -0,0 +1,805 @@
+/************************************************************************************
+ * arch/arm/src/lm/lm3s_vectors.S
+ * arch/arm/src/chip/lm3s_vectors.S
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/irq.h>
+
+/************************************************************************************
+ * Preprocessor Definitions
+ ************************************************************************************/
+
+/* Memory Map:
+ *
+ * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
+ * 0x0002:0000 - Address of vectors if using bootloader
+ * 0x0003:ffff - End of flash
+ * 0x2000:0000 - Start of SRAM and start of .data (_sdata)
+ *             - End of .data (_edata) abd start of .bss (_sbss)
+ *             - End of .bss (_ebss) and bottom of idle stack
+ *             - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap
+ * 0x2000:ffff - End of SRAM and end of heap
+ */
+
+#define IDLE_STACK		(_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
+#define HEAP_BASE		(_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
+
+/* The Cortex-M3 return from interrupt is unusual.  We provide the following special
+ * address to the BX instruction.  The particular value also forces a return to
+ * thread mode and covers state from the main stack point, the MSP (vs. the MSP).
+ */
+
+#define EXC_RETURN		0xfffffff9
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.globl		__start
+
+	.syntax		unified
+	.thumb
+	.file		"lm3s_vectors.S"
+
+/************************************************************************************
+ * Macros
+ ************************************************************************************/
+
+/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
+ * registers on the stack, then branches to an instantantiation of the following
+ * macro.  This macro simply loads the IRQ number into R0, then jumps to the common
+ * IRQ handling logic.
+ */
+
+	.macro	HANDLER, label, irqno
+	.thumb_func
+\label:
+	mov		r0, #\irqno
+	b		lm3s_irqcommon
+	.endm
+
+/************************************************************************************
+ * Vectors
+ ************************************************************************************/
+
+	.section	.vectors, "ax"
+	.code		16
+	.align		2
+	.globl		lm3s_vectors
+	.type		lm3s_vectors, function
+
+lm3s_vectors:
+
+/* Processor Exceptions */
+
+	.word	IDLE_STACK			/* Vector  0: Reset stack pointer */
+	.word	__start				/* Vector  1: Reset vector */
+	.word	lm3s_nmi			/* Vector  2: Non-Maskable Interrupt (NMI) */
+	.word	lm3s_hardfault		/* Vector  3: Hard fault */
+	.word	lm3s_mpu			/* Vector  4: Memory management (MPU) */
+	.word	lm3s_busfault		/* Vector  5: Bus fault */
+	.word	lm3s_usagefault		/* Vector  6: Usage fault */
+	.word	lm3s_reserved		/* Vector  7: Reserved */
+	.word	lm3s_reserved		/* Vector  8: Reserved */
+	.word	lm3s_reserved		/* Vector  9: Reserved */
+	.word	lm3s_reserved		/* Vector 10: Reserved */
+	.word	lm3s_svcall			/* Vector 11: SVC call */
+	.word	lm3s_dbgmonitor		/* Vector 12: Debug monitor */
+	.word	lm3s_reserved		/* Vector 13: Reserved */
+	.word	lm3s_pendsv			/* Vector 14: Pendable system service request */
+	.word	lm3s_systick		/* Vector 15: System tick */
+
+/* External Interrupts */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm3s_uart0			/* Vector 21: UART 0 */
+	.word	lm3s_uart1			/* Vector 22: UART 1 */
+	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
+	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
+	.word	lm3s_reserved		/* Vector 25: Reserved */
+	.word	lm3s_reserved		/* Vector 26: Reserved */
+	.word	lm3s_reserved		/* Vector 27: Reserved */
+	.word	lm3s_reserved		/* Vector 28: Reserved */
+	.word	lm3s_reserved		/* Vector 29: Reserved */
+	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
+	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
+	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
+	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
+	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
+	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
+	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
+	.word	lm3s_reserved		/* Vector 43: Reserved */
+	.word	lm3s_syscon			/* Vector 44: System Control */
+	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
+	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm3s_gpioh			/* Vector 48: GPIO Port H */
+	.word	lm3s_reserved		/* Vector 49: Reserved */
+	.word	lm3s_ssi1			/* Vector 50: SSI 1 */
+	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
+	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
+	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
+	.word	lm3s_reserved		/* Vector 54: Reserved */
+	.word	lm3s_reserved		/* Vector 55: Reserved */
+	.word	lm3s_reserved		/* Vector 56: Reserved */
+	.word	lm3s_reserved		/* Vector 57: Reserved */
+ 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
+	.word	lm3s_hib			/* Vector 59: Hibernation Module */
+	.word	lm3s_reserved		/* Vector 60: Reserved */
+	.word	lm3s_reserved		/* Vector 61: Reserved */
+	.word	lm3s_reserved		/* Vector 62: Reserved */
+	.word	lm3s_reserved		/* Vector 63: Reserved */
+	.word	lm3s_reserved		/* Vector 64: Reserved */
+	.word	lm3s_reserved		/* Vector 65: Reserved */
+	.word	lm3s_reserved		/* Vector 66: Reserved */
+	.word	lm3s_reserved		/* Vector 67: Reserved */
+	.word	lm3s_reserved		/* Vector 68: Reserved */
+	.word	lm3s_reserved		/* Vector 69: Reserved */
+	.word	lm3s_reserved		/* Vector 70: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm3s_uart0			/* Vector 21: UART 0 */
+	.word	lm3s_uart1			/* Vector 22: UART 1 */
+	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
+	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
+	.word	lm3s_reserved		/* Vector 25: Reserved */
+	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
+	.word	lm3s_reserved		/* Vector 27: Reserved */
+	.word	lm3s_reserved		/* Vector 28: Reserved */
+	.word	lm3s_reserved		/* Vector 29: Reserved */
+	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
+	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
+	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
+	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
+	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
+	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
+	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
+	.word	lm3s_reserved		/* Vector 43: Reserved */
+	.word	lm3s_syscon			/* Vector 44: System Control */
+	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
+	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm3s_reserved		/* Vector 48: Reserved */
+	.word	lm3s_reserved		/* Vector 49: Reserved */
+	.word	lm3s_reserved		/* Vector 50: Reserved */
+	.word	lm3s_reserved		/* Vector 51: Reserved */
+	.word	lm3s_reserved		/* Vector 52: Reserved */
+	.word	lm3s_reserved		/* Vector 53: Reserved */
+	.word	lm3s_reserved		/* Vector 54: Reserved */
+	.word	lm3s_reserved		/* Vector 55: Reserved */
+	.word	lm3s_reserved		/* Vector 56: Reserved */
+	.word	lm3s_reserved		/* Vector 57: Reserved */
+ 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
+	.word	lm3s_reserved		/* Vector 59: Reserved */
+	.word	lm3s_reserved		/* Vector 60: Reserved */
+	.word	lm3s_reserved		/* Vector 61: Reserved */
+	.word	lm3s_reserved		/* Vector 62: Reserved */
+	.word	lm3s_reserved		/* Vector 63: Reserved */
+	.word	lm3s_reserved		/* Vector 64: Reserved */
+	.word	lm3s_reserved		/* Vector 65: Reserved */
+	.word	lm3s_reserved		/* Vector 66: Reserved */
+	.word	lm3s_reserved		/* Vector 67: Reserved */
+	.word	lm3s_reserved		/* Vector 68: Reserved */
+	.word	lm3s_reserved		/* Vector 69: Reserved */
+	.word	lm3s_reserved		/* Vector 70: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm3s_uart0			/* Vector 21: UART 0 */
+	.word	lm3s_uart1			/* Vector 22: UART 1 */
+	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
+	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
+	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
+	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
+	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
+	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
+	.word	lm3s_qei0			/* Vector 29: QEI0 */
+	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
+	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
+	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
+	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
+	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
+	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
+	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
+	.word	lm3s_reserved		/* Vector 43: Reserved */
+	.word	lm3s_syscon			/* Vector 44: System Control */
+	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
+	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm3s_reserved		/* Vector 48: Reserved */
+	.word	lm3s_uart2			/* Vector 49: UART 2 */
+	.word	lm3s_reserved		/* Vector 50: Reserved */
+	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
+	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
+	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
+	.word	lm3s_qei1			/* Vector 54: QEI1 */
+	.word	lm3s_reserved		/* Vector 55: Reserved */
+	.word	lm3s_reserved		/* Vector 56: Reserved */
+	.word	lm3s_reserved		/* Vector 57: Reserved */
+ 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
+	.word	lm3s_hib			/* Vector 59: Hibernation Module */
+	.word	lm3s_reserved		/* Vector 60: Reserved */
+	.word	lm3s_reserved		/* Vector 61: Reserved */
+	.word	lm3s_reserved		/* Vector 62: Reserved */
+	.word	lm3s_reserved		/* Vector 63: Reserved */
+	.word	lm3s_reserved		/* Vector 64: Reserved */
+	.word	lm3s_reserved		/* Vector 65: Reserved */
+	.word	lm3s_reserved		/* Vector 66: Reserved */
+	.word	lm3s_reserved		/* Vector 67: Reserved */
+	.word	lm3s_reserved		/* Vector 68: Reserved */
+	.word	lm3s_reserved		/* Vector 69: Reserved */
+	.word	lm3s_reserved		/* Vector 70: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm3s_uart0			/* Vector 21: UART 0 */
+	.word	lm3s_uart1			/* Vector 22: UART 1 */
+	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
+	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
+	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
+	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
+	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
+	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
+	.word	lm3s_qei0			/* Vector 29: QEI0 */
+	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
+	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
+	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
+	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
+	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
+	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
+	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
+	.word	lm3s_cmp2			/* Vector 43: Reserved */
+	.word	lm3s_syscon			/* Vector 44: System Control */
+	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
+	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm3s_gpioh			/* Vector 48: GPIO Port H */
+	.word	lm3s_uart2			/* Vector 49: UART 2 */
+	.word	lm3s_ssi1			/* Vector 50: SSI 1 */
+	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
+	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
+	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
+	.word	lm3s_qei1			/* Vector 54: QEI1 */
+	.word	lm3s_can0			/* Vector 55: CAN 0 */
+	.word	lm3s_can1			/* Vector 56: CAN 1 */
+	.word	lm3s_reserved		/* Vector 57: Reserved */
+ 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
+	.word	lm3s_reserved		/* Vector 59: Reserved */
+	.word	lm3s_usb			/* Vector 60: USB */
+	.word	lm3s_pwm3			/* Vector 61: PWM 3 */
+	.word	lm3s_udmasoft		/* Vector 62: uDMA Software */
+	.word	lm3s_udmaerror		/* Vector 63: uDMA Error */
+	.word	lm3s_adc1_0			/* Vector 64: ADC1 Sequence 0 */
+	.word	lm3s_adc1_1			/* Vector 65: ADC1 Sequence 1 */
+	.word	lm3s_adc1_2			/* Vector 66: ADC1 Sequence 2 */
+	.word	lm3s_adc1_3			/* Vector 67: ADC1 Sequence 3 */
+	.word	lm3s_i2s0 			/* Vector 68: I2S 0 */
+	.word	lm3s_epi			/* Vector 69: Reserved */
+	.word	lm3s_gpioj			/* Vector 70: GPIO J */
+	.word	lm3s_reserved		/* Vector 71: Reserved */
+	#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm3s_uart0			/* Vector 21: UART 0 */
+	.word	lm3s_uart1			/* Vector 22: UART 1 */
+	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
+	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
+	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
+	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
+	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
+	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
+	.word	lm3s_qei0			/* Vector 29: QEI0 */
+	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
+	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
+	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
+	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
+	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
+	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
+	.word	lm3s_reserved		/* Vector 42: Reserved */
+	.word	lm3s_reserved		/* Vector 43: Reserved */
+	.word	lm3s_syscon			/* Vector 44: System Control */
+	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
+	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm3s_reserved		/* Vector 48: Reserved */
+	.word	lm3s_reserved		/* Vector 49: Reserved */
+	.word	lm3s_reserved		/* Vector 50: Reserved */
+	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
+	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
+	.word	lm3s_reserved		/* Vector 53: Reserved*/
+	.word	lm3s_qei1			/* Vector 54: QEI1 */
+	.word	lm3s_can0			/* Vector 55: Can Controller */
+	.word	lm3s_reserved		/* Vector 56: Reserved */
+	.word	lm3s_reserved		/* Vector 57: Reserved */
+ 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
+	.word	lm3s_hib			/* Vector 59: Hibernation Module */
+	.word	lm3s_reserved		/* Vector 60: Reserved */
+	.word	lm3s_reserved		/* Vector 61: Reserved */
+	.word	lm3s_reserved		/* Vector 62: Reserved */
+	.word	lm3s_reserved		/* Vector 63: Reserved */
+	.word	lm3s_reserved		/* Vector 64: Reserved */
+	.word	lm3s_reserved		/* Vector 65: Reserved */
+	.word	lm3s_reserved		/* Vector 66: Reserved */
+	.word	lm3s_reserved		/* Vector 67: Reserved */
+	.word	lm3s_reserved		/* Vector 68: Reserved */
+	.word	lm3s_reserved		/* Vector 69: Reserved */
+	.word	lm3s_reserved		/* Vector 70: Reserved */
+#else
+#  error "Vectors not specified for this LM3S chip"
+#endif
+	.size	lm3s_vectors, .-lm3s_vectors
+
+/************************************************************************************
+ * .text
+ ************************************************************************************/
+
+	.text
+	.type	handlers, function
+	.thumb_func
+handlers:
+	HANDLER	lm3s_reserved, LM3S_IRQ_RESERVED		/* Unexpected/reserved vector */
+	HANDLER	lm3s_nmi, LM3S_IRQ_NMI					/* Vector  2: Non-Maskable Interrupt (NMI) */
+	HANDLER	lm3s_hardfault, LM3S_IRQ_HARDFAULT		/* Vector  3: Hard fault */
+	HANDLER	lm3s_mpu, LM3S_IRQ_MEMFAULT				/* Vector  4: Memory management (MPU) */
+	HANDLER	lm3s_busfault, LM3S_IRQ_BUSFAULT		/* Vector  5: Bus fault */
+	HANDLER	lm3s_usagefault, LM3S_IRQ_USAGEFAULT	/* Vector  6: Usage fault */
+	HANDLER	lm3s_svcall, LM3S_IRQ_SVCALL			/* Vector 11: SVC call */
+	HANDLER	lm3s_dbgmonitor, LM3S_IRQ_DBGMONITOR	/* Vector 12: Debug Monitor */
+	HANDLER	lm3s_pendsv, LM3S_IRQ_PENDSV			/* Vector 14: Penable system service request */
+	HANDLER	lm3s_systick, LM3S_IRQ_SYSTICK			/* Vector 15: System tick */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+	HANDLER	lm3s_gpioh, LM3S_IRQ_GPIOH				/* Vector 48: GPIO Port H */
+	HANDLER	lm3s_ssi1, LM3S_IRQ_SSI1				/* Vector 50: SSI 1 */
+	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
+ 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+ 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+	HANDLER	lm3s_uart2, LM3S_IRQ_UART1				/* Vector 49: UART 1 */
+	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
+ 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+	HANDLER	lm3s_uart2, LM3S_IRQ_UART1				/* Vector 49: UART 1 */
+	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER	lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
+	HANDLER	lm3s_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
+ 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm3s_cmp2, LM3S_IRQ_COMPARE2			/* Vector 43: Analog Comparator 2 */
+	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+	HANDLER	lm3s_gpioh, LM3S_IRQ_GPIOH				/* Vector 48: GPIO Port H */
+	HANDLER	lm3s_uart2, LM3S_IRQ_UART2				/* Vector 49: UART 2 */
+	HANDLER	lm3s_ssi1, LM3S_IRQ_SSI1				/* Vector 50: GPIO Port H */
+	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER	lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
+ 	HANDLER	lm3s_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
+	HANDLER	lm3s_can1, LM3S_IRQ_CAN1				/* Vector 56: CAN 1 */
+	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+ 	HANDLER	lm3s_usb, LM3S_IRQ_USB					/* Vector 60: USB */
+ 	HANDLER	lm3s_pwm3, LM3S_IRQ_PWM3				/* Vector 61: PWM 3  */
+ 	HANDLER	lm3s_udmasoft, LM3S_IRQ_UDMASOFT		/* Vector 62: uDMA Software  */
+ 	HANDLER	lm3s_udmaerror, LM3S_IRQ_UDMAERROR		/* Vector 63: uDMA Error */
+ 	HANDLER	lm3s_adc1_0, LM3S_IRQ_ADC1_0			/* Vector 64: ADC1 Sequence 0 */
+ 	HANDLER	lm3s_adc1_1, LM3S_IRQ_ADC1_1			/* Vector 65: ADC1 Sequence 1 */
+ 	HANDLER	lm3s_adc1_2, LM3S_IRQ_ADC1_2			/* Vector 66: ADC1 Sequence 2 */
+ 	HANDLER	lm3s_adc1_3, LM3S_IRQ_ADC1_3			/* Vector 67: ADC1 Sequence 3 */
+ 	HANDLER	lm3s_i2s0, LM3S_IRQ_I2S0				/* Vector 68: I2S 0 */
+ 	HANDLER	lm3s_epi, LM3S_IRQ_EPI					/* Vector 69: EPI  */
+ 	HANDLER	lm3s_gpioj, LM3S_IRQ_GPIOJ				/* Vector 70: GPIO Port J */
+#else
+#  error "Vectors not specified for this LM3S chip"
+#endif
+
+/* Common IRQ handling logic.  On entry here, the return stack is on either
+ * the PSP or the MSP and looks like the following:
+ *
+ *      REG_XPSR
+ *      REG_R15
+ *      REG_R14
+ *      REG_R12
+ *      REG_R3
+ *      REG_R2
+ *      REG_R1
+ * MSP->REG_R0
+ *
+ * And
+ *      R0 contains the IRQ number
+ *      R14 Contains the EXC_RETURN value
+ *      We are in handler mode and the current SP is the MSP
+ */
+
+lm3s_irqcommon:
+
+	/* Complete the context save */
+
+#ifdef CONFIG_NUTTX_KERNEL
+	/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
+	 * (handler mode) if the state is on the MSP.  It can only be on the PSP if
+	 * EXC_RETURN is 0xfffffffd (unprivileged thread)
+	 */
+
+	adds	r2, r14, #3				/* If R14=0xfffffffd, then r2 == 0 */
+	ite		ne						/* Next two instructions are condition */
+	mrsne	r1, msp					/* R1=The main stack pointer */
+	mrseq	r1, psp					/* R1=The process stack pointer */
+#else
+	mrs		r1, msp					/* R1=The main stack pointer */
+#endif
+
+	mov		r2, r1					/* R2=Copy of the main/process stack pointer */
+	add		r2, #HW_XCPT_SIZE		/* R2=MSP/PSP before the interrupt was taken */
+	mrs		r3, primask				/* R3=Current PRIMASK setting */
+#ifdef CONFIG_NUTTX_KERNEL 
+	stmdb	r1!, {r2-r11,r14}		/* Save the remaining registers plus the SP value */
+#else
+	stmdb	r1!, {r2-r11}			/* Save the remaining registers plus the SP value */
+#endif
+
+	/* Disable interrupts, select the stack to use for interrupt handling
+	 * and call up_doirq to handle the interrupt
+	 */
+
+	cpsid	i						/* Disable further interrupts */
+
+	/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
+	 * stack pointer.  The way that this is done here prohibits nested interrupts!
+	 * Otherwise, we will re-use the main stack for interrupt level processing.
+	 */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	ldr		sp, =g_intstackbase
+	str		r1, [sp, #-4]!			/* Save the MSP on the interrupt stack */
+	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */
+	ldr		r1, [sp, #+4]!			/* Recover R1=main stack pointer */
+#else
+	mov		sp, r1					/* We are using the main stack pointer */
+	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */
+	mov		r1, sp					/* Recover R1=main stack pointer */
+#endif
+
+	/* On return from up_doirq, R0 will hold a pointer to register context
+	 * array to use for the interrupt return.  If that return value is the same
+	 * as current stack pointer, then things are relatively easy.
+	 */
+
+	cmp		r0, r1					/* Context switch? */
+	beq		1f						/* Branch if no context switch */
+
+	/* We are returning with a pending context switch.  This case is different
+	 * because in this case, the register save structure does not lie on the
+	 * stack but, rather, are within a TCB structure.  We'll have to copy some
+	 * values to the stack.
+	 */
+
+	add		r1, r0, #SW_XCPT_SIZE	/* R1=Address of HW save area in reg array */
+	ldmia	r1, {r4-r11}			/* Fetch eight registers in HW save area */
+	ldr		r1, [r0, #(4*REG_SP)]	/* R1=Value of SP before interrupt */
+	stmdb	r1!, {r4-r11}			/* Store eight registers in HW save area */
+#ifdef CONFIG_NUTTX_KERNEL 
+	ldmia	r0, {r2-r11,r14}		/* Recover R4-R11, r14 + 2 temp values */
+#else
+	ldmia	r0, {r2-r11}			/* Recover R4-R11 + 2 temp values */
+#endif
+	b		2f						/* Re-join common logic */
+
+	/* We are returning with no context switch.  We simply need to "unwind"
+	 * the same stack frame that we created
+	 */
+1:
+#ifdef CONFIG_NUTTX_KERNEL 
+	ldmia	r1!, {r2-r11,r14}		/* Recover R4-R11, r14 + 2 temp values */
+#else
+	ldmia	r1!, {r2-r11}			/* Recover R4-R11 + 2 temp values */
+#endif
+2:
+#ifdef CONFIG_NUTTX_KERNEL
+	/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
+	 * (handler mode) if the state is on the MSP.  It can only be on the PSP if
+	 * EXC_RETURN is 0xfffffffd (unprivileged thread)
+	 */
+
+	adds	r0, r14, #3				/* If R14=0xfffffffd, then r0 == 0 */
+	ite		ne						/* Next two instructions are condition */
+	msrne	msp, r1					/* R1=The main stack pointer */
+	msreq	psp, r1					/* R1=The process stack pointer */
+#else
+	msr		msp, r1					/* Recover the return MSP value */
+
+	/* Preload r14 with the special return value first (so that the return
+	 * actually occurs with interrupts still disabled).
+	 */
+
+	ldr		r14, =EXC_RETURN		/* Load the special value */
+#endif
+
+    /* Restore the interrupt state */
+
+	msr		primask, r3				/* Restore interrupts */
+
+	/* Always return with R14 containing the special value that will: (1)
+	 * return to thread mode, and (2) continue to use the MSP
+	 */
+
+	bx		r14						/* And return */
+	.size	handlers, .-handlers
+
+/************************************************************************************
+ *  Name: up_interruptstack/g_intstackbase
+ *
+ * Description:
+ *   Shouldn't happen
+ *
+ ************************************************************************************/
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	.bss
+	.global	g_intstackbase
+	.align	4
+up_interruptstack:
+	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
+g_intstackbase:
+	.size	up_interruptstack, .-up_interruptstack
+#endif
+
+/************************************************************************************
+ * .rodata
+ ************************************************************************************/
+
+	.section	.rodata, "a"
+
+/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
+ * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
+ * and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE thread is the thread that
+ * the system boots on and, eventually, becomes the idle, do nothing task that runs
+ * only when there is nothing else to run.  The heap continues from there until the
+ * end of memory.  See g_heapbase below.
+ */
+
+	.globl	g_heapbase
+	.type	g_heapbase, object
+g_heapbase:
+	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
+	.size	g_heapbase, .-g_heapbase
+
+	.end
diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.h b/nuttx/arch/arm/src/lm/lm_ethernet.h
new file mode 100644
index 000000000..29fe4fd17
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_ethernet.h
@@ -0,0 +1,103 @@
+/************************************************************************************
+ * arch/arm/src/lm/lm_ethernet.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_LM_ETHERNET_H
+#define __ARCH_ARM_SRC_LM_LM_ETHERNET_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+#if LM3S_NETHCONTROLLERS > 1
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: lm3s_ethinitialize
+ *
+ * Description:
+ *   Initialize the Ethernet driver for one interface.  If the LM3S chip
+ *   supports multiple Ethernet controllers, then bould specific logic
+ *   must implement up_netinitialize() and call this function to initialize
+ *   the desiresed interfaces.
+ *
+ * Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+int lm3s_ethinitialize(int intf);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* LM3S_NETHCONTROLLERS > 1 */
+#endif /* __ARCH_ARM_SRC_LM_LM_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm/lm_gpio.h b/nuttx/arch/arm/src/lm/lm_gpio.h
new file mode 100644
index 000000000..9577fd926
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_gpio.h
@@ -0,0 +1,223 @@
+/************************************************************************************
+ * arch/arm/src/lm/lm_gpio.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_LM_GPIO_H
+#define __ARCH_ARM_SRC_LM_LM_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Bit-encoded input to lm3s_configgpio() *******************************************/
+
+/* Encoding:
+ * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB
+ *
+ * These bits set the primary function of the pin:
+ * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn
+ */
+
+#define GPIO_FUNC_SHIFT               29                         /* Bit 31-29: GPIO function */
+#define GPIO_FUNC_MASK                (7 << GPIO_FUNC_SHIFT)     /* (See table 9-1 in data sheet) */
+#define GPIO_FUNC_INPUT               (0 << GPIO_FUNC_SHIFT)     /*   Digital GPIO input */
+#define GPIO_FUNC_OUTPUT              (1 << GPIO_FUNC_SHIFT)     /*   Digital GPIO output */
+#define GPIO_FUNC_ODINPUT             (2 << GPIO_FUNC_SHIFT)     /*   Open-drain GPIO input */
+#define GPIO_FUNC_ODOUTPUT            (3 << GPIO_FUNC_SHIFT)     /*   Open-drain GPIO output */
+#define GPIO_FUNC_PFODIO              (4 << GPIO_FUNC_SHIFT)     /*   Open-drain input/output (I2C) */
+#define GPIO_FUNC_PFINPUT             (5 << GPIO_FUNC_SHIFT)     /*   Digital input (Timer, CCP) */
+#define GPIO_FUNC_PFOUTPUT            (5 << GPIO_FUNC_SHIFT)     /*   Digital output (Timer, PWM, Comparator) */
+#define GPIO_FUNC_PFIO                (5 << GPIO_FUNC_SHIFT)     /*   Digital input/output (SSI, UART) */
+#define GPIO_FUNC_ANINPUT             (6 << GPIO_FUNC_SHIFT)     /*   Analog input (Comparator) */
+#define GPIO_FUNC_INTERRUPT           (7 << GPIO_FUNC_SHIFT)     /*   Interrupt function */
+#define GPIO_FUNC_MAX                 GPIO_FUNC_INTERRUPT
+
+/* That primary may be modified by the following options
+ * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn
+ */
+
+#define GPIO_STRENGTH_SHIFT           27                         /* Bits 28-27: Pad drive strength */
+#define GPIO_STRENGTH_MASK            (3 << GPIO_STRENGTH_SHIFT)
+#define GPIO_STRENGTH_2MA             (0 << GPIO_STRENGTH_SHIFT) /*   2mA pad drive strength */
+#define GPIO_STRENGTH_4MA             (1 << GPIO_STRENGTH_SHIFT) /*   4mA pad drive strength */
+#define GPIO_STRENGTH_8MA             (2 << GPIO_STRENGTH_SHIFT) /*   8mA pad drive strength */
+#define GPIO_STRENGTH_8MASC           (3 << GPIO_STRENGTH_SHIFT) /*   8mA Pad drive with slew rate control */
+#define GPIO_STRENGTH_MAX             GPIO_STRENGTH_8MASC
+
+#define GPIO_PADTYPE_SHIFT            24                         /* Bits 26-24: Pad type */
+#define GPIO_PADTYPE_MASK             (7 << GPIO_PADTYPE_SHIFT)
+#define GPIO_PADTYPE_STD              (0 << GPIO_PADTYPE_SHIFT)  /*   Push-pull */
+#define GPIO_PADTYPE_STDWPU           (1 << GPIO_PADTYPE_SHIFT)  /*   Push-pull with weak pull-up */
+#define GPIO_PADTYPE_STDWPD           (2 << GPIO_PADTYPE_SHIFT)  /*   Push-pull with weak pull-down */
+#define GPIO_PADTYPE_OD               (3 << GPIO_PADTYPE_SHIFT)  /*   Open-drain */
+#define GPIO_PADTYPE_ODWPU            (4 << GPIO_PADTYPE_SHIFT)  /*   Open-drain with weak pull-up */
+#define GPIO_PADTYPE_ODWPD            (5 << GPIO_PADTYPE_SHIFT)  /*   Open-drain with weak pull-down */
+#define GPIO_PADTYPE_ANALOG           (6 << GPIO_PADTYPE_SHIFT)  /*   Analog comparator */
+
+/* If the pin is an interrupt, then the following options apply
+ * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn
+ */
+
+#define GPIO_INT_SHIFT                21                         /* Bits 23-21: Interrupt type */
+#define GPIO_INT_MASK                 (7 << GPIO_INT_SHIFT)
+#define GPIO_INT_FALLINGEDGE          (0 << GPIO_INT_SHIFT)      /*   Interrupt on falling edge */
+#define GPIO_INT_RISINGEDGE           (1 << GPIO_INT_SHIFT)      /*   Interrupt on rising edge */
+#define GPIO_INT_BOTHEDGES            (2 << GPIO_INT_SHIFT)      /*   Interrupt on both edges */
+#define GPIO_INT_LOWLEVEL             (3 << GPIO_INT_SHIFT)      /*   Interrupt on low level */
+#define GPIO_INT_HIGHLEVEL            (4 << GPIO_INT_SHIFT)      /*   Interrupt on high level */
+
+/* If the pin is an GPIO digital output, then this identifies the initial output value:
+ * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn
+ */
+
+#define GPIO_VALUE_SHIFT              7                          /* Bit 7: If output, inital value of output */
+#define GPIO_VALUE_MASK               (1 << GPIO_VALUE_SHIFT)
+#define GPIO_VALUE_ZERO               (0 << GPIO_VALUE_SHIFT)    /*   Initial value is zero */
+#define GPIO_VALUE_ONE                (1 << GPIO_VALUE_SHIFT)    /*   Initial value is one */
+
+/* This identifies the GPIO port
+ * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn
+ */
+
+#define GPIO_PORT_SHIFT               3                          /* Bit 3-6:  Port number */
+#define GPIO_PORT_MASK                (15 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA                    (0 << GPIO_PORT_SHIFT)     /*   GPIOA */
+#define GPIO_PORTB                    (1 << GPIO_PORT_SHIFT)     /*   GPIOB */
+#define GPIO_PORTC                    (2 << GPIO_PORT_SHIFT)     /*   GPIOC */
+#define GPIO_PORTD                    (3 << GPIO_PORT_SHIFT)     /*   GPIOD */
+#define GPIO_PORTE                    (4 << GPIO_PORT_SHIFT)     /*   GPIOE */
+#define GPIO_PORTF                    (5 << GPIO_PORT_SHIFT)     /*   GPIOF */
+#define GPIO_PORTG                    (6 << GPIO_PORT_SHIFT)     /*   GPIOG */
+#define GPIO_PORTH                    (7 << GPIO_PORT_SHIFT)     /*   GPIOH */
+#define GPIO_PORTJ                    (8 << GPIO_PORT_SHIFT)     /*   GPIOJ */
+
+/* This identifies the bit in the port:
+ * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB
+ */
+
+#define GPIO_NUMBER_SHIFT             0                           /* Bits 0-2: GPIO number: 0-7 */
+#define GPIO_NUMBER_MASK              (7 << GPIO_NUMBER_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int lm3s_configgpio(uint32_t cfgset);
+
+/****************************************************************************
+ * Name: lm3s_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void lm3s_gpiowrite(uint32_t pinset, bool value);
+
+/****************************************************************************
+ * Name: lm3s_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool lm3s_gpioread(uint32_t pinset, bool value);
+
+/****************************************************************************
+ * Function:  lm3s_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the provided base address
+ *
+ ****************************************************************************/
+
+int lm3s_dumpgpio(uint32_t pinset, const char *msg);
+
+/****************************************************************************
+ * Name: gpio_irqinitialize
+ *
+ * Description:
+ *   Initialize all vectors to the unexpected interrupt handler
+ *
+ ****************************************************************************/
+
+int weak_function gpio_irqinitialize(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LM_LM_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.h b/nuttx/arch/arm/src/lm/lm_lowputc.h
new file mode 100644
index 000000000..b384bbd80
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_lowputc.h
@@ -0,0 +1,87 @@
+/************************************************************************************
+ * arch/arm/src/lm/lm3s_lowputc.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_LM_LOWPUTC_H
+#define __ARCH_ARM_SRC_LM_LM_LOWPUTC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Performs low level initialization.
+ *
+ ****************************************************************************/
+
+void up_lowsetup(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LM_LM_LOWPUTC_H */
diff --git a/nuttx/arch/arm/src/lm/lm_ssi.h b/nuttx/arch/arm/src/lm/lm_ssi.h
new file mode 100644
index 000000000..4e7119898
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_ssi.h
@@ -0,0 +1,114 @@
+/************************************************************************************
+ * arch/arm/src/lm/lm_ssi.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_LM_SSI_H
+#define __ARCH_ARM_SRC_LM_LM_SSI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * The external functions, lm3s_spiselect, lm3s_spistatus, and
+ * lm3s_spicmddata must be provided by board-specific logic.  These are
+ * implementations of the select, status, and cmddata methods of the SPI
+ * interface defined by struct spi_ops_s (see include/nuttx/spi.h).
+ * All other methods (including up_spiinitialize()) are provided by common
+ * logic.  To use this common SPI logic on your board:
+ *
+ *   1. Provide logic in lm3s_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
+ *      board-specific logic.  These functions will perform chip selection and
+ *      status operations using GPIOs in the way your board is configured.
+ *   3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide
+ *      the lm3s_spicmddata() function in your board-specific logic.  This
+ *      functions will perform cmd/data selection operations using GPIOs in
+ *      the way your board is configured.
+ *   4. Add a call to up_spiinitialize() in your low level application
+ *      initialization logic
+ *   5. The handle returned by up_spiinitialize() may then be used to bind the
+ *      SPI driver to higher level logic (e.g., calling 
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+struct spi_dev_s;
+enum spi_dev_e;
+void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+#ifdef CONFIG_SPI_CMDDATA
+int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LM_LM_SSI_H */
diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.h b/nuttx/arch/arm/src/lm/lm_syscontrol.h
new file mode 100644
index 000000000..79cc2349d
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_syscontrol.h
@@ -0,0 +1,100 @@
+/************************************************************************************
+ * arch/arm/src/lm/lm3s_syscontrol.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H
+#define __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_clockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on desired rcc and rcc2 settings.
+ *   This is use to set up the initial clocking but can be used later to
+ *   support slow clocked, low power consumption modes.
+ *
+ ****************************************************************************/
+
+void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2);
+
+/****************************************************************************
+ * Name: up_clockconfig
+ *
+ * Description:
+ *   Called early in the bootsequence (before .data and .bss are available)
+ *   in order to configure initial clocking.
+ *
+ ****************************************************************************/
+
+void up_clockconfig(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/lm3s/Kconfig b/nuttx/arch/arm/src/lm3s/Kconfig
deleted file mode 100644
index aaf8342fa..000000000
--- a/nuttx/arch/arm/src/lm3s/Kconfig
+++ /dev/null
@@ -1,199 +0,0 @@
-#
-# For a description of the syntax of this configuration file,
-# see misc/tools/kconfig-language.txt.
-#
-
-comment "LM3S Configuration Options"
-
-choice
-	prompt "LM3S Chip Selection"
-	default ARCH_CHIP_LM3S6965
-	depends on ARCH_CHIP_LM3S
-
-config ARCH_CHIP_LM3S6918
-	bool "LM3S6918"
-	select LM3S_HAVE_SSI1
-
-config ARCH_CHIP_LM3S9B96
-	bool "LM3S9B96"
-
-config ARCH_CHIP_LM3S6432
-	bool "LM3S6432"
-
-config ARCH_CHIP_LM3S6965
-	bool "LM3S6965"
-
-config ARCH_CHIP_LM3S8962
-	bool "LM3S8962"
-
-endchoice
-
-config LM3S_HAVE_SSI1
-	bool
-
-config LM3S_REVA2
-	bool "Rev A2"
-	default n
-	---help---
-		Some early silicon returned an increase LDO voltage or 2.75V to work
-		around a PLL bug
-
-config LM3S_DFU
-	bool "DFU"
-	default y
-
-menu "Select LM3S Peripheral Support"
-
-config LM3S_UART0
-	bool "UART0"
-	select ARCH_HAVE_UART0
-	default n
-
-config LM3S_UART1
-	bool "UART1"
-	select ARCH_HAVE_UART1
-	default n
-
-config SSI0_DISABLE
-	bool "Disable SSI0"
-	default y
-
-config SSI1_DISABLE
-	bool "Disable SSI1"
-	default y
-
-config LM3S_UART2
-	bool "UART2"
-	select ARCH_HAVE_UART2
-	default n
-
-config LM3S_ETHERNET
-	bool "LM3S Ethernet"
-	default n
-	---help---
-		This must be set (along with NET) to build the LM3S Ethernet driver.
-
-endmenu
-
-menu "Disable GPIO Interrupts"
-
-config LM3S_DISABLE_GPIOA_IRQS
-	bool "Disable GPIOA IRQs"
-	default n
-
-config LM3S_DISABLE_GPIOB_IRQS
-	bool "Disable GPIOB IRQs"
-	default n
-
-config LM3S_DISABLE_GPIOC_IRQS
-	bool "Disable GPIOC IRQs"
-	default n
-
-config LM3S_DISABLE_GPIOD_IRQS
-	bool "Disable GPIOD IRQs"
-	default n
-
-config LM3S_DISABLE_GPIOE_IRQS
-	bool "Disable GPIOE IRQs"
-	default n
-
-config LM3S_DISABLE_GPIOF_IRQS
-	bool "Disable GPIOF IRQs"
-	default n
-
-config LM3S_DISABLE_GPIOG_IRQS
-	bool "Disable GPIOG IRQs"
-	default n
-
-config LM3S_DISABLE_GPIOH_IRQS
-	bool "Disable GPIOH IRQs"
-	default n
-
-config LM3S_DISABLE_GPIOJ_IRQS
-	bool "Disable GPIOJ IRQs"
-	default n
-
-endmenu
-
-if LM3S_ETHERNET
-menu "LM3S Ethernet Configuration"
-
-config LM3S_ETHLEDS
-	bool "Ethernet LEDs"
-	default n
-	---help---
-	Enable to use Ethernet LEDs on the board.
-
-config LM3S_BOARDMAC
-	bool "Board MAC"
-	default n
-	---help---
-		If the board-specific logic can provide a MAC address (via
-		lm3s_ethernetmac()), then this should be selected.
-
-config LM3S_ETHHDUPLEX
-	bool "Force Half Duplex"
-	default n
-	---help---
-		Set to force half duplex operation
-
-config LM3S_ETHNOAUTOCRC
-	bool "Disable auto-CRC"
-	default n
-	---help---
-		Set to suppress auto-CRC generation
-
-config LM3S_ETHNOPAD
-	bool "Disable Tx Padding"
-	default n
-	---help---
-		Set to suppress Tx padding
-
-config LM3S_MULTICAST
-	bool "Enable Multicast"
-	default n
-	---help---
-		Set to enable multicast frames
-
-config LM3S_PROMISCUOUS
-	bool "Enable Promiscuous Mode"
-	default n
-	---help---
-		Set to enable promiscuous mode
-
-config LM3S_TIMESTAMP
-	bool "Enable Timestamping"
-	default n
-
-config LM3S_BADCRC
-	bool "Enable Bad CRC Rejection"
-	default n
-	---help---
-		Set to enable bad CRC rejection.
-
-config M3S_DUMPPACKET
-	bool "Dump Packets"
-	default n
-	---help---
-		Dump each packet received/sent to the console.
-
-endmenu
-endif
-
-if !SSI0_DISABLE || !SSI1_DISABLE
-menu "LM3S SSI Configuration"
-
-config SSI_POLLWAIT
-	bool "Poll Wait (No-Interrupt) Mode"
-	default y
-
-config SSI_TXLIMIT
-	int "Tx Limit"
-	default 4
-	---help---
-		Default of 4 assumes half of the 8 entry FIFO
-
-endmenu
-endif
-
-
diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs
deleted file mode 100644
index 66b8f5658..000000000
--- a/nuttx/arch/arm/src/lm3s/Make.defs
+++ /dev/null
@@ -1,64 +0,0 @@
-############################################################################
-# arch/arm/src/lm3s/Make.defs
-#
-#   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-HEAD_ASRC	= lm3s_vectors.S
-
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
-			  vfork.S
-CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
-			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
-			  up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \
-			  up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
-			  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
-			  up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
-			  up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \
-			  up_vfork.c
-
-ifeq ($(CONFIG_ARCH_MEMCPY),y)
-CMN_ASRCS	+= up_memcpy.S
-endif
-
-ifeq ($(CONFIG_ELF),y)
-CMN_CSRCS += up_elf.c
-endif
-
-CHIP_ASRCS	= 
-CHIP_CSRCS	= lm3s_start.c lm3s_syscontrol.c lm3s_irq.c \
-			  lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \
-			  lm3s_serial.c lm3s_ssi.c lm3s_dumpgpio.c
-
-ifdef CONFIG_NET
-CHIP_CSRCS	+= lm3s_ethernet.c
-endif
diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h
deleted file mode 100644
index 481a9be15..000000000
--- a/nuttx/arch/arm/src/lm3s/chip.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip.h
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <arch/lm3s/chip.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Then get all of the register definitions */
-
-#include "chip/lm_memorymap.h"    /* Memory map */
-#include "chip/lm3s_syscontrol.h" /* System control module */
-#include "chip/lm3s_gpio.h"       /* GPIO modules */
-#include "chip/lm3s_uart.h"       /* UART modules */
-#include "chip/lm3s_i2c.h"        /* I2C modules */
-#include "chip/lm3s_ssi.h"        /* SSI modules */
-#include "chip/lm3s_ethernet.h"   /* Ethernet MAC and PHY */
-#include "chip/lm3s_flash.h"      /* FLASH */
-
-/* The LM3S69xx only supports 8 priority levels.  The hardware priority mechanism
- * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
- * the Stellaris family), so any prioritization must be performed in those bits.
- * The default priority level is set to the middle value
- */
-
-#define NVIC_SYSH_PRIORITY_MIN     0xe0 /* All bits set in minimum priority */
-#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
-#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h
deleted file mode 100644
index 5b54d44ac..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_epi.h
- *
- *   Copyright (C) 2009-2013 Max Neklyudov. All rights reserved.
- *   Author: Max Neklyudov <macscomp@gmail.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* External Peripheral Interface Register Offsets ***********************************/
-
-#define LM3S_EPI_CFG_OFFSET           0x000
-#define LM3S_EPI_SDRAMCFG_OFFSET      0x010
-#define LM3S_EPI_ADDRMAP_OFFSET       0x01C
-#define LM3S_EPI_STAT_OFFSET          0x060
-#define LM3S_EPI_BAUD_OFFSET          0x004
-
-/* External Peripheral Interface Register Addresses *********************************/
-
-#define LM3S_EPI0_CFG                 (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
-#define LM3S_EPI0_SDRAMCFG            (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
-#define LM3S_EPI0_ADDRMAP             (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
-#define LM3S_EPI0_STAT                (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
-#define LM3S_EPI0_BAUD                (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
-
-/* External Peripheral Interface Register Bit Definitions ***************************/
-
-/* EPI Configuration (EPICFG), offset 0x000 */
-
-#define EPI_CFG_MODE_SHIFT            0         /* Bits 3-0: Mode Select */
-#define EPI_CFG_MODE_MASK             (0x1f << EPI_CFG_MODE_SHIFT)
-#  define EPI_CFG_MODE_SDRAM          (0x11 << EPI_CFG_MODE_SHIFT)  /* SDRAM + BLKEN */
-
-/* EPI Address Map (EPIADDRMAP), offset 0x01C */
-
-#define EPI_ADDRMAP_ERADR_SHIFT       0       /* Bits 1-0: External RAM Address */
-#define EPI_ADDRMAP_ERADR_MASK        (0x3 << EPI_ADDRMAP_ERADR_SHIFT)
-#  define EPI_ADDRMAP_ERADR_6         (0x1 << EPI_ADDRMAP_ERADR_SHIFT)
-#  define EPI_ADDRMAP_ERADR_8         (0x2 << EPI_ADDRMAP_ERADR_SHIFT)
-#define EPI_ADDRMAP_ERSZ_SHIFT        2       /* Bits 3-2: External RAM Size */
-#define EPI_ADDRMAP_ERSZ_MASK         (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_256B       (0x0 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_64KB       (0x1 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_16MB       (0x2 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_512MB      (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
-
-/* EPI Status (EPISTAT), offset 0x060 */
-
-#define EPI_STAT_INITSEQ_SHIFT        6       /* Bits 6: Initialization Sequence */
-#define EPI_STAT_INITSEQ_MASK         (0x1 << EPI_STAT_INITSEQ_SHIFT)
-
-/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */
-
-#define EPI_SDRAMCFG_SIZE_SHIFT       0       /* Bits 1-0: Size of SDRAM */
-#define EPI_SDRAMCFG_SIZE_MASK        (3 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_8MB       (0x0 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_16MB      (0x1 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_32MB      (0x2 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_64MB      (0x3 << EPI_SDRAMCFG_SIZE_SHIFT)
-#define EPI_SDRAMCFG_RFSH_SHIFT       16      /* Bits 26-16: Refresh Counter */
-#define EPI_SDRAMCFG_RFSH_MASK        (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT)
-#  define EPI_SDRAMCFG_RFSH(n)        ((n) << EPI_SDRAMCFG_RFSH_SHIFT)
-#define EPI_SDRAMCFG_FREQ_SHIFT       30      /* EPI Frequency Range */
-#define EPI_SDRAMCFG_FREQ_MASK        (3 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_0_15MHZ   (0x0 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_15_30MHZ  (0x1 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_30_50MHZ  (0x2 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT)
-
-/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */
-
-#define EPI_BAUD_COUNT0_SHIFT         0
-#define EPI_BAUD_COUNT0_MASK          (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
-#  define EPI_BAUD_COUNT0(n)          ((n) << EPI_BAUD_COUNT0_SHIFT)
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h
deleted file mode 100644
index 940686e7d..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_ethernet.h
- *
- *   Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/net/mii.h>
-
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Ethernet Controller Register Offsets *********************************************/
-
-/* Ethernet MAC Register Offsets */
-
-#define LM3S_MAC_RIS_OFFSET   0x000 /* Ethernet MAC Raw Interrupt Status */
-#define LM3S_MAC_IACK_OFFSET  0x000 /* Ethernet MAC Acknowledge */
-#define LM3S_MAC_IM_OFFSET    0x004 /* Ethernet MAC Interrupt Mask */
-#define LM3S_MAC_RCTL_OFFSET  0x008 /* Ethernet MAC Receive Control */
-#define LM3S_MAC_TCTL_OFFSET  0x00c /* Ethernet MAC Transmit Control */
-#define LM3S_MAC_DATA_OFFSET  0x010 /* Ethernet MAC Data */
-#define LM3S_MAC_IA0_OFFSET   0x014 /* Ethernet MAC Individual Address 0 */
-#define LM3S_MAC_IA1_OFFSET   0x018 /* Ethernet MAC Individual Address 1 */
-#define LM3S_MAC_THR_OFFSET   0x01c /* Ethernet MAC Threshold */
-#define LM3S_MAC_MCTL_OFFSET  0x020 /* Ethernet MAC Management Control */
-#define LM3S_MAC_MDV_OFFSET   0x024 /* Ethernet MAC Management Divider */
-#define LM3S_MAC_MTXD_OFFSET  0x02c /* Ethernet MAC Management Transmit Data */
-#define LM3S_MAC_MRXD_OFFSET  0x030 /* Ethernet MAC Management Receive Data */
-#define LM3S_MAC_NP_OFFSET    0x034 /* Ethernet MAC Number of Packets */
-#define LM3S_MAC_TR_OFFSET    0x038 /* Ethernet MAC Transmission Request */
-#ifdef LM3S_ETHTS
-#  define LM3S_MAC_TS_OFFSET  0x03c /* Ethernet MAC Time Stamp Configuration */
-#endif
-
-/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
-
-/* Ethernet Controller Register Addresses *******************************************/
-
-#define LM3S_MAC_RIS          (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
-#define LM3S_MAC_IACK         (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
-#define LM3S_MAC_IM           (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
-#define LM3S_MAC_RCTL         (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
-#define LM3S_MAC_TCTL         (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
-#define LM3S_MAC_DATA         (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
-#define LM3S_MAC_IA0          (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
-#define LM3S_MAC_IA1          (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
-#define LM3S_MAC_THR          (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
-#define LM3S_MAC_MCTL         (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
-#define LM3S_MAC_MDV          (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
-#define LM3S_MAC_MTXD         (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
-#define LM3S_MAC_MRXD         (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
-#define LM3S_MAC_NP           (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
-#define LM3S_MAC_TR           (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
-#ifdef LM3S_ETHTS
-#  define LM3S_MAC_TS         (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
-#endif
-
-/* Memory Mapped MII Management Registers */
-
-#define MAC_MII_MCR           (LM3S_ETHCON_BASE + MII_MCR)
-#define MAC_MII_MSR           (LM3S_ETHCON_BASE + MII_MSR)
-#define MAC_MII_PHYID1        (LM3S_ETHCON_BASE + MII_PHYID1)
-#define MAC_MII_PHYID2        (LM3S_ETHCON_BASE + MII_PHYID2)
-#define MAC_MII_ADVERTISE     (LM3S_ETHCON_BASE + MII_ADVERTISE)
-#define MAC_MII_LPA           (LM3S_ETHCON_BASE + MII_LPA)
-#define MAC_MII_EXPANSION     (LM3S_ETHCON_BASE + MII_EXPANSION)
-#define MAC_MII_VSPECIFIC     (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
-#define MAC_MII_INTCS         (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
-#define MAC_MII_DIAGNOSTIC    (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
-#define MAC_MII_XCVRCONTROL   (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
-#define MAC_MII_LEDCONFIG     (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
-#define MAC_MII_MDICONTROL    (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
-
-/* Ethernet Controller Register Bit Definitions *************************************/
-
-/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
-
-#define MAC_RIS_RXINT         (1 << 0)  /* Bit 0:  Packet Received */
-#define MAC_RIS_TXER          (1 << 1)  /* Bit 1:  Transmit Error */
-#define MAC_RIS_TXEMP         (1 << 2)  /* Bit 2:  Transmit FIFO Empty */
-#define MAC_RIS_FOV           (1 << 3)  /* Bit 3:  FIFO Overrun */
-#define MAC_RIS_RXER          (1 << 4)  /* Bit 4:  Receive Error */
-#define MAC_RIS_MDINT         (1 << 5)  /* Bit 5:  MII Transaction Complete */
-#define MAC_RIS_PHYINT        (1 << 6)  /* Bit 6:  PHY Interrupt */
-
-#define MAC_IACK_RXINT        (1 << 0)  /* Bit 0:  Clear Packet Received */
-#define MAC_IACK_TXER         (1 << 1)  /* Bit 1:  Clear Transmit Error */
-#define MAC_IACK_TXEMP        (1 << 2)  /* Bit 2:  Clear Transmit FIFO Empty */
-#define MAC_IACK_FOV          (1 << 3)  /* Bit 3:  Clear FIFO Overrun */
-#define MAC_IACK_RXER         (1 << 4)  /* Bit 4:  Clear Receive Error */
-#define MAC_IACK_MDINT        (1 << 5)  /* Bit 5:  Clear MII Transaction Complete */
-#define MAC_IACK_PHYINT       (1 << 6)  /* Bit 6:  Clear PHY Interrupt */
-
-/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
-
-#define MAC_IM_RXINTM         (1 << 0)  /* Bit 0:  Mask Packet Received */
-#define MAC_IM_TXERM          (1 << 1)  /* Bit 1:  Mask Transmit Error */
-#define MAC_IM_TXEMPM         (1 << 2)  /* Bit 2:  Mask Transmit FIFO Empty */
-#define MAC_IM_FOVM           (1 << 3)  /* Bit 3:  Mask FIFO Overrun */
-#define MAC_IM_RXERM          (1 << 4)  /* Bit 4:  Mask Receive Error */
-#define MAC_IM_MDINTM         (1 << 5)  /* Bit 5:  Mask MII Transaction Complete */
-#define MAC_IM_PHYINTM        (1 << 6)  /* Bit 6:  Mask PHY Interrupt */
-#define MAC_IM_ALLINTS        0x7f
-
-/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
-
-#define MAC_RCTL_RXEN         (1 << 0)  /* Bit 0:  Enable Receiver */
-#define MAC_RCTL_AMUL         (1 << 1)  /* Bit 1:  Enable Multicast Frames */
-#define MAC_RCTL_PRMS         (1 << 2)  /* Bit 2:  Enable Promiscuous Mode */
-#define MAC_RCTL_BADCRC       (1 << 3)  /* Bit 3:  Enable Reject Bad CRC */
-#define MAC_RCTL_RSTFIFO      (1 << 4)  /* Bit 4:  Clear Receive FIFO */
-
-/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
-
-#define MAC_TCTL_TXEN         (1 << 0)  /* Bit 0:  Enable Transmitter */
-#define MAC_TCTL_PADEN        (1 << 1)  /* Bit 1:  Enable Packet Padding */
-#define MAC_TCTL_CRC          (1 << 2)  /* Bit 2:  Enable CRC Generation */
-#define MAC_TCTL_DUPLEX       (1 << 4)  /* Bit 4:  Enable Duplex Mode */
-
-/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
-
-#define MAC_THR_MASK          0x3f      /* Bits 5-0: Threshold Value */
-
-/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
-
-#define MAC_MCTL_START        (1 << 0)  /* Bit 0:  MII Register Transaction Enable */
-#define MAC_MCTL_WRITE        (1 << 1)  /* Bit 1:  MII Register Transaction Type */
-#define MAC_MCTL_REGADR_SHIFT 3         /* Bits 7-3: MII Register Address */
-#define MAC_MCTL_REGADR_MASK  (0x1f << MAC_MCTL_REGADR_SHIFT)
-
-/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
-
-#define MAC_MDV_MASK          0xff      /* Bits 7-0: Clock Divider */
-
-/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
-
-#define MAC_MTXD_MASK         0xffff    /* Bits 15-0: MII Register Transmit Data */
-
-/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
-
-#define MAC_MTRD_MASK         0xffff    /* Bits 15-0: MII Register Receive Data */
-
-/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
-
-#define MAC_NP_MASK           0x3f      /* Bits 5-0: Number of Packets in Receive FIFO */
-
-/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
-
-#define MAC_TR_NEWTX          (1 << 0)  /* Bit 0:  New Transmission */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h
deleted file mode 100644
index 2bd8956b0..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_flash.h
- *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* FLASH register offsets ***********************************************************/
-
-/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
- * control base address of LM3S_FLASHCON_BASE.
- */
-
-#define LM3S_FLASH_FMA_OFFSET       0x000 /* Flash memory address */
-#define LM3S_FLASH_FMD_OFFSET       0x004 /* Flash memory data */
-#define LM3S_FLASH_FMC_OFFSET       0x008 /* Flash memory control */
-#define LM3S_FLASH_FCRIS_OFFSET     0x00c /* Flash controller raw interrupt status */
-#define LM3S_FLASH_FCIM_OFFSET      0x010 /* Flash controller interrupt mask */
-#define LM3S_FLASH_FCMISC_OFFSET    0x014 /* Flash controller masked interrupt status and clear */ */
-
-/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
- * System Control base address of LM3S_SYSCON_BASE
- */
-
-#define LM3S_FLASH_FMPRE_OFFSET     0x130 /* Flash memory protection read enable */
-#define LM3S_FLASH_FMPPE_OFFSET     0x134 /* Flash memory protection program enable */
-#define LM3S_FLASH_USECRL_OFFSET    0x140 /* USec Reload */
-#define LM3S_FLASH_USERDBG_OFFSET   0x1d0 /* User Debug */
-#define LM3S_FLASH_USERREG0_OFFSET  0x1e0 /* User Register 0 */
-#define LM3S_FLASH_USERREG1_OFFSET  0x1e4 /* User Register 1 */
-#define LM3S_FLASH_FMPRE0_OFFSET    0x200 /* Flash Memory Protection Read Enable 0 */
-#define LM3S_FLASH_FMPRE1_OFFSET    0x204 /* Flash Memory Protection Read Enable 1 */
-#define LM3S_FLASH_FMPRE2_OFFSET    0x208 /* Flash Memory Protection Read Enable 2 */
-#define LM3S_FLASH_FMPRE3_OFFSET    0x20c /* Flash Memory Protection Read Enable 3 */
-#define LM3S_FLASH_FMPPE0_OFFSET    0x400 /* Flash Memory Protection Program Enable 0 */
-#define LM3S_FLASH_FMPPE1_OFFSET    0x404 /* Flash Memory Protection Program Enable 1 */
-#define LM3S_FLASH_FMPPE2_OFFSET    0x408 /* Flash Memory Protection Program Enable 2 */
-#define LM3S_FLASH_FMPPE3_OFFSET    0x40c /*  Flash Memory Protection Program Enable 3 */
-
-/* FLASH register addresses *********************************************************/
-
-/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
- * control base address of LM3S_FLASHCON_BASE.
- */
-
-#define LM3S_FLASH_FMA              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
-#define LM3S_FLASH_FMD              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
-#define LM3S_FLASH_FMC              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
-#define LM3S_FLASH_FCRIS            (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
-#define LM3S_FLASH_FCIM             (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
-#define LM3S_FLASH_FCMISC           (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
-
-/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
- * System Control base address of LM3S_SYSCON_BASE
- */
-
-#define LM3S_FLASH_FMPRE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
-#define LM3S_FLASH_FMPPE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
-#define LM3S_FLASH_USECRL           (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
-#define LM3S_FLASH_USERDBG          (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
-#define LM3S_FLASH_USERREG0         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
-#define LM3S_FLASH_USERREG1         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
-#define LM3S_FLASH_FMPRE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
-#define LM3S_FLASH_FMPRE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
-#define LM3S_FLASH_FMPRE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
-#define LM3S_FLASH_FMPRE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
-#define LM3S_FLASH_FMPPE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
-#define LM3S_FLASH_FMPPE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
-#define LM3S_FLASH_FMPPE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
-#define LM3S_FLASH_FMPPE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
-
-/* FLASH register bit defitiions ****************************************************/
-/* To be provided */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h
deleted file mode 100644
index 7253c1e7a..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_gpio.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* GPIO Register Offsets ************************************************************/
-
-#define LM3S_GPIO_DATA_OFFSET         0x000 /* GPIO Data */
-#define LM3S_GPIO_DIR_OFFSET          0x400 /* GPIO Direction */
-#define LM3S_GPIO_IS_OFFSET           0x404 /* GPIO Interrupt Sense */
-#define LM3S_GPIO_IBE_OFFSET          0x408 /* GPIO Interrupt Both Edges */
-#define LM3S_GPIO_IEV_OFFSET          0x40c /* GPIO Interrupt Event */
-#define LM3S_GPIO_IM_OFFSET           0x410 /* GPIO Interrupt Mask */
-#define LM3S_GPIO_RIS_OFFSET          0x414 /* GPIO Raw Interrupt Status */
-#define LM3S_GPIO_MIS_OFFSET          0x418 /* GPIO Masked Interrupt Status */
-#define LM3S_GPIO_ICR_OFFSET          0x41c /* GPIO Interrupt Clear */
-#define LM3S_GPIO_AFSEL_OFFSET        0x420 /* GPIO Alternate Function */
-#define LM3S_GPIO_DR2R_OFFSET         0x500 /* Select GPIO 2-mA Drive Select */
-#define LM3S_GPIO_DR4R_OFFSET         0x504 /* GPIO 4-mA Drive Select */
-#define LM3S_GPIO_DR8R_OFFSET         0x508 /* GPIO 8-mA Drive Select */
-#define LM3S_GPIO_ODR_OFFSET          0x50c /* GPIO Open Drain Select */
-#define LM3S_GPIO_PUR_OFFSET          0x510 /* GPIO Pull-Up Select */
-#define LM3S_GPIO_PDR_OFFSET          0x514 /* GPIO Pull-Down Select */
-#define LM3S_GPIO_SLR_OFFSET          0x518 /* GPIO Slew Rate Control Select */
-#define LM3S_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
-#define LM3S_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
-#define LM3S_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
-#define LM3S_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
-#define LM3S_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
-#define LM3S_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
-#define LM3S_GPIO_PERIPHID7_OFFSET    0xfdc /* GPIO Peripheral Identification 7 */
-#define LM3S_GPIO_PERIPHID0_OFFSET    0xfe0 /* GPIO Peripheral Identification 0 */
-#define LM3S_GPIO_PERIPHID1_OFFSET    0xfe4 /* GPIO Peripheral Identification 1 */
-#define LM3S_GPIO_PERIPHID2_OFFSET    0xfe8 /* GPIO Peripheral Identification 2 */
-#define LM3S_GPIO_PERIPHID3_OFFSET    0xfec /* GPIO Peripheral Identification 3 */
-#define LM3S_GPIO_PCELLID0_OFFSET     0xff0 /* GPIO PrimeCell Identification 0 */
-#define LM3S_GPIO_PCELLID1_OFFSET     0xff4 /* GPIO PrimeCell Identification 1 */
-#define LM3S_GPIO_PCELLID2_OFFSET     0xff8 /* GPIO PrimeCell Identification 2 */
-#define LM3S_GPIO_PCELLID3_OFFSET     0xffc /* GPIO PrimeCell Identification 3*/
-
-/* GPIO Register Addresses **********************************************************/
-
-#define LM3S_GPIOA_DATA               (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOA_DIR                (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOA_IS                 (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOA_IBE                (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOA_IEV                (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOA_IM                 (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOA_RIS                (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOA_MIS                (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOA_ICR                (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOA_AFSEL              (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOA_DR2R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOA_DR4R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOA_DR8R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOA_ODR                (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOA_PUR                (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOA_PDR                (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOA_SLR                (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOA_DEN                (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOA_LOCK               (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOA_CR                 (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOA_PERIPHID4          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOA_PERIPHID5          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOA_PERIPHID6          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOA_PERIPHID7          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOA_PERIPHID0          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOA_PERIPHID1          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOA_PERIPHID2          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOA_PERIPHID3          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOA_PCELLID0           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOA_PCELLID1           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOA_PCELLID2           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOA_PCELLID3           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOB_DATA               (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOB_DIR                (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOB_IS                 (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOB_IBE                (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOB_IEV                (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOB_IM                 (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOB_RIS                (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOB_MIS                (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOB_ICR                (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOB_AFSEL              (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOB_DR2R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOB_DR4R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOB_DR8R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOB_ODR                (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOB_PUR                (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOB_PDR                (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOB_SLR                (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOB_DEN                (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOB_LOCK               (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOB_CR                 (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOB_PERIPHID4          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOB_PERIPHID5          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOB_PERIPHID6          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOB_PERIPHID7          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOB_PERIPHID0          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOB_PERIPHID1          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOB_PERIPHID2          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOB_PERIPHID3          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOB_PCELLID0           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOB_PCELLID1           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOB_PCELLID2           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOB_PCELLID3           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOC_DATA               (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOC_DIR                (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOC_IS                 (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOC_IBE                (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOC_IEV                (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOC_IM                 (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOC_RIS                (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOC_MIS                (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOC_ICR                (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOC_AFSEL              (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOC_DR2R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOC_DR4R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOC_DR8R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOC_ODR                (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOC_PUR                (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOC_PDR                (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOC_SLR                (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOC_DEN                (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOC_LOCK               (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOC_CR                 (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOC_PERIPHID4          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOC_PERIPHID5          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOC_PERIPHID6          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOC_PERIPHID7          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOC_PERIPHID0          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOC_PERIPHID1          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOC_PERIPHID2          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOC_PERIPHID3          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOC_PCELLID0           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOC_PCELLID1           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOC_PCELLID2           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOC_PCELLID3           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOD_DATA               (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOD_DIR                (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOD_IS                 (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOD_IBE                (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOD_IEV                (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOD_IM                 (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOD_RIS                (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOD_MIS                (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOD_ICR                (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOD_AFSEL              (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOD_DR2R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOD_DR4R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOD_DR8R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOD_ODR                (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOD_PUR                (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOD_PDR                (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOD_SLR                (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOD_DEN                (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOD_LOCK               (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOD_CR                 (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOD_PERIPHID4          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOD_PERIPHID5          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOD_PERIPHID6          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOD_PERIPHID7          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOD_PERIPHID0          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOD_PERIPHID1          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOD_PERIPHID2          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOD_PERIPHID3          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOD_PCELLID0           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOD_PCELLID1           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOD_PCELLID2           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOD_PCELLID3           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOE_DATA               (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOE_DIR                (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOE_IS                 (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOE_IBE                (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOE_IEV                (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOE_IM                 (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOE_RIS                (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOE_MIS                (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOE_ICR                (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOE_AFSEL              (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOE_DR2R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOE_DR4R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOE_DR8R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOE_ODR                (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOE_PUR                (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOE_PDR                (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOE_SLR                (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOE_DEN                (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOE_LOCK               (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOE_CR                 (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOE_PERIPHID4          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOE_PERIPHID5          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOE_PERIPHID6          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOE_PERIPHID7          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOE_PERIPHID0          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOE_PERIPHID1          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOE_PERIPHID2          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOE_PERIPHID3          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOE_PCELLID0           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOE_PCELLID1           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOE_PCELLID2           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOE_PCELLID3           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOF_DATA               (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOF_DIR                (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOF_IS                 (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOF_IBE                (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOF_IEV                (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOF_IM                 (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOF_RIS                (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOF_MIS                (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOF_ICR                (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOF_AFSEL              (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOF_DR2R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOF_DR4R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOF_DR8R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOF_ODR                (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOF_PUR                (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOF_PDR                (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOF_SLR                (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOF_DEN                (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOF_LOCK               (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOF_CR                 (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOF_PERIPHID4          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOF_PERIPHID5          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOF_PERIPHID6          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOF_PERIPHID7          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOF_PERIPHID0          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOF_PERIPHID1          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOF_PERIPHID2          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOF_PERIPHID3          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOF_PCELLID0           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOF_PCELLID1           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOF_PCELLID2           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOF_PCELLID3           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOG_DATA               (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOG_DIR                (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOG_IS                 (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOG_IBE                (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOG_IEV                (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOG_IM                 (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOG_RIS                (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOG_MIS                (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOG_ICR                (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOG_AFSEL              (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOG_DR2R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOG_DR4R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOG_DR8R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOG_ODR                (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOG_PUR                (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOG_PDR                (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOG_SLR                (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOG_DEN                (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOG_LOCK               (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOG_CR                 (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOG_PERIPHID4          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOG_PERIPHID5          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOG_PERIPHID6          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOG_PERIPHID7          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOG_PERIPHID0          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOG_PERIPHID1          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOG_PERIPHID2          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOG_PERIPHID3          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOG_PCELLID0           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOG_PCELLID1           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOG_PCELLID2           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOG_PCELLID3           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOH_DATA               (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOH_DIR                (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOH_IS                 (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOH_IBE                (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOH_IEV                (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOH_IM                 (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOH_RIS                (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOH_MIS                (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOH_ICR                (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOH_AFSEL              (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOH_DR2R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOH_DR4R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOH_DR8R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOH_ODR                (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOH_PUR                (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOH_PDR                (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOH_SLR                (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOH_DEN                (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOH_LOCK               (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOH_CR                 (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOH_PERIPHID4          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOH_PERIPHID5          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOH_PERIPHID6          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOH_PERIPHID7          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOH_PERIPHID0          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOH_PERIPHID1          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOH_PERIPHID2          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOH_PERIPHID3          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOH_PCELLID0           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOH_PCELLID1           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOH_PCELLID2           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOH_PCELLID3           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOJ_DATA               (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOJ_DIR                (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOJ_IS                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOJ_IBE                (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOJ_IEV                (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOJ_IM                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOJ_RIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOJ_MIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOJ_ICR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOJ_AFSEL              (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOJ_DR2R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOJ_DR4R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOJ_DR8R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOJ_ODR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOJ_PUR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOJ_PDR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOJ_SLR                (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOJ_DEN                (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOJ_LOCK               (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOJ_CR                 (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOJ_PERIPHID4          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOJ_PERIPHID5          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOJ_PERIPHID6          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOJ_PERIPHID7          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOJ_PERIPHID0          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOJ_PERIPHID1          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOJ_PERIPHID2          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOJ_PERIPHID3          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOJ_PCELLID0           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOJ_PCELLID1           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOJ_PCELLID2           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOJ_PCELLID3           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h
deleted file mode 100644
index 71ebe8fcf..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_i2c.h
- *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* I2C Register Offsets *************************************************************/
-
-/* I2C Master */
-
-#define LM3S_I2CM_SA_OFFSET  0x000 /* I2C Master Slave Address */
-#define LM3S_I2CM_CS_OFFSET  0x004 /* I2C Master Control/Status */
-#define LM3S_I2CM_DR_OFFSET  0x008 /* I2C Master Data */
-#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
-#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
-#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
-#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
-#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
-#define LM3S_I2CM_CR_OFFSET  0x020 /* I2C Master Configuration */
-
-/* I2C Slave */
-
-#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
-#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
-#define LM3S_I2CS_DR_OFFSET  0x008 /* I2C Slave Data */
-#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
-#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
-#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
-#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
-
-/* I2C Register Addresses ***********************************************************/
-
-#if LM3S_NI2C > 0
-
-/* I2C Master */
-
-#define LM3S_I2CM_BASE(n)    (LM3S_I2CM0_BASE + (n)*0x1000)
-#define LM3S_I2CM_SA(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM_CS(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM_DR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM_TPR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM_IMR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM_RIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM_MIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM_ICR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM_CR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
-
-/* I2C Slave */
-
-#define LM3S_I2CS_BASE(n)    (LM3S_I2CS0_BASE + (n)*0x1000)
-#define LM3S_I2CS_OAR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS_CSR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS_DR(n)      (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS_IMR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS_RIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS_MIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS_ICR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
-
-/* I2C0 Master */
-
-#define LM3S_I2CM0_SA        (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM0_CS        (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM0_DR        (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM0_TPR       (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM0_IMR       (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM0_RIS       (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM0_MIS       (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM0_ICR       (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM0_CR        (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
-
-/* I2C0 Slave */
-
-#define LM3S_I2CS0_OAR       (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS0_CSR       (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS0_DR        (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS0_IMR       (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS0_RIS       (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS0_MIS       (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS0_ICR       (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
-
-#if LM3S_NI2C > 1
-
-/* I2C1 Master */
-
-#define LM3S_I2CM1_SA        (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM1_CS        (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM1_DR        (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM1_TPR       (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM1_IMR       (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM1_RIS       (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM1_MIS       (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM1_ICR       (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM1_CR        (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
-
-/* I2C1 Slave */
-
-#define LM3S_I2CS1_OAR       (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS1_CSR       (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS1_DR        (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS1_IMR       (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS1_RIS       (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS1_MIS       (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS1_ICR       (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
-
-#endif
-#endif
-
-/* I2C_Register Bit Definitions *****************************************************/
-
-/* I2C Master Slave Address (I2CM_SA), offset 0x000 */
-
-#define I2CM_SA_RS           (1 << 0)  /* Bit 0:  Receive/Send */
-#define I2CM_SA_SA_SHIFT     1         /* Bits 7-1: I2C Slave Address */
-#define I2CM_SA_SA_MASK      (0x7f << I2CM_SA_SA_SHIFT)
-
-/* I2C Master Control/Status (I2CM_CS), offset 0x004 */
-
-#define I2CM_CS_BUSY         (1 << 0)  /* Bit 0:  I2C Busy (read) */
-#define I2CM_CS_ERROR        (1 << 1)  /* Bit 1:  Error in last bus operation (read) */
-#define I2CM_CS_ADRACK       (1 << 2)  /* Bit 2:  Acknowledge Address (read) */
-#define I2CM_CS_DATACK       (1 << 3)  /* Bit 3:  Acknowledge Data (read) */
-#define I2CM_CS_ARBLST       (1 << 4)  /* Bit 4:  Arbitration Lost (read) */
-#define I2CM_CS_IDLE         (1 << 5)  /* Bit 5:  I2C Idle (read) */
-#define I2CM_CS_BUSBSY       (1 << 6)  /* Bit 6:  Bus Busy (read) */
-
-#define I2CM_CS_RUN          (1 << 0)  /* Bit 0:  I2C Master Enable (write) */
-#define I2CM_CS_START        (1 << 1)  /* Bit 1:  Generate START (write) */
-#define I2CM_CS_STOP         (1 << 2)  /* Bit 2:  Generate STOP (write) */
-#define I2CM_CS_ACK          (1 << 3)  /* Bit 3:  Data Acknowledge Enable (write) */
-
-/* I2C Master Data (I2CM_DR), offset 0x008 */
-
-#define I2CM_DR_MASK         0xff      /* Bits 7-0: Data transferred */
-
-/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */
-
-#define I2CM_TPR_MASK        0xff      /* Bits 7-0: SCL Clock Period */
-
-/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */
-
-#define I2CM_IMR_IM          (1 << 0)  /* Bit 0:  Interrupt Mask */
-
-/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */
-
-#define I2CM_RIS_RIS         (1 << 0)  /* Bit 0:  Raw Interrupt Status */
-
-/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */
-
-#define I2CM_MIS_MIS         (1 << 0)  /* Bit 0:  Masked Interrupt Status */
-
-/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */
-
-#define I2CM_ICR_IC          (1 << 0)  /* Bit 0:  Masked Interrupt Status */
-
-/* I2C Master Configuration (I2CM_CR), offset 0x020 */
-
-#define I2CM_CR_LPBK         (1 << 0)  /* Bit 0:: I2C Loopback */
-#define I2CM_CR_MFE          (1 << 4 ) /* Bit 4:  I2C Master Function Enable */
-#define I2CM_CR_SFE          (1 << 5)  /* Bit 5:  I2C Slave Function Enable */
-
-/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */
-
-#define I2CS_OAR_MASK        0xff      /* Bits 7-0: I2C Slave Own Address */
-
-/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */
-
-#define I2CS_CSR_RREQ        (1 << 0)  /* Bit 0:  Receive Request (read) */
-#define I2CS_CSR_TREQ        (1 << 1)  /* Bit 1:  Transmit Request (read) */
-#define I2CS_CSR_FBR         (1 << 2)  /* Bit 2:  First Byte Received (read) */
-
-#define I2CS_CSR_DA          (1 << 0)  /* Bit 0:  Device Active (write) */
-
-/* I2C Slave Data (I2CS_DR), offset 0x008 */
-
-#define I2CS_DR_MASK         0xff      /* Bits 7-0: Data for Transfer */
-
-/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */
-
-#define I2CM_IMR_DATAIM      (1 << 0)  /* Bit 0:  Data Interrupt Mask */
-
-/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */
-
-#define I2CM_RIS_DATARIS     (1 << 0)  /* Bit 0:  Data Raw Interrupt Status */
-
-/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */
-
-#define I2CM_MIS_DATAMIS     (1 << 0)  /* Bit 0:  Data Masked Interrupt Status */
-
-/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */
-
-#define I2CM_ICR_DATAIC      (1 << 0)  /* Bit 0:  Data Interrupt Clear */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h
deleted file mode 100644
index 31dc2b249..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_memorymap.h
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Memory map ***********************************************************************/
- 
-#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
-    defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
-                                         /* -0x1fffffff: Reserved */
-#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
-                                         /* -0x21ffffff: Reserved */
-#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
-                                         /* -0x3fffffff: Reserved */
-#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
-                                         /* -0x41ffffff: Peripherals */
-#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
-                                         /* -0xdfffffff: Reserved */
-#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
-#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
-#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
-                                         /* -0xe000dfff: Reserved */
-#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
-                                         /* -0xe003ffff: Reserved */
-#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
-                                         /* -0xffffffff: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
-                                         /* -0x1fffffff: Reserved */
-#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
-                                         /* -0x21ffffff: Reserved */
-#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
-                                         /* -0x3fffffff: Reserved */
-#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
-                                         /* -0x41ffffff: Peripherals */
-#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
-                                         /* -0x5fffffff: Reserved */
-#  define LM3S_EPI0RAM_BASE   0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */
-#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
-#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
-#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
-                                         /* -0xe000dfff: Reserved */
-#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
-                                         /* -0xe003ffff: Reserved */
-#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
-                                         /* -0xffffffff: Reserved */
-#else
-#  error "Memory map not specified for this LM3S chip"
-#endif
-
-/* Peripheral base addresses ********************************************************/
-/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt
- * peripheral modules.  They could probably be combined into one peripheral memory
- * map.  However, keeping them separate does also provide so early, compile-time
- * error detection that makes the duplication worthwhile.
- */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x3fffff: Reserved */
-#  define LM3S_CANCON_BASE    (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN Controller */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
-/* FiRM Peripheral Base Addresses */
-
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
-                                                           /* -0x1ffff: Reserved */
-/* Peripheral Base Addresses */
-
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
-
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC0_BASE       (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
-#  define LM3S_ADC1_BASE       (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-#  define LM3S_GPIOJ_BASE     (LM3S_PERIPH_BASE + 0x3d000)  /* -0x3dfff: GPIO Port J */
-                                                            /* -0x3ffff: Reserved */
-#  define LM3S_CAN0_BASE      (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN 0 */
-#  define LM3S_CAN1_BASE      (LM3S_PERIPH_BASE + 0x41000)  /* -0x41fff: CAN 1 */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0x49fff: Reserved */
-#  define LM3S_USB_BASE       (LM3S_PERIPH_BASE + 0x50000)  /* -0x50fff: USB */
-                                                            /* -0x53fff: Reserved */
-#  define LM3S_I2S0_BASE      (LM3S_PERIPH_BASE + 0x54000)  /* -0x54fff: I2S 0 */
-                                                            /* -0x57fff: Reserved */
-#  define LM3S_GPIOAAHB_BASE  (LM3S_PERIPH_BASE + 0x58000)  /* -0x58fff: GPIO Port A (AHB aperture) */
-#  define LM3S_GPIOBAHB_BASE  (LM3S_PERIPH_BASE + 0x59000)  /* -0x59fff: GPIO Port B (AHB aperture) */
-#  define LM3S_GPIOCAHB_BASE  (LM3S_PERIPH_BASE + 0x5A000)  /* -0x5afff: GPIO Port C (AHB aperture) */
-#  define LM3S_GPIODAHB_BASE  (LM3S_PERIPH_BASE + 0x5B000)  /* -0x5bfff: GPIO Port D (AHB aperture) */
-#  define LM3S_GPIOEAHB_BASE  (LM3S_PERIPH_BASE + 0x5C000)  /* -0x5cfff: GPIO Port E (AHB aperture) */
-#  define LM3S_GPIOFAHB_BASE  (LM3S_PERIPH_BASE + 0x5D000)  /* -0x5dfff: GPIO Port F (AHB aperture) */
-#  define LM3S_GPIOGAHB_BASE  (LM3S_PERIPH_BASE + 0x5E000)  /* -0x5efff: GPIO Port G (AHB aperture) */
-#  define LM3S_GPIOHAHB_BASE  (LM3S_PERIPH_BASE + 0x5F000)  /* -0x5ffff: GPIO Port H (AHB aperture) */
-#  define LM3S_GPIOJAHB_BASE  (LM3S_PERIPH_BASE + 0x60000)  /* -0x60fff: GPIO Port J (AHB aperture) */
-                                                            /* -0xcffff: Reserved */
-#  define LM3S_EPI0_BASE      (LM3S_PERIPH_BASE + 0xD0000)  /* -0xd0fff: EPI 0 */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-#  define LM3S_UDMA_BASE      (LM3S_PERIPH_BASE + 0xff000)  /* -0xfffff: System Control */
-                                                            /* -0x1ffffff: Reserved */
-#else
-#  error "Peripheral base addresses not specified for this LM3S chip"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h
deleted file mode 100644
index 62a4a03fd..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_pinmap.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* The following lists the input value to lm3s_configgpio to setup the alternate,
- * hardware function for each pin.
- */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTA | 6)     /* PA6: Capture/Compare/PWM1 (CCP1) */
-#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
-#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 0)     /* PB0: Capture/Compare/PWM0 (CCP0) */
-#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 1)     /* PB1: Capture/Compare/PWM2 (CCP2) */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
-#  define GPIO_TMR5_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 4)     /* PC4: Capture/Compare/PWM5 (CCP5) */
-#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
-#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
-#  define GPIO_TMR4_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 7)     /* PC7: Capture/Compare/PWM4 (CCP4) */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
-#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
-#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
-#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
-#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT  | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO     | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO     | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT  | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO   | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT  | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO     | GPIO_PORTC | 1) /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO     | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 2) /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
-#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT  | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
-#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */
-#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT  | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT  | GPIO_PORTD | 6) /* PD6: PWM Fault */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO     | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */
-#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
-#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
-#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
-#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
-#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
-#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
-#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
-#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
-#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
-#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
-#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
-#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
-#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
-#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
-#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
-#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
-#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
-#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
-#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
-#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
-#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
-#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
-#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFODIO | GPIO_PORTA | 6)   /* PA6: I2C1 clock (I2C1SCL) */
-#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
-#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
-#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFODIO  | GPIO_PORTB | 2)  /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1)  /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
-#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
-#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
-#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
-#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
-#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
-#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
-#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
-#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
-#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
-#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
-#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
-#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
-#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
-#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
-#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
-#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
-#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
-#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
-#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
-#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
-
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT   | GPIO_PORTA | 0)       /* PA0: UART 0 receive (U0Rx) */
-#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTA | 1)       /* PA1: UART 0 transmit (U0Tx) */
-#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO      | GPIO_PORTA | 2)       /* PA2: SSI0 clock (SSI0Clk) */
-#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO      | GPIO_PORTA | 3)       /* PA3: SSI0 frame (SSI0Fss) */
-#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT   | GPIO_PORTA | 4)       /* PA4: SSI0 receive (SSI0Rx) */
-#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTA | 5)       /* PA5: SSI0 transmit (SSI0Tx) */
-#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO      | GPIO_PORTA | 6)       /* PA6: Capture/Compare/PWM0 (CCP1) */
-#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 0)       /* PB0: PWM Generator 1, PWM2 */
-#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 1)       /* PB1: PWM Generator 1, PWM3 */
-#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 2)       /* PB2: I2C0 clock (I2C0SCL) */
-#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO    | GPIO_PORTB | 3)       /* PB3: I2C0 data (I2C0SDA) */
-#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 4)       /* PB4: Analog comparator 0 negative input (C0-) */
-#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTB | 5)       /* PB5: Analog comparator 0 output (C0o) (differs) */
-#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 6)       /* PB6: Analog comparator 0 positive input (C0+) */
-#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT   | GPIO_PORTB | 7)       /* PB7: JTAG ~TRST */
-#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 0)       /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 0)       /* PC0: JTAG/SWD CLK */
-#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO      | GPIO_PORTC | 1)       /* PC1: JTAG TMS */
-#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO      | GPIO_PORTC | 1)       /* PC1: JTAG SWDIO */
-#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 2)       /* PC2: JTAG TDI */
-#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTC | 3)       /* PC3: JTAG TDO */
-#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTC | 3)       /* PC3: JTAG SWO */
-#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 4)       /* PC4: QEI module 0 phase A. */
-#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT   | GPIO_PORTC | 6)       /* PC6: QEI module 0 phase B. */
-#  define GPIO_CAN0_RX     (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 0)       /* PD0: CAN module  RX */
-#  define GPIO_CAN0_TX     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTD | 1)       /* PD1: CAN module TX */
-#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 2)       /* PD2: UART 1 receive (U1Rx) */
-#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT  | GPIO_PORTD | 3)       /* PD3: UART 1 transmit (U1Tx) */
-#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO      | GPIO_PORTD | 4)       /* PD4: Capture/Compare/PWM0 (CCP0) */
-#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT   | GPIO_PORTD | 6)       /* PD6: PWM Fault */
-#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFIO      | GPIO_PORTD | 7)       /* PC7: QEI module 0 index */
-#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTE | 0)       /* PE0: PWM Generator 2, PWM4 */
-#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTE | 1)       /* PE1: PWM Generator 1, PWM5 */
-#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 2)       /* PE2: QEI module 1 phase B. */
-#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 3)       /* PE3: QEI module 1 phase A. */
-#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 0)       /* PF0: PWM Generator 0, PWM0 */
-#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT   | GPIO_PORTE | 1)       /* PF1: QEI module 1 index. ) */
-#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 2)       /* PF2: LED1 */
-#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 3)       /* PF3: LED0 */
-#  define GPIO_PWM0_1     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTG | 1)       /* PG1:PWM Generator 0, PWM1 */
-#else
-#  error "Unknown LM3S chip"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h
deleted file mode 100644
index b56ca77cb..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_ssi.h
- *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <sys/types.h>
-
-#if LM3S_NSSI > 0
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* SSI register offsets *************************************************************/
-
-#define LM3S_SSI_CR0_OFFSET       0x000 /* SSI Control 0 */
-#define LM3S_SSI_CR1_OFFSET       0x004 /* SSI Control 1 */
-#define LM3S_SSI_DR_OFFSET        0x008 /* SSI Data */
-#define LM3S_SSI_SR_OFFSET        0x00c /* SSI Status */
-#define LM3S_SSI_CPSR_OFFSET      0x010 /* SSI Clock Prescale */
-#define LM3S_SSI_IM_OFFSET        0x014 /* SSI Interrupt Mask */
-#define LM3S_SSI_RIS_OFFSET       0x018 /* SSI Raw Interrupt Status */
-#define LM3S_SSI_MIS_OFFSET       0x01c /* SSI Masked Interrupt Status */
-#define LM3S_SSI_ICR_OFFSET       0x020 /* SSI Interrupt Clear */
-#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
-#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
-#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
-#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
-#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
-#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
-#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
-#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
-#define LM3S_SSI_PCELLID0_OFFSET  0xff0 /* SSI PrimeCell Identification 0 */
-#define LM3S_SSI_PCELLID1_OFFSET  0xff4 /* SSI PrimeCell Identification 1 */
-#define LM3S_SSI_PCELLID2_OFFSET  0xff8 /* SSI PrimeCell Identification 2 */
-#define LM3S_SSI_PCELLID3_OFFSET  0xffc /* SSI PrimeCell Identification 3 */
-
-/* SSI register addresses ***********************************************************/
-
-#define LM3S_SSI0_CR0             (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI0_CR1             (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI0_DR              (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI0_SR              (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI0_CPSR            (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI0_IM              (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI0_RIS             (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI0_MIS             (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI0_ICR             (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI0_PERIPHID4       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI0_PERIPHID5       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI0_PERIPHID6       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI0_PERIPHID7       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI0_PERIPHID0       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI0_PERIPHID1       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI0_PERIPHID2       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI0_PERIPHID3       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI0_PCELLID0        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI0_PCELLID1        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI0_PCELLID2        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI0_PCELLID3        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
-
-#if LM3S_NSSI > 1
-#define LM3S_SSI1_CR0             (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI1_CR1             (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI1_DR              (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI1_SR              (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI1_CPSR            (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI1_IM              (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI1_RIS             (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI1_MIS             (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI1_ICR             (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI1_PERIPHID4       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI1_PERIPHID5       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI1_PERIPHID6       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI1_PERIPHID7       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI1_PERIPHID0       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI1_PERIPHID1       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI1_PERIPHID2       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI1_PERIPHID3       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI1_PCELLID0        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI1_PCELLID1        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI1_PCELLID2        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI1_PCELLID3        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
-
-#define LM3S_SSI_BASE(n)          (LM3S_SSI0_BASE + (n)*0x01000)
-
-#define LM3S_SSI_CR0(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI_CR1(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI_DR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI_SR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI_CPSR(n)          (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI_IM(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI_RIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI_MIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI_ICR(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI_PERIPHID4(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI_PERIPHID5(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI_PERIPHID6(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI_PERIPHID7(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI_PERIPHID0(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI_PERIPHID1(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI_PERIPHID2(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI_PERIPHID3(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI_PCELLID0(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI_PCELLID1(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI_PCELLID2(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI_PCELLID3(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
-#endif /* LM3S_NSSI > 1 */
-
-/* SSI register bit defitiions ******************************************************/
-
-/* SSI Control 0 (SSICR0), offset 0x000 */
-
-#define SSI_CR0_DSS_SHIFT         0         /* Bits 3-0: SSI Data Size Select */
-#define SSI_CR0_DSS_MASK          (0x0f << SSI_CR0_DSS_SHIFT)
-#define   SSI_CR0_DSS(n)          ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
-#define SSI_CR0_FRF_SHIFT         4         /* Bits 5-4: SSI Frame Format Select */
-#define SSI_CR0_FRF_MASK          (3 << SSI_CR0_FRF_SHIFT)
-#define   SSI_CR0_FRF_SPI         (0 << SSI_CR0_FRF_SHIFT)     /* Freescale SPI format */
-#define   SSI_CR0_FRF_SSFF        (1 << SSI_CR0_FRF_SHIFT)     /* TI synchronous serial fram format */
-#define   SSI_CR0_FRF_UWIRE       (2 << SSI_CR0_FRF_SHIFT)     /* MICROWIRE frame format */
-#define SSI_CR0_SPO               (1 << 6)  /* Bit 6:  SSI Serial Clock Polarity */
-#define SSI_CR0_SPH               (1 << 7)  /* Bit 7:  SSI Serial Clock Phase */
-#define SSI_CR0_SCR_SHIFT         8         /* Bits 15-8: SSI Serial Clock Rate */
-#define SSI_CR0_SCR_MASK          (0xff << SSI_CR0_SCR_SHIFT)
-
-/* SSI Control 1 (SSICR1), offset 0x004 */
-
-#define SSI_CR1_LBM               (1 << 0)  /* Bit 0:  SSI Loopback Mode */
-#define SSI_CR1_SSE               (1 << 1)  /* Bit 1:  SSI Synchronous Serial Port Enable */
-#define SSI_CR1_MS                (1 << 2)  /* Bit 2:  SSI Master/Slave Select slave */
-#define SSI_CR1_SOD               (1 << 3)  /* Bit 3:  SSI Slave Mode Output Disable */
-
-/* SSI Data (SSIDR), offset 0x008 */
-
-#define SSI_DR_MASK               0xffff    /* Bits 15-0: SSI data */
-
-/* SSI Status (SSISR), offset 0x00c */
-
-#define SSI_SR_TFE                (1 << 0)  /* Bit 0:  SSI Transmit FIFO Empty */
-#define SSI_SR_TNF                (1 << 1)  /* Bit 1:  SSI Transmit FIFO Not Full */
-#define SSI_SR_RNE                (1 << 2)  /* Bit 2:  SSI Receive FIFO Not Empty */
-#define SSI_SR_RFF                (1 << 3)  /* Bit 3:  SSI Receive FIFO Full */
-#define SSI_SR_BSY                (1 << 4)  /* Bit 4:  SSI Busy Bit */
-
-/* SSI Clock Prescale (SSICPSR), offset 0x010 */
-
-#define SSI_CPSR_DIV_MASK         0xff      /* Bits 7-0: SSI Clock Prescale Divisor */
-
-/* SSI Interrupt Mask (SSIIM), offset 0x014 */
-
-#define SSI_IM_ROR                (1 << 0)  /* Bit 0:  SSI Receive Overrun Interrupt Mask */
-#define SSI_IM_RT                 (1 << 1)  /* Bit 1:  SSI Receive Time-Out Interrupt Mask */
-#define SSI_IM_RX                 (1 << 2)  /* Bit 2:  SSI Receive FIFO Interrupt Mask */
-#define SSI_IM_TX                 (1 << 3)  /* Bit 3:  SSI Transmit FIFO Interrupt Mask */
-
-/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
-
-#define SSI_RIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Raw Interrupt Status */
-#define SSI_RIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Raw Interrupt Status */
-#define SSI_RIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Raw Interrupt Status */
-#define SSI_RIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Raw Interrupt Status */
-
-/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
-
-#define SSI_MIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Masked Interrupt Status */
-#define SSI_MIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Masked Interrupt Status */
-#define SSI_MIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Masked Interrupt Status */
-#define SSI_MIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Masked Interrupt Status */
-
-/* SSI Interrupt Clear (SSIICR), offset 0x020 */
-
-#define SSI_ICR_ROR               (1 << 0)  /* Bit 0: SSI Receive Overrun Interrupt Clear */
-#define SSI_ICR_RT                (1 << 1)  /* Bit 1: SSI Receive Time-Out Interrupt Clear */
-
-/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
-
-#define SSI_PERIPHID_MASK         0xff      /* Bits 7-0: SSI Peripheral ID n */
-
-/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
-
-#define SSI_PCELLID_MASK          0xff      /* Bits 7-0: SSI Prime cell ID */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* LM3S_NSSI > 0 */
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h
deleted file mode 100644
index d66cfeb47..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_syscontrol.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* System Control Register Offsets **************************************************/
-
-#define LM3S_SYSCON_DID0_OFFSET       0x000 /* Device Identification 0 */
-#define LM3S_SYSCON_DID1_OFFSET       0x004 /* Device Identification 1 */
-#define LM3S_SYSCON_DC0_OFFSET        0x008 /* Device Capabilities 0 */
-#define LM3S_SYSCON_DC1_OFFSET        0x010 /* Device Capabilities 1 */
-#define LM3S_SYSCON_DC2_OFFSET        0x014 /* Device Capabilities 2 */
-#define LM3S_SYSCON_DC3_OFFSET        0x018 /* Device Capabilities 3 */
-#define LM3S_SYSCON_DC4_OFFSET        0x01c /* Device Capabilities 4 */
-#define LM3S_SYSCON_PBORCTL_OFFSET    0x030 /* Brown-Out Reset Control */
-#define LM3S_SYSCON_LDOPCTL_OFFSET    0x034 /* LDO Power Control */
-#define LM3S_SYSCON_SRCR0_OFFSET      0x040 /* Software Reset Control 0 */
-#define LM3S_SYSCON_SRCR1_OFFSET      0x044 /* Software Reset Control 1 */
-#define LM3S_SYSCON_SRCR2_OFFSET      0x048 /* Software Reset Control 2*/
-#define LM3S_SYSCON_RIS_OFFSET        0x050 /* Raw Interrupt Status */
-#define LM3S_SYSCON_IMC_OFFSET        0x054 /* Interrupt Mask Control */
-#define LM3S_SYSCON_MISC_OFFSET       0x058 /* Masked Interrupt Status and Clear */
-#define LM3S_SYSCON_RESC_OFFSET       0x05c /* Reset Cause */
-#define LM3S_SYSCON_RCC_OFFSET        0x060 /* Run-Mode Clock Configuration */
-#define LM3S_SYSCON_PLLCFG_OFFSET     0x064 /* XTAL to PLL Translation */
-#define LM3S_SYSCON_RCC2_OFFSET       0x070 /* Run-Mode Clock Configuration 2 */
-#define LM3S_SYSCON_RCGC0_OFFSET      0x100 /* Run Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_RCGC1_OFFSET      0x104 /* Run Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_RCGC2_OFFSET      0x108 /* Run Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_SCGC0_OFFSET      0x110 /* Sleep Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_SCGC1_OFFSET      0x114 /* Sleep Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_SCGC2_OFFSET      0x118 /* Sleep Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_DCGC0_OFFSET      0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_DCGC1_OFFSET      0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_DCGC2_OFFSET      0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
-
-/* System Control Register Addresses ************************************************/
-
-#define LM3S_SYSCON_DID0              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
-#define LM3S_SYSCON_DID1              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
-#define LM3S_SYSCON_DC0               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
-#define LM3S_SYSCON_DC1               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
-#define LM3S_SYSCON_DC2               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
-#define LM3S_SYSCON_DC3               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
-#define LM3S_SYSCON_DC4               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
-#define LM3S_SYSCON_PBORCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
-#define LM3S_SYSCON_LDOPCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
-#define LM3S_SYSCON_SRCR0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
-#define LM3S_SYSCON_SRCR1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
-#define LM3S_SYSCON_SRCR2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
-#define LM3S_SYSCON_RIS               (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
-#define LM3S_SYSCON_IMC               (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
-#define LM3S_SYSCON_MISC              (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
-#define LM3S_SYSCON_RESC              (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
-#define LM3S_SYSCON_RCC               (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
-#define LM3S_SYSCON_PLLCFG            (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
-#define LM3S_SYSCON_RCC2              (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
-#define LM3S_SYSCON_RCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
-#define LM3S_SYSCON_RCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
-#define LM3S_SYSCON_RCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
-#define LM3S_SYSCON_SCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
-#define LM3S_SYSCON_SCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
-#define LM3S_SYSCON_SCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
-#define LM3S_SYSCON_DCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
-#define LM3S_SYSCON_DCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
-#define LM3S_SYSCON_DCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
-#define LM3S_SYSCON_DSLPCLKCFG        (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
-
-/* System Control Register Bit Definitions ******************************************/
-
-/* Device Identification 0 (DID0), offset 0x000 */
-
-#define SYSCON_DID0_MINOR_SHIFT       0         /* Bits 7-0: Minor Revision of the device */
-#define SYSCON_DID0_MINOR_MASK        (0xff << SYSCON_DID0_MINOR_SHIFT)
-#define SYSCON_DID0_MAJOR_SHIFT       8         /* Bits 15-8: Major Revision of the device */
-#define SYSCON_DID0_MAJOR_MASK        (0xff << SYSCON_DID0_MAJOR_SHIFT)
-#define SYSCON_DID0_CLASS_SHIFT       16        /* Bits 23-16: Device Class */
-#define SYSCON_DID0_CLASS_MASK        (0xff << SYSCON_DID0_CLASS_SHIFT)
-#define SYSCON_DID0_VER_SHIFT         28        /* Bits 30-28: DID0 Version */
-#define SYSCON_DID0_VER_MASK          (7 << SYSCON_DID0_VER_SHIFT)
-
-/* Device Identification 1 (DID1), offset 0x004 */
-
-#define SYSCON_DID1_QUAL_SHIFT        0         /* Bits 1-0: Qualification Status */
-#define SYSCON_DID1_QUAL_MASK         (0x03 << SYSCON_DID1_QUAL_SHIFT)
-#define SYSCON_DID1_ROHS              (1 << 2)  /* Bit 2: RoHS-Compliance */
-#define SYSCON_DID1_PKG_SHIFT         3 /* Bits 4-3: Package Type */
-#define SYSCON_DID1_PKG_MASK          (0x03 << SYSCON_DID1_PKG_SHIFT)
-#define SYSCON_DID1_TEMP_SHIFT        5         /* Bits 7-5: Temperature Range */
-#define SYSCON_DID1_TEMP_MASK         (0x07 << SYSCON_DID1_TEMP_SHIFT)
-#define SYSCON_DID1_PINCOUNT_SHIFT    13        /* Bits 15-13: Package Pin Count */
-#define SYSCON_DID1_PINCOUNT_MASK     (0x07 << SYSCON_DID1_PINCOUNT_SHIFT)
-#define SYSCON_DID1_PARTNO_SHIFT      16        /* Bits 23-16: Part Number */
-#define SYSCON_DID1_PARTNO_MASK       (0xff << SYSCON_DID1_PARTNO_SHIFT)
-#define SYSCON_DID1_FAM_SHIFT         24        /* Bits 27-24: Family */
-#define SYSCON_DID1_FAM_MASK          (0x0f << SYSCON_DID1_FAM_SHIFT)
-#define SYSCON_DID1_VER_SHIFT         28        /* Bits 31-28:  DID1 Version */
-#define SYSCON_DID1_VER_MASK          (0x0f << SYSCON_DID1_VER_SHIFT)
-
-/* Device Capabilities 0 (DC0), offset 0x008 */
-
-#define SYSCON_DC0_FLASHSZ_SHIFT      0         /* Bits 15-0: FLASH Size */
-#define SYSCON_DC0_FLASHSZ_MASK       (0xffff << SYSCON_DC0_FLASHSZ_SHIFT)
-#define SYSCON_DC0_SRAMSZ_SHIFT       16        /* Bits 31-16: SRAM Size */
-#define SYSCON_DC0_SRAMSZ_MASK        (0xffff << SYSCON_DC0_SRAMSZ_SHIFT)
-
-/* Device Capabilities 1 (DC1), offset 0x010 */
-
-#define SYSCON_DC1_JTAG               (1 << 0)  /* Bit 0: JTAG Present */
-#define SYSCON_DC1_SWD                (1 << 1)  /* Bit 1: SWD Present */
-#define SYSCON_DC1_SWO                (1 << 2)  /* Bit 2: SWO Trace Port Present */
-#define SYSCON_DC1_WDT                (1 << 3)  /* Bit 3: Watchdog Timer Present */
-#define SYSCON_DC1_PLL                (1 << 4)  /* Bit 4: PLL Present */
-#define SYSCON_DC1_TEMPSNS            (1 << 5)  /* Bit 5: Temp Sensor Present */
-#define SYSCON_DC1_HIB                (1 << 6)  /* Bit 6: Hibernation Module Present */
-#define SYSCON_DC1_MPU                (1 << 7)  /* Bit 7: MPU Present */
-#define SYSCON_DC1_MAXADCSPD_SHIFT    8         /* Bits 9-8: Max ADC Speed */
-#define SYSCON_DC1_MAXADCSPD_MASK     (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT)
-#define SYSCON_DC1_ADC                (1 << 16) /* Bit 16: ADC Module Present */
-#define SYSCON_DC1_MINSYSDIV_SHIFT    12        /* Bits 15-12: System Clock Divider Minimum */
-#define SYSCON_DC1_MINSYSDIV_MASK     (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT)
-
-/* Device Capabilities 2 (DC2), offset 0x014 */
-
-#define SYSCON_DC2_UART0              (1 << 0)  /* Bit 0: UART0 Present */
-#define SYSCON_DC2_UART1              (1 << 1)  /* Bit 1: UART1 Present */
-#define SYSCON_DC2_SSI0               (1 << 4)  /* Bit 4: SSI0 Present */
-#define SYSCON_DC2_SSI1               (1 << 5)  /* Bit 5: SSI1 Present */
-#define SYSCON_DC2_I2C0               (1 << 12) /* Bit 12: I2C Module 0 Present */
-#define SYSCON_DC2_I2C1               (1 << 14) /* Bit 14: I2C Module 1 Present */
-#define SYSCON_DC2_TIMER0             (1 << 16) /* Bit 16: Timer 0 Present */
-#define SYSCON_DC2_TIMER1             (1 << 17) /* Bit 17: Timer 1 Present */
-#define SYSCON_DC2_TIMER2             (1 << 18) /* Bit 18: Timer 2 Present */
-#define SYSCON_DC2_TIMER3             (1 << 19) /* Bit 19: Timer 3 Present */
-#define SYSCON_DC2_COMP0              (1 << 24) /* Bit 24: Analog Comparator 0 Present */
-#define SYSCON_DC2_COMP1              (1 << 25) /* Bit 25: Analog Comparator 1 Present */
-
-/* Device Capabilities 3 (DC3), offset 0x018 */
-
-#define SYSCON_DC3_C0MINUS            (1 << 6)  /* Bit 6: C0- Pin Present */
-#define SYSCON_DC3_C0PLUS             (1 << 7)  /* Bit 7: C0+ Pin Present */
-#define SYSCON_DC3_C0O                (1 << 8)  /* Bit 8: C0o Pin Present */
-#define SYSCON_DC3_C1MINUS            (1 << 9)  /* Bit 9: C1- Pin Present */
-#define SYSCON_DC3_C1PLUS             (1 << 10) /* Bit 10: C1+ Pin Present */
-#define SYSCON_DC3_ADC0               (1 << 16) /* Bit 16: ADC0 Pin Present */
-#define SYSCON_DC3_ADC1               (1 << 17) /* Bit 17: ADC1 Pin Present */
-#define SYSCON_DC3_ADC2               (1 << 18) /* Bit 18: ADC2 Pin Present */
-#define SYSCON_DC3_ADC3               (1 << 19) /* Bit 19: ADC3 Pin Present */
-#define SYSCON_DC3_ADC4               (1 << 20) /* Bit 20: ADC4 Pin Present */
-#define SYSCON_DC3_ADC5               (1 << 21) /* Bit 21: ADC5 Pin Present */
-#define SYSCON_DC3_ADC6               (1 << 22) /* Bit 22: ADC6 Pin Present */
-#define SYSCON_DC3_ADC7               (1 << 23) /* Bit 23: ADC7 Pin Present */
-#define SYSCON_DC3_CCP0               (1 << 24) /* Bit 24: CCP0 Pin Present */
-#define SYSCON_DC3_CCP1               (1 << 25) /* Bit 25: CCP1 Pin Present */
-#define SYSCON_DC3_CCP2               (1 << 26) /* Bit 26: CCP2 Pin Present */
-#define SYSCON_DC3_CCP3               (1 << 27) /* Bit 27: CCP3 Pin Present */
-#define SYSCON_DC3_CCP4               (1 << 28) /* Bit 28: CCP4 Pin Present */
-#define SYSCON_DC3_CCP5               (1 << 29) /* Bit 29: CCP5 Pin Present */
-#define SYSCON_DC3_32KHZ              (1 << 31) /* Bit 31: 32KHz Input Clock Available */
-
-/* Device Capabilities 4 (DC4), offset 0x01c */
-
-#define SYSCON_DC4_GPIO(n)            (1 << (n))
-#define SYSCON_DC4_GPIOA              (1 << 0)  /* Bit 0: GPIO Port A Present */
-#define SYSCON_DC4_GPIOB              (1 << 1)  /* Bit 1: GPIO Port B Present */
-#define SYSCON_DC4_GPIOC              (1 << 2)  /* Bit 2: GPIO Port C Present */
-#define SYSCON_DC4_GPIOD              (1 << 3)  /* Bit 3: GPIO Port D Present */
-#define SYSCON_DC4_GPIOE              (1 << 4)  /* Bit 4: GPIO Port E Present */
-#define SYSCON_DC4_GPIOF              (1 << 5)  /* Bit 5: GPIO Port F Present */
-#define SYSCON_DC4_GPIOG              (1 << 6)  /* Bit 6: GPIO Port G Present */
-#define SYSCON_DC4_GPIOH              (1 << 7)  /* Bit 7: GPIO Port H Present */
-#define SYSCON_DC4_EMAC0              (1 << 28) /* Bit 28: Ethernet MAC0 Present */
-#define SYSCON_DC4_EPHY0              (1 << 30) /* Bit 30: Ethernet PHY0 Present */
-
-/* Brown-Out Reset Control (PBORCTL), offset 0x030 */
-
-#define SYSCON_PBORCTL_BORIOR         (1 << 1)  /* Bit 1: BOR Interrupt or Reset */
-
-/* LDO Power Control (LDOPCTL), offset 0x034 */
-
-#define SYSCON_LDOPCTL_VADJ_SHIFT     0         /* Bits 5-0: LDO Output Voltage */
-#define SYSCON_LDOPCTL_VADJ_MASK      (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT)
-#  define SYSCON_LPDOPCTL_2500MV      (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/
-#  define SYSCON_LPDOPCTL_2450MV      (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */
-#  define SYSCON_LPDOPCTL_2400MV      (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */
-#  define SYSCON_LPDOPCTL_2350MV      (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */
-#  define SYSCON_LPDOPCTL_2300MV      (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */
-#  define SYSCON_LPDOPCTL_2250MV      (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */
-#  define SYSCON_LPDOPCTL_2750MV      (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */
-#  define SYSCON_LPDOPCTL_2700MV      (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */
-#  define SYSCON_LPDOPCTL_2650MV      (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */
-#  define SYSCON_LPDOPCTL_2600MV      (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */
-#  define SYSCON_LPDOPCTL_2550MV      (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */
-
-/* Software Reset Control 0 (SRCR0), offset 0x040 */
-
-#define SYSCON_SRCR0_WDT              (1 << 3)  /* Bit 3: WDT Reset Control */
-#define SYSCON_SRCR0_HIB              (1 << 6)  /* Bit 6: HIB Reset Control */
-#define SYSCON_SRCR0_ADC              (1 << 16) /* Bit 16: ADC0 Reset Control */
-
-/* Software Reset Control 1 (SRCR1), offset 0x044 */
-
-#define SYSCON_SRCR1_UART0            (1 << 0)  /* Bit 0: UART0 Reset Control */
-#define SYSCON_SRCR1_UART1            (1 << 1)  /* Bit 1: UART1 Reset Control */
-#define SYSCON_SRCR1_SSI0             (1 << 4)  /* Bit 4: SSI0 Reset Control1 */
-#define SYSCON_SRCR1_SSI1             (1 << 5)  /* Bit 5: SSI1 Reset Control */
-#define SYSCON_SRCR1_I2C0             (1 << 12) /* Bit 12: I2C0 Reset Control */
-#define SYSCON_SRCR1_I2C1             (1 << 14) /* Bit 14: I2C1 Reset Control */
-#define SYSCON_SRCR1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Reset Control */
-#define SYSCON_SRCR1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Reset Control */
-#define SYSCON_SRCR1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Reset Control */
-#define SYSCON_SRCR1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Reset Control */
-#define SYSCON_SRCR1_COMP0            (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */
-#define SYSCON_SRCR1_COMP1            (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */
-
-/* Software Reset Control 2 (SRCR2), offset 0x048 */
-
-#define SYSCON_SRCR2_GPIO(n)          (1 << (n))
-#define SYSCON_SRCR2_GPIOA            (1 << 0)  /* Bit 0: Port A Reset Control */
-#define SYSCON_SRCR2_GPIOB            (1 << 1)  /* Bit 1: Port B Reset Control */
-#define SYSCON_SRCR2_GPIOC            (1 << 2)  /* Bit 2: Port C Reset Control */
-#define SYSCON_SRCR2_GPIOD            (1 << 3)  /* Bit 3: Port D Reset Control */
-#define SYSCON_SRCR2_GPIOE            (1 << 4)  /* Bit 4: Port E Reset Control */
-#define SYSCON_SRCR2_GPIOF            (1 << 5)  /* Bit 5: Port F Reset Control */
-#define SYSCON_SRCR2_GPIOG            (1 << 6)  /* Bit 6: Port G Reset Control */
-#define SYSCON_SRCR2_GPIOH            (1 << 7)  /* Bit 7: Port H Reset Control */
-#define SYSCON_SRCR2_EMAC0            (1 << 28) /* Bit 28: MAC0 Reset Control */
-#define SYSCON_SRCR2_EPHY0            (1 << 30) /* Bit 30: PHY0 Reset Control */
-
-/* Raw Interrupt Status (RIS), offset 0x050 */
-
-#define SYSCON_RIS_BORRIS             (1 << 1)  /* Bit 1: Brown-Out Reset Raw Interrupt Status */
-#define SYSCON_RIS_PLLLRIS            (1 << 6)  /* Bit 6: PLL Lock Raw Interrupt Status */
-
-/* Interrupt Mask Control (IMC), offset 0x054 */
-
-#define SYSCON_IMC_BORIM              (1 << 1)  /* Bit 1: Brown-Out Reset Interrupt Mask */
-#define SYSCON_IMC_PLLLIM             (1 << 6)  /* Bit 6: PLL Lock Interrupt Mask */
-
-/* Masked Interrupt Status and Clear (MISC), offset 0x058 */
-
-#define SYSCON_MISC_BORMIS            (1 << 1)  /* Bit 1: BOR Masked Interrupt Status */
-#define SYSCON_MISC_PLLLMIS           (1 << 6)  /* Bit 6: PLL Lock Masked Interrupt Status */
-
-/* Reset Cause (RESC), offset 0x05C */
-
-#define SYSCON_RESC_EXT               (1 << 0)  /* Bit 0: External Reset */
-#define SYSCON_RESC_POR               (1 << 1)  /* Bit 1: Power-On Reset */
-#define SYSCON_RESC_BOR               (1 << 2)  /* Bit 2: Brown-Out Reset */
-#define SYSCON_RESC_WDT               (1 << 3)  /* Bit 3: Watchdog Timer Reset */
-#define SYSCON_RESC_SW                (1 << 4)  /* Bit 4: Software Reset */
-
-/* Run-Mode Clock Configuration (RCC), offset 0x060 */
-
-#define SYSCON_RCC_MOSCDIS            (1 << 0)  /* Bit 0: Main Oscillator Disable */
-#define SYSCON_RCC_IOSCDIS            (1 << 1)  /* Bit 1: Internal Oscillator Disable */
-#define SYSCON_RCC_OSCSRC_SHIFT       4         /* Bits 5-4: Oscillator Source */
-#define SYSCON_RCC_OSCSRC_MASK        (0x03 << SYSCON_RCC_OSCSRC_SHIFT)
-#  define SYSCON_RCC_OSCSRC_MOSC      (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */
-#  define SYSCON_RCC_OSCSRC_IOSC      (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */
-#  define SYSCON_RCC_OSCSRC_IOSC4     (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */
-#  define SYSCON_RCC_OSCSRC_30KHZ     (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */
-#define SYSCON_RCC_XTAL_SHIFT         6         /* Bits 10-6: Crystal Value */
-#define SYSCON_RCC_XTAL_MASK          (0x1f << SYSCON_RCC_XTAL_SHIFT)
-#  define SYSCON_RCC_XTAL1000KHZ      ( 0 << SYSCON_RCC_XTAL_SHIFT)  /* 1.0000MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL1843KHZ      ( 1 << SYSCON_RCC_XTAL_SHIFT)  /* 1.8432MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL2000KHZ      ( 2 << SYSCON_RCC_XTAL_SHIFT)  /* 2.0000MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL2580KHZ      ( 3 << SYSCON_RCC_XTAL_SHIFT)  /* 2.4576MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL3580KHZ      ( 4 << SYSCON_RCC_XTAL_SHIFT)  /* 3.5795MHz */
-#  define SYSCON_RCC_XTAL3686KHZ      ( 5 << SYSCON_RCC_XTAL_SHIFT)  /* 3.6864MHz */
-#  define SYSCON_RCC_XTAL4000KHZ      ( 6 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0000MHz */
-#  define SYSCON_RCC_XTAL4096KHZ      ( 7 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0960MHz */
-#  define SYSCON_RCC_XTAL4915KHZ      ( 8 << SYSCON_RCC_XTAL_SHIFT)  /* 4.9152MHz */
-#  define SYSCON_RCC_XTAL5000KHZ      ( 9 << SYSCON_RCC_XTAL_SHIFT)  /* 5.0000MHz */
-#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT)  /* 5.1200MHz */
-#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT)  /* 6.0000MHz (reset value) */
-#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT)  /* 6.1440MHz */
-#  define SYSCON_RCC_XTAL7373KHZ      (13 << SYSCON_RCC_XTAL_SHIFT)  /* 7.3728MHz */
-#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT)  /* 8.0000MHz */
-#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT)  /* 8.1920MHz */
-#ifdef CONFIG_ARCH_CHIP_LM3S9B96
-#  define SYSCON_RCC_XTAL10000KHZ     (16 << SYSCON_RCC_XTAL_SHIFT)  /* 10.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL12000KHZ     (17 << SYSCON_RCC_XTAL_SHIFT)  /* 12.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL12888KHZ     (18 << SYSCON_RCC_XTAL_SHIFT)  /* 12.288 MHz */
-#  define SYSCON_RCC_XTAL13560KHZ     (19 << SYSCON_RCC_XTAL_SHIFT)  /* 13.56 MHz */
-#  define SYSCON_RCC_XTAL14318KHZ     (20 << SYSCON_RCC_XTAL_SHIFT)  /* 14.31818 MHz */
-#  define SYSCON_RCC_XTAL16000KHZ     (21 << SYSCON_RCC_XTAL_SHIFT)  /* 16.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL16384KHZ     (22 << SYSCON_RCC_XTAL_SHIFT)  /* 16.384 MHz */
-#endif
-#define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
-#define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
-#define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */
-#define SYSCON_RCC_SYSDIV_SHIFT       23        /* Bits 26-23: System Clock Divisor */
-#define SYSCON_RCC_SYSDIV_MASK        (0x0f << SYSCON_RCC_SYSDIV_SHIFT)
-#  define SYSCON_RCC_SYSDIV(n)        (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT)
-#define SYSCON_RCC_ACG                (1 << 27) /* Bit 27: Auto Clock Gating */
-
-/* XTAL to PLL Translation (PLLCFG), offset 0x064 */
-
-#define SYSCON_PLLCFG_F_SHIFT         5         /* Bits 13-5: PLL F Value */
-#define SYSCON_PLLCFG_F_MASK          (0x1ff << SYSCON_PLLCFG_F_SHIFT)
-#define SYSCON_PLLCFG_R_SHIFT         0         /* Bits 4-0: PLL R Value  */
-#define SYSCON_PLLCFG_R_MASK          (0x1f << SYSCON_PLLCFG_R_SHIFT)
-
-/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */
-
-#define SYSCON_RCC2_OSCSRC2_SHIFT     4         /* Bits 6-4: Oscillator Source */
-#define SYSCON_RCC2_OSCSRC2_MASK      (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT)
-#  define SYSCON_RCC2_OSCSRC2_MOSC    (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */
-#  define SYSCON_RCC2_OSCSRC2_IOSC    (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */
-#  define SYSCON_RCC2_OSCSRC2_IOSC4   (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */
-#  define SYSCON_RCC2_OSCSRC2_30KHZ   (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */
-#  define SYSCON_RCC2_OSCSRC2_32KHZ   (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */
-#define SYSCON_RCC2_BYPASS2           (1 << 11) /* Bit 11: Bypass PLL */
-#define SYSCON_RCC2_PWRDN2            (1 << 13) /* Bit 13: Power-Down PLL */
-#define SYSCON_RCC2_SYSDIV2_SHIFT     23        /* Bits 28-23: System Clock Divisor */
-#define SYSCON_RCC2_SYSDIV2_MASK      (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT)
-#  define SYSCON_RCC2_SYSDIV(n)       ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT)
-#define SYSCON_RCC2_USERCC2           (1 << 31) /* Bit 31: Use RCC2 When set */
-
-/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */
-
-#define SYSCON_RCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_RCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_RCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_RCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_RCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */
-
-#define SYSCON_RCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_RCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_RCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_RCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_RCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_RCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_RCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_RCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */
-
-#define SYSCON_RCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_RCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_RCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_RCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_RCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_RCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_RCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_RCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_RCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_RCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_RCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */
-
-#define SYSCON_SCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_SCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_SCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_SCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_SCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */
-
-#define SYSCON_SCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_SCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_SCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_SCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_SCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_SCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_SCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_SCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */
-
-#define SYSCON_SCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_SCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_SCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_SCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_SCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_SCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_SCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_SCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_SCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_SCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_SCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */
-
-#define SYSCON_DCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_DCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_DCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_DCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_DCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */
-
-#define SYSCON_DCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_DCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_DCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_DCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_DCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_DCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_DCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_DCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */
-
-#define SYSCON_DCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_DCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_DCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_DCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_DCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_DCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_DCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_DCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_DCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_DCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_DCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */
-
-#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */
-#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK  (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT)
-#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT   4 /* Bits 6-4: Clock Source */
-#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK    (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h
deleted file mode 100644
index 649737f13..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_timer.h
- *
- *   Copyright (C) 2012 Max Nekludov. All rights reserved.
- *   Author: Max Nekludov <macscomp@gmail.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Timer register offsets ***********************************************************/
-
-#define TIMER_GPTMCFG_OFFSET             0x000
-#define TIMER_GPTMTAMR_OFFSET            0x004
-#define TIMER_GPTMCTL_OFFSET             0x00C
-#define TIMER_GPTMIMR_OFFSET             0x018
-#define TIMER_GPTMRIS_OFFSET             0x01C
-#define TIMER_GPTMICR_OFFSET             0x024
-#define TIMER_GPTMTAILR_OFFSET           0x028
-#define TIMER_GPTMTAR_OFFSET             0x048
-
-/* SSI register addresses ***********************************************************/
-
-#define LM3S_TIMER_BASE(n)               (LM3S_TIMER0_BASE + (n)*0x01000)
-
-#define LM3S_TIMER_GPTMCFG(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
-#define LM3S_TIMER_GPTMTAMR(n)           (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
-#define LM3S_TIMER_GPTMCTL(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
-#define LM3S_TIMER_GPTMIMR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
-#define LM3S_TIMER_GPTMRIS(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
-#define LM3S_TIMER_GPTMICR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
-#define LM3S_TIMER_GPTMTAILR(n)          (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
-#define LM3S_TIMER_GPTMTAR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
-
-/* SSI register bit defitiions ******************************************************/
-
-/* GPTM Configuration (GPTMCFG), offset 0x000 */
-
-#define TIMER_GPTMCFG_CFG_SHIFT          0    /* Bits 2-0: GPTM Configuration */
-#define TIMER_GPTM_CFG_MASK              (0x07 << TIMER_GPTMCFG_CFG_SHIFT)
-#define   TIMER_GPTMCFG_CFG_32           (0 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit timer configuration */
-#define   TIMER_GPTMCFG_CFG_RTC          (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit real-time clock (RTC) counter configuration */
-#define   TIMER_GPTMCFG_CFG_16           (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 16-bit timer configuration */
-
-/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */
-
-#define TIMER_GPTMTAMR_TAMR_SHIFT        0    /* Bits 1-0: GPTM Timer A Mode */
-#define TIMER_GPTMTAMR_TAMR_MASK         (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT)
-#define   TIMER_GPTMTAMR_TAMR_ONESHOT    (1 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* One-Shot Timer mode */
-#define   TIMER_GPTMTAMR_TAMR_PERIODIC   (2 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Periodic Timer mode */
-#define   TIMER_GPTMTAMR_TAMR_CAPTURE    (3 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Capture mode */
-#define TIMER_GPTMTAMR_TACMR_SHIFT       2    /* Bits 2:   GPTM Timer A Capture Mode */
-#define TIMER_GPTMTAMR_TACMR_MASK        (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT)
-#define   TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Count mode */
-#define   TIMER_GPTMTAMR_TACMR_EDGETIME  (1 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Time mode */
-#define TIMER_GPTMTAMR_TAAMS_SHIFT       3    /* Bits 3:   GPTM Timer A Alternate Mode Select */
-#define TIMER_GPTMTAMR_TAAMS_MASK        (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT)
-#define   TIMER_GPTMTAMR_TAAMS_CAPTURE   (0 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* Capture mode is enabled */
-#define   TIMER_GPTMTAMR_TAAMS_PWM       (1 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* PWM mode is enabled */
-#define TIMER_GPTMTAMR_TACDIR_SHIFT      4    /* Bits 4:   GPTM Timer A Count Direction */
-#define TIMER_GPTMTAMR_TACDIR_MASK       (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT)
-#define   TIMER_GPTMTAMR_TACDIR_DOWN     (0 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* The timer counts down */
-#define   TIMER_GPTMTAMR_TACDIR_UP       (1 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* When in one-shot or periodic mode, the timer counts up */
-#define TIMER_GPTMTAMR_TAMIE_SHIFT       5    /* Bits 5:   GPTM Timer A Match Interrupt Enable */
-#define TIMER_GPTMTAMR_TAMIE_MASK        (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT)
-
-/* GPTM Control (GPTMCTL), offset 0x00C */
-
-#define TIMER_GPTMCTL_TAEN_SHIFT         0    /* Bits 0:   GPTM Timer A Enable */
-#define TIMER_GPTMCTL_TAEN_MASK          (0x01 << TIMER_GPTMCTL_TAEN_SHIFT)
-#define TIMER_GPTMCTL_TASTALL_SHIFT      1    /* Bits 1:   GPTM Timer A Stall Enable */
-#define TIMER_GPTMCTL_TASTALL_MASK       (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT)
-
-/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */
-
-#define TIMER_GPTMIMR_TATOIM_SHIFT       0    /* Bits 0:   GPTM Timer A Time-Out Interrupt Mask */
-#define TIMER_GPTMIMR_TATOIM_MASK        (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT)
-
-/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */
-
-#define TIMER_GPTMRIS_TATORIS_SHIFT      0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt */
-#define TIMER_GPTMRIS_TATORIS_MASK       (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT)
-
-/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */
-
-#define TIMER_GPTMICR_TATOCINT_SHIFT     0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt Clear*/
-#define TIMER_GPTMICR_TATOCINT_MASK      (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h
deleted file mode 100644
index 0fef5ccf7..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm3s_uart.h
- *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* UART register offsets ************************************************************/
-
-#define LM3S_UART_DR_OFFSET        0x000 /* UART Data */
-#define LM3S_UART_RSR_OFFSET       0x004 /* UART Receive Status */
-#define LM3S_UART_ECR_OFFSET       0x004 /* UART Error Clear */
-#define LM3S_UART_FR_OFFSET        0x018 /* UART Flag */
-#define LM3S_UART_ILPR_OFFSET      0x020 /* UART IrDA Low-Power Register */
-#define LM3S_UART_IBRD_OFFSET      0x024 /* UART Integer Baud-Rate Divisor*/
-#define LM3S_UART_FBRD_OFFSET      0x028 /* UART Fractional Baud-Rate Divisor */
-#define LM3S_UART_LCRH_OFFSET      0x02c /* UART Line Control */
-#define LM3S_UART_CTL_OFFSET       0x030 /* UART Control */
-#define LM3S_UART_IFLS_OFFSET      0x034 /* UART Interrupt FIFO Level Select */
-#define LM3S_UART_IM_OFFSET        0x038 /* UART Interrupt Mask */
-#define LM3S_UART_RIS_OFFSET       0x03c /* UART Raw Interrupt Status */
-#define LM3S_UART_MIS_OFFSET       0x040 /* UART Masked Interrupt Status */
-#define LM3S_UART_ICR_OFFSET       0x044 /* UART Interrupt Clear */
-#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
-#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
-#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
-#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
-#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
-#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
-#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
-#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
-#define LM3S_UART_PCELLID0_OFFSET  0xff0 /* UART PrimeCell Identification 0 */
-#define LM3S_UART_PCELLID1_OFFSET  0xff4 /* UART PrimeCell Identification 1 */
-#define LM3S_UART_PCELLID2_OFFSET  0xff8 /* UART PrimeCell Identification 2 */
-#define LM3S_UART_PCELLID3_OFFSET  0xffc /* UART PrimeCell Identification 3 */
-
-/* UART register addresses **********************************************************/
-
-#define LM3S_UART_BASE(n)          (LM3S_UART0_BASE + (n)*0x01000)
-
-#define LM3S_UART_DR(n)            (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
-#define LM3S_UART_RSR(n)           (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART_ECR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART_FR(n)            (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
-#define LM3S_UART_ILPR(n)          (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART_IBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART_FBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART_LCRH(n)          (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART_CTL(n)           (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART_IFLS(n)          (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART_IM(n)            (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
-#define LM3S_UART_RIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART_MIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART_ICR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART_PERIPHID4(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART_PERIPHID5(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART_PERIPHID6(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART_PERIPHID7(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART_PERIPHID0(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART_PERIPHID1(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART_PERIPHID2(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART_PERIPHID3(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART_PCELLID0(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART_PCELLID1(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART_PCELLID2(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART_PCELLID3(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
-
-#define LM3S_UART0_DR              (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
-#define LM3S_UART0_RSR             (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART0_ECR             (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART0_FR              (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
-#define LM3S_UART0_ILPR            (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART0_IBRD            (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART0_FBRD            (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART0_LCRH            (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART0_CTL             (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART0_IFLS            (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART0_IM              (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
-#define LM3S_UART0_RIS             (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART0_MIS             (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART0_ICR             (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART0_PERIPHID4       (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART0_PERIPHID5       (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART0_PERIPHID6       (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART0_PERIPHID7       (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART0_PERIPHID0       (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART0_PERIPHID1       (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART0_PERIPHID2       (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART0_PERIPHID3       (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART0_PCELLID0        (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART0_PCELLID1        (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART0_PCELLID2        (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART0_PCELLID3        (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
-
-#define LM3S_UART1_DR              (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
-#define LM3S_UART1_RSR             (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART1_ECR             (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART1_FR              (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
-#define LM3S_UART1_ILPR            (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART1_IBRD            (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART1_FBRD            (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART1_LCRH            (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART1_CTL             (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART1_IFLS            (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART1_IM              (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
-#define LM3S_UART1_RIS             (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART1_MIS             (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART1_ICR             (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART1_PERIPHID4       (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART1_PERIPHID5       (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART1_PERIPHID6       (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART1_PERIPHID7       (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART1_PERIPHID0       (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART1_PERIPHID1       (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART1_PERIPHID2       (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART1_PERIPHID3       (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART1_PCELLID0        (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART1_PCELLID1        (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART1_PCELLID2        (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART1_PCELLID3        (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
-
-/* UART register bit settings *******************************************************/
-
-/* UART Data (DR), offset 0x000 */
-
-#define UART_DR_DATA_SHIFT         0         /* Bits 7-0: Data Transmitted or Received */
-#define UART_DR_DATA_MASK          (0xff << UART_DR_DATA_SHIFT)
-#define UART_DR_FE                 (1 << 8)  /* Bit 8:  UART Framing Error */
-#define UART_DR_PE                 (1 << 9)  /* Bit 9:  UART Parity Error */
-#define UART_DR_BE                 (1 << 10) /* Bit 10: UART Break Error */
-#define UART_DR_OE                 (1 << 11) /* Bit 11: UART Overrun Error */
-
-/* UART Receive Status (RSR), offset 0x004 */
-
-#define UART_RSR_FE                (1 << 0)  /* Bit 0:  UART Framing Error */
-#define UART_RSR_PE                (1 << 1)  /* Bit 1:  UART Parity Error */
-#define UART_RSR_BE                (1 << 2)  /* Bit 2:  UART Break Error */
-#define UART_RSR_OE                (1 << 3)  /* Bit 3:  UART Overrun Error */
-
-/* UART Error Clear (ECR), offset 0x004 */
-/* Writing any value to this register clears pending error indications */
-
-/* UART Flag (FR), offset 0x018 */
-
-#define UART_FR_BUSY               (1 << 3)  /* Bit 3:  UART Busy */
-#define UART_FR_RXFE               (1 << 4)  /* Bit 4:  UART Receive FIFO Empty */
-#define UART_FR_TXFF               (1 << 5)  /* Bit 5:  UART Transmit FIFO Full */
-#define UART_FR_RXFF               (1 << 6)  /* Bit 6:  UART Receive FIFO Full */
-#define UART_FR_TXFE               (1 << 7)  /* Bit 7:  UART Transmit FIFO Empty */
-
-/* UART IrDA Low-Power Register (ILPR), offset 0x020 */
-
-#define UART_ILPR_DVSR_MASK        (0xff)    /* Bits 7-0: IrDA Low-Power Divisor */
-
-/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */
-
-#define UART_IBRD_DIVINT_MASK      (0xffff)  /* Bits 15-0: Integer Baud-Rate Divisor */
-
-/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */
-
-#define UART_FBRD_DIVFRAC_MASK     (0x3f)    /* Bits 5-0: Fractional Baud-Rate Divisor */
-
-/* Register 7: UART Line Control (LCRH), offset 0x02C */
-
-#define UART_LCRH_BRK              (1 << 0)  /* Bit 0:  UART Send Break */
-#define UART_LCRH_PEN              (1 << 1)  /* Bit 1:  UART Parity Enable */
-#define UART_LCRH_EPS              (1 << 2)  /* Bit 2:  UART Even Parity Select */
-#define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
-#define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
-#define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
-#define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
-#  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
-#  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
-#  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
-#  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
-#define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
-
-/* UART Control (CTL), offset 0x030 */
-
-#define UART_CTL_UARTEN            (1 << 0)  /* Bit 0:  UART Enable */
-#define UART_CTL_SIREN             (1 << 1)  /* Bit 1:  UART SIR Enable */
-#define UART_CTL_SIRLP             (1 << 2)  /* Bit 2:  UART SIR Low Power Mode */
-#define UART_CTL_LBE               (1 << 7)  /* Bit 7:  UART Loop Back Enable */
-#define UART_CTL_TXE               (1 << 8)  /* Bit 8:  UART Transmit Enable */
-#define UART_CTL_RXE               (1 << 9)  /* Bit 9:  UART Receive Enable */
-
-/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */
-
-#define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */
-#define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
-#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
-#define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 5-3: UART Receive Interrupt FIFO Level Select */
-#define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
-#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
-
-/* UART Interrupt Mask (IM), offset 0x038 */
-
-#define UART_IM_RXIM               (1 << 4)  /* Bit 4:  UART Receive Interrupt Mask */
-#define UART_IM_TXIM               (1 << 5)  /* Bit 5:  UART Transmit Interrupt Mask */
-#define UART_IM_RTIM               (1 << 6)  /* Bit 6:  UART Receive Time-Out Interrupt Mask */
-#define UART_IM_FEIM               (1 << 7)  /* Bit 7:  UART Framing Error Interrupt Mask */
-#define UART_IM_PEIM               (1 << 8)  /* Bit 8:  UART Parity Error Interrupt Mask */
-#define UART_IM_BEIM               (1 << 9)  /* Bit 9:  UART Break Error Interrupt Mask */
-#define UART_IM_OEIM               (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */
-
-
-/* UART Raw Interrupt Status (RIS), offset 0x03c */
-
-#define UART_RIS_RXRIS             (1 << 4)  /* Bit 4:  UART Receive Raw Interrupt Status */
-#define UART_RIS_TXRIS             (1 << 5)  /* Bit 5:  UART Transmit Raw Interrupt Status */
-#define UART_RIS_RTRIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Raw Interrupt Status */
-#define UART_RIS_FERIS             (1 << 7)  /* Bit 7:  UART Framing Error Raw Interrupt Status */
-#define UART_RIS_PERIS             (1 << 8)  /* Bit 8:  UART Parity Error Raw Interrupt Status */
-#define UART_RIS_BERIS             (1 << 9)  /* Bit 9:  UART Break Error Raw Interrupt Status */
-#define UART_RIS_OERIS             (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */
-
-/* UART Masked Interrupt Status (MIS), offset 0x040 */
-
-#define UART_MIS_RXMIS             (1 << 4)  /* Bit 4:  UART Receive Masked Interrupt Status */
-#define UART_MIS_TXMIS             (1 << 5)  /* Bit 5:  UART Transmit Masked Interrupt Status */
-#define UART_MIS_RTMIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Masked Interrupt Status */
-#define UART_MIS_FEMIS             (1 << 7)  /* Bit 7:  UART Framing Error Masked Interrupt Status */
-#define UART_MIS_PEMIS             (1 << 8)  /* Bit 8:  UART Parity Error Masked Interrupt Status */
-#define UART_MIS_BEMIS             (1 << 9)  /* Bit 9:  UART Break Error Masked Interrupt Status */
-#define UART_MIS_OEMIS             (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */
-
-/* UART Interrupt Clear (ICR), offset 0x044 */
-
-#define UART_ICR_RXIC             (1 << 4)  /* Bit 4:  Receive Interrupt Clear */
-#define UART_ICR_TXIC             (1 << 5)  /* Bit 5:  Transmit Interrupt Clear */
-#define UART_ICR_RTIC             (1 << 6)  /* Bit 6:  Receive Time-Out Interrupt Clear */
-#define UART_ICR_FEIC             (1 << 7)  /* Bit 7:  Framing Error Interrupt Clear */
-#define UART_ICR_PEIC             (1 << 8)  /* Bit 8:  Parity Error Interrupt Clear */
-#define UART_ICR_BEIC             (1 << 9)  /* Bit 9:  Break Error Interrupt Clear */
-#define UART_ICR_OEIC             (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
- */
-
-/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
-
-#define UART_PERIPHID4_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
-
-/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
-
-#define UART_PERIPHID5_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
-
-/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
-
-#define UART_PERIPHID6_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
-
-/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
-
-#define UART_PERIPHID7_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
-
-/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
-
-#define UART_PERIPHID0_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
-
-/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
-
-#define UART_PERIPHID1_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
-
-/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
-
-#define UART_PERIPHID2_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
-
-/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
-
-#define UART_PERIPHID3_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
-
-/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
-
-#define UART_CELLID0_MASK         (0xff)    /* UART PrimeCell ID Register[7:0] */
-
-/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
-
-#define UART_CELLID1_MASK         (0xff)    /* UART PrimeCell ID Register[15:8] */
-
-/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
-
-#define UART_CELLID02MASK         (0xff)    /* UART PrimeCell ID Register[23:16] */
-
-/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
-
-#define UART_CELLID3_MASK         (0xff)    /* UART PrimeCell ID Register[31:24] */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h
deleted file mode 100644
index c52857847..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm_memorymap.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/* Include the memory map file for the specific Stellaris chip */
-
-#ifdef CONFIG_ARCH_CHIP_LM3S
-#  include "chip/lm3s_memorymap.h"
-#else
-#  error "Unsupported Stellaris memory map"
-#endif
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h
deleted file mode 100644
index b00a6e794..000000000
--- a/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/chip/lm_pinmap.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H
-#define __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/* Include the memory map file for the specific Stellaris chip */
-
-#ifdef CONFIG_ARCH_CHIP_LM3S
-#  include "chip/lm3s_pinmap.h"
-#else
-#  error "Unsupported Stellaris PIN mapping"
-#endif
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c
deleted file mode 100644
index 9d205b763..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_dumpgpio.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <debug.h>
-
-#include <nuttx/arch.h>
-
-#include "up_arch.h"
-
-#include "chip.h"
-#include "lm_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/* NOTE: this is duplicated in lm3s_gpio.c */
-
-#ifdef LM3S_GPIOH_BASE
-static const uint32_t g_gpiobase[8] =
-{
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
-};
-
-static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
-#else
-static const uint32_t g_gpiobase[8] =
-{
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
-};
-
-static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_gpiobaseaddress
- *
- * Description:
- *   Given a GPIO enumeration value, return the base address of the
- *   associated GPIO registers.
- *
- ****************************************************************************/
-
-static inline uint32_t lm3s_gpiobaseaddress(int port)
-{
-  return g_gpiobase[port & 7];
-}
-
-/****************************************************************************
- * Name: lm3s_gpioport
- *
- * Description:
- *   Given a GPIO enumeration value, return the base address of the
- *   associated GPIO registers.
- *
- ****************************************************************************/
-
-static inline uint8_t lm3s_gpioport(int port)
-{
-  return g_portchar[port & 7];
-}
-
-/****************************************************************************
- * Global Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function:  lm3s_dumpgpio
- *
- * Description:
- *   Dump all GPIO registers associated with the provided base address
- *
- ****************************************************************************/
-
-int lm3s_dumpgpio(uint32_t pinset, const char *msg)
-{
-  irqstate_t   flags;
-  unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  uint32_t     base;
-  uint32_t     rcgc2;
-  bool         enabled;
-
-  /* Get the base address associated with the GPIO port */
-
-  base = lm3s_gpiobaseaddress(port);
-  DEBUGASSERT(base != 0);
-
-  /* The following requires exclusive access to the GPIO registers */
-
-  flags   = irqsave();
-  rcgc2   = getreg32(LM3S_SYSCON_RCGC2);
-  enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
-
-  lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
-        lm3s_gpioport(port), pinset, base, msg);
-  lldbg("  RCGC2: %08x (%s)\n",
-        rcgc2, enabled ? "enabled" : "disabled" );
-
-  /* Don't bother with the rest unless the port is enabled */
-
-  if (enabled)
-    {
-      lldbg("  AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
-            getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET),
-            getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc));
-      lldbg("  IS:    %02x IBE: %02x IEV: %02x IM:  %02x RIS: %08x MIS: %08x\n",
-            getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET),
-            getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET));
-      lldbg("  2MA:   %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
-            getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET),
-            getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET),
-            getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET),
-            getreg32(base + LM3S_GPIO_SLR_OFFSET));
-    }
-  irqrestore(flags);
-  return OK;
-}
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c
deleted file mode 100644
index f44b6654f..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c
+++ /dev/null
@@ -1,1472 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_ethernet.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#if defined(CONFIG_NET) && defined(CONFIG_LM3S_ETHERNET)
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <time.h>
-#include <string.h>
-#include <debug.h>
-#include <wdog.h>
-#include <errno.h>
-
-#include <nuttx/irq.h>
-#include <nuttx/arch.h>
-#include <arch/board/board.h>
-#include <nuttx/net/uip/uip.h>
-#include <nuttx/net/uip/uip-arp.h>
-#include <nuttx/net/uip/uip-arch.h>
-
-#include "chip.h"
-#include "up_arch.h"
-
-#include "lm_gpio.h"
-#include "lm_ethernet.h"
-#include "chip/lm_pinmap.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Half duplex can be forced if CONFIG_LM3S_ETHHDUPLEX is defined. */
-
-#ifdef CONFIG_LM3S_ETHHDUPLEX
-#  define LM3S_DUPLEX_SETBITS 0
-#  define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
-#else 
-#  define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX
-#  define LM3S_DUPLEX_CLRBITS 0
-#endif
-
-/* Auto CRC generation can be suppressed if CONFIG_LM3S_ETHNOAUTOCRC is definde */
-
-#ifdef CONFIG_LM3S_ETHNOAUTOCRC
-#  define LM3S_CRC_SETBITS 0
-#  define LM3S_CRC_CLRBITS MAC_TCTL_CRC
-#else 
-#  define LM3S_CRC_SETBITS MAC_TCTL_CRC
-#  define LM3S_CRC_CLRBITS 0
-#endif
-
-/* Tx padding can be suppressed if CONFIG_LM3S_ETHNOPAD is defined */
-
-#ifdef CONFIG_LM3S_ETHNOPAD
-#  define LM3S_PADEN_SETBITS 0
-#  define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN
-#else 
-#  define LM3S_PADEN_SETBITS MAC_TCTL_PADEN
-#  define LM3S_PADEN_CLRBITS 0
-#endif
-
-#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS)
-#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS)
-
-/* Multicast frames can be enabled by defining CONFIG_LM3S_MULTICAST */
-
-#ifdef CONFIG_LM3S_MULTICAST
-#  define LM3S_AMUL_SETBITS MAC_RCTL_AMUL
-#  define LM3S_AMUL_CLRBITS 0
-#else 
-#  define LM3S_AMUL_SETBITS 0
-#  define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL
-#endif
-
-/* Promiscuous mode can be enabled by defining CONFIG_LM3S_PROMISCUOUS */
-
-#ifdef CONFIG_LM3S_PROMISCUOUS
-#  define LM3S_PRMS_SETBITS MAC_RCTL_PRMS
-#  define LM3S_PRMS_CLRBITS 0
-#else 
-#  define LM3S_PRMS_SETBITS 0
-#  define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS
-#endif
-
-/* Bad CRC rejection can be enabled by define CONFIG_LM3S_BADCRC */
-
-#ifdef CONFIG_LM3S_BADCRC
-#  define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC
-#  define LM3S_BADCRC_CLRBITS 0
-#else 
-#  define LM3S_BADCRC_SETBITS 0
-#  define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC
-#endif
-
-#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS)
-#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS)
-
-/* CONFIG_LM3S_DUMPPACKET will dump the contents of each packet to the console. */
-
-#ifdef CONFIG_LM3S_DUMPPACKET
-#  define lm3s_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
-#else
-#  define lm3s_dumppacket(m,a,n)
-#endif
-
-/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
-
-#define LM3S_WDDELAY   (1*CLK_TCK)
-#define LM3S_POLLHSEC  (1*2)
-
-/* TX timeout = 1 minute */
-
-#define LM3S_TXTIMEOUT (60*CLK_TCK)
-
-/* This is a helper pointer for accessing the contents of the Ethernet header */
-
-#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf)
-
-#define LM32S_MAX_MDCCLK 2500000
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/* EMAC statistics (debug only) */
-
-#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
-struct lm3s_statistics_s
-{
-  uint32_t rx_int;         /* Number of Rx interrupts received */
-  uint32_t rx_packets;     /* Number of packets received (sum of the following): */
-  uint32_t rx_ip;          /*   Number of Rx IP packets received */
-  uint32_t rx_arp;         /*   Number of Rx ARP packets received */
-  uint32_t rx_dropped;     /*   Number of dropped, unsupported Rx packets */
-  uint32_t rx_pktsize;     /*   Number of dropped, too small or too big */
-  uint32_t rx_errors;      /* Number of Rx errors (reception error) */
-  uint32_t rx_ovrerrors;   /* Number of Rx FIFO overrun errors */
-  uint32_t tx_int;         /* Number of Tx interrupts received */
-  uint32_t tx_packets;     /* Number of Tx packets queued */
-  uint32_t tx_errors;      /* Number of Tx errors (transmission error)*/
-  uint32_t tx_timeouts;    /* Number of Tx timeout errors */
-};
-#  define EMAC_STAT(priv,name) priv->ld_stat.name++
-#else
-#  define EMAC_STAT(priv,name)
-#endif
-
-/* The lm3s_driver_s encapsulates all state information for a single hardware
- * interface
- */
-
-struct lm3s_driver_s
-{
-  /* The following fields would only be necessary on chips that support
-   * multiple Ethernet controllers.
-   */
-
-#if LM3S_NETHCONTROLLERS > 1
-  uint32_t ld_base;             /* Ethernet controller base address */
-  int      ld_irq;              /* Ethernet controller IRQ */
-#endif
-
-  bool     ld_bifup;           /* true:ifup false:ifdown */
-  WDOG_ID  ld_txpoll;          /* TX poll timer */
-  WDOG_ID  ld_txtimeout;       /* TX timeout timer */
-
-#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
-  struct lm3s_statistics_s ld_stat;
-#endif
-
-  /* This holds the information visible to uIP/NuttX */
-
-  struct uip_driver_s ld_dev;  /* Interface understood by uIP */
-};
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-static struct lm3s_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS];
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/* Miscellaneous low level helpers */
-
-#if LM3S_NETHCONTROLLERS > 1
-static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset);
-static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value);
-#else
-static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset);
-static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value);
-#endif
-static void lm3s_ethreset(struct lm3s_driver_s *priv);
-#if 0 /* Not used */
-static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value);
-#endif
-static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr);
-
-/* Common TX logic */
-
-static int  lm3s_transmit(struct lm3s_driver_s *priv);
-static int  lm3s_uiptxpoll(struct uip_driver_s *dev);
-
-/* Interrupt handling */
-
-static void lm3s_receive(struct lm3s_driver_s *priv);
-static void lm3s_txdone(struct lm3s_driver_s *priv);
-static int  lm3s_interrupt(int irq, FAR void *context);
-
-/* Watchdog timer expirations */
-
-static void lm3s_polltimer(int argc, uint32_t arg, ...);
-static void lm3s_txtimeout(int argc, uint32_t arg, ...);
-
-/* NuttX callback functions */
-
-static int  lm3s_ifup(struct uip_driver_s *dev);
-static int  lm3s_ifdown(struct uip_driver_s *dev);
-static int  lm3s_txavail(struct uip_driver_s *dev);
-#ifdef CONFIG_NET_IGMP
-static int  lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
-static int  lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function: lm3s_ethin
- *
- * Description:
- *   Read a register from the Ethernet module
- *
- * Parameters:
- *   priv   - Reference to the driver state structure
- *   offset - Byte offset of the register from the ethernet base address
- *
- * Returned Value:
- *   Register value
- *
- ****************************************************************************/
-
-#if LM3S_NETHCONTROLLERS > 1
-static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset)
-{
-  return getreg32(priv->ld_base + offset);
-}
-#else
-static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset)
-{
-  return getreg32(LM3S_ETHCON_BASE + offset);
-}
-#endif
-
-/****************************************************************************
- * Function: lm3s_ethout
- *
- * Description:
- *   Write a register to the Ethernet module
- *
- * Parameters:
- *   priv   - Reference to the driver state structure
- *   offset - Byte offset of the register from the ethernet base address
- *   value  - The value to write the Ethernet register
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#if LM3S_NETHCONTROLLERS > 1
-static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value)
-{
-  putreg32(value, priv->ld_base + offset);
-}
-#else
-static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value)
-{
-  putreg32(value, LM3S_ETHCON_BASE + offset);
-}
-#endif
-
-/****************************************************************************
- * Function: lm3s_ethreset
- *
- * Description:
- *   Configure and reset the Ethernet module, leaving it in a disabled state.
- *
- * Parameters:
- *   priv   - Reference to the driver state structure
- *
- * Returned Value:
- *   OK on success; a negated errno on failure
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_ethreset(struct lm3s_driver_s *priv)
-{
-  irqstate_t flags;
-  uint32_t regval;
-
-#if LM3S_NETHCONTROLLERS > 1
-#  error "If multiple interfaces are supported, this function would have to be redesigned"
-#endif
-
-  /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
-
-  flags   = irqsave();
-  regval  = getreg32(LM3S_SYSCON_RCGC2);
-  regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_RCGC2);
-  nllvdbg("RCGC2: %08x\n", regval);
-
-  /* Put the Ethernet controller into the reset state */
-
-  regval = getreg32(LM3S_SYSCON_SRCR2);
-  regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_SRCR2);
-
-  /* Wait just a bit.  This is a much longer delay than necessary */
-
-  up_mdelay(2);
-
-  /* Then take the Ethernet controller out of the reset state */
-
-  regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_SRCR2);
-  nllvdbg("SRCR2: %08x\n", regval);
-
-  /* Wait just a bit, again.  If we touch the ethernet too soon, we may busfault. */
-
-  up_mdelay(2);
-
-  /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */
-
-#ifdef CONFIG_LM3S_ETHLEDS
-  /* Configure the pins for the peripheral function */
-
-  lm3s_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
-  lm3s_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
-#endif
-
-  /* Disable all Ethernet controller interrupts */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
-  regval &= ~MAC_IM_ALLINTS;
-  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
-
-  /* Clear any pending interrupts (shouldn't be any) */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
-  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
-  irqrestore(flags);
-}
-
-/****************************************************************************
- * Function: lm3s_phywrite
- *
- * Description:
- *   Write a 16-bit word to a PHY register
- *
- * Parameters:
- *   priv    - Reference to the driver state structure
- *   regaddr - Address of the PHY register to write
- *   value   - The value to write to the register
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#if 0 /* Not used */
-static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value)
-{
-  /* Wait for any MII transactions in progress to complete */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
-
-  /* Set up the data to be written */
-
-  DEBUGASSERT(value < MAC_MTXD_MASK);
-  lm3s_ethout(priv, LM3S_MAC_MTXD_OFFSET, value);
-
-  /* Set up the PHY register address and start the write operation */
-
-  regaddr <<= MAC_MCTL_REGADR_SHIFT;
-  DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
-  lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
-
-  /* Wait for the write transaction to complete */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
-}
-#endif
-
-/****************************************************************************
- * Function: lm3s_phyread
- *
- * Description:
- *   Write a 16-bit word to a PHY register
- *
- * Parameters:
- *   priv    - Reference to the driver state structure
- *   regaddr - Address of the PHY register to write
- *   value   - The value to write to the register
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr)
-{
-  /* Wait for any MII transactions in progress to complete */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
-
-  /* Set up the PHY register address and start the read operation */
-
-  regaddr <<= MAC_MCTL_REGADR_SHIFT;
-  DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
-  lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
-
-  /* Wait for the write transaction to complete */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
-
-  /* Read and return the PHY data */
-
-  return (uint16_t)(lm3s_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
-}
-
-/****************************************************************************
- * Function: lm3s_transmit
- *
- * Description:
- *   Start hardware transmission.  Called either from the txdone interrupt
- *   handling or from watchdog based polling.
- *
- * Parameters:
- *   priv  - Reference to the driver state structure
- *
- * Returned Value:
- *   OK on success; a negated errno on failure
- *
- ****************************************************************************/
-
-static int lm3s_transmit(struct lm3s_driver_s *priv)
-{
-  irqstate_t flags;
-  uint32_t   regval;
-  uint8_t   *dbuf;
-  int        pktlen;
-  int        bytesleft;
-  int        ret = -EBUSY;
-
-  /* Verify that the hardware is ready to send another packet */
-
-  flags = irqsave();
-  if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-    {
-      /* Increment statistics */
-
-      EMAC_STAT(priv, tx_packets);
-      lm3s_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
-
-      /* Transfer the packet into the Tx FIFO.  The LS 16-bits of the first
-       * 32-bit word written to the Tx FIFO contains the Ethernet payload
-       * data length.  That is the full length of the message (d_len) minus
-       * the size of the Ethernet header (14).
-       */
-
-      pktlen     = priv->ld_dev.d_len;
-      nllvdbg("Sending packet, pktlen: %d\n", pktlen);
-      DEBUGASSERT(pktlen > UIP_LLH_LEN);
-
-      dbuf       = priv->ld_dev.d_buf;
-      regval     = (uint32_t)(pktlen - 14);
-      regval    |= ((uint32_t)(*dbuf++) << 16);
-      regval    |= ((uint32_t)(*dbuf++) << 24);
-      lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
-
-      /* Write all of the whole, 32-bit values in the middle of the packet */
-
-      for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4)
-        {
-          /* Transfer a whole word from the user buffer.  Note, the user
-           * buffer may be un-aligned.
-           */
-
-          lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
-        }
-
-      /* Write the last, partial word in the FIFO */
-
-      if (bytesleft > 0)
-        {
-          /* Write the last word */
-
-          regval = 0;
-          switch (bytesleft)
-            {
-              case 0:
-              default:
-                break;
-
-              case 3:
-                regval |= ((uint32_t)dbuf[2] << 16);
-              case 2:
-                regval |= ((uint32_t)dbuf[1] << 8);
-              case 1:
-                regval |= (uint32_t)dbuf[0];
-                break;
-            }
-          lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
-        }
-
-      /* Activate the transmitter */
-
-      lm3s_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX);
-
-      /* Setup the TX timeout watchdog (perhaps restarting the timer) */
-
-      (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32_t)priv);
-      ret = OK;
-    }
-
-  irqrestore(flags);
-  return ret;
-}
-
-/****************************************************************************
- * Function: lm3s_uiptxpoll
- *
- * Description:
- *   The transmitter is available, check if uIP has any outgoing packets ready
- *   to send.  This is a callback from uip_poll().  uip_poll() may be called:
- *
- *   1. When the preceding TX packet send is complete,
- *   2. When the preceding TX packet send timesout and the interface is reset
- *   3. During normal TX polling
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *
- * Returned Value:
- *   OK on success; a negated errno on failure
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static int lm3s_uiptxpoll(struct uip_driver_s *dev)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
-  int ret = OK;
-
-  /* If the polling resulted in data that should be sent out on the network,
-   * the field d_len is set to a value > 0.
-   */
-
-  nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len);
-  if (priv->ld_dev.d_len > 0)
-    {
-      /* Send the packet.  lm3s_transmit() will return zero if the
-       * packet was successfully handled.
-       */
-
-      DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-      uip_arp_out(&priv->ld_dev);
-      ret = lm3s_transmit(priv);
-    }
-
-  /* If zero is returned, the polling will continue until all connections have
-   * been examined.
-   */
-
-  return ret;
-}
-
-/****************************************************************************
- * Function: lm3s_receive
- *
- * Description:
- *   An interrupt was received indicating the availability of a new RX packet
- *
- * Parameters:
- *   priv  - Reference to the driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_receive(struct lm3s_driver_s *priv)
-{
-  uint32_t regval;
-  uint8_t *dbuf;
-  int      pktlen;
-  int      bytesleft;
-
-  /* Loop while there are incoming packets to be processed */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
-    {
-      /* Update statistics */
-
-      EMAC_STAT(priv, rx_packets);
-
-      /* Copy the data data from the hardware to priv->ld_dev.d_buf.  Set
-       * amount of data in priv->ld_dev.d_len
-       */
-
-      dbuf = priv->ld_dev.d_buf;
-
-      /* The packet frame length begins in the LS 16-bits of the first
-       * word from the FIFO followed by the Ethernet header beginning
-       * in the MS 16-bits of the first word.
-       *
-       * Pick off the packet length from the first word.  This packet length
-       * includes the len/type field (size 2) and the FCS (size 4).
-       */
-
-      regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
-      pktlen = (int)(regval & 0x0000ffff);
-      nllvdbg("Receiving packet, pktlen: %d\n", pktlen);
-
-      /* Check if the pktlen is valid.  It should be large enough to hold
-       * an Ethernet header and small enough to fit entirely in the I/O
-       * buffer.  Six is subtracted to acount for the 2-byte length/type
-       * and 4 byte FCS that are not copied into the uIP packet.
-       */
-
-      if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6))
-        {
-          int wordlen;
-
-          /* We will have to drop this packet */
-
-          nlldbg("Bad packet size dropped (%d)\n", pktlen);
-          EMAC_STAT(priv, rx_pktsize);
-
-          /* The number of bytes and words left to read is pktlen - 4 (including,
-           * the final, possibly partial word) because we've already read 4 bytes.
-           */
-
-          wordlen = (pktlen - 1) >> 2;
-
-          /* Read and discard the remaining words in the FIFO */
-
-          while (wordlen--)
-            {
-              (void)lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
-            }
-
-          /* Check for another packet */
-
-          continue;
-        }
-
-      /* Save the first two bytes from the first word */
-
-      *dbuf++   = (uint8_t)((regval >> 16) & 0xff);
-      *dbuf++   = (uint8_t)((regval >> 24) & 0xff);
-
-      /* Read all of the whole, 32-bit values in the middle of the packet.
-       * We've already read the length (2 bytes) plus the first two bytes
-       * of data.
-       */
-
-      for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4)
-        {
-          /* Transfer a whole word to the user buffer.  Note, the user
-           * buffer may be un-aligned.
-           */
-
-          *(uint32_t*)dbuf = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
-        }
-
-      /* Handle the last, partial word in the FIFO (0-3 bytes) and discard
-       * the 4-byte FCS.
-       */
-
-      for (; bytesleft > 0; bytesleft -= 4)
-        {
-          /* Read the last word.  And transfer all but the last four
-           * bytes of the FCS into the user buffer.
-           */
-
-          regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
-          switch (bytesleft)
-            {
-              default:
-                break;
-
-              case 7:
-                dbuf[2] = (regval >> 16) & 0xff;
-              case 6:
-                dbuf[1] = (regval >> 8) & 0xff;
-              case 5:
-                dbuf[0] = regval & 0xff;
-                break;
-            }
-        }
-
-      /* Pass the packet length to uIP MINUS 2 bytes for the length and
-       * 4 bytes for the FCS.
-       */
-
-      priv->ld_dev.d_len = pktlen - 6;
-      lm3s_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
-
-      /* We only accept IP packets of the configured type and ARP packets */
-
-#ifdef CONFIG_NET_IPv6
-      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6))
-#else
-      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP))
-#endif
-        {
-          nllvdbg("IP packet received (%02x)\n", ETHBUF->type);
-          EMAC_STAT(priv, rx_ip);
-
-          uip_arp_ipin(&priv->ld_dev);
-          uip_input(&priv->ld_dev);
-
-          /* If the above function invocation resulted in data that should be
-           * sent out on the network, the field  d_len will set to a value > 0.
-           */
-
-          if (priv->ld_dev.d_len > 0)
-            {
-              uip_arp_out(&priv->ld_dev);
-              lm3s_transmit(priv);
-            }
-        }
-      else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP))
-        {
-          nllvdbg("ARP packet received (%02x)\n", ETHBUF->type);
-          EMAC_STAT(priv, rx_arp);
-
-          uip_arp_arpin(&priv->ld_dev);
-
-          /* If the above function invocation resulted in data that should be
-           * sent out on the network, the field  d_len will set to a value > 0.
-           */
-
-           if (priv->ld_dev.d_len > 0)
-             {
-               lm3s_transmit(priv);
-             }
-        }
-#ifdef CONFIG_DEBUG
-      else
-        {
-          nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type));
-          EMAC_STAT(priv, rx_dropped);
-        }
-#endif
-    }
-}
-
-/****************************************************************************
- * Function: lm3s_txdone
- *
- * Description:
- *   An interrupt was received indicating that the last TX packet(s) is done
- *
- * Parameters:
- *   priv  - Reference to the driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_txdone(struct lm3s_driver_s *priv)
-{
-  /* Cancel the TX timeout */
-
-  wd_cancel(priv->ld_txtimeout);
-
-  /* Verify that the Tx FIFO is not in use.  The NEWTX bit initiates an
-   * Ethernet transmission once the packet has been placed in the TX FIFO.
-   * This bit is cleared once the transmission has been completed.  Since
-   * we get here because of of TXEMP which indicates that the packet was
-   * transmitted and that the TX FIFO is empty, NEWTX should always be zero
-   * at this point.
-   */
-
-  DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-
-  /* Then poll uIP for new XMIT data */
-
-  (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
-}
-
-/****************************************************************************
- * Function: lm3s_interrupt
- *
- * Description:
- *   Hardware interrupt handler
- *
- * Parameters:
- *   irq     - Number of the IRQ that generated the interrupt
- *   context - Interrupt register state save info (architecture-specific)
- *
- * Returned Value:
- *   OK on success
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static int lm3s_interrupt(int irq, FAR void *context)
-{
-  register struct lm3s_driver_s *priv;
-  uint32_t ris;
-
-#if LM3S_NETHCONTROLLERS > 1
-# error "A mechanism to associate and interface with an IRQ is needed"
-#else
-  priv = &g_lm3sdev[0];
-#endif
-
-  /* Read the raw interrupt status register */
-
-  ris = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
-
-  /* Clear all pending interrupts */
-
-  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, ris);
-
-  /* Check for errors */
-
-#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
-  if ((ris & MAC_RIS_TXER) != 0)
-    {
-      EMAC_STAT(priv, tx_errors);      /* Number of Tx errors */
-    }
-
-  if ((ris & MAC_RIS_FOV) != 0)
-    {
-      EMAC_STAT(priv, rx_ovrerrors);   /* Number of Rx FIFO overrun errors */
-    }
-
-  if ((ris & MAC_RIS_RXER) != 0)
-    {
-      EMAC_STAT(priv, rx_errors);      /* Number of Rx errors */
-    }
-#endif
-
-  /* Handle (unmasked) interrupts according to status bit settings */
-
-  ris &= lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
-
-  /* Is this an Rx interrupt (meaning that a packet has been received)? */
-
-  if ((ris & MAC_RIS_RXINT) != 0)
-    {
-      /* Handle the incoming packet */
-
-      EMAC_STAT(priv, rx_int);
-      lm3s_receive(priv);
-    }
-
-  /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */
-
-  if ((ris & MAC_RIS_TXEMP) != 0)
-    {
-       /* Handle the complete of the transmission */
-
-      EMAC_STAT(priv, tx_int);
-      lm3s_txdone(priv);
-    }
-
-  /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if 
-   * there are no pending transmissions).
-   */
-
-  return OK;
-}
-
-/****************************************************************************
- * Function: lm3s_txtimeout
- *
- * Description:
- *   Our TX watchdog timed out.  Called from the timer interrupt handler.
- *   The last TX never completed.  Reset the hardware and start again.
- *
- * Parameters:
- *   argc - The number of available arguments
- *   arg  - The first argument
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_txtimeout(int argc, uint32_t arg, ...)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg;
-
-  /* Increment statistics */
-
-  nlldbg("Tx timeout\n");
-  EMAC_STAT(priv, tx_timeouts);
-
-  /* Then reset the hardware */
-
-  DEBUGASSERT(priv->ld_bifup);
-  lm3s_ifdown(&priv->ld_dev);
-  lm3s_ifup(&priv->ld_dev);
-
-  /* Then poll uIP for new XMIT data */
-
-  (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
-}
-
-/****************************************************************************
- * Function: lm3s_polltimer
- *
- * Description:
- *   Periodic timer handler.  Called from the timer interrupt handler.
- *
- * Parameters:
- *   argc - The number of available arguments
- *   arg  - The first argument
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_polltimer(int argc, uint32_t arg, ...)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg;
-
-  /* Check if we can send another Tx packet now.  The NEWTX bit initiates an
-   * Ethernet transmission once the packet has been placed in the TX FIFO.
-   * This bit is cleared once the transmission has been completed.
-   *
-   * NOTE: This can cause missing poll cycles and, hence, some timing
-   * inaccuracies.
-   */
-
-  if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-    {
-      /* If so, update TCP timing states and poll uIP for new XMIT data */
-
-      (void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC);
-
-      /* Setup the watchdog poll timer again */
-
-      (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg);
-    }
-}
-
-/****************************************************************************
- * Function: lm3s_ifup
- *
- * Description:
- *   NuttX Callback: Bring up the Ethernet interface when an IP address is
- *   provided 
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static int lm3s_ifup(struct uip_driver_s *dev)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
-  irqstate_t flags;
-  uint32_t regval;
-  uint32_t div;
-  uint16_t phyreg;
-
-  nlldbg("Bringing up: %d.%d.%d.%d\n",
-       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
-
-  /* Enable and reset the Ethernet controller */
-
-  flags = irqsave();
-  lm3s_ethreset(priv);
-
-  /* Set the management clock divider register for access to the PHY
-   * register set. The MDC clock is divided down from the system clock per:
-   *
-   *   MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1))
-   *   div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1
-   *
-   * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000.  We will
-   * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded.
-   */
-
-  div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK;
-  lm3s_ethout(priv, LM3S_MAC_MDV_OFFSET, div);
-  nllvdbg("MDV:   %08x\n", div);
-
-  /* Then configure the Ethernet Controller for normal operation 
-   *
-   * Setup the transmit control register (Full duplex, TX CRC Auto Generation,
-   * TX Padding Enabled).
-   */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET);
-  regval &= ~LM3S_TCTCL_CLRBITS;
-  regval |= LM3S_TCTCL_SETBITS;
-  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
-  nllvdbg("TCTL:  %08x\n", regval);
-
-  /* Setup the receive control register (Disable multicast frames, disable
-   * promiscuous mode, disable bad CRC rejection).
-   */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval &= ~LM3S_RCTCL_CLRBITS;
-  regval |= LM3S_RCTCL_SETBITS;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-  nllvdbg("RCTL:  %08x\n", regval);
-
-  /* Setup the time stamp configuration register */
-
-#ifdef LM3S_ETHTS
-  regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET);
-#ifdef CONFIG_LM3S_TIMESTAMP
-  regval |= MAC_TS_EN;
-#else
-  regval &= ~(MAC_TS_EN);
-#endif
-  lm3s_ethout(priv, LM3S_MAC_TS_OFFSET, regval);
-  nllvdbg("TS:    %08x\n", regval);
-#endif
-
-  /* Wait for the link to come up.  This following is not very conservative
-   * of system resources -- it really should wait gracefully on a semaphore
-   * and the interrupt handler should post the semaphore when LINKSTATUS is
-   * set
-   */
-
-  nlldbg("Waiting for link\n");
-  do
-    {
-      phyreg = lm3s_phyread(priv, MII_MSR);
-    }
-  while ((phyreg & MII_MSR_LINKSTATUS) == 0);
-  nlldbg("Link established\n");
-
-  /* Reset the receive FIFO */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RSTFIFO;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Enable the Ethernet receiver */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RXEN;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Enable the Ethernet transmitter */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET);
-  regval |= MAC_TCTL_TXEN;
-  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
-
-  /* Reset the receive FIFO (again) */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RSTFIFO;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Enable the Ethernet interrupt */
-
-#if LM3S_NETHCONTROLLERS > 1
-  up_enable_irq(priv->irq);
-#else
-  up_enable_irq(LM3S_IRQ_ETHCON);
-#endif
-
-  /* Enable the Ethernet RX packet receipt interrupt */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
-  regval |= MAC_IM_RXINTM;
-  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
-
-  /* Program the hardware with it's MAC address (for filtering) */
-
-  regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 |
-           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 |
-           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 |
-           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0];
-  lm3s_ethout(priv, LM3S_MAC_IA0_OFFSET, regval);
-
-  regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 |
-           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4];
-  lm3s_ethout(priv, LM3S_MAC_IA1_OFFSET, regval);
-
-  /* Set and activate a timer process */
-
-  (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, (uint32_t)priv);
-
-  priv->ld_bifup = true;
-  irqrestore(flags);
-  return OK;
-}
-
-/****************************************************************************
- * Function: lm3s_ifdown
- *
- * Description:
- *   NuttX Callback: Stop the interface.  The only way to restore normal
- *   behavior is to call lm3s_ifup().
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static int lm3s_ifdown(struct uip_driver_s *dev)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
-  irqstate_t flags;
-  uint32_t regval;
-
-  nlldbg("Taking down: %d.%d.%d.%d\n",
-       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
-
-  /* Cancel the TX poll timer and TX timeout timers */
-
-  flags = irqsave();
-  wd_cancel(priv->ld_txpoll);
-  wd_cancel(priv->ld_txtimeout);
-
-  /* Disable the Ethernet interrupt */
-
-#if LM3S_NETHCONTROLLERS > 1
-  up_disable_irq(priv->irq);
-#else
-  up_disable_irq(LM3S_IRQ_ETHCON);
-#endif
-
-  /* Disable all Ethernet controller interrupt sources */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
-  regval &= ~MAC_IM_ALLINTS;
-  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
-
-  /* Reset the receive FIFO */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RSTFIFO;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Disable the Ethernet receiver */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval &= ~MAC_RCTL_RXEN;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Disable the Ethernet transmitter */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval &= ~MAC_TCTL_TXEN;
-  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
-
-  /* Reset the receive FIFO (again) */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RSTFIFO;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Clear any pending interrupts */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
-  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
-
-  /* The interface is now DOWN */
-
-  priv->ld_bifup = false;
-  irqrestore(flags);
-  return OK;
-}
-
-/****************************************************************************
- * Function: lm3s_txavail
- *
- * Description:
- *   Driver callback invoked when new TX data is available.  This is a 
- *   stimulus perform an out-of-cycle poll and, thereby, reduce the TX
- *   latency.
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *   Called in normal user mode
- *
- ****************************************************************************/
-
-static int lm3s_txavail(struct uip_driver_s *dev)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
-  irqstate_t flags;
-
-  /* Ignore the notification if the interface is not yet up or if the Tx FIFO
-   * hardware is not available at this time.  The NEWTX bit initiates an
-   * Ethernet transmission once the packet has been placed in the TX FIFO.
-   * This bit is cleared once the transmission has been completed.  When the
-   * transmission completes, lm3s_txdone() will be called and the Tx polling
-   * will occur at that time.
-   */
-
-  flags = irqsave();
-  if (priv->ld_bifup && (lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-    {
-      /* If the interface is up and we can use the Tx FIFO, then poll uIP
-       * for new Tx data
-       */
-
-      (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
-    }
-
-  irqrestore(flags);
-  return OK;
-}
-
-/****************************************************************************
- * Function: lm3s_addmac
- *
- * Description:
- *   NuttX Callback: Add the specified MAC address to the hardware multicast
- *   address filtering
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *   mac  - The MAC address to be added 
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#ifdef CONFIG_NET_IGMP
-static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
-{
-  FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private;
-
-  /* Add the MAC address to the hardware multicast routing table */
-
-#warning "Multicast MAC support not implemented"
-  return OK;
-}
-#endif
-
-/****************************************************************************
- * Function: lm3s_rmmac
- *
- * Description:
- *   NuttX Callback: Remove the specified MAC address from the hardware multicast
- *   address filtering
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *   mac  - The MAC address to be removed 
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#ifdef CONFIG_NET_IGMP
-static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
-{
-  FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private;
-
-  /* Add the MAC address to the hardware multicast routing table */
-
-#warning "Multicast MAC support not implemented"
-  return OK;
-}
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function: lm3s_ethinitialize
- *
- * Description:
- *   Initialize the Ethernet driver for one interface
- *
- * Parameters:
- *   None
- *
- * Returned Value:
- *   OK on success; Negated errno on failure.
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#if LM3S_NETHCONTROLLERS > 1
-int lm3s_ethinitialize(int intf)
-#else
-static inline int lm3s_ethinitialize(int intf)
-#endif
-{
-  struct lm3s_driver_s *priv = &g_lm3sdev[intf];
-  int ret;
-
-  /* Check if the Ethernet module is present */
-
-  ndbg("Setting up eth%d\n", intf);
-
-#if LM3S_NETHCONTROLLERS > 1
-# error "This debug check only works with one interface"
-#else
-  DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
-#endif
-  DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS);
-
-  /* Initialize the driver structure */
-
-  memset(priv, 0, sizeof(struct lm3s_driver_s));
-  priv->ld_dev.d_ifup    = lm3s_ifup;     /* I/F down callback */
-  priv->ld_dev.d_ifdown  = lm3s_ifdown;   /* I/F up (new IP address) callback */
-  priv->ld_dev.d_txavail = lm3s_txavail;  /* New TX data callback */
-#ifdef CONFIG_NET_IGMP
-  priv->ld_dev.d_addmac  = lm3s_addmac;   /* Add multicast MAC address */
-  priv->ld_dev.d_rmmac   = lm3s_rmmac;    /* Remove multicast MAC address */
-#endif
-  priv->ld_dev.d_private = (void*)priv;   /* Used to recover private state from dev */
-
-  /* Create a watchdog for timing polling for and timing of transmisstions */
-
-#if LM3S_NETHCONTROLLERS > 1
-# error "A mechanism to associate base address an IRQ with an interface is needed"
-  priv->ld_base          = ??;            /* Ethernet controller base address */
-  priv->ld_irq           = ??;            /* Ethernet controller IRQ number */
-#endif
-  priv->ld_txpoll        = wd_create();   /* Create periodic poll timer */
-  priv->ld_txtimeout     = wd_create();   /* Create TX timeout timer */
-
-  /* If the board can provide us with a MAC address, get the address
-   * from the board now.  The MAC will not be applied until lm3s_ifup()
-   * is caleld (and the MAC can be overwritten with a netdev ioctl call). 
-   */
-
-#ifdef CONFIG_LM3S_BOARDMAC
-   lm3s_ethernetmac(&priv->ld_dev.d_mac);
-#endif
-
-  /* Perform minimal, one-time initialization -- just reset the controller and
-   * leave it disabled.  The Ethernet controller will be reset and properly
-   * re-initialized each time lm3s_ifup() is called.
-   */
-
-  lm3s_ethreset(priv);
-  lm3s_ifdown(&priv->ld_dev);
-
-  /* Attach the IRQ to the driver */
-
-#if LM3S_NETHCONTROLLERS > 1
-  ret = irq_attach(priv->irq, lm3s_interrupt);
-#else
-  ret = irq_attach(LM3S_IRQ_ETHCON, lm3s_interrupt);
-#endif
-  if (ret != 0)
-    {
-      /* We could not attach the ISR to the IRQ */
-
-      return -EAGAIN;
-    }
-
-  /* Register the device with the OS so that socket IOCTLs can be performed */
-
-  (void)netdev_register(&priv->ld_dev);
-  return OK;
-}
-
-
-/************************************************************************************
- * Name: up_netinitialize
- *
- * Description:
- *   Initialize the first network interface.  If there are more than one interface
- *   in the chip, then board-specific logic will have to provide this function to
- *   determine which, if any, Ethernet controllers should be initialized.
- *
- ************************************************************************************/
-
-#if LM3S_NETHCONTROLLERS == 1
-void up_netinitialize(void)
-{
-  (void)lm3s_ethinitialize(0);
-}
-#endif
-
-#endif /* CONFIG_NET && CONFIG_LM3S_ETHERNET */
-
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c
deleted file mode 100644
index dd005fdd1..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c
+++ /dev/null
@@ -1,854 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_gpio.c
- * arch/arm/src/chip/lm3s_gpio.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <string.h>
-#include <assert.h>
-#include <debug.h>
-
-#include <arch/irq.h>
-
-#include "up_arch.h"
-#include "os_internal.h"
-#include "lm_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* These definitions are part of the implementation of the  GPIO pad
- * configuration of Table 9-1 in the LM3S6918 data sheet.
- */
-
-#define AFSEL_SHIFT            5
-#define AFSEL_1                (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */
-#define AFSEL_0                0
-#define AFSEL_X                0
-
-#define DIR_SHIFT              4
-#define DIR_1                  (1 << DIR_SHIFT)   /* Set/clear bit in GPIO DIR register */
-#define DIR_0                  0
-#define DIR_X                  0
-
-#define ODR_SHIFT              3
-#define ODR_1                  (1 << ODR_SHIFT)   /* Set/clear bit in GPIO ODR register */
-#define ODR_0                  0
-#define ODR_X                  0
-
-#define DEN_SHIFT              2
-#define DEN_1                  (1 << DEN_SHIFT)   /* Set/clear bit in GPIO DEN register */
-#define DEN_0                  0
-#define DEN_X                  0
-
-#define PUR_SHIFT              1
-#define PUR_1                  (1 << PUR_SHIFT)   /* Set/clear bit in GPIO PUR register */
-#define PUR_0                  0
-#define PUR_X                  0
-
-#define PDR_SHIFT              0
-#define PDR_1                  (1 << PDR_SHIFT)   /* Set/clear bit in GPIO PDR register */
-#define PDR_0                  0
-#define PDR_X                  0
-
-#define GPIO_INPUT_SETBITS     (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_INPUT_CLRBITS     (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_OUTPUT_SETBITS    (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_OUTPUT_CLRBITS    (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_ODINPUT_SETBITS   (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_ODINPUT_CLRBITS   (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_ODOUTPUT_SETBITS  (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_ODOUTPUT_CLRBITS  (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_PFODIO_SETBITS    (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_PFODIO_CLRBITS    (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_PFIO_SETBITS      (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_PFIO_CLRBITS      (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_ANINPUT_SETBITS   (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0)
-#define GPIO_ANINPUT_CLRBITS   (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1)
-
-#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X)
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-struct gpio_func_s
-{
-  uint8_t setbits;  /* A set of GPIO register bits to set */
-  uint8_t clrbits;  /* A set of GPIO register bits to clear */
-};
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-static const struct gpio_func_s g_funcbits[] =
-{
-  {GPIO_INPUT_SETBITS,     GPIO_INPUT_CLRBITS},     /* GPIO_FUNC_INPUT */
-  {GPIO_OUTPUT_SETBITS,    GPIO_OUTPUT_CLRBITS},    /* GPIO_FUNC_OUTPUT */
-  {GPIO_ODINPUT_SETBITS,   GPIO_ODINPUT_CLRBITS},   /* GPIO_FUNC_ODINPUT */
-  {GPIO_ODOUTPUT_SETBITS,  GPIO_ODOUTPUT_CLRBITS},  /* GPIO_FUNC_ODOUTPUT */
-  {GPIO_PFODIO_SETBITS,    GPIO_PFODIO_CLRBITS},    /* GPIO_FUNC_PFODIO */
-  {GPIO_PFIO_SETBITS,      GPIO_PFIO_CLRBITS},      /* GPIO_FUNC_PFIO */
-  {GPIO_ANINPUT_SETBITS,   GPIO_ANINPUT_CLRBITS},   /* GPIO_FUNC_ANINPUT */
-  {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
-};
-
-static const uint32_t g_gpiobase[LM3S_NPORTS] =
-{
-  /* All support LM3S parts have at least 7 ports, GPIOA-G */
-
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE,
-
-  /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
-
-#if LM3S_NPORTS > 7
-  LM3S_GPIOH_BASE,
-#endif
-
-  /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
-
-#if LM3S_NPORTS > 8
-  LM3S_GPIOJ_BASE,
-#endif
-};
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_gpiobaseaddress
- *
- * Description:
- *   Given a GPIO enumeration value, return the base address of the
- *   associated GPIO registers.
- *
- ****************************************************************************/
-
-static uint32_t lm3s_gpiobaseaddress(unsigned int port)
-{
-  uint32_t gpiobase = 0;
-  if (port < LM3S_NPORTS)
-    {
-      gpiobase = g_gpiobase[port];
-    }
-  return gpiobase;
-}
-
-/****************************************************************************
- * Name: lm3s_gpiofunc
- *
- * Description:
- *   Configure GPIO registers for a specific function
- *
- ****************************************************************************/
-
-static void lm3s_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func)
-{
-  uint32_t setbit;
-  uint32_t clrbit;
-  uint32_t regval;
-
-  /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain
-   * control register. Setting a bit in this register enables the open drain
-   * configuration of the corresponding GPIO pad. When open drain mode is enabled,
-   * the corresponding bit should also be set in the GPIO Digital Input Enable
-   * (GPIO DEN) register ... Corresponding bits in the drive strength registers
-   * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the
-   * desired rise and fall times. The GPIO acts as an open drain input if the
-   * corresponding bit in the GPIO DIR register is set to 0; and as an open
-   * drain output when set to 1."
-   */
-
-  setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
-
-  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
-  regval &= ~clrbit;
-  regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
-
-  /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
-   * register. When a bit is set to 1, it enables a weak pull-up resistor on the
-   * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
-   * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
-   */
-
-  setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno;
-
-  if (setbit || clrbit)
-    {
-      regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
-      regval &= ~clrbit;
-      regval |= setbit;
-      putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
-    }
-
-  /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
-   * register. When a bit is set to 1, it enables a weak pull-down resistor on the
-   * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
-   * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
-   */
-
-  setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno;
-
-  if (setbit || clrbit)
-    {
-      regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
-      regval &= ~clrbit;
-      regval |= setbit;
-      putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
-    }
-
-  /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
-   * register. By default, with the exception of the GPIO signals used for JTAG/SWD
-   * function, all other GPIO signals are configured out of reset to be undriven
-   * (tristate). Their digital function is disabled; they do not drive a logic
-   * value on the pin and they do not allow the pin voltage into the GPIO receiver.
-   * To use the pin in a digital function (either GPIO or alternate function), the
-   * corresponding GPIODEN bit must be set."
-   */
-
-  setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
-
-  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
-  regval &= ~clrbit;
-  regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
-
-  /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
-   * direction register. Bits set to 1 in the GPIODIR register configure
-   * the corresponding pin to be an output, while bits set to 0 configure the
-   * pins to be inputs. All bits are cleared by a reset, meaning all GPIO
-   * pins are inputs by default.
-   */
-
-  setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
-
-  regval = getreg32(base + LM3S_GPIO_DIR_OFFSET);
-  regval &= ~clrbit;
-  regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_DIR_OFFSET);
-
-  /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
-   * control select register. Writing a 1 to any bit in this register selects
-   * the hardware control for the corresponding GPIO line. All bits are cleared
-   * by a reset, therefore no GPIO line is set to hardware control by default."
-   *
-   * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit
-   * and unlock the GPIO.  That is not implemented here.
-   */
-
-  setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
-
-  regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET);
-  regval &= ~clrbit;
-  regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET);
-}
-
-/****************************************************************************
- * Name: lm3s_gpiopadstrength
- *
- * Description:
- *   Set up pad strength and pull-ups
- *
- ****************************************************************************/
-
-static inline void lm3s_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset)
-{
-  int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT;
-  uint32_t regoffset;
-  uint32_t regval;
-  uint32_t slrset;
-  uint32_t slrclr;
-
-  /* Prepare bits to disable slew */
-
-  slrset = 0;
-  slrclr = pin;
-
-  switch (strength)
-    {
-      case 0: /* 2mA pad drive strength */
-        {
-          /* "The GPIODR2R register is the 2-mA drive control register. It
-           * allows for each GPIO signal in the port to be individually configured
-           * without affecting the other pads. When writing a DRV2 bit for a GPIO
-           * signal, the corresponding DRV4 bit in the GPIO DR4R register and the
-           * DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
-           */
-
-          regoffset = LM3S_GPIO_DR2R_OFFSET;
-        }
-        break;
-
-      case 1: /* 4mA pad drive strength */
-        {
-          /* "The GPIODR4R register is the 4-mA drive control register. It allows
-           * for each GPIO signal in the port to be individually configured without
-           * affecting the other pads. When writing the DRV4 bit for a GPIO signal,
-           * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit
-           * in the GPIO DR8R register are automatically cleared by hardware."
-           */
-
-          regoffset = LM3S_GPIO_DR4R_OFFSET;
-        }
-        break;
-
-      case 3: /* 8mA Pad drive with slew rate control */
-        {
-          /* "The GPIOSLR register is the slew rate control register. Slew rate
-           * control is only available when using the 8-mA drive strength option
-           * via the GPIO 8-mA Drive Select (GPIODR8R) register..."
-           */
-
-          slrset = pin;
-          slrclr = 0;
-        }
-        /* Fall through */
-
-      case 2: /* 8mA pad drive strength (without slew rate control) */
-        {
-          /* "The GPIODR8R register is the 8-mA drive control register. It
-           * allows for each GPIO signal in the port to be individually configured
-           * without affecting the other pads. When writing the DRV8 bit for a GPIO
-           * signal, the corresponding DRV2 bit in the GPIO DR2R register and the
-           * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
-           */
-
-          regoffset = LM3S_GPIO_DR8R_OFFSET;
-        }
-        break;
-    }
-
-  /* Set the selected pad strength and set/clear optional slew rate control */
-
-  regval = getreg32(base + regoffset);
-  regval |= pin;
-  putreg32(regval, base + regoffset);
-
-  regval  = getreg32(base + LM3S_GPIO_SLR_OFFSET);
-  regval &= slrclr;
-  regval |= slrset;
-  putreg32(regval, base + LM3S_GPIO_SLR_OFFSET);
-}
-
-/****************************************************************************
- * Name: lm3s_gpiopadtype
- *
- * Description:
- *   Set up pad strength and pull-ups.  Some of these values may be over-
- *   written by lm3s_gpiofunc, depending on the function selection.  Others
- *   are optional for different function selections.
- *
- ****************************************************************************/
-
-static inline void lm3s_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
-{
-  int padtype  = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT;
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  uint32_t odrset;
-  uint32_t odrclr;
-#endif
-  uint32_t purset;
-  uint32_t purclr;
-  uint32_t pdrset;
-  uint32_t pdrclr;
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  uint32_t denset;
-  uint32_t denclr;
-#endif
-  uint32_t regval;
-
-  /* Assume digital GPIO function, push-pull with no pull-up or pull-down */
-
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  odrset = 0;
-  odrclr = pin;
-#endif
-  purset = 0;
-  purclr = pin;
-  pdrset = 0;
-  pdrclr = pin;
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  denset = pin;
-  denclr = 0;
-#endif
-
-  switch (padtype)
-    {
-      case 0: /* Push-pull */
-      default:
-        {
-        }
-        break;
-
-      case 1: /* Push-pull with weak pull-up */
-        {
-          purset = pin;
-          purclr = 0;
-        }
-        break;
-      case 2: /* Push-pull with weak pull-down */
-        {
-          pdrset = pin;
-          pdrclr = 0;
-        }
-        break;
-      case 3: /* Open-drain */
-        {
-#if 0 /* always overwritten by lm3s_gpiofunc */
-          odrset = pin;
-          odrclr = 0;
-#endif
-        }
-        break;
-      case 4: /* Open-drain with weak pull-up */
-        {
-#if 0 /* always overwritten by lm3s_gpiofunc */
-          odrset = pin;
-          odrclr = 0;
-#endif
-          purset = pin;
-          purclr = 0;
-        }
-        break;
-      case 5: /* Open-drain with weak pull-down */
-        {
-#if 0 /* always overwritten by lm3s_gpiofunc */
-          odrset = pin;
-          odrclr = 0;
-#endif
-          pdrset = pin;
-          pdrclr = 0;
-        }
-        break;
-      case 6: /* Analog comparator */
-        {
-#if 0 /* always overwritten by lm3s_gpiofunc */
-          denset = 0;
-          denclr = pin;
-#endif
-        }
-        break;
-    }
-
-  /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain
-   * control register. Setting a bit in this register enables the open drain
-   * configuration of the corresponding GPIO pad. When open drain mode is enabled,
-   * the corresponding bit should also be set in the GPIO Digital Input Enable
-   * (GPIO DEN) register ... Corresponding bits in the drive strength registers
-   * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the
-   * desired rise and fall times. The GPIO acts as an open drain input if the
-   * corresponding bit in the GPIO DIR register is set to 0; and as an open
-   * drain output when set to 1."
-   */
-
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
-  regval &= ~odrclr;
-  regval |= odrset;
-  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
-#endif
-
-  /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
-   * register. When a bit is set to 1, it enables a weak pull-up resistor on the
-   * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
-   * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
-   */
-
-  regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
-  regval &= ~purclr;
-  regval |= purset;
-  putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
-
-  /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
-   * register. When a bit is set to 1, it enables a weak pull-down resistor on the
-   * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
-   * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
-   */
-
-  regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
-  regval &= ~pdrclr;
-  regval |= pdrset;
-  putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
-
-  /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
-   * register. By default, with the exception of the GPIO signals used for JTAG/SWD
-   * function, all other GPIO signals are configured out of reset to be undriven
-   * (tristate). Their digital function is disabled; they do not drive a logic
-   * value on the pin and they do not allow the pin voltage into the GPIO receiver.
-   * To use the pin in a digital function (either GPIO or alternate function), the
-   * corresponding GPIODEN bit must be set."
-   */
-
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
-  regval &= ~denclr;
-  regval |= denset;
-  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
-#endif
-}
-
-/****************************************************************************
- * Name: lm3s_initoutput
- *
- * Description:
- *   Set the GPIO output value
- *
- ****************************************************************************/
-
-static inline void lm3s_initoutput(uint32_t cfgset)
-{
-  bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO);
-  lm3s_gpiowrite(cfgset, value);
-}
-
-/****************************************************************************
- * Name: lm3s_interrupt
- *
- * Description:
- *   Configure the interrupt pin.
- *
- ****************************************************************************/
-
-static inline void lm3s_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
-{
-  int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT;
-  uint32_t regval;
-  uint32_t isset;
-  uint32_t isclr;
-  uint32_t ibeset;
-  uint32_t ibeclr;
-  uint32_t iveset;
-  uint32_t iveclr;
-
-  /* Mask and clear the GPIO interrupt
-   *
-   * "The GPIOIM register is the interrupt mask register. Bits set to High in
-   * GPIO IM allow the corresponding pins to trigger their individual interrupts
-   * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering
-   * on that pin. All bits are cleared by a reset."
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
-  regval &= ~pin;
-  putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
-
-  /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
-   * in this register clears the corresponding interrupt edge detection logic
-   * register. Writing a 0 has no effect."
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_ICR_OFFSET);
-  regval |= pin;
-  putreg32(regval, base + LM3S_GPIO_ICR_OFFSET);
-
-  /* Assume rising edge */
-
-  isset  = 0;            /* Not level sensed */
-  isclr  = pin;
-  ibeset = 0;            /* Single edge */
-  ibeclr = pin;
-  iveset = pin;          /* Rising edge or high levels*/
-  iveclr = 0;
-
-  /* Then handle according to the selected interrupt type */
-
-  switch (inttype)
-    {
-      case 0:            /* Interrupt on falling edge */
-        {
-          iveset = 0;    /* Falling edge or low levels*/
-          iveclr = pin;
-        }
-        break;
-
-      case 1:           /* Interrupt on rising edge */
-      default:
-        break;
-
-      case 2:           /* Interrupt on both edges */
-        {
-          ibeset = pin; /* Both edges */
-          ibeclr = 0;
-        }
-        break;
-
-      case 3:           /* Interrupt on low level */
-        {
-          isset = pin;  /* Level sensed */
-          isclr = 0;
-          iveset = 0;   /* Falling edge or low levels*/
-          iveclr = pin;
-        }
-        break;
-
-      case 4:           /* Interrupt on high level */
-        {
-          isset = pin;  /* Level sensed */
-          isclr = 0;
-        }
-        break;
-    }
-
-  /* "The GPIO IS register is the interrupt sense register. Bits set to
-   * 1 in GPIOIS configure the corresponding pins to detect levels, while
-   * bits set to 0 configure the pins to detect edges. All bits are cleared
-   * by a reset.
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_IS_OFFSET);
-  regval &= isclr;
-  regval |= isset;
-  putreg32(regval, base + LM3S_GPIO_IS_OFFSET);
-
-  /* "The GPIO IBE register is the interrupt both-edges register. When the
-   * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
-   * set to detect edges, bits set to High in GPIO IBE configure the
-   * corresponding pin to detect both rising and falling edges, regardless
-   * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ...
-   * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits
-   * are cleared by a reset.
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_IBE_OFFSET);
-  regval &= ibeclr;
-  regval |= ibeset;
-  putreg32(regval, base + LM3S_GPIO_IBE_OFFSET);
-
-  /* "The GPIOIEV register is the interrupt event register. Bits set to
-   * High in GPIO IEV configure the corresponding pin to detect rising edges
-   * or high levels, depending on the corresponding bit value in the GPIO
-   * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to
-   * detect falling edges or low levels, depending on the corresponding bit
-   * value in GPIOIS. All bits are cleared by a reset.
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_IEV_OFFSET);
-  regval &= iveclr;
-  regval |= iveset;
-  putreg32(regval, base + LM3S_GPIO_IEV_OFFSET);
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_configgpio
- *
- * Description:
- *   Configure a GPIO pin based on bit-encoded description of the pin.
- *
- ****************************************************************************/
-
-int lm3s_configgpio(uint32_t cfgset)
-{
-  irqstate_t   flags;
-  unsigned int func;
-  unsigned int port;
-  unsigned int pinno;
-  uint32_t     pin;
-  uint32_t     base;
-  uint32_t     regval;
-
-  /* Decode the basics */
-
-  func  = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT;
-  port  = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  pinno = (cfgset & GPIO_NUMBER_MASK);
-  pin   = (1 <<pinno);
-
-  DEBUGASSERT(func <= GPIO_FUNC_MAX);
-
-  /* Get the base address associated with the GPIO port */
-
-  base = lm3s_gpiobaseaddress(port);
-  DEBUGASSERT(base != 0);
-
-  /* The following requires exclusive access to the GPIO registers */
-
-  flags = irqsave();
-
-  /* Enable clocking for this GPIO peripheral. "To use the GPIO, the peripheral
-   * clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn)
-   * in the RCGC2 register."
-   */
-
-  regval = getreg32(LM3S_SYSCON_RCGC2);
-  regval |= SYSCON_RCGC2_GPIO(port);
-  putreg32(regval, LM3S_SYSCON_RCGC2);
-
-  /* First, set the port to digital input.  This is the safest state in which
-   * to perform reconfiguration.
-   */
-
-  lm3s_gpiofunc(base, pinno, &g_funcbits[0]);
-
-  /* Then set up pad strengths and pull-ups.  These setups should be done before
-   * setting up the function because some function settings will over-ride these
-   * user options.
-   */
-
-  lm3s_gpiopadstrength(base, pin, cfgset);
-  lm3s_gpiopadtype(base, pin, cfgset);
-
-  /* Then set up the real pin function */
-
-  lm3s_gpiofunc(base, pinno, &g_funcbits[func]);
-
-  /* Special GPIO digital output pins */
-
-  if (func == 1 || func == 3)
-    {
-      lm3s_initoutput(cfgset);
-    }
-
-
-  /* Special setup for interrupt GPIO pins */
-
-  else if (func == 7)
-    {
-      lm3s_interrupt(base, pin, cfgset);
-    }
-
-  irqrestore(flags);
-  return OK;
-}
-
-/****************************************************************************
- * Name: lm3s_gpiowrite
- *
- * Description:
- *   Write one or zero to the selected GPIO pin
- *
- ****************************************************************************/
-
-void lm3s_gpiowrite(uint32_t pinset, bool value)
-{
-  unsigned int port;
-  unsigned int pinno;
-  uint32_t     base;
-
-  /* Decode the basics */
-
-  port  = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  pinno = (pinset & GPIO_NUMBER_MASK);
-
-  /* Get the base address associated with the GPIO port */
-
-  base  = lm3s_gpiobaseaddress(port);
-
-  /* "The GPIO DATA register is the data register. In software control mode,
-   *  values written in the GPIO DATA register are transferred onto the GPIO
-   *  port pins if the respective pins have been configured as outputs through
-   *  the GPIO Direction (GPIO DIR) register ...
-   *
-   * "In order to write to GPIO DATA, the corresponding bits in the mask,
-   *  resulting from the address bus bits [9:2], must be High. Otherwise, the
-   *  bit values remain unchanged by the write. 
-   *
-   * "... All bits are cleared by a reset."
-   */
-
-  putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
-}
-
-/****************************************************************************
- * Name: lm3s_gpioread
- *
- * Description:
- *   Read one or zero from the selected GPIO pin
- *
- ****************************************************************************/
-
-bool lm3s_gpioread(uint32_t pinset, bool value)
-{
-  unsigned int port;
-  unsigned int pinno;
-  uint32_t     base;
-
-  /* Decode the basics */
-
-  port  = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  pinno = (pinset & GPIO_NUMBER_MASK);
-
-  /* Get the base address associated with the GPIO port */
-
-  base = lm3s_gpiobaseaddress(port);
-
-  /* "... the values read from this register are determined for each bit
-   *  by the mask bit derived from the address used to access the data register,
-   *  bits [9:2]. Bits that are 1 in the address mask cause the corresponding
-   *  bits in GPIODATA to be read, and bits that are 0 in the address mask cause
-   *  the corresponding bits in GPIO DATA to be read as 0, regardless of their
-   *  value.
-   *
-   * "A read from GPIO DATA returns the last bit value written if the respective
-   *  pins are configured as outputs, or it returns the value on the
-   *  corresponding input pin when these are configured as inputs. All bits
-   *  are cleared by a reset."
-   */
-
-  return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
-}
-
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c
deleted file mode 100644
index 511195f2d..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_gpioirq.c
- * arch/arm/src/chip/lm3s_gpioirq.c
- *
- *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <string.h>
-#include <assert.h>
-#include <debug.h>
-
-#include <arch/irq.h>
-
-#include "up_arch.h"
-#include "os_internal.h"
-#include "irq_internal.h"
-
-#include "lm_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/* A table of handlers for each GPIO interrupt */
-
-static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
-
-/* A table that maps a GPIO group to a GPIO base address.  Overly complicated
- * because we support disabling interrupt support for arbitrary ports.  This
- * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h
- */
-
-static const uint32_t g_gpiobase[] =
-{
-#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
-   LM3S_GPIOA_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
-  LM3S_GPIOB_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
-  LM3S_GPIOC_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
-  LM3S_GPIOD_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
-  LM3S_GPIOE_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
-  LM3S_GPIOF_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
-  LM3S_GPIOG_BASE,
-#endif
-
-  /* NOTE: Not all LM3S architectures support GPIOs above GPIOG.  If the chip
-   * does not support these higher ports, then they must be disabled in the
-   * configuration.  Otherwise, the following will likely cause compilation
-   * errors!
-   */
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
-  LM3S_GPIOH_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
-  LM3S_GPIOJ_BASE,
-#endif
-};
-
-#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t))
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_gpiobaseaddress
- *
- * Input:
- *   gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS.
- *
- * Description:
- *   Given a GPIO enumeration value, return the base address of the
- *   associated GPIO registers.  NOTE that range checking was provided by
- *   callee
- *
- ****************************************************************************/
-
-static uint32_t lm3s_gpiobaseaddress(unsigned int gpioirq)
-{
-  unsigned int ndx = gpioirq >> 3;
-  if (ndx < GPIO_NADDRS)
-    {
-      return g_gpiobase[ndx];
-    }
-  return 0;
-}
-
-/****************************************************************************
- * Name: lm3s_gpio*handler
- *
- * Description:
- *   Handle interrupts on each enabled GPIO port
- *
- ****************************************************************************/
-
-static int lm3s_gpiohandler(uint32_t regbase, int irqbase, void *context)
-{
-  uint32_t mis;
-  int irq;
-  int pin;
-
-  /* Handle each pending GPIO interrupt.  "The GPIO MIS register is the masked
-   * interrupt status register. Bits read High in GPIO MIS reflect the status
-   * of input lines triggering an interrupt. Bits read as Low indicate that
-   * either no interrupt has been generated, or the interrupt is masked."
-   */
-
-  mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff;
-
-  /* Clear all GPIO interrupts that we are going to process.  "The GPIO ICR
-   * register is the interrupt clear register. Writing a 1 to a bit in this
-   * register clears the corresponding interrupt edge detection logic register.
-   * Writing a 0 has no effect."
-   */
-
-  putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET);
-
-  /* Now process each IRQ pending in the MIS */
-
-  for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1)
-    {
-      if ((mis & 1) != 0)
-        {
-          irq = irqbase + pin;
-          g_gpioirqvector[irq - NR_IRQS](irq, context);
-        }
-    }
-  return OK;
-}
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
-static int lm3s_gpioahandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
-static int lm3s_gpiobhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
-static int lm3s_gpiochandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
-static int lm3s_gpiodhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
-static int lm3s_gpioehandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
-static int lm3s_gpiofhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
-static int lm3s_gpioghandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
-static int lm3s_gpiohhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
-static int lm3s_gpiojhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context);
-}
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: gpio_irqinitialize
- *
- * Description:
- *   Initialize all vectors to the unexpected interrupt handler
- *
- ****************************************************************************/
-
-int gpio_irqinitialize(void)
-{
-  int i;
-
-  /* Point all interrupt vectors to the unexpected interrupt */
-
-  for (i = 0; i < NR_GPIO_IRQS; i++)
-    {
-      g_gpioirqvector[i] = irq_unexpected_isr;
-    }
-
-  /* Then attach each GPIO interrupt handlers and enable corresponding GPIO
-   * interrupts
-   */
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
-  irq_attach(LM3S_IRQ_GPIOA, lm3s_gpioahandler);
-  up_enable_irq(LM3S_IRQ_GPIOA);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
-  irq_attach(LM3S_IRQ_GPIOB, lm3s_gpiobhandler);
-  up_enable_irq(LM3S_IRQ_GPIOB);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
-  irq_attach(LM3S_IRQ_GPIOC, lm3s_gpiochandler);
-  up_enable_irq(LM3S_IRQ_GPIOC);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
-  irq_attach(LM3S_IRQ_GPIOD, lm3s_gpiodhandler);
-  up_enable_irq(LM3S_IRQ_GPIOD);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
-  irq_attach(LM3S_IRQ_GPIOE, lm3s_gpioehandler);
-  up_enable_irq(LM3S_IRQ_GPIOE);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
-  irq_attach(LM3S_IRQ_GPIOF, lm3s_gpiofhandler);
-  up_enable_irq(LM3S_IRQ_GPIOF);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
-  irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler);
-  up_enable_irq(LM3S_IRQ_GPIOG);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
-  irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler);
-  up_enable_irq(LM3S_IRQ_GPIOH);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
-  irq_attach(LM3S_IRQ_GPIOJ, lm3s_gpiojhandler);
-  up_enable_irq(LM3S_IRQ_GPIOJ);
-#endif
-
-  return OK;
-}
-
-/****************************************************************************
- * Name: gpio_irqattach
- *
- * Description:
- *   Attach in GPIO interrupt to the provide 'isr'
- *
- ****************************************************************************/
-
-int gpio_irqattach(int irq, xcpt_t isr)
-{
-  irqstate_t flags;
-  int        gpioirq = irq - NR_IRQS;
-  int        ret     = ERROR;
-
-  if ((unsigned)gpioirq < NR_GPIO_IRQS)
-    {
-      flags = irqsave();
-
-      /* If the new ISR is NULL, then the ISR is being detached.
-       * In this case, disable the ISR and direct any interrupts
-       * to the unexpected interrupt handler.
-       */
-
-      if (isr == NULL)
-        {
-#ifndef CONFIG_ARCH_NOINTC
-           gpio_irqdisable(gpioirq);
-#endif
-           isr = irq_unexpected_isr;
-        }
-
-      /* Save the new ISR in the table. */
-
-      g_irqvector[gpioirq] = isr;
-      irqrestore(flags);
-      ret = OK;
-    }
-  return ret;
-}
-
-/****************************************************************************
- * Name: gpio_irqenable
- *
- * Description:
- *   Enable the GPIO IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void gpio_irqenable(int irq)
-{
-  irqstate_t flags;
-  int        gpioirq = irq - NR_IRQS;
-  uint32_t   base;
-  uint32_t   regval;
-  int        pin;
-
-  if ((unsigned)gpioirq < NR_GPIO_IRQS)
-    {
-      /* Get the base address of the GPIO module associated with this IRQ */
-
-      base = lm3s_gpiobaseaddress(gpioirq);
-      DEBUGASSERT(base != 0);
-      pin  = (1 << (gpioirq & 7));
-
-      /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
-       * mask register. Bits set to High in GPIO IM allow the corresponding
-       * pins to trigger their individual interrupts and the combined GPIO INTR
-       * line. Clearing a bit disables interrupt triggering on that pin. All
-       * bits are cleared by a reset.
-       */
-
-      flags   = irqsave();
-      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
-      regval |= pin;
-      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
-      irqrestore(flags);
-    }
-}
-
-/****************************************************************************
- * Name: gpio_irqdisable
- *
- * Description:
- *   Disable the GPIO IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void gpio_irqdisable(int irq)
-{
-  irqstate_t flags;
-  int        gpioirq = irq - NR_IRQS;
-  uint32_t   base;
-  uint32_t   regval;
-  int        pin;
-
-  if ((unsigned)gpioirq < NR_GPIO_IRQS)
-    {
-      /* Get the base address of the GPIO module associated with this IRQ */
-
-      base = lm3s_gpiobaseaddress(gpioirq);
-      DEBUGASSERT(base != 0);
-      pin  = (1 << (gpioirq & 7));
-
-      /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
-       * mask register. Bits set to High in GPIO IM allow the corresponding
-       * pins to trigger their individual interrupts and the combined GPIO INTR
-       * line. Clearing a bit disables interrupt triggering on that pin. All
-       * bits are cleared by a reset.
-       */
-
-      flags   = irqsave();
-      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
-      regval &= ~pin;
-      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
-      irqrestore(flags);
-    }
-}
-
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_irq.c b/nuttx/arch/arm/src/lm3s/lm3s_irq.c
deleted file mode 100644
index 2f0b9fa72..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_irq.c
+++ /dev/null
@@ -1,458 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_irq.c
- * arch/arm/src/chip/lm3s_irq.c
- *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <debug.h>
-
-#include <nuttx/irq.h>
-#include <nuttx/arch.h>
-#include <arch/irq.h>
-
-#include "nvic.h"
-#include "up_arch.h"
-#include "os_internal.h"
-#include "up_internal.h"
-
-#include "chip.h"
-#include "lm_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Enable NVIC debug features that are probably only desireable during
- * bringup
- */
-
-#undef LM3S_IRQ_DEBUG
-
-/* Get a 32-bit version of the default priority */
-
-#define DEFPRIORITY32 \
-  (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
-   NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
-   NVIC_SYSH_PRIORITY_DEFAULT << 8  |\
-   NVIC_SYSH_PRIORITY_DEFAULT)
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-volatile uint32_t *current_regs;
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_dumpnvic
- *
- * Description:
- *   Dump some interesting NVIC registers
- *
- ****************************************************************************/
-
-#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
-static void lm3s_dumpnvic(const char *msg, int irq)
-{
-  irqstate_t flags;
-
-  flags = irqsave();
-  slldbg("NVIC (%s, irq=%d):\n", msg, irq);
-  slldbg("  INTCTRL:    %08x VECTAB: %08x\n",
-         getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
-#if 0
-  slldbg("  SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
-         getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
-         getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
-#endif
-  slldbg("  IRQ ENABLE: %08x %08x\n",
-         getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
-  slldbg("  SYSH_PRIO:  %08x %08x %08x\n",
-         getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
-         getreg32(NVIC_SYSH12_15_PRIORITY));
-  slldbg("  IRQ PRIO:   %08x %08x %08x %08x\n", 
-        getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
-        getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
-  slldbg("              %08x %08x %08x %08x\n", 
-        getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
-        getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
-  slldbg("              %08x %08x %08x %08x\n", 
-        getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
-        getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
-  irqrestore(flags);
-}
-#else
-#  define lm3s_dumpnvic(msg, irq)
-#endif
-
-/****************************************************************************
- * Name: lm3s_nmi, lm3s_busfault, lm3s_usagefault, lm3s_pendsv,
- *       lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved
- *
- * Description:
- *   Handlers for various execptions.  None are handled and all are fatal
- *   error conditions.  The only advantage these provided over the default
- *   unexpected interrupt handler is that they provide a diagnostic output.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_DEBUG
-static int lm3s_nmi(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! NMI received\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_busfault(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! Bus fault recived\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_usagefault(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! Usage fault received\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_pendsv(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! PendSV received\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_dbgmonitor(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! Debug Monitor receieved\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_reserved(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! Reserved interrupt\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-#endif
-
-/****************************************************************************
- * Name: lm3s_irqinfo
- *
- * Description:
- *   Given an IRQ number, provide the register and bit setting to enable or
- *   disable the irq.
- *
- ****************************************************************************/
-
-static int lm3s_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
-{
-  DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS);
-
-  /* Check for external interrupt */
-
-  if (irq >= LM3S_IRQ_INTERRUPTS)
-    {
-      if (irq < LM3S_IRQ_INTERRUPTS + 32)
-        {
-           *regaddr = NVIC_IRQ0_31_ENABLE;
-           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS);
-        }
-      else if (irq < NR_IRQS)
-        {
-           *regaddr = NVIC_IRQ32_63_ENABLE;
-           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
-        }
-      else
-        {
-          return ERROR; /* Invalid interrupt */
-        }
-    }
-
-  /* Handler processor exceptions.  Only a few can be disabled */
-
-  else
-    {
-       *regaddr = NVIC_SYSHCON;
-       if (irq == LM3S_IRQ_MEMFAULT)
-        {
-          *bit = NVIC_SYSHCON_MEMFAULTENA;
-        }
-      else if (irq == LM3S_IRQ_BUSFAULT)
-        {
-          *bit = NVIC_SYSHCON_BUSFAULTENA;
-        }
-      else if (irq == LM3S_IRQ_USAGEFAULT)
-        {
-          *bit = NVIC_SYSHCON_USGFAULTENA;
-        }
-      else if (irq == LM3S_IRQ_SYSTICK)
-        {
-          *regaddr = NVIC_SYSTICK_CTRL;
-          *bit = NVIC_SYSTICK_CTRL_ENABLE;
-        }
-      else
-        {
-          return ERROR; /* Invalid or unsupported exception */
-        }
-    }
-
-  return OK;
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_irqinitialize
- ****************************************************************************/
-
-void up_irqinitialize(void)
-{
-  /* Disable all interrupts */
-
-  putreg32(0, NVIC_IRQ0_31_ENABLE);
-  putreg32(0, NVIC_IRQ32_63_ENABLE);
-
-  /* Set all interrrupts (and exceptions) to the default priority */
-
-  putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
-
-  putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
-
-  /* currents_regs is non-NULL only while processing an interrupt */
-
-  current_regs = NULL;
-
-  /* Initialize support for GPIO interrupts if included in this build */
-
-#ifndef CONFIG_LM3S_DISABLE_GPIO_IRQS
-#ifdef CONFIG_HAVE_WEAKFUNCTIONS
-  if (gpio_irqinitialize != NULL)
-#endif
-    {
-      gpio_irqinitialize();
-    }
-#endif
-
-  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
-   * exception is used for performing context switches; The Hard Fault
-   * must also be caught because a SVCall may show up as a Hard Fault
-   * under certain conditions.
-   */
-
-  irq_attach(LM3S_IRQ_SVCALL, up_svcall);
-  irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault);
-
-  /* Set the priority of the SVCall interrupt */
-
-#ifdef CONFIG_ARCH_IRQPRIO
-/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
-#endif
-
-  /* If the MPU is enabled, then attach and enable the Memory Management
-   * Fault handler.
-   */
-
-#ifdef CONFIG_ARMV7M_MPU
-  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
-  up_enable_irq(LM3S_IRQ_MEMFAULT);
-#endif
-
-  /* Attach all other processor exceptions (except reset and sys tick) */
-
-#ifdef CONFIG_DEBUG
-  irq_attach(LM3S_IRQ_NMI, lm3s_nmi);
-#ifndef CONFIG_ARMV7M_MPU
-  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
-#endif
-  irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault);
-  irq_attach(LM3S_IRQ_USAGEFAULT, lm3s_usagefault);
-  irq_attach(LM3S_IRQ_PENDSV, lm3s_pendsv);
-  irq_attach(LM3S_IRQ_DBGMONITOR, lm3s_dbgmonitor);
-  irq_attach(LM3S_IRQ_RESERVED, lm3s_reserved);
-#endif
-
-  lm3s_dumpnvic("initial", NR_IRQS);
-
-#ifndef CONFIG_SUPPRESS_INTERRUPTS
-
-  /* And finally, enable interrupts */
-
-  setbasepri(NVIC_SYSH_PRIORITY_MAX);
-  irqrestore(0);
-#endif
-}
-
-/****************************************************************************
- * Name: up_disable_irq
- *
- * Description:
- *   Disable the IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void up_disable_irq(int irq)
-{
-  uint32_t regaddr;
-  uint32_t regval;
-  uint32_t bit;
-
-  if (lm3s_irqinfo(irq, &regaddr, &bit) == 0)
-    {
-      /* Clear the appropriate bit in the register to enable the interrupt */
-
-      regval  = getreg32(regaddr);
-      regval &= ~bit;
-      putreg32(regval, regaddr);
-    }
-  lm3s_dumpnvic("disable", irq);
-}
-
-/****************************************************************************
- * Name: up_enable_irq
- *
- * Description:
- *   Enable the IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void up_enable_irq(int irq)
-{
-  uint32_t regaddr;
-  uint32_t regval;
-  uint32_t bit;
-
-  if (lm3s_irqinfo(irq, &regaddr, &bit) == 0)
-    {
-      /* Set the appropriate bit in the register to enable the interrupt */
-
-      regval  = getreg32(regaddr);
-      regval |= bit;
-      putreg32(regval, regaddr);
-    }
-  lm3s_dumpnvic("enable", irq);
-}
-
-/****************************************************************************
- * Name: up_maskack_irq
- *
- * Description:
- *   Mask the IRQ and acknowledge it
- *
- ****************************************************************************/
-
-void up_maskack_irq(int irq)
-{
-  up_disable_irq(irq);
-}
-
-/****************************************************************************
- * Name: up_prioritize_irq
- *
- * Description:
- *   Set the priority of an IRQ.
- *
- *   Since this API is not supported on all architectures, it should be
- *   avoided in common implementations where possible.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_IRQPRIO
-int up_prioritize_irq(int irq, int priority)
-{
-  uint32_t regaddr;
-  uint32_t regval;
-  int shift;
-
-  DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
-
-  if (irq < LM3S_IRQ_INTERRUPTS)
-    {
-      irq    -= 4;
-      regaddr = NVIC_SYSH_PRIORITY(irq);
-    }
-  else
-    {
-      irq    -= LM3S_IRQ_INTERRUPTS;
-      regaddr = NVIC_IRQ_PRIORITY(irq);
-    }
-
-  regval      = getreg32(regaddr);
-  shift       = ((irq & 3) << 3);
-  regval     &= ~(0xff << shift);
-  regval     |= (priority << shift);
-  putreg32(regval, regaddr);
-
-  lm3s_dumpnvic("prioritize", irq);
-  return OK;
-}
-#endif
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
deleted file mode 100644
index bdbd5a906..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/**************************************************************************
- * arch/arm/src/lm3s/lm3s_lowputc.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- **************************************************************************/
-
-/**************************************************************************
- * Included Files
- **************************************************************************/
-
-#include <nuttx/config.h>
-#include <stdint.h>
-
-#include <arch/board/board.h>
-
-#include "chip.h"
-#include "up_arch.h"
-#include "up_internal.h"
-
-#include "lm_gpio.h"
-#include "chip/lm_pinmap.h"
-
-#include "lm_lowputc.h"
-
-/**************************************************************************
- * Pre-processor Definitions
- **************************************************************************/
-
-/* Configuration **********************************************************/
-
-#if LM3S_NUARTS < 2
-#  undef  CONFIG_LM3S_UART1
-#  undef  CONFIG_UART1_SERIAL_CONSOLE
-#endif
-
-#if LM3S_NUARTS < 3
-#  undef  CONFIG_LM3S_UART2
-#  undef  CONFIG_UART2_SERIAL_CONSOLE
-#endif
-
-/* Is there a serial console? */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0)
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1)
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2)
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#else
-#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  undef HAVE_CONSOLE
-#endif
-
-/* Select UART parameters for the selected console */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART0_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART0_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART0_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART0_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART0_2STOP
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART1_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART1_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART1_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART1_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART1_2STOP
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART2_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART2_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART2_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART2_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART2_2STOP
-#else
-#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
-#endif
-
-/* Get LCRH settings */
-
-#if LM3S_CONSOLE_BITS == 5
-#  define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
-#elif LM3S_CONSOLE_BITS == 6
-#  define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
-#elif LM3S_CONSOLE_BITS == 7
-#  define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
-#elif LM3S_CONSOLE_BITS == 8
-#  define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
-#else
-#  error "Number of bits not supported"
-#endif
-
-#if LM3S_CONSOLE_PARITY == 0
-#  define UART_LCRH_PARITY (0)
-#elif LM3S_CONSOLE_PARITY == 1
-#  define UART_LCRH_PARITY UART_LCRH_PEN
-#elif LM3S_CONSOLE_PARITY == 2
-#  define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
-#else
-#  error "Invalid parity selection"
-#endif
-
-#if LM3S_CONSOLE_2STOP != 0
-#  define UART_LCRH_NSTOP UART_LCRH_STP2
-#else
-#  define UART_LCRH_NSTOP (0)
-#endif
-
-#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN)
-
-/* Calculate BAUD rate from the SYS clock:
- *
- * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit
- *  fractional part. The number formed by these two values is used by the baud-rate generator
- *  to determine the bit period. Having a fractional baud-rate divider allows the UART to
- *  generate all the standard baud rates.
- *
- * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD)
- *  register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
- *  Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship
- *  to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional
- *  part, separated by a decimal place.):
- *
- *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
- *
- * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number
- *  (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated
- *  by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5
- *  to account for rounding errors:
- *
- *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
- *
- * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred
- *  to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is
- *  used for error detection during receive operations.
- *
- * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and
- *  UARTFBRD registers form an internal 30-bit register. This internal register is only
- *  updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
- *  divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
- */
-
-#define LM3S_BRDDEN     (16 * LM3S_CONSOLE_BAUD)
-#define LM3S_BRDI       (SYSCLK_FREQUENCY / LM3S_BRDDEN)
-#define LM3S_REMAINDER  (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
-#define LM3S_DIVFRAC    ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
-
-/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
- *
- * LM3S_BRDDEN    = (16 * 115,200)                           = 1,843,200
- * LM3S_BRDI      = 50,000,000 / 1,843,200                   = 27
- * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27              = 233,600
- * LM3S_DIVFRAC   = (233,600 * 64 + 921,600) / 1,843,200     = 8
- *
- * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
- */
-
-/**************************************************************************
- * Private Types
- **************************************************************************/
-
-/**************************************************************************
- * Private Function Prototypes
- **************************************************************************/
-
-/**************************************************************************
- * Global Variables
- **************************************************************************/
-
-/**************************************************************************
- * Private Variables
- **************************************************************************/
-
-/**************************************************************************
- * Private Functions
- **************************************************************************/
-
-/**************************************************************************
- * Public Functions
- **************************************************************************/
-
-/**************************************************************************
- * Name: up_lowputc
- *
- * Description:
- *   Output one byte on the serial console
- *
- **************************************************************************/
-
-void up_lowputc(char ch)
-{
-#ifdef HAVE_CONSOLE
-  /* Wait until the TX FIFO is not full */
-
-  while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
-
-  /* Then send the character */
-
-  putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET);
-#endif
-}
-
-/**************************************************************************
- * Name: up_lowsetup
- *
- * Description:
- *   This performs basic initialization of the UART used for the serial
- *   console.  Its purpose is to get the console output availabe as soon
- *   as possible.
- *
- **************************************************************************/
-
-void up_lowsetup(void)
-{
-  uint32_t regval;
-#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
-  uint32_t ctl;
-#endif
-
-  /* Enable the selected UARTs and configure GPIO pins to need by the
-   * the selected UARTs.  NOTE: The serial driver later depends on
-   * this pin configuration -- whether or not a serial console is selected.
-   */
-
-#ifdef CONFIG_LM3S_UART0
-  regval  = getreg32(LM3S_SYSCON_RCGC1);
-  regval |= SYSCON_RCGC1_UART0;
-  putreg32(regval, LM3S_SYSCON_RCGC1);
-
-  lm3s_configgpio(GPIO_UART0_RX);
-  lm3s_configgpio(GPIO_UART0_TX);
-#endif
-
-#ifdef CONFIG_LM3S_UART1
-  regval  = getreg32(LM3S_SYSCON_RCGC1);
-  regval |= SYSCON_RCGC1_UART1;
-  putreg32(regval, LM3S_SYSCON_RCGC1);
-
-  lm3s_configgpio(GPIO_UART1_RX);
-  lm3s_configgpio(GPIO_UART1_TX);
-#endif
-
-  /* Enable the selected console device */
-
-#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
-  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
-
-  ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
-  ctl &= ~UART_CTL_UARTEN;
-  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
-
-  /* Write the integer portion of the BRD to the UART IBRD register */
-
-  putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
-
-  /* Write the fractional portion of the BRD to the UART FBRD register */
-
-  putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
-
-  /* Write the desired serial parameters to the UART LCRH register */
-
-  putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
-
-  /* Enable the UART by setting the UARTEN bit in the UART CTL register */
-
-  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
-  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
-#endif
-
-}
-
-
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_serial.c b/nuttx/arch/arm/src/lm3s/lm3s_serial.c
deleted file mode 100644
index 7ed9b6fa8..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_serial.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_serial.c
- *
- *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include <unistd.h>
-#include <semaphore.h>
-#include <string.h>
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/irq.h>
-#include <nuttx/arch.h>
-#include <nuttx/serial/serial.h>
-
-#include <arch/serial.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
-#include "up_arch.h"
-#include "up_internal.h"
-#include "os_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Some sanity checks *******************************************************/
-
-#if LM3S_NUARTS < 2
-#  undef  CONFIG_LM3S_UART1
-#  undef  CONFIG_UART1_SERIAL_CONSOLE
-#endif
-
-#if LM3S_NUARTS < 3
-#  undef  CONFIG_LM3S_UART2
-#  undef  CONFIG_UART2_SERIAL_CONSOLE
-#endif
-
-/* Is there a UART enabled? */
-
-#if !defined(CONFIG_LM3S_UART0) && !defined(CONFIG_LM3S_UART1) && !defined(CONFIG_LM3S_UART2)
-#  error "No UARTs enabled"
-#endif
-
-/* Is there a serial console? */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0)
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1)
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2)
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#else
-#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  undef HAVE_CONSOLE
-#endif
-
-/* If we are not using the serial driver for the console, then we
- * still must provide some minimal implementation of up_putc.
- */
-
-#ifdef USE_SERIALDRIVER
-
-/* Which UART with be tty0/console and which tty1? */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE)
-#  define CONSOLE_DEV     g_uart0port     /* UART0 is console */
-#  define TTYS0_DEV       g_uart0port     /* UART0 is ttyS0 */
-#  ifdef CONFIG_LM3S_UART1
-#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
-#    else
-#      undef TTYS2_DEV                    /* No ttyS2 */
-#    endif
-#  else
-#    undef TTYS2_DEV                      /* No ttyS2 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
-#    else
-#      undef TTYS1_DEV                    /* No ttyS1 */
-#    endif
-#  endif
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
-#  define CONSOLE_DEV     g_uart1port     /* UART1 is console */
-#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
-#  ifdef CONFIG_LM3S_UART0
-#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
-#    else
-#      undef TTYS2_DEV                    /* No ttyS2 */
-#    endif
-#  else
-#    undef TTYS2_DEV                      /* No ttyS2 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
-#    else
-#      undef TTYS1_DEV                    /* No ttyS1 */
-#    endif
-#  endif
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
-#  define CONSOLE_DEV     g_uart2port     /* UART2 is console */
-#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
-#  ifdef CONFIG_LM3S_UART0
-#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
-#    else
-#      undef TTYS2_DEV                    /* No ttyS2 */
-#    endif
-#  else
-#    undef TTYS2_DEV                      /* No ttyS2 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
-#    else
-#      undef TTYS1_DEV                    /* No ttyS1 */
-#    endif
-#  endif
-#elifdefined(CONFIG_LM3S_UART0)
-#  undef  CONSOLE_DEV                     /* No console device */
-#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
-#  ifdef CONFIG_LM3S_UART1
-#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
-#    else
-#      undef TTYS2_DEV                    /* No ttyS2 */
-#    endif
-#  else
-#    undef TTYS2_DEV                      /* No ttyS2 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
-#    else
-#      undef TTYS1_DEV                    /* No ttyS1 */
-#    endif
-#  endif
-#elifdefined(CONFIG_LM3S_UART1)
-#  undef  CONSOLE_DEV                     /* No console device */
-#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
-#  undef TTYS2_DEV                        /* No ttyS2 */
-#  ifdef CONFIG_LM3S_UART2
-#    define TTYS1_DEV     g_uart2port     /* UART2 is ttyS1 */
-#  else
-#    undef TTYS1_DEV                      /* No ttyS1 */
-#  endif
-#elifdefined(CONFIG_LM3S_UART2)
-#  undef  CONSOLE_DEV                     /* No console device */
-#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
-#  undef  TTYS1_DEV                       /* No ttyS1 */
-#  undef  TTYS2_DEV                       /* No ttyS2 */
-#else
-#  error "No valid TTY devices"
-#  undef  CONSOLE_DEV                     /* No console device */
-#  undef  TTYS0_DEV                       /* No ttyS0 */
-#  undef  TTYS1_DEV                       /* No ttyS1 */
-#  undef  TTYS2_DEV                       /* No ttyS2 */
-#endif
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-struct up_dev_s
-{
-  uint32_t uartbase; /* Base address of UART registers */
-  uint32_t baud;     /* Configured baud */
-  uint32_t im;       /* Saved IM value */
-  uint8_t  irq;      /* IRQ associated with this UART */
-  uint8_t  parity;   /* 0=none, 1=odd, 2=even */
-  uint8_t  bits;     /* Number of bits (7 or 8) */
-  bool    stopbits2; /* true: Configure with 2 stop bits instead of 1 */
-};
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-static int  up_setup(struct uart_dev_s *dev);
-static void up_shutdown(struct uart_dev_s *dev);
-static int  up_attach(struct uart_dev_s *dev);
-static void up_detach(struct uart_dev_s *dev);
-static int  up_interrupt(int irq, void *context);
-static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
-static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
-static void up_rxint(struct uart_dev_s *dev, bool enable);
-static bool up_rxavailable(struct uart_dev_s *dev);
-static void up_send(struct uart_dev_s *dev, int ch);
-static void up_txint(struct uart_dev_s *dev, bool enable);
-static bool up_txready(struct uart_dev_s *dev);
-static bool up_txempty(struct uart_dev_s *dev);
-
-/****************************************************************************
- * Private Variables
- ****************************************************************************/
-
-struct uart_ops_s g_uart_ops =
-{
-  .setup          = up_setup,
-  .shutdown       = up_shutdown,
-  .attach         = up_attach,
-  .detach         = up_detach,
-  .ioctl          = up_ioctl,
-  .receive        = up_receive,
-  .rxint          = up_rxint,
-  .rxavailable    = up_rxavailable,
-  .send           = up_send,
-  .txint          = up_txint,
-  .txready        = up_txready,
-  .txempty        = up_txempty,
-};
-
-/* I/O buffers */
-
-#ifdef CONFIG_LM3S_UART0
-static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
-static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
-#endif
-#ifdef CONFIG_LM3S_UART1
-static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
-static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
-#endif
-#ifdef CONFIG_LM3S_UART2
-static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
-static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
-#endif
-
-/* This describes the state of the LM3S uart0 port. */
-
-#ifdef CONFIG_LM3S_UART0
-static struct up_dev_s g_uart0priv =
-{
-  .uartbase       = LM3S_UART0_BASE,
-  .baud           = CONFIG_UART0_BAUD,
-  .irq            = LM3S_IRQ_UART0,
-  .parity         = CONFIG_UART0_PARITY,
-  .bits           = CONFIG_UART0_BITS,
-  .stopbits2      = CONFIG_UART0_2STOP,
-};
-
-static uart_dev_t g_uart0port =
-{
-  .recv     =
-  {
-    .size   = CONFIG_UART0_RXBUFSIZE,
-    .buffer = g_uart0rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART0_TXBUFSIZE,
-    .buffer = g_uart0txbuffer,
-  },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart0priv,
-};
-#endif
-
-/* This describes the state of the LM3S uart1 port. */
-
-#ifdef CONFIG_LM3S_UART1
-static struct up_dev_s g_uart1priv =
-{
-  .uartbase       = LM3S_UART1_BASE,
-  .baud           = CONFIG_UART1_BAUD,
-  .irq            = LM3S_IRQ_UART1,
-  .parity         = CONFIG_UART1_PARITY,
-  .bits           = CONFIG_UART1_BITS,
-  .stopbits2      = CONFIG_UART1_2STOP,
-};
-
-static uart_dev_t g_uart1port =
-{
-  .recv     =
-  {
-    .size   = CONFIG_UART1_RXBUFSIZE,
-    .buffer = g_uart1rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART1_TXBUFSIZE,
-    .buffer = g_uart1txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart1priv,
-};
-#endif
-
-/* This describes the state of the LM3S uart1 port. */
-
-#ifdef CONFIG_LM3S_UART2
-static struct up_dev_s g_uart2priv =
-{
-  .uartbase       = LM3S_UART2_BASE,
-  .baud           = CONFIG_UART2_BAUD,
-  .irq            = LM3S_IRQ_UART2,
-  .parity         = CONFIG_UART2_PARITY,
-  .bits           = CONFIG_UART2_BITS,
-  .stopbits2      = CONFIG_UART2_2STOP,
-};
-
-static uart_dev_t g_uart2port =
-{
-  .recv     =
-  {
-    .size   = CONFIG_UART2_RXBUFSIZE,
-    .buffer = g_uart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART2_TXBUFSIZE,
-    .buffer = g_uart2txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart2priv,
-};
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_serialin
- ****************************************************************************/
-
-static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
-{
-  return getreg32(priv->uartbase + offset);
-}
-
-/****************************************************************************
- * Name: up_serialout
- ****************************************************************************/
-
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
-{
-  putreg32(value, priv->uartbase + offset);
-}
-
-/****************************************************************************
- * Name: up_disableuartint
- ****************************************************************************/
-
-static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
-{
-  /* Return the current interrupt mask value */
-
-  if (im)
-    {
-      *im = priv->im;
-    }
-
-  /* Disable all interrupts */
-
-  priv->im = 0;
-  up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
-}
-
-/****************************************************************************
- * Name: up_restoreuartint
- ****************************************************************************/
-
-static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
-{
-  priv->im = im;
-  up_serialout(priv, LM3S_UART_IM_OFFSET, im);
-}
-
-/****************************************************************************
- * Name: up_waittxnotfull
- ****************************************************************************/
-
-#ifdef HAVE_CONSOLE
-static inline void up_waittxnotfull(struct up_dev_s *priv)
-{
-  int tmp;
-
-  /* Limit how long we will wait for the TX available condition */
-
-  for (tmp = 1000 ; tmp > 0 ; tmp--)
-    {
-      /* Check Tx FIFO is full */
-
-      if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
-        {
-          /* The Tx FIFO is not full... return */
-
-          break;
-        }
-    }
-
-  /* If we get here, then the wait has timed out and the Tx FIFO remains
-   * full.
-   */
-}
-#endif
-
-/****************************************************************************
- * Name: up_setup
- *
- * Description:
- *   Configure the UART baud, bits, parity, fifos, etc. This
- *   method is called the first time that the serial port is
- *   opened.
- *
- ****************************************************************************/
-
-static int up_setup(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  uint32_t lcrh;
-  uint32_t ctl;
-#ifndef CONFIG_SUPPRESS_UART_CONFIG
-  uint32_t den;
-  uint32_t brdi;
-  uint32_t remainder;
-  uint32_t divfrac;
-
-  /* Note:  The logic here depends on the fact that that the UART module
-   * was enabled and the GPIOs were configured in up_lowsetup().
-   */
-
-  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
-
-  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
-  ctl &= ~UART_CTL_UARTEN;
-  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
-
-  /* Calculate BAUD rate from the SYS clock:
-   *
-   * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer
-   *  and a 6-bit fractional part. The number formed by these two values is
-   *  used by the baud-rate generator to determine the bit period. Having a
-   *  fractional baud-rate divider allows the UART to generate all the standard
-   *  baud rates.
-   *
-   * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor
-   *  (UARTIBRD) register ... and the 6-bit fractional part is loaded with the
-   *  UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate
-   *  divisor (BRD) has the following relationship to the system clock (where
-   *  BRDI is the integer part of the BRD and BRDF is the fractional part,
-   *  separated by a decimal place.):
-   *
-   *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
-   *
-   * "where UARTSysClk is the system clock connected to the UART. The 6-bit
-   *  fractional number (that is to be loaded into the DIVFRAC bit field in the
-   *  UARTFBRD register) can be calculated by taking the fractional part of the
-   *  baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
-   *  rounding errors:
-   *
-   *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
-   *
-   * "The UART generates an internal baud-rate reference clock at 16x the baud-
-   *  rate (referred to as Baud16). This reference clock is divided by 16 to
-   *  generate the transmit clock, and is used for error detection during receive
-   *  operations.
-   *
-   * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the
-   *  UARTIBRD and UARTFBRD registers form an internal 30-bit register. This
-   *  internal register is only updated when a write operation to UARTLCRH is
-   *  performed, so any changes to the baud-rate divisor must be followed by a
-   *  write to the UARTLCRH register for the changes to take effect. ..."
-   */
-
-  den       = priv->baud << 4;
-  brdi      = SYSCLK_FREQUENCY / den;
-  remainder = SYSCLK_FREQUENCY - den * brdi;
-  divfrac   = ((remainder << 6) + (den >> 1)) / den;
-
-  up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
-  up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
-
-  /* Set up the LCRH register */
-
-  lcrh = 0;
-  switch (priv->bits)
-    {
-      case 5:
-        lcrh |= UART_LCRH_WLEN_5BITS;
-        break;
-      case 6:
-        lcrh |= UART_LCRH_WLEN_6BITS;
-        break;
-      case 7:
-        lcrh |= UART_LCRH_WLEN_7BITS;
-        break;
-      case 8:
-      default:
-        lcrh |= UART_LCRH_WLEN_8BITS;
-        break;
-    }
-
-  switch (priv->parity)
-    {
-      case 0:
-      default:
-        break;
-      case 1:
-        lcrh |= UART_LCRH_PEN;
-        break;
-      case 2:
-        lcrh |= UART_LCRH_PEN|UART_LCRH_EPS;
-        break;
-    }
-
-  if (priv->stopbits2)
-    {
-      lcrh |= UART_LCRH_STP2;
-    }
-
-  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
-#endif
-
-  /* Set the UART to interrupt whenever the TX FIFO is almost empty or when
-   * any character is received.
-   */
-
-  up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
-
-  /* Flush the Rx and Tx FIFOs -- How do you do that?*/
-
-  /* Enable Rx interrupts from the UART except for Tx interrupts.  We don't want
-   * Tx interrupts until we have something to send.  We will check for serial
-   * errors as part of Rx interrupt processing (no interrupts will be received
-   * yet because the interrupt is still disabled at the interrupt controller.
-   */
-
-  up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
-
-  /* Enable the FIFOs */
-
-#ifdef CONFIG_SUPPRESS_UART_CONFIG
-  lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
-#endif
-  lcrh |= UART_LCRH_FEN;
-  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
-
-  /* Enable Rx, Tx, and the UART */
-
-#ifdef CONFIG_SUPPRESS_UART_CONFIG
-  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
-#endif
-  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
-  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
-
-  /* Set up the cache IM value */
-
-  priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
-  return OK;
-}
-
-/****************************************************************************
- * Name: up_shutdown
- *
- * Description:
- *   Disable the UART.  This method is called when the serial
- *   port is closed
- *
- ****************************************************************************/
-
-static void up_shutdown(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_disableuartint(priv, NULL);
-}
-
-/****************************************************************************
- * Name: up_attach
- *
- * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
- *   the setup() method is called, however, the serial console may operate in
- *   a non-interrupt driven mode during the boot phase.
- *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
- *
- ****************************************************************************/
-
-static int up_attach(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  int ret;
-
-  /* Attach and enable the IRQ */
-
-  ret = irq_attach(priv->irq, up_interrupt);
-  if (ret == OK)
-    {
-       /* Enable the interrupt (RX and TX interrupts are still disabled
-        * in the UART
-        */
-
-       up_enable_irq(priv->irq);
-    }
-  return ret;
-}
-
-/****************************************************************************
- * Name: up_detach
- *
- * Description:
- *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception is
- *   the serial console which is never shutdown.
- *
- ****************************************************************************/
-
-static void up_detach(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_disable_irq(priv->irq);
-  irq_detach(priv->irq);
-}
-
-/****************************************************************************
- * Name: up_interrupt
- *
- * Description:
- *   This is the UART interrupt handler.  It will be invoked
- *   when an interrupt received on the 'irq'  It should call
- *   uart_transmitchars or uart_receivechar to perform the
- *   appropriate data transfers.  The interrupt handling logic\
- *   must be able to map the 'irq' number into the approprite
- *   uart_dev_s structure in order to call these functions.
- *
- ****************************************************************************/
-
-static int up_interrupt(int irq, void *context)
-{
-  struct uart_dev_s *dev = NULL;
-  struct up_dev_s   *priv;
-  uint32_t           mis;
-  int                passes;
-  bool               handled;
-
-#ifdef CONFIG_LM3S_UART0
-  if (g_uart0priv.irq == irq)
-    {
-      dev = &g_uart0port;
-    }
-  else
-#endif
-#ifdef CONFIG_LM3S_UART1
-  if (g_uart1priv.irq == irq)
-    {
-      dev = &g_uart1port;
-    }
-  else
-#endif
-    {
-      PANIC(OSERR_INTERNAL);
-    }
-  priv = (struct up_dev_s*)dev->priv;
-
-  /* Loop until there are no characters to be transferred or,
-   * until we have been looping for a long time.
-   */
-
-  handled = true;
-  for (passes = 0; passes < 256 && handled; passes++)
-    {
-      handled = false;
-
-      /* Get the masked UART status and clear the pending interrupts. */
-
-       mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
-       up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
-
-      /* Handle incoming, receive bytes (with or without timeout) */
-
-      if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0)
-        {
-           /* Rx buffer not empty ... process incoming bytes */
-
-           uart_recvchars(dev);
-           handled = true;
-        }
-
-      /* Handle outgoing, transmit bytes */
-
-      if ((mis & UART_MIS_TXMIS) != 0)
-        {
-           /* Tx FIFO not full ... process outgoing bytes */
-
-           uart_xmitchars(dev);
-           handled = true;
-        }
-    }
-    return OK;
-}
-
-/****************************************************************************
- * Name: up_ioctl
- *
- * Description:
- *   All ioctl calls will be routed through this method
- *
- ****************************************************************************/
-
-static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
-{
-  struct inode      *inode = filep->f_inode;
-  struct uart_dev_s *dev   = inode->i_private;
-  int                ret    = OK;
-
-  switch (cmd)
-    {
-    case TIOCSERGSTRUCT:
-      {
-         struct up_dev_s *user = (struct up_dev_s*)arg;
-         if (!user)
-           {
-             ret = -EINVAL;
-           }
-         else
-           {
-             memcpy(user, dev, sizeof(struct up_dev_s));
-           }
-       }
-       break;
-
-    default:
-      ret = -ENOTTY;
-      break;
-    }
-
-  return ret;
-}
-
-/****************************************************************************
- * Name: up_receive
- *
- * Description:
- *   Called (usually) from the interrupt level to receive one
- *   character from the UART.  Error bits associated with the
- *   receipt are provided in the return 'status'.
- *
- ****************************************************************************/
-
-static int up_receive(struct uart_dev_s *dev, uint32_t *status)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  uint32_t rxd;
-
-  /* Get the Rx byte + 4 bits of error information.  Return those in status */
-
-  rxd     = up_serialin(priv, LM3S_UART_DR_OFFSET);
-  *status = rxd;
-
-  /* The lower 8bits of the Rx data is the actual recevied byte */
-
-  return rxd & 0xff;
-}
-
-/****************************************************************************
- * Name: up_rxint
- *
- * Description:
- *   Call to enable or disable RX interrupts
- *
- ****************************************************************************/
-
-static void up_rxint(struct uart_dev_s *dev, bool enable)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  if (enable)
-    {
-      /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx
-       * timeout occurs.
-       */
-
-#ifndef CONFIG_SUPPRESS_SERIAL_INTS
-      priv->im |= (UART_IM_RXIM|UART_IM_RTIM);
-#endif
-    }
-  else
-    {
-      priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
-    }
-  up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
-}
-
-/****************************************************************************
- * Name: up_rxavailable
- *
- * Description:
- *   Return true if the receive fifo is not empty
- *
- ****************************************************************************/
-
-static bool up_rxavailable(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
-}
-
-/****************************************************************************
- * Name: up_send
- *
- * Description:
- *   This method will send one byte on the UART
- *
- ****************************************************************************/
-
-static void up_send(struct uart_dev_s *dev, int ch)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
-}
-
-/****************************************************************************
- * Name: up_txint
- *
- * Description:
- *   Call to enable or disable TX interrupts
- *
- ****************************************************************************/
-
-static void up_txint(struct uart_dev_s *dev, bool enable)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  irqstate_t flags;
-
-  flags = irqsave();
-  if (enable)
-    {
-      /* Set to receive an interrupt when the TX fifo is half emptied */
-
-#ifndef CONFIG_SUPPRESS_SERIAL_INTS
-      priv->im |= UART_IM_TXIM;
-      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
-
-      /* The serial driver wants an interrupt here, but will not get get
-       * one unless we "prime the pump."  I believe that this is because
-       * behave like a level interrupt and the LM3S interrupts behave
-       * (at least by default) like edge interrupts.
-       *
-       * In any event, faking a TX interrupt here solves the problem;
-       * Call uart_xmitchars() just as would have been done if we recieved
-       * the TX interrupt.
-       */
-
-      uart_xmitchars(dev);
-#endif
-    }
-  else
-    {
-      /* Disable the TX interrupt */
-
-      priv->im &= ~UART_IM_TXIM;
-      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
-    }
-  irqrestore(flags);
-}
-
-/****************************************************************************
- * Name: up_txready
- *
- * Description:
- *   Return true if the tranmsit fifo is not full
- *
- ****************************************************************************/
-
-static bool up_txready(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
-}
-
-/****************************************************************************
- * Name: up_txempty
- *
- * Description:
- *   Return true if the transmit fifo is empty
- *
- ****************************************************************************/
-
-static bool up_txempty(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_serialinit
- *
- * Description:
- *   Performs the low level UART initialization early in 
- *   debug so that the serial console will be available
- *   during bootup.  This must be called before up_serialinit.
- *
- ****************************************************************************/
-
-void up_earlyserialinit(void)
-{
-  /* NOTE:  All GPIO configuration for the UARTs was performed in
-   * up_lowsetup
-   */
-
-  /* Disable all UARTS */
-
-  up_disableuartint(TTYS0_DEV.priv, NULL);
-#ifdef TTYS1_DEV
-  up_disableuartint(TTYS1_DEV.priv, NULL);
-#endif
-#ifdef TTYS2_DEV
-  up_disableuartint(TTYS2_DEV.priv, NULL);
-#endif
-
-  /* Configuration whichever one is the console */
-
-#ifdef HAVE_CONSOLE
-  CONSOLE_DEV.isconsole = true;
-  up_setup(&CONSOLE_DEV);
-#endif
-}
-
-/****************************************************************************
- * Name: up_serialinit
- *
- * Description:
- *   Register serial console and serial ports.  This assumes
- *   that up_earlyserialinit was called previously.
- *
- ****************************************************************************/
-
-void up_serialinit(void)
-{
-  /* Register the console */
-
-#ifdef HAVE_CONSOLE
-  (void)uart_register("/dev/console", &CONSOLE_DEV);
-#endif
-
-  /* Register all UARTs */
-
-  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
-#ifdef TTYS1_DEV
-  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
-#endif
-#ifdef TTYS2_DEV
-  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
-#endif
-}
-
-/****************************************************************************
- * Name: up_putc
- *
- * Description:
- *   Provide priority, low-level access to support OS debug  writes
- *
- ****************************************************************************/
-
-int up_putc(int ch)
-{
-#ifdef HAVE_CONSOLE
-  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
-  uint32_t im;
-
-  up_disableuartint(priv, &im);
-  up_waittxnotfull(priv);
-  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
-
-  /* Check for LF */
-
-  if (ch == '\n')
-    {
-      /* Add CR */
-
-      up_waittxnotfull(priv);
-      up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r');
-    }
-
-  up_waittxnotfull(priv);
-  up_restoreuartint(priv, im);
-#endif
-  return ch;
-}
-
-#else /* USE_SERIALDRIVER */
-
-/****************************************************************************
- * Name: up_putc
- *
- * Description:
- *   Provide priority, low-level access to support OS debug writes
- *
- ****************************************************************************/
-
-int up_putc(int ch)
-{
-#ifdef HAVE_CONSOLE
-  /* Check for LF */
-
-  if (ch == '\n')
-    {
-      /* Add CR */
-
-      up_lowputc('\r');
-    }
-
-  up_lowputc(ch);
-#endif
-  return ch;
-}
-
-#endif /* USE_SERIALDRIVER */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c
deleted file mode 100644
index 8cd1cee07..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c
+++ /dev/null
@@ -1,1580 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm32/lm3s_ssi.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include <semaphore.h>
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/spi.h>
-
-#include <arch/irq.h>
-#include <arch/board/board.h>
-
-#include "up_internal.h"
-#include "up_arch.h"
-
-#include "chip.h"
-#include "lm_gpio.h"
-#include "lm_ssi.h"
-#include "chip/lm_pinmap.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Enables debug output from this file (needs CONFIG_DEBUG with
- * CONFIG_DEBUG_VERBOSE too)
- */
-
-#undef SSI_DEBUG  /* Define to enable debug */
-
-#ifdef SSI_DEBUG
-#  define ssidbg  lldbg
-#  define ssivdbg llvdbg
-#else
-#  define ssidbg(x...)
-#  define ssivdbg(x...)
-#endif
-
-/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI
- * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in
- * such case, the following must be expanded).
- */
-
-#if LM3S_NSSI == 0
-#  undef CONFIG_SSI0_DISABLE
-#  define CONFIG_SSI0_DISABLE 1
-#  undef CONFIG_SSI1_DISABLE
-#  define CONFIG_SSI1_DISABLE 1
-#elif LM3S_NSSI == 1
-#  undef CONFIG_SSI1_DISABLE
-#  define CONFIG_SSI1_DISABLE 1
-#endif
-
-/* Which SSI modules have been enabled? */
-
-#ifndef CONFIG_SSI0_DISABLE
-#  define SSI0_NDX 0             /* Index to SSI0 in g_ssidev[] */
-#  ifndef CONFIG_SSI1_DISABLE
-#   define SSI1_NDX 1            /* Index to SSI1 in g_ssidev[] */
-#   define NSSI_ENABLED 2        /* Two SSI interfaces: SSI0 & SSI1 */
-#  else
-#   define NSSI_ENABLED 1        /* One SSI interface: SSI0 */
-#   define SSI_BASE          LM3S_SSI0_BASE
-#   define SSI_IRQ           LM3S_IRQ_SSI0
-#  endif
-#else
-#  ifndef CONFIG_SSI1_DISABLE
-#   define SSI1_NDX 0            /* Index to SSI1 in g_ssidev[] */
-#   define NSSI_ENABLED 1        /* One SSI interface: SSI1 */
-#   define SSI_BASE          LM3S_SSI1_BASE
-#   define SSI_IRQ           LM3S_IRQ_SSI1
-#  else
-#   define NSSI_ENABLED 0        /* No SSI interfaces */
-#  endif
-#endif
-
-/* Compile the rest of the file only if at least one SSI interface has been
- * enabled.
- */
-
-#if NSSI_ENABLED > 0
-
-/* The number of (16-bit) words that will fit in the Tx FIFO */
-
-#define LM3S_TXFIFO_WORDS 8
-
-/* Configuration settings */
-
-#ifndef CONFIG_SSI_TXLIMIT
-#  define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2)
-#endif
-
-#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS
-#  error "Invalid range for CONFIG_SSI_TXLIMIT"
-#endif
-
-#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2)
-#  error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
-#endif
-
-/****************************************************************************
- * Private Type Definitions
- ****************************************************************************/
-
-struct lm3s_ssidev_s
-{
-  const struct spi_ops_s *ops;  /* Common SPI operations */
-#ifndef CONFIG_SSI_POLLWAIT
-  sem_t  xfrsem;                /* Wait for transfer to complete */
-#endif
-
-  /* These following are the source and destination buffers of the transfer.
-   * they are retained in this structure so that they will be accessible
-   * from an interrupt handler.  The actual type of the buffer is uint8_t if
-   * nbits <=8 and uint16_t if nbits >8.
-   */
-
-  void  *txbuffer;              /* Source buffer */
-  void  *rxbuffer;              /* Destination buffer */
-
-  /* These are functions pointers that are configured to perform the
-   * appropriate transfer for the particular kind of exchange that is
-   * occurring.  Differnt functions may be selected depending on (1)
-   * if the tx or txbuffer is NULL and depending on the number of bits
-   * per word.
-   */
-
-  void  (*txword)(struct lm3s_ssidev_s *priv);
-  void  (*rxword)(struct lm3s_ssidev_s *priv);
-
-#if NSSI_ENABLED > 1
-  uint32_t base;                /* SSI register base address */
-#endif
-
-  int      ntxwords;            /* Number of words left to transfer on the Tx FIFO */
-  int      nrxwords;            /* Number of words received on the Rx FIFO */
-  int      nwords;              /* Number of words to be exchanged */
-  uint8_t  nbits;               /* Current number of bits per word */
-
-#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
-  uint8_t  irq;                 /* SSI IRQ number */
-#endif
-
-  /* If there is more than one device on the SPI bus, then we have to enforce
-   * mutual exclusion and remember some configuration settings to reduce the
-   * overhead of constant SPI re-configuration.
-   */
-
-#ifndef CONFIG_SPI_OWNBUS
-  sem_t    exclsem;             /* For exclusive access to the SSI bus */
-  uint32_t frequency;           /* Current desired SCLK frequency */
-  uint32_t actual;              /* Current actual SCLK frequency */
-  uint8_t  mode;                /* Current mode 0,1,2,3 */
-#endif
-};
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/* SSI register access */
-
-static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv,
-              unsigned int offset);
-static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset,
-              uint32_t value);
-
-/* Misc helpers */
-
-static uint32_t ssi_disable(struct lm3s_ssidev_s *priv);
-static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable);
-
-#ifndef CONFIG_SSI_POLLWAIT
-static void ssi_semtake(sem_t *sem);
-#define ssi_semgive(s) sem_post(s);
-#endif
-
-/* SSI data transfer */
-
-static void ssi_txnull(struct lm3s_ssidev_s *priv);
-static void ssi_txuint16(struct lm3s_ssidev_s *priv);
-static void ssi_txuint8(struct lm3s_ssidev_s *priv);
-static void ssi_rxnull(struct lm3s_ssidev_s *priv);
-static void ssi_rxuint16(struct lm3s_ssidev_s *priv);
-static void ssi_rxuint8(struct lm3s_ssidev_s *priv);
-static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv);
-static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv);
-#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT)
-static inline int ssi_performtx(struct lm3s_ssidev_s *priv);
-#else
-static int  ssi_performtx(struct lm3s_ssidev_s *priv);
-#endif
-static inline void ssi_performrx(struct lm3s_ssidev_s *priv);
-static int  ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer,
-                         void *rxbuffer, unsigned int nwords);
-
-/* Interrupt handling */
-
-#ifndef CONFIG_SSI_POLLWAIT
-static inline struct lm3s_ssidev_s *ssi_mapirq(int irq);
-static int  ssi_interrupt(int irq, void *context);
-#endif
-
-/* SPI methods */
-
-#ifndef CONFIG_SPI_OWNBUS
-static int  ssi_lock(FAR struct spi_dev_s *dev, bool lock);
-#endif
-static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv,
-              uint32_t frequency);
-static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev,
-              uint32_t frequency);
-static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv,
-              enum spi_mode_e mode);
-static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
-static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits);
-static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits);
-static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd);
-#ifdef CONFIG_SPI_EXCHANGE
-static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
-                         FAR void *rxbuffer, size_t nwords);
-#else
-static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
-              size_t nwords);
-static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
-              size_t nwords);
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/* Common SSI operations */
-
-static const struct spi_ops_s g_spiops =
-{
-#ifndef CONFIG_SPI_OWNBUS
-  .lock         = ssi_lock,
-#endif
-  .select       = lm3s_spiselect,    /* Provided externally by board logic */
-  .setfrequency = ssi_setfrequency,
-  .setmode      = ssi_setmode,
-  .setbits      = ssi_setbits,
-  .status       = lm3s_spistatus,    /* Provided externally by board logic */
-#ifdef CONFIG_SPI_CMDDATA
-  .cmddata      = lm3s_spicmddata,
-#endif
-  .send         = ssi_send,
-#ifdef CONFIG_SPI_EXCHANGE
-  .exchange     = ssi_exchange,
-#else
-  .sndblock     = ssi_sndblock,
-  .recvblock    = ssi_recvblock,
-#endif
-};
-
-/* This supports is up to two SSI busses/ports */
-
-static struct lm3s_ssidev_s g_ssidev[] =
-{
-#ifndef CONFIG_SSI0_DISABLE
-  {
-    .ops  = &g_spiops,
-#if NSSI_ENABLED > 1
-    .base = LM3S_SSI0_BASE,
-#endif
-#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
-    .irq  = LM3S_IRQ_SSI0,
-#endif
-  },
-#endif
-#ifndef CONFIG_SSI1_DISABLE
-  {
-    .ops  = &g_spiops,
-#if NSSI_ENABLED > 1
-    .base = LM3S_SSI1_BASE,
-#endif
-#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
-    .irq  = LM3S_IRQ_SSI1,
-#endif
-  },
-#endif
-};
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: ssi_getreg
- *
- * Description:
- *   Read the SSI register at this offeset
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   offset - Offset to the SSI register from the register base address
- *
- * Returned Value:
- *   Value of the register at this offset
- *
- ****************************************************************************/
-
-static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, unsigned int offset)
-{
-#if NSSI_ENABLED > 1
-  return getreg32(priv->base + offset);
-#else
-  return getreg32(SSI_BASE + offset);
-#endif
-}
-
-/****************************************************************************
- * Name: ssi_putreg
- *
- * Description:
- *   Write the value to the SSI register at this offeset
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   offset - Offset to the SSI register from the register base address
- *   value  - Value to write
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, uint32_t value)
-{
-#if NSSI_ENABLED > 1
-  putreg32(value, priv->base + offset);
-#else
-  putreg32(value, SSI_BASE + offset);
-#endif
-}
-
-/****************************************************************************
- * Name: ssi_disable
- *
- * Description:
- *   Disable SSI operation.  NOTE: The SSI must be disabled before any control
- *   registers can be re-programmed.
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   State of the SSI before the SSE was disabled
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static uint32_t ssi_disable(struct lm3s_ssidev_s *priv)
-{
-  uint32_t retval;
-  uint32_t regval;
-
-  retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
-  regval = (retval & ~SSI_CR1_SSE);
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
-  ssivdbg("CR1: %08x\n", regval);
-  return retval;
-}
-
-/****************************************************************************
- * Name: ssi_enable
- *
- * Description:
- *   Restore the SSI operational state
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   enable - The previous operational state
- *
- * Returned Value:
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable)
-{
-  uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
-  regval &= ~SSI_CR1_SSE;
-  regval  |= (enable & SSI_CR1_SSE);
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
-  ssivdbg("CR1: %08x\n", regval);
-}
-
-/****************************************************************************
- * Name: ssi_semtake
- *
- * Description:
- *   Wait for a semaphore (handling interruption by signals);
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   enable - The previous operational state
- *
- * Returned Value:
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SSI_POLLWAIT
-static void ssi_semtake(sem_t *sem)
-{
-  int ret;
-  do
-    {
-      ret = sem_wait(sem);
-    }
-  while (ret < 0 && errno == EINTR);
-  DEBUGASSERT(ret == 0);
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8
- *
- * Description:
- *   Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer
- *   pointer appropriately.  The selected function dependes on (1) if there
- *   is a source txbuffer provided, and (2) if the number of bits per
- *   word is <=8 or >8.
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static void ssi_txnull(struct lm3s_ssidev_s *priv)
-{
-  ssivdbg("TX: ->0xffff\n");
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff);
-}
-
-static void ssi_txuint16(struct lm3s_ssidev_s *priv)
-{
-  uint16_t *ptr    = (uint16_t*)priv->txbuffer;
-  ssivdbg("TX: %p->%04x\n", ptr, *ptr);
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
-  priv->txbuffer = (void*)ptr;
-}
-
-static void ssi_txuint8(struct lm3s_ssidev_s *priv)
-{
-  uint8_t *ptr   = (uint8_t*)priv->txbuffer;
-  ssivdbg("TX: %p->%02x\n", ptr, *ptr);
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
-  priv->txbuffer = (void*)ptr;
-}
-
-/****************************************************************************
- * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8
- *
- * Description:
- *   Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the
- *   user rxvbuffer and update the rxbuffer pointer appropriately.  The
- *   selected function dependes on (1) if there is a desination rxbuffer
- *   provided, and (2) if the number of bits per word is <=8 or >8.
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static void ssi_rxnull(struct lm3s_ssidev_s *priv)
-{
-#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
-  uint32_t regval  = ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
-  ssivdbg("RX: discard %04x\n", regval);
-#else
-  (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
-#endif
-}
-
-static void ssi_rxuint16(struct lm3s_ssidev_s *priv)
-{
-  uint16_t *ptr    = (uint16_t*)priv->rxbuffer;
-  *ptr           = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
-  ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
-  priv->rxbuffer = (void*)(++ptr);
-}
-
-static void ssi_rxuint8(struct lm3s_ssidev_s *priv)
-{
-  uint8_t *ptr   = (uint8_t*)priv->rxbuffer;
-  *ptr           = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
-  ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
-  priv->rxbuffer = (void*)(++ptr);
-}
-
-/****************************************************************************
- * Name: ssi_txfifofull
- *
- * Description:
- *   Return true if the Tx FIFO is full
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   true: Not full
- *
- ****************************************************************************/
-
-static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv)
-{
-  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
-}
-
-/****************************************************************************
- * Name: ssi_rxfifoempty
- *
- * Description:
- *   Return true if the Rx FIFO is empty
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   true: Not empty
- *
- ****************************************************************************/
-
-static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv)
-{
-  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
-}
-
-/****************************************************************************
- * Name: ssi_performtx
- *
- * Description:
- *   If the Tx FIFO is empty, then transfer as many words as we can to
- *   the FIFO.
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   The number of words written to the Tx FIFO (a value from 0 to 8,
- *   inclusive).
- *
- ****************************************************************************/
-
-#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT)
-static inline int ssi_performtx(struct lm3s_ssidev_s *priv)
-{
-  /* Check if the Tx FIFO is full and more data to transfer */
-
-  if (!ssi_txfifofull(priv) && priv->ntxwords > 0)
-    {
-      /* Transfer one word to the Tx FIFO */
-
-      priv->txword(priv);
-      priv->ntxwords--;
-      return 1;
-    }
-  return 0;
-}
-
-#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */
-
-static int ssi_performtx(struct lm3s_ssidev_s *priv)
-{
-#ifndef CONFIG_SSI_POLLWAIT
-  uint32_t regval;
-#endif
-  int ntxd = 0;  /* Number of words written to Tx FIFO */
-
-  /* Check if the Tx FIFO is full */
-
-  if (!ssi_txfifofull(priv))
-    {
-      /* Not full.. Check if all of the Tx words have been sent */
-
-      if (priv->ntxwords > 0)
-        {
-          /* No.. Transfer more words until either the Tx FIFO is full or
-           * until all of the user provided data has been sent.
-           */
-#ifdef CONFIG_SSI_TXLIMIT
-          /* Further limit the number of words that we put into the Tx
-           * FIFO to CONFIG_SSI_TXLIMIT.  Otherwise, we could
-           * overrun the Rx FIFO on a very fast SSI bus.
-           */
-          for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++)
-#else
-          for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++)
-#endif
-            {
-               priv->txword(priv);
-            }
-
-          /* Update the count of words to to transferred */
-
-          priv->ntxwords -= ntxd;
-        }
-
-      /* Check again... Now have all of the Tx words been sent? */
-
-#ifndef CONFIG_SSI_POLLWAIT
-      regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
-      if (priv->ntxwords > 0)
-        {
-          /* No.. Enable the Tx FIFO interrupt.  This interrupt occurs
-           * when the Tx FIFO is 1/2 full or less.
-           */
-
-#ifdef CONFIG_DEBUG
-          regval |= (SSI_IM_TX|SSI_RIS_ROR);
-#else
-          regval |= SSI_IM_TX;
-#endif
-        }
-      else
-        {
-          /* Yes.. Disable the Tx FIFO interrupt.  The final stages of
-           * the transfer will be driven by Rx FIFO interrupts.
-           */
-
-          regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
-        }
-      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
-#endif /* CONFIG_SSI_POLLWAIT */
-    }
-  return ntxd;
-}
-
-#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */
-
-/****************************************************************************
- * Name: ssi_performrx
- *
- * Description:
- *   Transfer as many bytes as possible from the Rx FIFO to the user Rx
- *   buffer (if one was provided).
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static inline void ssi_performrx(struct lm3s_ssidev_s *priv)
-{
-#ifndef CONFIG_SSI_POLLWAIT
-  uint32_t regval;
-#endif
-
-  /* Loop while data is available in the Rx FIFO */
-
-  while (!ssi_rxfifoempty(priv))
-    {
-      /* Have all of the requested words been transferred from the Rx FIFO? */
-
-      if (priv->nrxwords < priv->nwords)
-        {
-          /* No.. Read more data from Rx FIFO */
-
-          priv->rxword(priv);
-          priv->nrxwords++;
-        }
-    }
-
-  /* The Rx FIFO is now empty.  While there is Tx data to be sent, the
-   * transfer will be driven by Tx FIFO interrupts.  The final part
-   * of the transfer is driven by Rx FIFO interrupts only.
-   */
-
-#ifndef CONFIG_SSI_POLLWAIT
-  regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
-  if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
-    {
-       /* There are no more outgoing words to send, but there are
-        * additional incoming words expected (I would think that this
-        * a real corner case, be we will handle it with an extra 
-        * interrupt, probably an Rx timeout).
-        */
-
-#ifdef CONFIG_DEBUG
-      regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR);
-#else
-      regval |= (SSI_IM_RX|SSI_IM_RT);
-#endif
-    }
-  else
-    {
-      /* No.. there are either more Tx words to send or all Rx words
-       * have received.  Disable Rx FIFO interrupts.
-       */
-
-      regval &= ~(SSI_IM_RX|SSI_IM_RT);
-    }
-  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
-#endif /* CONFIG_SSI_POLLWAIT */
-}
-
-/****************************************************************************
- * Name: ssi_transfer
- *
- * Description:
- *   Exchange a block data with the SPI device
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   txbuffer - The buffer of data to send to the device (may be NULL).
- *   rxbuffer - The buffer to receive data from the device (may be NULL).
- *   nwords   - The total number of words to be exchanged.  If the interface
- *              uses <= 8 bits per word, then this is the number of uint8_t's;
- *              if the interface uses >8 bits per word, then this is the
- *              number of uint16_t's
- *
- * Returned Value:
- *   0: success, <0:Negated error number on failure
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer,
-                        void *rxbuffer, unsigned int nwords)
-{
-#ifndef CONFIG_SSI_POLLWAIT
-  irqstate_t flags;
-#endif
-  int ntxd;
-
-  ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords);
-
-  /* Set up to perform the transfer */
-
-  priv->txbuffer     = (uint8_t*)txbuffer; /* Source buffer */
-  priv->rxbuffer     = (uint8_t*)rxbuffer; /* Destination buffer */
-  priv->ntxwords     = nwords;             /* Number of words left to send */
-  priv->nrxwords     = 0;                  /* Number of words received */
-  priv->nwords       = nwords;             /* Total number of exchanges */
-
-  /* Set up the low-level data transfer function pointers */
-
-  if (priv->nbits > 8)
-    {
-      priv->txword = ssi_txuint16;
-      priv->rxword = ssi_rxuint16;
-    }
-  else
-    {
-      priv->txword = ssi_txuint8;
-      priv->rxword = ssi_rxuint8;
-    }
-
-  if (!txbuffer)
-    {
-      priv->txword = ssi_txnull;
-    }
-
-  if (!rxbuffer)
-    {
-      priv->rxword = ssi_rxnull;
-    }
-
-  /* Prime the Tx FIFO to start the sequence (saves one interrupt).
-   * At this point, all SSI interrupts should be disabled, but the
-   * operation of ssi_performtx() will set up the interrupts
-   * approapriately (if nwords > TxFIFO size).
-   */
-
-#ifndef CONFIG_SSI_POLLWAIT
-  flags = irqsave();
-  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
-          priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
-
-  ntxd  = ssi_performtx(priv);
-
-  /* For the case where nwords < Tx FIFO size, ssi_performrx will
-   * configure interrupts correctly for the final phase of the
-   * the transfer.
-   */
-
-  ssi_performrx(priv);
-
-  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
-          priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
-          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
-
-  /* Wait for the transfer to complete.  Since there is no handshake
-   * with SPI, the following should complete even if there are problems
-   * with the transfer, so it should be safe with no timeout.
-   */
-
-  ssivdbg("Waiting for transfer complete\n");
-  irqrestore(flags);
-  do
-    {
-      ssi_semtake(&priv->xfrsem);
-    }
-  while (priv->nrxwords < priv->nwords);
-  ssidbg("Transfer complete\n");
-
-#else
-  /* Perform the transfer using polling logic.  This will totally
-   * dominate the CPU until the transfer is complete.  Only recommended
-   * if (1) your SPI is very fast, and (2) if you only use very short
-   * transfers.
-   */
-
-  do
-    {
-      /* Handle outgoing Tx FIFO transfers */
-
-      ntxd = ssi_performtx(priv);
-
-      /* Handle incoming Rx FIFO transfers */
-
-      ssi_performrx(priv);
-
-      /* If there are other threads at this same priority level,
-       * the following may help:
-       */
-
-      sched_yield();
-    }
-  while (priv->nrxwords < priv->nwords);
-#endif
-  return OK;
-}
-
-/****************************************************************************
- * Name: ssi_mapirq
- *
- * Description:
- *   Map an IRQ number into the appropriate SSI device
- *
- * Input Parameters:
- *   irq   - The IRQ number to be mapped
- *
- * Returned Value:
- *   On success, a reference to the private data structgure for this IRQ.
- *   NULL on failure.
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SSI_POLLWAIT
-static inline struct lm3s_ssidev_s *ssi_mapirq(int irq)
-{
-  switch (irq)
-    {
-#ifndef CONFIG_SSI0_DISABLE
-      case LM3S_IRQ_SSI0:
-        return &g_ssidev[SSI0_NDX];
-#endif
-#ifndef CONFIG_SSI1_DISABLE
-      case LM3S_IRQ_SSI1:
-        return &g_ssidev[SSI1_NDX];
-#endif
-      default:
-        return NULL;
-    }
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_interrupt
- *
- * Description:
- *   Exchange a block data with the SSI device
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   txbuffer - The buffer of data to send to the device (may be NULL).
- *   rxbuffer - The buffer to receive data from the device (may be NULL).
- *   nwords   - The total number of words to be exchanged.  If the interface
- *              uses <= 8 bits per word, then this is the number of uint8_t's;
- *              if the interface uses >8 bits per word, then this is the
- *              number of uint16_t's
- *
- * Returned Value:
- *   0: success, <0:Negated error number on failure
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SSI_POLLWAIT
-static int ssi_interrupt(int irq, void *context)
-{
-  struct lm3s_ssidev_s *priv = ssi_mapirq(irq);
-  uint32_t regval;
-  int ntxd;
-
-  DEBUGASSERT(priv != NULL);
-
-  /* Clear pending interrupts */
-
-  regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET);
-  ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval);
-
-  /* Check for Rx FIFO overruns */
-
-#ifdef CONFIG_DEBUG
-  if ((regval & SSI_RIS_ROR) != 0)
-    {
-      lldbg("Rx FIFO Overrun!\n");
-    }
-#endif
-
-  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
-          priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
-
-  /* Handle outgoing Tx FIFO transfers */
-
-  ntxd = ssi_performtx(priv);
-
-  /* Handle incoming Rx FIFO transfers */
-
-  ssi_performrx(priv);
-
-  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
-          priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
-          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
-
-  /* Check if the transfer is complete */
-
-  if (priv->nrxwords >= priv->nwords)
-    {
-      /* Yes.. Disable all SSI interrupt sources */
-
-      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
-
-      /* Wake up the waiting thread */
-
-      ssidbg("Transfer complete\n");
-      ssi_semgive(&priv->xfrsem);
-    }
-  return OK;
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_lock
- *
- * Description:
- *   On SPI busses where there are multiple devices, it will be necessary to
- *   lock SPI to have exclusive access to the busses for a sequence of
- *   transfers.  The bus should be locked before the chip is selected. After
- *   locking the SPI bus, the caller should then also call the setfrequency,
- *   setbits, and setmode methods to make sure that the SPI is properly
- *   configured for the device.  If the SPI buss is being shared, then it
- *   may have been left in an incompatible state.
- *
- * Input Parameters:
- *   dev  - Device-specific state data
- *   lock - true: Lock spi bus, false: unlock SPI bus
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SPI_OWNBUS
-static int ssi_lock(FAR struct spi_dev_s *dev, bool lock)
-{
-  FAR struct lm3s_ssidev_s *priv = (FAR struct lm3s_ssidev_s *)dev;
-
-  if (lock)
-    {
-      /* Take the semaphore (perhaps waiting) */
-
-      while (sem_wait(&priv->exclsem) != 0)
-        {
-          /* The only case that an error should occur here is if the wait was awakened
-           * by a signal.
-           */
-
-          ASSERT(errno == EINTR);
-        }
-    }
-  else
-    {
-      (void)sem_post(&priv->exclsem);
-    }
-  return OK;
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_setfrequency
- *
- * Description:
- *   Set the SPI frequency.
- *
- * Input Parameters:
- *   dev -       Device-specific state data
- *   frequency - The SPI frequency requested
- *
- * Returned Value:
- *   Returns the actual frequency selected
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, uint32_t frequency)
-{
-  uint32_t maxdvsr;
-  uint32_t cpsdvsr;
-  uint32_t regval;
-  uint32_t scr;
-  uint32_t actual;
-
-  ssidbg("frequency: %d\n", frequency);
-  DEBUGASSERT(frequency);
-
-  /* Has the frequency changed? */
-
-#ifndef CONFIG_SPI_OWNBUS
-  if (frequency != priv->frequency)
-    {
-#endif
-      /* "The serial bit rate is derived by dividing down the input clock
-       *  (FSysClk). The clock is first divided by an even prescale value
-       *  CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
-       *  (SSI_CPSR) register ... The clock is further divided by a value
-       *  from 1 to 256, which is 1 + SCR, where SCR is the value programmed 
-       *  i n the SSI Control0 (SSICR0) register ...
-       *
-       * "The frequency of the output clock SSIClk is defined by:
-       *
-       *    "SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
-       *
-       * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz,
-       *  the module may not be able to operate at that speed. For master mode,
-       *  the system clock must be at least two times faster than the SSIClk.
-       *  For slave mode, the system clock must be at least 12 times faster
-       *  than the SSIClk."
-       */
-
-      if (frequency > SYSCLK_FREQUENCY/2)
-        {
-          frequency = SYSCLK_FREQUENCY/2;
-        }
-
-      /* Find optimal values for CPSDVSR and SCR.  This loop is inefficient,
-       * but should not have to execute many times.
-       *
-       * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000.
-       *
-       *   maxcvsr = 125
-       *   1. cpsdvsr = 2, scr = 61 -> DONE
-       *
-       *   This would correspond to an actual frequency of:
-       *   50,000,000 / (2 * (62)) = 403,226
-       *
-       * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000.
-       *
-       *   maxcvsr = 2
-       *   1. cpsdvsr = 2, scr = 0 -> DONE
-       *
-       *   This would correspond to an actual frequency of:
-       *   50,000,000 / (2 * (1)) = 25,000,000
-       */
-
-      maxdvsr = SYSCLK_FREQUENCY / frequency;
-      cpsdvsr = 0;
-      do
-        {
-          cpsdvsr += 2;
-          scr = (maxdvsr / cpsdvsr) - 1;
-        }
-      while (scr > 255);
-
-      /* Set CPDVSR */
-
-      DEBUGASSERT(cpsdvsr < 255);
-      ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr);
-
-      /* Set SCR */
-
-      regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
-      regval &= ~SSI_CR0_SCR_MASK;
-      regval |= (scr << SSI_CR0_SCR_SHIFT);
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
-      ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
-
-      /* Calcluate the actual frequency */
-
-      actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1));
-
-      /* Save the frequency selection so that subsequent reconfigurations will be
-       * faster.
-       */
-
-#ifndef CONFIG_SPI_OWNBUS
-      priv->frequency = frequency;
-      priv->actual    = actual;
-    }
-  return priv->actual;
-#else
-  return actual;
-#endif
-}
-
-static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  uint32_t enable;
-  uint32_t actual;
-
-  /* NOTE that the SSI must be disabled when setting any configuration registers. */
-
-  enable = ssi_disable(priv);
-  actual = ssi_setfrequencyinternal(priv, frequency);
-  ssi_enable(priv, enable);
-  return actual;
-}
-
-/****************************************************************************
- * Name: ssi_setmode
- *
- * Description:
- *   Set the SPI mode. Optional.  See enum spi_mode_e for mode definitions
- *
- * Input Parameters:
- *   dev -  Device-specific state data
- *   mode - The SPI mode requested
- *
- * Returned Value:
- *   none
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, enum spi_mode_e mode)
-{
-  uint32_t modebits;
-  uint32_t regval;
-
-  ssidbg("mode: %d\n", mode);
-  DEBUGASSERT(priv);
-
-  /* Has the number of bits per word changed? */
-
-#ifndef CONFIG_SPI_OWNBUS
-  if (mode != priv->mode)
-    {
-#endif
-      /* Select the CTL register bits based on the selected mode */
-
-      switch (mode)
-        {
-        case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
-          modebits = 0;
-          break;
-
-        case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
-          modebits = SSI_CR0_SPH;
-          break;
-
-        case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
-          modebits = SSI_CR0_SPO;
-         break;
-
-        case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
-          modebits = SSI_CR0_SPH|SSI_CR0_SPO;
-          break;
-
-        default:
-          return;
-        }
-
-      /* Then set the selected mode: Freescale SPI format, mode0-3 */
-
-      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
-      regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
-      regval |= modebits;
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
-      ssivdbg("CR0: %08x\n", regval);
-
-      /* Save the mode so that subsequent re-configuratins will be faster */
-
-#ifndef CONFIG_SPI_OWNBUS
-      priv->mode = mode;
-    }
-#endif
-}
-
-static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  uint32_t enable;
-
-  /* NOTE that the SSI must be disabled when setting any configuration registers. */
-
-  enable = ssi_disable(priv);
-  ssi_setmodeinternal(priv, mode);
-  ssi_enable(priv, enable);
-}
-
-/****************************************************************************
- * Name: ssi_setbits
- *
- * Description:
- *   Set the number if bits per word.
- *
- * Input Parameters:
- *   dev -  Device-specific state data
- *   nbits - The number of bits requests
- *
- * Returned Value:
- *   none
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits)
-{
-  uint32_t regval;
-
-  ssidbg("nbits: %d\n", nbits);
-  DEBUGASSERT(priv);
-  if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
-    {
-      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
-      regval &= ~SSI_CR0_DSS_MASK;
-      regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
-      ssivdbg("CR0: %08x\n", regval);
-
-      priv->nbits = nbits;
-    }
-}
-
-static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  uint32_t enable;
-
-  /* NOTE that the SSI must be disabled when setting any configuration registers. */
-
-  enable = ssi_disable(priv);
-  ssi_setbitsinternal(priv, nbits);
-  ssi_enable(priv, enable);
-}
-
-/****************************************************************************
- * Name: ssi_send
- *
- * Description:
- *   Exchange one word on SPI
- *
- * Input Parameters:
- *   dev - Device-specific state data
- *   wd  - The word to send.  the size of the data is determined by the
- *         number of bits selected for the SPI interface.
- *
- * Returned Value:
- *   response
- *
- ****************************************************************************/
-
-static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s*)dev;
-  uint16_t response = 0;
-
-  (void)ssi_transfer(priv, &wd, &response, 1);
-  return response;
-}
-
-/****************************************************************************
- * Name: SPI_EXCHANGE
- *
- * Description:
- *   Exahange a block of data from SPI. Required.
- *
- * Input Parameters:
- *   dev      - Device-specific state data
- *   buffer   - A pointer to the buffer of data to be sent
- *   rxbuffer - A pointer to the buffer in which to recieve data
- *   nwords   - the length of data that to be exchanged in units of words.
- *              The wordsize is determined by the number of bits-per-word
- *              selected for the SPI interface.  If nbits <= 8, the data is
- *              packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifdef CONFIG_SPI_EXCHANGE
-static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
-                         FAR void *rxbuffer, size_t nwords)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords);
-}
-#endif
-
-/*************************************************************************
- * Name: ssi_sndblock
- *
- * Description:
- *   Send a block of data on SPI
- *
- * Input Parameters:
- *   dev -    Device-specific state data
- *   buffer - A pointer to the buffer of data to be sent
- *   nwords - the length of data to send from the buffer in number of words.
- *            The wordsize is determined by the number of bits-per-word
- *            selected for the SPI interface.  If nbits <= 8, the data is
- *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SPI_EXCHANGE
-static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  (void)ssi_transfer(priv, buffer, NULL, nwords);
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_recvblock
- *
- * Description:
- *   Revice a block of data from SPI
- *
- * Input Parameters:
- *   dev -    Device-specific state data
- *   buffer - A pointer to the buffer in which to recieve data
- *   nwords - the length of data that can be received in the buffer in number
- *            of words.  The wordsize is determined by the number of bits-per-word
- *            selected for the SPI interface.  If nbits <= 8, the data is
- *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SPI_EXCHANGE
-static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  (void)ssi_transfer(priv, NULL, buffer, nwords);
-}
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_spiinitialize
- *
- * Description:
- *   Initialize common parts the selected SPI port.  Initialization of
- *   chip select GPIOs must have been performed by board specific logic
- *   prior to calling this function.  Specifically:  GPIOs should have
- *   been configured for output, and all chip selects disabled.
- *
- *   One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select.  However,
- *   If multiple devices on on the bus, then multiple chip selects will be
- *   required.  Theregore, all GPIO chip management is deferred to board-
- *   specific logic.
- *
- * Input Parameter:
- *   Port number (for hardware that has mutiple SSI interfaces)
- *
- * Returned Value:
- *   Valid SPI device structure reference on succcess; a NULL on failure
- *
- ****************************************************************************/
-
-FAR struct spi_dev_s *up_spiinitialize(int port)
-{
-  struct lm3s_ssidev_s *priv;
-  irqstate_t flags;
-  uint8_t regval;
-
-  ssidbg("port: %d\n", port);
- 
-  /* Set up for the selected port */
-
-  flags = irqsave();
-  switch (port)
-    {
-#ifndef CONFIG_SSI0_DISABLE
-    case 0:
-      /* Select SSI0 */
-
-      priv = &g_ssidev[SSI0_NDX];
-
-      /* Enable the SSI0 peripheral */
-
-      regval = getreg32(LM3S_SYSCON_RCGC1);
-      regval |= SYSCON_RCGC1_SSI0;
-      putreg32(regval, LM3S_SYSCON_RCGC1);
-      ssivdbg("RCGC1: %08x\n", regval);
-
-      /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
-       * logic in this file makes no assumptions about chip select)
-       */
-
-      lm3s_configgpio(GPIO_SSI0_CLK);  /* PA2: SSI0 clock (SSI0Clk) */
-   /* lm3s_configgpio(GPIO_SSI0_FSS);     PA3: SSI0 frame (SSI0Fss) */
-      lm3s_configgpio(GPIO_SSI0_RX);   /* PA4: SSI0 receive (SSI0Rx) */
-      lm3s_configgpio(GPIO_SSI0_TX);   /* PA5: SSI0 transmit (SSI0Tx) */
-      break;
-#endif /* CONFIG_SSI0_DISABLE */
-
-#ifndef CONFIG_SSI1_DISABLE
-    case 1:
-      /* Select SSI0 */
-
-      priv = &g_ssidev[SSI1_NDX];
-
-      /* Enable the SSI1 peripheral */
-
-      regval = getreg32(LM3S_SYSCON_RCGC1);
-      regval |= SYSCON_RCGC1_SSI1;
-      putreg32(regval, LM3S_SYSCON_RCGC1);
-      ssivdbg("RCGC1: %08x\n", regval);
-
-      /* Configure SSI1 GPIOs */
-
-      lm3s_configgpio(GPIO_SSI1_CLK);  /* PE0: SSI1 clock (SSI1Clk) */
-   /* lm3s_configgpio(GPIO_SSI1_FSS);     PE1: SSI1 frame (SSI1Fss) */
-      lm3s_configgpio(GPIO_SSI1_RX);   /* PE2: SSI1 receive (SSI1Rx) */
-      lm3s_configgpio(GPIO_SSI1_TX);   /* PE3: SSI1 transmit (SSI1Tx) */
-      break;
-#endif /* CONFIG_SSI1_DISABLE */
-
-    default:
-      irqrestore(flags);
-      return NULL;
-    }
-
-  /* Initialize the state structure */
-
-#ifndef CONFIG_SSI_POLLWAIT
-  sem_init(&priv->xfrsem, 0, 0);
-#endif
-#ifndef CONFIG_SPI_OWNBUS
-  sem_init(&priv->exclsem, 0, 1);
-#endif
-
-  /* Set all CR1 fields to reset state.  This will be master mode. */
-
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0);
-
-  /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
-
-  ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0);
-
-  /* Set the initial mode to mode 0.  The application may override
-   * this initial setting using the setmode() method.
-   */
-
-  ssi_setmodeinternal(priv, SPIDEV_MODE0);
-
-  /* Set the initial data width to 8-bits.  The application may
-   * override this initial setting using the setbits() method.
-   */
-
-  ssi_setbitsinternal(priv, 8);
-
-  /* Pick some initialize clock frequency. 400,000Hz is the startup
-   * MMC/SD frequency used for card detection.  The application may
-   * override this setting using the setfrequency() method.
-   */
-
-  ssi_setfrequencyinternal(priv, 400000);
-
-  /* Disable all SSI interrupt sources.  They will be enabled only
-   * while there is an SSI transfer in progress.
-   */
-
-  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
-
-  /* Attach the interrupt */
-
-#ifndef CONFIG_SSI_POLLWAIT
-#if NSSI_ENABLED > 1
-  irq_attach(priv->irq, (xcpt_t)ssi_interrupt);
-#else
-  irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt);
-#endif
-#endif /* CONFIG_SSI_POLLWAIT */
-
-  /* Enable the SSI for operation */
-
-  ssi_enable(priv, SSI_CR1_SSE);
-
-  /* Enable SSI interrupts (They are still disabled at the source). */
-
-#ifndef CONFIG_SSI_POLLWAIT
-#if NSSI_ENABLED > 1
-  up_enable_irq(priv->irq);
-#else
-  up_enable_irq(SSI_IRQ);
-#endif
-#endif /* CONFIG_SSI_POLLWAIT */
-
-  irqrestore(flags);
-  return (FAR struct spi_dev_s *)priv;
-}
-
-#endif /* NSSI_ENABLED > 0 */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_start.c b/nuttx/arch/arm/src/lm3s/lm3s_start.c
deleted file mode 100644
index 341b82e50..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_start.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_start.c
- * arch/arm/src/chip/lm3s_start.c
- *
- *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <assert.h>
-#include <debug.h>
-
-#include <nuttx/init.h>
-#include <arch/board/board.h>
-
-#include "up_arch.h"
-#include "up_internal.h"
-
-#include "lm_lowputc.h"
-#include "lm_syscontrol.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-extern void lm3s_vectors(void);
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: showprogress
- *
- * Description:
- *   Print a character on the UART to show boot status.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_DEBUG
-#  define showprogress(c) up_lowputc(c)
-#else
-#  define showprogress(c)
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: _start
- *
- * Description:
- *   This is the reset entry point.
- *
- ****************************************************************************/
-
-void __start(void)
-{
-  const uint32_t *src;
-  uint32_t *dest;
-
-  /* Configure the uart so that we can get debug output as soon as possible */
-
-  up_clockconfig();
-  up_lowsetup();
-  showprogress('A');
-
-  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
-   * certain that there are no issues with the state of global variables.
-   */
-
-  for (dest = &_sbss; dest < &_ebss; )
-    {
-      *dest++ = 0;
-    }
-  showprogress('B');
-
-  /* Move the intialized data section from his temporary holding spot in
-   * FLASH into the correct place in SRAM.  The correct place in SRAM is
-   * give by _sdata and _edata.  The temporary location is in FLASH at the
-   * end of all of the other read-only data (.text, .rodata) at _eronly.
-   */
-
-  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
-    {
-      *dest++ = *src++;
-    }
-  showprogress('C');
-
-  /* Perform early serial initialization */
-
-#ifdef USE_EARLYSERIALINIT
-  up_earlyserialinit();
-#endif
-  showprogress('D');
-
-  /* Initialize onboard resources */
-
-  lm3s_boardinitialize();
-  showprogress('E');
-
-  /* Then start NuttX */
-
-  showprogress('\r');
-  showprogress('\n');
-  os_start();
-
-  /* Shoulnd't get here */
-
-  for(;;);
-}
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
deleted file mode 100644
index 3ad0cacb5..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_syscontrol.c
- * arch/arm/src/chip/lm3s_syscontrol.c
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <assert.h>
-#include <debug.h>
-
-#include <nuttx/init.h>
-#include <arch/board/board.h>
-
-#include "up_arch.h"
-#include "up_internal.h"
-#include "chip.h"
-#include "lm_syscontrol.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define RCC_OSCMASK   (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
-#define RCC_XTALMASK  (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN)
-#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2)
-#define RCC_DIVMASK   (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
-#define RCC2_DIVMASK  (SYSCON_RCC2_SYSDIV2_MASK)
-#define FAST_OSCDELAY (512*1024)
-#define SLOW_OSCDELAY (4*1024)
-#define PLLLOCK_DELAY (32*1024)
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_delay
- *
- * Description:
- *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
- *   the time that we wait can be significant and is determined by the previous
- *   clock setting, not the one that we are configuring.
- *
- ****************************************************************************/
-
-static inline void lm3s_delay(uint32_t delay)
-{
-  __asm__ __volatile__("1:\n"
-                       "\tsubs  %0, #1\n"
-                       "\tbne   1b\n"
-                       : "=r"(delay) : "r"(delay));
-}
-
-/****************************************************************************
- * Name: lm3s_oscdelay
- *
- * Description:
- *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
- *   the time that we wait can be significant and is determined by the previous
- *   clock setting, not the one that we are configuring.
- *
- ****************************************************************************/
-
-static inline void lm3s_oscdelay(uint32_t rcc, uint32_t rcc2)
-{
-  /* Wait for the oscillator  to stabilize.  A smaller delay is used if the
-   * current clock rate is very slow.
-   */
-
-  uint32_t delay = FAST_OSCDELAY;
-
-  /* Are we currently using RCC2? */
-
-  if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
-    {
-      uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK;
-      if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) ||
-          (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ))
-        {
-          delay = SLOW_OSCDELAY;
-        }
-    }
-
-  /* No.. using srce in RCC */
-
-  else
-    {
-      uint32_t rccsrc  = rcc  & SYSCON_RCC_OSCSRC_MASK;
-      if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ)
-        {
-          delay = SLOW_OSCDELAY;
-        }
-    }
-
-  /* Then delay that number of loops */
-
-  lm3s_delay(delay);
-}
-
-/****************************************************************************
- * Name: lm3s_plllock
- *
- * Description:
- *   The new RCC values have been selected... wait for the PLL to lock on
- *
- ****************************************************************************/
-
-static inline void lm3s_plllock(void)
-{
-  volatile uint32_t delay;
-
-  /* Loop until the lock is achieved or until a timeout occurs */
-
-  for (delay = PLLLOCK_DELAY; delay > 0; delay--)
-    {
-      /* Check if the PLL is locked on */
-
-      if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
-        {
-          /* Yes.. return now */
-
-          return;
-        }
-    }
-
-  /* If we get here, then PLL lock was not achieved */
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_clockconfig
- *
- * Description:
- *   Called to change to new clock based on desired rcc and rcc2 settings.
- *   This is use to set up the initial clocking but can be used later to
- *   support slow clocked, low power consumption modes.
- *
- ****************************************************************************/
-
-void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2)
-{
-  uint32_t rcc;
-  uint32_t rcc2;
-
-  /* Get the current values of the RCC and RCC2 registers */
-
-  rcc  = getreg32(LM3S_SYSCON_RCC);
-  rcc2 = getreg32(LM3S_SYSCON_RCC2);
-
-  /* Temporarily bypass the PLL and system clock dividers */
-
-  rcc |= SYSCON_RCC_BYPASS;
-  rcc &= ~(SYSCON_RCC_USESYSDIV);
-  putreg32(rcc, LM3S_SYSCON_RCC);
-
-  rcc2 |= SYSCON_RCC2_BYPASS2;
-  putreg32(rcc2, LM3S_SYSCON_RCC2);
-
-  /* We are probably using the main oscillator.  The main oscillator is disabled on
-   * reset and so probably must be enabled here.  The internal oscillator is enabled
-   * on rest and if that is selected, most likely nothing needs to be done.
-   */
-
-  if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) ||
-      ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS)))
-    {
-      /* Enable any selected osciallators (but don't disable any yet) */
-
-      rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
-      putreg32(rcc, LM3S_SYSCON_RCC);
-
-      /* Wait for the newly selected oscillator(s) to settle.  This is tricky because
-       * the time that we wait can be significant and is determined by the previous
-       * clock setting, not the one that we are configuring.
-       */
-
-      lm3s_oscdelay(rcc, rcc2);
-    }
-
-  /* Set the new crystal value, oscillator source and PLL configuration */
-
-  rcc  &= ~RCC_XTALMASK;
-  rcc  |= newrcc & RCC_XTALMASK;
-
-  rcc2 &= ~RCC2_XTALMASK;
-  rcc2 |= newrcc2 & RCC2_XTALMASK;
-
-  /* Clear the PLL lock interrupt */
-
-  putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC);
-
-  /* Write the new RCC/RCC2 values.  Order depends upon whether RCC2 or RCC
-   * is currently enabled.
-   */
-
-  if (rcc2 & SYSCON_RCC2_USERCC2)
-    {
-      putreg32(rcc2, LM3S_SYSCON_RCC2);
-      putreg32(rcc, LM3S_SYSCON_RCC);
-    }
-    else
-    {
-      putreg32(rcc, LM3S_SYSCON_RCC);
-      putreg32(rcc2, LM3S_SYSCON_RCC2);
-    }
-
-  /* Wait for the new crystal value and oscillator source to take effect */
-
-  lm3s_delay(16);
-
-  /* Set the requested system divider and disable the non-selected osciallators */
-
-  rcc &= ~RCC_DIVMASK;
-  rcc |= newrcc & RCC_DIVMASK;
-
-  rcc2 &= ~RCC2_DIVMASK;
-  rcc2 |= newrcc2 & RCC2_DIVMASK;
-
-  /* Will the PLL output be used to clock the system? */
-
-  if ((newrcc & SYSCON_RCC_BYPASS) == 0)
-    {
-      /* Yes, wail untill the PLL is locked */
-
-      lm3s_plllock();
-
-      /* Then enable the PLL */
-
-      rcc  &= ~SYSCON_RCC_BYPASS;
-      rcc2 &= ~SYSCON_RCC2_BYPASS2;
-    }
-
-  /* Now we can set the final RCC/RCC2 values */
-
-  putreg32(rcc, LM3S_SYSCON_RCC);
-  putreg32(rcc2, LM3S_SYSCON_RCC2);
-
-  /* Wait for the system divider to be effective */
-
-  lm3s_delay(6);
-}
-
-/****************************************************************************
- * Name: up_clockconfig
- *
- * Description:
- *   Called early in the bootsequence (before .data and .bss are available)
- *   in order to configure initial clocking.
- *
- ****************************************************************************/
-
-void up_clockconfig(void)
-{
-#ifdef CONFIG_LM3S_REVA2
-  /* Some early silicon returned an increase LDO voltage or 2.75V to work
-   * around a PLL bug
-   */
-
-  putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL);
-#endif
-
-  /* Set the clocking to run with the default settings provided in the board.h
-   * header file
-   */
-
-  lm3s_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE);
-}
-
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c
deleted file mode 100644
index 9cd912249..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm3s/lm3s_timerisr.c
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <time.h>
-#include <debug.h>
-#include <nuttx/arch.h>
-#include <arch/board/board.h>
-
-#include "nvic.h"
-#include "clock_internal.h"
-#include "up_internal.h"
-#include "up_arch.h"
-
-#include "chip.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* The desired timer interrupt frequency is provided by the definition
- * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
- * system clock ticks per second.  That value is a user configurable setting
- * that defaults to 100 (100 ticks per second = 10 MS interval).
- *
- * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h
- * header file.
- */
-
-#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1)
-
-/* The size of the reload field is 24 bits.  Verify taht the reload value
- * will fit in the reload register.
- */
-
-#if SYSTICK_RELOAD > 0x00ffffff
-#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
-#endif
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Global Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function:  up_timerisr
- *
- * Description:
- *   The timer ISR will perform a variety of services for various portions
- *   of the systems.
- *
- ****************************************************************************/
-
-int up_timerisr(int irq, uint32_t *regs)
-{
-   /* Process timer interrupt */
-
-   sched_process_timer();
-   return 0;
-}
-
-/****************************************************************************
- * Function:  up_timerinit
- *
- * Description:
- *   This function is called during start-up to initialize
- *   the timer interrupt.
- *
- ****************************************************************************/
-
-void up_timerinit(void)
-{
-  uint32_t regval;
-
-  /* Set the SysTick interrupt to the default priority */
-
-  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
-  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
-  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
-  putreg32(regval, NVIC_SYSH12_15_PRIORITY);
-
-  /* Configure SysTick to interrupt at the requested rate */
-
-  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
-
-  /* Attach the timer interrupt vector */
-
-  (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr);
-
-  /* Enable SysTick interrupts */
-
-  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
-
-  /* And enable the timer interrupt */
-
-  up_enable_irq(LM3S_IRQ_SYSTICK);
-}
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S
deleted file mode 100644
index 71db122a0..000000000
--- a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S
+++ /dev/null
@@ -1,805 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_vectors.S
- * arch/arm/src/chip/lm3s_vectors.S
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <arch/irq.h>
-
-/************************************************************************************
- * Preprocessor Definitions
- ************************************************************************************/
-
-/* Memory Map:
- *
- * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
- * 0x0002:0000 - Address of vectors if using bootloader
- * 0x0003:ffff - End of flash
- * 0x2000:0000 - Start of SRAM and start of .data (_sdata)
- *             - End of .data (_edata) abd start of .bss (_sbss)
- *             - End of .bss (_ebss) and bottom of idle stack
- *             - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap
- * 0x2000:ffff - End of SRAM and end of heap
- */
-
-#define IDLE_STACK		(_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
-#define HEAP_BASE		(_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
-
-/* The Cortex-M3 return from interrupt is unusual.  We provide the following special
- * address to the BX instruction.  The particular value also forces a return to
- * thread mode and covers state from the main stack point, the MSP (vs. the MSP).
- */
-
-#define EXC_RETURN		0xfffffff9
-
-/************************************************************************************
- * Global Symbols
- ************************************************************************************/
-
-	.globl		__start
-
-	.syntax		unified
-	.thumb
-	.file		"lm3s_vectors.S"
-
-/************************************************************************************
- * Macros
- ************************************************************************************/
-
-/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
- * registers on the stack, then branches to an instantantiation of the following
- * macro.  This macro simply loads the IRQ number into R0, then jumps to the common
- * IRQ handling logic.
- */
-
-	.macro	HANDLER, label, irqno
-	.thumb_func
-\label:
-	mov		r0, #\irqno
-	b		lm3s_irqcommon
-	.endm
-
-/************************************************************************************
- * Vectors
- ************************************************************************************/
-
-	.section	.vectors, "ax"
-	.code		16
-	.align		2
-	.globl		lm3s_vectors
-	.type		lm3s_vectors, function
-
-lm3s_vectors:
-
-/* Processor Exceptions */
-
-	.word	IDLE_STACK			/* Vector  0: Reset stack pointer */
-	.word	__start				/* Vector  1: Reset vector */
-	.word	lm3s_nmi			/* Vector  2: Non-Maskable Interrupt (NMI) */
-	.word	lm3s_hardfault		/* Vector  3: Hard fault */
-	.word	lm3s_mpu			/* Vector  4: Memory management (MPU) */
-	.word	lm3s_busfault		/* Vector  5: Bus fault */
-	.word	lm3s_usagefault		/* Vector  6: Usage fault */
-	.word	lm3s_reserved		/* Vector  7: Reserved */
-	.word	lm3s_reserved		/* Vector  8: Reserved */
-	.word	lm3s_reserved		/* Vector  9: Reserved */
-	.word	lm3s_reserved		/* Vector 10: Reserved */
-	.word	lm3s_svcall			/* Vector 11: SVC call */
-	.word	lm3s_dbgmonitor		/* Vector 12: Debug monitor */
-	.word	lm3s_reserved		/* Vector 13: Reserved */
-	.word	lm3s_pendsv			/* Vector 14: Pendable system service request */
-	.word	lm3s_systick		/* Vector 15: System tick */
-
-/* External Interrupts */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_reserved		/* Vector 25: Reserved */
-	.word	lm3s_reserved		/* Vector 26: Reserved */
-	.word	lm3s_reserved		/* Vector 27: Reserved */
-	.word	lm3s_reserved		/* Vector 28: Reserved */
-	.word	lm3s_reserved		/* Vector 29: Reserved */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
-	.word	lm3s_reserved		/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_gpioh			/* Vector 48: GPIO Port H */
-	.word	lm3s_reserved		/* Vector 49: Reserved */
-	.word	lm3s_ssi1			/* Vector 50: SSI 1 */
-	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
-	.word	lm3s_reserved		/* Vector 54: Reserved */
-	.word	lm3s_reserved		/* Vector 55: Reserved */
-	.word	lm3s_reserved		/* Vector 56: Reserved */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_hib			/* Vector 59: Hibernation Module */
-	.word	lm3s_reserved		/* Vector 60: Reserved */
-	.word	lm3s_reserved		/* Vector 61: Reserved */
-	.word	lm3s_reserved		/* Vector 62: Reserved */
-	.word	lm3s_reserved		/* Vector 63: Reserved */
-	.word	lm3s_reserved		/* Vector 64: Reserved */
-	.word	lm3s_reserved		/* Vector 65: Reserved */
-	.word	lm3s_reserved		/* Vector 66: Reserved */
-	.word	lm3s_reserved		/* Vector 67: Reserved */
-	.word	lm3s_reserved		/* Vector 68: Reserved */
-	.word	lm3s_reserved		/* Vector 69: Reserved */
-	.word	lm3s_reserved		/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_reserved		/* Vector 25: Reserved */
-	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
-	.word	lm3s_reserved		/* Vector 27: Reserved */
-	.word	lm3s_reserved		/* Vector 28: Reserved */
-	.word	lm3s_reserved		/* Vector 29: Reserved */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
-	.word	lm3s_reserved		/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_reserved		/* Vector 48: Reserved */
-	.word	lm3s_reserved		/* Vector 49: Reserved */
-	.word	lm3s_reserved		/* Vector 50: Reserved */
-	.word	lm3s_reserved		/* Vector 51: Reserved */
-	.word	lm3s_reserved		/* Vector 52: Reserved */
-	.word	lm3s_reserved		/* Vector 53: Reserved */
-	.word	lm3s_reserved		/* Vector 54: Reserved */
-	.word	lm3s_reserved		/* Vector 55: Reserved */
-	.word	lm3s_reserved		/* Vector 56: Reserved */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_reserved		/* Vector 59: Reserved */
-	.word	lm3s_reserved		/* Vector 60: Reserved */
-	.word	lm3s_reserved		/* Vector 61: Reserved */
-	.word	lm3s_reserved		/* Vector 62: Reserved */
-	.word	lm3s_reserved		/* Vector 63: Reserved */
-	.word	lm3s_reserved		/* Vector 64: Reserved */
-	.word	lm3s_reserved		/* Vector 65: Reserved */
-	.word	lm3s_reserved		/* Vector 66: Reserved */
-	.word	lm3s_reserved		/* Vector 67: Reserved */
-	.word	lm3s_reserved		/* Vector 68: Reserved */
-	.word	lm3s_reserved		/* Vector 69: Reserved */
-	.word	lm3s_reserved		/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
-	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
-	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
-	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
-	.word	lm3s_qei0			/* Vector 29: QEI0 */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
-	.word	lm3s_reserved		/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_reserved		/* Vector 48: Reserved */
-	.word	lm3s_uart2			/* Vector 49: UART 2 */
-	.word	lm3s_reserved		/* Vector 50: Reserved */
-	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
-	.word	lm3s_qei1			/* Vector 54: QEI1 */
-	.word	lm3s_reserved		/* Vector 55: Reserved */
-	.word	lm3s_reserved		/* Vector 56: Reserved */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_hib			/* Vector 59: Hibernation Module */
-	.word	lm3s_reserved		/* Vector 60: Reserved */
-	.word	lm3s_reserved		/* Vector 61: Reserved */
-	.word	lm3s_reserved		/* Vector 62: Reserved */
-	.word	lm3s_reserved		/* Vector 63: Reserved */
-	.word	lm3s_reserved		/* Vector 64: Reserved */
-	.word	lm3s_reserved		/* Vector 65: Reserved */
-	.word	lm3s_reserved		/* Vector 66: Reserved */
-	.word	lm3s_reserved		/* Vector 67: Reserved */
-	.word	lm3s_reserved		/* Vector 68: Reserved */
-	.word	lm3s_reserved		/* Vector 69: Reserved */
-	.word	lm3s_reserved		/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
-	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
-	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
-	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
-	.word	lm3s_qei0			/* Vector 29: QEI0 */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
-	.word	lm3s_cmp2			/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_gpioh			/* Vector 48: GPIO Port H */
-	.word	lm3s_uart2			/* Vector 49: UART 2 */
-	.word	lm3s_ssi1			/* Vector 50: SSI 1 */
-	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
-	.word	lm3s_qei1			/* Vector 54: QEI1 */
-	.word	lm3s_can0			/* Vector 55: CAN 0 */
-	.word	lm3s_can1			/* Vector 56: CAN 1 */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_reserved		/* Vector 59: Reserved */
-	.word	lm3s_usb			/* Vector 60: USB */
-	.word	lm3s_pwm3			/* Vector 61: PWM 3 */
-	.word	lm3s_udmasoft		/* Vector 62: uDMA Software */
-	.word	lm3s_udmaerror		/* Vector 63: uDMA Error */
-	.word	lm3s_adc1_0			/* Vector 64: ADC1 Sequence 0 */
-	.word	lm3s_adc1_1			/* Vector 65: ADC1 Sequence 1 */
-	.word	lm3s_adc1_2			/* Vector 66: ADC1 Sequence 2 */
-	.word	lm3s_adc1_3			/* Vector 67: ADC1 Sequence 3 */
-	.word	lm3s_i2s0 			/* Vector 68: I2S 0 */
-	.word	lm3s_epi			/* Vector 69: Reserved */
-	.word	lm3s_gpioj			/* Vector 70: GPIO J */
-	.word	lm3s_reserved		/* Vector 71: Reserved */
-	#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
-	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
-	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
-	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
-	.word	lm3s_qei0			/* Vector 29: QEI0 */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_reserved		/* Vector 42: Reserved */
-	.word	lm3s_reserved		/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_reserved		/* Vector 48: Reserved */
-	.word	lm3s_reserved		/* Vector 49: Reserved */
-	.word	lm3s_reserved		/* Vector 50: Reserved */
-	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm3s_reserved		/* Vector 53: Reserved*/
-	.word	lm3s_qei1			/* Vector 54: QEI1 */
-	.word	lm3s_can0			/* Vector 55: Can Controller */
-	.word	lm3s_reserved		/* Vector 56: Reserved */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_hib			/* Vector 59: Hibernation Module */
-	.word	lm3s_reserved		/* Vector 60: Reserved */
-	.word	lm3s_reserved		/* Vector 61: Reserved */
-	.word	lm3s_reserved		/* Vector 62: Reserved */
-	.word	lm3s_reserved		/* Vector 63: Reserved */
-	.word	lm3s_reserved		/* Vector 64: Reserved */
-	.word	lm3s_reserved		/* Vector 65: Reserved */
-	.word	lm3s_reserved		/* Vector 66: Reserved */
-	.word	lm3s_reserved		/* Vector 67: Reserved */
-	.word	lm3s_reserved		/* Vector 68: Reserved */
-	.word	lm3s_reserved		/* Vector 69: Reserved */
-	.word	lm3s_reserved		/* Vector 70: Reserved */
-#else
-#  error "Vectors not specified for this LM3S chip"
-#endif
-	.size	lm3s_vectors, .-lm3s_vectors
-
-/************************************************************************************
- * .text
- ************************************************************************************/
-
-	.text
-	.type	handlers, function
-	.thumb_func
-handlers:
-	HANDLER	lm3s_reserved, LM3S_IRQ_RESERVED		/* Unexpected/reserved vector */
-	HANDLER	lm3s_nmi, LM3S_IRQ_NMI					/* Vector  2: Non-Maskable Interrupt (NMI) */
-	HANDLER	lm3s_hardfault, LM3S_IRQ_HARDFAULT		/* Vector  3: Hard fault */
-	HANDLER	lm3s_mpu, LM3S_IRQ_MEMFAULT				/* Vector  4: Memory management (MPU) */
-	HANDLER	lm3s_busfault, LM3S_IRQ_BUSFAULT		/* Vector  5: Bus fault */
-	HANDLER	lm3s_usagefault, LM3S_IRQ_USAGEFAULT	/* Vector  6: Usage fault */
-	HANDLER	lm3s_svcall, LM3S_IRQ_SVCALL			/* Vector 11: SVC call */
-	HANDLER	lm3s_dbgmonitor, LM3S_IRQ_DBGMONITOR	/* Vector 12: Debug Monitor */
-	HANDLER	lm3s_pendsv, LM3S_IRQ_PENDSV			/* Vector 14: Penable system service request */
-	HANDLER	lm3s_systick, LM3S_IRQ_SYSTICK			/* Vector 15: System tick */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm3s_gpioh, LM3S_IRQ_GPIOH				/* Vector 48: GPIO Port H */
-	HANDLER	lm3s_ssi1, LM3S_IRQ_SSI1				/* Vector 50: SSI 1 */
-	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
- 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
- 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm3s_uart2, LM3S_IRQ_UART1				/* Vector 49: UART 1 */
-	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
- 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm3s_uart2, LM3S_IRQ_UART1				/* Vector 49: UART 1 */
-	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER	lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
-	HANDLER	lm3s_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
- 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm3s_cmp2, LM3S_IRQ_COMPARE2			/* Vector 43: Analog Comparator 2 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm3s_gpioh, LM3S_IRQ_GPIOH				/* Vector 48: GPIO Port H */
-	HANDLER	lm3s_uart2, LM3S_IRQ_UART2				/* Vector 49: UART 2 */
-	HANDLER	lm3s_ssi1, LM3S_IRQ_SSI1				/* Vector 50: GPIO Port H */
-	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER	lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
- 	HANDLER	lm3s_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
-	HANDLER	lm3s_can1, LM3S_IRQ_CAN1				/* Vector 56: CAN 1 */
-	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
- 	HANDLER	lm3s_usb, LM3S_IRQ_USB					/* Vector 60: USB */
- 	HANDLER	lm3s_pwm3, LM3S_IRQ_PWM3				/* Vector 61: PWM 3  */
- 	HANDLER	lm3s_udmasoft, LM3S_IRQ_UDMASOFT		/* Vector 62: uDMA Software  */
- 	HANDLER	lm3s_udmaerror, LM3S_IRQ_UDMAERROR		/* Vector 63: uDMA Error */
- 	HANDLER	lm3s_adc1_0, LM3S_IRQ_ADC1_0			/* Vector 64: ADC1 Sequence 0 */
- 	HANDLER	lm3s_adc1_1, LM3S_IRQ_ADC1_1			/* Vector 65: ADC1 Sequence 1 */
- 	HANDLER	lm3s_adc1_2, LM3S_IRQ_ADC1_2			/* Vector 66: ADC1 Sequence 2 */
- 	HANDLER	lm3s_adc1_3, LM3S_IRQ_ADC1_3			/* Vector 67: ADC1 Sequence 3 */
- 	HANDLER	lm3s_i2s0, LM3S_IRQ_I2S0				/* Vector 68: I2S 0 */
- 	HANDLER	lm3s_epi, LM3S_IRQ_EPI					/* Vector 69: EPI  */
- 	HANDLER	lm3s_gpioj, LM3S_IRQ_GPIOJ				/* Vector 70: GPIO Port J */
-#else
-#  error "Vectors not specified for this LM3S chip"
-#endif
-
-/* Common IRQ handling logic.  On entry here, the return stack is on either
- * the PSP or the MSP and looks like the following:
- *
- *      REG_XPSR
- *      REG_R15
- *      REG_R14
- *      REG_R12
- *      REG_R3
- *      REG_R2
- *      REG_R1
- * MSP->REG_R0
- *
- * And
- *      R0 contains the IRQ number
- *      R14 Contains the EXC_RETURN value
- *      We are in handler mode and the current SP is the MSP
- */
-
-lm3s_irqcommon:
-
-	/* Complete the context save */
-
-#ifdef CONFIG_NUTTX_KERNEL
-	/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
-	 * (handler mode) if the state is on the MSP.  It can only be on the PSP if
-	 * EXC_RETURN is 0xfffffffd (unprivileged thread)
-	 */
-
-	adds	r2, r14, #3				/* If R14=0xfffffffd, then r2 == 0 */
-	ite		ne						/* Next two instructions are condition */
-	mrsne	r1, msp					/* R1=The main stack pointer */
-	mrseq	r1, psp					/* R1=The process stack pointer */
-#else
-	mrs		r1, msp					/* R1=The main stack pointer */
-#endif
-
-	mov		r2, r1					/* R2=Copy of the main/process stack pointer */
-	add		r2, #HW_XCPT_SIZE		/* R2=MSP/PSP before the interrupt was taken */
-	mrs		r3, primask				/* R3=Current PRIMASK setting */
-#ifdef CONFIG_NUTTX_KERNEL 
-	stmdb	r1!, {r2-r11,r14}		/* Save the remaining registers plus the SP value */
-#else
-	stmdb	r1!, {r2-r11}			/* Save the remaining registers plus the SP value */
-#endif
-
-	/* Disable interrupts, select the stack to use for interrupt handling
-	 * and call up_doirq to handle the interrupt
-	 */
-
-	cpsid	i						/* Disable further interrupts */
-
-	/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
-	 * stack pointer.  The way that this is done here prohibits nested interrupts!
-	 * Otherwise, we will re-use the main stack for interrupt level processing.
-	 */
-
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
-	ldr		sp, =g_intstackbase
-	str		r1, [sp, #-4]!			/* Save the MSP on the interrupt stack */
-	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */
-	ldr		r1, [sp, #+4]!			/* Recover R1=main stack pointer */
-#else
-	mov		sp, r1					/* We are using the main stack pointer */
-	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */
-	mov		r1, sp					/* Recover R1=main stack pointer */
-#endif
-
-	/* On return from up_doirq, R0 will hold a pointer to register context
-	 * array to use for the interrupt return.  If that return value is the same
-	 * as current stack pointer, then things are relatively easy.
-	 */
-
-	cmp		r0, r1					/* Context switch? */
-	beq		1f						/* Branch if no context switch */
-
-	/* We are returning with a pending context switch.  This case is different
-	 * because in this case, the register save structure does not lie on the
-	 * stack but, rather, are within a TCB structure.  We'll have to copy some
-	 * values to the stack.
-	 */
-
-	add		r1, r0, #SW_XCPT_SIZE	/* R1=Address of HW save area in reg array */
-	ldmia	r1, {r4-r11}			/* Fetch eight registers in HW save area */
-	ldr		r1, [r0, #(4*REG_SP)]	/* R1=Value of SP before interrupt */
-	stmdb	r1!, {r4-r11}			/* Store eight registers in HW save area */
-#ifdef CONFIG_NUTTX_KERNEL 
-	ldmia	r0, {r2-r11,r14}		/* Recover R4-R11, r14 + 2 temp values */
-#else
-	ldmia	r0, {r2-r11}			/* Recover R4-R11 + 2 temp values */
-#endif
-	b		2f						/* Re-join common logic */
-
-	/* We are returning with no context switch.  We simply need to "unwind"
-	 * the same stack frame that we created
-	 */
-1:
-#ifdef CONFIG_NUTTX_KERNEL 
-	ldmia	r1!, {r2-r11,r14}		/* Recover R4-R11, r14 + 2 temp values */
-#else
-	ldmia	r1!, {r2-r11}			/* Recover R4-R11 + 2 temp values */
-#endif
-2:
-#ifdef CONFIG_NUTTX_KERNEL
-	/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
-	 * (handler mode) if the state is on the MSP.  It can only be on the PSP if
-	 * EXC_RETURN is 0xfffffffd (unprivileged thread)
-	 */
-
-	adds	r0, r14, #3				/* If R14=0xfffffffd, then r0 == 0 */
-	ite		ne						/* Next two instructions are condition */
-	msrne	msp, r1					/* R1=The main stack pointer */
-	msreq	psp, r1					/* R1=The process stack pointer */
-#else
-	msr		msp, r1					/* Recover the return MSP value */
-
-	/* Preload r14 with the special return value first (so that the return
-	 * actually occurs with interrupts still disabled).
-	 */
-
-	ldr		r14, =EXC_RETURN		/* Load the special value */
-#endif
-
-    /* Restore the interrupt state */
-
-	msr		primask, r3				/* Restore interrupts */
-
-	/* Always return with R14 containing the special value that will: (1)
-	 * return to thread mode, and (2) continue to use the MSP
-	 */
-
-	bx		r14						/* And return */
-	.size	handlers, .-handlers
-
-/************************************************************************************
- *  Name: up_interruptstack/g_intstackbase
- *
- * Description:
- *   Shouldn't happen
- *
- ************************************************************************************/
-
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
-	.bss
-	.global	g_intstackbase
-	.align	4
-up_interruptstack:
-	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
-g_intstackbase:
-	.size	up_interruptstack, .-up_interruptstack
-#endif
-
-/************************************************************************************
- * .rodata
- ************************************************************************************/
-
-	.section	.rodata, "a"
-
-/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
- * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
- * and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE thread is the thread that
- * the system boots on and, eventually, becomes the idle, do nothing task that runs
- * only when there is nothing else to run.  The heap continues from there until the
- * end of memory.  See g_heapbase below.
- */
-
-	.globl	g_heapbase
-	.type	g_heapbase, object
-g_heapbase:
-	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
-	.size	g_heapbase, .-g_heapbase
-
-	.end
diff --git a/nuttx/arch/arm/src/lm3s/lm_ethernet.h b/nuttx/arch/arm/src/lm3s/lm_ethernet.h
deleted file mode 100644
index 600955b95..000000000
--- a/nuttx/arch/arm/src/lm3s/lm_ethernet.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm_ethernet.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H
-#define __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-
-#if LM3S_NETHCONTROLLERS > 1
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Function: lm3s_ethinitialize
- *
- * Description:
- *   Initialize the Ethernet driver for one interface.  If the LM3S chip
- *   supports multiple Ethernet controllers, then bould specific logic
- *   must implement up_netinitialize() and call this function to initialize
- *   the desiresed interfaces.
- *
- * Parameters:
- *   None
- *
- * Returned Value:
- *   OK on success; Negated errno on failure.
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-int lm3s_ethinitialize(int intf);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* LM3S_NETHCONTROLLERS > 1 */
-#endif /* __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm_gpio.h b/nuttx/arch/arm/src/lm3s/lm_gpio.h
deleted file mode 100644
index 1bfb79fc9..000000000
--- a/nuttx/arch/arm/src/lm3s/lm_gpio.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm_gpio.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM_GPIO_H
-#define __ARCH_ARM_SRC_LM3S_LM_GPIO_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "up_internal.h"
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Bit-encoded input to lm3s_configgpio() *******************************************/
-
-/* Encoding:
- * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB
- *
- * These bits set the primary function of the pin:
- * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn
- */
-
-#define GPIO_FUNC_SHIFT               29                         /* Bit 31-29: GPIO function */
-#define GPIO_FUNC_MASK                (7 << GPIO_FUNC_SHIFT)     /* (See table 9-1 in data sheet) */
-#define GPIO_FUNC_INPUT               (0 << GPIO_FUNC_SHIFT)     /*   Digital GPIO input */
-#define GPIO_FUNC_OUTPUT              (1 << GPIO_FUNC_SHIFT)     /*   Digital GPIO output */
-#define GPIO_FUNC_ODINPUT             (2 << GPIO_FUNC_SHIFT)     /*   Open-drain GPIO input */
-#define GPIO_FUNC_ODOUTPUT            (3 << GPIO_FUNC_SHIFT)     /*   Open-drain GPIO output */
-#define GPIO_FUNC_PFODIO              (4 << GPIO_FUNC_SHIFT)     /*   Open-drain input/output (I2C) */
-#define GPIO_FUNC_PFINPUT             (5 << GPIO_FUNC_SHIFT)     /*   Digital input (Timer, CCP) */
-#define GPIO_FUNC_PFOUTPUT            (5 << GPIO_FUNC_SHIFT)     /*   Digital output (Timer, PWM, Comparator) */
-#define GPIO_FUNC_PFIO                (5 << GPIO_FUNC_SHIFT)     /*   Digital input/output (SSI, UART) */
-#define GPIO_FUNC_ANINPUT             (6 << GPIO_FUNC_SHIFT)     /*   Analog input (Comparator) */
-#define GPIO_FUNC_INTERRUPT           (7 << GPIO_FUNC_SHIFT)     /*   Interrupt function */
-#define GPIO_FUNC_MAX                 GPIO_FUNC_INTERRUPT
-
-/* That primary may be modified by the following options
- * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn
- */
-
-#define GPIO_STRENGTH_SHIFT           27                         /* Bits 28-27: Pad drive strength */
-#define GPIO_STRENGTH_MASK            (3 << GPIO_STRENGTH_SHIFT)
-#define GPIO_STRENGTH_2MA             (0 << GPIO_STRENGTH_SHIFT) /*   2mA pad drive strength */
-#define GPIO_STRENGTH_4MA             (1 << GPIO_STRENGTH_SHIFT) /*   4mA pad drive strength */
-#define GPIO_STRENGTH_8MA             (2 << GPIO_STRENGTH_SHIFT) /*   8mA pad drive strength */
-#define GPIO_STRENGTH_8MASC           (3 << GPIO_STRENGTH_SHIFT) /*   8mA Pad drive with slew rate control */
-#define GPIO_STRENGTH_MAX             GPIO_STRENGTH_8MASC
-
-#define GPIO_PADTYPE_SHIFT            24                         /* Bits 26-24: Pad type */
-#define GPIO_PADTYPE_MASK             (7 << GPIO_PADTYPE_SHIFT)
-#define GPIO_PADTYPE_STD              (0 << GPIO_PADTYPE_SHIFT)  /*   Push-pull */
-#define GPIO_PADTYPE_STDWPU           (1 << GPIO_PADTYPE_SHIFT)  /*   Push-pull with weak pull-up */
-#define GPIO_PADTYPE_STDWPD           (2 << GPIO_PADTYPE_SHIFT)  /*   Push-pull with weak pull-down */
-#define GPIO_PADTYPE_OD               (3 << GPIO_PADTYPE_SHIFT)  /*   Open-drain */
-#define GPIO_PADTYPE_ODWPU            (4 << GPIO_PADTYPE_SHIFT)  /*   Open-drain with weak pull-up */
-#define GPIO_PADTYPE_ODWPD            (5 << GPIO_PADTYPE_SHIFT)  /*   Open-drain with weak pull-down */
-#define GPIO_PADTYPE_ANALOG           (6 << GPIO_PADTYPE_SHIFT)  /*   Analog comparator */
-
-/* If the pin is an interrupt, then the following options apply
- * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn
- */
-
-#define GPIO_INT_SHIFT                21                         /* Bits 23-21: Interrupt type */
-#define GPIO_INT_MASK                 (7 << GPIO_INT_SHIFT)
-#define GPIO_INT_FALLINGEDGE          (0 << GPIO_INT_SHIFT)      /*   Interrupt on falling edge */
-#define GPIO_INT_RISINGEDGE           (1 << GPIO_INT_SHIFT)      /*   Interrupt on rising edge */
-#define GPIO_INT_BOTHEDGES            (2 << GPIO_INT_SHIFT)      /*   Interrupt on both edges */
-#define GPIO_INT_LOWLEVEL             (3 << GPIO_INT_SHIFT)      /*   Interrupt on low level */
-#define GPIO_INT_HIGHLEVEL            (4 << GPIO_INT_SHIFT)      /*   Interrupt on high level */
-
-/* If the pin is an GPIO digital output, then this identifies the initial output value:
- * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn
- */
-
-#define GPIO_VALUE_SHIFT              7                          /* Bit 7: If output, inital value of output */
-#define GPIO_VALUE_MASK               (1 << GPIO_VALUE_SHIFT)
-#define GPIO_VALUE_ZERO               (0 << GPIO_VALUE_SHIFT)    /*   Initial value is zero */
-#define GPIO_VALUE_ONE                (1 << GPIO_VALUE_SHIFT)    /*   Initial value is one */
-
-/* This identifies the GPIO port
- * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn
- */
-
-#define GPIO_PORT_SHIFT               3                          /* Bit 3-6:  Port number */
-#define GPIO_PORT_MASK                (15 << GPIO_PORT_SHIFT)
-#define GPIO_PORTA                    (0 << GPIO_PORT_SHIFT)     /*   GPIOA */
-#define GPIO_PORTB                    (1 << GPIO_PORT_SHIFT)     /*   GPIOB */
-#define GPIO_PORTC                    (2 << GPIO_PORT_SHIFT)     /*   GPIOC */
-#define GPIO_PORTD                    (3 << GPIO_PORT_SHIFT)     /*   GPIOD */
-#define GPIO_PORTE                    (4 << GPIO_PORT_SHIFT)     /*   GPIOE */
-#define GPIO_PORTF                    (5 << GPIO_PORT_SHIFT)     /*   GPIOF */
-#define GPIO_PORTG                    (6 << GPIO_PORT_SHIFT)     /*   GPIOG */
-#define GPIO_PORTH                    (7 << GPIO_PORT_SHIFT)     /*   GPIOH */
-#define GPIO_PORTJ                    (8 << GPIO_PORT_SHIFT)     /*   GPIOJ */
-
-/* This identifies the bit in the port:
- * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB
- */
-
-#define GPIO_NUMBER_SHIFT             0                           /* Bits 0-2: GPIO number: 0-7 */
-#define GPIO_NUMBER_MASK              (7 << GPIO_NUMBER_SHIFT)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_configgpio
- *
- * Description:
- *   Configure a GPIO pin based on bit-encoded description of the pin.
- *
- ****************************************************************************/
-
-int lm3s_configgpio(uint32_t cfgset);
-
-/****************************************************************************
- * Name: lm3s_gpiowrite
- *
- * Description:
- *   Write one or zero to the selected GPIO pin
- *
- ****************************************************************************/
-
-void lm3s_gpiowrite(uint32_t pinset, bool value);
-
-/****************************************************************************
- * Name: lm3s_gpioread
- *
- * Description:
- *   Read one or zero from the selected GPIO pin
- *
- ****************************************************************************/
-
-bool lm3s_gpioread(uint32_t pinset, bool value);
-
-/****************************************************************************
- * Function:  lm3s_dumpgpio
- *
- * Description:
- *   Dump all GPIO registers associated with the provided base address
- *
- ****************************************************************************/
-
-int lm3s_dumpgpio(uint32_t pinset, const char *msg);
-
-/****************************************************************************
- * Name: gpio_irqinitialize
- *
- * Description:
- *   Initialize all vectors to the unexpected interrupt handler
- *
- ****************************************************************************/
-
-int weak_function gpio_irqinitialize(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_LM3S_LM_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm_lowputc.h b/nuttx/arch/arm/src/lm3s/lm_lowputc.h
deleted file mode 100644
index 8e2858ebf..000000000
--- a/nuttx/arch/arm/src/lm3s/lm_lowputc.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_lowputc.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H
-#define __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_lowsetup
- *
- * Description:
- *   Called at the very beginning of _start.  Performs low level initialization.
- *
- ****************************************************************************/
-
-void up_lowsetup(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm_ssi.h b/nuttx/arch/arm/src/lm3s/lm_ssi.h
deleted file mode 100644
index dd1e30817..000000000
--- a/nuttx/arch/arm/src/lm3s/lm_ssi.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm_ssi.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM_SSI_H
-#define __ARCH_ARM_SRC_LM3S_LM_SSI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * The external functions, lm3s_spiselect, lm3s_spistatus, and
- * lm3s_spicmddata must be provided by board-specific logic.  These are
- * implementations of the select, status, and cmddata methods of the SPI
- * interface defined by struct spi_ops_s (see include/nuttx/spi.h).
- * All other methods (including up_spiinitialize()) are provided by common
- * logic.  To use this common SPI logic on your board:
- *
- *   1. Provide logic in lm3s_boardinitialize() to configure SPI chip select
- *      pins.
- *   2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
- *      board-specific logic.  These functions will perform chip selection and
- *      status operations using GPIOs in the way your board is configured.
- *   3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide
- *      the lm3s_spicmddata() function in your board-specific logic.  This
- *      functions will perform cmd/data selection operations using GPIOs in
- *      the way your board is configured.
- *   4. Add a call to up_spiinitialize() in your low level application
- *      initialization logic
- *   5. The handle returned by up_spiinitialize() may then be used to bind the
- *      SPI driver to higher level logic (e.g., calling 
- *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
- *      the SPI MMC/SD driver).
- *
- ****************************************************************************/
-
-struct spi_dev_s;
-enum spi_dev_e;
-void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-#ifdef CONFIG_SPI_CMDDATA
-int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
-#endif
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_LM3S_LM_SSI_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm_syscontrol.h
deleted file mode 100644
index 7c49da565..000000000
--- a/nuttx/arch/arm/src/lm3s/lm_syscontrol.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm3s/lm3s_syscontrol.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H
-#define __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_clockconfig
- *
- * Description:
- *   Called to change to new clock based on desired rcc and rcc2 settings.
- *   This is use to set up the initial clocking but can be used later to
- *   support slow clocked, low power consumption modes.
- *
- ****************************************************************************/
-
-void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2);
-
-/****************************************************************************
- * Name: up_clockconfig
- *
- * Description:
- *   Called early in the bootsequence (before .data and .bss are available)
- *   in order to configure initial clocking.
- *
- ****************************************************************************/
-
-void up_clockconfig(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H */
diff --git a/nuttx/configs/eagle100/README.txt b/nuttx/configs/eagle100/README.txt
index a79ac2b2d..3f9da652b 100644
--- a/nuttx/configs/eagle100/README.txt
+++ b/nuttx/configs/eagle100/README.txt
@@ -273,7 +273,7 @@ Eagle100-specific Configuration Options
 
     CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
 
-       CONFIG_ARCH_CHIP=lm3s
+       CONFIG_ARCH_CHIP=lm
 
     CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
        chip:
@@ -371,7 +371,7 @@ Eagle100-specific Configuration Options
       to build the LM3S Ethernet driver
     CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
-      a MAC address (via lm3s_ethernetmac()), then this should be selected.
+      a MAC address (via lm_ethernetmac()), then this should be selected.
     CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
     CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
     CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
diff --git a/nuttx/configs/eagle100/httpd/defconfig b/nuttx/configs/eagle100/httpd/defconfig
index c2ea86bed..cf4f97930 100644
--- a/nuttx/configs/eagle100/httpd/defconfig
+++ b/nuttx/configs/eagle100/httpd/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
diff --git a/nuttx/configs/eagle100/nettest/defconfig b/nuttx/configs/eagle100/nettest/defconfig
index 2dab94846..a3b50ead6 100644
--- a/nuttx/configs/eagle100/nettest/defconfig
+++ b/nuttx/configs/eagle100/nettest/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
diff --git a/nuttx/configs/eagle100/nsh/defconfig b/nuttx/configs/eagle100/nsh/defconfig
index fd141bc80..342023d6a 100644
--- a/nuttx/configs/eagle100/nsh/defconfig
+++ b/nuttx/configs/eagle100/nsh/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
diff --git a/nuttx/configs/eagle100/nxflat/defconfig b/nuttx/configs/eagle100/nxflat/defconfig
index 20cd50432..fe02ab4b9 100644
--- a/nuttx/configs/eagle100/nxflat/defconfig
+++ b/nuttx/configs/eagle100/nxflat/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig
index 01f3be334..52496c4a3 100644
--- a/nuttx/configs/eagle100/ostest/defconfig
+++ b/nuttx/configs/eagle100/ostest/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
diff --git a/nuttx/configs/eagle100/thttpd/defconfig b/nuttx/configs/eagle100/thttpd/defconfig
index 460bd64b3..7efbbed11 100644
--- a/nuttx/configs/eagle100/thttpd/defconfig
+++ b/nuttx/configs/eagle100/thttpd/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6918=y
 CONFIG_ARCH_BOARD="eagle100"
diff --git a/nuttx/configs/ekk-lm3s9b96/README.txt b/nuttx/configs/ekk-lm3s9b96/README.txt
index d331c1cd5..f7896118e 100644
--- a/nuttx/configs/ekk-lm3s9b96/README.txt
+++ b/nuttx/configs/ekk-lm3s9b96/README.txt
@@ -173,13 +173,13 @@ IDEs
   2) Start the NuttX build at least one time from the Cygwin command line
      before trying to create your project.  This is necessary to create
      certain auto-generated files and directories that will be needed.
-  3) Set up include pathes:  You will need include/, arch/arm/src/lm3s,
+  3) Set up include pathes:  You will need include/, arch/arm/src/lm,
      arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
   4) All assembly files need to have the definition option -D __ASSEMBLY__
      on the command line.
 
   Startup files will probably cause you some headaches.  The NuttX startup file
-  is arch/arm/src/lm3s/lm3s_vectors.S.
+  is arch/arm/src/lm/lm_vectors.S.
 
 NuttX EABI "buildroot" Toolchain
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -294,7 +294,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
 
     CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
 
-       CONFIG_ARCH_CHIP=lm3s
+       CONFIG_ARCH_CHIP=lm
 
     CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
        chip:
@@ -389,7 +389,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
       to build the LM3S Ethernet driver
     CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
-      a MAC address (via lm3s_ethernetmac()), then this should be selected.
+      a MAC address (via lm_ethernetmac()), then this should be selected.
     CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
     CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
     CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
diff --git a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
index d8ae63cff..b614c0316 100644
--- a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
+++ b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
@@ -39,7 +39,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S9B96=y
 CONFIG_ARCH_BOARD="ekk-lm3s9b96"
diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
index 62a092d1f..df5622360 100644
--- a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
+++ b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
@@ -39,7 +39,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S9B96=y
 CONFIG_ARCH_BOARD="ekk-lm3s9b96"
diff --git a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
index bb3315f5b..17b0d0e27 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
+++ b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
@@ -1,6 +1,6 @@
 /************************************************************************************
  * configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
- * arch/arm/src/board/lm3s6965ek_internal.n
+ * arch/arm/src/board/lm3s6965ek_internal.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
diff --git a/nuttx/configs/lm3s6432-s2e/README.txt b/nuttx/configs/lm3s6432-s2e/README.txt
index 296a10f05..669708c16 100644
--- a/nuttx/configs/lm3s6432-s2e/README.txt
+++ b/nuttx/configs/lm3s6432-s2e/README.txt
@@ -163,13 +163,13 @@ IDEs
   2) Start the NuttX build at least one time from the Cygwin command line
      before trying to create your project.  This is necessary to create
      certain auto-generated files and directories that will be needed.
-  3) Set up include pathes:  You will need include/, arch/arm/src/lm3s,
+  3) Set up include pathes:  You will need include/, arch/arm/src/lm,
      arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
   4) All assembly files need to have the definition option -D __ASSEMBLY__
      on the command line.
 
   Startup files will probably cause you some headaches.  The NuttX startup file
-  is arch/arm/src/lm3s/lm3s_vectors.S.
+  is arch/arm/src/lm/lm_vectors.S.
 
 NuttX EABI "buildroot" Toolchain
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -288,7 +288,7 @@ Stellaris MDL-S2E Reference Design Configuration Options
 
     CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
 
-       CONFIG_ARCH_CHIP=lm3s
+       CONFIG_ARCH_CHIP=lm
 
     CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
        chip:
diff --git a/nuttx/configs/lm3s6432-s2e/nsh/defconfig b/nuttx/configs/lm3s6432-s2e/nsh/defconfig
index 7d1657cda..edd61eacc 100644
--- a/nuttx/configs/lm3s6432-s2e/nsh/defconfig
+++ b/nuttx/configs/lm3s6432-s2e/nsh/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6432=y
 CONFIG_ARCH_BOARD="lm3s6432-s2e"
diff --git a/nuttx/configs/lm3s6432-s2e/ostest/defconfig b/nuttx/configs/lm3s6432-s2e/ostest/defconfig
index 90357ce7f..2d32db81c 100644
--- a/nuttx/configs/lm3s6432-s2e/ostest/defconfig
+++ b/nuttx/configs/lm3s6432-s2e/ostest/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S6432=y
 CONFIG_ARCH_BOARD="lm3s6432-s2e"
diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt
index 09a07ec68..5a9cdbf4e 100644
--- a/nuttx/configs/lm3s6965-ek/README.txt
+++ b/nuttx/configs/lm3s6965-ek/README.txt
@@ -197,13 +197,13 @@ IDEs
   2) Start the NuttX build at least one time from the Cygwin command line
      before trying to create your project.  This is necessary to create
      certain auto-generated files and directories that will be needed.
-  3) Set up include pathes:  You will need include/, arch/arm/src/lm3s,
+  3) Set up include pathes:  You will need include/, arch/arm/src/lm,
      arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
   4) All assembly files need to have the definition option -D __ASSEMBLY__
      on the command line.
 
   Startup files will probably cause you some headaches.  The NuttX startup file
-  is arch/arm/src/lm3s/lm3s_vectors.S.
+  is arch/arm/src/lm/lm_vectors.S.
 
 NuttX EABI "buildroot" Toolchain
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -357,7 +357,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
 
     CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
 
-       CONFIG_ARCH_CHIP=lm3s
+       CONFIG_ARCH_CHIP=lm
 
     CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
        chip:
@@ -452,7 +452,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
       to build the LM3S Ethernet driver
     CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
-      a MAC address (via lm3s_ethernetmac()), then this should be selected.
+      a MAC address (via lm_ethernetmac()), then this should be selected.
     CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
     CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
     CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig
index 64f4397cb..c1827920b 100755
--- a/nuttx/configs/lm3s6965-ek/nsh/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig
@@ -65,6 +65,7 @@ CONFIG_ARCH="arm"
 # CONFIG_ARCH_CHIP_DM320 is not set
 # CONFIG_ARCH_CHIP_IMX is not set
 # CONFIG_ARCH_CHIP_KINETIS is not set
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 # CONFIG_ARCH_CHIP_LPC17XX is not set
 # CONFIG_ARCH_CHIP_LPC214X is not set
@@ -76,7 +77,7 @@ CONFIG_ARCH_CHIP_LM3S=y
 # CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_FAMILY="armv7-m"
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
 CONFIG_ARCH_HAVE_MPU=y
 # CONFIG_ARMV7M_MPU is not set
 CONFIG_BOARD_LOOPSPERMSEC=4531
diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig
index be75c2875..e3cac8dd7 100755
--- a/nuttx/configs/lm3s6965-ek/nx/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nx/defconfig
@@ -65,6 +65,7 @@ CONFIG_ARCH="arm"
 # CONFIG_ARCH_CHIP_DM320 is not set
 # CONFIG_ARCH_CHIP_IMX is not set
 # CONFIG_ARCH_CHIP_KINETIS is not set
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 # CONFIG_ARCH_CHIP_LPC17XX is not set
 # CONFIG_ARCH_CHIP_LPC214X is not set
@@ -76,7 +77,7 @@ CONFIG_ARCH_CHIP_LM3S=y
 # CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_FAMILY="armv7-m"
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
 CONFIG_ARCH_HAVE_MPU=y
 # CONFIG_ARMV7M_MPU is not set
 CONFIG_BOARD_LOOPSPERMSEC=4531
diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig
index 83e89a6ae..81247c795 100755
--- a/nuttx/configs/lm3s6965-ek/ostest/defconfig
+++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig
@@ -65,6 +65,7 @@ CONFIG_ARCH="arm"
 # CONFIG_ARCH_CHIP_DM320 is not set
 # CONFIG_ARCH_CHIP_IMX is not set
 # CONFIG_ARCH_CHIP_KINETIS is not set
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 # CONFIG_ARCH_CHIP_LPC17XX is not set
 # CONFIG_ARCH_CHIP_LPC214X is not set
@@ -76,7 +77,7 @@ CONFIG_ARCH_CHIP_LM3S=y
 # CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM3=y
 CONFIG_ARCH_FAMILY="armv7-m"
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
 CONFIG_ARCH_HAVE_MPU=y
 # CONFIG_ARMV7M_MPU is not set
 CONFIG_BOARD_LOOPSPERMSEC=4531
diff --git a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
index 8ebd4cf65..4cd2eddc7 100644
--- a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
+++ b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
@@ -1,6 +1,6 @@
 /************************************************************************************
  * configs/lm3s6965-ek/src/lm3s6965ek_internal.h
- * arch/arm/src/board/lm3s6965ek_internal.n
+ * arch/arm/src/board/lm3s6965ek_internal.h
  *
  *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
diff --git a/nuttx/configs/lm3s8962-ek/README.txt b/nuttx/configs/lm3s8962-ek/README.txt
index fdb783466..0f796e38d 100644
--- a/nuttx/configs/lm3s8962-ek/README.txt
+++ b/nuttx/configs/lm3s8962-ek/README.txt
@@ -181,13 +181,13 @@ IDEs
   2) Start the NuttX build at least one time from the Cygwin command line
      before trying to create your project.  This is necessary to create
      certain auto-generated files and directories that will be needed.
-  3) Set up include pathes:  You will need include/, arch/arm/src/lm3s,
+  3) Set up include pathes:  You will need include/, arch/arm/src/lm,
      arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
   4) All assembly files need to have the definition option -D __ASSEMBLY__
      on the command line.
 
   Startup files will probably cause you some headaches.  The NuttX startup file
-  is arch/arm/src/lm3s/lm3s_vectors.S.
+  is arch/arm/src/lm/lm_vectors.S.
 
 NuttX EABI "buildroot" Toolchain
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -341,7 +341,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
 
     CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
 
-       CONFIG_ARCH_CHIP=lm3s
+       CONFIG_ARCH_CHIP=lm
 
     CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
        chip:
@@ -436,7 +436,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
       to build the LM3S Ethernet driver
     CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
-      a MAC address (via lm3s_ethernetmac()), then this should be selected.
+      a MAC address (via lm_ethernetmac()), then this should be selected.
     CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
     CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
     CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
diff --git a/nuttx/configs/lm3s8962-ek/nsh/defconfig b/nuttx/configs/lm3s8962-ek/nsh/defconfig
index 79f90d5f9..1d3df2fa7 100755
--- a/nuttx/configs/lm3s8962-ek/nsh/defconfig
+++ b/nuttx/configs/lm3s8962-ek/nsh/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S8962=y
 CONFIG_ARCH_BOARD="lm3s8962-ek"
diff --git a/nuttx/configs/lm3s8962-ek/nx/defconfig b/nuttx/configs/lm3s8962-ek/nx/defconfig
index 8424b6623..37fc8903d 100755
--- a/nuttx/configs/lm3s8962-ek/nx/defconfig
+++ b/nuttx/configs/lm3s8962-ek/nx/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S8962=y
 CONFIG_ARCH_BOARD="lm3s8962-ek"
diff --git a/nuttx/configs/lm3s8962-ek/ostest/defconfig b/nuttx/configs/lm3s8962-ek/ostest/defconfig
index 73fbff29f..731003fd0 100755
--- a/nuttx/configs/lm3s8962-ek/ostest/defconfig
+++ b/nuttx/configs/lm3s8962-ek/ostest/defconfig
@@ -38,7 +38,8 @@
 CONFIG_ARCH="arm"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_CORTEXM3=y
-CONFIG_ARCH_CHIP="lm3s"
+CONFIG_ARCH_CHIP="lm"
+CONFIG_ARCH_CHIP_LM=y
 CONFIG_ARCH_CHIP_LM3S=y
 CONFIG_ARCH_CHIP_LM3S8962=y
 CONFIG_ARCH_BOARD="lm3s8962-ek"
-- 
cgit v1.2.3


From 8156a2bed16d732d2489f7d6fe410b110c29b1d5 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Wed, 9 Jan 2013 12:55:13 +0000
Subject: Use kconfig- prefix to avoid tool name conflicts (from Jose Pablo
 Carballo)

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5496 42af7a65-404d-4744-a932-0658087f49c3
---
 misc/tools/README.txt                      |  61 ++++++++++---
 nuttx/Makefile.unix                        |   6 +-
 nuttx/Makefile.win                         |   6 +-
 nuttx/README.txt                           |  20 ++---
 nuttx/arch/arm/src/lm/Kconfig              |  10 +--
 nuttx/configs/amber/README.txt             |   2 +-
 nuttx/configs/ea3131/README.txt            |   2 +-
 nuttx/configs/ea3152/README.txt            |   4 +-
 nuttx/configs/ez80f910200kitg/README.txt   |   4 +-
 nuttx/configs/ez80f910200zco/README.txt    |   4 +-
 nuttx/configs/fire-stm32v2/README.txt      |   8 +-
 nuttx/configs/lm3s6965-ek/README.txt       |  12 +--
 nuttx/configs/mcu123-lpc214x/README.txt    |   4 +-
 nuttx/configs/micropendous3/README.txt     |   2 +-
 nuttx/configs/mirtoo/README.txt            |   2 +-
 nuttx/configs/ntosd-dm320/README.txt       |   4 +-
 nuttx/configs/olimex-lpc1766stk/README.txt |   4 +-
 nuttx/configs/sim/README.txt               |  16 ++--
 nuttx/configs/stm3220g-eval/README.txt     |   8 +-
 nuttx/configs/stm3240g-eval/README.txt     |   6 +-
 nuttx/configs/stm32f4discovery/README.txt  |  16 ++--
 nuttx/configs/teensy/README.txt            |   2 +-
 nuttx/configs/xtrs/README.txt              |   2 +-
 nuttx/configs/z16f2800100zcog/README.txt   |   8 +-
 nuttx/configs/z80sim/README.txt            |   2 +-
 nuttx/configs/z8encore000zco/README.txt    |   4 +-
 nuttx/configs/z8f64200100kit/README.txt    |   4 +-
 nuttx/configs/zp214xpa/README.txt          |   8 +-
 nuttx/include/spawn.h                      | 137 +++++++++++++++++++++++++++++
 nuttx/libc/Kconfig                         |  28 +++---
 nuttx/libc/Makefile                        |   1 +
 nuttx/libc/spawn/Make.defs                 |  46 ++++++++++
 nuttx/tools/README.txt                     |   8 +-
 nuttx/tools/kconfig.bat                    |   6 +-
 34 files changed, 340 insertions(+), 117 deletions(-)
 create mode 100644 nuttx/include/spawn.h
 create mode 100644 nuttx/libc/spawn/Make.defs

(limited to 'nuttx/arch')

diff --git a/misc/tools/README.txt b/misc/tools/README.txt
index 512d8ebaa..1546c6f39 100644
--- a/misc/tools/README.txt
+++ b/misc/tools/README.txt
@@ -1,8 +1,18 @@
 misc/tools/README.txt
 =====================
 
+Contents:
+
+  o genromfs-0.5.2.tar.gz
+  o kconfig-frontends
+    - --program-prefix=
+    - kconfig-frontends-3.3.0-1-libintl.patch
+    - kconfig-macos.patch
+    - kconfig-macos.patch
+    - kconfig-frontends for Windows
+
 genromfs-0.5.2.tar.gz
----------------------
+=====================
 
   This is a snapshot of the genromfs tarball taken from
   http://sourceforge.net/projects/romfs/.  This snapshot is provided to
@@ -12,34 +22,60 @@ genromfs-0.5.2.tar.gz
   from the buildroot.
 
 kconfig-frontends
------------------
+=================
 
-  This is a snapshot of the kconfig-frontends version 3.6.0 tarball taken
+  This is a snapshot of the kconfig-frontends version 3.7.0 tarball taken
   from http://ymorin.is-a-geek.org/projects/kconfig-frontends.
 
   General build instructions:
 
     cd kconfig-frontends
-    ./configure --program-prefix=
+    ./configure
     make
     make install
 
-  If you do not specify --program-prefix= in the configuration, then the
-  current kconfig-frontends code will add the prefix kconfig- to the generated
-  tools.
+  To suppress the nconf and the graphical interfaces which are not used by
+  NuttX:
+
+    ./configure --disable-gconf --disable-qconf
+    make
+    make install
 
-  To suppress the graphical interfaces:
+  To suppress the graphical interfaces, use static libraries, and disable
+  creation of other utilities:
 
-    ./configure --disable-gconf --disable-qconf --program-prefix=
+    ./configure --disable-shared --enable-static --disable-gconf --disable-qconf --disable-nconf --disable-utils
     make
     make install
 
+  You may require root privileges to 'make install'.
+
+--program-prefix=
+-----------------
+
+  Beginning somwhere between version 3.3.0 and 3.6.0, the prefix was added
+  to the kconfig-frontends tools.  The default prefix is kconfig-.  So,
+  after 3.3.0, conf becomes kconfig-conf, mconf becomes kconfig-mconf, etc.
+  All of the NuttX documentation, Makefiles, scripts have been updated to
+  used this default prefix.
+
+  This introduces an incompatibility with the 3.3.0 version.  In the 3.6.0
+  timeframe, the configure argument --program-prefix= was added to
+  eliminated the kconfig- prefix.  This, however, caused problems when we
+  got to the 3.7.0 version which generates a binary called kconfig-diff
+  (installed at /usr/local/bin).  Without the prefix, may conflict with
+  the standard diff utility (at /bin), depending upon how your PATH
+  variable is configured.  Because of this, we decided to "bite the bullet"
+  and use the standard prefix at 3.7.0 and later.
+
+  This problem could probably also be avoided using --disable-utils.
+
 kconfig-frontends-3.3.0-1-libintl.patch
 ---------------------------------------
 
   The above build instructions did not work for me under my Cygwin
   installation with kconfig-frontends-3.3.0.  This patch is a awful hack
-  but will successfully build 'mconf' under Cygwin.
+  but will successfully build 'kconfig-mconf' under Cygwin.
 
     cat kconfig-frontends-3.3.0-1-libintl.patch | patch -p0
     cd kconfig-frontends-3.3.0-1
@@ -49,8 +85,7 @@ kconfig-frontends-3.3.0-1-libintl.patch
 
   See: http://ymorin.is-a-geek.org/hg/kconfig-frontends/file/tip/docs/known-issues.txt
 
-  Update: According to the release notes, version 3.6.0 (and above)
-  will build on Cygwin with no patches: 
+  Update: Version 3.6.0 (and above) will build on Cygwin with no patches: 
 
     http://ymorin.is-a-geek.org/download/kconfig-frontends/
 
@@ -66,7 +101,7 @@ kconfig-macos.patch
     make install
 
 kconfig-frontends for Windows
-=============================
+-----------------------------
 
 From http://tech.groups.yahoo.com/group/nuttx/message/2900:
 
diff --git a/nuttx/Makefile.unix b/nuttx/Makefile.unix
index d66c06bd8..47debcccf 100644
--- a/nuttx/Makefile.unix
+++ b/nuttx/Makefile.unix
@@ -642,13 +642,13 @@ pass2dep: context tools/mkdeps$(HOSTEXEEXT)
 # misc/tools/README.txt for additional information.
 
 config:
-	$(Q) APPSDIR=${CONFIG_APPS_DIR} conf Kconfig
+	$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf Kconfig
 
 oldconfig:
-	$(Q) APPSDIR=${CONFIG_APPS_DIR} conf --oldconfig Kconfig
+	$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --oldconfig Kconfig
 
 menuconfig:
-	$(Q) APPSDIR=${CONFIG_APPS_DIR} mconf Kconfig
+	$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-mconf Kconfig
 
 # export
 #
diff --git a/nuttx/Makefile.win b/nuttx/Makefile.win
index 803d073b2..5c4404f57 100644
--- a/nuttx/Makefile.win
+++ b/nuttx/Makefile.win
@@ -651,13 +651,13 @@ configenv:
 	$(Q) set APPSDIR=${CONFIG_APPS_DIR}
 
 config: configenv
-	$(Q) conf Kconfig
+	$(Q) kconfig-conf Kconfig
 
 oldconfig: configenv
-	$(Q) conf --oldconfig Kconfig
+	$(Q) kconfig-conf --oldconfig Kconfig
 
 menuconfig: configenv
-	$(Q) mconf Kconfig
+	$(Q) kconfig-mconf Kconfig
 
 # export
 #
diff --git a/nuttx/README.txt b/nuttx/README.txt
index 0348f7f30..23d0e1a81 100644
--- a/nuttx/README.txt
+++ b/nuttx/README.txt
@@ -243,8 +243,8 @@ additional file to the directory the NuttX application package (APPSDIR)):
     The appconfig file describes the applications that need to be
     built in the appliction directory (APPSDIR).  Not all configurations
     have an appconfig file.  This file is deprecated and will not be
-    used with new defconfig files produced with the mconf configuration
-    tool.
+    used with new defconfig files produced with the kconfig-mconf
+    configuration tool.
 
 General information about configuring NuttX can be found in:
 
@@ -439,14 +439,14 @@ NuttX Configuration Tool under DOS
      And of course, after you use the configuration tool you need to
      restore CONFIG_WINDOWS_NATIVE=y and the correct CONFIG_APPS_DIR.
 
-  2) You can, with some effort, run the the Cygwin mconf tool directly
-     in the CMD.exe shell.  In this case, you do not have to modify the
-     .config file, but there are other complexities:
+  2) You can, with some effort, run the the Cygwin kconfig-mconf tool
+     directly in the CMD.exe shell.  In this case, you do not have to
+     modify the .config file, but there are other complexities:
 
       a. You need to temporarily set the Cgywin directories in the PATH
-         variable then run mconf manually like:
+         variable then run kconfig-mconf manually like:
 
-          mconf Kconfig
+          kconfig-mconf Kconfig
 
          There is a Windows bacht file at tools/kconfig.bat that automates
          these steps:
@@ -454,9 +454,9 @@ NuttX Configuration Tool under DOS
          tools/kconfig menuconfig
 
        b. There is an issue with accessing DOS environment variables from
-          the Cygwin mconf running in the CMD.exe shell.  The following
-          change to the top-level Kconfig file seems to work around these
-          problems:
+          the Cygwin kconfig-mconf running in the CMD.exe shell.  The
+          following change to the top-level Kconfig file seems to work
+          around these problems:
   
           config APPSDIR
               string
diff --git a/nuttx/arch/arm/src/lm/Kconfig b/nuttx/arch/arm/src/lm/Kconfig
index 74d1712f3..2d2504c7e 100644
--- a/nuttx/arch/arm/src/lm/Kconfig
+++ b/nuttx/arch/arm/src/lm/Kconfig
@@ -60,7 +60,7 @@ config LM3S_DFU
 	bool "DFU"
 	default y
 
-menu "Select LM3S Peripheral Support"
+menu "Stellaris Peripheral Support"
 
 config LM3S_UART0
 	bool "UART0"
@@ -86,10 +86,10 @@ config LM3S_UART2
 	default n
 
 config LM3S_ETHERNET
-	bool "LM3S Ethernet"
+	bool "Stellaris Ethernet"
 	default n
 	---help---
-		This must be set (along with NET) to build the LM3S Ethernet driver.
+		This must be set (along with NET) to build the Stellaris Ethernet driver.
 
 endmenu
 
@@ -134,7 +134,7 @@ config LM3S_DISABLE_GPIOJ_IRQS
 endmenu
 
 if LM3S_ETHERNET
-menu "LM3S Ethernet Configuration"
+menu "Stellaris Ethernet Configuration"
 
 config LM3S_ETHLEDS
 	bool "Ethernet LEDs"
@@ -199,7 +199,7 @@ endmenu
 endif
 
 if !SSI0_DISABLE || !SSI1_DISABLE
-menu "LM3S SSI Configuration"
+menu "Stellaris SSI Configuration"
 
 config SSI_POLLWAIT
 	bool "Poll Wait (No-Interrupt) Mode"
diff --git a/nuttx/configs/amber/README.txt b/nuttx/configs/amber/README.txt
index 56e31ba7f..9f40dcdd2 100644
--- a/nuttx/configs/amber/README.txt
+++ b/nuttx/configs/amber/README.txt
@@ -187,7 +187,7 @@ Atmel AVRISP mkII Connection
 Toolchains
 ^^^^^^^^^^
 
-The toolchain may be selected using the mconf tool (via 'make menuconfig'),
+The toolchain may be selected using the kconfig-mconf tool (via 'make menuconfig'),
 by editing the existing configuration file (defconfig), or by overriding
 the toolchain on the make commandline with CONFIG_AVR_TOOLCHAIN=<toolchain>.
 
diff --git a/nuttx/configs/ea3131/README.txt b/nuttx/configs/ea3131/README.txt
index fcfc0792f..986b7778c 100644
--- a/nuttx/configs/ea3131/README.txt
+++ b/nuttx/configs/ea3131/README.txt
@@ -53,7 +53,7 @@ GNU Toolchain Options
   If you are not using CONFIG_LPC31_BUILDROOT, then you may also have to modify
   the PATH in the setenv.h file if your make cannot find the tools.
 
-  The toolchain may also be set using the mconf utility (make menuconfig) or by
+  The toolchain may also be set using the kconfig-mconf utility (make menuconfig) or by
   passing CONFIG_ARM_TOOLCHAIN=<toolchain> to make, where <toolchain> is one
   of CODESOURCERYW, CODESOURCERYL, DEVKITARM, BUILDROOT or GNU_EABI as described
   above.
diff --git a/nuttx/configs/ea3152/README.txt b/nuttx/configs/ea3152/README.txt
index da57945bd..4f507e7b0 100644
--- a/nuttx/configs/ea3152/README.txt
+++ b/nuttx/configs/ea3152/README.txt
@@ -52,8 +52,8 @@ GNU Toolchain Options
   If you are not using CONFIG_LPC31_BUILDROOT, then you may also have to modify
   the PATH in the setenv.h file if your make cannot find the tools.
 
-  The toolchain may also be set using the mconf utility (make menuconfig) or by
-  passing CONFIG_ARM_TOOLCHAIN=<toolchain> to make, where <toolchain> is one
+  The toolchain may also be set using the kconfig-mconf utility (make menuconfig)
+  or by passing CONFIG_ARM_TOOLCHAIN=<toolchain> to make, where <toolchain> is one
   of CODESOURCERYW, CODESOURCERYL, DEVKITARM, BUILDROOT or GNU_EABI as described
   above.
 
diff --git a/nuttx/configs/ez80f910200kitg/README.txt b/nuttx/configs/ez80f910200kitg/README.txt
index e314b0fe1..8d9086b4e 100644
--- a/nuttx/configs/ez80f910200kitg/README.txt
+++ b/nuttx/configs/ez80f910200kitg/README.txt
@@ -88,8 +88,8 @@ available:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/ez80f910200zco/README.txt b/nuttx/configs/ez80f910200zco/README.txt
index 1bc9e56b8..7df503217 100644
--- a/nuttx/configs/ez80f910200zco/README.txt
+++ b/nuttx/configs/ez80f910200zco/README.txt
@@ -102,8 +102,8 @@ ostest
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/fire-stm32v2/README.txt b/nuttx/configs/fire-stm32v2/README.txt
index 88b5bf583..d12a9b27d 100644
--- a/nuttx/configs/fire-stm32v2/README.txt
+++ b/nuttx/configs/fire-stm32v2/README.txt
@@ -826,9 +826,9 @@ Where <subdir> is one of the following:
     contains support for some built-in applications that can be enabled by making
     some additional minor change to the configuration file.
 
-    Reconfiguring:  This configuration uses to the mconf configuration tool to control
-    the configuration.  See the section entitled "NuttX Configuration Tool"
-    in the top-level README.txt file.
+    Reconfiguring:  This configuration uses to the kconfig-mconf configuration tool
+    to control the configuration.  See the section entitled "NuttX Configuration
+    Tool" in the top-level README.txt file.
 
     Start Delays:  If no SD card is present in the slot, or if the network is not
     connected, then there will be long start-up delays before you get the NSH
@@ -842,7 +842,7 @@ Where <subdir> is one of the following:
     verified.  The ENC28J60 network is not yet functional.  Networking is
     enabled by default in this configuration for testing purposes.  To use this
     configuration, the network must currently be disabled.  To do this using
-    the mconf configuration tool:
+    the kconfig-mconf configuration tool:
 
     > make menuconfig
 
diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt
index 5a9cdbf4e..e0349f5de 100644
--- a/nuttx/configs/lm3s6965-ek/README.txt
+++ b/nuttx/configs/lm3s6965-ek/README.txt
@@ -482,8 +482,8 @@ Where <subdir> is one of the following:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
@@ -512,8 +512,8 @@ Where <subdir> is one of the following:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
@@ -532,8 +532,8 @@ Where <subdir> is one of the following:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/mcu123-lpc214x/README.txt b/nuttx/configs/mcu123-lpc214x/README.txt
index 4c7c608b7..1c6c9bde8 100644
--- a/nuttx/configs/mcu123-lpc214x/README.txt
+++ b/nuttx/configs/mcu123-lpc214x/README.txt
@@ -354,8 +354,8 @@ nsh:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/micropendous3/README.txt b/nuttx/configs/micropendous3/README.txt
index 1b0f2c8ce..6b586bd64 100644
--- a/nuttx/configs/micropendous3/README.txt
+++ b/nuttx/configs/micropendous3/README.txt
@@ -200,7 +200,7 @@ There are several toolchain options.  However, testing has been performed
 using *only* the NuttX buildroot toolchain described below.  Therefore,
 the NuttX buildroot toolchain is the recommended choice.
 
-The toolchain may be selected using the mconf tool (via 'make menuconfig'),
+The toolchain may be selected using the kconfig-mconf tool (via 'make menuconfig'),
 by editing the existing configuration file (defconfig), or by overriding
 the toolchain on the make commandline with CONFIG_AVR_TOOLCHAIN=<toolchain>.
 
diff --git a/nuttx/configs/mirtoo/README.txt b/nuttx/configs/mirtoo/README.txt
index 89c137a03..6d3ea234e 100644
--- a/nuttx/configs/mirtoo/README.txt
+++ b/nuttx/configs/mirtoo/README.txt
@@ -324,7 +324,7 @@ Toolchains
 ==========
 
   Note that in addition to the configuration options listed below, the
-  toolchain can be configured using the mconf utility ('make menuconfig')
+  toolchain can be configured using the kconfig-mconf utility ('make menuconfig')
   or by passing CONFIG_MIPS32_TOOLCHAIN=<toolchain> to make, where
   <toolchain> is one of GNU_ELF, MICROCHIPL, MICROCHIPW, MICROCHIPL_LITE,
   MICROCHIPW_LITE, MICROCHIPOPENL or PINGUINOW as described below.
diff --git a/nuttx/configs/ntosd-dm320/README.txt b/nuttx/configs/ntosd-dm320/README.txt
index d85e53525..675716154 100644
--- a/nuttx/configs/ntosd-dm320/README.txt
+++ b/nuttx/configs/ntosd-dm320/README.txt
@@ -72,8 +72,8 @@ GNU Toolchain Options
   If you are not using CONFIG_DM320_BUILDROOT, then you may also have to modify
   the PATH in the setenv.h file if your make cannot find the tools.
 
-  The toolchain may also be set using the mconf utility (make menuconfig) or by
-  passing CONFIG_ARM_TOOLCHAIN=<toolchain> to make, where <toolchain> is one
+  The toolchain may also be set using the kconfig-mconf utility (make menuconfig)
+  or by passing CONFIG_ARM_TOOLCHAIN=<toolchain> to make, where <toolchain> is one
   of CODESOURCERYW, CODESOURCERYL, DEVKITARM, BUILDROOT or GNU_EABI as described
   above.
 
diff --git a/nuttx/configs/olimex-lpc1766stk/README.txt b/nuttx/configs/olimex-lpc1766stk/README.txt
index 35f00e9f2..13c63d18b 100644
--- a/nuttx/configs/olimex-lpc1766stk/README.txt
+++ b/nuttx/configs/olimex-lpc1766stk/README.txt
@@ -904,8 +904,8 @@ Where <subdir> is one of the following:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt
index ff756fb4b..8abfd9c23 100644
--- a/nuttx/configs/sim/README.txt
+++ b/nuttx/configs/sim/README.txt
@@ -209,8 +209,8 @@ cxxtest
   2. This configuration uses the mconf-based configuration tool.  To
      change this configuration using that tool, you should:
 
-     a. Build and install the mconf tool.  See nuttx/README.txt and
-        misc/tools/
+     a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+        and misc/tools/
 
      b. Execute 'make menuconfig' in nuttx/ in order to start the
         reconfiguration process.
@@ -455,8 +455,8 @@ nxlines
   1. This configuration uses the mconf-based configuration tool.  To
      change this configuration using that tool, you should:
 
-     a. Build and install the mconf tool.  See nuttx/README.txt and
-        misc/tools/
+     a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+        and misc/tools/
 
      b. Execute 'make menuconfig' in nuttx/ in order to start the
         reconfiguration process.
@@ -481,8 +481,8 @@ nxwm
   1. This configuration uses the mconf-based configuration tool.  To
      change this configuration using that tool, you should:
 
-     a. Build and install the mconf tool.  See nuttx/README.txt and
-        misc/tools/
+     a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+        and misc/tools/
 
      b. Execute 'make menuconfig' in nuttx/ in order to start the
         reconfiguration process.
@@ -543,8 +543,8 @@ ostest
   1. This configuration uses the mconf-based configuration tool.  To
      change this configuration using that tool, you should:
 
-     a. Build and install the mconf tool.  See nuttx/README.txt and
-        misc/tools/
+     a. Build and install the kconfig mconf tool.  See nuttx/README.txt
+        and misc/tools/
 
      b. Execute 'make menuconfig' in nuttx/ in order to start the
         reconfiguration process.
diff --git a/nuttx/configs/stm3220g-eval/README.txt b/nuttx/configs/stm3220g-eval/README.txt
index e7bdd4de0..40c918582 100644
--- a/nuttx/configs/stm3220g-eval/README.txt
+++ b/nuttx/configs/stm3220g-eval/README.txt
@@ -65,8 +65,8 @@ GNU Toolchain Options
   If you change the default toolchain, then you may also have to modify the PATH in
   the setenv.h file if your make cannot find the tools.
 
-  The toolchain may also be set using the mconf utility (make menuconfig) or by
-  passing CONFIG_ARMV7M_TOOLCHAIN=<toolchain> to make, where <toolchain> is one
+  The toolchain may also be set using the kconfig-mconf utility (make menuconfig)
+  or by passing CONFIG_ARMV7M_TOOLCHAIN=<toolchain> to make, where <toolchain> is one
   of CODESOURCERYW, CODESOURCERYL, ATOLLOC, DEVKITARM, RAISONANCE, BUILDROOT or
   GNU_EABI as described above.
 
@@ -1082,8 +1082,8 @@ Where <subdir> is one of the following:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/stm3240g-eval/README.txt b/nuttx/configs/stm3240g-eval/README.txt
index 829f3a777..e8a3c4b25 100644
--- a/nuttx/configs/stm3240g-eval/README.txt
+++ b/nuttx/configs/stm3240g-eval/README.txt
@@ -951,9 +951,9 @@ Where <subdir> is one of the following:
       CONFIG_EXAMPLES_DISCOVER_IPADDR   - (not defined)
       CONFIG_EXAMPLES_DISCOVER_DRIPADDR - Router IP address
 
-    NOTE:  This configuration uses to the mconf configuration tool to control
-    the configuration.  See the section entitled "NuttX Configuration Tool"
-    in the top-level README.txt file.
+    NOTE:  This configuration uses to the kconfig-mconf configuration tool to
+    control the configuration.  See the section entitled "NuttX Configuration
+    Tool" in the top-level README.txt file.
 
   nettest:
   -------
diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt
index 28072f44b..ef61b05e6 100644
--- a/nuttx/configs/stm32f4discovery/README.txt
+++ b/nuttx/configs/stm32f4discovery/README.txt
@@ -1038,8 +1038,8 @@ Where <subdir> is one of the following:
   2. This configuration uses the mconf-based configuration tool.  To
      change this configuration using that tool, you should:
 
-     a. Build and install the mconf tool.  See nuttx/README.txt and
-        misc/tools/
+     a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+        and misc/tools/
 
      b. Execute 'make menuconfig' in nuttx/ in order to start the
         reconfiguration process.
@@ -1087,8 +1087,8 @@ Where <subdir> is one of the following:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
@@ -1121,8 +1121,8 @@ Where <subdir> is one of the following:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
@@ -1350,8 +1350,8 @@ Where <subdir> is one of the following:
   2. This configuration uses the mconf-based configuration tool.  To
      change this configuration using that tool, you should:
 
-     a. Build and install the mconf tool.  See nuttx/README.txt and
-        misc/tools/
+     a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+        and misc/tools/
 
      b. Execute 'make menuconfig' in nuttx/ in order to start the
         reconfiguration process.
diff --git a/nuttx/configs/teensy/README.txt b/nuttx/configs/teensy/README.txt
index 951f4a87e..23e7d6c98 100644
--- a/nuttx/configs/teensy/README.txt
+++ b/nuttx/configs/teensy/README.txt
@@ -203,7 +203,7 @@ There are several toolchain options.  However, testing has been performed
 using *only* the NuttX buildroot toolchain described below.  Therefore,
 the NuttX buildroot toolchain is the recommended choice.
 
-The toolchain may be selected using the mconf tool (via 'make menuconfig'),
+The toolchain may be selected using the kconfig-mconf tool (via 'make menuconfig'),
 by editing the existing configuration file (defconfig), or by overriding
 the toolchain on the make commandline with CONFIG_AVR_TOOLCHAIN=<toolchain>.
 
diff --git a/nuttx/configs/xtrs/README.txt b/nuttx/configs/xtrs/README.txt
index d462dcab1..f8b3d0e73 100644
--- a/nuttx/configs/xtrs/README.txt
+++ b/nuttx/configs/xtrs/README.txt
@@ -165,7 +165,7 @@ Reconfiguring NuttX
 These configurations all use the kconfig-frontends, mconf-based configuration
 tool.  To change this configuration using that tool, you should:
 
-  a. Build and install the mconf tool.  See nuttx/README.txt and
+  a. Build and install the kconfig-mconf tool.  See nuttx/README.txt and
      misc/tools/README.txt
 
   b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration
diff --git a/nuttx/configs/z16f2800100zcog/README.txt b/nuttx/configs/z16f2800100zcog/README.txt
index e12931df2..4d61a41da 100644
--- a/nuttx/configs/z16f2800100zcog/README.txt
+++ b/nuttx/configs/z16f2800100zcog/README.txt
@@ -105,8 +105,8 @@ ostest
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
@@ -154,8 +154,8 @@ pashello
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/z80sim/README.txt b/nuttx/configs/z80sim/README.txt
index 595a17783..f4055207c 100644
--- a/nuttx/configs/z80sim/README.txt
+++ b/nuttx/configs/z80sim/README.txt
@@ -112,7 +112,7 @@ Reconfiguring NuttX
 These configurations all use the kconfig-frontends, mconf-based configuration
 tool.  To change this configuration using that tool, you should:
 
-  a. Build and install the mconf tool.  See nuttx/README.txt and
+  a. Build and install the kconfig-mconf tool.  See nuttx/README.txt and
      misc/tools/README.txt
 
   b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration
diff --git a/nuttx/configs/z8encore000zco/README.txt b/nuttx/configs/z8encore000zco/README.txt
index 7ca50db8c..70d62ea80 100644
--- a/nuttx/configs/z8encore000zco/README.txt
+++ b/nuttx/configs/z8encore000zco/README.txt
@@ -73,8 +73,8 @@ available:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/z8f64200100kit/README.txt b/nuttx/configs/z8f64200100kit/README.txt
index b0f224ad8..e3c22d87b 100644
--- a/nuttx/configs/z8f64200100kit/README.txt
+++ b/nuttx/configs/z8f64200100kit/README.txt
@@ -73,8 +73,8 @@ available:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/configs/zp214xpa/README.txt b/nuttx/configs/zp214xpa/README.txt
index 58a2242d0..88d03b9de 100644
--- a/nuttx/configs/zp214xpa/README.txt
+++ b/nuttx/configs/zp214xpa/README.txt
@@ -303,8 +303,8 @@ Configurations:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
@@ -327,8 +327,8 @@ Configurations:
     1. This configuration uses the mconf-based configuration tool.  To
        change this configuration using that tool, you should:
 
-       a. Build and install the mconf tool.  See nuttx/README.txt and
-          misc/tools/
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
 
        b. Execute 'make menuconfig' in nuttx/ in order to start the
           reconfiguration process.
diff --git a/nuttx/include/spawn.h b/nuttx/include/spawn.h
new file mode 100644
index 000000000..3463670b5
--- /dev/null
+++ b/nuttx/include/spawn.h
@@ -0,0 +1,137 @@
+/****************************************************************************
+ * include/spawn.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __INCLUDE_LIBGEN_H
+#define __INCLUDE_LIBGEN_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <signal.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* "The spawn.h header shall define the flags that may be set in a
+ * posix_spawnattr_t object using the posix_spawnattr_setflags() function:"
+ */
+
+#define POSIX_SPAWN_RESETIDS      (1 << 0)
+#define POSIX_SPAWN_SETPGROUP     (1 << 1)
+#define POSIX_SPAWN_SETSCHEDPARAM (1 << 2)
+#define POSIX_SPAWN_SETSCHEDULER  (1 << 3)
+#define POSIX_SPAWN_SETSIGDEF     (1 << 4)
+#define POSIX_SPAWN_SETSIGMASK    (1 << 5)
+
+/****************************************************************************
+ * Type Definitions
+ ****************************************************************************/
+/* "The spawn.h header shall define the posix_spawnattr_t and
+ * posix_spawn_file_actions_t types used in performing spawn operations.
+ */
+
+struct posix_spawnattr_s
+{
+/* To be provided */
+};
+typedef struct posix_spawnattr_s posix_spawnattr_t;
+
+struct posix_spawn_file_actions_s
+{
+/* To be provided */
+};
+typedef struct posix_spawn_file_actions_s posix_spawn_file_actions_t;
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+/* "The following shall be declared as functions and may also be defined as
+ * macros. Function prototypes shall be provided."
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+int posix_spawn(FAR pid_t *, FAR const char *,
+      FAR const posix_spawn_file_actions_t *, FAR const posix_spawnattr_t *,
+      FAR char *const [], FAR char *const []);
+int posix_spawnp(FAR pid_t *, FAR const char *,
+      FAR const posix_spawn_file_actions_t *, FAR const posix_spawnattr_t *,
+      FAR char *const [], FAR char *const []);
+
+int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *);
+int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *);
+
+int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *,
+      int);
+int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *,
+      int, int);
+int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *,
+      int, FAR const char *, int, mode_t);
+
+int posix_spawnattr_init(FAR posix_spawnattr_t *);
+int posix_spawnattr_destroy(FAR posix_spawnattr_t *);
+
+int posix_spawnattr_getflags(FAR const posix_spawnattr_t *, FAR short *);
+int posix_spawnattr_getpgroup(FAR const posix_spawnattr_t *, FAR pid_t *);
+int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *,
+      FAR struct sched_param *);
+int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *,
+      FAR int *);
+int posix_spawnattr_getsigdefault(FAR const posix_spawnattr_t *,
+      FAR sigset_t *);
+int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *,
+      FAR sigset_t *);
+
+int posix_spawnattr_setflags(FAR posix_spawnattr_t *, short);
+int posix_spawnattr_setpgroup(FAR posix_spawnattr_t *, pid_t);
+int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *,
+      FAR const struct sched_param *);
+int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *, int);
+int posix_spawnattr_setsigdefault(FAR posix_spawnattr_t *,
+      FAR const sigset_t *);
+int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *,
+      FAR const sigset_t *);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __INCLUDE_LIBGEN_H */
diff --git a/nuttx/libc/Kconfig b/nuttx/libc/Kconfig
index 699b3ebb2..d739b6351 100644
--- a/nuttx/libc/Kconfig
+++ b/nuttx/libc/Kconfig
@@ -72,15 +72,17 @@ config EOL_IS_EITHER_CRLF
 endchoice
 
 config LIBC_EXECFUNCS
-	bool "Enable exec[l|v] Support"
+	bool "Enable exec[l|v] / posix_spawn() Support"
 	default n
 	depends on !BINFMT_DISABLE
 	---help---
 		Enable support for the exec[l|v] family of functions that can be
-		used to start other programs, terminating the current program.
-		Typical usage is (1) first call vfork() to create a new thread, then
-		(2) call exec[l|v] to replace the new thread with a program from the
-		file system.
+		used to start other programs, terminating the current program and
+		the posix_spawn() familty of functions that can be used start other
+		programs without terminating the current program.  The typical
+		usage of the exec[l|v] functions is (1) first call vfork() to create
+		a new thread, then (2) call exec[l|v] to replace the new thread with
+		a program from the file system.
 
 		NOTE 1: This two step process start is completely unnecessary in
 		NuttX and is provided only for compatibily with Unix systems.  These
@@ -89,9 +91,11 @@ config LIBC_EXECFUNCS
 		the new thread will be terminated by the exec[l|v] call, it really
 		served no purpose other than to suport Unix compatility.
 
-		NOTE 2: Support for exec[l|v] is conditional because is requires
-		additional support for symbol tables that will not be available in
-		the typical system.
+		The posix_spawn() functions do not have this inefficiency.
+
+		NOTE 2: Support for exec[l|v] and posix_spawn() is conditional
+		because they require additional support for symbol tables that
+		will not be available in the typical system.
 
 if LIBC_EXECFUNCS
 
@@ -99,8 +103,8 @@ config EXECFUNCS_SYMTAB
 	string "Symbol table used by exec[l|v]"
 	default "g_symtab"
 	---help---
-		The exec[l|v] functions are wrapper functions that (1) call the non-
-		standard binfmt function 'exec', and then (2) exit(0).  The binfmt
+		The exec[l|v] and posix_spawn() functions are wrapper functions that
+		call the non-standard binfmt function 'exec').  The binfmt
 		function 'exec' needs to have (1) a symbol table that provides the
 		list of symbols exported by the base code, and (2) the number of
 		symbols in that table.  This selection provides the name of that
@@ -110,8 +114,8 @@ config EXECFUNCS_NSYMBOLS
 	int "Number of Symbols in the Table"
 	default 0
 	---help---
-		The exec[l|v] functions are wrapper functions that (1) call the non-
-		standard binfmt function 'exec', and then (2) exit(0).  The binfmt
+		The exec[l|v] and posix_spawn() functions are wrapper functions that
+		call the non-standard binfmt function 'exec').  The binfmt
 		function 'exec' needs to have (1) a symbol table that provides the
 		list of symbols exported by the base code, and (2) the number of
 		symbols in that table.  This selection provides the number of
diff --git a/nuttx/libc/Makefile b/nuttx/libc/Makefile
index 22dbba1d9..a76620585 100644
--- a/nuttx/libc/Makefile
+++ b/nuttx/libc/Makefile
@@ -57,6 +57,7 @@ include time/Make.defs
 include libgen/Make.defs
 include dirent/Make.defs
 include termios/Make.defs
+include spawn/Make.defs
 include queue/Make.defs
 include misc/Make.defs
 
diff --git a/nuttx/libc/spawn/Make.defs b/nuttx/libc/spawn/Make.defs
new file mode 100644
index 000000000..17d9f393a
--- /dev/null
+++ b/nuttx/libc/spawn/Make.defs
@@ -0,0 +1,46 @@
+############################################################################
+# libc/spawn/Make.defs
+#
+#   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Add the spawn C files to the build
+
+ifeq ($(CONFIG_LIBC_EXECFUNCS),y)
+
+CSRCS += 
+
+# Add the spawn directory to the build
+
+DEPPATH += --dep-path spawn
+VPATH += :spawn
+endif
diff --git a/nuttx/tools/README.txt b/nuttx/tools/README.txt
index 5651ff2f0..8df4a7783 100644
--- a/nuttx/tools/README.txt
+++ b/nuttx/tools/README.txt
@@ -445,11 +445,11 @@ kconfig.bat
   only a few options for the Windows user (see the top-level README.txt
   file).
 
-  You can, with some effort, run the the Cygwin mconf tool directly
+  You can, with some effort, run the the Cygwin kconfig-mconf tool directly
   in the CMD.exe shell.  In this case, you do not have to modify the
   .config file, but there are other complexities:  You need to
   temporarily set the Cgywin directories in the PATH variable and
-  then run mconf outside of the Make system.
+  then run kconfig-mconf outside of the Make system.
 
   kconfig.bat is a Windows batch file at tools/kconfig.bat that automates
   these steps.  It is used from the top-level NuttX directory like:
@@ -457,8 +457,8 @@ kconfig.bat
     tools/kconfig menuconfig
 
   NOTE: There is an currently an issue with accessing DOS environment
-  variables from the Cygwin mconf running in the CMD.exe shell.  The
-  following change to the top-level Kconfig file seems to work around
+  variables from the Cygwin kconfig-mconf running in the CMD.exe shell.
+  The following change to the top-level Kconfig file seems to work around
   these problems:
   
      config APPSDIR
diff --git a/nuttx/tools/kconfig.bat b/nuttx/tools/kconfig.bat
index 65ab60506..db01e7515 100755
--- a/nuttx/tools/kconfig.bat
+++ b/nuttx/tools/kconfig.bat
@@ -100,15 +100,15 @@ echo ERROR: Unrecognized action: %action%
 goto :ShowUsage
 
 :DoConfig
-conf Kconfig
+kconfig-conf Kconfig
 goto End
 
 :DoOldConfig
-conf --oldconfig Kconfig
+kconfig-conf --oldconfig Kconfig
 goto End
 
 :DoMenuConfig
-mconf Kconfig
+kconfig-mconf Kconfig
 goto End
 
 :MissingArgument
-- 
cgit v1.2.3


From 51fc8af31f24540bd567bd6d808b8a1fffc4adbc Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Wed, 9 Jan 2013 14:48:55 +0000
Subject: Rename LM3S files, variables, and types from lm3s_ to lm_; Rename
 configuration variables from CONFIG_LM3S_ to CONFIG_LM_

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5497 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/Documentation/NuttxPortingGuide.html         |    2 +-
 nuttx/arch/arm/include/lm/irq.h                    |   18 +-
 nuttx/arch/arm/src/armv7-m/Toolchain.defs          |    8 +-
 nuttx/arch/arm/src/lm/Kconfig                      |   56 +-
 nuttx/arch/arm/src/lm/Make.defs                    |    9 +-
 nuttx/arch/arm/src/lm/chip.h                       |   16 +-
 nuttx/arch/arm/src/lm/chip/lm3s_epi.h              |  113 --
 nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h         |  203 ---
 nuttx/arch/arm/src/lm/chip/lm3s_flash.h            |  128 --
 nuttx/arch/arm/src/lm/chip/lm3s_gpio.h             |  395 -----
 nuttx/arch/arm/src/lm/chip/lm3s_i2c.h              |  247 ---
 nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h           |    2 +-
 nuttx/arch/arm/src/lm/chip/lm3s_ssi.h              |  235 ---
 nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h       |  495 ------
 nuttx/arch/arm/src/lm/chip/lm3s_timer.h            |  125 --
 nuttx/arch/arm/src/lm/chip/lm3s_uart.h             |  347 -----
 nuttx/arch/arm/src/lm/chip/lm_epi.h                |  113 ++
 nuttx/arch/arm/src/lm/chip/lm_ethernet.h           |  203 +++
 nuttx/arch/arm/src/lm/chip/lm_flash.h              |  128 ++
 nuttx/arch/arm/src/lm/chip/lm_gpio.h               |  395 +++++
 nuttx/arch/arm/src/lm/chip/lm_i2c.h                |  247 +++
 nuttx/arch/arm/src/lm/chip/lm_ssi.h                |  235 +++
 nuttx/arch/arm/src/lm/chip/lm_syscontrol.h         |  495 ++++++
 nuttx/arch/arm/src/lm/chip/lm_timer.h              |  125 ++
 nuttx/arch/arm/src/lm/chip/lm_uart.h               |  347 +++++
 nuttx/arch/arm/src/lm/lm3s_dumpgpio.c              |  167 ---
 nuttx/arch/arm/src/lm/lm3s_ethernet.c              | 1472 ------------------
 nuttx/arch/arm/src/lm/lm3s_gpio.c                  |  854 -----------
 nuttx/arch/arm/src/lm/lm3s_gpioirq.c               |  434 ------
 nuttx/arch/arm/src/lm/lm3s_irq.c                   |  458 ------
 nuttx/arch/arm/src/lm/lm3s_lowputc.c               |  309 ----
 nuttx/arch/arm/src/lm/lm3s_serial.c                | 1064 -------------
 nuttx/arch/arm/src/lm/lm3s_ssi.c                   | 1580 --------------------
 nuttx/arch/arm/src/lm/lm3s_start.c                 |  154 --
 nuttx/arch/arm/src/lm/lm3s_syscontrol.c            |  315 ----
 nuttx/arch/arm/src/lm/lm3s_timerisr.c              |  142 --
 nuttx/arch/arm/src/lm/lm3s_vectors.S               |  805 ----------
 nuttx/arch/arm/src/lm/lm_dumpgpio.c                |  167 +++
 nuttx/arch/arm/src/lm/lm_ethernet.c                | 1472 ++++++++++++++++++
 nuttx/arch/arm/src/lm/lm_ethernet.h                |    4 +-
 nuttx/arch/arm/src/lm/lm_gpio.c                    |  854 +++++++++++
 nuttx/arch/arm/src/lm/lm_gpio.h                    |   42 +-
 nuttx/arch/arm/src/lm/lm_gpioirq.c                 |  434 ++++++
 nuttx/arch/arm/src/lm/lm_irq.c                     |  458 ++++++
 nuttx/arch/arm/src/lm/lm_lowputc.c                 |  309 ++++
 nuttx/arch/arm/src/lm/lm_lowputc.h                 |    2 +-
 nuttx/arch/arm/src/lm/lm_serial.c                  | 1064 +++++++++++++
 nuttx/arch/arm/src/lm/lm_ssi.c                     | 1580 ++++++++++++++++++++
 nuttx/arch/arm/src/lm/lm_ssi.h                     |   16 +-
 nuttx/arch/arm/src/lm/lm_start.c                   |  154 ++
 nuttx/arch/arm/src/lm/lm_syscontrol.c              |  315 ++++
 nuttx/arch/arm/src/lm/lm_syscontrol.h              |    6 +-
 nuttx/arch/arm/src/lm/lm_timerisr.c                |  142 ++
 nuttx/arch/arm/src/lm/lm_vectors.S                 |  805 ++++++++++
 nuttx/configs/eagle100/README.txt                  |   38 +-
 nuttx/configs/eagle100/httpd/defconfig             |   42 +-
 nuttx/configs/eagle100/include/board.h             |   12 +-
 nuttx/configs/eagle100/nettest/defconfig           |   42 +-
 nuttx/configs/eagle100/nsh/defconfig               |   42 +-
 nuttx/configs/eagle100/nxflat/defconfig            |   42 +-
 nuttx/configs/eagle100/ostest/defconfig            |   42 +-
 nuttx/configs/eagle100/src/eagle100_internal.h     |    4 +-
 nuttx/configs/eagle100/src/up_boot.c               |   10 +-
 nuttx/configs/eagle100/src/up_ethernet.c           |    8 +-
 nuttx/configs/eagle100/src/up_leds.c               |   20 +-
 nuttx/configs/eagle100/src/up_ssi.c                |   26 +-
 nuttx/configs/eagle100/thttpd/defconfig            |   42 +-
 nuttx/configs/ekk-lm3s9b96/README.txt              |   48 +-
 nuttx/configs/ekk-lm3s9b96/include/board.h         |   12 +-
 nuttx/configs/ekk-lm3s9b96/nsh/defconfig           |   54 +-
 nuttx/configs/ekk-lm3s9b96/ostest/defconfig        |   54 +-
 .../ekk-lm3s9b96/src/ekklm3s9b96_internal.h        |    4 +-
 nuttx/configs/ekk-lm3s9b96/src/up_boot.c           |   10 +-
 nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c       |    8 +-
 nuttx/configs/ekk-lm3s9b96/src/up_leds.c           |   20 +-
 nuttx/configs/ekk-lm3s9b96/src/up_ssi.c            |   26 +-
 nuttx/configs/lm3s6432-s2e/README.txt              |   48 +-
 nuttx/configs/lm3s6432-s2e/include/board.h         |   12 +-
 nuttx/configs/lm3s6432-s2e/nsh/defconfig           |   52 +-
 nuttx/configs/lm3s6432-s2e/ostest/defconfig        |   52 +-
 .../lm3s6432-s2e/src/lm3s6432s2e_internal.h        |    4 +-
 nuttx/configs/lm3s6432-s2e/src/up_boot.c           |   20 +-
 nuttx/configs/lm3s6432-s2e/src/up_ethernet.c       |    8 +-
 nuttx/configs/lm3s6432-s2e/src/up_leds.c           |   22 +-
 nuttx/configs/lm3s6432-s2e/src/up_ssi.c            |   26 +-
 nuttx/configs/lm3s6965-ek/README.txt               |   48 +-
 nuttx/configs/lm3s6965-ek/include/board.h          |   12 +-
 nuttx/configs/lm3s6965-ek/nsh/defconfig            |   48 +-
 nuttx/configs/lm3s6965-ek/nx/defconfig             |   30 +-
 nuttx/configs/lm3s6965-ek/ostest/defconfig         |   30 +-
 .../configs/lm3s6965-ek/src/lm3s6965ek_internal.h  |    4 +-
 nuttx/configs/lm3s6965-ek/src/up_boot.c            |   10 +-
 nuttx/configs/lm3s6965-ek/src/up_ethernet.c        |    8 +-
 nuttx/configs/lm3s6965-ek/src/up_leds.c            |   20 +-
 nuttx/configs/lm3s6965-ek/src/up_oled.c            |   14 +-
 nuttx/configs/lm3s6965-ek/src/up_ssi.c             |   30 +-
 nuttx/configs/lm3s8962-ek/README.txt               |   48 +-
 nuttx/configs/lm3s8962-ek/include/board.h          |   12 +-
 nuttx/configs/lm3s8962-ek/nsh/defconfig            |   54 +-
 nuttx/configs/lm3s8962-ek/nx/defconfig             |   54 +-
 nuttx/configs/lm3s8962-ek/ostest/defconfig         |   54 +-
 .../configs/lm3s8962-ek/src/lm3s8962ek_internal.h  |    4 +-
 nuttx/configs/lm3s8962-ek/src/up_boot.c            |   10 +-
 nuttx/configs/lm3s8962-ek/src/up_ethernet.c        |    8 +-
 nuttx/configs/lm3s8962-ek/src/up_leds.c            |   20 +-
 nuttx/configs/lm3s8962-ek/src/up_oled.c            |   14 +-
 nuttx/configs/lm3s8962-ek/src/up_ssi.c             |   30 +-
 107 files changed, 10838 insertions(+), 10839 deletions(-)
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_epi.h
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_flash.h
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_gpio.h
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_i2c.h
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_ssi.h
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_timer.h
 delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_uart.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_epi.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_ethernet.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_flash.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_gpio.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_i2c.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_ssi.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_syscontrol.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_timer.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_uart.h
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_dumpgpio.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_ethernet.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_gpio.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_gpioirq.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_irq.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_lowputc.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_serial.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_ssi.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_start.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_syscontrol.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_timerisr.c
 delete mode 100644 nuttx/arch/arm/src/lm/lm3s_vectors.S
 create mode 100644 nuttx/arch/arm/src/lm/lm_dumpgpio.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_ethernet.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_gpio.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_gpioirq.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_irq.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_lowputc.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_serial.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_ssi.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_start.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_syscontrol.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_timerisr.c
 create mode 100644 nuttx/arch/arm/src/lm/lm_vectors.S

(limited to 'nuttx/arch')

diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html
index 48fafb89f..b1664f3f0 100644
--- a/nuttx/Documentation/NuttxPortingGuide.html
+++ b/nuttx/Documentation/NuttxPortingGuide.html
@@ -2901,7 +2901,7 @@ extern void up_ledoff(int led);
   <li>
     <p>
     <b>Examples</b>:
-    <code>arch/arm/src/chip/lm3s_serial.c</code>, <code>arch/arm/src/lpc214x/lpc214x_serial.c</code>, <code>arch/z16/src/z16f/z16f_serial.c</code>, etc.
+    <code>arch/arm/src/chip/lm_serial.c</code>, <code>arch/arm/src/lpc214x/lpc214x_serial.c</code>, <code>arch/z16/src/z16f/z16f_serial.c</code>, etc.
     </p>
   </li>
 </ul>
diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h
index a80517e40..136496fef 100644
--- a/nuttx/arch/arm/include/lm/irq.h
+++ b/nuttx/arch/arm/include/lm/irq.h
@@ -308,7 +308,7 @@
  * be disabled in order to reduce the size of the implemenation.
  */
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
 #  define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0)
 #  define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1)
 #  define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2)
@@ -322,7 +322,7 @@
 #  define _NGPIOAIRQS      NR_IRQS
 #endif
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
 #  define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
 #  define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
 #  define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
@@ -336,7 +336,7 @@
 #  define _NGPIOBIRQS      _NGPIOAIRQS
 #endif
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
 #  define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
 #  define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
 #  define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
@@ -350,7 +350,7 @@
 #  define _NGPIOCIRQS      _NGPIOBIRQS
 #endif
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
 #  define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
 #  define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
 #  define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
@@ -364,7 +364,7 @@
 #  define _NGPIODIRQS      _NGPIOCIRQS
 #endif
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
 #  define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
 #  define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
 #  define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
@@ -378,7 +378,7 @@
 #  define _NGPIOEIRQS      _NGPIODIRQS
 #endif
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
 #  define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
 #  define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
 #  define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
@@ -392,7 +392,7 @@
 #  define _NGPIOFIRQS      _NGPIOEIRQS
 #endif
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
 #  define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
 #  define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
 #  define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
@@ -406,7 +406,7 @@
 #  define _NGPIOGIRQS      _NGPIOFIRQS
 #endif
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
 #  define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
 #  define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
 #  define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
@@ -420,7 +420,7 @@
 #  define _NGPIOHIRQS      _NGPIOGIRQS
 #endif
 
-#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
+#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
 #  define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
 #  define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
 #  define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
diff --git a/nuttx/arch/arm/src/armv7-m/Toolchain.defs b/nuttx/arch/arm/src/armv7-m/Toolchain.defs
index d7f2ed77f..45ee9e36c 100644
--- a/nuttx/arch/arm/src/armv7-m/Toolchain.defs
+++ b/nuttx/arch/arm/src/armv7-m/Toolchain.defs
@@ -53,7 +53,7 @@ ifeq ($(filter y, \
 endif
 ifeq ($(filter y, \
       $(CONFIG_KINETIS_BUILDROOT) \
-      $(CONFIG_LM3S_BUILDROOT) \
+      $(CONFIG_LM_BUILDROOT) \
       $(CONFIG_LPC17_BUILDROOT) \
       $(CONFIG_LPC43_BUILDROOT) \
       $(CONFIG_SAM3U_BUILDROOT) \
@@ -77,7 +77,7 @@ ifeq ($(filter y, \
 endif
 ifeq ($(filter y, \
       $(CONFIG_KINETIS_CODESOURCERYL) \
-      $(CONFIG_LM3S_CODESOURCERYL) \
+      $(CONFIG_LM_CODESOURCERYL) \
       $(CONFIG_LPC17_CODESOURCERYL) \
       $(CONFIG_LPC43_CODESOURCERYL) \
       $(CONFIG_SAM3U_CODESOURCERYL) \
@@ -88,7 +88,7 @@ ifeq ($(filter y, \
 endif
 ifeq ($(filter y, \
       $(CONFIG_KINETIS_CODESOURCERYW) \
-      $(CONFIG_LM3S_CODESOURCERYW) \
+      $(CONFIG_LM_CODESOURCERYW) \
       $(CONFIG_LPC17_CODESOURCERYW) \
       $(CONFIG_LPC43_CODESOURCERYW) \
       $(CONFIG_SAM3U_CODESOURCERYW) \
@@ -99,7 +99,7 @@ ifeq ($(filter y, \
 endif
 ifeq ($(filter y, \
       $(CONFIG_KINETIS_DEVKITARM) \
-      $(CONFIG_LM3S_DEVKITARM) \
+      $(CONFIG_LM_DEVKITARM) \
       $(CONFIG_LPC17_DEVKITARM) \
       $(CONFIG_LPC43_DEVKITARM) \
       $(CONFIG_SAM3U_DEVKITARM) \
diff --git a/nuttx/arch/arm/src/lm/Kconfig b/nuttx/arch/arm/src/lm/Kconfig
index 2d2504c7e..5d6bccc92 100644
--- a/nuttx/arch/arm/src/lm/Kconfig
+++ b/nuttx/arch/arm/src/lm/Kconfig
@@ -14,7 +14,7 @@ config ARCH_CHIP_LM3S6918
 	bool "LM3S6918"
 	select ARCH_CORTEXM3
 	select ARCH_CHIP_LM3S
-	select LM3S_HAVE_SSI1
+	select LM_HAVE_SSI1
 
 config ARCH_CHIP_LM3S9B96
 	bool "LM3S9B96"
@@ -46,28 +46,28 @@ config ARCH_CHIP_LM3S
 config ARCH_CHIP_LM4F
 	bool
 
-config LM3S_HAVE_SSI1
+config LM_HAVE_SSI1
 	bool
 
-config LM3S_REVA2
+config LM_REVA2
 	bool "Rev A2"
 	default n
 	---help---
 		Some early silicon returned an increase LDO voltage or 2.75V to work
 		around a PLL bug
 
-config LM3S_DFU
+config LM_DFU
 	bool "DFU"
 	default y
 
 menu "Stellaris Peripheral Support"
 
-config LM3S_UART0
+config LM_UART0
 	bool "UART0"
 	select ARCH_HAVE_UART0
 	default n
 
-config LM3S_UART1
+config LM_UART1
 	bool "UART1"
 	select ARCH_HAVE_UART1
 	default n
@@ -80,12 +80,12 @@ config SSI1_DISABLE
 	bool "Disable SSI1"
 	default y
 
-config LM3S_UART2
+config LM_UART2
 	bool "UART2"
 	select ARCH_HAVE_UART2
 	default n
 
-config LM3S_ETHERNET
+config LM_ETHERNET
 	bool "Stellaris Ethernet"
 	default n
 	---help---
@@ -95,95 +95,95 @@ endmenu
 
 menu "Disable GPIO Interrupts"
 
-config LM3S_DISABLE_GPIOA_IRQS
+config LM_DISABLE_GPIOA_IRQS
 	bool "Disable GPIOA IRQs"
 	default n
 
-config LM3S_DISABLE_GPIOB_IRQS
+config LM_DISABLE_GPIOB_IRQS
 	bool "Disable GPIOB IRQs"
 	default n
 
-config LM3S_DISABLE_GPIOC_IRQS
+config LM_DISABLE_GPIOC_IRQS
 	bool "Disable GPIOC IRQs"
 	default n
 
-config LM3S_DISABLE_GPIOD_IRQS
+config LM_DISABLE_GPIOD_IRQS
 	bool "Disable GPIOD IRQs"
 	default n
 
-config LM3S_DISABLE_GPIOE_IRQS
+config LM_DISABLE_GPIOE_IRQS
 	bool "Disable GPIOE IRQs"
 	default n
 
-config LM3S_DISABLE_GPIOF_IRQS
+config LM_DISABLE_GPIOF_IRQS
 	bool "Disable GPIOF IRQs"
 	default n
 
-config LM3S_DISABLE_GPIOG_IRQS
+config LM_DISABLE_GPIOG_IRQS
 	bool "Disable GPIOG IRQs"
 	default n
 
-config LM3S_DISABLE_GPIOH_IRQS
+config LM_DISABLE_GPIOH_IRQS
 	bool "Disable GPIOH IRQs"
 	default n
 
-config LM3S_DISABLE_GPIOJ_IRQS
+config LM_DISABLE_GPIOJ_IRQS
 	bool "Disable GPIOJ IRQs"
 	default n
 
 endmenu
 
-if LM3S_ETHERNET
+if LM_ETHERNET
 menu "Stellaris Ethernet Configuration"
 
-config LM3S_ETHLEDS
+config LM_ETHLEDS
 	bool "Ethernet LEDs"
 	default n
 	---help---
 	Enable to use Ethernet LEDs on the board.
 
-config LM3S_BOARDMAC
+config LM_BOARDMAC
 	bool "Board MAC"
 	default n
 	---help---
 		If the board-specific logic can provide a MAC address (via
-		lm3s_ethernetmac()), then this should be selected.
+		lm_ethernetmac()), then this should be selected.
 
-config LM3S_ETHHDUPLEX
+config LM_ETHHDUPLEX
 	bool "Force Half Duplex"
 	default n
 	---help---
 		Set to force half duplex operation
 
-config LM3S_ETHNOAUTOCRC
+config LM_ETHNOAUTOCRC
 	bool "Disable auto-CRC"
 	default n
 	---help---
 		Set to suppress auto-CRC generation
 
-config LM3S_ETHNOPAD
+config LM_ETHNOPAD
 	bool "Disable Tx Padding"
 	default n
 	---help---
 		Set to suppress Tx padding
 
-config LM3S_MULTICAST
+config LM_MULTICAST
 	bool "Enable Multicast"
 	default n
 	---help---
 		Set to enable multicast frames
 
-config LM3S_PROMISCUOUS
+config LM_PROMISCUOUS
 	bool "Enable Promiscuous Mode"
 	default n
 	---help---
 		Set to enable promiscuous mode
 
-config LM3S_TIMESTAMP
+config LM_TIMESTAMP
 	bool "Enable Timestamping"
 	default n
 
-config LM3S_BADCRC
+config LM_BADCRC
 	bool "Enable Bad CRC Rejection"
 	default n
 	---help---
diff --git a/nuttx/arch/arm/src/lm/Make.defs b/nuttx/arch/arm/src/lm/Make.defs
index aacbb1c83..e760f7e01 100644
--- a/nuttx/arch/arm/src/lm/Make.defs
+++ b/nuttx/arch/arm/src/lm/Make.defs
@@ -33,7 +33,7 @@
 #
 ############################################################################
 
-HEAD_ASRC	= lm3s_vectors.S
+HEAD_ASRC	= lm_vectors.S
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \
 			  vfork.S
@@ -55,10 +55,9 @@ CMN_CSRCS += up_elf.c
 endif
 
 CHIP_ASRCS	= 
-CHIP_CSRCS	= lm3s_start.c lm3s_syscontrol.c lm3s_irq.c \
-			  lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \
-			  lm3s_serial.c lm3s_ssi.c lm3s_dumpgpio.c
+CHIP_CSRCS	= lm_start.c lm_syscontrol.c lm_irq.c lm_gpio.c lm_gpioirq.c \
+			  lm_timerisr.c lm_lowputc.c lm_serial.c lm_ssi.c lm_dumpgpio.c
 
 ifdef CONFIG_NET
-CHIP_CSRCS	+= lm3s_ethernet.c
+CHIP_CSRCS	+= lm_ethernet.c
 endif
diff --git a/nuttx/arch/arm/src/lm/chip.h b/nuttx/arch/arm/src/lm/chip.h
index 5857b3094..b5974b5dc 100644
--- a/nuttx/arch/arm/src/lm/chip.h
+++ b/nuttx/arch/arm/src/lm/chip.h
@@ -49,14 +49,14 @@
 
 /* Then get all of the register definitions */
 
-#include "chip/lm_memorymap.h"    /* Memory map */
-#include "chip/lm3s_syscontrol.h" /* System control module */
-#include "chip/lm3s_gpio.h"       /* GPIO modules */
-#include "chip/lm3s_uart.h"       /* UART modules */
-#include "chip/lm3s_i2c.h"        /* I2C modules */
-#include "chip/lm3s_ssi.h"        /* SSI modules */
-#include "chip/lm3s_ethernet.h"   /* Ethernet MAC and PHY */
-#include "chip/lm3s_flash.h"      /* FLASH */
+#include "chip/lm_memorymap.h"  /* Memory map */
+#include "chip/lm_syscontrol.h" /* System control module */
+#include "chip/lm_gpio.h"       /* GPIO modules */
+#include "chip/lm_uart.h"       /* UART modules */
+#include "chip/lm_i2c.h"        /* I2C modules */
+#include "chip/lm_ssi.h"        /* SSI modules */
+#include "chip/lm_ethernet.h"   /* Ethernet MAC and PHY */
+#include "chip/lm_flash.h"      /* FLASH */
 
 /* The LM3S69xx only supports 8 priority levels.  The hardware priority mechanism
  * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm/chip/lm3s_epi.h
deleted file mode 100644
index 82fc94f4c..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_epi.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_epi.h
- *
- *   Copyright (C) 2009-2013 Max Neklyudov. All rights reserved.
- *   Author: Max Neklyudov <macscomp@gmail.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* External Peripheral Interface Register Offsets ***********************************/
-
-#define LM3S_EPI_CFG_OFFSET           0x000
-#define LM3S_EPI_SDRAMCFG_OFFSET      0x010
-#define LM3S_EPI_ADDRMAP_OFFSET       0x01C
-#define LM3S_EPI_STAT_OFFSET          0x060
-#define LM3S_EPI_BAUD_OFFSET          0x004
-
-/* External Peripheral Interface Register Addresses *********************************/
-
-#define LM3S_EPI0_CFG                 (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
-#define LM3S_EPI0_SDRAMCFG            (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
-#define LM3S_EPI0_ADDRMAP             (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
-#define LM3S_EPI0_STAT                (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
-#define LM3S_EPI0_BAUD                (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
-
-/* External Peripheral Interface Register Bit Definitions ***************************/
-
-/* EPI Configuration (EPICFG), offset 0x000 */
-
-#define EPI_CFG_MODE_SHIFT            0         /* Bits 3-0: Mode Select */
-#define EPI_CFG_MODE_MASK             (0x1f << EPI_CFG_MODE_SHIFT)
-#  define EPI_CFG_MODE_SDRAM          (0x11 << EPI_CFG_MODE_SHIFT)  /* SDRAM + BLKEN */
-
-/* EPI Address Map (EPIADDRMAP), offset 0x01C */
-
-#define EPI_ADDRMAP_ERADR_SHIFT       0       /* Bits 1-0: External RAM Address */
-#define EPI_ADDRMAP_ERADR_MASK        (0x3 << EPI_ADDRMAP_ERADR_SHIFT)
-#  define EPI_ADDRMAP_ERADR_6         (0x1 << EPI_ADDRMAP_ERADR_SHIFT)
-#  define EPI_ADDRMAP_ERADR_8         (0x2 << EPI_ADDRMAP_ERADR_SHIFT)
-#define EPI_ADDRMAP_ERSZ_SHIFT        2       /* Bits 3-2: External RAM Size */
-#define EPI_ADDRMAP_ERSZ_MASK         (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_256B       (0x0 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_64KB       (0x1 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_16MB       (0x2 << EPI_ADDRMAP_ERSZ_SHIFT)
-#  define EPI_ADDRMAP_ERSZ_512MB      (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
-
-/* EPI Status (EPISTAT), offset 0x060 */
-
-#define EPI_STAT_INITSEQ_SHIFT        6       /* Bits 6: Initialization Sequence */
-#define EPI_STAT_INITSEQ_MASK         (0x1 << EPI_STAT_INITSEQ_SHIFT)
-
-/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */
-
-#define EPI_SDRAMCFG_SIZE_SHIFT       0       /* Bits 1-0: Size of SDRAM */
-#define EPI_SDRAMCFG_SIZE_MASK        (3 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_8MB       (0x0 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_16MB      (0x1 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_32MB      (0x2 << EPI_SDRAMCFG_SIZE_SHIFT)
-#  define EPI_SDRAMCFG_SIZE_64MB      (0x3 << EPI_SDRAMCFG_SIZE_SHIFT)
-#define EPI_SDRAMCFG_RFSH_SHIFT       16      /* Bits 26-16: Refresh Counter */
-#define EPI_SDRAMCFG_RFSH_MASK        (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT)
-#  define EPI_SDRAMCFG_RFSH(n)        ((n) << EPI_SDRAMCFG_RFSH_SHIFT)
-#define EPI_SDRAMCFG_FREQ_SHIFT       30      /* EPI Frequency Range */
-#define EPI_SDRAMCFG_FREQ_MASK        (3 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_0_15MHZ   (0x0 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_15_30MHZ  (0x1 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_30_50MHZ  (0x2 << EPI_SDRAMCFG_FREQ_SHIFT)
-#  define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT)
-
-/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */
-
-#define EPI_BAUD_COUNT0_SHIFT         0
-#define EPI_BAUD_COUNT0_MASK          (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
-#  define EPI_BAUD_COUNT0(n)          ((n) << EPI_BAUD_COUNT0_SHIFT)
-
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h
deleted file mode 100644
index 512e96221..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_ethernet.h
- *
- *   Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/net/mii.h>
-
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Ethernet Controller Register Offsets *********************************************/
-
-/* Ethernet MAC Register Offsets */
-
-#define LM3S_MAC_RIS_OFFSET   0x000 /* Ethernet MAC Raw Interrupt Status */
-#define LM3S_MAC_IACK_OFFSET  0x000 /* Ethernet MAC Acknowledge */
-#define LM3S_MAC_IM_OFFSET    0x004 /* Ethernet MAC Interrupt Mask */
-#define LM3S_MAC_RCTL_OFFSET  0x008 /* Ethernet MAC Receive Control */
-#define LM3S_MAC_TCTL_OFFSET  0x00c /* Ethernet MAC Transmit Control */
-#define LM3S_MAC_DATA_OFFSET  0x010 /* Ethernet MAC Data */
-#define LM3S_MAC_IA0_OFFSET   0x014 /* Ethernet MAC Individual Address 0 */
-#define LM3S_MAC_IA1_OFFSET   0x018 /* Ethernet MAC Individual Address 1 */
-#define LM3S_MAC_THR_OFFSET   0x01c /* Ethernet MAC Threshold */
-#define LM3S_MAC_MCTL_OFFSET  0x020 /* Ethernet MAC Management Control */
-#define LM3S_MAC_MDV_OFFSET   0x024 /* Ethernet MAC Management Divider */
-#define LM3S_MAC_MTXD_OFFSET  0x02c /* Ethernet MAC Management Transmit Data */
-#define LM3S_MAC_MRXD_OFFSET  0x030 /* Ethernet MAC Management Receive Data */
-#define LM3S_MAC_NP_OFFSET    0x034 /* Ethernet MAC Number of Packets */
-#define LM3S_MAC_TR_OFFSET    0x038 /* Ethernet MAC Transmission Request */
-#ifdef LM3S_ETHTS
-#  define LM3S_MAC_TS_OFFSET  0x03c /* Ethernet MAC Time Stamp Configuration */
-#endif
-
-/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
-
-/* Ethernet Controller Register Addresses *******************************************/
-
-#define LM3S_MAC_RIS          (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
-#define LM3S_MAC_IACK         (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
-#define LM3S_MAC_IM           (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
-#define LM3S_MAC_RCTL         (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
-#define LM3S_MAC_TCTL         (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
-#define LM3S_MAC_DATA         (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
-#define LM3S_MAC_IA0          (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
-#define LM3S_MAC_IA1          (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
-#define LM3S_MAC_THR          (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
-#define LM3S_MAC_MCTL         (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
-#define LM3S_MAC_MDV          (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
-#define LM3S_MAC_MTXD         (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
-#define LM3S_MAC_MRXD         (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
-#define LM3S_MAC_NP           (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
-#define LM3S_MAC_TR           (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
-#ifdef LM3S_ETHTS
-#  define LM3S_MAC_TS         (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
-#endif
-
-/* Memory Mapped MII Management Registers */
-
-#define MAC_MII_MCR           (LM3S_ETHCON_BASE + MII_MCR)
-#define MAC_MII_MSR           (LM3S_ETHCON_BASE + MII_MSR)
-#define MAC_MII_PHYID1        (LM3S_ETHCON_BASE + MII_PHYID1)
-#define MAC_MII_PHYID2        (LM3S_ETHCON_BASE + MII_PHYID2)
-#define MAC_MII_ADVERTISE     (LM3S_ETHCON_BASE + MII_ADVERTISE)
-#define MAC_MII_LPA           (LM3S_ETHCON_BASE + MII_LPA)
-#define MAC_MII_EXPANSION     (LM3S_ETHCON_BASE + MII_EXPANSION)
-#define MAC_MII_VSPECIFIC     (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
-#define MAC_MII_INTCS         (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
-#define MAC_MII_DIAGNOSTIC    (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
-#define MAC_MII_XCVRCONTROL   (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
-#define MAC_MII_LEDCONFIG     (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
-#define MAC_MII_MDICONTROL    (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
-
-/* Ethernet Controller Register Bit Definitions *************************************/
-
-/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
-
-#define MAC_RIS_RXINT         (1 << 0)  /* Bit 0:  Packet Received */
-#define MAC_RIS_TXER          (1 << 1)  /* Bit 1:  Transmit Error */
-#define MAC_RIS_TXEMP         (1 << 2)  /* Bit 2:  Transmit FIFO Empty */
-#define MAC_RIS_FOV           (1 << 3)  /* Bit 3:  FIFO Overrun */
-#define MAC_RIS_RXER          (1 << 4)  /* Bit 4:  Receive Error */
-#define MAC_RIS_MDINT         (1 << 5)  /* Bit 5:  MII Transaction Complete */
-#define MAC_RIS_PHYINT        (1 << 6)  /* Bit 6:  PHY Interrupt */
-
-#define MAC_IACK_RXINT        (1 << 0)  /* Bit 0:  Clear Packet Received */
-#define MAC_IACK_TXER         (1 << 1)  /* Bit 1:  Clear Transmit Error */
-#define MAC_IACK_TXEMP        (1 << 2)  /* Bit 2:  Clear Transmit FIFO Empty */
-#define MAC_IACK_FOV          (1 << 3)  /* Bit 3:  Clear FIFO Overrun */
-#define MAC_IACK_RXER         (1 << 4)  /* Bit 4:  Clear Receive Error */
-#define MAC_IACK_MDINT        (1 << 5)  /* Bit 5:  Clear MII Transaction Complete */
-#define MAC_IACK_PHYINT       (1 << 6)  /* Bit 6:  Clear PHY Interrupt */
-
-/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
-
-#define MAC_IM_RXINTM         (1 << 0)  /* Bit 0:  Mask Packet Received */
-#define MAC_IM_TXERM          (1 << 1)  /* Bit 1:  Mask Transmit Error */
-#define MAC_IM_TXEMPM         (1 << 2)  /* Bit 2:  Mask Transmit FIFO Empty */
-#define MAC_IM_FOVM           (1 << 3)  /* Bit 3:  Mask FIFO Overrun */
-#define MAC_IM_RXERM          (1 << 4)  /* Bit 4:  Mask Receive Error */
-#define MAC_IM_MDINTM         (1 << 5)  /* Bit 5:  Mask MII Transaction Complete */
-#define MAC_IM_PHYINTM        (1 << 6)  /* Bit 6:  Mask PHY Interrupt */
-#define MAC_IM_ALLINTS        0x7f
-
-/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
-
-#define MAC_RCTL_RXEN         (1 << 0)  /* Bit 0:  Enable Receiver */
-#define MAC_RCTL_AMUL         (1 << 1)  /* Bit 1:  Enable Multicast Frames */
-#define MAC_RCTL_PRMS         (1 << 2)  /* Bit 2:  Enable Promiscuous Mode */
-#define MAC_RCTL_BADCRC       (1 << 3)  /* Bit 3:  Enable Reject Bad CRC */
-#define MAC_RCTL_RSTFIFO      (1 << 4)  /* Bit 4:  Clear Receive FIFO */
-
-/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
-
-#define MAC_TCTL_TXEN         (1 << 0)  /* Bit 0:  Enable Transmitter */
-#define MAC_TCTL_PADEN        (1 << 1)  /* Bit 1:  Enable Packet Padding */
-#define MAC_TCTL_CRC          (1 << 2)  /* Bit 2:  Enable CRC Generation */
-#define MAC_TCTL_DUPLEX       (1 << 4)  /* Bit 4:  Enable Duplex Mode */
-
-/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
-
-#define MAC_THR_MASK          0x3f      /* Bits 5-0: Threshold Value */
-
-/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
-
-#define MAC_MCTL_START        (1 << 0)  /* Bit 0:  MII Register Transaction Enable */
-#define MAC_MCTL_WRITE        (1 << 1)  /* Bit 1:  MII Register Transaction Type */
-#define MAC_MCTL_REGADR_SHIFT 3         /* Bits 7-3: MII Register Address */
-#define MAC_MCTL_REGADR_MASK  (0x1f << MAC_MCTL_REGADR_SHIFT)
-
-/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
-
-#define MAC_MDV_MASK          0xff      /* Bits 7-0: Clock Divider */
-
-/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
-
-#define MAC_MTXD_MASK         0xffff    /* Bits 15-0: MII Register Transmit Data */
-
-/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
-
-#define MAC_MTRD_MASK         0xffff    /* Bits 15-0: MII Register Receive Data */
-
-/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
-
-#define MAC_NP_MASK           0x3f      /* Bits 5-0: Number of Packets in Receive FIFO */
-
-/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
-
-#define MAC_TR_NEWTX          (1 << 0)  /* Bit 0:  New Transmission */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm/chip/lm3s_flash.h
deleted file mode 100644
index 2f6dc78fa..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_flash.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_flash.h
- *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* FLASH register offsets ***********************************************************/
-
-/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
- * control base address of LM3S_FLASHCON_BASE.
- */
-
-#define LM3S_FLASH_FMA_OFFSET       0x000 /* Flash memory address */
-#define LM3S_FLASH_FMD_OFFSET       0x004 /* Flash memory data */
-#define LM3S_FLASH_FMC_OFFSET       0x008 /* Flash memory control */
-#define LM3S_FLASH_FCRIS_OFFSET     0x00c /* Flash controller raw interrupt status */
-#define LM3S_FLASH_FCIM_OFFSET      0x010 /* Flash controller interrupt mask */
-#define LM3S_FLASH_FCMISC_OFFSET    0x014 /* Flash controller masked interrupt status and clear */ */
-
-/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
- * System Control base address of LM3S_SYSCON_BASE
- */
-
-#define LM3S_FLASH_FMPRE_OFFSET     0x130 /* Flash memory protection read enable */
-#define LM3S_FLASH_FMPPE_OFFSET     0x134 /* Flash memory protection program enable */
-#define LM3S_FLASH_USECRL_OFFSET    0x140 /* USec Reload */
-#define LM3S_FLASH_USERDBG_OFFSET   0x1d0 /* User Debug */
-#define LM3S_FLASH_USERREG0_OFFSET  0x1e0 /* User Register 0 */
-#define LM3S_FLASH_USERREG1_OFFSET  0x1e4 /* User Register 1 */
-#define LM3S_FLASH_FMPRE0_OFFSET    0x200 /* Flash Memory Protection Read Enable 0 */
-#define LM3S_FLASH_FMPRE1_OFFSET    0x204 /* Flash Memory Protection Read Enable 1 */
-#define LM3S_FLASH_FMPRE2_OFFSET    0x208 /* Flash Memory Protection Read Enable 2 */
-#define LM3S_FLASH_FMPRE3_OFFSET    0x20c /* Flash Memory Protection Read Enable 3 */
-#define LM3S_FLASH_FMPPE0_OFFSET    0x400 /* Flash Memory Protection Program Enable 0 */
-#define LM3S_FLASH_FMPPE1_OFFSET    0x404 /* Flash Memory Protection Program Enable 1 */
-#define LM3S_FLASH_FMPPE2_OFFSET    0x408 /* Flash Memory Protection Program Enable 2 */
-#define LM3S_FLASH_FMPPE3_OFFSET    0x40c /*  Flash Memory Protection Program Enable 3 */
-
-/* FLASH register addresses *********************************************************/
-
-/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
- * control base address of LM3S_FLASHCON_BASE.
- */
-
-#define LM3S_FLASH_FMA              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
-#define LM3S_FLASH_FMD              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
-#define LM3S_FLASH_FMC              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
-#define LM3S_FLASH_FCRIS            (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
-#define LM3S_FLASH_FCIM             (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
-#define LM3S_FLASH_FCMISC           (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
-
-/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
- * System Control base address of LM3S_SYSCON_BASE
- */
-
-#define LM3S_FLASH_FMPRE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
-#define LM3S_FLASH_FMPPE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
-#define LM3S_FLASH_USECRL           (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
-#define LM3S_FLASH_USERDBG          (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
-#define LM3S_FLASH_USERREG0         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
-#define LM3S_FLASH_USERREG1         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
-#define LM3S_FLASH_FMPRE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
-#define LM3S_FLASH_FMPRE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
-#define LM3S_FLASH_FMPRE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
-#define LM3S_FLASH_FMPRE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
-#define LM3S_FLASH_FMPPE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
-#define LM3S_FLASH_FMPPE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
-#define LM3S_FLASH_FMPPE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
-#define LM3S_FLASH_FMPPE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
-
-/* FLASH register bit defitiions ****************************************************/
-/* To be provided */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h
deleted file mode 100644
index 2c199dae9..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_gpio.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* GPIO Register Offsets ************************************************************/
-
-#define LM3S_GPIO_DATA_OFFSET         0x000 /* GPIO Data */
-#define LM3S_GPIO_DIR_OFFSET          0x400 /* GPIO Direction */
-#define LM3S_GPIO_IS_OFFSET           0x404 /* GPIO Interrupt Sense */
-#define LM3S_GPIO_IBE_OFFSET          0x408 /* GPIO Interrupt Both Edges */
-#define LM3S_GPIO_IEV_OFFSET          0x40c /* GPIO Interrupt Event */
-#define LM3S_GPIO_IM_OFFSET           0x410 /* GPIO Interrupt Mask */
-#define LM3S_GPIO_RIS_OFFSET          0x414 /* GPIO Raw Interrupt Status */
-#define LM3S_GPIO_MIS_OFFSET          0x418 /* GPIO Masked Interrupt Status */
-#define LM3S_GPIO_ICR_OFFSET          0x41c /* GPIO Interrupt Clear */
-#define LM3S_GPIO_AFSEL_OFFSET        0x420 /* GPIO Alternate Function */
-#define LM3S_GPIO_DR2R_OFFSET         0x500 /* Select GPIO 2-mA Drive Select */
-#define LM3S_GPIO_DR4R_OFFSET         0x504 /* GPIO 4-mA Drive Select */
-#define LM3S_GPIO_DR8R_OFFSET         0x508 /* GPIO 8-mA Drive Select */
-#define LM3S_GPIO_ODR_OFFSET          0x50c /* GPIO Open Drain Select */
-#define LM3S_GPIO_PUR_OFFSET          0x510 /* GPIO Pull-Up Select */
-#define LM3S_GPIO_PDR_OFFSET          0x514 /* GPIO Pull-Down Select */
-#define LM3S_GPIO_SLR_OFFSET          0x518 /* GPIO Slew Rate Control Select */
-#define LM3S_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
-#define LM3S_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
-#define LM3S_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
-#define LM3S_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
-#define LM3S_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
-#define LM3S_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
-#define LM3S_GPIO_PERIPHID7_OFFSET    0xfdc /* GPIO Peripheral Identification 7 */
-#define LM3S_GPIO_PERIPHID0_OFFSET    0xfe0 /* GPIO Peripheral Identification 0 */
-#define LM3S_GPIO_PERIPHID1_OFFSET    0xfe4 /* GPIO Peripheral Identification 1 */
-#define LM3S_GPIO_PERIPHID2_OFFSET    0xfe8 /* GPIO Peripheral Identification 2 */
-#define LM3S_GPIO_PERIPHID3_OFFSET    0xfec /* GPIO Peripheral Identification 3 */
-#define LM3S_GPIO_PCELLID0_OFFSET     0xff0 /* GPIO PrimeCell Identification 0 */
-#define LM3S_GPIO_PCELLID1_OFFSET     0xff4 /* GPIO PrimeCell Identification 1 */
-#define LM3S_GPIO_PCELLID2_OFFSET     0xff8 /* GPIO PrimeCell Identification 2 */
-#define LM3S_GPIO_PCELLID3_OFFSET     0xffc /* GPIO PrimeCell Identification 3*/
-
-/* GPIO Register Addresses **********************************************************/
-
-#define LM3S_GPIOA_DATA               (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOA_DIR                (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOA_IS                 (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOA_IBE                (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOA_IEV                (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOA_IM                 (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOA_RIS                (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOA_MIS                (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOA_ICR                (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOA_AFSEL              (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOA_DR2R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOA_DR4R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOA_DR8R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOA_ODR                (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOA_PUR                (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOA_PDR                (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOA_SLR                (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOA_DEN                (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOA_LOCK               (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOA_CR                 (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOA_PERIPHID4          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOA_PERIPHID5          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOA_PERIPHID6          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOA_PERIPHID7          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOA_PERIPHID0          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOA_PERIPHID1          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOA_PERIPHID2          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOA_PERIPHID3          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOA_PCELLID0           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOA_PCELLID1           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOA_PCELLID2           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOA_PCELLID3           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOB_DATA               (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOB_DIR                (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOB_IS                 (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOB_IBE                (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOB_IEV                (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOB_IM                 (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOB_RIS                (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOB_MIS                (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOB_ICR                (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOB_AFSEL              (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOB_DR2R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOB_DR4R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOB_DR8R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOB_ODR                (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOB_PUR                (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOB_PDR                (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOB_SLR                (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOB_DEN                (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOB_LOCK               (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOB_CR                 (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOB_PERIPHID4          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOB_PERIPHID5          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOB_PERIPHID6          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOB_PERIPHID7          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOB_PERIPHID0          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOB_PERIPHID1          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOB_PERIPHID2          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOB_PERIPHID3          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOB_PCELLID0           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOB_PCELLID1           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOB_PCELLID2           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOB_PCELLID3           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOC_DATA               (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOC_DIR                (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOC_IS                 (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOC_IBE                (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOC_IEV                (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOC_IM                 (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOC_RIS                (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOC_MIS                (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOC_ICR                (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOC_AFSEL              (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOC_DR2R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOC_DR4R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOC_DR8R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOC_ODR                (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOC_PUR                (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOC_PDR                (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOC_SLR                (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOC_DEN                (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOC_LOCK               (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOC_CR                 (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOC_PERIPHID4          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOC_PERIPHID5          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOC_PERIPHID6          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOC_PERIPHID7          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOC_PERIPHID0          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOC_PERIPHID1          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOC_PERIPHID2          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOC_PERIPHID3          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOC_PCELLID0           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOC_PCELLID1           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOC_PCELLID2           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOC_PCELLID3           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOD_DATA               (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOD_DIR                (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOD_IS                 (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOD_IBE                (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOD_IEV                (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOD_IM                 (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOD_RIS                (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOD_MIS                (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOD_ICR                (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOD_AFSEL              (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOD_DR2R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOD_DR4R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOD_DR8R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOD_ODR                (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOD_PUR                (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOD_PDR                (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOD_SLR                (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOD_DEN                (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOD_LOCK               (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOD_CR                 (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOD_PERIPHID4          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOD_PERIPHID5          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOD_PERIPHID6          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOD_PERIPHID7          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOD_PERIPHID0          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOD_PERIPHID1          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOD_PERIPHID2          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOD_PERIPHID3          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOD_PCELLID0           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOD_PCELLID1           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOD_PCELLID2           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOD_PCELLID3           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOE_DATA               (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOE_DIR                (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOE_IS                 (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOE_IBE                (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOE_IEV                (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOE_IM                 (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOE_RIS                (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOE_MIS                (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOE_ICR                (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOE_AFSEL              (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOE_DR2R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOE_DR4R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOE_DR8R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOE_ODR                (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOE_PUR                (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOE_PDR                (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOE_SLR                (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOE_DEN                (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOE_LOCK               (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOE_CR                 (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOE_PERIPHID4          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOE_PERIPHID5          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOE_PERIPHID6          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOE_PERIPHID7          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOE_PERIPHID0          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOE_PERIPHID1          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOE_PERIPHID2          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOE_PERIPHID3          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOE_PCELLID0           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOE_PCELLID1           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOE_PCELLID2           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOE_PCELLID3           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOF_DATA               (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOF_DIR                (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOF_IS                 (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOF_IBE                (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOF_IEV                (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOF_IM                 (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOF_RIS                (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOF_MIS                (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOF_ICR                (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOF_AFSEL              (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOF_DR2R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOF_DR4R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOF_DR8R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOF_ODR                (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOF_PUR                (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOF_PDR                (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOF_SLR                (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOF_DEN                (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOF_LOCK               (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOF_CR                 (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOF_PERIPHID4          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOF_PERIPHID5          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOF_PERIPHID6          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOF_PERIPHID7          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOF_PERIPHID0          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOF_PERIPHID1          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOF_PERIPHID2          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOF_PERIPHID3          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOF_PCELLID0           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOF_PCELLID1           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOF_PCELLID2           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOF_PCELLID3           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOG_DATA               (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOG_DIR                (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOG_IS                 (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOG_IBE                (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOG_IEV                (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOG_IM                 (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOG_RIS                (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOG_MIS                (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOG_ICR                (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOG_AFSEL              (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOG_DR2R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOG_DR4R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOG_DR8R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOG_ODR                (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOG_PUR                (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOG_PDR                (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOG_SLR                (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOG_DEN                (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOG_LOCK               (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOG_CR                 (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOG_PERIPHID4          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOG_PERIPHID5          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOG_PERIPHID6          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOG_PERIPHID7          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOG_PERIPHID0          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOG_PERIPHID1          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOG_PERIPHID2          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOG_PERIPHID3          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOG_PCELLID0           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOG_PCELLID1           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOG_PCELLID2           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOG_PCELLID3           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOH_DATA               (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOH_DIR                (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOH_IS                 (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOH_IBE                (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOH_IEV                (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOH_IM                 (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOH_RIS                (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOH_MIS                (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOH_ICR                (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOH_AFSEL              (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOH_DR2R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOH_DR4R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOH_DR8R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOH_ODR                (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOH_PUR                (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOH_PDR                (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOH_SLR                (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOH_DEN                (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOH_LOCK               (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOH_CR                 (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOH_PERIPHID4          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOH_PERIPHID5          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOH_PERIPHID6          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOH_PERIPHID7          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOH_PERIPHID0          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOH_PERIPHID1          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOH_PERIPHID2          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOH_PERIPHID3          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOH_PCELLID0           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOH_PCELLID1           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOH_PCELLID2           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOH_PCELLID3           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-#define LM3S_GPIOJ_DATA               (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOJ_DIR                (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOJ_IS                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOJ_IBE                (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOJ_IEV                (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOJ_IM                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOJ_RIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOJ_MIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOJ_ICR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOJ_AFSEL              (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOJ_DR2R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOJ_DR4R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOJ_DR8R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOJ_ODR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOJ_PUR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOJ_PDR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOJ_SLR                (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOJ_DEN                (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOJ_LOCK               (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOJ_CR                 (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOJ_PERIPHID4          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOJ_PERIPHID5          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOJ_PERIPHID6          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOJ_PERIPHID7          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOJ_PERIPHID0          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOJ_PERIPHID1          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOJ_PERIPHID2          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOJ_PERIPHID3          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOJ_PCELLID0           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOJ_PCELLID1           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOJ_PCELLID2           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOJ_PCELLID3           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h
deleted file mode 100644
index e029c4f3f..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_i2c.h
- *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* I2C Register Offsets *************************************************************/
-
-/* I2C Master */
-
-#define LM3S_I2CM_SA_OFFSET  0x000 /* I2C Master Slave Address */
-#define LM3S_I2CM_CS_OFFSET  0x004 /* I2C Master Control/Status */
-#define LM3S_I2CM_DR_OFFSET  0x008 /* I2C Master Data */
-#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
-#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
-#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
-#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
-#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
-#define LM3S_I2CM_CR_OFFSET  0x020 /* I2C Master Configuration */
-
-/* I2C Slave */
-
-#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
-#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
-#define LM3S_I2CS_DR_OFFSET  0x008 /* I2C Slave Data */
-#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
-#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
-#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
-#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
-
-/* I2C Register Addresses ***********************************************************/
-
-#if LM3S_NI2C > 0
-
-/* I2C Master */
-
-#define LM3S_I2CM_BASE(n)    (LM3S_I2CM0_BASE + (n)*0x1000)
-#define LM3S_I2CM_SA(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM_CS(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM_DR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM_TPR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM_IMR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM_RIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM_MIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM_ICR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM_CR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
-
-/* I2C Slave */
-
-#define LM3S_I2CS_BASE(n)    (LM3S_I2CS0_BASE + (n)*0x1000)
-#define LM3S_I2CS_OAR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS_CSR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS_DR(n)      (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS_IMR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS_RIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS_MIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS_ICR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
-
-/* I2C0 Master */
-
-#define LM3S_I2CM0_SA        (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM0_CS        (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM0_DR        (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM0_TPR       (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM0_IMR       (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM0_RIS       (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM0_MIS       (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM0_ICR       (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM0_CR        (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
-
-/* I2C0 Slave */
-
-#define LM3S_I2CS0_OAR       (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS0_CSR       (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS0_DR        (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS0_IMR       (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS0_RIS       (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS0_MIS       (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS0_ICR       (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
-
-#if LM3S_NI2C > 1
-
-/* I2C1 Master */
-
-#define LM3S_I2CM1_SA        (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM1_CS        (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM1_DR        (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM1_TPR       (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM1_IMR       (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM1_RIS       (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM1_MIS       (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM1_ICR       (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM1_CR        (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
-
-/* I2C1 Slave */
-
-#define LM3S_I2CS1_OAR       (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS1_CSR       (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS1_DR        (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS1_IMR       (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS1_RIS       (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS1_MIS       (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS1_ICR       (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
-
-#endif
-#endif
-
-/* I2C_Register Bit Definitions *****************************************************/
-
-/* I2C Master Slave Address (I2CM_SA), offset 0x000 */
-
-#define I2CM_SA_RS           (1 << 0)  /* Bit 0:  Receive/Send */
-#define I2CM_SA_SA_SHIFT     1         /* Bits 7-1: I2C Slave Address */
-#define I2CM_SA_SA_MASK      (0x7f << I2CM_SA_SA_SHIFT)
-
-/* I2C Master Control/Status (I2CM_CS), offset 0x004 */
-
-#define I2CM_CS_BUSY         (1 << 0)  /* Bit 0:  I2C Busy (read) */
-#define I2CM_CS_ERROR        (1 << 1)  /* Bit 1:  Error in last bus operation (read) */
-#define I2CM_CS_ADRACK       (1 << 2)  /* Bit 2:  Acknowledge Address (read) */
-#define I2CM_CS_DATACK       (1 << 3)  /* Bit 3:  Acknowledge Data (read) */
-#define I2CM_CS_ARBLST       (1 << 4)  /* Bit 4:  Arbitration Lost (read) */
-#define I2CM_CS_IDLE         (1 << 5)  /* Bit 5:  I2C Idle (read) */
-#define I2CM_CS_BUSBSY       (1 << 6)  /* Bit 6:  Bus Busy (read) */
-
-#define I2CM_CS_RUN          (1 << 0)  /* Bit 0:  I2C Master Enable (write) */
-#define I2CM_CS_START        (1 << 1)  /* Bit 1:  Generate START (write) */
-#define I2CM_CS_STOP         (1 << 2)  /* Bit 2:  Generate STOP (write) */
-#define I2CM_CS_ACK          (1 << 3)  /* Bit 3:  Data Acknowledge Enable (write) */
-
-/* I2C Master Data (I2CM_DR), offset 0x008 */
-
-#define I2CM_DR_MASK         0xff      /* Bits 7-0: Data transferred */
-
-/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */
-
-#define I2CM_TPR_MASK        0xff      /* Bits 7-0: SCL Clock Period */
-
-/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */
-
-#define I2CM_IMR_IM          (1 << 0)  /* Bit 0:  Interrupt Mask */
-
-/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */
-
-#define I2CM_RIS_RIS         (1 << 0)  /* Bit 0:  Raw Interrupt Status */
-
-/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */
-
-#define I2CM_MIS_MIS         (1 << 0)  /* Bit 0:  Masked Interrupt Status */
-
-/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */
-
-#define I2CM_ICR_IC          (1 << 0)  /* Bit 0:  Masked Interrupt Status */
-
-/* I2C Master Configuration (I2CM_CR), offset 0x020 */
-
-#define I2CM_CR_LPBK         (1 << 0)  /* Bit 0:: I2C Loopback */
-#define I2CM_CR_MFE          (1 << 4 ) /* Bit 4:  I2C Master Function Enable */
-#define I2CM_CR_SFE          (1 << 5)  /* Bit 5:  I2C Slave Function Enable */
-
-/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */
-
-#define I2CS_OAR_MASK        0xff      /* Bits 7-0: I2C Slave Own Address */
-
-/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */
-
-#define I2CS_CSR_RREQ        (1 << 0)  /* Bit 0:  Receive Request (read) */
-#define I2CS_CSR_TREQ        (1 << 1)  /* Bit 1:  Transmit Request (read) */
-#define I2CS_CSR_FBR         (1 << 2)  /* Bit 2:  First Byte Received (read) */
-
-#define I2CS_CSR_DA          (1 << 0)  /* Bit 0:  Device Active (write) */
-
-/* I2C Slave Data (I2CS_DR), offset 0x008 */
-
-#define I2CS_DR_MASK         0xff      /* Bits 7-0: Data for Transfer */
-
-/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */
-
-#define I2CM_IMR_DATAIM      (1 << 0)  /* Bit 0:  Data Interrupt Mask */
-
-/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */
-
-#define I2CM_RIS_DATARIS     (1 << 0)  /* Bit 0:  Data Raw Interrupt Status */
-
-/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */
-
-#define I2CM_MIS_DATAMIS     (1 << 0)  /* Bit 0:  Data Masked Interrupt Status */
-
-/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */
-
-#define I2CM_ICR_DATAIC      (1 << 0)  /* Bit 0:  Data Interrupt Clear */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
index 85ec1369a..a478304b0 100644
--- a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
@@ -46,7 +46,7 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
-/* The following lists the input value to lm3s_configgpio to setup the alternate,
+/* The following lists the input value to lm_configgpio to setup the alternate,
  * hardware function for each pin.
  */
 
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h
deleted file mode 100644
index be5a766e5..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_ssi.h
- *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <sys/types.h>
-
-#if LM3S_NSSI > 0
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* SSI register offsets *************************************************************/
-
-#define LM3S_SSI_CR0_OFFSET       0x000 /* SSI Control 0 */
-#define LM3S_SSI_CR1_OFFSET       0x004 /* SSI Control 1 */
-#define LM3S_SSI_DR_OFFSET        0x008 /* SSI Data */
-#define LM3S_SSI_SR_OFFSET        0x00c /* SSI Status */
-#define LM3S_SSI_CPSR_OFFSET      0x010 /* SSI Clock Prescale */
-#define LM3S_SSI_IM_OFFSET        0x014 /* SSI Interrupt Mask */
-#define LM3S_SSI_RIS_OFFSET       0x018 /* SSI Raw Interrupt Status */
-#define LM3S_SSI_MIS_OFFSET       0x01c /* SSI Masked Interrupt Status */
-#define LM3S_SSI_ICR_OFFSET       0x020 /* SSI Interrupt Clear */
-#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
-#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
-#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
-#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
-#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
-#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
-#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
-#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
-#define LM3S_SSI_PCELLID0_OFFSET  0xff0 /* SSI PrimeCell Identification 0 */
-#define LM3S_SSI_PCELLID1_OFFSET  0xff4 /* SSI PrimeCell Identification 1 */
-#define LM3S_SSI_PCELLID2_OFFSET  0xff8 /* SSI PrimeCell Identification 2 */
-#define LM3S_SSI_PCELLID3_OFFSET  0xffc /* SSI PrimeCell Identification 3 */
-
-/* SSI register addresses ***********************************************************/
-
-#define LM3S_SSI0_CR0             (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI0_CR1             (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI0_DR              (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI0_SR              (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI0_CPSR            (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI0_IM              (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI0_RIS             (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI0_MIS             (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI0_ICR             (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI0_PERIPHID4       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI0_PERIPHID5       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI0_PERIPHID6       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI0_PERIPHID7       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI0_PERIPHID0       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI0_PERIPHID1       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI0_PERIPHID2       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI0_PERIPHID3       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI0_PCELLID0        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI0_PCELLID1        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI0_PCELLID2        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI0_PCELLID3        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
-
-#if LM3S_NSSI > 1
-#define LM3S_SSI1_CR0             (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI1_CR1             (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI1_DR              (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI1_SR              (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI1_CPSR            (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI1_IM              (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI1_RIS             (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI1_MIS             (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI1_ICR             (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI1_PERIPHID4       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI1_PERIPHID5       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI1_PERIPHID6       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI1_PERIPHID7       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI1_PERIPHID0       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI1_PERIPHID1       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI1_PERIPHID2       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI1_PERIPHID3       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI1_PCELLID0        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI1_PCELLID1        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI1_PCELLID2        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI1_PCELLID3        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
-
-#define LM3S_SSI_BASE(n)          (LM3S_SSI0_BASE + (n)*0x01000)
-
-#define LM3S_SSI_CR0(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI_CR1(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI_DR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI_SR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI_CPSR(n)          (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI_IM(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI_RIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI_MIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI_ICR(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI_PERIPHID4(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI_PERIPHID5(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI_PERIPHID6(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI_PERIPHID7(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI_PERIPHID0(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI_PERIPHID1(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI_PERIPHID2(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI_PERIPHID3(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI_PCELLID0(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI_PCELLID1(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI_PCELLID2(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI_PCELLID3(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
-#endif /* LM3S_NSSI > 1 */
-
-/* SSI register bit defitiions ******************************************************/
-
-/* SSI Control 0 (SSICR0), offset 0x000 */
-
-#define SSI_CR0_DSS_SHIFT         0         /* Bits 3-0: SSI Data Size Select */
-#define SSI_CR0_DSS_MASK          (0x0f << SSI_CR0_DSS_SHIFT)
-#define   SSI_CR0_DSS(n)          ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
-#define SSI_CR0_FRF_SHIFT         4         /* Bits 5-4: SSI Frame Format Select */
-#define SSI_CR0_FRF_MASK          (3 << SSI_CR0_FRF_SHIFT)
-#define   SSI_CR0_FRF_SPI         (0 << SSI_CR0_FRF_SHIFT)     /* Freescale SPI format */
-#define   SSI_CR0_FRF_SSFF        (1 << SSI_CR0_FRF_SHIFT)     /* TI synchronous serial fram format */
-#define   SSI_CR0_FRF_UWIRE       (2 << SSI_CR0_FRF_SHIFT)     /* MICROWIRE frame format */
-#define SSI_CR0_SPO               (1 << 6)  /* Bit 6:  SSI Serial Clock Polarity */
-#define SSI_CR0_SPH               (1 << 7)  /* Bit 7:  SSI Serial Clock Phase */
-#define SSI_CR0_SCR_SHIFT         8         /* Bits 15-8: SSI Serial Clock Rate */
-#define SSI_CR0_SCR_MASK          (0xff << SSI_CR0_SCR_SHIFT)
-
-/* SSI Control 1 (SSICR1), offset 0x004 */
-
-#define SSI_CR1_LBM               (1 << 0)  /* Bit 0:  SSI Loopback Mode */
-#define SSI_CR1_SSE               (1 << 1)  /* Bit 1:  SSI Synchronous Serial Port Enable */
-#define SSI_CR1_MS                (1 << 2)  /* Bit 2:  SSI Master/Slave Select slave */
-#define SSI_CR1_SOD               (1 << 3)  /* Bit 3:  SSI Slave Mode Output Disable */
-
-/* SSI Data (SSIDR), offset 0x008 */
-
-#define SSI_DR_MASK               0xffff    /* Bits 15-0: SSI data */
-
-/* SSI Status (SSISR), offset 0x00c */
-
-#define SSI_SR_TFE                (1 << 0)  /* Bit 0:  SSI Transmit FIFO Empty */
-#define SSI_SR_TNF                (1 << 1)  /* Bit 1:  SSI Transmit FIFO Not Full */
-#define SSI_SR_RNE                (1 << 2)  /* Bit 2:  SSI Receive FIFO Not Empty */
-#define SSI_SR_RFF                (1 << 3)  /* Bit 3:  SSI Receive FIFO Full */
-#define SSI_SR_BSY                (1 << 4)  /* Bit 4:  SSI Busy Bit */
-
-/* SSI Clock Prescale (SSICPSR), offset 0x010 */
-
-#define SSI_CPSR_DIV_MASK         0xff      /* Bits 7-0: SSI Clock Prescale Divisor */
-
-/* SSI Interrupt Mask (SSIIM), offset 0x014 */
-
-#define SSI_IM_ROR                (1 << 0)  /* Bit 0:  SSI Receive Overrun Interrupt Mask */
-#define SSI_IM_RT                 (1 << 1)  /* Bit 1:  SSI Receive Time-Out Interrupt Mask */
-#define SSI_IM_RX                 (1 << 2)  /* Bit 2:  SSI Receive FIFO Interrupt Mask */
-#define SSI_IM_TX                 (1 << 3)  /* Bit 3:  SSI Transmit FIFO Interrupt Mask */
-
-/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
-
-#define SSI_RIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Raw Interrupt Status */
-#define SSI_RIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Raw Interrupt Status */
-#define SSI_RIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Raw Interrupt Status */
-#define SSI_RIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Raw Interrupt Status */
-
-/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
-
-#define SSI_MIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Masked Interrupt Status */
-#define SSI_MIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Masked Interrupt Status */
-#define SSI_MIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Masked Interrupt Status */
-#define SSI_MIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Masked Interrupt Status */
-
-/* SSI Interrupt Clear (SSIICR), offset 0x020 */
-
-#define SSI_ICR_ROR               (1 << 0)  /* Bit 0: SSI Receive Overrun Interrupt Clear */
-#define SSI_ICR_RT                (1 << 1)  /* Bit 1: SSI Receive Time-Out Interrupt Clear */
-
-/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
-
-#define SSI_PERIPHID_MASK         0xff      /* Bits 7-0: SSI Peripheral ID n */
-
-/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
-
-#define SSI_PCELLID_MASK          0xff      /* Bits 7-0: SSI Prime cell ID */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#endif /* LM3S_NSSI > 0 */
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h
deleted file mode 100644
index 00a222ee3..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_syscontrol.h
- *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* System Control Register Offsets **************************************************/
-
-#define LM3S_SYSCON_DID0_OFFSET       0x000 /* Device Identification 0 */
-#define LM3S_SYSCON_DID1_OFFSET       0x004 /* Device Identification 1 */
-#define LM3S_SYSCON_DC0_OFFSET        0x008 /* Device Capabilities 0 */
-#define LM3S_SYSCON_DC1_OFFSET        0x010 /* Device Capabilities 1 */
-#define LM3S_SYSCON_DC2_OFFSET        0x014 /* Device Capabilities 2 */
-#define LM3S_SYSCON_DC3_OFFSET        0x018 /* Device Capabilities 3 */
-#define LM3S_SYSCON_DC4_OFFSET        0x01c /* Device Capabilities 4 */
-#define LM3S_SYSCON_PBORCTL_OFFSET    0x030 /* Brown-Out Reset Control */
-#define LM3S_SYSCON_LDOPCTL_OFFSET    0x034 /* LDO Power Control */
-#define LM3S_SYSCON_SRCR0_OFFSET      0x040 /* Software Reset Control 0 */
-#define LM3S_SYSCON_SRCR1_OFFSET      0x044 /* Software Reset Control 1 */
-#define LM3S_SYSCON_SRCR2_OFFSET      0x048 /* Software Reset Control 2*/
-#define LM3S_SYSCON_RIS_OFFSET        0x050 /* Raw Interrupt Status */
-#define LM3S_SYSCON_IMC_OFFSET        0x054 /* Interrupt Mask Control */
-#define LM3S_SYSCON_MISC_OFFSET       0x058 /* Masked Interrupt Status and Clear */
-#define LM3S_SYSCON_RESC_OFFSET       0x05c /* Reset Cause */
-#define LM3S_SYSCON_RCC_OFFSET        0x060 /* Run-Mode Clock Configuration */
-#define LM3S_SYSCON_PLLCFG_OFFSET     0x064 /* XTAL to PLL Translation */
-#define LM3S_SYSCON_RCC2_OFFSET       0x070 /* Run-Mode Clock Configuration 2 */
-#define LM3S_SYSCON_RCGC0_OFFSET      0x100 /* Run Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_RCGC1_OFFSET      0x104 /* Run Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_RCGC2_OFFSET      0x108 /* Run Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_SCGC0_OFFSET      0x110 /* Sleep Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_SCGC1_OFFSET      0x114 /* Sleep Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_SCGC2_OFFSET      0x118 /* Sleep Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_DCGC0_OFFSET      0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_DCGC1_OFFSET      0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_DCGC2_OFFSET      0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
-
-/* System Control Register Addresses ************************************************/
-
-#define LM3S_SYSCON_DID0              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
-#define LM3S_SYSCON_DID1              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
-#define LM3S_SYSCON_DC0               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
-#define LM3S_SYSCON_DC1               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
-#define LM3S_SYSCON_DC2               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
-#define LM3S_SYSCON_DC3               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
-#define LM3S_SYSCON_DC4               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
-#define LM3S_SYSCON_PBORCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
-#define LM3S_SYSCON_LDOPCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
-#define LM3S_SYSCON_SRCR0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
-#define LM3S_SYSCON_SRCR1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
-#define LM3S_SYSCON_SRCR2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
-#define LM3S_SYSCON_RIS               (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
-#define LM3S_SYSCON_IMC               (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
-#define LM3S_SYSCON_MISC              (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
-#define LM3S_SYSCON_RESC              (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
-#define LM3S_SYSCON_RCC               (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
-#define LM3S_SYSCON_PLLCFG            (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
-#define LM3S_SYSCON_RCC2              (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
-#define LM3S_SYSCON_RCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
-#define LM3S_SYSCON_RCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
-#define LM3S_SYSCON_RCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
-#define LM3S_SYSCON_SCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
-#define LM3S_SYSCON_SCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
-#define LM3S_SYSCON_SCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
-#define LM3S_SYSCON_DCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
-#define LM3S_SYSCON_DCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
-#define LM3S_SYSCON_DCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
-#define LM3S_SYSCON_DSLPCLKCFG        (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
-
-/* System Control Register Bit Definitions ******************************************/
-
-/* Device Identification 0 (DID0), offset 0x000 */
-
-#define SYSCON_DID0_MINOR_SHIFT       0         /* Bits 7-0: Minor Revision of the device */
-#define SYSCON_DID0_MINOR_MASK        (0xff << SYSCON_DID0_MINOR_SHIFT)
-#define SYSCON_DID0_MAJOR_SHIFT       8         /* Bits 15-8: Major Revision of the device */
-#define SYSCON_DID0_MAJOR_MASK        (0xff << SYSCON_DID0_MAJOR_SHIFT)
-#define SYSCON_DID0_CLASS_SHIFT       16        /* Bits 23-16: Device Class */
-#define SYSCON_DID0_CLASS_MASK        (0xff << SYSCON_DID0_CLASS_SHIFT)
-#define SYSCON_DID0_VER_SHIFT         28        /* Bits 30-28: DID0 Version */
-#define SYSCON_DID0_VER_MASK          (7 << SYSCON_DID0_VER_SHIFT)
-
-/* Device Identification 1 (DID1), offset 0x004 */
-
-#define SYSCON_DID1_QUAL_SHIFT        0         /* Bits 1-0: Qualification Status */
-#define SYSCON_DID1_QUAL_MASK         (0x03 << SYSCON_DID1_QUAL_SHIFT)
-#define SYSCON_DID1_ROHS              (1 << 2)  /* Bit 2: RoHS-Compliance */
-#define SYSCON_DID1_PKG_SHIFT         3 /* Bits 4-3: Package Type */
-#define SYSCON_DID1_PKG_MASK          (0x03 << SYSCON_DID1_PKG_SHIFT)
-#define SYSCON_DID1_TEMP_SHIFT        5         /* Bits 7-5: Temperature Range */
-#define SYSCON_DID1_TEMP_MASK         (0x07 << SYSCON_DID1_TEMP_SHIFT)
-#define SYSCON_DID1_PINCOUNT_SHIFT    13        /* Bits 15-13: Package Pin Count */
-#define SYSCON_DID1_PINCOUNT_MASK     (0x07 << SYSCON_DID1_PINCOUNT_SHIFT)
-#define SYSCON_DID1_PARTNO_SHIFT      16        /* Bits 23-16: Part Number */
-#define SYSCON_DID1_PARTNO_MASK       (0xff << SYSCON_DID1_PARTNO_SHIFT)
-#define SYSCON_DID1_FAM_SHIFT         24        /* Bits 27-24: Family */
-#define SYSCON_DID1_FAM_MASK          (0x0f << SYSCON_DID1_FAM_SHIFT)
-#define SYSCON_DID1_VER_SHIFT         28        /* Bits 31-28:  DID1 Version */
-#define SYSCON_DID1_VER_MASK          (0x0f << SYSCON_DID1_VER_SHIFT)
-
-/* Device Capabilities 0 (DC0), offset 0x008 */
-
-#define SYSCON_DC0_FLASHSZ_SHIFT      0         /* Bits 15-0: FLASH Size */
-#define SYSCON_DC0_FLASHSZ_MASK       (0xffff << SYSCON_DC0_FLASHSZ_SHIFT)
-#define SYSCON_DC0_SRAMSZ_SHIFT       16        /* Bits 31-16: SRAM Size */
-#define SYSCON_DC0_SRAMSZ_MASK        (0xffff << SYSCON_DC0_SRAMSZ_SHIFT)
-
-/* Device Capabilities 1 (DC1), offset 0x010 */
-
-#define SYSCON_DC1_JTAG               (1 << 0)  /* Bit 0: JTAG Present */
-#define SYSCON_DC1_SWD                (1 << 1)  /* Bit 1: SWD Present */
-#define SYSCON_DC1_SWO                (1 << 2)  /* Bit 2: SWO Trace Port Present */
-#define SYSCON_DC1_WDT                (1 << 3)  /* Bit 3: Watchdog Timer Present */
-#define SYSCON_DC1_PLL                (1 << 4)  /* Bit 4: PLL Present */
-#define SYSCON_DC1_TEMPSNS            (1 << 5)  /* Bit 5: Temp Sensor Present */
-#define SYSCON_DC1_HIB                (1 << 6)  /* Bit 6: Hibernation Module Present */
-#define SYSCON_DC1_MPU                (1 << 7)  /* Bit 7: MPU Present */
-#define SYSCON_DC1_MAXADCSPD_SHIFT    8         /* Bits 9-8: Max ADC Speed */
-#define SYSCON_DC1_MAXADCSPD_MASK     (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT)
-#define SYSCON_DC1_ADC                (1 << 16) /* Bit 16: ADC Module Present */
-#define SYSCON_DC1_MINSYSDIV_SHIFT    12        /* Bits 15-12: System Clock Divider Minimum */
-#define SYSCON_DC1_MINSYSDIV_MASK     (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT)
-
-/* Device Capabilities 2 (DC2), offset 0x014 */
-
-#define SYSCON_DC2_UART0              (1 << 0)  /* Bit 0: UART0 Present */
-#define SYSCON_DC2_UART1              (1 << 1)  /* Bit 1: UART1 Present */
-#define SYSCON_DC2_SSI0               (1 << 4)  /* Bit 4: SSI0 Present */
-#define SYSCON_DC2_SSI1               (1 << 5)  /* Bit 5: SSI1 Present */
-#define SYSCON_DC2_I2C0               (1 << 12) /* Bit 12: I2C Module 0 Present */
-#define SYSCON_DC2_I2C1               (1 << 14) /* Bit 14: I2C Module 1 Present */
-#define SYSCON_DC2_TIMER0             (1 << 16) /* Bit 16: Timer 0 Present */
-#define SYSCON_DC2_TIMER1             (1 << 17) /* Bit 17: Timer 1 Present */
-#define SYSCON_DC2_TIMER2             (1 << 18) /* Bit 18: Timer 2 Present */
-#define SYSCON_DC2_TIMER3             (1 << 19) /* Bit 19: Timer 3 Present */
-#define SYSCON_DC2_COMP0              (1 << 24) /* Bit 24: Analog Comparator 0 Present */
-#define SYSCON_DC2_COMP1              (1 << 25) /* Bit 25: Analog Comparator 1 Present */
-
-/* Device Capabilities 3 (DC3), offset 0x018 */
-
-#define SYSCON_DC3_C0MINUS            (1 << 6)  /* Bit 6: C0- Pin Present */
-#define SYSCON_DC3_C0PLUS             (1 << 7)  /* Bit 7: C0+ Pin Present */
-#define SYSCON_DC3_C0O                (1 << 8)  /* Bit 8: C0o Pin Present */
-#define SYSCON_DC3_C1MINUS            (1 << 9)  /* Bit 9: C1- Pin Present */
-#define SYSCON_DC3_C1PLUS             (1 << 10) /* Bit 10: C1+ Pin Present */
-#define SYSCON_DC3_ADC0               (1 << 16) /* Bit 16: ADC0 Pin Present */
-#define SYSCON_DC3_ADC1               (1 << 17) /* Bit 17: ADC1 Pin Present */
-#define SYSCON_DC3_ADC2               (1 << 18) /* Bit 18: ADC2 Pin Present */
-#define SYSCON_DC3_ADC3               (1 << 19) /* Bit 19: ADC3 Pin Present */
-#define SYSCON_DC3_ADC4               (1 << 20) /* Bit 20: ADC4 Pin Present */
-#define SYSCON_DC3_ADC5               (1 << 21) /* Bit 21: ADC5 Pin Present */
-#define SYSCON_DC3_ADC6               (1 << 22) /* Bit 22: ADC6 Pin Present */
-#define SYSCON_DC3_ADC7               (1 << 23) /* Bit 23: ADC7 Pin Present */
-#define SYSCON_DC3_CCP0               (1 << 24) /* Bit 24: CCP0 Pin Present */
-#define SYSCON_DC3_CCP1               (1 << 25) /* Bit 25: CCP1 Pin Present */
-#define SYSCON_DC3_CCP2               (1 << 26) /* Bit 26: CCP2 Pin Present */
-#define SYSCON_DC3_CCP3               (1 << 27) /* Bit 27: CCP3 Pin Present */
-#define SYSCON_DC3_CCP4               (1 << 28) /* Bit 28: CCP4 Pin Present */
-#define SYSCON_DC3_CCP5               (1 << 29) /* Bit 29: CCP5 Pin Present */
-#define SYSCON_DC3_32KHZ              (1 << 31) /* Bit 31: 32KHz Input Clock Available */
-
-/* Device Capabilities 4 (DC4), offset 0x01c */
-
-#define SYSCON_DC4_GPIO(n)            (1 << (n))
-#define SYSCON_DC4_GPIOA              (1 << 0)  /* Bit 0: GPIO Port A Present */
-#define SYSCON_DC4_GPIOB              (1 << 1)  /* Bit 1: GPIO Port B Present */
-#define SYSCON_DC4_GPIOC              (1 << 2)  /* Bit 2: GPIO Port C Present */
-#define SYSCON_DC4_GPIOD              (1 << 3)  /* Bit 3: GPIO Port D Present */
-#define SYSCON_DC4_GPIOE              (1 << 4)  /* Bit 4: GPIO Port E Present */
-#define SYSCON_DC4_GPIOF              (1 << 5)  /* Bit 5: GPIO Port F Present */
-#define SYSCON_DC4_GPIOG              (1 << 6)  /* Bit 6: GPIO Port G Present */
-#define SYSCON_DC4_GPIOH              (1 << 7)  /* Bit 7: GPIO Port H Present */
-#define SYSCON_DC4_EMAC0              (1 << 28) /* Bit 28: Ethernet MAC0 Present */
-#define SYSCON_DC4_EPHY0              (1 << 30) /* Bit 30: Ethernet PHY0 Present */
-
-/* Brown-Out Reset Control (PBORCTL), offset 0x030 */
-
-#define SYSCON_PBORCTL_BORIOR         (1 << 1)  /* Bit 1: BOR Interrupt or Reset */
-
-/* LDO Power Control (LDOPCTL), offset 0x034 */
-
-#define SYSCON_LDOPCTL_VADJ_SHIFT     0         /* Bits 5-0: LDO Output Voltage */
-#define SYSCON_LDOPCTL_VADJ_MASK      (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT)
-#  define SYSCON_LPDOPCTL_2500MV      (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/
-#  define SYSCON_LPDOPCTL_2450MV      (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */
-#  define SYSCON_LPDOPCTL_2400MV      (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */
-#  define SYSCON_LPDOPCTL_2350MV      (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */
-#  define SYSCON_LPDOPCTL_2300MV      (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */
-#  define SYSCON_LPDOPCTL_2250MV      (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */
-#  define SYSCON_LPDOPCTL_2750MV      (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */
-#  define SYSCON_LPDOPCTL_2700MV      (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */
-#  define SYSCON_LPDOPCTL_2650MV      (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */
-#  define SYSCON_LPDOPCTL_2600MV      (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */
-#  define SYSCON_LPDOPCTL_2550MV      (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */
-
-/* Software Reset Control 0 (SRCR0), offset 0x040 */
-
-#define SYSCON_SRCR0_WDT              (1 << 3)  /* Bit 3: WDT Reset Control */
-#define SYSCON_SRCR0_HIB              (1 << 6)  /* Bit 6: HIB Reset Control */
-#define SYSCON_SRCR0_ADC              (1 << 16) /* Bit 16: ADC0 Reset Control */
-
-/* Software Reset Control 1 (SRCR1), offset 0x044 */
-
-#define SYSCON_SRCR1_UART0            (1 << 0)  /* Bit 0: UART0 Reset Control */
-#define SYSCON_SRCR1_UART1            (1 << 1)  /* Bit 1: UART1 Reset Control */
-#define SYSCON_SRCR1_SSI0             (1 << 4)  /* Bit 4: SSI0 Reset Control1 */
-#define SYSCON_SRCR1_SSI1             (1 << 5)  /* Bit 5: SSI1 Reset Control */
-#define SYSCON_SRCR1_I2C0             (1 << 12) /* Bit 12: I2C0 Reset Control */
-#define SYSCON_SRCR1_I2C1             (1 << 14) /* Bit 14: I2C1 Reset Control */
-#define SYSCON_SRCR1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Reset Control */
-#define SYSCON_SRCR1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Reset Control */
-#define SYSCON_SRCR1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Reset Control */
-#define SYSCON_SRCR1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Reset Control */
-#define SYSCON_SRCR1_COMP0            (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */
-#define SYSCON_SRCR1_COMP1            (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */
-
-/* Software Reset Control 2 (SRCR2), offset 0x048 */
-
-#define SYSCON_SRCR2_GPIO(n)          (1 << (n))
-#define SYSCON_SRCR2_GPIOA            (1 << 0)  /* Bit 0: Port A Reset Control */
-#define SYSCON_SRCR2_GPIOB            (1 << 1)  /* Bit 1: Port B Reset Control */
-#define SYSCON_SRCR2_GPIOC            (1 << 2)  /* Bit 2: Port C Reset Control */
-#define SYSCON_SRCR2_GPIOD            (1 << 3)  /* Bit 3: Port D Reset Control */
-#define SYSCON_SRCR2_GPIOE            (1 << 4)  /* Bit 4: Port E Reset Control */
-#define SYSCON_SRCR2_GPIOF            (1 << 5)  /* Bit 5: Port F Reset Control */
-#define SYSCON_SRCR2_GPIOG            (1 << 6)  /* Bit 6: Port G Reset Control */
-#define SYSCON_SRCR2_GPIOH            (1 << 7)  /* Bit 7: Port H Reset Control */
-#define SYSCON_SRCR2_EMAC0            (1 << 28) /* Bit 28: MAC0 Reset Control */
-#define SYSCON_SRCR2_EPHY0            (1 << 30) /* Bit 30: PHY0 Reset Control */
-
-/* Raw Interrupt Status (RIS), offset 0x050 */
-
-#define SYSCON_RIS_BORRIS             (1 << 1)  /* Bit 1: Brown-Out Reset Raw Interrupt Status */
-#define SYSCON_RIS_PLLLRIS            (1 << 6)  /* Bit 6: PLL Lock Raw Interrupt Status */
-
-/* Interrupt Mask Control (IMC), offset 0x054 */
-
-#define SYSCON_IMC_BORIM              (1 << 1)  /* Bit 1: Brown-Out Reset Interrupt Mask */
-#define SYSCON_IMC_PLLLIM             (1 << 6)  /* Bit 6: PLL Lock Interrupt Mask */
-
-/* Masked Interrupt Status and Clear (MISC), offset 0x058 */
-
-#define SYSCON_MISC_BORMIS            (1 << 1)  /* Bit 1: BOR Masked Interrupt Status */
-#define SYSCON_MISC_PLLLMIS           (1 << 6)  /* Bit 6: PLL Lock Masked Interrupt Status */
-
-/* Reset Cause (RESC), offset 0x05C */
-
-#define SYSCON_RESC_EXT               (1 << 0)  /* Bit 0: External Reset */
-#define SYSCON_RESC_POR               (1 << 1)  /* Bit 1: Power-On Reset */
-#define SYSCON_RESC_BOR               (1 << 2)  /* Bit 2: Brown-Out Reset */
-#define SYSCON_RESC_WDT               (1 << 3)  /* Bit 3: Watchdog Timer Reset */
-#define SYSCON_RESC_SW                (1 << 4)  /* Bit 4: Software Reset */
-
-/* Run-Mode Clock Configuration (RCC), offset 0x060 */
-
-#define SYSCON_RCC_MOSCDIS            (1 << 0)  /* Bit 0: Main Oscillator Disable */
-#define SYSCON_RCC_IOSCDIS            (1 << 1)  /* Bit 1: Internal Oscillator Disable */
-#define SYSCON_RCC_OSCSRC_SHIFT       4         /* Bits 5-4: Oscillator Source */
-#define SYSCON_RCC_OSCSRC_MASK        (0x03 << SYSCON_RCC_OSCSRC_SHIFT)
-#  define SYSCON_RCC_OSCSRC_MOSC      (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */
-#  define SYSCON_RCC_OSCSRC_IOSC      (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */
-#  define SYSCON_RCC_OSCSRC_IOSC4     (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */
-#  define SYSCON_RCC_OSCSRC_30KHZ     (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */
-#define SYSCON_RCC_XTAL_SHIFT         6         /* Bits 10-6: Crystal Value */
-#define SYSCON_RCC_XTAL_MASK          (0x1f << SYSCON_RCC_XTAL_SHIFT)
-#  define SYSCON_RCC_XTAL1000KHZ      ( 0 << SYSCON_RCC_XTAL_SHIFT)  /* 1.0000MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL1843KHZ      ( 1 << SYSCON_RCC_XTAL_SHIFT)  /* 1.8432MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL2000KHZ      ( 2 << SYSCON_RCC_XTAL_SHIFT)  /* 2.0000MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL2580KHZ      ( 3 << SYSCON_RCC_XTAL_SHIFT)  /* 2.4576MHz (NO PLL) */
-#  define SYSCON_RCC_XTAL3580KHZ      ( 4 << SYSCON_RCC_XTAL_SHIFT)  /* 3.5795MHz */
-#  define SYSCON_RCC_XTAL3686KHZ      ( 5 << SYSCON_RCC_XTAL_SHIFT)  /* 3.6864MHz */
-#  define SYSCON_RCC_XTAL4000KHZ      ( 6 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0000MHz */
-#  define SYSCON_RCC_XTAL4096KHZ      ( 7 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0960MHz */
-#  define SYSCON_RCC_XTAL4915KHZ      ( 8 << SYSCON_RCC_XTAL_SHIFT)  /* 4.9152MHz */
-#  define SYSCON_RCC_XTAL5000KHZ      ( 9 << SYSCON_RCC_XTAL_SHIFT)  /* 5.0000MHz */
-#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT)  /* 5.1200MHz */
-#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT)  /* 6.0000MHz (reset value) */
-#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT)  /* 6.1440MHz */
-#  define SYSCON_RCC_XTAL7373KHZ      (13 << SYSCON_RCC_XTAL_SHIFT)  /* 7.3728MHz */
-#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT)  /* 8.0000MHz */
-#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT)  /* 8.1920MHz */
-#ifdef CONFIG_ARCH_CHIP_LM3S9B96
-#  define SYSCON_RCC_XTAL10000KHZ     (16 << SYSCON_RCC_XTAL_SHIFT)  /* 10.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL12000KHZ     (17 << SYSCON_RCC_XTAL_SHIFT)  /* 12.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL12888KHZ     (18 << SYSCON_RCC_XTAL_SHIFT)  /* 12.288 MHz */
-#  define SYSCON_RCC_XTAL13560KHZ     (19 << SYSCON_RCC_XTAL_SHIFT)  /* 13.56 MHz */
-#  define SYSCON_RCC_XTAL14318KHZ     (20 << SYSCON_RCC_XTAL_SHIFT)  /* 14.31818 MHz */
-#  define SYSCON_RCC_XTAL16000KHZ     (21 << SYSCON_RCC_XTAL_SHIFT)  /* 16.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL16384KHZ     (22 << SYSCON_RCC_XTAL_SHIFT)  /* 16.384 MHz */
-#endif
-#define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
-#define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
-#define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */
-#define SYSCON_RCC_SYSDIV_SHIFT       23        /* Bits 26-23: System Clock Divisor */
-#define SYSCON_RCC_SYSDIV_MASK        (0x0f << SYSCON_RCC_SYSDIV_SHIFT)
-#  define SYSCON_RCC_SYSDIV(n)        (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT)
-#define SYSCON_RCC_ACG                (1 << 27) /* Bit 27: Auto Clock Gating */
-
-/* XTAL to PLL Translation (PLLCFG), offset 0x064 */
-
-#define SYSCON_PLLCFG_F_SHIFT         5         /* Bits 13-5: PLL F Value */
-#define SYSCON_PLLCFG_F_MASK          (0x1ff << SYSCON_PLLCFG_F_SHIFT)
-#define SYSCON_PLLCFG_R_SHIFT         0         /* Bits 4-0: PLL R Value  */
-#define SYSCON_PLLCFG_R_MASK          (0x1f << SYSCON_PLLCFG_R_SHIFT)
-
-/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */
-
-#define SYSCON_RCC2_OSCSRC2_SHIFT     4         /* Bits 6-4: Oscillator Source */
-#define SYSCON_RCC2_OSCSRC2_MASK      (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT)
-#  define SYSCON_RCC2_OSCSRC2_MOSC    (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */
-#  define SYSCON_RCC2_OSCSRC2_IOSC    (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */
-#  define SYSCON_RCC2_OSCSRC2_IOSC4   (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */
-#  define SYSCON_RCC2_OSCSRC2_30KHZ   (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */
-#  define SYSCON_RCC2_OSCSRC2_32KHZ   (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */
-#define SYSCON_RCC2_BYPASS2           (1 << 11) /* Bit 11: Bypass PLL */
-#define SYSCON_RCC2_PWRDN2            (1 << 13) /* Bit 13: Power-Down PLL */
-#define SYSCON_RCC2_SYSDIV2_SHIFT     23        /* Bits 28-23: System Clock Divisor */
-#define SYSCON_RCC2_SYSDIV2_MASK      (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT)
-#  define SYSCON_RCC2_SYSDIV(n)       ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT)
-#define SYSCON_RCC2_USERCC2           (1 << 31) /* Bit 31: Use RCC2 When set */
-
-/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */
-
-#define SYSCON_RCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_RCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_RCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_RCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_RCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */
-
-#define SYSCON_RCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_RCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_RCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_RCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_RCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_RCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_RCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_RCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_RCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */
-
-#define SYSCON_RCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_RCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_RCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_RCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_RCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_RCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_RCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_RCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_RCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_RCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_RCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */
-
-#define SYSCON_SCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_SCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_SCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_SCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_SCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */
-
-#define SYSCON_SCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_SCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_SCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_SCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_SCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_SCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_SCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_SCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_SCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */
-
-#define SYSCON_SCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_SCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_SCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_SCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_SCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_SCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_SCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_SCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_SCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_SCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_SCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */
-
-#define SYSCON_DCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
-#define SYSCON_DCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
-#define SYSCON_DCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
-#define SYSCON_DCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT)
-#define SYSCON_DCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
-
-/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */
-
-#define SYSCON_DCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
-#define SYSCON_DCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
-#define SYSCON_DCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
-#define SYSCON_DCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
-#define SYSCON_DCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
-#define SYSCON_DCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
-#define SYSCON_DCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
-#define SYSCON_DCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
-#define SYSCON_DCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
-
-/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */
-
-#define SYSCON_DCGC2_GPIO(n)          (1 << (n))
-#define SYSCON_DCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
-#define SYSCON_DCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
-#define SYSCON_DCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
-#define SYSCON_DCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
-#define SYSCON_DCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
-#define SYSCON_DCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
-#define SYSCON_DCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
-#define SYSCON_DCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
-#define SYSCON_DCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
-#define SYSCON_DCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
-
-/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */
-
-#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */
-#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK  (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT)
-#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT   4 /* Bits 6-4: Clock Source */
-#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK    (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm/chip/lm3s_timer.h
deleted file mode 100644
index 6be963cc3..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_timer.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_timer.h
- *
- *   Copyright (C) 2012 Max Nekludov. All rights reserved.
- *   Author: Max Nekludov <macscomp@gmail.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Timer register offsets ***********************************************************/
-
-#define TIMER_GPTMCFG_OFFSET             0x000
-#define TIMER_GPTMTAMR_OFFSET            0x004
-#define TIMER_GPTMCTL_OFFSET             0x00C
-#define TIMER_GPTMIMR_OFFSET             0x018
-#define TIMER_GPTMRIS_OFFSET             0x01C
-#define TIMER_GPTMICR_OFFSET             0x024
-#define TIMER_GPTMTAILR_OFFSET           0x028
-#define TIMER_GPTMTAR_OFFSET             0x048
-
-/* SSI register addresses ***********************************************************/
-
-#define LM3S_TIMER_BASE(n)               (LM3S_TIMER0_BASE + (n)*0x01000)
-
-#define LM3S_TIMER_GPTMCFG(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
-#define LM3S_TIMER_GPTMTAMR(n)           (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
-#define LM3S_TIMER_GPTMCTL(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
-#define LM3S_TIMER_GPTMIMR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
-#define LM3S_TIMER_GPTMRIS(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
-#define LM3S_TIMER_GPTMICR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
-#define LM3S_TIMER_GPTMTAILR(n)          (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
-#define LM3S_TIMER_GPTMTAR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
-
-/* SSI register bit defitiions ******************************************************/
-
-/* GPTM Configuration (GPTMCFG), offset 0x000 */
-
-#define TIMER_GPTMCFG_CFG_SHIFT          0    /* Bits 2-0: GPTM Configuration */
-#define TIMER_GPTM_CFG_MASK              (0x07 << TIMER_GPTMCFG_CFG_SHIFT)
-#define   TIMER_GPTMCFG_CFG_32           (0 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit timer configuration */
-#define   TIMER_GPTMCFG_CFG_RTC          (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit real-time clock (RTC) counter configuration */
-#define   TIMER_GPTMCFG_CFG_16           (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 16-bit timer configuration */
-
-/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */
-
-#define TIMER_GPTMTAMR_TAMR_SHIFT        0    /* Bits 1-0: GPTM Timer A Mode */
-#define TIMER_GPTMTAMR_TAMR_MASK         (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT)
-#define   TIMER_GPTMTAMR_TAMR_ONESHOT    (1 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* One-Shot Timer mode */
-#define   TIMER_GPTMTAMR_TAMR_PERIODIC   (2 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Periodic Timer mode */
-#define   TIMER_GPTMTAMR_TAMR_CAPTURE    (3 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Capture mode */
-#define TIMER_GPTMTAMR_TACMR_SHIFT       2    /* Bits 2:   GPTM Timer A Capture Mode */
-#define TIMER_GPTMTAMR_TACMR_MASK        (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT)
-#define   TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Count mode */
-#define   TIMER_GPTMTAMR_TACMR_EDGETIME  (1 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Time mode */
-#define TIMER_GPTMTAMR_TAAMS_SHIFT       3    /* Bits 3:   GPTM Timer A Alternate Mode Select */
-#define TIMER_GPTMTAMR_TAAMS_MASK        (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT)
-#define   TIMER_GPTMTAMR_TAAMS_CAPTURE   (0 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* Capture mode is enabled */
-#define   TIMER_GPTMTAMR_TAAMS_PWM       (1 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* PWM mode is enabled */
-#define TIMER_GPTMTAMR_TACDIR_SHIFT      4    /* Bits 4:   GPTM Timer A Count Direction */
-#define TIMER_GPTMTAMR_TACDIR_MASK       (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT)
-#define   TIMER_GPTMTAMR_TACDIR_DOWN     (0 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* The timer counts down */
-#define   TIMER_GPTMTAMR_TACDIR_UP       (1 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* When in one-shot or periodic mode, the timer counts up */
-#define TIMER_GPTMTAMR_TAMIE_SHIFT       5    /* Bits 5:   GPTM Timer A Match Interrupt Enable */
-#define TIMER_GPTMTAMR_TAMIE_MASK        (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT)
-
-/* GPTM Control (GPTMCTL), offset 0x00C */
-
-#define TIMER_GPTMCTL_TAEN_SHIFT         0    /* Bits 0:   GPTM Timer A Enable */
-#define TIMER_GPTMCTL_TAEN_MASK          (0x01 << TIMER_GPTMCTL_TAEN_SHIFT)
-#define TIMER_GPTMCTL_TASTALL_SHIFT      1    /* Bits 1:   GPTM Timer A Stall Enable */
-#define TIMER_GPTMCTL_TASTALL_MASK       (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT)
-
-/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */
-
-#define TIMER_GPTMIMR_TATOIM_SHIFT       0    /* Bits 0:   GPTM Timer A Time-Out Interrupt Mask */
-#define TIMER_GPTMIMR_TATOIM_MASK        (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT)
-
-/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */
-
-#define TIMER_GPTMRIS_TATORIS_SHIFT      0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt */
-#define TIMER_GPTMRIS_TATORIS_MASK       (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT)
-
-/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */
-
-#define TIMER_GPTMICR_TATOCINT_SHIFT     0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt Clear*/
-#define TIMER_GPTMICR_TATOCINT_MASK      (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
-
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm/chip/lm3s_uart.h
deleted file mode 100644
index 98dcbce12..000000000
--- a/nuttx/arch/arm/src/lm/chip/lm3s_uart.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/chip/lm3s_uart.h
- *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* UART register offsets ************************************************************/
-
-#define LM3S_UART_DR_OFFSET        0x000 /* UART Data */
-#define LM3S_UART_RSR_OFFSET       0x004 /* UART Receive Status */
-#define LM3S_UART_ECR_OFFSET       0x004 /* UART Error Clear */
-#define LM3S_UART_FR_OFFSET        0x018 /* UART Flag */
-#define LM3S_UART_ILPR_OFFSET      0x020 /* UART IrDA Low-Power Register */
-#define LM3S_UART_IBRD_OFFSET      0x024 /* UART Integer Baud-Rate Divisor*/
-#define LM3S_UART_FBRD_OFFSET      0x028 /* UART Fractional Baud-Rate Divisor */
-#define LM3S_UART_LCRH_OFFSET      0x02c /* UART Line Control */
-#define LM3S_UART_CTL_OFFSET       0x030 /* UART Control */
-#define LM3S_UART_IFLS_OFFSET      0x034 /* UART Interrupt FIFO Level Select */
-#define LM3S_UART_IM_OFFSET        0x038 /* UART Interrupt Mask */
-#define LM3S_UART_RIS_OFFSET       0x03c /* UART Raw Interrupt Status */
-#define LM3S_UART_MIS_OFFSET       0x040 /* UART Masked Interrupt Status */
-#define LM3S_UART_ICR_OFFSET       0x044 /* UART Interrupt Clear */
-#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
-#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
-#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
-#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
-#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
-#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
-#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
-#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
-#define LM3S_UART_PCELLID0_OFFSET  0xff0 /* UART PrimeCell Identification 0 */
-#define LM3S_UART_PCELLID1_OFFSET  0xff4 /* UART PrimeCell Identification 1 */
-#define LM3S_UART_PCELLID2_OFFSET  0xff8 /* UART PrimeCell Identification 2 */
-#define LM3S_UART_PCELLID3_OFFSET  0xffc /* UART PrimeCell Identification 3 */
-
-/* UART register addresses **********************************************************/
-
-#define LM3S_UART_BASE(n)          (LM3S_UART0_BASE + (n)*0x01000)
-
-#define LM3S_UART_DR(n)            (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
-#define LM3S_UART_RSR(n)           (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART_ECR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART_FR(n)            (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
-#define LM3S_UART_ILPR(n)          (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART_IBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART_FBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART_LCRH(n)          (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART_CTL(n)           (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART_IFLS(n)          (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART_IM(n)            (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
-#define LM3S_UART_RIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART_MIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART_ICR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART_PERIPHID4(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART_PERIPHID5(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART_PERIPHID6(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART_PERIPHID7(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART_PERIPHID0(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART_PERIPHID1(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART_PERIPHID2(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART_PERIPHID3(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART_PCELLID0(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART_PCELLID1(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART_PCELLID2(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART_PCELLID3(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
-
-#define LM3S_UART0_DR              (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
-#define LM3S_UART0_RSR             (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART0_ECR             (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART0_FR              (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
-#define LM3S_UART0_ILPR            (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART0_IBRD            (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART0_FBRD            (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART0_LCRH            (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART0_CTL             (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART0_IFLS            (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART0_IM              (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
-#define LM3S_UART0_RIS             (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART0_MIS             (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART0_ICR             (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART0_PERIPHID4       (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART0_PERIPHID5       (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART0_PERIPHID6       (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART0_PERIPHID7       (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART0_PERIPHID0       (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART0_PERIPHID1       (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART0_PERIPHID2       (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART0_PERIPHID3       (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART0_PCELLID0        (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART0_PCELLID1        (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART0_PCELLID2        (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART0_PCELLID3        (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
-
-#define LM3S_UART1_DR              (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
-#define LM3S_UART1_RSR             (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART1_ECR             (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART1_FR              (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
-#define LM3S_UART1_ILPR            (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART1_IBRD            (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART1_FBRD            (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART1_LCRH            (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART1_CTL             (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART1_IFLS            (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART1_IM              (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
-#define LM3S_UART1_RIS             (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART1_MIS             (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART1_ICR             (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART1_PERIPHID4       (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART1_PERIPHID5       (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART1_PERIPHID6       (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART1_PERIPHID7       (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART1_PERIPHID0       (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART1_PERIPHID1       (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART1_PERIPHID2       (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART1_PERIPHID3       (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART1_PCELLID0        (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART1_PCELLID1        (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART1_PCELLID2        (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART1_PCELLID3        (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
-
-/* UART register bit settings *******************************************************/
-
-/* UART Data (DR), offset 0x000 */
-
-#define UART_DR_DATA_SHIFT         0         /* Bits 7-0: Data Transmitted or Received */
-#define UART_DR_DATA_MASK          (0xff << UART_DR_DATA_SHIFT)
-#define UART_DR_FE                 (1 << 8)  /* Bit 8:  UART Framing Error */
-#define UART_DR_PE                 (1 << 9)  /* Bit 9:  UART Parity Error */
-#define UART_DR_BE                 (1 << 10) /* Bit 10: UART Break Error */
-#define UART_DR_OE                 (1 << 11) /* Bit 11: UART Overrun Error */
-
-/* UART Receive Status (RSR), offset 0x004 */
-
-#define UART_RSR_FE                (1 << 0)  /* Bit 0:  UART Framing Error */
-#define UART_RSR_PE                (1 << 1)  /* Bit 1:  UART Parity Error */
-#define UART_RSR_BE                (1 << 2)  /* Bit 2:  UART Break Error */
-#define UART_RSR_OE                (1 << 3)  /* Bit 3:  UART Overrun Error */
-
-/* UART Error Clear (ECR), offset 0x004 */
-/* Writing any value to this register clears pending error indications */
-
-/* UART Flag (FR), offset 0x018 */
-
-#define UART_FR_BUSY               (1 << 3)  /* Bit 3:  UART Busy */
-#define UART_FR_RXFE               (1 << 4)  /* Bit 4:  UART Receive FIFO Empty */
-#define UART_FR_TXFF               (1 << 5)  /* Bit 5:  UART Transmit FIFO Full */
-#define UART_FR_RXFF               (1 << 6)  /* Bit 6:  UART Receive FIFO Full */
-#define UART_FR_TXFE               (1 << 7)  /* Bit 7:  UART Transmit FIFO Empty */
-
-/* UART IrDA Low-Power Register (ILPR), offset 0x020 */
-
-#define UART_ILPR_DVSR_MASK        (0xff)    /* Bits 7-0: IrDA Low-Power Divisor */
-
-/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */
-
-#define UART_IBRD_DIVINT_MASK      (0xffff)  /* Bits 15-0: Integer Baud-Rate Divisor */
-
-/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */
-
-#define UART_FBRD_DIVFRAC_MASK     (0x3f)    /* Bits 5-0: Fractional Baud-Rate Divisor */
-
-/* Register 7: UART Line Control (LCRH), offset 0x02C */
-
-#define UART_LCRH_BRK              (1 << 0)  /* Bit 0:  UART Send Break */
-#define UART_LCRH_PEN              (1 << 1)  /* Bit 1:  UART Parity Enable */
-#define UART_LCRH_EPS              (1 << 2)  /* Bit 2:  UART Even Parity Select */
-#define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
-#define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
-#define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
-#define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
-#  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
-#  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
-#  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
-#  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
-#define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
-
-/* UART Control (CTL), offset 0x030 */
-
-#define UART_CTL_UARTEN            (1 << 0)  /* Bit 0:  UART Enable */
-#define UART_CTL_SIREN             (1 << 1)  /* Bit 1:  UART SIR Enable */
-#define UART_CTL_SIRLP             (1 << 2)  /* Bit 2:  UART SIR Low Power Mode */
-#define UART_CTL_LBE               (1 << 7)  /* Bit 7:  UART Loop Back Enable */
-#define UART_CTL_TXE               (1 << 8)  /* Bit 8:  UART Transmit Enable */
-#define UART_CTL_RXE               (1 << 9)  /* Bit 9:  UART Receive Enable */
-
-/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */
-
-#define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */
-#define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
-#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
-#define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 5-3: UART Receive Interrupt FIFO Level Select */
-#define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
-#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
-
-/* UART Interrupt Mask (IM), offset 0x038 */
-
-#define UART_IM_RXIM               (1 << 4)  /* Bit 4:  UART Receive Interrupt Mask */
-#define UART_IM_TXIM               (1 << 5)  /* Bit 5:  UART Transmit Interrupt Mask */
-#define UART_IM_RTIM               (1 << 6)  /* Bit 6:  UART Receive Time-Out Interrupt Mask */
-#define UART_IM_FEIM               (1 << 7)  /* Bit 7:  UART Framing Error Interrupt Mask */
-#define UART_IM_PEIM               (1 << 8)  /* Bit 8:  UART Parity Error Interrupt Mask */
-#define UART_IM_BEIM               (1 << 9)  /* Bit 9:  UART Break Error Interrupt Mask */
-#define UART_IM_OEIM               (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */
-
-
-/* UART Raw Interrupt Status (RIS), offset 0x03c */
-
-#define UART_RIS_RXRIS             (1 << 4)  /* Bit 4:  UART Receive Raw Interrupt Status */
-#define UART_RIS_TXRIS             (1 << 5)  /* Bit 5:  UART Transmit Raw Interrupt Status */
-#define UART_RIS_RTRIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Raw Interrupt Status */
-#define UART_RIS_FERIS             (1 << 7)  /* Bit 7:  UART Framing Error Raw Interrupt Status */
-#define UART_RIS_PERIS             (1 << 8)  /* Bit 8:  UART Parity Error Raw Interrupt Status */
-#define UART_RIS_BERIS             (1 << 9)  /* Bit 9:  UART Break Error Raw Interrupt Status */
-#define UART_RIS_OERIS             (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */
-
-/* UART Masked Interrupt Status (MIS), offset 0x040 */
-
-#define UART_MIS_RXMIS             (1 << 4)  /* Bit 4:  UART Receive Masked Interrupt Status */
-#define UART_MIS_TXMIS             (1 << 5)  /* Bit 5:  UART Transmit Masked Interrupt Status */
-#define UART_MIS_RTMIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Masked Interrupt Status */
-#define UART_MIS_FEMIS             (1 << 7)  /* Bit 7:  UART Framing Error Masked Interrupt Status */
-#define UART_MIS_PEMIS             (1 << 8)  /* Bit 8:  UART Parity Error Masked Interrupt Status */
-#define UART_MIS_BEMIS             (1 << 9)  /* Bit 9:  UART Break Error Masked Interrupt Status */
-#define UART_MIS_OEMIS             (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */
-
-/* UART Interrupt Clear (ICR), offset 0x044 */
-
-#define UART_ICR_RXIC             (1 << 4)  /* Bit 4:  Receive Interrupt Clear */
-#define UART_ICR_TXIC             (1 << 5)  /* Bit 5:  Transmit Interrupt Clear */
-#define UART_ICR_RTIC             (1 << 6)  /* Bit 6:  Receive Time-Out Interrupt Clear */
-#define UART_ICR_FEIC             (1 << 7)  /* Bit 7:  Framing Error Interrupt Clear */
-#define UART_ICR_PEIC             (1 << 8)  /* Bit 8:  Parity Error Interrupt Clear */
-#define UART_ICR_BEIC             (1 << 9)  /* Bit 9:  Break Error Interrupt Clear */
-#define UART_ICR_OEIC             (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
- */
-
-/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
-
-#define UART_PERIPHID4_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
-
-/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
-
-#define UART_PERIPHID5_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
-
-/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
-
-#define UART_PERIPHID6_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
-
-/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
-
-#define UART_PERIPHID7_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
-
-/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
-
-#define UART_PERIPHID0_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
-
-/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
-
-#define UART_PERIPHID1_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
-
-/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
-
-#define UART_PERIPHID2_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
-
-/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
-
-#define UART_PERIPHID3_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
-
-/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
-
-#define UART_CELLID0_MASK         (0xff)    /* UART PrimeCell ID Register[7:0] */
-
-/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
-
-#define UART_CELLID1_MASK         (0xff)    /* UART PrimeCell ID Register[15:8] */
-
-/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
-
-#define UART_CELLID02MASK         (0xff)    /* UART PrimeCell ID Register[23:16] */
-
-/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
-
-#define UART_CELLID3_MASK         (0xff)    /* UART PrimeCell ID Register[31:24] */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_epi.h b/nuttx/arch/arm/src/lm/chip/lm_epi.h
new file mode 100644
index 000000000..e36986079
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_epi.h
@@ -0,0 +1,113 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_epi.h
+ *
+ *   Copyright (C) 2009-2013 Max Neklyudov. All rights reserved.
+ *   Author: Max Neklyudov <macscomp@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* External Peripheral Interface Register Offsets ***********************************/
+
+#define LM3S_EPI_CFG_OFFSET           0x000
+#define LM3S_EPI_SDRAMCFG_OFFSET      0x010
+#define LM3S_EPI_ADDRMAP_OFFSET       0x01C
+#define LM3S_EPI_STAT_OFFSET          0x060
+#define LM3S_EPI_BAUD_OFFSET          0x004
+
+/* External Peripheral Interface Register Addresses *********************************/
+
+#define LM3S_EPI0_CFG                 (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
+#define LM3S_EPI0_SDRAMCFG            (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
+#define LM3S_EPI0_ADDRMAP             (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
+#define LM3S_EPI0_STAT                (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
+#define LM3S_EPI0_BAUD                (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
+
+/* External Peripheral Interface Register Bit Definitions ***************************/
+
+/* EPI Configuration (EPICFG), offset 0x000 */
+
+#define EPI_CFG_MODE_SHIFT            0         /* Bits 3-0: Mode Select */
+#define EPI_CFG_MODE_MASK             (0x1f << EPI_CFG_MODE_SHIFT)
+#  define EPI_CFG_MODE_SDRAM          (0x11 << EPI_CFG_MODE_SHIFT)  /* SDRAM + BLKEN */
+
+/* EPI Address Map (EPIADDRMAP), offset 0x01C */
+
+#define EPI_ADDRMAP_ERADR_SHIFT       0       /* Bits 1-0: External RAM Address */
+#define EPI_ADDRMAP_ERADR_MASK        (0x3 << EPI_ADDRMAP_ERADR_SHIFT)
+#  define EPI_ADDRMAP_ERADR_6         (0x1 << EPI_ADDRMAP_ERADR_SHIFT)
+#  define EPI_ADDRMAP_ERADR_8         (0x2 << EPI_ADDRMAP_ERADR_SHIFT)
+#define EPI_ADDRMAP_ERSZ_SHIFT        2       /* Bits 3-2: External RAM Size */
+#define EPI_ADDRMAP_ERSZ_MASK         (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_256B       (0x0 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_64KB       (0x1 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_16MB       (0x2 << EPI_ADDRMAP_ERSZ_SHIFT)
+#  define EPI_ADDRMAP_ERSZ_512MB      (0x3 << EPI_ADDRMAP_ERSZ_SHIFT)
+
+/* EPI Status (EPISTAT), offset 0x060 */
+
+#define EPI_STAT_INITSEQ_SHIFT        6       /* Bits 6: Initialization Sequence */
+#define EPI_STAT_INITSEQ_MASK         (0x1 << EPI_STAT_INITSEQ_SHIFT)
+
+/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */
+
+#define EPI_SDRAMCFG_SIZE_SHIFT       0       /* Bits 1-0: Size of SDRAM */
+#define EPI_SDRAMCFG_SIZE_MASK        (3 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_8MB       (0x0 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_16MB      (0x1 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_32MB      (0x2 << EPI_SDRAMCFG_SIZE_SHIFT)
+#  define EPI_SDRAMCFG_SIZE_64MB      (0x3 << EPI_SDRAMCFG_SIZE_SHIFT)
+#define EPI_SDRAMCFG_RFSH_SHIFT       16      /* Bits 26-16: Refresh Counter */
+#define EPI_SDRAMCFG_RFSH_MASK        (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT)
+#  define EPI_SDRAMCFG_RFSH(n)        ((n) << EPI_SDRAMCFG_RFSH_SHIFT)
+#define EPI_SDRAMCFG_FREQ_SHIFT       30      /* EPI Frequency Range */
+#define EPI_SDRAMCFG_FREQ_MASK        (3 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_0_15MHZ   (0x0 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_15_30MHZ  (0x1 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_30_50MHZ  (0x2 << EPI_SDRAMCFG_FREQ_SHIFT)
+#  define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT)
+
+/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */
+
+#define EPI_BAUD_COUNT0_SHIFT         0
+#define EPI_BAUD_COUNT0_MASK          (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
+#  define EPI_BAUD_COUNT0(n)          ((n) << EPI_BAUD_COUNT0_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h
new file mode 100644
index 000000000..46a101005
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h
@@ -0,0 +1,203 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_ethernet.h
+ *
+ *   Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/net/mii.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Ethernet Controller Register Offsets *********************************************/
+
+/* Ethernet MAC Register Offsets */
+
+#define LM3S_MAC_RIS_OFFSET   0x000 /* Ethernet MAC Raw Interrupt Status */
+#define LM3S_MAC_IACK_OFFSET  0x000 /* Ethernet MAC Acknowledge */
+#define LM3S_MAC_IM_OFFSET    0x004 /* Ethernet MAC Interrupt Mask */
+#define LM3S_MAC_RCTL_OFFSET  0x008 /* Ethernet MAC Receive Control */
+#define LM3S_MAC_TCTL_OFFSET  0x00c /* Ethernet MAC Transmit Control */
+#define LM3S_MAC_DATA_OFFSET  0x010 /* Ethernet MAC Data */
+#define LM3S_MAC_IA0_OFFSET   0x014 /* Ethernet MAC Individual Address 0 */
+#define LM3S_MAC_IA1_OFFSET   0x018 /* Ethernet MAC Individual Address 1 */
+#define LM3S_MAC_THR_OFFSET   0x01c /* Ethernet MAC Threshold */
+#define LM3S_MAC_MCTL_OFFSET  0x020 /* Ethernet MAC Management Control */
+#define LM3S_MAC_MDV_OFFSET   0x024 /* Ethernet MAC Management Divider */
+#define LM3S_MAC_MTXD_OFFSET  0x02c /* Ethernet MAC Management Transmit Data */
+#define LM3S_MAC_MRXD_OFFSET  0x030 /* Ethernet MAC Management Receive Data */
+#define LM3S_MAC_NP_OFFSET    0x034 /* Ethernet MAC Number of Packets */
+#define LM3S_MAC_TR_OFFSET    0x038 /* Ethernet MAC Transmission Request */
+#ifdef LM3S_ETHTS
+#  define LM3S_MAC_TS_OFFSET  0x03c /* Ethernet MAC Time Stamp Configuration */
+#endif
+
+/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
+
+/* Ethernet Controller Register Addresses *******************************************/
+
+#define LM3S_MAC_RIS          (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
+#define LM3S_MAC_IACK         (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
+#define LM3S_MAC_IM           (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
+#define LM3S_MAC_RCTL         (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
+#define LM3S_MAC_TCTL         (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
+#define LM3S_MAC_DATA         (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
+#define LM3S_MAC_IA0          (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
+#define LM3S_MAC_IA1          (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
+#define LM3S_MAC_THR          (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
+#define LM3S_MAC_MCTL         (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
+#define LM3S_MAC_MDV          (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
+#define LM3S_MAC_MTXD         (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
+#define LM3S_MAC_MRXD         (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
+#define LM3S_MAC_NP           (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
+#define LM3S_MAC_TR           (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
+#ifdef LM3S_ETHTS
+#  define LM3S_MAC_TS         (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
+#endif
+
+/* Memory Mapped MII Management Registers */
+
+#define MAC_MII_MCR           (LM3S_ETHCON_BASE + MII_MCR)
+#define MAC_MII_MSR           (LM3S_ETHCON_BASE + MII_MSR)
+#define MAC_MII_PHYID1        (LM3S_ETHCON_BASE + MII_PHYID1)
+#define MAC_MII_PHYID2        (LM3S_ETHCON_BASE + MII_PHYID2)
+#define MAC_MII_ADVERTISE     (LM3S_ETHCON_BASE + MII_ADVERTISE)
+#define MAC_MII_LPA           (LM3S_ETHCON_BASE + MII_LPA)
+#define MAC_MII_EXPANSION     (LM3S_ETHCON_BASE + MII_EXPANSION)
+#define MAC_MII_VSPECIFIC     (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
+#define MAC_MII_INTCS         (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
+#define MAC_MII_DIAGNOSTIC    (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
+#define MAC_MII_XCVRCONTROL   (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
+#define MAC_MII_LEDCONFIG     (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
+#define MAC_MII_MDICONTROL    (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
+
+/* Ethernet Controller Register Bit Definitions *************************************/
+
+/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
+
+#define MAC_RIS_RXINT         (1 << 0)  /* Bit 0:  Packet Received */
+#define MAC_RIS_TXER          (1 << 1)  /* Bit 1:  Transmit Error */
+#define MAC_RIS_TXEMP         (1 << 2)  /* Bit 2:  Transmit FIFO Empty */
+#define MAC_RIS_FOV           (1 << 3)  /* Bit 3:  FIFO Overrun */
+#define MAC_RIS_RXER          (1 << 4)  /* Bit 4:  Receive Error */
+#define MAC_RIS_MDINT         (1 << 5)  /* Bit 5:  MII Transaction Complete */
+#define MAC_RIS_PHYINT        (1 << 6)  /* Bit 6:  PHY Interrupt */
+
+#define MAC_IACK_RXINT        (1 << 0)  /* Bit 0:  Clear Packet Received */
+#define MAC_IACK_TXER         (1 << 1)  /* Bit 1:  Clear Transmit Error */
+#define MAC_IACK_TXEMP        (1 << 2)  /* Bit 2:  Clear Transmit FIFO Empty */
+#define MAC_IACK_FOV          (1 << 3)  /* Bit 3:  Clear FIFO Overrun */
+#define MAC_IACK_RXER         (1 << 4)  /* Bit 4:  Clear Receive Error */
+#define MAC_IACK_MDINT        (1 << 5)  /* Bit 5:  Clear MII Transaction Complete */
+#define MAC_IACK_PHYINT       (1 << 6)  /* Bit 6:  Clear PHY Interrupt */
+
+/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
+
+#define MAC_IM_RXINTM         (1 << 0)  /* Bit 0:  Mask Packet Received */
+#define MAC_IM_TXERM          (1 << 1)  /* Bit 1:  Mask Transmit Error */
+#define MAC_IM_TXEMPM         (1 << 2)  /* Bit 2:  Mask Transmit FIFO Empty */
+#define MAC_IM_FOVM           (1 << 3)  /* Bit 3:  Mask FIFO Overrun */
+#define MAC_IM_RXERM          (1 << 4)  /* Bit 4:  Mask Receive Error */
+#define MAC_IM_MDINTM         (1 << 5)  /* Bit 5:  Mask MII Transaction Complete */
+#define MAC_IM_PHYINTM        (1 << 6)  /* Bit 6:  Mask PHY Interrupt */
+#define MAC_IM_ALLINTS        0x7f
+
+/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
+
+#define MAC_RCTL_RXEN         (1 << 0)  /* Bit 0:  Enable Receiver */
+#define MAC_RCTL_AMUL         (1 << 1)  /* Bit 1:  Enable Multicast Frames */
+#define MAC_RCTL_PRMS         (1 << 2)  /* Bit 2:  Enable Promiscuous Mode */
+#define MAC_RCTL_BADCRC       (1 << 3)  /* Bit 3:  Enable Reject Bad CRC */
+#define MAC_RCTL_RSTFIFO      (1 << 4)  /* Bit 4:  Clear Receive FIFO */
+
+/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
+
+#define MAC_TCTL_TXEN         (1 << 0)  /* Bit 0:  Enable Transmitter */
+#define MAC_TCTL_PADEN        (1 << 1)  /* Bit 1:  Enable Packet Padding */
+#define MAC_TCTL_CRC          (1 << 2)  /* Bit 2:  Enable CRC Generation */
+#define MAC_TCTL_DUPLEX       (1 << 4)  /* Bit 4:  Enable Duplex Mode */
+
+/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
+
+#define MAC_THR_MASK          0x3f      /* Bits 5-0: Threshold Value */
+
+/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
+
+#define MAC_MCTL_START        (1 << 0)  /* Bit 0:  MII Register Transaction Enable */
+#define MAC_MCTL_WRITE        (1 << 1)  /* Bit 1:  MII Register Transaction Type */
+#define MAC_MCTL_REGADR_SHIFT 3         /* Bits 7-3: MII Register Address */
+#define MAC_MCTL_REGADR_MASK  (0x1f << MAC_MCTL_REGADR_SHIFT)
+
+/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
+
+#define MAC_MDV_MASK          0xff      /* Bits 7-0: Clock Divider */
+
+/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
+
+#define MAC_MTXD_MASK         0xffff    /* Bits 15-0: MII Register Transmit Data */
+
+/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
+
+#define MAC_MTRD_MASK         0xffff    /* Bits 15-0: MII Register Receive Data */
+
+/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
+
+#define MAC_NP_MASK           0x3f      /* Bits 5-0: Number of Packets in Receive FIFO */
+
+/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
+
+#define MAC_TR_NEWTX          (1 << 0)  /* Bit 0:  New Transmission */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_flash.h b/nuttx/arch/arm/src/lm/chip/lm_flash.h
new file mode 100644
index 000000000..0d4808526
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_flash.h
@@ -0,0 +1,128 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_flash.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* FLASH register offsets ***********************************************************/
+
+/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
+ * control base address of LM3S_FLASHCON_BASE.
+ */
+
+#define LM3S_FLASH_FMA_OFFSET       0x000 /* Flash memory address */
+#define LM3S_FLASH_FMD_OFFSET       0x004 /* Flash memory data */
+#define LM3S_FLASH_FMC_OFFSET       0x008 /* Flash memory control */
+#define LM3S_FLASH_FCRIS_OFFSET     0x00c /* Flash controller raw interrupt status */
+#define LM3S_FLASH_FCIM_OFFSET      0x010 /* Flash controller interrupt mask */
+#define LM3S_FLASH_FCMISC_OFFSET    0x014 /* Flash controller masked interrupt status and clear */ */
+
+/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
+ * System Control base address of LM3S_SYSCON_BASE
+ */
+
+#define LM3S_FLASH_FMPRE_OFFSET     0x130 /* Flash memory protection read enable */
+#define LM3S_FLASH_FMPPE_OFFSET     0x134 /* Flash memory protection program enable */
+#define LM3S_FLASH_USECRL_OFFSET    0x140 /* USec Reload */
+#define LM3S_FLASH_USERDBG_OFFSET   0x1d0 /* User Debug */
+#define LM3S_FLASH_USERREG0_OFFSET  0x1e0 /* User Register 0 */
+#define LM3S_FLASH_USERREG1_OFFSET  0x1e4 /* User Register 1 */
+#define LM3S_FLASH_FMPRE0_OFFSET    0x200 /* Flash Memory Protection Read Enable 0 */
+#define LM3S_FLASH_FMPRE1_OFFSET    0x204 /* Flash Memory Protection Read Enable 1 */
+#define LM3S_FLASH_FMPRE2_OFFSET    0x208 /* Flash Memory Protection Read Enable 2 */
+#define LM3S_FLASH_FMPRE3_OFFSET    0x20c /* Flash Memory Protection Read Enable 3 */
+#define LM3S_FLASH_FMPPE0_OFFSET    0x400 /* Flash Memory Protection Program Enable 0 */
+#define LM3S_FLASH_FMPPE1_OFFSET    0x404 /* Flash Memory Protection Program Enable 1 */
+#define LM3S_FLASH_FMPPE2_OFFSET    0x408 /* Flash Memory Protection Program Enable 2 */
+#define LM3S_FLASH_FMPPE3_OFFSET    0x40c /*  Flash Memory Protection Program Enable 3 */
+
+/* FLASH register addresses *********************************************************/
+
+/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
+ * control base address of LM3S_FLASHCON_BASE.
+ */
+
+#define LM3S_FLASH_FMA              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
+#define LM3S_FLASH_FMD              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
+#define LM3S_FLASH_FMC              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
+#define LM3S_FLASH_FCRIS            (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
+#define LM3S_FLASH_FCIM             (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
+#define LM3S_FLASH_FCMISC           (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
+
+/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
+ * System Control base address of LM3S_SYSCON_BASE
+ */
+
+#define LM3S_FLASH_FMPRE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
+#define LM3S_FLASH_FMPPE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
+#define LM3S_FLASH_USECRL           (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
+#define LM3S_FLASH_USERDBG          (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
+#define LM3S_FLASH_USERREG0         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
+#define LM3S_FLASH_USERREG1         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
+#define LM3S_FLASH_FMPRE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
+#define LM3S_FLASH_FMPRE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
+#define LM3S_FLASH_FMPRE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
+#define LM3S_FLASH_FMPRE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
+#define LM3S_FLASH_FMPPE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
+#define LM3S_FLASH_FMPPE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
+#define LM3S_FLASH_FMPPE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
+#define LM3S_FLASH_FMPPE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
+
+/* FLASH register bit defitiions ****************************************************/
+/* To be provided */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_gpio.h b/nuttx/arch/arm/src/lm/chip/lm_gpio.h
new file mode 100644
index 000000000..4ca8e8ff9
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_gpio.h
@@ -0,0 +1,395 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_gpio.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* GPIO Register Offsets ************************************************************/
+
+#define LM3S_GPIO_DATA_OFFSET         0x000 /* GPIO Data */
+#define LM3S_GPIO_DIR_OFFSET          0x400 /* GPIO Direction */
+#define LM3S_GPIO_IS_OFFSET           0x404 /* GPIO Interrupt Sense */
+#define LM3S_GPIO_IBE_OFFSET          0x408 /* GPIO Interrupt Both Edges */
+#define LM3S_GPIO_IEV_OFFSET          0x40c /* GPIO Interrupt Event */
+#define LM3S_GPIO_IM_OFFSET           0x410 /* GPIO Interrupt Mask */
+#define LM3S_GPIO_RIS_OFFSET          0x414 /* GPIO Raw Interrupt Status */
+#define LM3S_GPIO_MIS_OFFSET          0x418 /* GPIO Masked Interrupt Status */
+#define LM3S_GPIO_ICR_OFFSET          0x41c /* GPIO Interrupt Clear */
+#define LM3S_GPIO_AFSEL_OFFSET        0x420 /* GPIO Alternate Function */
+#define LM3S_GPIO_DR2R_OFFSET         0x500 /* Select GPIO 2-mA Drive Select */
+#define LM3S_GPIO_DR4R_OFFSET         0x504 /* GPIO 4-mA Drive Select */
+#define LM3S_GPIO_DR8R_OFFSET         0x508 /* GPIO 8-mA Drive Select */
+#define LM3S_GPIO_ODR_OFFSET          0x50c /* GPIO Open Drain Select */
+#define LM3S_GPIO_PUR_OFFSET          0x510 /* GPIO Pull-Up Select */
+#define LM3S_GPIO_PDR_OFFSET          0x514 /* GPIO Pull-Down Select */
+#define LM3S_GPIO_SLR_OFFSET          0x518 /* GPIO Slew Rate Control Select */
+#define LM3S_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
+#define LM3S_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
+#define LM3S_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
+#define LM3S_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
+#define LM3S_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
+#define LM3S_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
+#define LM3S_GPIO_PERIPHID7_OFFSET    0xfdc /* GPIO Peripheral Identification 7 */
+#define LM3S_GPIO_PERIPHID0_OFFSET    0xfe0 /* GPIO Peripheral Identification 0 */
+#define LM3S_GPIO_PERIPHID1_OFFSET    0xfe4 /* GPIO Peripheral Identification 1 */
+#define LM3S_GPIO_PERIPHID2_OFFSET    0xfe8 /* GPIO Peripheral Identification 2 */
+#define LM3S_GPIO_PERIPHID3_OFFSET    0xfec /* GPIO Peripheral Identification 3 */
+#define LM3S_GPIO_PCELLID0_OFFSET     0xff0 /* GPIO PrimeCell Identification 0 */
+#define LM3S_GPIO_PCELLID1_OFFSET     0xff4 /* GPIO PrimeCell Identification 1 */
+#define LM3S_GPIO_PCELLID2_OFFSET     0xff8 /* GPIO PrimeCell Identification 2 */
+#define LM3S_GPIO_PCELLID3_OFFSET     0xffc /* GPIO PrimeCell Identification 3*/
+
+/* GPIO Register Addresses **********************************************************/
+
+#define LM3S_GPIOA_DATA               (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOA_DIR                (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOA_IS                 (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOA_IBE                (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOA_IEV                (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOA_IM                 (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOA_RIS                (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOA_MIS                (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOA_ICR                (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOA_AFSEL              (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOA_DR2R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOA_DR4R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOA_DR8R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOA_ODR                (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOA_PUR                (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOA_PDR                (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOA_SLR                (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOA_DEN                (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOA_LOCK               (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOA_CR                 (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOA_PERIPHID4          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOA_PERIPHID5          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOA_PERIPHID6          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOA_PERIPHID7          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOA_PERIPHID0          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOA_PERIPHID1          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOA_PERIPHID2          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOA_PERIPHID3          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOA_PCELLID0           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOA_PCELLID1           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOA_PCELLID2           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOA_PCELLID3           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOB_DATA               (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOB_DIR                (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOB_IS                 (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOB_IBE                (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOB_IEV                (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOB_IM                 (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOB_RIS                (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOB_MIS                (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOB_ICR                (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOB_AFSEL              (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOB_DR2R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOB_DR4R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOB_DR8R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOB_ODR                (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOB_PUR                (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOB_PDR                (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOB_SLR                (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOB_DEN                (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOB_LOCK               (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOB_CR                 (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOB_PERIPHID4          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOB_PERIPHID5          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOB_PERIPHID6          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOB_PERIPHID7          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOB_PERIPHID0          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOB_PERIPHID1          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOB_PERIPHID2          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOB_PERIPHID3          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOB_PCELLID0           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOB_PCELLID1           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOB_PCELLID2           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOB_PCELLID3           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOC_DATA               (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOC_DIR                (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOC_IS                 (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOC_IBE                (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOC_IEV                (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOC_IM                 (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOC_RIS                (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOC_MIS                (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOC_ICR                (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOC_AFSEL              (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOC_DR2R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOC_DR4R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOC_DR8R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOC_ODR                (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOC_PUR                (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOC_PDR                (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOC_SLR                (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOC_DEN                (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOC_LOCK               (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOC_CR                 (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOC_PERIPHID4          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOC_PERIPHID5          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOC_PERIPHID6          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOC_PERIPHID7          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOC_PERIPHID0          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOC_PERIPHID1          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOC_PERIPHID2          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOC_PERIPHID3          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOC_PCELLID0           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOC_PCELLID1           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOC_PCELLID2           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOC_PCELLID3           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOD_DATA               (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOD_DIR                (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOD_IS                 (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOD_IBE                (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOD_IEV                (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOD_IM                 (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOD_RIS                (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOD_MIS                (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOD_ICR                (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOD_AFSEL              (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOD_DR2R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOD_DR4R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOD_DR8R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOD_ODR                (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOD_PUR                (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOD_PDR                (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOD_SLR                (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOD_DEN                (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOD_LOCK               (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOD_CR                 (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOD_PERIPHID4          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOD_PERIPHID5          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOD_PERIPHID6          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOD_PERIPHID7          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOD_PERIPHID0          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOD_PERIPHID1          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOD_PERIPHID2          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOD_PERIPHID3          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOD_PCELLID0           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOD_PCELLID1           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOD_PCELLID2           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOD_PCELLID3           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOE_DATA               (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOE_DIR                (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOE_IS                 (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOE_IBE                (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOE_IEV                (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOE_IM                 (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOE_RIS                (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOE_MIS                (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOE_ICR                (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOE_AFSEL              (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOE_DR2R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOE_DR4R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOE_DR8R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOE_ODR                (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOE_PUR                (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOE_PDR                (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOE_SLR                (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOE_DEN                (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOE_LOCK               (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOE_CR                 (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOE_PERIPHID4          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOE_PERIPHID5          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOE_PERIPHID6          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOE_PERIPHID7          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOE_PERIPHID0          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOE_PERIPHID1          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOE_PERIPHID2          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOE_PERIPHID3          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOE_PCELLID0           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOE_PCELLID1           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOE_PCELLID2           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOE_PCELLID3           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOF_DATA               (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOF_DIR                (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOF_IS                 (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOF_IBE                (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOF_IEV                (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOF_IM                 (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOF_RIS                (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOF_MIS                (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOF_ICR                (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOF_AFSEL              (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOF_DR2R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOF_DR4R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOF_DR8R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOF_ODR                (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOF_PUR                (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOF_PDR                (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOF_SLR                (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOF_DEN                (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOF_LOCK               (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOF_CR                 (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOF_PERIPHID4          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOF_PERIPHID5          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOF_PERIPHID6          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOF_PERIPHID7          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOF_PERIPHID0          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOF_PERIPHID1          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOF_PERIPHID2          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOF_PERIPHID3          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOF_PCELLID0           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOF_PCELLID1           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOF_PCELLID2           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOF_PCELLID3           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOG_DATA               (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOG_DIR                (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOG_IS                 (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOG_IBE                (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOG_IEV                (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOG_IM                 (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOG_RIS                (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOG_MIS                (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOG_ICR                (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOG_AFSEL              (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOG_DR2R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOG_DR4R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOG_DR8R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOG_ODR                (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOG_PUR                (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOG_PDR                (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOG_SLR                (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOG_DEN                (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOG_LOCK               (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOG_CR                 (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOG_PERIPHID4          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOG_PERIPHID5          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOG_PERIPHID6          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOG_PERIPHID7          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOG_PERIPHID0          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOG_PERIPHID1          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOG_PERIPHID2          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOG_PERIPHID3          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOG_PCELLID0           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOG_PCELLID1           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOG_PCELLID2           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOG_PCELLID3           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOH_DATA               (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOH_DIR                (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOH_IS                 (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOH_IBE                (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOH_IEV                (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOH_IM                 (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOH_RIS                (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOH_MIS                (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOH_ICR                (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOH_AFSEL              (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOH_DR2R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOH_DR4R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOH_DR8R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOH_ODR                (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOH_PUR                (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOH_PDR                (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOH_SLR                (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOH_DEN                (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOH_LOCK               (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOH_CR                 (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOH_PERIPHID4          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOH_PERIPHID5          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOH_PERIPHID6          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOH_PERIPHID7          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOH_PERIPHID0          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOH_PERIPHID1          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOH_PERIPHID2          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOH_PERIPHID3          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOH_PCELLID0           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOH_PCELLID1           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOH_PCELLID2           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOH_PCELLID3           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+#define LM3S_GPIOJ_DATA               (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET)
+#define LM3S_GPIOJ_DIR                (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET)
+#define LM3S_GPIOJ_IS                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET)
+#define LM3S_GPIOJ_IBE                (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET)
+#define LM3S_GPIOJ_IEV                (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET)
+#define LM3S_GPIOJ_IM                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET)
+#define LM3S_GPIOJ_RIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET)
+#define LM3S_GPIOJ_MIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET)
+#define LM3S_GPIOJ_ICR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET)
+#define LM3S_GPIOJ_AFSEL              (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET)
+#define LM3S_GPIOJ_DR2R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET)
+#define LM3S_GPIOJ_DR4R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET)
+#define LM3S_GPIOJ_DR8R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET)
+#define LM3S_GPIOJ_ODR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET)
+#define LM3S_GPIOJ_PUR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET)
+#define LM3S_GPIOJ_PDR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET)
+#define LM3S_GPIOJ_SLR                (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET)
+#define LM3S_GPIOJ_DEN                (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET)
+#define LM3S_GPIOJ_LOCK               (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET)
+#define LM3S_GPIOJ_CR                 (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET)
+#define LM3S_GPIOJ_PERIPHID4          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
+#define LM3S_GPIOJ_PERIPHID5          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
+#define LM3S_GPIOJ_PERIPHID6          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
+#define LM3S_GPIOJ_PERIPHID7          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
+#define LM3S_GPIOJ_PERIPHID0          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
+#define LM3S_GPIOJ_PERIPHID1          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
+#define LM3S_GPIOJ_PERIPHID2          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
+#define LM3S_GPIOJ_PERIPHID3          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
+#define LM3S_GPIOJ_PCELLID0           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET)
+#define LM3S_GPIOJ_PCELLID1           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET)
+#define LM3S_GPIOJ_PCELLID2           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET)
+#define LM3S_GPIOJ_PCELLID3           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_i2c.h b/nuttx/arch/arm/src/lm/chip/lm_i2c.h
new file mode 100644
index 000000000..919ac1348
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_i2c.h
@@ -0,0 +1,247 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_i2c.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* I2C Register Offsets *************************************************************/
+
+/* I2C Master */
+
+#define LM3S_I2CM_SA_OFFSET  0x000 /* I2C Master Slave Address */
+#define LM3S_I2CM_CS_OFFSET  0x004 /* I2C Master Control/Status */
+#define LM3S_I2CM_DR_OFFSET  0x008 /* I2C Master Data */
+#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
+#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
+#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
+#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
+#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
+#define LM3S_I2CM_CR_OFFSET  0x020 /* I2C Master Configuration */
+
+/* I2C Slave */
+
+#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
+#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
+#define LM3S_I2CS_DR_OFFSET  0x008 /* I2C Slave Data */
+#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
+#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
+#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
+#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
+
+/* I2C Register Addresses ***********************************************************/
+
+#if LM3S_NI2C > 0
+
+/* I2C Master */
+
+#define LM3S_I2CM_BASE(n)    (LM3S_I2CM0_BASE + (n)*0x1000)
+#define LM3S_I2CM_SA(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM_CS(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM_DR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM_TPR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM_IMR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM_RIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM_MIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM_ICR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM_CR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
+
+/* I2C Slave */
+
+#define LM3S_I2CS_BASE(n)    (LM3S_I2CS0_BASE + (n)*0x1000)
+#define LM3S_I2CS_OAR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS_CSR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS_DR(n)      (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS_IMR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS_RIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS_MIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS_ICR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
+
+/* I2C0 Master */
+
+#define LM3S_I2CM0_SA        (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM0_CS        (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM0_DR        (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM0_TPR       (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM0_IMR       (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM0_RIS       (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM0_MIS       (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM0_ICR       (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM0_CR        (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
+
+/* I2C0 Slave */
+
+#define LM3S_I2CS0_OAR       (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS0_CSR       (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS0_DR        (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS0_IMR       (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS0_RIS       (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS0_MIS       (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS0_ICR       (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
+
+#if LM3S_NI2C > 1
+
+/* I2C1 Master */
+
+#define LM3S_I2CM1_SA        (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
+#define LM3S_I2CM1_CS        (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
+#define LM3S_I2CM1_DR        (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
+#define LM3S_I2CM1_TPR       (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
+#define LM3S_I2CM1_IMR       (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
+#define LM3S_I2CM1_RIS       (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
+#define LM3S_I2CM1_MIS       (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
+#define LM3S_I2CM1_ICR       (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
+#define LM3S_I2CM1_CR        (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
+
+/* I2C1 Slave */
+
+#define LM3S_I2CS1_OAR       (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
+#define LM3S_I2CS1_CSR       (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
+#define LM3S_I2CS1_DR        (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
+#define LM3S_I2CS1_IMR       (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
+#define LM3S_I2CS1_RIS       (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
+#define LM3S_I2CS1_MIS       (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
+#define LM3S_I2CS1_ICR       (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
+
+#endif
+#endif
+
+/* I2C_Register Bit Definitions *****************************************************/
+
+/* I2C Master Slave Address (I2CM_SA), offset 0x000 */
+
+#define I2CM_SA_RS           (1 << 0)  /* Bit 0:  Receive/Send */
+#define I2CM_SA_SA_SHIFT     1         /* Bits 7-1: I2C Slave Address */
+#define I2CM_SA_SA_MASK      (0x7f << I2CM_SA_SA_SHIFT)
+
+/* I2C Master Control/Status (I2CM_CS), offset 0x004 */
+
+#define I2CM_CS_BUSY         (1 << 0)  /* Bit 0:  I2C Busy (read) */
+#define I2CM_CS_ERROR        (1 << 1)  /* Bit 1:  Error in last bus operation (read) */
+#define I2CM_CS_ADRACK       (1 << 2)  /* Bit 2:  Acknowledge Address (read) */
+#define I2CM_CS_DATACK       (1 << 3)  /* Bit 3:  Acknowledge Data (read) */
+#define I2CM_CS_ARBLST       (1 << 4)  /* Bit 4:  Arbitration Lost (read) */
+#define I2CM_CS_IDLE         (1 << 5)  /* Bit 5:  I2C Idle (read) */
+#define I2CM_CS_BUSBSY       (1 << 6)  /* Bit 6:  Bus Busy (read) */
+
+#define I2CM_CS_RUN          (1 << 0)  /* Bit 0:  I2C Master Enable (write) */
+#define I2CM_CS_START        (1 << 1)  /* Bit 1:  Generate START (write) */
+#define I2CM_CS_STOP         (1 << 2)  /* Bit 2:  Generate STOP (write) */
+#define I2CM_CS_ACK          (1 << 3)  /* Bit 3:  Data Acknowledge Enable (write) */
+
+/* I2C Master Data (I2CM_DR), offset 0x008 */
+
+#define I2CM_DR_MASK         0xff      /* Bits 7-0: Data transferred */
+
+/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */
+
+#define I2CM_TPR_MASK        0xff      /* Bits 7-0: SCL Clock Period */
+
+/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */
+
+#define I2CM_IMR_IM          (1 << 0)  /* Bit 0:  Interrupt Mask */
+
+/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */
+
+#define I2CM_RIS_RIS         (1 << 0)  /* Bit 0:  Raw Interrupt Status */
+
+/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */
+
+#define I2CM_MIS_MIS         (1 << 0)  /* Bit 0:  Masked Interrupt Status */
+
+/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */
+
+#define I2CM_ICR_IC          (1 << 0)  /* Bit 0:  Masked Interrupt Status */
+
+/* I2C Master Configuration (I2CM_CR), offset 0x020 */
+
+#define I2CM_CR_LPBK         (1 << 0)  /* Bit 0:: I2C Loopback */
+#define I2CM_CR_MFE          (1 << 4 ) /* Bit 4:  I2C Master Function Enable */
+#define I2CM_CR_SFE          (1 << 5)  /* Bit 5:  I2C Slave Function Enable */
+
+/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */
+
+#define I2CS_OAR_MASK        0xff      /* Bits 7-0: I2C Slave Own Address */
+
+/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */
+
+#define I2CS_CSR_RREQ        (1 << 0)  /* Bit 0:  Receive Request (read) */
+#define I2CS_CSR_TREQ        (1 << 1)  /* Bit 1:  Transmit Request (read) */
+#define I2CS_CSR_FBR         (1 << 2)  /* Bit 2:  First Byte Received (read) */
+
+#define I2CS_CSR_DA          (1 << 0)  /* Bit 0:  Device Active (write) */
+
+/* I2C Slave Data (I2CS_DR), offset 0x008 */
+
+#define I2CS_DR_MASK         0xff      /* Bits 7-0: Data for Transfer */
+
+/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */
+
+#define I2CM_IMR_DATAIM      (1 << 0)  /* Bit 0:  Data Interrupt Mask */
+
+/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */
+
+#define I2CM_RIS_DATARIS     (1 << 0)  /* Bit 0:  Data Raw Interrupt Status */
+
+/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */
+
+#define I2CM_MIS_DATAMIS     (1 << 0)  /* Bit 0:  Data Masked Interrupt Status */
+
+/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */
+
+#define I2CM_ICR_DATAIC      (1 << 0)  /* Bit 0:  Data Interrupt Clear */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_ssi.h b/nuttx/arch/arm/src/lm/chip/lm_ssi.h
new file mode 100644
index 000000000..b58aec733
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_ssi.h
@@ -0,0 +1,235 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_ssi.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#if LM3S_NSSI > 0
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* SSI register offsets *************************************************************/
+
+#define LM3S_SSI_CR0_OFFSET       0x000 /* SSI Control 0 */
+#define LM3S_SSI_CR1_OFFSET       0x004 /* SSI Control 1 */
+#define LM3S_SSI_DR_OFFSET        0x008 /* SSI Data */
+#define LM3S_SSI_SR_OFFSET        0x00c /* SSI Status */
+#define LM3S_SSI_CPSR_OFFSET      0x010 /* SSI Clock Prescale */
+#define LM3S_SSI_IM_OFFSET        0x014 /* SSI Interrupt Mask */
+#define LM3S_SSI_RIS_OFFSET       0x018 /* SSI Raw Interrupt Status */
+#define LM3S_SSI_MIS_OFFSET       0x01c /* SSI Masked Interrupt Status */
+#define LM3S_SSI_ICR_OFFSET       0x020 /* SSI Interrupt Clear */
+#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
+#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
+#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
+#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
+#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
+#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
+#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
+#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
+#define LM3S_SSI_PCELLID0_OFFSET  0xff0 /* SSI PrimeCell Identification 0 */
+#define LM3S_SSI_PCELLID1_OFFSET  0xff4 /* SSI PrimeCell Identification 1 */
+#define LM3S_SSI_PCELLID2_OFFSET  0xff8 /* SSI PrimeCell Identification 2 */
+#define LM3S_SSI_PCELLID3_OFFSET  0xffc /* SSI PrimeCell Identification 3 */
+
+/* SSI register addresses ***********************************************************/
+
+#define LM3S_SSI0_CR0             (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI0_CR1             (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI0_DR              (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI0_SR              (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI0_CPSR            (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI0_IM              (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI0_RIS             (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI0_MIS             (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI0_ICR             (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI0_PERIPHID4       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI0_PERIPHID5       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI0_PERIPHID6       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI0_PERIPHID7       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI0_PERIPHID0       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI0_PERIPHID1       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI0_PERIPHID2       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI0_PERIPHID3       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI0_PCELLID0        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI0_PCELLID1        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI0_PCELLID2        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI0_PCELLID3        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
+
+#if LM3S_NSSI > 1
+#define LM3S_SSI1_CR0             (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI1_CR1             (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI1_DR              (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI1_SR              (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI1_CPSR            (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI1_IM              (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI1_RIS             (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI1_MIS             (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI1_ICR             (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI1_PERIPHID4       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI1_PERIPHID5       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI1_PERIPHID6       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI1_PERIPHID7       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI1_PERIPHID0       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI1_PERIPHID1       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI1_PERIPHID2       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI1_PERIPHID3       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI1_PCELLID0        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI1_PCELLID1        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI1_PCELLID2        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI1_PCELLID3        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
+
+#define LM3S_SSI_BASE(n)          (LM3S_SSI0_BASE + (n)*0x01000)
+
+#define LM3S_SSI_CR0(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
+#define LM3S_SSI_CR1(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
+#define LM3S_SSI_DR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
+#define LM3S_SSI_SR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
+#define LM3S_SSI_CPSR(n)          (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
+#define LM3S_SSI_IM(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
+#define LM3S_SSI_RIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
+#define LM3S_SSI_MIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
+#define LM3S_SSI_ICR(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
+#define LM3S_SSI_PERIPHID4(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
+#define LM3S_SSI_PERIPHID5(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
+#define LM3S_SSI_PERIPHID6(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
+#define LM3S_SSI_PERIPHID7(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
+#define LM3S_SSI_PERIPHID0(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
+#define LM3S_SSI_PERIPHID1(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
+#define LM3S_SSI_PERIPHID2(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
+#define LM3S_SSI_PERIPHID3(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
+#define LM3S_SSI_PCELLID0(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
+#define LM3S_SSI_PCELLID1(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
+#define LM3S_SSI_PCELLID2(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
+#define LM3S_SSI_PCELLID3(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
+#endif /* LM3S_NSSI > 1 */
+
+/* SSI register bit defitiions ******************************************************/
+
+/* SSI Control 0 (SSICR0), offset 0x000 */
+
+#define SSI_CR0_DSS_SHIFT         0         /* Bits 3-0: SSI Data Size Select */
+#define SSI_CR0_DSS_MASK          (0x0f << SSI_CR0_DSS_SHIFT)
+#define   SSI_CR0_DSS(n)          ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
+#define SSI_CR0_FRF_SHIFT         4         /* Bits 5-4: SSI Frame Format Select */
+#define SSI_CR0_FRF_MASK          (3 << SSI_CR0_FRF_SHIFT)
+#define   SSI_CR0_FRF_SPI         (0 << SSI_CR0_FRF_SHIFT)     /* Freescale SPI format */
+#define   SSI_CR0_FRF_SSFF        (1 << SSI_CR0_FRF_SHIFT)     /* TI synchronous serial fram format */
+#define   SSI_CR0_FRF_UWIRE       (2 << SSI_CR0_FRF_SHIFT)     /* MICROWIRE frame format */
+#define SSI_CR0_SPO               (1 << 6)  /* Bit 6:  SSI Serial Clock Polarity */
+#define SSI_CR0_SPH               (1 << 7)  /* Bit 7:  SSI Serial Clock Phase */
+#define SSI_CR0_SCR_SHIFT         8         /* Bits 15-8: SSI Serial Clock Rate */
+#define SSI_CR0_SCR_MASK          (0xff << SSI_CR0_SCR_SHIFT)
+
+/* SSI Control 1 (SSICR1), offset 0x004 */
+
+#define SSI_CR1_LBM               (1 << 0)  /* Bit 0:  SSI Loopback Mode */
+#define SSI_CR1_SSE               (1 << 1)  /* Bit 1:  SSI Synchronous Serial Port Enable */
+#define SSI_CR1_MS                (1 << 2)  /* Bit 2:  SSI Master/Slave Select slave */
+#define SSI_CR1_SOD               (1 << 3)  /* Bit 3:  SSI Slave Mode Output Disable */
+
+/* SSI Data (SSIDR), offset 0x008 */
+
+#define SSI_DR_MASK               0xffff    /* Bits 15-0: SSI data */
+
+/* SSI Status (SSISR), offset 0x00c */
+
+#define SSI_SR_TFE                (1 << 0)  /* Bit 0:  SSI Transmit FIFO Empty */
+#define SSI_SR_TNF                (1 << 1)  /* Bit 1:  SSI Transmit FIFO Not Full */
+#define SSI_SR_RNE                (1 << 2)  /* Bit 2:  SSI Receive FIFO Not Empty */
+#define SSI_SR_RFF                (1 << 3)  /* Bit 3:  SSI Receive FIFO Full */
+#define SSI_SR_BSY                (1 << 4)  /* Bit 4:  SSI Busy Bit */
+
+/* SSI Clock Prescale (SSICPSR), offset 0x010 */
+
+#define SSI_CPSR_DIV_MASK         0xff      /* Bits 7-0: SSI Clock Prescale Divisor */
+
+/* SSI Interrupt Mask (SSIIM), offset 0x014 */
+
+#define SSI_IM_ROR                (1 << 0)  /* Bit 0:  SSI Receive Overrun Interrupt Mask */
+#define SSI_IM_RT                 (1 << 1)  /* Bit 1:  SSI Receive Time-Out Interrupt Mask */
+#define SSI_IM_RX                 (1 << 2)  /* Bit 2:  SSI Receive FIFO Interrupt Mask */
+#define SSI_IM_TX                 (1 << 3)  /* Bit 3:  SSI Transmit FIFO Interrupt Mask */
+
+/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
+
+#define SSI_RIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Raw Interrupt Status */
+#define SSI_RIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Raw Interrupt Status */
+#define SSI_RIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Raw Interrupt Status */
+#define SSI_RIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Raw Interrupt Status */
+
+/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
+
+#define SSI_MIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Masked Interrupt Status */
+#define SSI_MIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Masked Interrupt Status */
+#define SSI_MIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Masked Interrupt Status */
+#define SSI_MIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Masked Interrupt Status */
+
+/* SSI Interrupt Clear (SSIICR), offset 0x020 */
+
+#define SSI_ICR_ROR               (1 << 0)  /* Bit 0: SSI Receive Overrun Interrupt Clear */
+#define SSI_ICR_RT                (1 << 1)  /* Bit 1: SSI Receive Time-Out Interrupt Clear */
+
+/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
+
+#define SSI_PERIPHID_MASK         0xff      /* Bits 7-0: SSI Peripheral ID n */
+
+/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
+
+#define SSI_PCELLID_MASK          0xff      /* Bits 7-0: SSI Prime cell ID */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* LM3S_NSSI > 0 */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h
new file mode 100644
index 000000000..6ca8ac3ff
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h
@@ -0,0 +1,495 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_syscontrol.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* System Control Register Offsets **************************************************/
+
+#define LM3S_SYSCON_DID0_OFFSET       0x000 /* Device Identification 0 */
+#define LM3S_SYSCON_DID1_OFFSET       0x004 /* Device Identification 1 */
+#define LM3S_SYSCON_DC0_OFFSET        0x008 /* Device Capabilities 0 */
+#define LM3S_SYSCON_DC1_OFFSET        0x010 /* Device Capabilities 1 */
+#define LM3S_SYSCON_DC2_OFFSET        0x014 /* Device Capabilities 2 */
+#define LM3S_SYSCON_DC3_OFFSET        0x018 /* Device Capabilities 3 */
+#define LM3S_SYSCON_DC4_OFFSET        0x01c /* Device Capabilities 4 */
+#define LM3S_SYSCON_PBORCTL_OFFSET    0x030 /* Brown-Out Reset Control */
+#define LM3S_SYSCON_LDOPCTL_OFFSET    0x034 /* LDO Power Control */
+#define LM3S_SYSCON_SRCR0_OFFSET      0x040 /* Software Reset Control 0 */
+#define LM3S_SYSCON_SRCR1_OFFSET      0x044 /* Software Reset Control 1 */
+#define LM3S_SYSCON_SRCR2_OFFSET      0x048 /* Software Reset Control 2*/
+#define LM3S_SYSCON_RIS_OFFSET        0x050 /* Raw Interrupt Status */
+#define LM3S_SYSCON_IMC_OFFSET        0x054 /* Interrupt Mask Control */
+#define LM3S_SYSCON_MISC_OFFSET       0x058 /* Masked Interrupt Status and Clear */
+#define LM3S_SYSCON_RESC_OFFSET       0x05c /* Reset Cause */
+#define LM3S_SYSCON_RCC_OFFSET        0x060 /* Run-Mode Clock Configuration */
+#define LM3S_SYSCON_PLLCFG_OFFSET     0x064 /* XTAL to PLL Translation */
+#define LM3S_SYSCON_RCC2_OFFSET       0x070 /* Run-Mode Clock Configuration 2 */
+#define LM3S_SYSCON_RCGC0_OFFSET      0x100 /* Run Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_RCGC1_OFFSET      0x104 /* Run Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_RCGC2_OFFSET      0x108 /* Run Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_SCGC0_OFFSET      0x110 /* Sleep Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_SCGC1_OFFSET      0x114 /* Sleep Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_SCGC2_OFFSET      0x118 /* Sleep Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_DCGC0_OFFSET      0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
+#define LM3S_SYSCON_DCGC1_OFFSET      0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
+#define LM3S_SYSCON_DCGC2_OFFSET      0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
+#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
+
+/* System Control Register Addresses ************************************************/
+
+#define LM3S_SYSCON_DID0              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
+#define LM3S_SYSCON_DID1              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
+#define LM3S_SYSCON_DC0               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
+#define LM3S_SYSCON_DC1               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
+#define LM3S_SYSCON_DC2               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
+#define LM3S_SYSCON_DC3               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
+#define LM3S_SYSCON_DC4               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
+#define LM3S_SYSCON_PBORCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
+#define LM3S_SYSCON_LDOPCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
+#define LM3S_SYSCON_SRCR0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
+#define LM3S_SYSCON_SRCR1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
+#define LM3S_SYSCON_SRCR2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
+#define LM3S_SYSCON_RIS               (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
+#define LM3S_SYSCON_IMC               (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
+#define LM3S_SYSCON_MISC              (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
+#define LM3S_SYSCON_RESC              (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
+#define LM3S_SYSCON_RCC               (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
+#define LM3S_SYSCON_PLLCFG            (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
+#define LM3S_SYSCON_RCC2              (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
+#define LM3S_SYSCON_RCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
+#define LM3S_SYSCON_RCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
+#define LM3S_SYSCON_RCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
+#define LM3S_SYSCON_SCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
+#define LM3S_SYSCON_SCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
+#define LM3S_SYSCON_SCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
+#define LM3S_SYSCON_DCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
+#define LM3S_SYSCON_DCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
+#define LM3S_SYSCON_DCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
+#define LM3S_SYSCON_DSLPCLKCFG        (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
+
+/* System Control Register Bit Definitions ******************************************/
+
+/* Device Identification 0 (DID0), offset 0x000 */
+
+#define SYSCON_DID0_MINOR_SHIFT       0         /* Bits 7-0: Minor Revision of the device */
+#define SYSCON_DID0_MINOR_MASK        (0xff << SYSCON_DID0_MINOR_SHIFT)
+#define SYSCON_DID0_MAJOR_SHIFT       8         /* Bits 15-8: Major Revision of the device */
+#define SYSCON_DID0_MAJOR_MASK        (0xff << SYSCON_DID0_MAJOR_SHIFT)
+#define SYSCON_DID0_CLASS_SHIFT       16        /* Bits 23-16: Device Class */
+#define SYSCON_DID0_CLASS_MASK        (0xff << SYSCON_DID0_CLASS_SHIFT)
+#define SYSCON_DID0_VER_SHIFT         28        /* Bits 30-28: DID0 Version */
+#define SYSCON_DID0_VER_MASK          (7 << SYSCON_DID0_VER_SHIFT)
+
+/* Device Identification 1 (DID1), offset 0x004 */
+
+#define SYSCON_DID1_QUAL_SHIFT        0         /* Bits 1-0: Qualification Status */
+#define SYSCON_DID1_QUAL_MASK         (0x03 << SYSCON_DID1_QUAL_SHIFT)
+#define SYSCON_DID1_ROHS              (1 << 2)  /* Bit 2: RoHS-Compliance */
+#define SYSCON_DID1_PKG_SHIFT         3 /* Bits 4-3: Package Type */
+#define SYSCON_DID1_PKG_MASK          (0x03 << SYSCON_DID1_PKG_SHIFT)
+#define SYSCON_DID1_TEMP_SHIFT        5         /* Bits 7-5: Temperature Range */
+#define SYSCON_DID1_TEMP_MASK         (0x07 << SYSCON_DID1_TEMP_SHIFT)
+#define SYSCON_DID1_PINCOUNT_SHIFT    13        /* Bits 15-13: Package Pin Count */
+#define SYSCON_DID1_PINCOUNT_MASK     (0x07 << SYSCON_DID1_PINCOUNT_SHIFT)
+#define SYSCON_DID1_PARTNO_SHIFT      16        /* Bits 23-16: Part Number */
+#define SYSCON_DID1_PARTNO_MASK       (0xff << SYSCON_DID1_PARTNO_SHIFT)
+#define SYSCON_DID1_FAM_SHIFT         24        /* Bits 27-24: Family */
+#define SYSCON_DID1_FAM_MASK          (0x0f << SYSCON_DID1_FAM_SHIFT)
+#define SYSCON_DID1_VER_SHIFT         28        /* Bits 31-28:  DID1 Version */
+#define SYSCON_DID1_VER_MASK          (0x0f << SYSCON_DID1_VER_SHIFT)
+
+/* Device Capabilities 0 (DC0), offset 0x008 */
+
+#define SYSCON_DC0_FLASHSZ_SHIFT      0         /* Bits 15-0: FLASH Size */
+#define SYSCON_DC0_FLASHSZ_MASK       (0xffff << SYSCON_DC0_FLASHSZ_SHIFT)
+#define SYSCON_DC0_SRAMSZ_SHIFT       16        /* Bits 31-16: SRAM Size */
+#define SYSCON_DC0_SRAMSZ_MASK        (0xffff << SYSCON_DC0_SRAMSZ_SHIFT)
+
+/* Device Capabilities 1 (DC1), offset 0x010 */
+
+#define SYSCON_DC1_JTAG               (1 << 0)  /* Bit 0: JTAG Present */
+#define SYSCON_DC1_SWD                (1 << 1)  /* Bit 1: SWD Present */
+#define SYSCON_DC1_SWO                (1 << 2)  /* Bit 2: SWO Trace Port Present */
+#define SYSCON_DC1_WDT                (1 << 3)  /* Bit 3: Watchdog Timer Present */
+#define SYSCON_DC1_PLL                (1 << 4)  /* Bit 4: PLL Present */
+#define SYSCON_DC1_TEMPSNS            (1 << 5)  /* Bit 5: Temp Sensor Present */
+#define SYSCON_DC1_HIB                (1 << 6)  /* Bit 6: Hibernation Module Present */
+#define SYSCON_DC1_MPU                (1 << 7)  /* Bit 7: MPU Present */
+#define SYSCON_DC1_MAXADCSPD_SHIFT    8         /* Bits 9-8: Max ADC Speed */
+#define SYSCON_DC1_MAXADCSPD_MASK     (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT)
+#define SYSCON_DC1_ADC                (1 << 16) /* Bit 16: ADC Module Present */
+#define SYSCON_DC1_MINSYSDIV_SHIFT    12        /* Bits 15-12: System Clock Divider Minimum */
+#define SYSCON_DC1_MINSYSDIV_MASK     (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT)
+
+/* Device Capabilities 2 (DC2), offset 0x014 */
+
+#define SYSCON_DC2_UART0              (1 << 0)  /* Bit 0: UART0 Present */
+#define SYSCON_DC2_UART1              (1 << 1)  /* Bit 1: UART1 Present */
+#define SYSCON_DC2_SSI0               (1 << 4)  /* Bit 4: SSI0 Present */
+#define SYSCON_DC2_SSI1               (1 << 5)  /* Bit 5: SSI1 Present */
+#define SYSCON_DC2_I2C0               (1 << 12) /* Bit 12: I2C Module 0 Present */
+#define SYSCON_DC2_I2C1               (1 << 14) /* Bit 14: I2C Module 1 Present */
+#define SYSCON_DC2_TIMER0             (1 << 16) /* Bit 16: Timer 0 Present */
+#define SYSCON_DC2_TIMER1             (1 << 17) /* Bit 17: Timer 1 Present */
+#define SYSCON_DC2_TIMER2             (1 << 18) /* Bit 18: Timer 2 Present */
+#define SYSCON_DC2_TIMER3             (1 << 19) /* Bit 19: Timer 3 Present */
+#define SYSCON_DC2_COMP0              (1 << 24) /* Bit 24: Analog Comparator 0 Present */
+#define SYSCON_DC2_COMP1              (1 << 25) /* Bit 25: Analog Comparator 1 Present */
+
+/* Device Capabilities 3 (DC3), offset 0x018 */
+
+#define SYSCON_DC3_C0MINUS            (1 << 6)  /* Bit 6: C0- Pin Present */
+#define SYSCON_DC3_C0PLUS             (1 << 7)  /* Bit 7: C0+ Pin Present */
+#define SYSCON_DC3_C0O                (1 << 8)  /* Bit 8: C0o Pin Present */
+#define SYSCON_DC3_C1MINUS            (1 << 9)  /* Bit 9: C1- Pin Present */
+#define SYSCON_DC3_C1PLUS             (1 << 10) /* Bit 10: C1+ Pin Present */
+#define SYSCON_DC3_ADC0               (1 << 16) /* Bit 16: ADC0 Pin Present */
+#define SYSCON_DC3_ADC1               (1 << 17) /* Bit 17: ADC1 Pin Present */
+#define SYSCON_DC3_ADC2               (1 << 18) /* Bit 18: ADC2 Pin Present */
+#define SYSCON_DC3_ADC3               (1 << 19) /* Bit 19: ADC3 Pin Present */
+#define SYSCON_DC3_ADC4               (1 << 20) /* Bit 20: ADC4 Pin Present */
+#define SYSCON_DC3_ADC5               (1 << 21) /* Bit 21: ADC5 Pin Present */
+#define SYSCON_DC3_ADC6               (1 << 22) /* Bit 22: ADC6 Pin Present */
+#define SYSCON_DC3_ADC7               (1 << 23) /* Bit 23: ADC7 Pin Present */
+#define SYSCON_DC3_CCP0               (1 << 24) /* Bit 24: CCP0 Pin Present */
+#define SYSCON_DC3_CCP1               (1 << 25) /* Bit 25: CCP1 Pin Present */
+#define SYSCON_DC3_CCP2               (1 << 26) /* Bit 26: CCP2 Pin Present */
+#define SYSCON_DC3_CCP3               (1 << 27) /* Bit 27: CCP3 Pin Present */
+#define SYSCON_DC3_CCP4               (1 << 28) /* Bit 28: CCP4 Pin Present */
+#define SYSCON_DC3_CCP5               (1 << 29) /* Bit 29: CCP5 Pin Present */
+#define SYSCON_DC3_32KHZ              (1 << 31) /* Bit 31: 32KHz Input Clock Available */
+
+/* Device Capabilities 4 (DC4), offset 0x01c */
+
+#define SYSCON_DC4_GPIO(n)            (1 << (n))
+#define SYSCON_DC4_GPIOA              (1 << 0)  /* Bit 0: GPIO Port A Present */
+#define SYSCON_DC4_GPIOB              (1 << 1)  /* Bit 1: GPIO Port B Present */
+#define SYSCON_DC4_GPIOC              (1 << 2)  /* Bit 2: GPIO Port C Present */
+#define SYSCON_DC4_GPIOD              (1 << 3)  /* Bit 3: GPIO Port D Present */
+#define SYSCON_DC4_GPIOE              (1 << 4)  /* Bit 4: GPIO Port E Present */
+#define SYSCON_DC4_GPIOF              (1 << 5)  /* Bit 5: GPIO Port F Present */
+#define SYSCON_DC4_GPIOG              (1 << 6)  /* Bit 6: GPIO Port G Present */
+#define SYSCON_DC4_GPIOH              (1 << 7)  /* Bit 7: GPIO Port H Present */
+#define SYSCON_DC4_EMAC0              (1 << 28) /* Bit 28: Ethernet MAC0 Present */
+#define SYSCON_DC4_EPHY0              (1 << 30) /* Bit 30: Ethernet PHY0 Present */
+
+/* Brown-Out Reset Control (PBORCTL), offset 0x030 */
+
+#define SYSCON_PBORCTL_BORIOR         (1 << 1)  /* Bit 1: BOR Interrupt or Reset */
+
+/* LDO Power Control (LDOPCTL), offset 0x034 */
+
+#define SYSCON_LDOPCTL_VADJ_SHIFT     0         /* Bits 5-0: LDO Output Voltage */
+#define SYSCON_LDOPCTL_VADJ_MASK      (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT)
+#  define SYSCON_LPDOPCTL_2500MV      (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/
+#  define SYSCON_LPDOPCTL_2450MV      (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */
+#  define SYSCON_LPDOPCTL_2400MV      (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */
+#  define SYSCON_LPDOPCTL_2350MV      (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */
+#  define SYSCON_LPDOPCTL_2300MV      (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */
+#  define SYSCON_LPDOPCTL_2250MV      (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */
+#  define SYSCON_LPDOPCTL_2750MV      (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */
+#  define SYSCON_LPDOPCTL_2700MV      (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */
+#  define SYSCON_LPDOPCTL_2650MV      (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */
+#  define SYSCON_LPDOPCTL_2600MV      (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */
+#  define SYSCON_LPDOPCTL_2550MV      (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */
+
+/* Software Reset Control 0 (SRCR0), offset 0x040 */
+
+#define SYSCON_SRCR0_WDT              (1 << 3)  /* Bit 3: WDT Reset Control */
+#define SYSCON_SRCR0_HIB              (1 << 6)  /* Bit 6: HIB Reset Control */
+#define SYSCON_SRCR0_ADC              (1 << 16) /* Bit 16: ADC0 Reset Control */
+
+/* Software Reset Control 1 (SRCR1), offset 0x044 */
+
+#define SYSCON_SRCR1_UART0            (1 << 0)  /* Bit 0: UART0 Reset Control */
+#define SYSCON_SRCR1_UART1            (1 << 1)  /* Bit 1: UART1 Reset Control */
+#define SYSCON_SRCR1_SSI0             (1 << 4)  /* Bit 4: SSI0 Reset Control1 */
+#define SYSCON_SRCR1_SSI1             (1 << 5)  /* Bit 5: SSI1 Reset Control */
+#define SYSCON_SRCR1_I2C0             (1 << 12) /* Bit 12: I2C0 Reset Control */
+#define SYSCON_SRCR1_I2C1             (1 << 14) /* Bit 14: I2C1 Reset Control */
+#define SYSCON_SRCR1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Reset Control */
+#define SYSCON_SRCR1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Reset Control */
+#define SYSCON_SRCR1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Reset Control */
+#define SYSCON_SRCR1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Reset Control */
+#define SYSCON_SRCR1_COMP0            (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */
+#define SYSCON_SRCR1_COMP1            (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */
+
+/* Software Reset Control 2 (SRCR2), offset 0x048 */
+
+#define SYSCON_SRCR2_GPIO(n)          (1 << (n))
+#define SYSCON_SRCR2_GPIOA            (1 << 0)  /* Bit 0: Port A Reset Control */
+#define SYSCON_SRCR2_GPIOB            (1 << 1)  /* Bit 1: Port B Reset Control */
+#define SYSCON_SRCR2_GPIOC            (1 << 2)  /* Bit 2: Port C Reset Control */
+#define SYSCON_SRCR2_GPIOD            (1 << 3)  /* Bit 3: Port D Reset Control */
+#define SYSCON_SRCR2_GPIOE            (1 << 4)  /* Bit 4: Port E Reset Control */
+#define SYSCON_SRCR2_GPIOF            (1 << 5)  /* Bit 5: Port F Reset Control */
+#define SYSCON_SRCR2_GPIOG            (1 << 6)  /* Bit 6: Port G Reset Control */
+#define SYSCON_SRCR2_GPIOH            (1 << 7)  /* Bit 7: Port H Reset Control */
+#define SYSCON_SRCR2_EMAC0            (1 << 28) /* Bit 28: MAC0 Reset Control */
+#define SYSCON_SRCR2_EPHY0            (1 << 30) /* Bit 30: PHY0 Reset Control */
+
+/* Raw Interrupt Status (RIS), offset 0x050 */
+
+#define SYSCON_RIS_BORRIS             (1 << 1)  /* Bit 1: Brown-Out Reset Raw Interrupt Status */
+#define SYSCON_RIS_PLLLRIS            (1 << 6)  /* Bit 6: PLL Lock Raw Interrupt Status */
+
+/* Interrupt Mask Control (IMC), offset 0x054 */
+
+#define SYSCON_IMC_BORIM              (1 << 1)  /* Bit 1: Brown-Out Reset Interrupt Mask */
+#define SYSCON_IMC_PLLLIM             (1 << 6)  /* Bit 6: PLL Lock Interrupt Mask */
+
+/* Masked Interrupt Status and Clear (MISC), offset 0x058 */
+
+#define SYSCON_MISC_BORMIS            (1 << 1)  /* Bit 1: BOR Masked Interrupt Status */
+#define SYSCON_MISC_PLLLMIS           (1 << 6)  /* Bit 6: PLL Lock Masked Interrupt Status */
+
+/* Reset Cause (RESC), offset 0x05C */
+
+#define SYSCON_RESC_EXT               (1 << 0)  /* Bit 0: External Reset */
+#define SYSCON_RESC_POR               (1 << 1)  /* Bit 1: Power-On Reset */
+#define SYSCON_RESC_BOR               (1 << 2)  /* Bit 2: Brown-Out Reset */
+#define SYSCON_RESC_WDT               (1 << 3)  /* Bit 3: Watchdog Timer Reset */
+#define SYSCON_RESC_SW                (1 << 4)  /* Bit 4: Software Reset */
+
+/* Run-Mode Clock Configuration (RCC), offset 0x060 */
+
+#define SYSCON_RCC_MOSCDIS            (1 << 0)  /* Bit 0: Main Oscillator Disable */
+#define SYSCON_RCC_IOSCDIS            (1 << 1)  /* Bit 1: Internal Oscillator Disable */
+#define SYSCON_RCC_OSCSRC_SHIFT       4         /* Bits 5-4: Oscillator Source */
+#define SYSCON_RCC_OSCSRC_MASK        (0x03 << SYSCON_RCC_OSCSRC_SHIFT)
+#  define SYSCON_RCC_OSCSRC_MOSC      (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */
+#  define SYSCON_RCC_OSCSRC_IOSC      (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */
+#  define SYSCON_RCC_OSCSRC_IOSC4     (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */
+#  define SYSCON_RCC_OSCSRC_30KHZ     (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */
+#define SYSCON_RCC_XTAL_SHIFT         6         /* Bits 10-6: Crystal Value */
+#define SYSCON_RCC_XTAL_MASK          (0x1f << SYSCON_RCC_XTAL_SHIFT)
+#  define SYSCON_RCC_XTAL1000KHZ      ( 0 << SYSCON_RCC_XTAL_SHIFT)  /* 1.0000MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL1843KHZ      ( 1 << SYSCON_RCC_XTAL_SHIFT)  /* 1.8432MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL2000KHZ      ( 2 << SYSCON_RCC_XTAL_SHIFT)  /* 2.0000MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL2580KHZ      ( 3 << SYSCON_RCC_XTAL_SHIFT)  /* 2.4576MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL3580KHZ      ( 4 << SYSCON_RCC_XTAL_SHIFT)  /* 3.5795MHz */
+#  define SYSCON_RCC_XTAL3686KHZ      ( 5 << SYSCON_RCC_XTAL_SHIFT)  /* 3.6864MHz */
+#  define SYSCON_RCC_XTAL4000KHZ      ( 6 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0000MHz */
+#  define SYSCON_RCC_XTAL4096KHZ      ( 7 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0960MHz */
+#  define SYSCON_RCC_XTAL4915KHZ      ( 8 << SYSCON_RCC_XTAL_SHIFT)  /* 4.9152MHz */
+#  define SYSCON_RCC_XTAL5000KHZ      ( 9 << SYSCON_RCC_XTAL_SHIFT)  /* 5.0000MHz */
+#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT)  /* 5.1200MHz */
+#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT)  /* 6.0000MHz (reset value) */
+#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT)  /* 6.1440MHz */
+#  define SYSCON_RCC_XTAL7373KHZ      (13 << SYSCON_RCC_XTAL_SHIFT)  /* 7.3728MHz */
+#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT)  /* 8.0000MHz */
+#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT)  /* 8.1920MHz */
+#ifdef CONFIG_ARCH_CHIP_LM3S9B96
+#  define SYSCON_RCC_XTAL10000KHZ     (16 << SYSCON_RCC_XTAL_SHIFT)  /* 10.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL12000KHZ     (17 << SYSCON_RCC_XTAL_SHIFT)  /* 12.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL12888KHZ     (18 << SYSCON_RCC_XTAL_SHIFT)  /* 12.288 MHz */
+#  define SYSCON_RCC_XTAL13560KHZ     (19 << SYSCON_RCC_XTAL_SHIFT)  /* 13.56 MHz */
+#  define SYSCON_RCC_XTAL14318KHZ     (20 << SYSCON_RCC_XTAL_SHIFT)  /* 14.31818 MHz */
+#  define SYSCON_RCC_XTAL16000KHZ     (21 << SYSCON_RCC_XTAL_SHIFT)  /* 16.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL16384KHZ     (22 << SYSCON_RCC_XTAL_SHIFT)  /* 16.384 MHz */
+#endif
+#define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
+#define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
+#define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */
+#define SYSCON_RCC_SYSDIV_SHIFT       23        /* Bits 26-23: System Clock Divisor */
+#define SYSCON_RCC_SYSDIV_MASK        (0x0f << SYSCON_RCC_SYSDIV_SHIFT)
+#  define SYSCON_RCC_SYSDIV(n)        (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT)
+#define SYSCON_RCC_ACG                (1 << 27) /* Bit 27: Auto Clock Gating */
+
+/* XTAL to PLL Translation (PLLCFG), offset 0x064 */
+
+#define SYSCON_PLLCFG_F_SHIFT         5         /* Bits 13-5: PLL F Value */
+#define SYSCON_PLLCFG_F_MASK          (0x1ff << SYSCON_PLLCFG_F_SHIFT)
+#define SYSCON_PLLCFG_R_SHIFT         0         /* Bits 4-0: PLL R Value  */
+#define SYSCON_PLLCFG_R_MASK          (0x1f << SYSCON_PLLCFG_R_SHIFT)
+
+/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */
+
+#define SYSCON_RCC2_OSCSRC2_SHIFT     4         /* Bits 6-4: Oscillator Source */
+#define SYSCON_RCC2_OSCSRC2_MASK      (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT)
+#  define SYSCON_RCC2_OSCSRC2_MOSC    (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */
+#  define SYSCON_RCC2_OSCSRC2_IOSC    (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */
+#  define SYSCON_RCC2_OSCSRC2_IOSC4   (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */
+#  define SYSCON_RCC2_OSCSRC2_30KHZ   (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */
+#  define SYSCON_RCC2_OSCSRC2_32KHZ   (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */
+#define SYSCON_RCC2_BYPASS2           (1 << 11) /* Bit 11: Bypass PLL */
+#define SYSCON_RCC2_PWRDN2            (1 << 13) /* Bit 13: Power-Down PLL */
+#define SYSCON_RCC2_SYSDIV2_SHIFT     23        /* Bits 28-23: System Clock Divisor */
+#define SYSCON_RCC2_SYSDIV2_MASK      (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT)
+#  define SYSCON_RCC2_SYSDIV(n)       ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT)
+#define SYSCON_RCC2_USERCC2           (1 << 31) /* Bit 31: Use RCC2 When set */
+
+/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */
+
+#define SYSCON_RCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_RCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_RCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_RCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_RCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */
+
+#define SYSCON_RCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_RCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_RCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_RCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_RCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_RCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_RCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_RCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_RCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */
+
+#define SYSCON_RCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_RCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_RCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_RCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_RCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_RCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_RCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_RCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_RCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_RCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_RCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */
+
+#define SYSCON_SCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_SCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_SCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_SCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_SCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */
+
+#define SYSCON_SCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_SCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_SCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_SCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_SCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_SCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_SCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_SCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_SCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */
+
+#define SYSCON_SCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_SCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_SCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_SCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_SCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_SCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_SCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_SCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_SCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_SCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_SCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */
+
+#define SYSCON_DCGC0_WDT              (1 << 3)  /* Bit 3: WDT Clock Gating Control */
+#define SYSCON_DCGC0_HIB              (1 << 6)  /* Bit 6: HIB Clock Gating Control */
+#define SYSCON_DCGC0_MAXADCSPD_SHIFT  8         /* Bits 9-8: ADC Sample Speed */
+#define SYSCON_DCGC0_MAXADCSPD_MASK   (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT)
+#define SYSCON_DCGC0_ADC              (1 << 16) /* Bit 16: ADC0 Clock Gating Control */
+
+/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */
+
+#define SYSCON_DCGC1_UART0            (1 << 0)  /* Bit 0: UART0 Clock Gating Control */
+#define SYSCON_DCGC1_UART1            (1 << 1)  /* Bit 1: UART1 Clock Gating Control */
+#define SYSCON_DCGC1_SSI0             (1 << 4)  /* Bit 4: SSI0 Clock Gating Control */
+#define SYSCON_DCGC1_SSI1             (1 << 5)  /* Bit 5: SSI1 Clock Gating Control */
+#define SYSCON_DCGC1_I2C0             (1 << 12) /* Bit 12: I2C0 Clock Gating Control */
+#define SYSCON_DCGC1_I2C1             (1 << 14) /* Bit 14: I2C1 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER0           (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER1           (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER2           (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */
+#define SYSCON_DCGC1_TIMER3           (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */
+#define SYSCON_DCGC1_COMP0            (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */
+#define SYSCON_DCGC1_COMP1            (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */
+
+/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */
+
+#define SYSCON_DCGC2_GPIO(n)          (1 << (n))
+#define SYSCON_DCGC2_GPIOA            (1 << 0)  /* Bit 0: Port A Clock Gating Control */
+#define SYSCON_DCGC2_GPIOB            (1 << 1)  /* Bit 1: Port B Clock Gating Control */
+#define SYSCON_DCGC2_GPIOC            (1 << 2)  /* Bit 2: Port C Clock Gating Control */
+#define SYSCON_DCGC2_GPIOD            (1 << 3)  /* Bit 3: Port D Clock Gating Control */
+#define SYSCON_DCGC2_GPIOE            (1 << 4)  /* Bit 4: Port E Clock Gating Control */
+#define SYSCON_DCGC2_GPIOF            (1 << 5)  /* Bit 5: Port F Clock Gating Control */
+#define SYSCON_DCGC2_GPIOG            (1 << 6)  /* Bit 6: Port G Clock Gating Control */
+#define SYSCON_DCGC2_GPIOH            (1 << 7)  /* Bit 7: Port H Clock Gating Control */
+#define SYSCON_DCGC2_EMAC0            (1 << 28) /* Bit 28: MAC0 Clock Gating Control */
+#define SYSCON_DCGC2_EPHY0            (1 << 30) /* Bit 30: PHY0 Clock Gating Control */
+
+/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */
+
+#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */
+#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK  (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT)
+#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT   4 /* Bits 6-4: Clock Source */
+#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK    (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_timer.h b/nuttx/arch/arm/src/lm/chip/lm_timer.h
new file mode 100644
index 000000000..f2824ce1f
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_timer.h
@@ -0,0 +1,125 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_timer.h
+ *
+ *   Copyright (C) 2012 Max Nekludov. All rights reserved.
+ *   Author: Max Nekludov <macscomp@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Timer register offsets ***********************************************************/
+
+#define TIMER_GPTMCFG_OFFSET             0x000
+#define TIMER_GPTMTAMR_OFFSET            0x004
+#define TIMER_GPTMCTL_OFFSET             0x00C
+#define TIMER_GPTMIMR_OFFSET             0x018
+#define TIMER_GPTMRIS_OFFSET             0x01C
+#define TIMER_GPTMICR_OFFSET             0x024
+#define TIMER_GPTMTAILR_OFFSET           0x028
+#define TIMER_GPTMTAR_OFFSET             0x048
+
+/* SSI register addresses ***********************************************************/
+
+#define LM3S_TIMER_BASE(n)               (LM3S_TIMER0_BASE + (n)*0x01000)
+
+#define LM3S_TIMER_GPTMCFG(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
+#define LM3S_TIMER_GPTMTAMR(n)           (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
+#define LM3S_TIMER_GPTMCTL(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
+#define LM3S_TIMER_GPTMIMR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
+#define LM3S_TIMER_GPTMRIS(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
+#define LM3S_TIMER_GPTMICR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
+#define LM3S_TIMER_GPTMTAILR(n)          (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
+#define LM3S_TIMER_GPTMTAR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
+
+/* SSI register bit defitiions ******************************************************/
+
+/* GPTM Configuration (GPTMCFG), offset 0x000 */
+
+#define TIMER_GPTMCFG_CFG_SHIFT          0    /* Bits 2-0: GPTM Configuration */
+#define TIMER_GPTM_CFG_MASK              (0x07 << TIMER_GPTMCFG_CFG_SHIFT)
+#define   TIMER_GPTMCFG_CFG_32           (0 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit timer configuration */
+#define   TIMER_GPTMCFG_CFG_RTC          (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 32-bit real-time clock (RTC) counter configuration */
+#define   TIMER_GPTMCFG_CFG_16           (1 << TIMER_GPTMCFG_CFG_SHIFT)       /* 16-bit timer configuration */
+
+/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */
+
+#define TIMER_GPTMTAMR_TAMR_SHIFT        0    /* Bits 1-0: GPTM Timer A Mode */
+#define TIMER_GPTMTAMR_TAMR_MASK         (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT)
+#define   TIMER_GPTMTAMR_TAMR_ONESHOT    (1 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* One-Shot Timer mode */
+#define   TIMER_GPTMTAMR_TAMR_PERIODIC   (2 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Periodic Timer mode */
+#define   TIMER_GPTMTAMR_TAMR_CAPTURE    (3 << TIMER_GPTMTAMR_TAMR_SHIFT)     /* Capture mode */
+#define TIMER_GPTMTAMR_TACMR_SHIFT       2    /* Bits 2:   GPTM Timer A Capture Mode */
+#define TIMER_GPTMTAMR_TACMR_MASK        (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT)
+#define   TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Count mode */
+#define   TIMER_GPTMTAMR_TACMR_EDGETIME  (1 << TIMER_GPTMTAMR_TACMR_SHIFT)    /* Edge-Time mode */
+#define TIMER_GPTMTAMR_TAAMS_SHIFT       3    /* Bits 3:   GPTM Timer A Alternate Mode Select */
+#define TIMER_GPTMTAMR_TAAMS_MASK        (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT)
+#define   TIMER_GPTMTAMR_TAAMS_CAPTURE   (0 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* Capture mode is enabled */
+#define   TIMER_GPTMTAMR_TAAMS_PWM       (1 << TIMER_GPTMTAMR_TAAMS_SHIFT)    /* PWM mode is enabled */
+#define TIMER_GPTMTAMR_TACDIR_SHIFT      4    /* Bits 4:   GPTM Timer A Count Direction */
+#define TIMER_GPTMTAMR_TACDIR_MASK       (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT)
+#define   TIMER_GPTMTAMR_TACDIR_DOWN     (0 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* The timer counts down */
+#define   TIMER_GPTMTAMR_TACDIR_UP       (1 << TIMER_GPTMTAMR_TACDIR_SHIFT)   /* When in one-shot or periodic mode, the timer counts up */
+#define TIMER_GPTMTAMR_TAMIE_SHIFT       5    /* Bits 5:   GPTM Timer A Match Interrupt Enable */
+#define TIMER_GPTMTAMR_TAMIE_MASK        (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT)
+
+/* GPTM Control (GPTMCTL), offset 0x00C */
+
+#define TIMER_GPTMCTL_TAEN_SHIFT         0    /* Bits 0:   GPTM Timer A Enable */
+#define TIMER_GPTMCTL_TAEN_MASK          (0x01 << TIMER_GPTMCTL_TAEN_SHIFT)
+#define TIMER_GPTMCTL_TASTALL_SHIFT      1    /* Bits 1:   GPTM Timer A Stall Enable */
+#define TIMER_GPTMCTL_TASTALL_MASK       (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT)
+
+/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */
+
+#define TIMER_GPTMIMR_TATOIM_SHIFT       0    /* Bits 0:   GPTM Timer A Time-Out Interrupt Mask */
+#define TIMER_GPTMIMR_TATOIM_MASK        (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT)
+
+/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */
+
+#define TIMER_GPTMRIS_TATORIS_SHIFT      0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt */
+#define TIMER_GPTMRIS_TATORIS_MASK       (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT)
+
+/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */
+
+#define TIMER_GPTMICR_TATOCINT_SHIFT     0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt Clear*/
+#define TIMER_GPTMICR_TATOCINT_MASK      (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_uart.h b/nuttx/arch/arm/src/lm/chip/lm_uart.h
new file mode 100644
index 000000000..9a03ff063
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_uart.h
@@ -0,0 +1,347 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_uart.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* UART register offsets ************************************************************/
+
+#define LM3S_UART_DR_OFFSET        0x000 /* UART Data */
+#define LM3S_UART_RSR_OFFSET       0x004 /* UART Receive Status */
+#define LM3S_UART_ECR_OFFSET       0x004 /* UART Error Clear */
+#define LM3S_UART_FR_OFFSET        0x018 /* UART Flag */
+#define LM3S_UART_ILPR_OFFSET      0x020 /* UART IrDA Low-Power Register */
+#define LM3S_UART_IBRD_OFFSET      0x024 /* UART Integer Baud-Rate Divisor*/
+#define LM3S_UART_FBRD_OFFSET      0x028 /* UART Fractional Baud-Rate Divisor */
+#define LM3S_UART_LCRH_OFFSET      0x02c /* UART Line Control */
+#define LM3S_UART_CTL_OFFSET       0x030 /* UART Control */
+#define LM3S_UART_IFLS_OFFSET      0x034 /* UART Interrupt FIFO Level Select */
+#define LM3S_UART_IM_OFFSET        0x038 /* UART Interrupt Mask */
+#define LM3S_UART_RIS_OFFSET       0x03c /* UART Raw Interrupt Status */
+#define LM3S_UART_MIS_OFFSET       0x040 /* UART Masked Interrupt Status */
+#define LM3S_UART_ICR_OFFSET       0x044 /* UART Interrupt Clear */
+#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
+#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
+#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
+#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
+#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
+#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
+#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
+#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
+#define LM3S_UART_PCELLID0_OFFSET  0xff0 /* UART PrimeCell Identification 0 */
+#define LM3S_UART_PCELLID1_OFFSET  0xff4 /* UART PrimeCell Identification 1 */
+#define LM3S_UART_PCELLID2_OFFSET  0xff8 /* UART PrimeCell Identification 2 */
+#define LM3S_UART_PCELLID3_OFFSET  0xffc /* UART PrimeCell Identification 3 */
+
+/* UART register addresses **********************************************************/
+
+#define LM3S_UART_BASE(n)          (LM3S_UART0_BASE + (n)*0x01000)
+
+#define LM3S_UART_DR(n)            (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
+#define LM3S_UART_RSR(n)           (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART_ECR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART_FR(n)            (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
+#define LM3S_UART_ILPR(n)          (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART_IBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART_FBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART_LCRH(n)          (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART_CTL(n)           (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART_IFLS(n)          (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART_IM(n)            (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
+#define LM3S_UART_RIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART_MIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART_ICR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART_PERIPHID4(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART_PERIPHID5(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART_PERIPHID6(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART_PERIPHID7(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART_PERIPHID0(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART_PERIPHID1(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART_PERIPHID2(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART_PERIPHID3(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART_PCELLID0(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART_PCELLID1(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART_PCELLID2(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART_PCELLID3(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
+
+#define LM3S_UART0_DR              (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
+#define LM3S_UART0_RSR             (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART0_ECR             (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART0_FR              (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
+#define LM3S_UART0_ILPR            (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART0_IBRD            (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART0_FBRD            (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART0_LCRH            (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART0_CTL             (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART0_IFLS            (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART0_IM              (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
+#define LM3S_UART0_RIS             (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART0_MIS             (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART0_ICR             (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART0_PERIPHID4       (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART0_PERIPHID5       (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART0_PERIPHID6       (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART0_PERIPHID7       (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART0_PERIPHID0       (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART0_PERIPHID1       (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART0_PERIPHID2       (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART0_PERIPHID3       (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART0_PCELLID0        (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART0_PCELLID1        (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART0_PCELLID2        (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART0_PCELLID3        (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
+
+#define LM3S_UART1_DR              (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
+#define LM3S_UART1_RSR             (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
+#define LM3S_UART1_ECR             (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
+#define LM3S_UART1_FR              (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
+#define LM3S_UART1_ILPR            (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
+#define LM3S_UART1_IBRD            (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
+#define LM3S_UART1_FBRD            (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
+#define LM3S_UART1_LCRH            (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
+#define LM3S_UART1_CTL             (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
+#define LM3S_UART1_IFLS            (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
+#define LM3S_UART1_IM              (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
+#define LM3S_UART1_RIS             (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
+#define LM3S_UART1_MIS             (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
+#define LM3S_UART1_ICR             (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
+#define LM3S_UART1_PERIPHID4       (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
+#define LM3S_UART1_PERIPHID5       (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
+#define LM3S_UART1_PERIPHID6       (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
+#define LM3S_UART1_PERIPHID7       (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
+#define LM3S_UART1_PERIPHID0       (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
+#define LM3S_UART1_PERIPHID1       (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
+#define LM3S_UART1_PERIPHID2       (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
+#define LM3S_UART1_PERIPHID3       (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
+#define LM3S_UART1_PCELLID0        (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
+#define LM3S_UART1_PCELLID1        (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
+#define LM3S_UART1_PCELLID2        (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
+#define LM3S_UART1_PCELLID3        (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
+
+/* UART register bit settings *******************************************************/
+
+/* UART Data (DR), offset 0x000 */
+
+#define UART_DR_DATA_SHIFT         0         /* Bits 7-0: Data Transmitted or Received */
+#define UART_DR_DATA_MASK          (0xff << UART_DR_DATA_SHIFT)
+#define UART_DR_FE                 (1 << 8)  /* Bit 8:  UART Framing Error */
+#define UART_DR_PE                 (1 << 9)  /* Bit 9:  UART Parity Error */
+#define UART_DR_BE                 (1 << 10) /* Bit 10: UART Break Error */
+#define UART_DR_OE                 (1 << 11) /* Bit 11: UART Overrun Error */
+
+/* UART Receive Status (RSR), offset 0x004 */
+
+#define UART_RSR_FE                (1 << 0)  /* Bit 0:  UART Framing Error */
+#define UART_RSR_PE                (1 << 1)  /* Bit 1:  UART Parity Error */
+#define UART_RSR_BE                (1 << 2)  /* Bit 2:  UART Break Error */
+#define UART_RSR_OE                (1 << 3)  /* Bit 3:  UART Overrun Error */
+
+/* UART Error Clear (ECR), offset 0x004 */
+/* Writing any value to this register clears pending error indications */
+
+/* UART Flag (FR), offset 0x018 */
+
+#define UART_FR_BUSY               (1 << 3)  /* Bit 3:  UART Busy */
+#define UART_FR_RXFE               (1 << 4)  /* Bit 4:  UART Receive FIFO Empty */
+#define UART_FR_TXFF               (1 << 5)  /* Bit 5:  UART Transmit FIFO Full */
+#define UART_FR_RXFF               (1 << 6)  /* Bit 6:  UART Receive FIFO Full */
+#define UART_FR_TXFE               (1 << 7)  /* Bit 7:  UART Transmit FIFO Empty */
+
+/* UART IrDA Low-Power Register (ILPR), offset 0x020 */
+
+#define UART_ILPR_DVSR_MASK        (0xff)    /* Bits 7-0: IrDA Low-Power Divisor */
+
+/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */
+
+#define UART_IBRD_DIVINT_MASK      (0xffff)  /* Bits 15-0: Integer Baud-Rate Divisor */
+
+/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */
+
+#define UART_FBRD_DIVFRAC_MASK     (0x3f)    /* Bits 5-0: Fractional Baud-Rate Divisor */
+
+/* Register 7: UART Line Control (LCRH), offset 0x02C */
+
+#define UART_LCRH_BRK              (1 << 0)  /* Bit 0:  UART Send Break */
+#define UART_LCRH_PEN              (1 << 1)  /* Bit 1:  UART Parity Enable */
+#define UART_LCRH_EPS              (1 << 2)  /* Bit 2:  UART Even Parity Select */
+#define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
+#define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
+#define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
+#define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
+#  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
+#  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
+#  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
+#  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
+#define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
+
+/* UART Control (CTL), offset 0x030 */
+
+#define UART_CTL_UARTEN            (1 << 0)  /* Bit 0:  UART Enable */
+#define UART_CTL_SIREN             (1 << 1)  /* Bit 1:  UART SIR Enable */
+#define UART_CTL_SIRLP             (1 << 2)  /* Bit 2:  UART SIR Low Power Mode */
+#define UART_CTL_LBE               (1 << 7)  /* Bit 7:  UART Loop Back Enable */
+#define UART_CTL_TXE               (1 << 8)  /* Bit 8:  UART Transmit Enable */
+#define UART_CTL_RXE               (1 << 9)  /* Bit 9:  UART Receive Enable */
+
+/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */
+
+#define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */
+#define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
+#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+#define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 5-3: UART Receive Interrupt FIFO Level Select */
+#define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
+#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
+
+/* UART Interrupt Mask (IM), offset 0x038 */
+
+#define UART_IM_RXIM               (1 << 4)  /* Bit 4:  UART Receive Interrupt Mask */
+#define UART_IM_TXIM               (1 << 5)  /* Bit 5:  UART Transmit Interrupt Mask */
+#define UART_IM_RTIM               (1 << 6)  /* Bit 6:  UART Receive Time-Out Interrupt Mask */
+#define UART_IM_FEIM               (1 << 7)  /* Bit 7:  UART Framing Error Interrupt Mask */
+#define UART_IM_PEIM               (1 << 8)  /* Bit 8:  UART Parity Error Interrupt Mask */
+#define UART_IM_BEIM               (1 << 9)  /* Bit 9:  UART Break Error Interrupt Mask */
+#define UART_IM_OEIM               (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */
+
+
+/* UART Raw Interrupt Status (RIS), offset 0x03c */
+
+#define UART_RIS_RXRIS             (1 << 4)  /* Bit 4:  UART Receive Raw Interrupt Status */
+#define UART_RIS_TXRIS             (1 << 5)  /* Bit 5:  UART Transmit Raw Interrupt Status */
+#define UART_RIS_RTRIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Raw Interrupt Status */
+#define UART_RIS_FERIS             (1 << 7)  /* Bit 7:  UART Framing Error Raw Interrupt Status */
+#define UART_RIS_PERIS             (1 << 8)  /* Bit 8:  UART Parity Error Raw Interrupt Status */
+#define UART_RIS_BERIS             (1 << 9)  /* Bit 9:  UART Break Error Raw Interrupt Status */
+#define UART_RIS_OERIS             (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */
+
+/* UART Masked Interrupt Status (MIS), offset 0x040 */
+
+#define UART_MIS_RXMIS             (1 << 4)  /* Bit 4:  UART Receive Masked Interrupt Status */
+#define UART_MIS_TXMIS             (1 << 5)  /* Bit 5:  UART Transmit Masked Interrupt Status */
+#define UART_MIS_RTMIS             (1 << 6)  /* Bit 6:  UART Receive Time-Out Masked Interrupt Status */
+#define UART_MIS_FEMIS             (1 << 7)  /* Bit 7:  UART Framing Error Masked Interrupt Status */
+#define UART_MIS_PEMIS             (1 << 8)  /* Bit 8:  UART Parity Error Masked Interrupt Status */
+#define UART_MIS_BEMIS             (1 << 9)  /* Bit 9:  UART Break Error Masked Interrupt Status */
+#define UART_MIS_OEMIS             (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */
+
+/* UART Interrupt Clear (ICR), offset 0x044 */
+
+#define UART_ICR_RXIC             (1 << 4)  /* Bit 4:  Receive Interrupt Clear */
+#define UART_ICR_TXIC             (1 << 5)  /* Bit 5:  Transmit Interrupt Clear */
+#define UART_ICR_RTIC             (1 << 6)  /* Bit 6:  Receive Time-Out Interrupt Clear */
+#define UART_ICR_FEIC             (1 << 7)  /* Bit 7:  Framing Error Interrupt Clear */
+#define UART_ICR_PEIC             (1 << 8)  /* Bit 8:  Parity Error Interrupt Clear */
+#define UART_ICR_BEIC             (1 << 9)  /* Bit 9:  Break Error Interrupt Clear */
+#define UART_ICR_OEIC             (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
+ */
+
+/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
+
+#define UART_PERIPHID4_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
+
+/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
+
+#define UART_PERIPHID5_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
+
+/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
+
+#define UART_PERIPHID6_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
+
+/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
+
+#define UART_PERIPHID7_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
+
+/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
+
+#define UART_PERIPHID0_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
+
+/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
+
+#define UART_PERIPHID1_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
+
+/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
+
+#define UART_PERIPHID2_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
+
+/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
+
+#define UART_PERIPHID3_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
+
+/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
+
+#define UART_CELLID0_MASK         (0xff)    /* UART PrimeCell ID Register[7:0] */
+
+/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
+
+#define UART_CELLID1_MASK         (0xff)    /* UART PrimeCell ID Register[15:8] */
+
+/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
+
+#define UART_CELLID02MASK         (0xff)    /* UART PrimeCell ID Register[23:16] */
+
+/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
+
+#define UART_CELLID3_MASK         (0xff)    /* UART PrimeCell ID Register[31:24] */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */
diff --git a/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c
deleted file mode 100644
index a84dc59dd..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_dumpgpio.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <debug.h>
-
-#include <nuttx/arch.h>
-
-#include "up_arch.h"
-
-#include "chip.h"
-#include "lm_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/* NOTE: this is duplicated in lm3s_gpio.c */
-
-#ifdef LM3S_GPIOH_BASE
-static const uint32_t g_gpiobase[8] =
-{
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
-};
-
-static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
-#else
-static const uint32_t g_gpiobase[8] =
-{
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
-};
-
-static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_gpiobaseaddress
- *
- * Description:
- *   Given a GPIO enumeration value, return the base address of the
- *   associated GPIO registers.
- *
- ****************************************************************************/
-
-static inline uint32_t lm3s_gpiobaseaddress(int port)
-{
-  return g_gpiobase[port & 7];
-}
-
-/****************************************************************************
- * Name: lm3s_gpioport
- *
- * Description:
- *   Given a GPIO enumeration value, return the base address of the
- *   associated GPIO registers.
- *
- ****************************************************************************/
-
-static inline uint8_t lm3s_gpioport(int port)
-{
-  return g_portchar[port & 7];
-}
-
-/****************************************************************************
- * Global Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function:  lm3s_dumpgpio
- *
- * Description:
- *   Dump all GPIO registers associated with the provided base address
- *
- ****************************************************************************/
-
-int lm3s_dumpgpio(uint32_t pinset, const char *msg)
-{
-  irqstate_t   flags;
-  unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  uint32_t     base;
-  uint32_t     rcgc2;
-  bool         enabled;
-
-  /* Get the base address associated with the GPIO port */
-
-  base = lm3s_gpiobaseaddress(port);
-  DEBUGASSERT(base != 0);
-
-  /* The following requires exclusive access to the GPIO registers */
-
-  flags   = irqsave();
-  rcgc2   = getreg32(LM3S_SYSCON_RCGC2);
-  enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
-
-  lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
-        lm3s_gpioport(port), pinset, base, msg);
-  lldbg("  RCGC2: %08x (%s)\n",
-        rcgc2, enabled ? "enabled" : "disabled" );
-
-  /* Don't bother with the rest unless the port is enabled */
-
-  if (enabled)
-    {
-      lldbg("  AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
-            getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET),
-            getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc));
-      lldbg("  IS:    %02x IBE: %02x IEV: %02x IM:  %02x RIS: %08x MIS: %08x\n",
-            getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET),
-            getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET));
-      lldbg("  2MA:   %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
-            getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET),
-            getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET),
-            getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET),
-            getreg32(base + LM3S_GPIO_SLR_OFFSET));
-    }
-  irqrestore(flags);
-  return OK;
-}
diff --git a/nuttx/arch/arm/src/lm/lm3s_ethernet.c b/nuttx/arch/arm/src/lm/lm3s_ethernet.c
deleted file mode 100644
index f6edab5ae..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_ethernet.c
+++ /dev/null
@@ -1,1472 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_ethernet.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#if defined(CONFIG_NET) && defined(CONFIG_LM3S_ETHERNET)
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <time.h>
-#include <string.h>
-#include <debug.h>
-#include <wdog.h>
-#include <errno.h>
-
-#include <nuttx/irq.h>
-#include <nuttx/arch.h>
-#include <arch/board/board.h>
-#include <nuttx/net/uip/uip.h>
-#include <nuttx/net/uip/uip-arp.h>
-#include <nuttx/net/uip/uip-arch.h>
-
-#include "chip.h"
-#include "up_arch.h"
-
-#include "lm_gpio.h"
-#include "lm_ethernet.h"
-#include "chip/lm_pinmap.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Half duplex can be forced if CONFIG_LM3S_ETHHDUPLEX is defined. */
-
-#ifdef CONFIG_LM3S_ETHHDUPLEX
-#  define LM3S_DUPLEX_SETBITS 0
-#  define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
-#else 
-#  define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX
-#  define LM3S_DUPLEX_CLRBITS 0
-#endif
-
-/* Auto CRC generation can be suppressed if CONFIG_LM3S_ETHNOAUTOCRC is definde */
-
-#ifdef CONFIG_LM3S_ETHNOAUTOCRC
-#  define LM3S_CRC_SETBITS 0
-#  define LM3S_CRC_CLRBITS MAC_TCTL_CRC
-#else 
-#  define LM3S_CRC_SETBITS MAC_TCTL_CRC
-#  define LM3S_CRC_CLRBITS 0
-#endif
-
-/* Tx padding can be suppressed if CONFIG_LM3S_ETHNOPAD is defined */
-
-#ifdef CONFIG_LM3S_ETHNOPAD
-#  define LM3S_PADEN_SETBITS 0
-#  define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN
-#else 
-#  define LM3S_PADEN_SETBITS MAC_TCTL_PADEN
-#  define LM3S_PADEN_CLRBITS 0
-#endif
-
-#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS)
-#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS)
-
-/* Multicast frames can be enabled by defining CONFIG_LM3S_MULTICAST */
-
-#ifdef CONFIG_LM3S_MULTICAST
-#  define LM3S_AMUL_SETBITS MAC_RCTL_AMUL
-#  define LM3S_AMUL_CLRBITS 0
-#else 
-#  define LM3S_AMUL_SETBITS 0
-#  define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL
-#endif
-
-/* Promiscuous mode can be enabled by defining CONFIG_LM3S_PROMISCUOUS */
-
-#ifdef CONFIG_LM3S_PROMISCUOUS
-#  define LM3S_PRMS_SETBITS MAC_RCTL_PRMS
-#  define LM3S_PRMS_CLRBITS 0
-#else 
-#  define LM3S_PRMS_SETBITS 0
-#  define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS
-#endif
-
-/* Bad CRC rejection can be enabled by define CONFIG_LM3S_BADCRC */
-
-#ifdef CONFIG_LM3S_BADCRC
-#  define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC
-#  define LM3S_BADCRC_CLRBITS 0
-#else 
-#  define LM3S_BADCRC_SETBITS 0
-#  define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC
-#endif
-
-#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS)
-#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS)
-
-/* CONFIG_LM3S_DUMPPACKET will dump the contents of each packet to the console. */
-
-#ifdef CONFIG_LM3S_DUMPPACKET
-#  define lm3s_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
-#else
-#  define lm3s_dumppacket(m,a,n)
-#endif
-
-/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
-
-#define LM3S_WDDELAY   (1*CLK_TCK)
-#define LM3S_POLLHSEC  (1*2)
-
-/* TX timeout = 1 minute */
-
-#define LM3S_TXTIMEOUT (60*CLK_TCK)
-
-/* This is a helper pointer for accessing the contents of the Ethernet header */
-
-#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf)
-
-#define LM32S_MAX_MDCCLK 2500000
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/* EMAC statistics (debug only) */
-
-#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
-struct lm3s_statistics_s
-{
-  uint32_t rx_int;         /* Number of Rx interrupts received */
-  uint32_t rx_packets;     /* Number of packets received (sum of the following): */
-  uint32_t rx_ip;          /*   Number of Rx IP packets received */
-  uint32_t rx_arp;         /*   Number of Rx ARP packets received */
-  uint32_t rx_dropped;     /*   Number of dropped, unsupported Rx packets */
-  uint32_t rx_pktsize;     /*   Number of dropped, too small or too big */
-  uint32_t rx_errors;      /* Number of Rx errors (reception error) */
-  uint32_t rx_ovrerrors;   /* Number of Rx FIFO overrun errors */
-  uint32_t tx_int;         /* Number of Tx interrupts received */
-  uint32_t tx_packets;     /* Number of Tx packets queued */
-  uint32_t tx_errors;      /* Number of Tx errors (transmission error)*/
-  uint32_t tx_timeouts;    /* Number of Tx timeout errors */
-};
-#  define EMAC_STAT(priv,name) priv->ld_stat.name++
-#else
-#  define EMAC_STAT(priv,name)
-#endif
-
-/* The lm3s_driver_s encapsulates all state information for a single hardware
- * interface
- */
-
-struct lm3s_driver_s
-{
-  /* The following fields would only be necessary on chips that support
-   * multiple Ethernet controllers.
-   */
-
-#if LM3S_NETHCONTROLLERS > 1
-  uint32_t ld_base;             /* Ethernet controller base address */
-  int      ld_irq;              /* Ethernet controller IRQ */
-#endif
-
-  bool     ld_bifup;           /* true:ifup false:ifdown */
-  WDOG_ID  ld_txpoll;          /* TX poll timer */
-  WDOG_ID  ld_txtimeout;       /* TX timeout timer */
-
-#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
-  struct lm3s_statistics_s ld_stat;
-#endif
-
-  /* This holds the information visible to uIP/NuttX */
-
-  struct uip_driver_s ld_dev;  /* Interface understood by uIP */
-};
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-static struct lm3s_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS];
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/* Miscellaneous low level helpers */
-
-#if LM3S_NETHCONTROLLERS > 1
-static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset);
-static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value);
-#else
-static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset);
-static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value);
-#endif
-static void lm3s_ethreset(struct lm3s_driver_s *priv);
-#if 0 /* Not used */
-static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value);
-#endif
-static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr);
-
-/* Common TX logic */
-
-static int  lm3s_transmit(struct lm3s_driver_s *priv);
-static int  lm3s_uiptxpoll(struct uip_driver_s *dev);
-
-/* Interrupt handling */
-
-static void lm3s_receive(struct lm3s_driver_s *priv);
-static void lm3s_txdone(struct lm3s_driver_s *priv);
-static int  lm3s_interrupt(int irq, FAR void *context);
-
-/* Watchdog timer expirations */
-
-static void lm3s_polltimer(int argc, uint32_t arg, ...);
-static void lm3s_txtimeout(int argc, uint32_t arg, ...);
-
-/* NuttX callback functions */
-
-static int  lm3s_ifup(struct uip_driver_s *dev);
-static int  lm3s_ifdown(struct uip_driver_s *dev);
-static int  lm3s_txavail(struct uip_driver_s *dev);
-#ifdef CONFIG_NET_IGMP
-static int  lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
-static int  lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function: lm3s_ethin
- *
- * Description:
- *   Read a register from the Ethernet module
- *
- * Parameters:
- *   priv   - Reference to the driver state structure
- *   offset - Byte offset of the register from the ethernet base address
- *
- * Returned Value:
- *   Register value
- *
- ****************************************************************************/
-
-#if LM3S_NETHCONTROLLERS > 1
-static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset)
-{
-  return getreg32(priv->ld_base + offset);
-}
-#else
-static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset)
-{
-  return getreg32(LM3S_ETHCON_BASE + offset);
-}
-#endif
-
-/****************************************************************************
- * Function: lm3s_ethout
- *
- * Description:
- *   Write a register to the Ethernet module
- *
- * Parameters:
- *   priv   - Reference to the driver state structure
- *   offset - Byte offset of the register from the ethernet base address
- *   value  - The value to write the Ethernet register
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#if LM3S_NETHCONTROLLERS > 1
-static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value)
-{
-  putreg32(value, priv->ld_base + offset);
-}
-#else
-static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value)
-{
-  putreg32(value, LM3S_ETHCON_BASE + offset);
-}
-#endif
-
-/****************************************************************************
- * Function: lm3s_ethreset
- *
- * Description:
- *   Configure and reset the Ethernet module, leaving it in a disabled state.
- *
- * Parameters:
- *   priv   - Reference to the driver state structure
- *
- * Returned Value:
- *   OK on success; a negated errno on failure
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_ethreset(struct lm3s_driver_s *priv)
-{
-  irqstate_t flags;
-  uint32_t regval;
-
-#if LM3S_NETHCONTROLLERS > 1
-#  error "If multiple interfaces are supported, this function would have to be redesigned"
-#endif
-
-  /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
-
-  flags   = irqsave();
-  regval  = getreg32(LM3S_SYSCON_RCGC2);
-  regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_RCGC2);
-  nllvdbg("RCGC2: %08x\n", regval);
-
-  /* Put the Ethernet controller into the reset state */
-
-  regval = getreg32(LM3S_SYSCON_SRCR2);
-  regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_SRCR2);
-
-  /* Wait just a bit.  This is a much longer delay than necessary */
-
-  up_mdelay(2);
-
-  /* Then take the Ethernet controller out of the reset state */
-
-  regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_SRCR2);
-  nllvdbg("SRCR2: %08x\n", regval);
-
-  /* Wait just a bit, again.  If we touch the ethernet too soon, we may busfault. */
-
-  up_mdelay(2);
-
-  /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */
-
-#ifdef CONFIG_LM3S_ETHLEDS
-  /* Configure the pins for the peripheral function */
-
-  lm3s_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
-  lm3s_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
-#endif
-
-  /* Disable all Ethernet controller interrupts */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
-  regval &= ~MAC_IM_ALLINTS;
-  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
-
-  /* Clear any pending interrupts (shouldn't be any) */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
-  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
-  irqrestore(flags);
-}
-
-/****************************************************************************
- * Function: lm3s_phywrite
- *
- * Description:
- *   Write a 16-bit word to a PHY register
- *
- * Parameters:
- *   priv    - Reference to the driver state structure
- *   regaddr - Address of the PHY register to write
- *   value   - The value to write to the register
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#if 0 /* Not used */
-static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value)
-{
-  /* Wait for any MII transactions in progress to complete */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
-
-  /* Set up the data to be written */
-
-  DEBUGASSERT(value < MAC_MTXD_MASK);
-  lm3s_ethout(priv, LM3S_MAC_MTXD_OFFSET, value);
-
-  /* Set up the PHY register address and start the write operation */
-
-  regaddr <<= MAC_MCTL_REGADR_SHIFT;
-  DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
-  lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
-
-  /* Wait for the write transaction to complete */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
-}
-#endif
-
-/****************************************************************************
- * Function: lm3s_phyread
- *
- * Description:
- *   Write a 16-bit word to a PHY register
- *
- * Parameters:
- *   priv    - Reference to the driver state structure
- *   regaddr - Address of the PHY register to write
- *   value   - The value to write to the register
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr)
-{
-  /* Wait for any MII transactions in progress to complete */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
-
-  /* Set up the PHY register address and start the read operation */
-
-  regaddr <<= MAC_MCTL_REGADR_SHIFT;
-  DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
-  lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
-
-  /* Wait for the write transaction to complete */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
-
-  /* Read and return the PHY data */
-
-  return (uint16_t)(lm3s_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
-}
-
-/****************************************************************************
- * Function: lm3s_transmit
- *
- * Description:
- *   Start hardware transmission.  Called either from the txdone interrupt
- *   handling or from watchdog based polling.
- *
- * Parameters:
- *   priv  - Reference to the driver state structure
- *
- * Returned Value:
- *   OK on success; a negated errno on failure
- *
- ****************************************************************************/
-
-static int lm3s_transmit(struct lm3s_driver_s *priv)
-{
-  irqstate_t flags;
-  uint32_t   regval;
-  uint8_t   *dbuf;
-  int        pktlen;
-  int        bytesleft;
-  int        ret = -EBUSY;
-
-  /* Verify that the hardware is ready to send another packet */
-
-  flags = irqsave();
-  if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-    {
-      /* Increment statistics */
-
-      EMAC_STAT(priv, tx_packets);
-      lm3s_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
-
-      /* Transfer the packet into the Tx FIFO.  The LS 16-bits of the first
-       * 32-bit word written to the Tx FIFO contains the Ethernet payload
-       * data length.  That is the full length of the message (d_len) minus
-       * the size of the Ethernet header (14).
-       */
-
-      pktlen     = priv->ld_dev.d_len;
-      nllvdbg("Sending packet, pktlen: %d\n", pktlen);
-      DEBUGASSERT(pktlen > UIP_LLH_LEN);
-
-      dbuf       = priv->ld_dev.d_buf;
-      regval     = (uint32_t)(pktlen - 14);
-      regval    |= ((uint32_t)(*dbuf++) << 16);
-      regval    |= ((uint32_t)(*dbuf++) << 24);
-      lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
-
-      /* Write all of the whole, 32-bit values in the middle of the packet */
-
-      for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4)
-        {
-          /* Transfer a whole word from the user buffer.  Note, the user
-           * buffer may be un-aligned.
-           */
-
-          lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
-        }
-
-      /* Write the last, partial word in the FIFO */
-
-      if (bytesleft > 0)
-        {
-          /* Write the last word */
-
-          regval = 0;
-          switch (bytesleft)
-            {
-              case 0:
-              default:
-                break;
-
-              case 3:
-                regval |= ((uint32_t)dbuf[2] << 16);
-              case 2:
-                regval |= ((uint32_t)dbuf[1] << 8);
-              case 1:
-                regval |= (uint32_t)dbuf[0];
-                break;
-            }
-          lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
-        }
-
-      /* Activate the transmitter */
-
-      lm3s_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX);
-
-      /* Setup the TX timeout watchdog (perhaps restarting the timer) */
-
-      (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32_t)priv);
-      ret = OK;
-    }
-
-  irqrestore(flags);
-  return ret;
-}
-
-/****************************************************************************
- * Function: lm3s_uiptxpoll
- *
- * Description:
- *   The transmitter is available, check if uIP has any outgoing packets ready
- *   to send.  This is a callback from uip_poll().  uip_poll() may be called:
- *
- *   1. When the preceding TX packet send is complete,
- *   2. When the preceding TX packet send timesout and the interface is reset
- *   3. During normal TX polling
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *
- * Returned Value:
- *   OK on success; a negated errno on failure
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static int lm3s_uiptxpoll(struct uip_driver_s *dev)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
-  int ret = OK;
-
-  /* If the polling resulted in data that should be sent out on the network,
-   * the field d_len is set to a value > 0.
-   */
-
-  nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len);
-  if (priv->ld_dev.d_len > 0)
-    {
-      /* Send the packet.  lm3s_transmit() will return zero if the
-       * packet was successfully handled.
-       */
-
-      DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-      uip_arp_out(&priv->ld_dev);
-      ret = lm3s_transmit(priv);
-    }
-
-  /* If zero is returned, the polling will continue until all connections have
-   * been examined.
-   */
-
-  return ret;
-}
-
-/****************************************************************************
- * Function: lm3s_receive
- *
- * Description:
- *   An interrupt was received indicating the availability of a new RX packet
- *
- * Parameters:
- *   priv  - Reference to the driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_receive(struct lm3s_driver_s *priv)
-{
-  uint32_t regval;
-  uint8_t *dbuf;
-  int      pktlen;
-  int      bytesleft;
-
-  /* Loop while there are incoming packets to be processed */
-
-  while ((lm3s_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
-    {
-      /* Update statistics */
-
-      EMAC_STAT(priv, rx_packets);
-
-      /* Copy the data data from the hardware to priv->ld_dev.d_buf.  Set
-       * amount of data in priv->ld_dev.d_len
-       */
-
-      dbuf = priv->ld_dev.d_buf;
-
-      /* The packet frame length begins in the LS 16-bits of the first
-       * word from the FIFO followed by the Ethernet header beginning
-       * in the MS 16-bits of the first word.
-       *
-       * Pick off the packet length from the first word.  This packet length
-       * includes the len/type field (size 2) and the FCS (size 4).
-       */
-
-      regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
-      pktlen = (int)(regval & 0x0000ffff);
-      nllvdbg("Receiving packet, pktlen: %d\n", pktlen);
-
-      /* Check if the pktlen is valid.  It should be large enough to hold
-       * an Ethernet header and small enough to fit entirely in the I/O
-       * buffer.  Six is subtracted to acount for the 2-byte length/type
-       * and 4 byte FCS that are not copied into the uIP packet.
-       */
-
-      if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6))
-        {
-          int wordlen;
-
-          /* We will have to drop this packet */
-
-          nlldbg("Bad packet size dropped (%d)\n", pktlen);
-          EMAC_STAT(priv, rx_pktsize);
-
-          /* The number of bytes and words left to read is pktlen - 4 (including,
-           * the final, possibly partial word) because we've already read 4 bytes.
-           */
-
-          wordlen = (pktlen - 1) >> 2;
-
-          /* Read and discard the remaining words in the FIFO */
-
-          while (wordlen--)
-            {
-              (void)lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
-            }
-
-          /* Check for another packet */
-
-          continue;
-        }
-
-      /* Save the first two bytes from the first word */
-
-      *dbuf++   = (uint8_t)((regval >> 16) & 0xff);
-      *dbuf++   = (uint8_t)((regval >> 24) & 0xff);
-
-      /* Read all of the whole, 32-bit values in the middle of the packet.
-       * We've already read the length (2 bytes) plus the first two bytes
-       * of data.
-       */
-
-      for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4)
-        {
-          /* Transfer a whole word to the user buffer.  Note, the user
-           * buffer may be un-aligned.
-           */
-
-          *(uint32_t*)dbuf = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
-        }
-
-      /* Handle the last, partial word in the FIFO (0-3 bytes) and discard
-       * the 4-byte FCS.
-       */
-
-      for (; bytesleft > 0; bytesleft -= 4)
-        {
-          /* Read the last word.  And transfer all but the last four
-           * bytes of the FCS into the user buffer.
-           */
-
-          regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
-          switch (bytesleft)
-            {
-              default:
-                break;
-
-              case 7:
-                dbuf[2] = (regval >> 16) & 0xff;
-              case 6:
-                dbuf[1] = (regval >> 8) & 0xff;
-              case 5:
-                dbuf[0] = regval & 0xff;
-                break;
-            }
-        }
-
-      /* Pass the packet length to uIP MINUS 2 bytes for the length and
-       * 4 bytes for the FCS.
-       */
-
-      priv->ld_dev.d_len = pktlen - 6;
-      lm3s_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
-
-      /* We only accept IP packets of the configured type and ARP packets */
-
-#ifdef CONFIG_NET_IPv6
-      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6))
-#else
-      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP))
-#endif
-        {
-          nllvdbg("IP packet received (%02x)\n", ETHBUF->type);
-          EMAC_STAT(priv, rx_ip);
-
-          uip_arp_ipin(&priv->ld_dev);
-          uip_input(&priv->ld_dev);
-
-          /* If the above function invocation resulted in data that should be
-           * sent out on the network, the field  d_len will set to a value > 0.
-           */
-
-          if (priv->ld_dev.d_len > 0)
-            {
-              uip_arp_out(&priv->ld_dev);
-              lm3s_transmit(priv);
-            }
-        }
-      else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP))
-        {
-          nllvdbg("ARP packet received (%02x)\n", ETHBUF->type);
-          EMAC_STAT(priv, rx_arp);
-
-          uip_arp_arpin(&priv->ld_dev);
-
-          /* If the above function invocation resulted in data that should be
-           * sent out on the network, the field  d_len will set to a value > 0.
-           */
-
-           if (priv->ld_dev.d_len > 0)
-             {
-               lm3s_transmit(priv);
-             }
-        }
-#ifdef CONFIG_DEBUG
-      else
-        {
-          nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type));
-          EMAC_STAT(priv, rx_dropped);
-        }
-#endif
-    }
-}
-
-/****************************************************************************
- * Function: lm3s_txdone
- *
- * Description:
- *   An interrupt was received indicating that the last TX packet(s) is done
- *
- * Parameters:
- *   priv  - Reference to the driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_txdone(struct lm3s_driver_s *priv)
-{
-  /* Cancel the TX timeout */
-
-  wd_cancel(priv->ld_txtimeout);
-
-  /* Verify that the Tx FIFO is not in use.  The NEWTX bit initiates an
-   * Ethernet transmission once the packet has been placed in the TX FIFO.
-   * This bit is cleared once the transmission has been completed.  Since
-   * we get here because of of TXEMP which indicates that the packet was
-   * transmitted and that the TX FIFO is empty, NEWTX should always be zero
-   * at this point.
-   */
-
-  DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-
-  /* Then poll uIP for new XMIT data */
-
-  (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
-}
-
-/****************************************************************************
- * Function: lm3s_interrupt
- *
- * Description:
- *   Hardware interrupt handler
- *
- * Parameters:
- *   irq     - Number of the IRQ that generated the interrupt
- *   context - Interrupt register state save info (architecture-specific)
- *
- * Returned Value:
- *   OK on success
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static int lm3s_interrupt(int irq, FAR void *context)
-{
-  register struct lm3s_driver_s *priv;
-  uint32_t ris;
-
-#if LM3S_NETHCONTROLLERS > 1
-# error "A mechanism to associate and interface with an IRQ is needed"
-#else
-  priv = &g_lm3sdev[0];
-#endif
-
-  /* Read the raw interrupt status register */
-
-  ris = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
-
-  /* Clear all pending interrupts */
-
-  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, ris);
-
-  /* Check for errors */
-
-#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
-  if ((ris & MAC_RIS_TXER) != 0)
-    {
-      EMAC_STAT(priv, tx_errors);      /* Number of Tx errors */
-    }
-
-  if ((ris & MAC_RIS_FOV) != 0)
-    {
-      EMAC_STAT(priv, rx_ovrerrors);   /* Number of Rx FIFO overrun errors */
-    }
-
-  if ((ris & MAC_RIS_RXER) != 0)
-    {
-      EMAC_STAT(priv, rx_errors);      /* Number of Rx errors */
-    }
-#endif
-
-  /* Handle (unmasked) interrupts according to status bit settings */
-
-  ris &= lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
-
-  /* Is this an Rx interrupt (meaning that a packet has been received)? */
-
-  if ((ris & MAC_RIS_RXINT) != 0)
-    {
-      /* Handle the incoming packet */
-
-      EMAC_STAT(priv, rx_int);
-      lm3s_receive(priv);
-    }
-
-  /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */
-
-  if ((ris & MAC_RIS_TXEMP) != 0)
-    {
-       /* Handle the complete of the transmission */
-
-      EMAC_STAT(priv, tx_int);
-      lm3s_txdone(priv);
-    }
-
-  /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if 
-   * there are no pending transmissions).
-   */
-
-  return OK;
-}
-
-/****************************************************************************
- * Function: lm3s_txtimeout
- *
- * Description:
- *   Our TX watchdog timed out.  Called from the timer interrupt handler.
- *   The last TX never completed.  Reset the hardware and start again.
- *
- * Parameters:
- *   argc - The number of available arguments
- *   arg  - The first argument
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_txtimeout(int argc, uint32_t arg, ...)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg;
-
-  /* Increment statistics */
-
-  nlldbg("Tx timeout\n");
-  EMAC_STAT(priv, tx_timeouts);
-
-  /* Then reset the hardware */
-
-  DEBUGASSERT(priv->ld_bifup);
-  lm3s_ifdown(&priv->ld_dev);
-  lm3s_ifup(&priv->ld_dev);
-
-  /* Then poll uIP for new XMIT data */
-
-  (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
-}
-
-/****************************************************************************
- * Function: lm3s_polltimer
- *
- * Description:
- *   Periodic timer handler.  Called from the timer interrupt handler.
- *
- * Parameters:
- *   argc - The number of available arguments
- *   arg  - The first argument
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static void lm3s_polltimer(int argc, uint32_t arg, ...)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg;
-
-  /* Check if we can send another Tx packet now.  The NEWTX bit initiates an
-   * Ethernet transmission once the packet has been placed in the TX FIFO.
-   * This bit is cleared once the transmission has been completed.
-   *
-   * NOTE: This can cause missing poll cycles and, hence, some timing
-   * inaccuracies.
-   */
-
-  if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-    {
-      /* If so, update TCP timing states and poll uIP for new XMIT data */
-
-      (void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC);
-
-      /* Setup the watchdog poll timer again */
-
-      (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg);
-    }
-}
-
-/****************************************************************************
- * Function: lm3s_ifup
- *
- * Description:
- *   NuttX Callback: Bring up the Ethernet interface when an IP address is
- *   provided 
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static int lm3s_ifup(struct uip_driver_s *dev)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
-  irqstate_t flags;
-  uint32_t regval;
-  uint32_t div;
-  uint16_t phyreg;
-
-  nlldbg("Bringing up: %d.%d.%d.%d\n",
-       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
-
-  /* Enable and reset the Ethernet controller */
-
-  flags = irqsave();
-  lm3s_ethreset(priv);
-
-  /* Set the management clock divider register for access to the PHY
-   * register set. The MDC clock is divided down from the system clock per:
-   *
-   *   MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1))
-   *   div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1
-   *
-   * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000.  We will
-   * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded.
-   */
-
-  div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK;
-  lm3s_ethout(priv, LM3S_MAC_MDV_OFFSET, div);
-  nllvdbg("MDV:   %08x\n", div);
-
-  /* Then configure the Ethernet Controller for normal operation 
-   *
-   * Setup the transmit control register (Full duplex, TX CRC Auto Generation,
-   * TX Padding Enabled).
-   */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET);
-  regval &= ~LM3S_TCTCL_CLRBITS;
-  regval |= LM3S_TCTCL_SETBITS;
-  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
-  nllvdbg("TCTL:  %08x\n", regval);
-
-  /* Setup the receive control register (Disable multicast frames, disable
-   * promiscuous mode, disable bad CRC rejection).
-   */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval &= ~LM3S_RCTCL_CLRBITS;
-  regval |= LM3S_RCTCL_SETBITS;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-  nllvdbg("RCTL:  %08x\n", regval);
-
-  /* Setup the time stamp configuration register */
-
-#ifdef LM3S_ETHTS
-  regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET);
-#ifdef CONFIG_LM3S_TIMESTAMP
-  regval |= MAC_TS_EN;
-#else
-  regval &= ~(MAC_TS_EN);
-#endif
-  lm3s_ethout(priv, LM3S_MAC_TS_OFFSET, regval);
-  nllvdbg("TS:    %08x\n", regval);
-#endif
-
-  /* Wait for the link to come up.  This following is not very conservative
-   * of system resources -- it really should wait gracefully on a semaphore
-   * and the interrupt handler should post the semaphore when LINKSTATUS is
-   * set
-   */
-
-  nlldbg("Waiting for link\n");
-  do
-    {
-      phyreg = lm3s_phyread(priv, MII_MSR);
-    }
-  while ((phyreg & MII_MSR_LINKSTATUS) == 0);
-  nlldbg("Link established\n");
-
-  /* Reset the receive FIFO */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RSTFIFO;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Enable the Ethernet receiver */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RXEN;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Enable the Ethernet transmitter */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET);
-  regval |= MAC_TCTL_TXEN;
-  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
-
-  /* Reset the receive FIFO (again) */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RSTFIFO;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Enable the Ethernet interrupt */
-
-#if LM3S_NETHCONTROLLERS > 1
-  up_enable_irq(priv->irq);
-#else
-  up_enable_irq(LM3S_IRQ_ETHCON);
-#endif
-
-  /* Enable the Ethernet RX packet receipt interrupt */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
-  regval |= MAC_IM_RXINTM;
-  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
-
-  /* Program the hardware with it's MAC address (for filtering) */
-
-  regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 |
-           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 |
-           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 |
-           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0];
-  lm3s_ethout(priv, LM3S_MAC_IA0_OFFSET, regval);
-
-  regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 |
-           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4];
-  lm3s_ethout(priv, LM3S_MAC_IA1_OFFSET, regval);
-
-  /* Set and activate a timer process */
-
-  (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, (uint32_t)priv);
-
-  priv->ld_bifup = true;
-  irqrestore(flags);
-  return OK;
-}
-
-/****************************************************************************
- * Function: lm3s_ifdown
- *
- * Description:
- *   NuttX Callback: Stop the interface.  The only way to restore normal
- *   behavior is to call lm3s_ifup().
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-static int lm3s_ifdown(struct uip_driver_s *dev)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
-  irqstate_t flags;
-  uint32_t regval;
-
-  nlldbg("Taking down: %d.%d.%d.%d\n",
-       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
-
-  /* Cancel the TX poll timer and TX timeout timers */
-
-  flags = irqsave();
-  wd_cancel(priv->ld_txpoll);
-  wd_cancel(priv->ld_txtimeout);
-
-  /* Disable the Ethernet interrupt */
-
-#if LM3S_NETHCONTROLLERS > 1
-  up_disable_irq(priv->irq);
-#else
-  up_disable_irq(LM3S_IRQ_ETHCON);
-#endif
-
-  /* Disable all Ethernet controller interrupt sources */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET);
-  regval &= ~MAC_IM_ALLINTS;
-  lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
-
-  /* Reset the receive FIFO */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RSTFIFO;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Disable the Ethernet receiver */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval &= ~MAC_RCTL_RXEN;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Disable the Ethernet transmitter */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval &= ~MAC_TCTL_TXEN;
-  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
-
-  /* Reset the receive FIFO (again) */
-
-  regval  = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval |= MAC_RCTL_RSTFIFO;
-  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-
-  /* Clear any pending interrupts */
-
-  regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET);
-  lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
-
-  /* The interface is now DOWN */
-
-  priv->ld_bifup = false;
-  irqrestore(flags);
-  return OK;
-}
-
-/****************************************************************************
- * Function: lm3s_txavail
- *
- * Description:
- *   Driver callback invoked when new TX data is available.  This is a 
- *   stimulus perform an out-of-cycle poll and, thereby, reduce the TX
- *   latency.
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *   Called in normal user mode
- *
- ****************************************************************************/
-
-static int lm3s_txavail(struct uip_driver_s *dev)
-{
-  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private;
-  irqstate_t flags;
-
-  /* Ignore the notification if the interface is not yet up or if the Tx FIFO
-   * hardware is not available at this time.  The NEWTX bit initiates an
-   * Ethernet transmission once the packet has been placed in the TX FIFO.
-   * This bit is cleared once the transmission has been completed.  When the
-   * transmission completes, lm3s_txdone() will be called and the Tx polling
-   * will occur at that time.
-   */
-
-  flags = irqsave();
-  if (priv->ld_bifup && (lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
-    {
-      /* If the interface is up and we can use the Tx FIFO, then poll uIP
-       * for new Tx data
-       */
-
-      (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll);
-    }
-
-  irqrestore(flags);
-  return OK;
-}
-
-/****************************************************************************
- * Function: lm3s_addmac
- *
- * Description:
- *   NuttX Callback: Add the specified MAC address to the hardware multicast
- *   address filtering
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *   mac  - The MAC address to be added 
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#ifdef CONFIG_NET_IGMP
-static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
-{
-  FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private;
-
-  /* Add the MAC address to the hardware multicast routing table */
-
-#warning "Multicast MAC support not implemented"
-  return OK;
-}
-#endif
-
-/****************************************************************************
- * Function: lm3s_rmmac
- *
- * Description:
- *   NuttX Callback: Remove the specified MAC address from the hardware multicast
- *   address filtering
- *
- * Parameters:
- *   dev  - Reference to the NuttX driver state structure
- *   mac  - The MAC address to be removed 
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#ifdef CONFIG_NET_IGMP
-static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
-{
-  FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private;
-
-  /* Add the MAC address to the hardware multicast routing table */
-
-#warning "Multicast MAC support not implemented"
-  return OK;
-}
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function: lm3s_ethinitialize
- *
- * Description:
- *   Initialize the Ethernet driver for one interface
- *
- * Parameters:
- *   None
- *
- * Returned Value:
- *   OK on success; Negated errno on failure.
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#if LM3S_NETHCONTROLLERS > 1
-int lm3s_ethinitialize(int intf)
-#else
-static inline int lm3s_ethinitialize(int intf)
-#endif
-{
-  struct lm3s_driver_s *priv = &g_lm3sdev[intf];
-  int ret;
-
-  /* Check if the Ethernet module is present */
-
-  ndbg("Setting up eth%d\n", intf);
-
-#if LM3S_NETHCONTROLLERS > 1
-# error "This debug check only works with one interface"
-#else
-  DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
-#endif
-  DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS);
-
-  /* Initialize the driver structure */
-
-  memset(priv, 0, sizeof(struct lm3s_driver_s));
-  priv->ld_dev.d_ifup    = lm3s_ifup;     /* I/F down callback */
-  priv->ld_dev.d_ifdown  = lm3s_ifdown;   /* I/F up (new IP address) callback */
-  priv->ld_dev.d_txavail = lm3s_txavail;  /* New TX data callback */
-#ifdef CONFIG_NET_IGMP
-  priv->ld_dev.d_addmac  = lm3s_addmac;   /* Add multicast MAC address */
-  priv->ld_dev.d_rmmac   = lm3s_rmmac;    /* Remove multicast MAC address */
-#endif
-  priv->ld_dev.d_private = (void*)priv;   /* Used to recover private state from dev */
-
-  /* Create a watchdog for timing polling for and timing of transmisstions */
-
-#if LM3S_NETHCONTROLLERS > 1
-# error "A mechanism to associate base address an IRQ with an interface is needed"
-  priv->ld_base          = ??;            /* Ethernet controller base address */
-  priv->ld_irq           = ??;            /* Ethernet controller IRQ number */
-#endif
-  priv->ld_txpoll        = wd_create();   /* Create periodic poll timer */
-  priv->ld_txtimeout     = wd_create();   /* Create TX timeout timer */
-
-  /* If the board can provide us with a MAC address, get the address
-   * from the board now.  The MAC will not be applied until lm3s_ifup()
-   * is caleld (and the MAC can be overwritten with a netdev ioctl call). 
-   */
-
-#ifdef CONFIG_LM3S_BOARDMAC
-   lm3s_ethernetmac(&priv->ld_dev.d_mac);
-#endif
-
-  /* Perform minimal, one-time initialization -- just reset the controller and
-   * leave it disabled.  The Ethernet controller will be reset and properly
-   * re-initialized each time lm3s_ifup() is called.
-   */
-
-  lm3s_ethreset(priv);
-  lm3s_ifdown(&priv->ld_dev);
-
-  /* Attach the IRQ to the driver */
-
-#if LM3S_NETHCONTROLLERS > 1
-  ret = irq_attach(priv->irq, lm3s_interrupt);
-#else
-  ret = irq_attach(LM3S_IRQ_ETHCON, lm3s_interrupt);
-#endif
-  if (ret != 0)
-    {
-      /* We could not attach the ISR to the IRQ */
-
-      return -EAGAIN;
-    }
-
-  /* Register the device with the OS so that socket IOCTLs can be performed */
-
-  (void)netdev_register(&priv->ld_dev);
-  return OK;
-}
-
-
-/************************************************************************************
- * Name: up_netinitialize
- *
- * Description:
- *   Initialize the first network interface.  If there are more than one interface
- *   in the chip, then board-specific logic will have to provide this function to
- *   determine which, if any, Ethernet controllers should be initialized.
- *
- ************************************************************************************/
-
-#if LM3S_NETHCONTROLLERS == 1
-void up_netinitialize(void)
-{
-  (void)lm3s_ethinitialize(0);
-}
-#endif
-
-#endif /* CONFIG_NET && CONFIG_LM3S_ETHERNET */
-
diff --git a/nuttx/arch/arm/src/lm/lm3s_gpio.c b/nuttx/arch/arm/src/lm/lm3s_gpio.c
deleted file mode 100644
index 48cbefabf..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_gpio.c
+++ /dev/null
@@ -1,854 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_gpio.c
- * arch/arm/src/chip/lm3s_gpio.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <string.h>
-#include <assert.h>
-#include <debug.h>
-
-#include <arch/irq.h>
-
-#include "up_arch.h"
-#include "os_internal.h"
-#include "lm_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* These definitions are part of the implementation of the  GPIO pad
- * configuration of Table 9-1 in the LM3S6918 data sheet.
- */
-
-#define AFSEL_SHIFT            5
-#define AFSEL_1                (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */
-#define AFSEL_0                0
-#define AFSEL_X                0
-
-#define DIR_SHIFT              4
-#define DIR_1                  (1 << DIR_SHIFT)   /* Set/clear bit in GPIO DIR register */
-#define DIR_0                  0
-#define DIR_X                  0
-
-#define ODR_SHIFT              3
-#define ODR_1                  (1 << ODR_SHIFT)   /* Set/clear bit in GPIO ODR register */
-#define ODR_0                  0
-#define ODR_X                  0
-
-#define DEN_SHIFT              2
-#define DEN_1                  (1 << DEN_SHIFT)   /* Set/clear bit in GPIO DEN register */
-#define DEN_0                  0
-#define DEN_X                  0
-
-#define PUR_SHIFT              1
-#define PUR_1                  (1 << PUR_SHIFT)   /* Set/clear bit in GPIO PUR register */
-#define PUR_0                  0
-#define PUR_X                  0
-
-#define PDR_SHIFT              0
-#define PDR_1                  (1 << PDR_SHIFT)   /* Set/clear bit in GPIO PDR register */
-#define PDR_0                  0
-#define PDR_X                  0
-
-#define GPIO_INPUT_SETBITS     (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_INPUT_CLRBITS     (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_OUTPUT_SETBITS    (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_OUTPUT_CLRBITS    (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_ODINPUT_SETBITS   (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_ODINPUT_CLRBITS   (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_ODOUTPUT_SETBITS  (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_ODOUTPUT_CLRBITS  (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_PFODIO_SETBITS    (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_PFODIO_CLRBITS    (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_PFIO_SETBITS      (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_PFIO_CLRBITS      (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X)
-
-#define GPIO_ANINPUT_SETBITS   (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0)
-#define GPIO_ANINPUT_CLRBITS   (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1)
-
-#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X)
-#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X)
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-struct gpio_func_s
-{
-  uint8_t setbits;  /* A set of GPIO register bits to set */
-  uint8_t clrbits;  /* A set of GPIO register bits to clear */
-};
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-static const struct gpio_func_s g_funcbits[] =
-{
-  {GPIO_INPUT_SETBITS,     GPIO_INPUT_CLRBITS},     /* GPIO_FUNC_INPUT */
-  {GPIO_OUTPUT_SETBITS,    GPIO_OUTPUT_CLRBITS},    /* GPIO_FUNC_OUTPUT */
-  {GPIO_ODINPUT_SETBITS,   GPIO_ODINPUT_CLRBITS},   /* GPIO_FUNC_ODINPUT */
-  {GPIO_ODOUTPUT_SETBITS,  GPIO_ODOUTPUT_CLRBITS},  /* GPIO_FUNC_ODOUTPUT */
-  {GPIO_PFODIO_SETBITS,    GPIO_PFODIO_CLRBITS},    /* GPIO_FUNC_PFODIO */
-  {GPIO_PFIO_SETBITS,      GPIO_PFIO_CLRBITS},      /* GPIO_FUNC_PFIO */
-  {GPIO_ANINPUT_SETBITS,   GPIO_ANINPUT_CLRBITS},   /* GPIO_FUNC_ANINPUT */
-  {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
-};
-
-static const uint32_t g_gpiobase[LM3S_NPORTS] =
-{
-  /* All support LM3S parts have at least 7 ports, GPIOA-G */
-
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE,
-
-  /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
-
-#if LM3S_NPORTS > 7
-  LM3S_GPIOH_BASE,
-#endif
-
-  /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
-
-#if LM3S_NPORTS > 8
-  LM3S_GPIOJ_BASE,
-#endif
-};
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_gpiobaseaddress
- *
- * Description:
- *   Given a GPIO enumeration value, return the base address of the
- *   associated GPIO registers.
- *
- ****************************************************************************/
-
-static uint32_t lm3s_gpiobaseaddress(unsigned int port)
-{
-  uint32_t gpiobase = 0;
-  if (port < LM3S_NPORTS)
-    {
-      gpiobase = g_gpiobase[port];
-    }
-  return gpiobase;
-}
-
-/****************************************************************************
- * Name: lm3s_gpiofunc
- *
- * Description:
- *   Configure GPIO registers for a specific function
- *
- ****************************************************************************/
-
-static void lm3s_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func)
-{
-  uint32_t setbit;
-  uint32_t clrbit;
-  uint32_t regval;
-
-  /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain
-   * control register. Setting a bit in this register enables the open drain
-   * configuration of the corresponding GPIO pad. When open drain mode is enabled,
-   * the corresponding bit should also be set in the GPIO Digital Input Enable
-   * (GPIO DEN) register ... Corresponding bits in the drive strength registers
-   * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the
-   * desired rise and fall times. The GPIO acts as an open drain input if the
-   * corresponding bit in the GPIO DIR register is set to 0; and as an open
-   * drain output when set to 1."
-   */
-
-  setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
-
-  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
-  regval &= ~clrbit;
-  regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
-
-  /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
-   * register. When a bit is set to 1, it enables a weak pull-up resistor on the
-   * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
-   * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
-   */
-
-  setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno;
-
-  if (setbit || clrbit)
-    {
-      regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
-      regval &= ~clrbit;
-      regval |= setbit;
-      putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
-    }
-
-  /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
-   * register. When a bit is set to 1, it enables a weak pull-down resistor on the
-   * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
-   * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
-   */
-
-  setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno;
-
-  if (setbit || clrbit)
-    {
-      regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
-      regval &= ~clrbit;
-      regval |= setbit;
-      putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
-    }
-
-  /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
-   * register. By default, with the exception of the GPIO signals used for JTAG/SWD
-   * function, all other GPIO signals are configured out of reset to be undriven
-   * (tristate). Their digital function is disabled; they do not drive a logic
-   * value on the pin and they do not allow the pin voltage into the GPIO receiver.
-   * To use the pin in a digital function (either GPIO or alternate function), the
-   * corresponding GPIODEN bit must be set."
-   */
-
-  setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
-
-  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
-  regval &= ~clrbit;
-  regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
-
-  /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
-   * direction register. Bits set to 1 in the GPIODIR register configure
-   * the corresponding pin to be an output, while bits set to 0 configure the
-   * pins to be inputs. All bits are cleared by a reset, meaning all GPIO
-   * pins are inputs by default.
-   */
-
-  setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
-
-  regval = getreg32(base + LM3S_GPIO_DIR_OFFSET);
-  regval &= ~clrbit;
-  regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_DIR_OFFSET);
-
-  /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
-   * control select register. Writing a 1 to any bit in this register selects
-   * the hardware control for the corresponding GPIO line. All bits are cleared
-   * by a reset, therefore no GPIO line is set to hardware control by default."
-   *
-   * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit
-   * and unlock the GPIO.  That is not implemented here.
-   */
-
-  setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
-  clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
-
-  regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET);
-  regval &= ~clrbit;
-  regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET);
-}
-
-/****************************************************************************
- * Name: lm3s_gpiopadstrength
- *
- * Description:
- *   Set up pad strength and pull-ups
- *
- ****************************************************************************/
-
-static inline void lm3s_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset)
-{
-  int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT;
-  uint32_t regoffset;
-  uint32_t regval;
-  uint32_t slrset;
-  uint32_t slrclr;
-
-  /* Prepare bits to disable slew */
-
-  slrset = 0;
-  slrclr = pin;
-
-  switch (strength)
-    {
-      case 0: /* 2mA pad drive strength */
-        {
-          /* "The GPIODR2R register is the 2-mA drive control register. It
-           * allows for each GPIO signal in the port to be individually configured
-           * without affecting the other pads. When writing a DRV2 bit for a GPIO
-           * signal, the corresponding DRV4 bit in the GPIO DR4R register and the
-           * DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
-           */
-
-          regoffset = LM3S_GPIO_DR2R_OFFSET;
-        }
-        break;
-
-      case 1: /* 4mA pad drive strength */
-        {
-          /* "The GPIODR4R register is the 4-mA drive control register. It allows
-           * for each GPIO signal in the port to be individually configured without
-           * affecting the other pads. When writing the DRV4 bit for a GPIO signal,
-           * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit
-           * in the GPIO DR8R register are automatically cleared by hardware."
-           */
-
-          regoffset = LM3S_GPIO_DR4R_OFFSET;
-        }
-        break;
-
-      case 3: /* 8mA Pad drive with slew rate control */
-        {
-          /* "The GPIOSLR register is the slew rate control register. Slew rate
-           * control is only available when using the 8-mA drive strength option
-           * via the GPIO 8-mA Drive Select (GPIODR8R) register..."
-           */
-
-          slrset = pin;
-          slrclr = 0;
-        }
-        /* Fall through */
-
-      case 2: /* 8mA pad drive strength (without slew rate control) */
-        {
-          /* "The GPIODR8R register is the 8-mA drive control register. It
-           * allows for each GPIO signal in the port to be individually configured
-           * without affecting the other pads. When writing the DRV8 bit for a GPIO
-           * signal, the corresponding DRV2 bit in the GPIO DR2R register and the
-           * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
-           */
-
-          regoffset = LM3S_GPIO_DR8R_OFFSET;
-        }
-        break;
-    }
-
-  /* Set the selected pad strength and set/clear optional slew rate control */
-
-  regval = getreg32(base + regoffset);
-  regval |= pin;
-  putreg32(regval, base + regoffset);
-
-  regval  = getreg32(base + LM3S_GPIO_SLR_OFFSET);
-  regval &= slrclr;
-  regval |= slrset;
-  putreg32(regval, base + LM3S_GPIO_SLR_OFFSET);
-}
-
-/****************************************************************************
- * Name: lm3s_gpiopadtype
- *
- * Description:
- *   Set up pad strength and pull-ups.  Some of these values may be over-
- *   written by lm3s_gpiofunc, depending on the function selection.  Others
- *   are optional for different function selections.
- *
- ****************************************************************************/
-
-static inline void lm3s_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
-{
-  int padtype  = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT;
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  uint32_t odrset;
-  uint32_t odrclr;
-#endif
-  uint32_t purset;
-  uint32_t purclr;
-  uint32_t pdrset;
-  uint32_t pdrclr;
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  uint32_t denset;
-  uint32_t denclr;
-#endif
-  uint32_t regval;
-
-  /* Assume digital GPIO function, push-pull with no pull-up or pull-down */
-
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  odrset = 0;
-  odrclr = pin;
-#endif
-  purset = 0;
-  purclr = pin;
-  pdrset = 0;
-  pdrclr = pin;
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  denset = pin;
-  denclr = 0;
-#endif
-
-  switch (padtype)
-    {
-      case 0: /* Push-pull */
-      default:
-        {
-        }
-        break;
-
-      case 1: /* Push-pull with weak pull-up */
-        {
-          purset = pin;
-          purclr = 0;
-        }
-        break;
-      case 2: /* Push-pull with weak pull-down */
-        {
-          pdrset = pin;
-          pdrclr = 0;
-        }
-        break;
-      case 3: /* Open-drain */
-        {
-#if 0 /* always overwritten by lm3s_gpiofunc */
-          odrset = pin;
-          odrclr = 0;
-#endif
-        }
-        break;
-      case 4: /* Open-drain with weak pull-up */
-        {
-#if 0 /* always overwritten by lm3s_gpiofunc */
-          odrset = pin;
-          odrclr = 0;
-#endif
-          purset = pin;
-          purclr = 0;
-        }
-        break;
-      case 5: /* Open-drain with weak pull-down */
-        {
-#if 0 /* always overwritten by lm3s_gpiofunc */
-          odrset = pin;
-          odrclr = 0;
-#endif
-          pdrset = pin;
-          pdrclr = 0;
-        }
-        break;
-      case 6: /* Analog comparator */
-        {
-#if 0 /* always overwritten by lm3s_gpiofunc */
-          denset = 0;
-          denclr = pin;
-#endif
-        }
-        break;
-    }
-
-  /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain
-   * control register. Setting a bit in this register enables the open drain
-   * configuration of the corresponding GPIO pad. When open drain mode is enabled,
-   * the corresponding bit should also be set in the GPIO Digital Input Enable
-   * (GPIO DEN) register ... Corresponding bits in the drive strength registers
-   * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the
-   * desired rise and fall times. The GPIO acts as an open drain input if the
-   * corresponding bit in the GPIO DIR register is set to 0; and as an open
-   * drain output when set to 1."
-   */
-
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
-  regval &= ~odrclr;
-  regval |= odrset;
-  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
-#endif
-
-  /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
-   * register. When a bit is set to 1, it enables a weak pull-up resistor on the
-   * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
-   * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
-   */
-
-  regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
-  regval &= ~purclr;
-  regval |= purset;
-  putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
-
-  /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
-   * register. When a bit is set to 1, it enables a weak pull-down resistor on the
-   * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
-   * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
-   */
-
-  regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
-  regval &= ~pdrclr;
-  regval |= pdrset;
-  putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
-
-  /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
-   * register. By default, with the exception of the GPIO signals used for JTAG/SWD
-   * function, all other GPIO signals are configured out of reset to be undriven
-   * (tristate). Their digital function is disabled; they do not drive a logic
-   * value on the pin and they do not allow the pin voltage into the GPIO receiver.
-   * To use the pin in a digital function (either GPIO or alternate function), the
-   * corresponding GPIODEN bit must be set."
-   */
-
-#if 0 /* always overwritten by lm3s_gpiofunc */
-  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
-  regval &= ~denclr;
-  regval |= denset;
-  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
-#endif
-}
-
-/****************************************************************************
- * Name: lm3s_initoutput
- *
- * Description:
- *   Set the GPIO output value
- *
- ****************************************************************************/
-
-static inline void lm3s_initoutput(uint32_t cfgset)
-{
-  bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO);
-  lm3s_gpiowrite(cfgset, value);
-}
-
-/****************************************************************************
- * Name: lm3s_interrupt
- *
- * Description:
- *   Configure the interrupt pin.
- *
- ****************************************************************************/
-
-static inline void lm3s_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
-{
-  int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT;
-  uint32_t regval;
-  uint32_t isset;
-  uint32_t isclr;
-  uint32_t ibeset;
-  uint32_t ibeclr;
-  uint32_t iveset;
-  uint32_t iveclr;
-
-  /* Mask and clear the GPIO interrupt
-   *
-   * "The GPIOIM register is the interrupt mask register. Bits set to High in
-   * GPIO IM allow the corresponding pins to trigger their individual interrupts
-   * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering
-   * on that pin. All bits are cleared by a reset."
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
-  regval &= ~pin;
-  putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
-
-  /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
-   * in this register clears the corresponding interrupt edge detection logic
-   * register. Writing a 0 has no effect."
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_ICR_OFFSET);
-  regval |= pin;
-  putreg32(regval, base + LM3S_GPIO_ICR_OFFSET);
-
-  /* Assume rising edge */
-
-  isset  = 0;            /* Not level sensed */
-  isclr  = pin;
-  ibeset = 0;            /* Single edge */
-  ibeclr = pin;
-  iveset = pin;          /* Rising edge or high levels*/
-  iveclr = 0;
-
-  /* Then handle according to the selected interrupt type */
-
-  switch (inttype)
-    {
-      case 0:            /* Interrupt on falling edge */
-        {
-          iveset = 0;    /* Falling edge or low levels*/
-          iveclr = pin;
-        }
-        break;
-
-      case 1:           /* Interrupt on rising edge */
-      default:
-        break;
-
-      case 2:           /* Interrupt on both edges */
-        {
-          ibeset = pin; /* Both edges */
-          ibeclr = 0;
-        }
-        break;
-
-      case 3:           /* Interrupt on low level */
-        {
-          isset = pin;  /* Level sensed */
-          isclr = 0;
-          iveset = 0;   /* Falling edge or low levels*/
-          iveclr = pin;
-        }
-        break;
-
-      case 4:           /* Interrupt on high level */
-        {
-          isset = pin;  /* Level sensed */
-          isclr = 0;
-        }
-        break;
-    }
-
-  /* "The GPIO IS register is the interrupt sense register. Bits set to
-   * 1 in GPIOIS configure the corresponding pins to detect levels, while
-   * bits set to 0 configure the pins to detect edges. All bits are cleared
-   * by a reset.
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_IS_OFFSET);
-  regval &= isclr;
-  regval |= isset;
-  putreg32(regval, base + LM3S_GPIO_IS_OFFSET);
-
-  /* "The GPIO IBE register is the interrupt both-edges register. When the
-   * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
-   * set to detect edges, bits set to High in GPIO IBE configure the
-   * corresponding pin to detect both rising and falling edges, regardless
-   * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ...
-   * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits
-   * are cleared by a reset.
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_IBE_OFFSET);
-  regval &= ibeclr;
-  regval |= ibeset;
-  putreg32(regval, base + LM3S_GPIO_IBE_OFFSET);
-
-  /* "The GPIOIEV register is the interrupt event register. Bits set to
-   * High in GPIO IEV configure the corresponding pin to detect rising edges
-   * or high levels, depending on the corresponding bit value in the GPIO
-   * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to
-   * detect falling edges or low levels, depending on the corresponding bit
-   * value in GPIOIS. All bits are cleared by a reset.
-   */
-
-  regval  = getreg32(base + LM3S_GPIO_IEV_OFFSET);
-  regval &= iveclr;
-  regval |= iveset;
-  putreg32(regval, base + LM3S_GPIO_IEV_OFFSET);
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_configgpio
- *
- * Description:
- *   Configure a GPIO pin based on bit-encoded description of the pin.
- *
- ****************************************************************************/
-
-int lm3s_configgpio(uint32_t cfgset)
-{
-  irqstate_t   flags;
-  unsigned int func;
-  unsigned int port;
-  unsigned int pinno;
-  uint32_t     pin;
-  uint32_t     base;
-  uint32_t     regval;
-
-  /* Decode the basics */
-
-  func  = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT;
-  port  = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  pinno = (cfgset & GPIO_NUMBER_MASK);
-  pin   = (1 <<pinno);
-
-  DEBUGASSERT(func <= GPIO_FUNC_MAX);
-
-  /* Get the base address associated with the GPIO port */
-
-  base = lm3s_gpiobaseaddress(port);
-  DEBUGASSERT(base != 0);
-
-  /* The following requires exclusive access to the GPIO registers */
-
-  flags = irqsave();
-
-  /* Enable clocking for this GPIO peripheral. "To use the GPIO, the peripheral
-   * clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn)
-   * in the RCGC2 register."
-   */
-
-  regval = getreg32(LM3S_SYSCON_RCGC2);
-  regval |= SYSCON_RCGC2_GPIO(port);
-  putreg32(regval, LM3S_SYSCON_RCGC2);
-
-  /* First, set the port to digital input.  This is the safest state in which
-   * to perform reconfiguration.
-   */
-
-  lm3s_gpiofunc(base, pinno, &g_funcbits[0]);
-
-  /* Then set up pad strengths and pull-ups.  These setups should be done before
-   * setting up the function because some function settings will over-ride these
-   * user options.
-   */
-
-  lm3s_gpiopadstrength(base, pin, cfgset);
-  lm3s_gpiopadtype(base, pin, cfgset);
-
-  /* Then set up the real pin function */
-
-  lm3s_gpiofunc(base, pinno, &g_funcbits[func]);
-
-  /* Special GPIO digital output pins */
-
-  if (func == 1 || func == 3)
-    {
-      lm3s_initoutput(cfgset);
-    }
-
-
-  /* Special setup for interrupt GPIO pins */
-
-  else if (func == 7)
-    {
-      lm3s_interrupt(base, pin, cfgset);
-    }
-
-  irqrestore(flags);
-  return OK;
-}
-
-/****************************************************************************
- * Name: lm3s_gpiowrite
- *
- * Description:
- *   Write one or zero to the selected GPIO pin
- *
- ****************************************************************************/
-
-void lm3s_gpiowrite(uint32_t pinset, bool value)
-{
-  unsigned int port;
-  unsigned int pinno;
-  uint32_t     base;
-
-  /* Decode the basics */
-
-  port  = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  pinno = (pinset & GPIO_NUMBER_MASK);
-
-  /* Get the base address associated with the GPIO port */
-
-  base  = lm3s_gpiobaseaddress(port);
-
-  /* "The GPIO DATA register is the data register. In software control mode,
-   *  values written in the GPIO DATA register are transferred onto the GPIO
-   *  port pins if the respective pins have been configured as outputs through
-   *  the GPIO Direction (GPIO DIR) register ...
-   *
-   * "In order to write to GPIO DATA, the corresponding bits in the mask,
-   *  resulting from the address bus bits [9:2], must be High. Otherwise, the
-   *  bit values remain unchanged by the write. 
-   *
-   * "... All bits are cleared by a reset."
-   */
-
-  putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
-}
-
-/****************************************************************************
- * Name: lm3s_gpioread
- *
- * Description:
- *   Read one or zero from the selected GPIO pin
- *
- ****************************************************************************/
-
-bool lm3s_gpioread(uint32_t pinset, bool value)
-{
-  unsigned int port;
-  unsigned int pinno;
-  uint32_t     base;
-
-  /* Decode the basics */
-
-  port  = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  pinno = (pinset & GPIO_NUMBER_MASK);
-
-  /* Get the base address associated with the GPIO port */
-
-  base = lm3s_gpiobaseaddress(port);
-
-  /* "... the values read from this register are determined for each bit
-   *  by the mask bit derived from the address used to access the data register,
-   *  bits [9:2]. Bits that are 1 in the address mask cause the corresponding
-   *  bits in GPIODATA to be read, and bits that are 0 in the address mask cause
-   *  the corresponding bits in GPIO DATA to be read as 0, regardless of their
-   *  value.
-   *
-   * "A read from GPIO DATA returns the last bit value written if the respective
-   *  pins are configured as outputs, or it returns the value on the
-   *  corresponding input pin when these are configured as inputs. All bits
-   *  are cleared by a reset."
-   */
-
-  return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
-}
-
diff --git a/nuttx/arch/arm/src/lm/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm/lm3s_gpioirq.c
deleted file mode 100644
index a54bfe335..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_gpioirq.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_gpioirq.c
- * arch/arm/src/chip/lm3s_gpioirq.c
- *
- *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <string.h>
-#include <assert.h>
-#include <debug.h>
-
-#include <arch/irq.h>
-
-#include "up_arch.h"
-#include "os_internal.h"
-#include "irq_internal.h"
-
-#include "lm_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/* A table of handlers for each GPIO interrupt */
-
-static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
-
-/* A table that maps a GPIO group to a GPIO base address.  Overly complicated
- * because we support disabling interrupt support for arbitrary ports.  This
- * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h
- */
-
-static const uint32_t g_gpiobase[] =
-{
-#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
-   LM3S_GPIOA_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
-  LM3S_GPIOB_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
-  LM3S_GPIOC_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
-  LM3S_GPIOD_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
-  LM3S_GPIOE_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
-  LM3S_GPIOF_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
-  LM3S_GPIOG_BASE,
-#endif
-
-  /* NOTE: Not all LM3S architectures support GPIOs above GPIOG.  If the chip
-   * does not support these higher ports, then they must be disabled in the
-   * configuration.  Otherwise, the following will likely cause compilation
-   * errors!
-   */
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
-  LM3S_GPIOH_BASE,
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
-  LM3S_GPIOJ_BASE,
-#endif
-};
-
-#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t))
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_gpiobaseaddress
- *
- * Input:
- *   gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS.
- *
- * Description:
- *   Given a GPIO enumeration value, return the base address of the
- *   associated GPIO registers.  NOTE that range checking was provided by
- *   callee
- *
- ****************************************************************************/
-
-static uint32_t lm3s_gpiobaseaddress(unsigned int gpioirq)
-{
-  unsigned int ndx = gpioirq >> 3;
-  if (ndx < GPIO_NADDRS)
-    {
-      return g_gpiobase[ndx];
-    }
-  return 0;
-}
-
-/****************************************************************************
- * Name: lm3s_gpio*handler
- *
- * Description:
- *   Handle interrupts on each enabled GPIO port
- *
- ****************************************************************************/
-
-static int lm3s_gpiohandler(uint32_t regbase, int irqbase, void *context)
-{
-  uint32_t mis;
-  int irq;
-  int pin;
-
-  /* Handle each pending GPIO interrupt.  "The GPIO MIS register is the masked
-   * interrupt status register. Bits read High in GPIO MIS reflect the status
-   * of input lines triggering an interrupt. Bits read as Low indicate that
-   * either no interrupt has been generated, or the interrupt is masked."
-   */
-
-  mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff;
-
-  /* Clear all GPIO interrupts that we are going to process.  "The GPIO ICR
-   * register is the interrupt clear register. Writing a 1 to a bit in this
-   * register clears the corresponding interrupt edge detection logic register.
-   * Writing a 0 has no effect."
-   */
-
-  putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET);
-
-  /* Now process each IRQ pending in the MIS */
-
-  for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1)
-    {
-      if ((mis & 1) != 0)
-        {
-          irq = irqbase + pin;
-          g_gpioirqvector[irq - NR_IRQS](irq, context);
-        }
-    }
-  return OK;
-}
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
-static int lm3s_gpioahandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
-static int lm3s_gpiobhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
-static int lm3s_gpiochandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
-static int lm3s_gpiodhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
-static int lm3s_gpioehandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
-static int lm3s_gpiofhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
-static int lm3s_gpioghandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
-static int lm3s_gpiohhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
-}
-#endif
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
-static int lm3s_gpiojhandler(int irq, FAR void *context)
-{
-  return lm3s_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context);
-}
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: gpio_irqinitialize
- *
- * Description:
- *   Initialize all vectors to the unexpected interrupt handler
- *
- ****************************************************************************/
-
-int gpio_irqinitialize(void)
-{
-  int i;
-
-  /* Point all interrupt vectors to the unexpected interrupt */
-
-  for (i = 0; i < NR_GPIO_IRQS; i++)
-    {
-      g_gpioirqvector[i] = irq_unexpected_isr;
-    }
-
-  /* Then attach each GPIO interrupt handlers and enable corresponding GPIO
-   * interrupts
-   */
-
-#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
-  irq_attach(LM3S_IRQ_GPIOA, lm3s_gpioahandler);
-  up_enable_irq(LM3S_IRQ_GPIOA);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
-  irq_attach(LM3S_IRQ_GPIOB, lm3s_gpiobhandler);
-  up_enable_irq(LM3S_IRQ_GPIOB);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
-  irq_attach(LM3S_IRQ_GPIOC, lm3s_gpiochandler);
-  up_enable_irq(LM3S_IRQ_GPIOC);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
-  irq_attach(LM3S_IRQ_GPIOD, lm3s_gpiodhandler);
-  up_enable_irq(LM3S_IRQ_GPIOD);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
-  irq_attach(LM3S_IRQ_GPIOE, lm3s_gpioehandler);
-  up_enable_irq(LM3S_IRQ_GPIOE);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
-  irq_attach(LM3S_IRQ_GPIOF, lm3s_gpiofhandler);
-  up_enable_irq(LM3S_IRQ_GPIOF);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
-  irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler);
-  up_enable_irq(LM3S_IRQ_GPIOG);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
-  irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler);
-  up_enable_irq(LM3S_IRQ_GPIOH);
-#endif
-#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS
-  irq_attach(LM3S_IRQ_GPIOJ, lm3s_gpiojhandler);
-  up_enable_irq(LM3S_IRQ_GPIOJ);
-#endif
-
-  return OK;
-}
-
-/****************************************************************************
- * Name: gpio_irqattach
- *
- * Description:
- *   Attach in GPIO interrupt to the provide 'isr'
- *
- ****************************************************************************/
-
-int gpio_irqattach(int irq, xcpt_t isr)
-{
-  irqstate_t flags;
-  int        gpioirq = irq - NR_IRQS;
-  int        ret     = ERROR;
-
-  if ((unsigned)gpioirq < NR_GPIO_IRQS)
-    {
-      flags = irqsave();
-
-      /* If the new ISR is NULL, then the ISR is being detached.
-       * In this case, disable the ISR and direct any interrupts
-       * to the unexpected interrupt handler.
-       */
-
-      if (isr == NULL)
-        {
-#ifndef CONFIG_ARCH_NOINTC
-           gpio_irqdisable(gpioirq);
-#endif
-           isr = irq_unexpected_isr;
-        }
-
-      /* Save the new ISR in the table. */
-
-      g_irqvector[gpioirq] = isr;
-      irqrestore(flags);
-      ret = OK;
-    }
-  return ret;
-}
-
-/****************************************************************************
- * Name: gpio_irqenable
- *
- * Description:
- *   Enable the GPIO IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void gpio_irqenable(int irq)
-{
-  irqstate_t flags;
-  int        gpioirq = irq - NR_IRQS;
-  uint32_t   base;
-  uint32_t   regval;
-  int        pin;
-
-  if ((unsigned)gpioirq < NR_GPIO_IRQS)
-    {
-      /* Get the base address of the GPIO module associated with this IRQ */
-
-      base = lm3s_gpiobaseaddress(gpioirq);
-      DEBUGASSERT(base != 0);
-      pin  = (1 << (gpioirq & 7));
-
-      /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
-       * mask register. Bits set to High in GPIO IM allow the corresponding
-       * pins to trigger their individual interrupts and the combined GPIO INTR
-       * line. Clearing a bit disables interrupt triggering on that pin. All
-       * bits are cleared by a reset.
-       */
-
-      flags   = irqsave();
-      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
-      regval |= pin;
-      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
-      irqrestore(flags);
-    }
-}
-
-/****************************************************************************
- * Name: gpio_irqdisable
- *
- * Description:
- *   Disable the GPIO IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void gpio_irqdisable(int irq)
-{
-  irqstate_t flags;
-  int        gpioirq = irq - NR_IRQS;
-  uint32_t   base;
-  uint32_t   regval;
-  int        pin;
-
-  if ((unsigned)gpioirq < NR_GPIO_IRQS)
-    {
-      /* Get the base address of the GPIO module associated with this IRQ */
-
-      base = lm3s_gpiobaseaddress(gpioirq);
-      DEBUGASSERT(base != 0);
-      pin  = (1 << (gpioirq & 7));
-
-      /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
-       * mask register. Bits set to High in GPIO IM allow the corresponding
-       * pins to trigger their individual interrupts and the combined GPIO INTR
-       * line. Clearing a bit disables interrupt triggering on that pin. All
-       * bits are cleared by a reset.
-       */
-
-      flags   = irqsave();
-      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
-      regval &= ~pin;
-      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
-      irqrestore(flags);
-    }
-}
-
diff --git a/nuttx/arch/arm/src/lm/lm3s_irq.c b/nuttx/arch/arm/src/lm/lm3s_irq.c
deleted file mode 100644
index 2039d84a8..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_irq.c
+++ /dev/null
@@ -1,458 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_irq.c
- * arch/arm/src/chip/lm3s_irq.c
- *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <debug.h>
-
-#include <nuttx/irq.h>
-#include <nuttx/arch.h>
-#include <arch/irq.h>
-
-#include "nvic.h"
-#include "up_arch.h"
-#include "os_internal.h"
-#include "up_internal.h"
-
-#include "chip.h"
-#include "lm_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Enable NVIC debug features that are probably only desireable during
- * bringup
- */
-
-#undef LM3S_IRQ_DEBUG
-
-/* Get a 32-bit version of the default priority */
-
-#define DEFPRIORITY32 \
-  (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
-   NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
-   NVIC_SYSH_PRIORITY_DEFAULT << 8  |\
-   NVIC_SYSH_PRIORITY_DEFAULT)
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-volatile uint32_t *current_regs;
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_dumpnvic
- *
- * Description:
- *   Dump some interesting NVIC registers
- *
- ****************************************************************************/
-
-#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
-static void lm3s_dumpnvic(const char *msg, int irq)
-{
-  irqstate_t flags;
-
-  flags = irqsave();
-  slldbg("NVIC (%s, irq=%d):\n", msg, irq);
-  slldbg("  INTCTRL:    %08x VECTAB: %08x\n",
-         getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
-#if 0
-  slldbg("  SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
-         getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
-         getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
-#endif
-  slldbg("  IRQ ENABLE: %08x %08x\n",
-         getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
-  slldbg("  SYSH_PRIO:  %08x %08x %08x\n",
-         getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
-         getreg32(NVIC_SYSH12_15_PRIORITY));
-  slldbg("  IRQ PRIO:   %08x %08x %08x %08x\n", 
-        getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
-        getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
-  slldbg("              %08x %08x %08x %08x\n", 
-        getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
-        getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
-  slldbg("              %08x %08x %08x %08x\n", 
-        getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
-        getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
-  irqrestore(flags);
-}
-#else
-#  define lm3s_dumpnvic(msg, irq)
-#endif
-
-/****************************************************************************
- * Name: lm3s_nmi, lm3s_busfault, lm3s_usagefault, lm3s_pendsv,
- *       lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved
- *
- * Description:
- *   Handlers for various execptions.  None are handled and all are fatal
- *   error conditions.  The only advantage these provided over the default
- *   unexpected interrupt handler is that they provide a diagnostic output.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_DEBUG
-static int lm3s_nmi(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! NMI received\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_busfault(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! Bus fault recived\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_usagefault(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! Usage fault received\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_pendsv(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! PendSV received\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_dbgmonitor(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! Debug Monitor receieved\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-
-static int lm3s_reserved(int irq, FAR void *context)
-{
-  (void)irqsave();
-  dbg("PANIC!!! Reserved interrupt\n");
-  PANIC(OSERR_UNEXPECTEDISR);
-  return 0;
-}
-#endif
-
-/****************************************************************************
- * Name: lm3s_irqinfo
- *
- * Description:
- *   Given an IRQ number, provide the register and bit setting to enable or
- *   disable the irq.
- *
- ****************************************************************************/
-
-static int lm3s_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
-{
-  DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS);
-
-  /* Check for external interrupt */
-
-  if (irq >= LM3S_IRQ_INTERRUPTS)
-    {
-      if (irq < LM3S_IRQ_INTERRUPTS + 32)
-        {
-           *regaddr = NVIC_IRQ0_31_ENABLE;
-           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS);
-        }
-      else if (irq < NR_IRQS)
-        {
-           *regaddr = NVIC_IRQ32_63_ENABLE;
-           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
-        }
-      else
-        {
-          return ERROR; /* Invalid interrupt */
-        }
-    }
-
-  /* Handler processor exceptions.  Only a few can be disabled */
-
-  else
-    {
-       *regaddr = NVIC_SYSHCON;
-       if (irq == LM3S_IRQ_MEMFAULT)
-        {
-          *bit = NVIC_SYSHCON_MEMFAULTENA;
-        }
-      else if (irq == LM3S_IRQ_BUSFAULT)
-        {
-          *bit = NVIC_SYSHCON_BUSFAULTENA;
-        }
-      else if (irq == LM3S_IRQ_USAGEFAULT)
-        {
-          *bit = NVIC_SYSHCON_USGFAULTENA;
-        }
-      else if (irq == LM3S_IRQ_SYSTICK)
-        {
-          *regaddr = NVIC_SYSTICK_CTRL;
-          *bit = NVIC_SYSTICK_CTRL_ENABLE;
-        }
-      else
-        {
-          return ERROR; /* Invalid or unsupported exception */
-        }
-    }
-
-  return OK;
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_irqinitialize
- ****************************************************************************/
-
-void up_irqinitialize(void)
-{
-  /* Disable all interrupts */
-
-  putreg32(0, NVIC_IRQ0_31_ENABLE);
-  putreg32(0, NVIC_IRQ32_63_ENABLE);
-
-  /* Set all interrrupts (and exceptions) to the default priority */
-
-  putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
-
-  putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
-  putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
-
-  /* currents_regs is non-NULL only while processing an interrupt */
-
-  current_regs = NULL;
-
-  /* Initialize support for GPIO interrupts if included in this build */
-
-#ifndef CONFIG_LM3S_DISABLE_GPIO_IRQS
-#ifdef CONFIG_HAVE_WEAKFUNCTIONS
-  if (gpio_irqinitialize != NULL)
-#endif
-    {
-      gpio_irqinitialize();
-    }
-#endif
-
-  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
-   * exception is used for performing context switches; The Hard Fault
-   * must also be caught because a SVCall may show up as a Hard Fault
-   * under certain conditions.
-   */
-
-  irq_attach(LM3S_IRQ_SVCALL, up_svcall);
-  irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault);
-
-  /* Set the priority of the SVCall interrupt */
-
-#ifdef CONFIG_ARCH_IRQPRIO
-/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
-#endif
-
-  /* If the MPU is enabled, then attach and enable the Memory Management
-   * Fault handler.
-   */
-
-#ifdef CONFIG_ARMV7M_MPU
-  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
-  up_enable_irq(LM3S_IRQ_MEMFAULT);
-#endif
-
-  /* Attach all other processor exceptions (except reset and sys tick) */
-
-#ifdef CONFIG_DEBUG
-  irq_attach(LM3S_IRQ_NMI, lm3s_nmi);
-#ifndef CONFIG_ARMV7M_MPU
-  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
-#endif
-  irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault);
-  irq_attach(LM3S_IRQ_USAGEFAULT, lm3s_usagefault);
-  irq_attach(LM3S_IRQ_PENDSV, lm3s_pendsv);
-  irq_attach(LM3S_IRQ_DBGMONITOR, lm3s_dbgmonitor);
-  irq_attach(LM3S_IRQ_RESERVED, lm3s_reserved);
-#endif
-
-  lm3s_dumpnvic("initial", NR_IRQS);
-
-#ifndef CONFIG_SUPPRESS_INTERRUPTS
-
-  /* And finally, enable interrupts */
-
-  setbasepri(NVIC_SYSH_PRIORITY_MAX);
-  irqrestore(0);
-#endif
-}
-
-/****************************************************************************
- * Name: up_disable_irq
- *
- * Description:
- *   Disable the IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void up_disable_irq(int irq)
-{
-  uint32_t regaddr;
-  uint32_t regval;
-  uint32_t bit;
-
-  if (lm3s_irqinfo(irq, &regaddr, &bit) == 0)
-    {
-      /* Clear the appropriate bit in the register to enable the interrupt */
-
-      regval  = getreg32(regaddr);
-      regval &= ~bit;
-      putreg32(regval, regaddr);
-    }
-  lm3s_dumpnvic("disable", irq);
-}
-
-/****************************************************************************
- * Name: up_enable_irq
- *
- * Description:
- *   Enable the IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void up_enable_irq(int irq)
-{
-  uint32_t regaddr;
-  uint32_t regval;
-  uint32_t bit;
-
-  if (lm3s_irqinfo(irq, &regaddr, &bit) == 0)
-    {
-      /* Set the appropriate bit in the register to enable the interrupt */
-
-      regval  = getreg32(regaddr);
-      regval |= bit;
-      putreg32(regval, regaddr);
-    }
-  lm3s_dumpnvic("enable", irq);
-}
-
-/****************************************************************************
- * Name: up_maskack_irq
- *
- * Description:
- *   Mask the IRQ and acknowledge it
- *
- ****************************************************************************/
-
-void up_maskack_irq(int irq)
-{
-  up_disable_irq(irq);
-}
-
-/****************************************************************************
- * Name: up_prioritize_irq
- *
- * Description:
- *   Set the priority of an IRQ.
- *
- *   Since this API is not supported on all architectures, it should be
- *   avoided in common implementations where possible.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_IRQPRIO
-int up_prioritize_irq(int irq, int priority)
-{
-  uint32_t regaddr;
-  uint32_t regval;
-  int shift;
-
-  DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
-
-  if (irq < LM3S_IRQ_INTERRUPTS)
-    {
-      irq    -= 4;
-      regaddr = NVIC_SYSH_PRIORITY(irq);
-    }
-  else
-    {
-      irq    -= LM3S_IRQ_INTERRUPTS;
-      regaddr = NVIC_IRQ_PRIORITY(irq);
-    }
-
-  regval      = getreg32(regaddr);
-  shift       = ((irq & 3) << 3);
-  regval     &= ~(0xff << shift);
-  regval     |= (priority << shift);
-  putreg32(regval, regaddr);
-
-  lm3s_dumpnvic("prioritize", irq);
-  return OK;
-}
-#endif
diff --git a/nuttx/arch/arm/src/lm/lm3s_lowputc.c b/nuttx/arch/arm/src/lm/lm3s_lowputc.c
deleted file mode 100644
index 7f9a826c8..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_lowputc.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/**************************************************************************
- * arch/arm/src/lm/lm3s_lowputc.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- **************************************************************************/
-
-/**************************************************************************
- * Included Files
- **************************************************************************/
-
-#include <nuttx/config.h>
-#include <stdint.h>
-
-#include <arch/board/board.h>
-
-#include "chip.h"
-#include "up_arch.h"
-#include "up_internal.h"
-
-#include "lm_gpio.h"
-#include "chip/lm_pinmap.h"
-
-#include "lm_lowputc.h"
-
-/**************************************************************************
- * Pre-processor Definitions
- **************************************************************************/
-
-/* Configuration **********************************************************/
-
-#if LM3S_NUARTS < 2
-#  undef  CONFIG_LM3S_UART1
-#  undef  CONFIG_UART1_SERIAL_CONSOLE
-#endif
-
-#if LM3S_NUARTS < 3
-#  undef  CONFIG_LM3S_UART2
-#  undef  CONFIG_UART2_SERIAL_CONSOLE
-#endif
-
-/* Is there a serial console? */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0)
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1)
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2)
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#else
-#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  undef HAVE_CONSOLE
-#endif
-
-/* Select UART parameters for the selected console */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART0_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART0_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART0_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART0_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART0_2STOP
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART1_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART1_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART1_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART1_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART1_2STOP
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART2_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART2_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART2_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART2_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART2_2STOP
-#else
-#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
-#endif
-
-/* Get LCRH settings */
-
-#if LM3S_CONSOLE_BITS == 5
-#  define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
-#elif LM3S_CONSOLE_BITS == 6
-#  define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
-#elif LM3S_CONSOLE_BITS == 7
-#  define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
-#elif LM3S_CONSOLE_BITS == 8
-#  define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
-#else
-#  error "Number of bits not supported"
-#endif
-
-#if LM3S_CONSOLE_PARITY == 0
-#  define UART_LCRH_PARITY (0)
-#elif LM3S_CONSOLE_PARITY == 1
-#  define UART_LCRH_PARITY UART_LCRH_PEN
-#elif LM3S_CONSOLE_PARITY == 2
-#  define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
-#else
-#  error "Invalid parity selection"
-#endif
-
-#if LM3S_CONSOLE_2STOP != 0
-#  define UART_LCRH_NSTOP UART_LCRH_STP2
-#else
-#  define UART_LCRH_NSTOP (0)
-#endif
-
-#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN)
-
-/* Calculate BAUD rate from the SYS clock:
- *
- * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit
- *  fractional part. The number formed by these two values is used by the baud-rate generator
- *  to determine the bit period. Having a fractional baud-rate divider allows the UART to
- *  generate all the standard baud rates.
- *
- * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD)
- *  register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
- *  Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship
- *  to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional
- *  part, separated by a decimal place.):
- *
- *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
- *
- * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number
- *  (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated
- *  by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5
- *  to account for rounding errors:
- *
- *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
- *
- * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred
- *  to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is
- *  used for error detection during receive operations.
- *
- * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and
- *  UARTFBRD registers form an internal 30-bit register. This internal register is only
- *  updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
- *  divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
- */
-
-#define LM3S_BRDDEN     (16 * LM3S_CONSOLE_BAUD)
-#define LM3S_BRDI       (SYSCLK_FREQUENCY / LM3S_BRDDEN)
-#define LM3S_REMAINDER  (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
-#define LM3S_DIVFRAC    ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
-
-/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
- *
- * LM3S_BRDDEN    = (16 * 115,200)                           = 1,843,200
- * LM3S_BRDI      = 50,000,000 / 1,843,200                   = 27
- * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27              = 233,600
- * LM3S_DIVFRAC   = (233,600 * 64 + 921,600) / 1,843,200     = 8
- *
- * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
- */
-
-/**************************************************************************
- * Private Types
- **************************************************************************/
-
-/**************************************************************************
- * Private Function Prototypes
- **************************************************************************/
-
-/**************************************************************************
- * Global Variables
- **************************************************************************/
-
-/**************************************************************************
- * Private Variables
- **************************************************************************/
-
-/**************************************************************************
- * Private Functions
- **************************************************************************/
-
-/**************************************************************************
- * Public Functions
- **************************************************************************/
-
-/**************************************************************************
- * Name: up_lowputc
- *
- * Description:
- *   Output one byte on the serial console
- *
- **************************************************************************/
-
-void up_lowputc(char ch)
-{
-#ifdef HAVE_CONSOLE
-  /* Wait until the TX FIFO is not full */
-
-  while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
-
-  /* Then send the character */
-
-  putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET);
-#endif
-}
-
-/**************************************************************************
- * Name: up_lowsetup
- *
- * Description:
- *   This performs basic initialization of the UART used for the serial
- *   console.  Its purpose is to get the console output availabe as soon
- *   as possible.
- *
- **************************************************************************/
-
-void up_lowsetup(void)
-{
-  uint32_t regval;
-#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
-  uint32_t ctl;
-#endif
-
-  /* Enable the selected UARTs and configure GPIO pins to need by the
-   * the selected UARTs.  NOTE: The serial driver later depends on
-   * this pin configuration -- whether or not a serial console is selected.
-   */
-
-#ifdef CONFIG_LM3S_UART0
-  regval  = getreg32(LM3S_SYSCON_RCGC1);
-  regval |= SYSCON_RCGC1_UART0;
-  putreg32(regval, LM3S_SYSCON_RCGC1);
-
-  lm3s_configgpio(GPIO_UART0_RX);
-  lm3s_configgpio(GPIO_UART0_TX);
-#endif
-
-#ifdef CONFIG_LM3S_UART1
-  regval  = getreg32(LM3S_SYSCON_RCGC1);
-  regval |= SYSCON_RCGC1_UART1;
-  putreg32(regval, LM3S_SYSCON_RCGC1);
-
-  lm3s_configgpio(GPIO_UART1_RX);
-  lm3s_configgpio(GPIO_UART1_TX);
-#endif
-
-  /* Enable the selected console device */
-
-#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
-  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
-
-  ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
-  ctl &= ~UART_CTL_UARTEN;
-  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
-
-  /* Write the integer portion of the BRD to the UART IBRD register */
-
-  putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
-
-  /* Write the fractional portion of the BRD to the UART FBRD register */
-
-  putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
-
-  /* Write the desired serial parameters to the UART LCRH register */
-
-  putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
-
-  /* Enable the UART by setting the UARTEN bit in the UART CTL register */
-
-  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
-  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
-#endif
-
-}
-
-
diff --git a/nuttx/arch/arm/src/lm/lm3s_serial.c b/nuttx/arch/arm/src/lm/lm3s_serial.c
deleted file mode 100644
index 79628c765..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_serial.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_serial.c
- *
- *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include <unistd.h>
-#include <semaphore.h>
-#include <string.h>
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/irq.h>
-#include <nuttx/arch.h>
-#include <nuttx/serial/serial.h>
-
-#include <arch/serial.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
-#include "up_arch.h"
-#include "up_internal.h"
-#include "os_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Some sanity checks *******************************************************/
-
-#if LM3S_NUARTS < 2
-#  undef  CONFIG_LM3S_UART1
-#  undef  CONFIG_UART1_SERIAL_CONSOLE
-#endif
-
-#if LM3S_NUARTS < 3
-#  undef  CONFIG_LM3S_UART2
-#  undef  CONFIG_UART2_SERIAL_CONSOLE
-#endif
-
-/* Is there a UART enabled? */
-
-#if !defined(CONFIG_LM3S_UART0) && !defined(CONFIG_LM3S_UART1) && !defined(CONFIG_LM3S_UART2)
-#  error "No UARTs enabled"
-#endif
-
-/* Is there a serial console? */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0)
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1)
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2)
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
-#else
-#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
-#  undef CONFIG_UART0_SERIAL_CONSOLE
-#  undef CONFIG_UART1_SERIAL_CONSOLE
-#  undef CONFIG_UART2_SERIAL_CONSOLE
-#  undef HAVE_CONSOLE
-#endif
-
-/* If we are not using the serial driver for the console, then we
- * still must provide some minimal implementation of up_putc.
- */
-
-#ifdef USE_SERIALDRIVER
-
-/* Which UART with be tty0/console and which tty1? */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE)
-#  define CONSOLE_DEV     g_uart0port     /* UART0 is console */
-#  define TTYS0_DEV       g_uart0port     /* UART0 is ttyS0 */
-#  ifdef CONFIG_LM3S_UART1
-#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
-#    else
-#      undef TTYS2_DEV                    /* No ttyS2 */
-#    endif
-#  else
-#    undef TTYS2_DEV                      /* No ttyS2 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
-#    else
-#      undef TTYS1_DEV                    /* No ttyS1 */
-#    endif
-#  endif
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
-#  define CONSOLE_DEV     g_uart1port     /* UART1 is console */
-#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
-#  ifdef CONFIG_LM3S_UART0
-#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
-#    else
-#      undef TTYS2_DEV                    /* No ttyS2 */
-#    endif
-#  else
-#    undef TTYS2_DEV                      /* No ttyS2 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
-#    else
-#      undef TTYS1_DEV                    /* No ttyS1 */
-#    endif
-#  endif
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
-#  define CONSOLE_DEV     g_uart2port     /* UART2 is console */
-#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
-#  ifdef CONFIG_LM3S_UART0
-#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
-#    else
-#      undef TTYS2_DEV                    /* No ttyS2 */
-#    endif
-#  else
-#    undef TTYS2_DEV                      /* No ttyS2 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
-#    else
-#      undef TTYS1_DEV                    /* No ttyS1 */
-#    endif
-#  endif
-#elifdefined(CONFIG_LM3S_UART0)
-#  undef  CONSOLE_DEV                     /* No console device */
-#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
-#  ifdef CONFIG_LM3S_UART1
-#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
-#    else
-#      undef TTYS2_DEV                    /* No ttyS2 */
-#    endif
-#  else
-#    undef TTYS2_DEV                      /* No ttyS2 */
-#    ifdef CONFIG_LM3S_UART2
-#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
-#    else
-#      undef TTYS1_DEV                    /* No ttyS1 */
-#    endif
-#  endif
-#elifdefined(CONFIG_LM3S_UART1)
-#  undef  CONSOLE_DEV                     /* No console device */
-#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
-#  undef TTYS2_DEV                        /* No ttyS2 */
-#  ifdef CONFIG_LM3S_UART2
-#    define TTYS1_DEV     g_uart2port     /* UART2 is ttyS1 */
-#  else
-#    undef TTYS1_DEV                      /* No ttyS1 */
-#  endif
-#elifdefined(CONFIG_LM3S_UART2)
-#  undef  CONSOLE_DEV                     /* No console device */
-#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
-#  undef  TTYS1_DEV                       /* No ttyS1 */
-#  undef  TTYS2_DEV                       /* No ttyS2 */
-#else
-#  error "No valid TTY devices"
-#  undef  CONSOLE_DEV                     /* No console device */
-#  undef  TTYS0_DEV                       /* No ttyS0 */
-#  undef  TTYS1_DEV                       /* No ttyS1 */
-#  undef  TTYS2_DEV                       /* No ttyS2 */
-#endif
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-struct up_dev_s
-{
-  uint32_t uartbase; /* Base address of UART registers */
-  uint32_t baud;     /* Configured baud */
-  uint32_t im;       /* Saved IM value */
-  uint8_t  irq;      /* IRQ associated with this UART */
-  uint8_t  parity;   /* 0=none, 1=odd, 2=even */
-  uint8_t  bits;     /* Number of bits (7 or 8) */
-  bool    stopbits2; /* true: Configure with 2 stop bits instead of 1 */
-};
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-static int  up_setup(struct uart_dev_s *dev);
-static void up_shutdown(struct uart_dev_s *dev);
-static int  up_attach(struct uart_dev_s *dev);
-static void up_detach(struct uart_dev_s *dev);
-static int  up_interrupt(int irq, void *context);
-static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
-static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
-static void up_rxint(struct uart_dev_s *dev, bool enable);
-static bool up_rxavailable(struct uart_dev_s *dev);
-static void up_send(struct uart_dev_s *dev, int ch);
-static void up_txint(struct uart_dev_s *dev, bool enable);
-static bool up_txready(struct uart_dev_s *dev);
-static bool up_txempty(struct uart_dev_s *dev);
-
-/****************************************************************************
- * Private Variables
- ****************************************************************************/
-
-struct uart_ops_s g_uart_ops =
-{
-  .setup          = up_setup,
-  .shutdown       = up_shutdown,
-  .attach         = up_attach,
-  .detach         = up_detach,
-  .ioctl          = up_ioctl,
-  .receive        = up_receive,
-  .rxint          = up_rxint,
-  .rxavailable    = up_rxavailable,
-  .send           = up_send,
-  .txint          = up_txint,
-  .txready        = up_txready,
-  .txempty        = up_txempty,
-};
-
-/* I/O buffers */
-
-#ifdef CONFIG_LM3S_UART0
-static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
-static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
-#endif
-#ifdef CONFIG_LM3S_UART1
-static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
-static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
-#endif
-#ifdef CONFIG_LM3S_UART2
-static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
-static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
-#endif
-
-/* This describes the state of the LM3S uart0 port. */
-
-#ifdef CONFIG_LM3S_UART0
-static struct up_dev_s g_uart0priv =
-{
-  .uartbase       = LM3S_UART0_BASE,
-  .baud           = CONFIG_UART0_BAUD,
-  .irq            = LM3S_IRQ_UART0,
-  .parity         = CONFIG_UART0_PARITY,
-  .bits           = CONFIG_UART0_BITS,
-  .stopbits2      = CONFIG_UART0_2STOP,
-};
-
-static uart_dev_t g_uart0port =
-{
-  .recv     =
-  {
-    .size   = CONFIG_UART0_RXBUFSIZE,
-    .buffer = g_uart0rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART0_TXBUFSIZE,
-    .buffer = g_uart0txbuffer,
-  },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart0priv,
-};
-#endif
-
-/* This describes the state of the LM3S uart1 port. */
-
-#ifdef CONFIG_LM3S_UART1
-static struct up_dev_s g_uart1priv =
-{
-  .uartbase       = LM3S_UART1_BASE,
-  .baud           = CONFIG_UART1_BAUD,
-  .irq            = LM3S_IRQ_UART1,
-  .parity         = CONFIG_UART1_PARITY,
-  .bits           = CONFIG_UART1_BITS,
-  .stopbits2      = CONFIG_UART1_2STOP,
-};
-
-static uart_dev_t g_uart1port =
-{
-  .recv     =
-  {
-    .size   = CONFIG_UART1_RXBUFSIZE,
-    .buffer = g_uart1rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART1_TXBUFSIZE,
-    .buffer = g_uart1txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart1priv,
-};
-#endif
-
-/* This describes the state of the LM3S uart1 port. */
-
-#ifdef CONFIG_LM3S_UART2
-static struct up_dev_s g_uart2priv =
-{
-  .uartbase       = LM3S_UART2_BASE,
-  .baud           = CONFIG_UART2_BAUD,
-  .irq            = LM3S_IRQ_UART2,
-  .parity         = CONFIG_UART2_PARITY,
-  .bits           = CONFIG_UART2_BITS,
-  .stopbits2      = CONFIG_UART2_2STOP,
-};
-
-static uart_dev_t g_uart2port =
-{
-  .recv     =
-  {
-    .size   = CONFIG_UART2_RXBUFSIZE,
-    .buffer = g_uart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART2_TXBUFSIZE,
-    .buffer = g_uart2txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart2priv,
-};
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_serialin
- ****************************************************************************/
-
-static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
-{
-  return getreg32(priv->uartbase + offset);
-}
-
-/****************************************************************************
- * Name: up_serialout
- ****************************************************************************/
-
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
-{
-  putreg32(value, priv->uartbase + offset);
-}
-
-/****************************************************************************
- * Name: up_disableuartint
- ****************************************************************************/
-
-static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
-{
-  /* Return the current interrupt mask value */
-
-  if (im)
-    {
-      *im = priv->im;
-    }
-
-  /* Disable all interrupts */
-
-  priv->im = 0;
-  up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
-}
-
-/****************************************************************************
- * Name: up_restoreuartint
- ****************************************************************************/
-
-static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
-{
-  priv->im = im;
-  up_serialout(priv, LM3S_UART_IM_OFFSET, im);
-}
-
-/****************************************************************************
- * Name: up_waittxnotfull
- ****************************************************************************/
-
-#ifdef HAVE_CONSOLE
-static inline void up_waittxnotfull(struct up_dev_s *priv)
-{
-  int tmp;
-
-  /* Limit how long we will wait for the TX available condition */
-
-  for (tmp = 1000 ; tmp > 0 ; tmp--)
-    {
-      /* Check Tx FIFO is full */
-
-      if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
-        {
-          /* The Tx FIFO is not full... return */
-
-          break;
-        }
-    }
-
-  /* If we get here, then the wait has timed out and the Tx FIFO remains
-   * full.
-   */
-}
-#endif
-
-/****************************************************************************
- * Name: up_setup
- *
- * Description:
- *   Configure the UART baud, bits, parity, fifos, etc. This
- *   method is called the first time that the serial port is
- *   opened.
- *
- ****************************************************************************/
-
-static int up_setup(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  uint32_t lcrh;
-  uint32_t ctl;
-#ifndef CONFIG_SUPPRESS_UART_CONFIG
-  uint32_t den;
-  uint32_t brdi;
-  uint32_t remainder;
-  uint32_t divfrac;
-
-  /* Note:  The logic here depends on the fact that that the UART module
-   * was enabled and the GPIOs were configured in up_lowsetup().
-   */
-
-  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
-
-  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
-  ctl &= ~UART_CTL_UARTEN;
-  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
-
-  /* Calculate BAUD rate from the SYS clock:
-   *
-   * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer
-   *  and a 6-bit fractional part. The number formed by these two values is
-   *  used by the baud-rate generator to determine the bit period. Having a
-   *  fractional baud-rate divider allows the UART to generate all the standard
-   *  baud rates.
-   *
-   * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor
-   *  (UARTIBRD) register ... and the 6-bit fractional part is loaded with the
-   *  UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate
-   *  divisor (BRD) has the following relationship to the system clock (where
-   *  BRDI is the integer part of the BRD and BRDF is the fractional part,
-   *  separated by a decimal place.):
-   *
-   *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
-   *
-   * "where UARTSysClk is the system clock connected to the UART. The 6-bit
-   *  fractional number (that is to be loaded into the DIVFRAC bit field in the
-   *  UARTFBRD register) can be calculated by taking the fractional part of the
-   *  baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
-   *  rounding errors:
-   *
-   *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
-   *
-   * "The UART generates an internal baud-rate reference clock at 16x the baud-
-   *  rate (referred to as Baud16). This reference clock is divided by 16 to
-   *  generate the transmit clock, and is used for error detection during receive
-   *  operations.
-   *
-   * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the
-   *  UARTIBRD and UARTFBRD registers form an internal 30-bit register. This
-   *  internal register is only updated when a write operation to UARTLCRH is
-   *  performed, so any changes to the baud-rate divisor must be followed by a
-   *  write to the UARTLCRH register for the changes to take effect. ..."
-   */
-
-  den       = priv->baud << 4;
-  brdi      = SYSCLK_FREQUENCY / den;
-  remainder = SYSCLK_FREQUENCY - den * brdi;
-  divfrac   = ((remainder << 6) + (den >> 1)) / den;
-
-  up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
-  up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
-
-  /* Set up the LCRH register */
-
-  lcrh = 0;
-  switch (priv->bits)
-    {
-      case 5:
-        lcrh |= UART_LCRH_WLEN_5BITS;
-        break;
-      case 6:
-        lcrh |= UART_LCRH_WLEN_6BITS;
-        break;
-      case 7:
-        lcrh |= UART_LCRH_WLEN_7BITS;
-        break;
-      case 8:
-      default:
-        lcrh |= UART_LCRH_WLEN_8BITS;
-        break;
-    }
-
-  switch (priv->parity)
-    {
-      case 0:
-      default:
-        break;
-      case 1:
-        lcrh |= UART_LCRH_PEN;
-        break;
-      case 2:
-        lcrh |= UART_LCRH_PEN|UART_LCRH_EPS;
-        break;
-    }
-
-  if (priv->stopbits2)
-    {
-      lcrh |= UART_LCRH_STP2;
-    }
-
-  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
-#endif
-
-  /* Set the UART to interrupt whenever the TX FIFO is almost empty or when
-   * any character is received.
-   */
-
-  up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
-
-  /* Flush the Rx and Tx FIFOs -- How do you do that?*/
-
-  /* Enable Rx interrupts from the UART except for Tx interrupts.  We don't want
-   * Tx interrupts until we have something to send.  We will check for serial
-   * errors as part of Rx interrupt processing (no interrupts will be received
-   * yet because the interrupt is still disabled at the interrupt controller.
-   */
-
-  up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
-
-  /* Enable the FIFOs */
-
-#ifdef CONFIG_SUPPRESS_UART_CONFIG
-  lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
-#endif
-  lcrh |= UART_LCRH_FEN;
-  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
-
-  /* Enable Rx, Tx, and the UART */
-
-#ifdef CONFIG_SUPPRESS_UART_CONFIG
-  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
-#endif
-  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
-  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
-
-  /* Set up the cache IM value */
-
-  priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
-  return OK;
-}
-
-/****************************************************************************
- * Name: up_shutdown
- *
- * Description:
- *   Disable the UART.  This method is called when the serial
- *   port is closed
- *
- ****************************************************************************/
-
-static void up_shutdown(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_disableuartint(priv, NULL);
-}
-
-/****************************************************************************
- * Name: up_attach
- *
- * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
- *   the setup() method is called, however, the serial console may operate in
- *   a non-interrupt driven mode during the boot phase.
- *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
- *
- ****************************************************************************/
-
-static int up_attach(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  int ret;
-
-  /* Attach and enable the IRQ */
-
-  ret = irq_attach(priv->irq, up_interrupt);
-  if (ret == OK)
-    {
-       /* Enable the interrupt (RX and TX interrupts are still disabled
-        * in the UART
-        */
-
-       up_enable_irq(priv->irq);
-    }
-  return ret;
-}
-
-/****************************************************************************
- * Name: up_detach
- *
- * Description:
- *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception is
- *   the serial console which is never shutdown.
- *
- ****************************************************************************/
-
-static void up_detach(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_disable_irq(priv->irq);
-  irq_detach(priv->irq);
-}
-
-/****************************************************************************
- * Name: up_interrupt
- *
- * Description:
- *   This is the UART interrupt handler.  It will be invoked
- *   when an interrupt received on the 'irq'  It should call
- *   uart_transmitchars or uart_receivechar to perform the
- *   appropriate data transfers.  The interrupt handling logic\
- *   must be able to map the 'irq' number into the approprite
- *   uart_dev_s structure in order to call these functions.
- *
- ****************************************************************************/
-
-static int up_interrupt(int irq, void *context)
-{
-  struct uart_dev_s *dev = NULL;
-  struct up_dev_s   *priv;
-  uint32_t           mis;
-  int                passes;
-  bool               handled;
-
-#ifdef CONFIG_LM3S_UART0
-  if (g_uart0priv.irq == irq)
-    {
-      dev = &g_uart0port;
-    }
-  else
-#endif
-#ifdef CONFIG_LM3S_UART1
-  if (g_uart1priv.irq == irq)
-    {
-      dev = &g_uart1port;
-    }
-  else
-#endif
-    {
-      PANIC(OSERR_INTERNAL);
-    }
-  priv = (struct up_dev_s*)dev->priv;
-
-  /* Loop until there are no characters to be transferred or,
-   * until we have been looping for a long time.
-   */
-
-  handled = true;
-  for (passes = 0; passes < 256 && handled; passes++)
-    {
-      handled = false;
-
-      /* Get the masked UART status and clear the pending interrupts. */
-
-       mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
-       up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
-
-      /* Handle incoming, receive bytes (with or without timeout) */
-
-      if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0)
-        {
-           /* Rx buffer not empty ... process incoming bytes */
-
-           uart_recvchars(dev);
-           handled = true;
-        }
-
-      /* Handle outgoing, transmit bytes */
-
-      if ((mis & UART_MIS_TXMIS) != 0)
-        {
-           /* Tx FIFO not full ... process outgoing bytes */
-
-           uart_xmitchars(dev);
-           handled = true;
-        }
-    }
-    return OK;
-}
-
-/****************************************************************************
- * Name: up_ioctl
- *
- * Description:
- *   All ioctl calls will be routed through this method
- *
- ****************************************************************************/
-
-static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
-{
-  struct inode      *inode = filep->f_inode;
-  struct uart_dev_s *dev   = inode->i_private;
-  int                ret    = OK;
-
-  switch (cmd)
-    {
-    case TIOCSERGSTRUCT:
-      {
-         struct up_dev_s *user = (struct up_dev_s*)arg;
-         if (!user)
-           {
-             ret = -EINVAL;
-           }
-         else
-           {
-             memcpy(user, dev, sizeof(struct up_dev_s));
-           }
-       }
-       break;
-
-    default:
-      ret = -ENOTTY;
-      break;
-    }
-
-  return ret;
-}
-
-/****************************************************************************
- * Name: up_receive
- *
- * Description:
- *   Called (usually) from the interrupt level to receive one
- *   character from the UART.  Error bits associated with the
- *   receipt are provided in the return 'status'.
- *
- ****************************************************************************/
-
-static int up_receive(struct uart_dev_s *dev, uint32_t *status)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  uint32_t rxd;
-
-  /* Get the Rx byte + 4 bits of error information.  Return those in status */
-
-  rxd     = up_serialin(priv, LM3S_UART_DR_OFFSET);
-  *status = rxd;
-
-  /* The lower 8bits of the Rx data is the actual recevied byte */
-
-  return rxd & 0xff;
-}
-
-/****************************************************************************
- * Name: up_rxint
- *
- * Description:
- *   Call to enable or disable RX interrupts
- *
- ****************************************************************************/
-
-static void up_rxint(struct uart_dev_s *dev, bool enable)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  if (enable)
-    {
-      /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx
-       * timeout occurs.
-       */
-
-#ifndef CONFIG_SUPPRESS_SERIAL_INTS
-      priv->im |= (UART_IM_RXIM|UART_IM_RTIM);
-#endif
-    }
-  else
-    {
-      priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
-    }
-  up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
-}
-
-/****************************************************************************
- * Name: up_rxavailable
- *
- * Description:
- *   Return true if the receive fifo is not empty
- *
- ****************************************************************************/
-
-static bool up_rxavailable(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
-}
-
-/****************************************************************************
- * Name: up_send
- *
- * Description:
- *   This method will send one byte on the UART
- *
- ****************************************************************************/
-
-static void up_send(struct uart_dev_s *dev, int ch)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
-}
-
-/****************************************************************************
- * Name: up_txint
- *
- * Description:
- *   Call to enable or disable TX interrupts
- *
- ****************************************************************************/
-
-static void up_txint(struct uart_dev_s *dev, bool enable)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  irqstate_t flags;
-
-  flags = irqsave();
-  if (enable)
-    {
-      /* Set to receive an interrupt when the TX fifo is half emptied */
-
-#ifndef CONFIG_SUPPRESS_SERIAL_INTS
-      priv->im |= UART_IM_TXIM;
-      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
-
-      /* The serial driver wants an interrupt here, but will not get get
-       * one unless we "prime the pump."  I believe that this is because
-       * behave like a level interrupt and the LM3S interrupts behave
-       * (at least by default) like edge interrupts.
-       *
-       * In any event, faking a TX interrupt here solves the problem;
-       * Call uart_xmitchars() just as would have been done if we recieved
-       * the TX interrupt.
-       */
-
-      uart_xmitchars(dev);
-#endif
-    }
-  else
-    {
-      /* Disable the TX interrupt */
-
-      priv->im &= ~UART_IM_TXIM;
-      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
-    }
-  irqrestore(flags);
-}
-
-/****************************************************************************
- * Name: up_txready
- *
- * Description:
- *   Return true if the tranmsit fifo is not full
- *
- ****************************************************************************/
-
-static bool up_txready(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
-}
-
-/****************************************************************************
- * Name: up_txempty
- *
- * Description:
- *   Return true if the transmit fifo is empty
- *
- ****************************************************************************/
-
-static bool up_txempty(struct uart_dev_s *dev)
-{
-  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_serialinit
- *
- * Description:
- *   Performs the low level UART initialization early in 
- *   debug so that the serial console will be available
- *   during bootup.  This must be called before up_serialinit.
- *
- ****************************************************************************/
-
-void up_earlyserialinit(void)
-{
-  /* NOTE:  All GPIO configuration for the UARTs was performed in
-   * up_lowsetup
-   */
-
-  /* Disable all UARTS */
-
-  up_disableuartint(TTYS0_DEV.priv, NULL);
-#ifdef TTYS1_DEV
-  up_disableuartint(TTYS1_DEV.priv, NULL);
-#endif
-#ifdef TTYS2_DEV
-  up_disableuartint(TTYS2_DEV.priv, NULL);
-#endif
-
-  /* Configuration whichever one is the console */
-
-#ifdef HAVE_CONSOLE
-  CONSOLE_DEV.isconsole = true;
-  up_setup(&CONSOLE_DEV);
-#endif
-}
-
-/****************************************************************************
- * Name: up_serialinit
- *
- * Description:
- *   Register serial console and serial ports.  This assumes
- *   that up_earlyserialinit was called previously.
- *
- ****************************************************************************/
-
-void up_serialinit(void)
-{
-  /* Register the console */
-
-#ifdef HAVE_CONSOLE
-  (void)uart_register("/dev/console", &CONSOLE_DEV);
-#endif
-
-  /* Register all UARTs */
-
-  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
-#ifdef TTYS1_DEV
-  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
-#endif
-#ifdef TTYS2_DEV
-  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
-#endif
-}
-
-/****************************************************************************
- * Name: up_putc
- *
- * Description:
- *   Provide priority, low-level access to support OS debug  writes
- *
- ****************************************************************************/
-
-int up_putc(int ch)
-{
-#ifdef HAVE_CONSOLE
-  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
-  uint32_t im;
-
-  up_disableuartint(priv, &im);
-  up_waittxnotfull(priv);
-  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
-
-  /* Check for LF */
-
-  if (ch == '\n')
-    {
-      /* Add CR */
-
-      up_waittxnotfull(priv);
-      up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r');
-    }
-
-  up_waittxnotfull(priv);
-  up_restoreuartint(priv, im);
-#endif
-  return ch;
-}
-
-#else /* USE_SERIALDRIVER */
-
-/****************************************************************************
- * Name: up_putc
- *
- * Description:
- *   Provide priority, low-level access to support OS debug writes
- *
- ****************************************************************************/
-
-int up_putc(int ch)
-{
-#ifdef HAVE_CONSOLE
-  /* Check for LF */
-
-  if (ch == '\n')
-    {
-      /* Add CR */
-
-      up_lowputc('\r');
-    }
-
-  up_lowputc(ch);
-#endif
-  return ch;
-}
-
-#endif /* USE_SERIALDRIVER */
diff --git a/nuttx/arch/arm/src/lm/lm3s_ssi.c b/nuttx/arch/arm/src/lm/lm3s_ssi.c
deleted file mode 100644
index 8cd1cee07..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_ssi.c
+++ /dev/null
@@ -1,1580 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm32/lm3s_ssi.c
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include <semaphore.h>
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/spi.h>
-
-#include <arch/irq.h>
-#include <arch/board/board.h>
-
-#include "up_internal.h"
-#include "up_arch.h"
-
-#include "chip.h"
-#include "lm_gpio.h"
-#include "lm_ssi.h"
-#include "chip/lm_pinmap.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Enables debug output from this file (needs CONFIG_DEBUG with
- * CONFIG_DEBUG_VERBOSE too)
- */
-
-#undef SSI_DEBUG  /* Define to enable debug */
-
-#ifdef SSI_DEBUG
-#  define ssidbg  lldbg
-#  define ssivdbg llvdbg
-#else
-#  define ssidbg(x...)
-#  define ssivdbg(x...)
-#endif
-
-/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI
- * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in
- * such case, the following must be expanded).
- */
-
-#if LM3S_NSSI == 0
-#  undef CONFIG_SSI0_DISABLE
-#  define CONFIG_SSI0_DISABLE 1
-#  undef CONFIG_SSI1_DISABLE
-#  define CONFIG_SSI1_DISABLE 1
-#elif LM3S_NSSI == 1
-#  undef CONFIG_SSI1_DISABLE
-#  define CONFIG_SSI1_DISABLE 1
-#endif
-
-/* Which SSI modules have been enabled? */
-
-#ifndef CONFIG_SSI0_DISABLE
-#  define SSI0_NDX 0             /* Index to SSI0 in g_ssidev[] */
-#  ifndef CONFIG_SSI1_DISABLE
-#   define SSI1_NDX 1            /* Index to SSI1 in g_ssidev[] */
-#   define NSSI_ENABLED 2        /* Two SSI interfaces: SSI0 & SSI1 */
-#  else
-#   define NSSI_ENABLED 1        /* One SSI interface: SSI0 */
-#   define SSI_BASE          LM3S_SSI0_BASE
-#   define SSI_IRQ           LM3S_IRQ_SSI0
-#  endif
-#else
-#  ifndef CONFIG_SSI1_DISABLE
-#   define SSI1_NDX 0            /* Index to SSI1 in g_ssidev[] */
-#   define NSSI_ENABLED 1        /* One SSI interface: SSI1 */
-#   define SSI_BASE          LM3S_SSI1_BASE
-#   define SSI_IRQ           LM3S_IRQ_SSI1
-#  else
-#   define NSSI_ENABLED 0        /* No SSI interfaces */
-#  endif
-#endif
-
-/* Compile the rest of the file only if at least one SSI interface has been
- * enabled.
- */
-
-#if NSSI_ENABLED > 0
-
-/* The number of (16-bit) words that will fit in the Tx FIFO */
-
-#define LM3S_TXFIFO_WORDS 8
-
-/* Configuration settings */
-
-#ifndef CONFIG_SSI_TXLIMIT
-#  define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2)
-#endif
-
-#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS
-#  error "Invalid range for CONFIG_SSI_TXLIMIT"
-#endif
-
-#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2)
-#  error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
-#endif
-
-/****************************************************************************
- * Private Type Definitions
- ****************************************************************************/
-
-struct lm3s_ssidev_s
-{
-  const struct spi_ops_s *ops;  /* Common SPI operations */
-#ifndef CONFIG_SSI_POLLWAIT
-  sem_t  xfrsem;                /* Wait for transfer to complete */
-#endif
-
-  /* These following are the source and destination buffers of the transfer.
-   * they are retained in this structure so that they will be accessible
-   * from an interrupt handler.  The actual type of the buffer is uint8_t if
-   * nbits <=8 and uint16_t if nbits >8.
-   */
-
-  void  *txbuffer;              /* Source buffer */
-  void  *rxbuffer;              /* Destination buffer */
-
-  /* These are functions pointers that are configured to perform the
-   * appropriate transfer for the particular kind of exchange that is
-   * occurring.  Differnt functions may be selected depending on (1)
-   * if the tx or txbuffer is NULL and depending on the number of bits
-   * per word.
-   */
-
-  void  (*txword)(struct lm3s_ssidev_s *priv);
-  void  (*rxword)(struct lm3s_ssidev_s *priv);
-
-#if NSSI_ENABLED > 1
-  uint32_t base;                /* SSI register base address */
-#endif
-
-  int      ntxwords;            /* Number of words left to transfer on the Tx FIFO */
-  int      nrxwords;            /* Number of words received on the Rx FIFO */
-  int      nwords;              /* Number of words to be exchanged */
-  uint8_t  nbits;               /* Current number of bits per word */
-
-#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
-  uint8_t  irq;                 /* SSI IRQ number */
-#endif
-
-  /* If there is more than one device on the SPI bus, then we have to enforce
-   * mutual exclusion and remember some configuration settings to reduce the
-   * overhead of constant SPI re-configuration.
-   */
-
-#ifndef CONFIG_SPI_OWNBUS
-  sem_t    exclsem;             /* For exclusive access to the SSI bus */
-  uint32_t frequency;           /* Current desired SCLK frequency */
-  uint32_t actual;              /* Current actual SCLK frequency */
-  uint8_t  mode;                /* Current mode 0,1,2,3 */
-#endif
-};
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/* SSI register access */
-
-static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv,
-              unsigned int offset);
-static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset,
-              uint32_t value);
-
-/* Misc helpers */
-
-static uint32_t ssi_disable(struct lm3s_ssidev_s *priv);
-static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable);
-
-#ifndef CONFIG_SSI_POLLWAIT
-static void ssi_semtake(sem_t *sem);
-#define ssi_semgive(s) sem_post(s);
-#endif
-
-/* SSI data transfer */
-
-static void ssi_txnull(struct lm3s_ssidev_s *priv);
-static void ssi_txuint16(struct lm3s_ssidev_s *priv);
-static void ssi_txuint8(struct lm3s_ssidev_s *priv);
-static void ssi_rxnull(struct lm3s_ssidev_s *priv);
-static void ssi_rxuint16(struct lm3s_ssidev_s *priv);
-static void ssi_rxuint8(struct lm3s_ssidev_s *priv);
-static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv);
-static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv);
-#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT)
-static inline int ssi_performtx(struct lm3s_ssidev_s *priv);
-#else
-static int  ssi_performtx(struct lm3s_ssidev_s *priv);
-#endif
-static inline void ssi_performrx(struct lm3s_ssidev_s *priv);
-static int  ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer,
-                         void *rxbuffer, unsigned int nwords);
-
-/* Interrupt handling */
-
-#ifndef CONFIG_SSI_POLLWAIT
-static inline struct lm3s_ssidev_s *ssi_mapirq(int irq);
-static int  ssi_interrupt(int irq, void *context);
-#endif
-
-/* SPI methods */
-
-#ifndef CONFIG_SPI_OWNBUS
-static int  ssi_lock(FAR struct spi_dev_s *dev, bool lock);
-#endif
-static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv,
-              uint32_t frequency);
-static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev,
-              uint32_t frequency);
-static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv,
-              enum spi_mode_e mode);
-static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
-static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits);
-static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits);
-static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd);
-#ifdef CONFIG_SPI_EXCHANGE
-static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
-                         FAR void *rxbuffer, size_t nwords);
-#else
-static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
-              size_t nwords);
-static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
-              size_t nwords);
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/* Common SSI operations */
-
-static const struct spi_ops_s g_spiops =
-{
-#ifndef CONFIG_SPI_OWNBUS
-  .lock         = ssi_lock,
-#endif
-  .select       = lm3s_spiselect,    /* Provided externally by board logic */
-  .setfrequency = ssi_setfrequency,
-  .setmode      = ssi_setmode,
-  .setbits      = ssi_setbits,
-  .status       = lm3s_spistatus,    /* Provided externally by board logic */
-#ifdef CONFIG_SPI_CMDDATA
-  .cmddata      = lm3s_spicmddata,
-#endif
-  .send         = ssi_send,
-#ifdef CONFIG_SPI_EXCHANGE
-  .exchange     = ssi_exchange,
-#else
-  .sndblock     = ssi_sndblock,
-  .recvblock    = ssi_recvblock,
-#endif
-};
-
-/* This supports is up to two SSI busses/ports */
-
-static struct lm3s_ssidev_s g_ssidev[] =
-{
-#ifndef CONFIG_SSI0_DISABLE
-  {
-    .ops  = &g_spiops,
-#if NSSI_ENABLED > 1
-    .base = LM3S_SSI0_BASE,
-#endif
-#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
-    .irq  = LM3S_IRQ_SSI0,
-#endif
-  },
-#endif
-#ifndef CONFIG_SSI1_DISABLE
-  {
-    .ops  = &g_spiops,
-#if NSSI_ENABLED > 1
-    .base = LM3S_SSI1_BASE,
-#endif
-#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
-    .irq  = LM3S_IRQ_SSI1,
-#endif
-  },
-#endif
-};
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: ssi_getreg
- *
- * Description:
- *   Read the SSI register at this offeset
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   offset - Offset to the SSI register from the register base address
- *
- * Returned Value:
- *   Value of the register at this offset
- *
- ****************************************************************************/
-
-static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, unsigned int offset)
-{
-#if NSSI_ENABLED > 1
-  return getreg32(priv->base + offset);
-#else
-  return getreg32(SSI_BASE + offset);
-#endif
-}
-
-/****************************************************************************
- * Name: ssi_putreg
- *
- * Description:
- *   Write the value to the SSI register at this offeset
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   offset - Offset to the SSI register from the register base address
- *   value  - Value to write
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, uint32_t value)
-{
-#if NSSI_ENABLED > 1
-  putreg32(value, priv->base + offset);
-#else
-  putreg32(value, SSI_BASE + offset);
-#endif
-}
-
-/****************************************************************************
- * Name: ssi_disable
- *
- * Description:
- *   Disable SSI operation.  NOTE: The SSI must be disabled before any control
- *   registers can be re-programmed.
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   State of the SSI before the SSE was disabled
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static uint32_t ssi_disable(struct lm3s_ssidev_s *priv)
-{
-  uint32_t retval;
-  uint32_t regval;
-
-  retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
-  regval = (retval & ~SSI_CR1_SSE);
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
-  ssivdbg("CR1: %08x\n", regval);
-  return retval;
-}
-
-/****************************************************************************
- * Name: ssi_enable
- *
- * Description:
- *   Restore the SSI operational state
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   enable - The previous operational state
- *
- * Returned Value:
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable)
-{
-  uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
-  regval &= ~SSI_CR1_SSE;
-  regval  |= (enable & SSI_CR1_SSE);
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
-  ssivdbg("CR1: %08x\n", regval);
-}
-
-/****************************************************************************
- * Name: ssi_semtake
- *
- * Description:
- *   Wait for a semaphore (handling interruption by signals);
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   enable - The previous operational state
- *
- * Returned Value:
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SSI_POLLWAIT
-static void ssi_semtake(sem_t *sem)
-{
-  int ret;
-  do
-    {
-      ret = sem_wait(sem);
-    }
-  while (ret < 0 && errno == EINTR);
-  DEBUGASSERT(ret == 0);
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8
- *
- * Description:
- *   Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer
- *   pointer appropriately.  The selected function dependes on (1) if there
- *   is a source txbuffer provided, and (2) if the number of bits per
- *   word is <=8 or >8.
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static void ssi_txnull(struct lm3s_ssidev_s *priv)
-{
-  ssivdbg("TX: ->0xffff\n");
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff);
-}
-
-static void ssi_txuint16(struct lm3s_ssidev_s *priv)
-{
-  uint16_t *ptr    = (uint16_t*)priv->txbuffer;
-  ssivdbg("TX: %p->%04x\n", ptr, *ptr);
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
-  priv->txbuffer = (void*)ptr;
-}
-
-static void ssi_txuint8(struct lm3s_ssidev_s *priv)
-{
-  uint8_t *ptr   = (uint8_t*)priv->txbuffer;
-  ssivdbg("TX: %p->%02x\n", ptr, *ptr);
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
-  priv->txbuffer = (void*)ptr;
-}
-
-/****************************************************************************
- * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8
- *
- * Description:
- *   Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the
- *   user rxvbuffer and update the rxbuffer pointer appropriately.  The
- *   selected function dependes on (1) if there is a desination rxbuffer
- *   provided, and (2) if the number of bits per word is <=8 or >8.
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static void ssi_rxnull(struct lm3s_ssidev_s *priv)
-{
-#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
-  uint32_t regval  = ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
-  ssivdbg("RX: discard %04x\n", regval);
-#else
-  (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
-#endif
-}
-
-static void ssi_rxuint16(struct lm3s_ssidev_s *priv)
-{
-  uint16_t *ptr    = (uint16_t*)priv->rxbuffer;
-  *ptr           = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
-  ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
-  priv->rxbuffer = (void*)(++ptr);
-}
-
-static void ssi_rxuint8(struct lm3s_ssidev_s *priv)
-{
-  uint8_t *ptr   = (uint8_t*)priv->rxbuffer;
-  *ptr           = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
-  ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
-  priv->rxbuffer = (void*)(++ptr);
-}
-
-/****************************************************************************
- * Name: ssi_txfifofull
- *
- * Description:
- *   Return true if the Tx FIFO is full
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   true: Not full
- *
- ****************************************************************************/
-
-static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv)
-{
-  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
-}
-
-/****************************************************************************
- * Name: ssi_rxfifoempty
- *
- * Description:
- *   Return true if the Rx FIFO is empty
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   true: Not empty
- *
- ****************************************************************************/
-
-static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv)
-{
-  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
-}
-
-/****************************************************************************
- * Name: ssi_performtx
- *
- * Description:
- *   If the Tx FIFO is empty, then transfer as many words as we can to
- *   the FIFO.
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   The number of words written to the Tx FIFO (a value from 0 to 8,
- *   inclusive).
- *
- ****************************************************************************/
-
-#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT)
-static inline int ssi_performtx(struct lm3s_ssidev_s *priv)
-{
-  /* Check if the Tx FIFO is full and more data to transfer */
-
-  if (!ssi_txfifofull(priv) && priv->ntxwords > 0)
-    {
-      /* Transfer one word to the Tx FIFO */
-
-      priv->txword(priv);
-      priv->ntxwords--;
-      return 1;
-    }
-  return 0;
-}
-
-#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */
-
-static int ssi_performtx(struct lm3s_ssidev_s *priv)
-{
-#ifndef CONFIG_SSI_POLLWAIT
-  uint32_t regval;
-#endif
-  int ntxd = 0;  /* Number of words written to Tx FIFO */
-
-  /* Check if the Tx FIFO is full */
-
-  if (!ssi_txfifofull(priv))
-    {
-      /* Not full.. Check if all of the Tx words have been sent */
-
-      if (priv->ntxwords > 0)
-        {
-          /* No.. Transfer more words until either the Tx FIFO is full or
-           * until all of the user provided data has been sent.
-           */
-#ifdef CONFIG_SSI_TXLIMIT
-          /* Further limit the number of words that we put into the Tx
-           * FIFO to CONFIG_SSI_TXLIMIT.  Otherwise, we could
-           * overrun the Rx FIFO on a very fast SSI bus.
-           */
-          for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++)
-#else
-          for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++)
-#endif
-            {
-               priv->txword(priv);
-            }
-
-          /* Update the count of words to to transferred */
-
-          priv->ntxwords -= ntxd;
-        }
-
-      /* Check again... Now have all of the Tx words been sent? */
-
-#ifndef CONFIG_SSI_POLLWAIT
-      regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
-      if (priv->ntxwords > 0)
-        {
-          /* No.. Enable the Tx FIFO interrupt.  This interrupt occurs
-           * when the Tx FIFO is 1/2 full or less.
-           */
-
-#ifdef CONFIG_DEBUG
-          regval |= (SSI_IM_TX|SSI_RIS_ROR);
-#else
-          regval |= SSI_IM_TX;
-#endif
-        }
-      else
-        {
-          /* Yes.. Disable the Tx FIFO interrupt.  The final stages of
-           * the transfer will be driven by Rx FIFO interrupts.
-           */
-
-          regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
-        }
-      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
-#endif /* CONFIG_SSI_POLLWAIT */
-    }
-  return ntxd;
-}
-
-#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */
-
-/****************************************************************************
- * Name: ssi_performrx
- *
- * Description:
- *   Transfer as many bytes as possible from the Rx FIFO to the user Rx
- *   buffer (if one was provided).
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static inline void ssi_performrx(struct lm3s_ssidev_s *priv)
-{
-#ifndef CONFIG_SSI_POLLWAIT
-  uint32_t regval;
-#endif
-
-  /* Loop while data is available in the Rx FIFO */
-
-  while (!ssi_rxfifoempty(priv))
-    {
-      /* Have all of the requested words been transferred from the Rx FIFO? */
-
-      if (priv->nrxwords < priv->nwords)
-        {
-          /* No.. Read more data from Rx FIFO */
-
-          priv->rxword(priv);
-          priv->nrxwords++;
-        }
-    }
-
-  /* The Rx FIFO is now empty.  While there is Tx data to be sent, the
-   * transfer will be driven by Tx FIFO interrupts.  The final part
-   * of the transfer is driven by Rx FIFO interrupts only.
-   */
-
-#ifndef CONFIG_SSI_POLLWAIT
-  regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
-  if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
-    {
-       /* There are no more outgoing words to send, but there are
-        * additional incoming words expected (I would think that this
-        * a real corner case, be we will handle it with an extra 
-        * interrupt, probably an Rx timeout).
-        */
-
-#ifdef CONFIG_DEBUG
-      regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR);
-#else
-      regval |= (SSI_IM_RX|SSI_IM_RT);
-#endif
-    }
-  else
-    {
-      /* No.. there are either more Tx words to send or all Rx words
-       * have received.  Disable Rx FIFO interrupts.
-       */
-
-      regval &= ~(SSI_IM_RX|SSI_IM_RT);
-    }
-  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
-#endif /* CONFIG_SSI_POLLWAIT */
-}
-
-/****************************************************************************
- * Name: ssi_transfer
- *
- * Description:
- *   Exchange a block data with the SPI device
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   txbuffer - The buffer of data to send to the device (may be NULL).
- *   rxbuffer - The buffer to receive data from the device (may be NULL).
- *   nwords   - The total number of words to be exchanged.  If the interface
- *              uses <= 8 bits per word, then this is the number of uint8_t's;
- *              if the interface uses >8 bits per word, then this is the
- *              number of uint16_t's
- *
- * Returned Value:
- *   0: success, <0:Negated error number on failure
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer,
-                        void *rxbuffer, unsigned int nwords)
-{
-#ifndef CONFIG_SSI_POLLWAIT
-  irqstate_t flags;
-#endif
-  int ntxd;
-
-  ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords);
-
-  /* Set up to perform the transfer */
-
-  priv->txbuffer     = (uint8_t*)txbuffer; /* Source buffer */
-  priv->rxbuffer     = (uint8_t*)rxbuffer; /* Destination buffer */
-  priv->ntxwords     = nwords;             /* Number of words left to send */
-  priv->nrxwords     = 0;                  /* Number of words received */
-  priv->nwords       = nwords;             /* Total number of exchanges */
-
-  /* Set up the low-level data transfer function pointers */
-
-  if (priv->nbits > 8)
-    {
-      priv->txword = ssi_txuint16;
-      priv->rxword = ssi_rxuint16;
-    }
-  else
-    {
-      priv->txword = ssi_txuint8;
-      priv->rxword = ssi_rxuint8;
-    }
-
-  if (!txbuffer)
-    {
-      priv->txword = ssi_txnull;
-    }
-
-  if (!rxbuffer)
-    {
-      priv->rxword = ssi_rxnull;
-    }
-
-  /* Prime the Tx FIFO to start the sequence (saves one interrupt).
-   * At this point, all SSI interrupts should be disabled, but the
-   * operation of ssi_performtx() will set up the interrupts
-   * approapriately (if nwords > TxFIFO size).
-   */
-
-#ifndef CONFIG_SSI_POLLWAIT
-  flags = irqsave();
-  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
-          priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
-
-  ntxd  = ssi_performtx(priv);
-
-  /* For the case where nwords < Tx FIFO size, ssi_performrx will
-   * configure interrupts correctly for the final phase of the
-   * the transfer.
-   */
-
-  ssi_performrx(priv);
-
-  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
-          priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
-          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
-
-  /* Wait for the transfer to complete.  Since there is no handshake
-   * with SPI, the following should complete even if there are problems
-   * with the transfer, so it should be safe with no timeout.
-   */
-
-  ssivdbg("Waiting for transfer complete\n");
-  irqrestore(flags);
-  do
-    {
-      ssi_semtake(&priv->xfrsem);
-    }
-  while (priv->nrxwords < priv->nwords);
-  ssidbg("Transfer complete\n");
-
-#else
-  /* Perform the transfer using polling logic.  This will totally
-   * dominate the CPU until the transfer is complete.  Only recommended
-   * if (1) your SPI is very fast, and (2) if you only use very short
-   * transfers.
-   */
-
-  do
-    {
-      /* Handle outgoing Tx FIFO transfers */
-
-      ntxd = ssi_performtx(priv);
-
-      /* Handle incoming Rx FIFO transfers */
-
-      ssi_performrx(priv);
-
-      /* If there are other threads at this same priority level,
-       * the following may help:
-       */
-
-      sched_yield();
-    }
-  while (priv->nrxwords < priv->nwords);
-#endif
-  return OK;
-}
-
-/****************************************************************************
- * Name: ssi_mapirq
- *
- * Description:
- *   Map an IRQ number into the appropriate SSI device
- *
- * Input Parameters:
- *   irq   - The IRQ number to be mapped
- *
- * Returned Value:
- *   On success, a reference to the private data structgure for this IRQ.
- *   NULL on failure.
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SSI_POLLWAIT
-static inline struct lm3s_ssidev_s *ssi_mapirq(int irq)
-{
-  switch (irq)
-    {
-#ifndef CONFIG_SSI0_DISABLE
-      case LM3S_IRQ_SSI0:
-        return &g_ssidev[SSI0_NDX];
-#endif
-#ifndef CONFIG_SSI1_DISABLE
-      case LM3S_IRQ_SSI1:
-        return &g_ssidev[SSI1_NDX];
-#endif
-      default:
-        return NULL;
-    }
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_interrupt
- *
- * Description:
- *   Exchange a block data with the SSI device
- *
- * Input Parameters:
- *   priv   - Device-specific state data
- *   txbuffer - The buffer of data to send to the device (may be NULL).
- *   rxbuffer - The buffer to receive data from the device (may be NULL).
- *   nwords   - The total number of words to be exchanged.  If the interface
- *              uses <= 8 bits per word, then this is the number of uint8_t's;
- *              if the interface uses >8 bits per word, then this is the
- *              number of uint16_t's
- *
- * Returned Value:
- *   0: success, <0:Negated error number on failure
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SSI_POLLWAIT
-static int ssi_interrupt(int irq, void *context)
-{
-  struct lm3s_ssidev_s *priv = ssi_mapirq(irq);
-  uint32_t regval;
-  int ntxd;
-
-  DEBUGASSERT(priv != NULL);
-
-  /* Clear pending interrupts */
-
-  regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET);
-  ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval);
-
-  /* Check for Rx FIFO overruns */
-
-#ifdef CONFIG_DEBUG
-  if ((regval & SSI_RIS_ROR) != 0)
-    {
-      lldbg("Rx FIFO Overrun!\n");
-    }
-#endif
-
-  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
-          priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
-
-  /* Handle outgoing Tx FIFO transfers */
-
-  ntxd = ssi_performtx(priv);
-
-  /* Handle incoming Rx FIFO transfers */
-
-  ssi_performrx(priv);
-
-  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
-          priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
-          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
-
-  /* Check if the transfer is complete */
-
-  if (priv->nrxwords >= priv->nwords)
-    {
-      /* Yes.. Disable all SSI interrupt sources */
-
-      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
-
-      /* Wake up the waiting thread */
-
-      ssidbg("Transfer complete\n");
-      ssi_semgive(&priv->xfrsem);
-    }
-  return OK;
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_lock
- *
- * Description:
- *   On SPI busses where there are multiple devices, it will be necessary to
- *   lock SPI to have exclusive access to the busses for a sequence of
- *   transfers.  The bus should be locked before the chip is selected. After
- *   locking the SPI bus, the caller should then also call the setfrequency,
- *   setbits, and setmode methods to make sure that the SPI is properly
- *   configured for the device.  If the SPI buss is being shared, then it
- *   may have been left in an incompatible state.
- *
- * Input Parameters:
- *   dev  - Device-specific state data
- *   lock - true: Lock spi bus, false: unlock SPI bus
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SPI_OWNBUS
-static int ssi_lock(FAR struct spi_dev_s *dev, bool lock)
-{
-  FAR struct lm3s_ssidev_s *priv = (FAR struct lm3s_ssidev_s *)dev;
-
-  if (lock)
-    {
-      /* Take the semaphore (perhaps waiting) */
-
-      while (sem_wait(&priv->exclsem) != 0)
-        {
-          /* The only case that an error should occur here is if the wait was awakened
-           * by a signal.
-           */
-
-          ASSERT(errno == EINTR);
-        }
-    }
-  else
-    {
-      (void)sem_post(&priv->exclsem);
-    }
-  return OK;
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_setfrequency
- *
- * Description:
- *   Set the SPI frequency.
- *
- * Input Parameters:
- *   dev -       Device-specific state data
- *   frequency - The SPI frequency requested
- *
- * Returned Value:
- *   Returns the actual frequency selected
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, uint32_t frequency)
-{
-  uint32_t maxdvsr;
-  uint32_t cpsdvsr;
-  uint32_t regval;
-  uint32_t scr;
-  uint32_t actual;
-
-  ssidbg("frequency: %d\n", frequency);
-  DEBUGASSERT(frequency);
-
-  /* Has the frequency changed? */
-
-#ifndef CONFIG_SPI_OWNBUS
-  if (frequency != priv->frequency)
-    {
-#endif
-      /* "The serial bit rate is derived by dividing down the input clock
-       *  (FSysClk). The clock is first divided by an even prescale value
-       *  CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
-       *  (SSI_CPSR) register ... The clock is further divided by a value
-       *  from 1 to 256, which is 1 + SCR, where SCR is the value programmed 
-       *  i n the SSI Control0 (SSICR0) register ...
-       *
-       * "The frequency of the output clock SSIClk is defined by:
-       *
-       *    "SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
-       *
-       * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz,
-       *  the module may not be able to operate at that speed. For master mode,
-       *  the system clock must be at least two times faster than the SSIClk.
-       *  For slave mode, the system clock must be at least 12 times faster
-       *  than the SSIClk."
-       */
-
-      if (frequency > SYSCLK_FREQUENCY/2)
-        {
-          frequency = SYSCLK_FREQUENCY/2;
-        }
-
-      /* Find optimal values for CPSDVSR and SCR.  This loop is inefficient,
-       * but should not have to execute many times.
-       *
-       * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000.
-       *
-       *   maxcvsr = 125
-       *   1. cpsdvsr = 2, scr = 61 -> DONE
-       *
-       *   This would correspond to an actual frequency of:
-       *   50,000,000 / (2 * (62)) = 403,226
-       *
-       * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000.
-       *
-       *   maxcvsr = 2
-       *   1. cpsdvsr = 2, scr = 0 -> DONE
-       *
-       *   This would correspond to an actual frequency of:
-       *   50,000,000 / (2 * (1)) = 25,000,000
-       */
-
-      maxdvsr = SYSCLK_FREQUENCY / frequency;
-      cpsdvsr = 0;
-      do
-        {
-          cpsdvsr += 2;
-          scr = (maxdvsr / cpsdvsr) - 1;
-        }
-      while (scr > 255);
-
-      /* Set CPDVSR */
-
-      DEBUGASSERT(cpsdvsr < 255);
-      ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr);
-
-      /* Set SCR */
-
-      regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
-      regval &= ~SSI_CR0_SCR_MASK;
-      regval |= (scr << SSI_CR0_SCR_SHIFT);
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
-      ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
-
-      /* Calcluate the actual frequency */
-
-      actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1));
-
-      /* Save the frequency selection so that subsequent reconfigurations will be
-       * faster.
-       */
-
-#ifndef CONFIG_SPI_OWNBUS
-      priv->frequency = frequency;
-      priv->actual    = actual;
-    }
-  return priv->actual;
-#else
-  return actual;
-#endif
-}
-
-static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  uint32_t enable;
-  uint32_t actual;
-
-  /* NOTE that the SSI must be disabled when setting any configuration registers. */
-
-  enable = ssi_disable(priv);
-  actual = ssi_setfrequencyinternal(priv, frequency);
-  ssi_enable(priv, enable);
-  return actual;
-}
-
-/****************************************************************************
- * Name: ssi_setmode
- *
- * Description:
- *   Set the SPI mode. Optional.  See enum spi_mode_e for mode definitions
- *
- * Input Parameters:
- *   dev -  Device-specific state data
- *   mode - The SPI mode requested
- *
- * Returned Value:
- *   none
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, enum spi_mode_e mode)
-{
-  uint32_t modebits;
-  uint32_t regval;
-
-  ssidbg("mode: %d\n", mode);
-  DEBUGASSERT(priv);
-
-  /* Has the number of bits per word changed? */
-
-#ifndef CONFIG_SPI_OWNBUS
-  if (mode != priv->mode)
-    {
-#endif
-      /* Select the CTL register bits based on the selected mode */
-
-      switch (mode)
-        {
-        case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
-          modebits = 0;
-          break;
-
-        case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
-          modebits = SSI_CR0_SPH;
-          break;
-
-        case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
-          modebits = SSI_CR0_SPO;
-         break;
-
-        case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
-          modebits = SSI_CR0_SPH|SSI_CR0_SPO;
-          break;
-
-        default:
-          return;
-        }
-
-      /* Then set the selected mode: Freescale SPI format, mode0-3 */
-
-      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
-      regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
-      regval |= modebits;
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
-      ssivdbg("CR0: %08x\n", regval);
-
-      /* Save the mode so that subsequent re-configuratins will be faster */
-
-#ifndef CONFIG_SPI_OWNBUS
-      priv->mode = mode;
-    }
-#endif
-}
-
-static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  uint32_t enable;
-
-  /* NOTE that the SSI must be disabled when setting any configuration registers. */
-
-  enable = ssi_disable(priv);
-  ssi_setmodeinternal(priv, mode);
-  ssi_enable(priv, enable);
-}
-
-/****************************************************************************
- * Name: ssi_setbits
- *
- * Description:
- *   Set the number if bits per word.
- *
- * Input Parameters:
- *   dev -  Device-specific state data
- *   nbits - The number of bits requests
- *
- * Returned Value:
- *   none
- *
- * Assumption:
- *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
- *
- ****************************************************************************/
-
-static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits)
-{
-  uint32_t regval;
-
-  ssidbg("nbits: %d\n", nbits);
-  DEBUGASSERT(priv);
-  if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
-    {
-      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
-      regval &= ~SSI_CR0_DSS_MASK;
-      regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
-      ssivdbg("CR0: %08x\n", regval);
-
-      priv->nbits = nbits;
-    }
-}
-
-static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  uint32_t enable;
-
-  /* NOTE that the SSI must be disabled when setting any configuration registers. */
-
-  enable = ssi_disable(priv);
-  ssi_setbitsinternal(priv, nbits);
-  ssi_enable(priv, enable);
-}
-
-/****************************************************************************
- * Name: ssi_send
- *
- * Description:
- *   Exchange one word on SPI
- *
- * Input Parameters:
- *   dev - Device-specific state data
- *   wd  - The word to send.  the size of the data is determined by the
- *         number of bits selected for the SPI interface.
- *
- * Returned Value:
- *   response
- *
- ****************************************************************************/
-
-static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s*)dev;
-  uint16_t response = 0;
-
-  (void)ssi_transfer(priv, &wd, &response, 1);
-  return response;
-}
-
-/****************************************************************************
- * Name: SPI_EXCHANGE
- *
- * Description:
- *   Exahange a block of data from SPI. Required.
- *
- * Input Parameters:
- *   dev      - Device-specific state data
- *   buffer   - A pointer to the buffer of data to be sent
- *   rxbuffer - A pointer to the buffer in which to recieve data
- *   nwords   - the length of data that to be exchanged in units of words.
- *              The wordsize is determined by the number of bits-per-word
- *              selected for the SPI interface.  If nbits <= 8, the data is
- *              packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifdef CONFIG_SPI_EXCHANGE
-static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
-                         FAR void *rxbuffer, size_t nwords)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords);
-}
-#endif
-
-/*************************************************************************
- * Name: ssi_sndblock
- *
- * Description:
- *   Send a block of data on SPI
- *
- * Input Parameters:
- *   dev -    Device-specific state data
- *   buffer - A pointer to the buffer of data to be sent
- *   nwords - the length of data to send from the buffer in number of words.
- *            The wordsize is determined by the number of bits-per-word
- *            selected for the SPI interface.  If nbits <= 8, the data is
- *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SPI_EXCHANGE
-static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  (void)ssi_transfer(priv, buffer, NULL, nwords);
-}
-#endif
-
-/****************************************************************************
- * Name: ssi_recvblock
- *
- * Description:
- *   Revice a block of data from SPI
- *
- * Input Parameters:
- *   dev -    Device-specific state data
- *   buffer - A pointer to the buffer in which to recieve data
- *   nwords - the length of data that can be received in the buffer in number
- *            of words.  The wordsize is determined by the number of bits-per-word
- *            selected for the SPI interface.  If nbits <= 8, the data is
- *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifndef CONFIG_SPI_EXCHANGE
-static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
-{
-  struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev;
-  (void)ssi_transfer(priv, NULL, buffer, nwords);
-}
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_spiinitialize
- *
- * Description:
- *   Initialize common parts the selected SPI port.  Initialization of
- *   chip select GPIOs must have been performed by board specific logic
- *   prior to calling this function.  Specifically:  GPIOs should have
- *   been configured for output, and all chip selects disabled.
- *
- *   One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select.  However,
- *   If multiple devices on on the bus, then multiple chip selects will be
- *   required.  Theregore, all GPIO chip management is deferred to board-
- *   specific logic.
- *
- * Input Parameter:
- *   Port number (for hardware that has mutiple SSI interfaces)
- *
- * Returned Value:
- *   Valid SPI device structure reference on succcess; a NULL on failure
- *
- ****************************************************************************/
-
-FAR struct spi_dev_s *up_spiinitialize(int port)
-{
-  struct lm3s_ssidev_s *priv;
-  irqstate_t flags;
-  uint8_t regval;
-
-  ssidbg("port: %d\n", port);
- 
-  /* Set up for the selected port */
-
-  flags = irqsave();
-  switch (port)
-    {
-#ifndef CONFIG_SSI0_DISABLE
-    case 0:
-      /* Select SSI0 */
-
-      priv = &g_ssidev[SSI0_NDX];
-
-      /* Enable the SSI0 peripheral */
-
-      regval = getreg32(LM3S_SYSCON_RCGC1);
-      regval |= SYSCON_RCGC1_SSI0;
-      putreg32(regval, LM3S_SYSCON_RCGC1);
-      ssivdbg("RCGC1: %08x\n", regval);
-
-      /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
-       * logic in this file makes no assumptions about chip select)
-       */
-
-      lm3s_configgpio(GPIO_SSI0_CLK);  /* PA2: SSI0 clock (SSI0Clk) */
-   /* lm3s_configgpio(GPIO_SSI0_FSS);     PA3: SSI0 frame (SSI0Fss) */
-      lm3s_configgpio(GPIO_SSI0_RX);   /* PA4: SSI0 receive (SSI0Rx) */
-      lm3s_configgpio(GPIO_SSI0_TX);   /* PA5: SSI0 transmit (SSI0Tx) */
-      break;
-#endif /* CONFIG_SSI0_DISABLE */
-
-#ifndef CONFIG_SSI1_DISABLE
-    case 1:
-      /* Select SSI0 */
-
-      priv = &g_ssidev[SSI1_NDX];
-
-      /* Enable the SSI1 peripheral */
-
-      regval = getreg32(LM3S_SYSCON_RCGC1);
-      regval |= SYSCON_RCGC1_SSI1;
-      putreg32(regval, LM3S_SYSCON_RCGC1);
-      ssivdbg("RCGC1: %08x\n", regval);
-
-      /* Configure SSI1 GPIOs */
-
-      lm3s_configgpio(GPIO_SSI1_CLK);  /* PE0: SSI1 clock (SSI1Clk) */
-   /* lm3s_configgpio(GPIO_SSI1_FSS);     PE1: SSI1 frame (SSI1Fss) */
-      lm3s_configgpio(GPIO_SSI1_RX);   /* PE2: SSI1 receive (SSI1Rx) */
-      lm3s_configgpio(GPIO_SSI1_TX);   /* PE3: SSI1 transmit (SSI1Tx) */
-      break;
-#endif /* CONFIG_SSI1_DISABLE */
-
-    default:
-      irqrestore(flags);
-      return NULL;
-    }
-
-  /* Initialize the state structure */
-
-#ifndef CONFIG_SSI_POLLWAIT
-  sem_init(&priv->xfrsem, 0, 0);
-#endif
-#ifndef CONFIG_SPI_OWNBUS
-  sem_init(&priv->exclsem, 0, 1);
-#endif
-
-  /* Set all CR1 fields to reset state.  This will be master mode. */
-
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0);
-
-  /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
-
-  ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0);
-
-  /* Set the initial mode to mode 0.  The application may override
-   * this initial setting using the setmode() method.
-   */
-
-  ssi_setmodeinternal(priv, SPIDEV_MODE0);
-
-  /* Set the initial data width to 8-bits.  The application may
-   * override this initial setting using the setbits() method.
-   */
-
-  ssi_setbitsinternal(priv, 8);
-
-  /* Pick some initialize clock frequency. 400,000Hz is the startup
-   * MMC/SD frequency used for card detection.  The application may
-   * override this setting using the setfrequency() method.
-   */
-
-  ssi_setfrequencyinternal(priv, 400000);
-
-  /* Disable all SSI interrupt sources.  They will be enabled only
-   * while there is an SSI transfer in progress.
-   */
-
-  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
-
-  /* Attach the interrupt */
-
-#ifndef CONFIG_SSI_POLLWAIT
-#if NSSI_ENABLED > 1
-  irq_attach(priv->irq, (xcpt_t)ssi_interrupt);
-#else
-  irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt);
-#endif
-#endif /* CONFIG_SSI_POLLWAIT */
-
-  /* Enable the SSI for operation */
-
-  ssi_enable(priv, SSI_CR1_SSE);
-
-  /* Enable SSI interrupts (They are still disabled at the source). */
-
-#ifndef CONFIG_SSI_POLLWAIT
-#if NSSI_ENABLED > 1
-  up_enable_irq(priv->irq);
-#else
-  up_enable_irq(SSI_IRQ);
-#endif
-#endif /* CONFIG_SSI_POLLWAIT */
-
-  irqrestore(flags);
-  return (FAR struct spi_dev_s *)priv;
-}
-
-#endif /* NSSI_ENABLED > 0 */
diff --git a/nuttx/arch/arm/src/lm/lm3s_start.c b/nuttx/arch/arm/src/lm/lm3s_start.c
deleted file mode 100644
index 4dfe92844..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_start.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_start.c
- * arch/arm/src/chip/lm3s_start.c
- *
- *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <assert.h>
-#include <debug.h>
-
-#include <nuttx/init.h>
-#include <arch/board/board.h>
-
-#include "up_arch.h"
-#include "up_internal.h"
-
-#include "lm_lowputc.h"
-#include "lm_syscontrol.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-extern void lm3s_vectors(void);
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: showprogress
- *
- * Description:
- *   Print a character on the UART to show boot status.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_DEBUG
-#  define showprogress(c) up_lowputc(c)
-#else
-#  define showprogress(c)
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: _start
- *
- * Description:
- *   This is the reset entry point.
- *
- ****************************************************************************/
-
-void __start(void)
-{
-  const uint32_t *src;
-  uint32_t *dest;
-
-  /* Configure the uart so that we can get debug output as soon as possible */
-
-  up_clockconfig();
-  up_lowsetup();
-  showprogress('A');
-
-  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
-   * certain that there are no issues with the state of global variables.
-   */
-
-  for (dest = &_sbss; dest < &_ebss; )
-    {
-      *dest++ = 0;
-    }
-  showprogress('B');
-
-  /* Move the intialized data section from his temporary holding spot in
-   * FLASH into the correct place in SRAM.  The correct place in SRAM is
-   * give by _sdata and _edata.  The temporary location is in FLASH at the
-   * end of all of the other read-only data (.text, .rodata) at _eronly.
-   */
-
-  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
-    {
-      *dest++ = *src++;
-    }
-  showprogress('C');
-
-  /* Perform early serial initialization */
-
-#ifdef USE_EARLYSERIALINIT
-  up_earlyserialinit();
-#endif
-  showprogress('D');
-
-  /* Initialize onboard resources */
-
-  lm3s_boardinitialize();
-  showprogress('E');
-
-  /* Then start NuttX */
-
-  showprogress('\r');
-  showprogress('\n');
-  os_start();
-
-  /* Shoulnd't get here */
-
-  for(;;);
-}
diff --git a/nuttx/arch/arm/src/lm/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm/lm3s_syscontrol.c
deleted file mode 100644
index 87545bec7..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_syscontrol.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_syscontrol.c
- * arch/arm/src/chip/lm3s_syscontrol.c
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <assert.h>
-#include <debug.h>
-
-#include <nuttx/init.h>
-#include <arch/board/board.h>
-
-#include "up_arch.h"
-#include "up_internal.h"
-#include "chip.h"
-#include "lm_syscontrol.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define RCC_OSCMASK   (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
-#define RCC_XTALMASK  (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN)
-#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2)
-#define RCC_DIVMASK   (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
-#define RCC2_DIVMASK  (SYSCON_RCC2_SYSDIV2_MASK)
-#define FAST_OSCDELAY (512*1024)
-#define SLOW_OSCDELAY (4*1024)
-#define PLLLOCK_DELAY (32*1024)
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_delay
- *
- * Description:
- *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
- *   the time that we wait can be significant and is determined by the previous
- *   clock setting, not the one that we are configuring.
- *
- ****************************************************************************/
-
-static inline void lm3s_delay(uint32_t delay)
-{
-  __asm__ __volatile__("1:\n"
-                       "\tsubs  %0, #1\n"
-                       "\tbne   1b\n"
-                       : "=r"(delay) : "r"(delay));
-}
-
-/****************************************************************************
- * Name: lm3s_oscdelay
- *
- * Description:
- *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
- *   the time that we wait can be significant and is determined by the previous
- *   clock setting, not the one that we are configuring.
- *
- ****************************************************************************/
-
-static inline void lm3s_oscdelay(uint32_t rcc, uint32_t rcc2)
-{
-  /* Wait for the oscillator  to stabilize.  A smaller delay is used if the
-   * current clock rate is very slow.
-   */
-
-  uint32_t delay = FAST_OSCDELAY;
-
-  /* Are we currently using RCC2? */
-
-  if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
-    {
-      uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK;
-      if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) ||
-          (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ))
-        {
-          delay = SLOW_OSCDELAY;
-        }
-    }
-
-  /* No.. using srce in RCC */
-
-  else
-    {
-      uint32_t rccsrc  = rcc  & SYSCON_RCC_OSCSRC_MASK;
-      if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ)
-        {
-          delay = SLOW_OSCDELAY;
-        }
-    }
-
-  /* Then delay that number of loops */
-
-  lm3s_delay(delay);
-}
-
-/****************************************************************************
- * Name: lm3s_plllock
- *
- * Description:
- *   The new RCC values have been selected... wait for the PLL to lock on
- *
- ****************************************************************************/
-
-static inline void lm3s_plllock(void)
-{
-  volatile uint32_t delay;
-
-  /* Loop until the lock is achieved or until a timeout occurs */
-
-  for (delay = PLLLOCK_DELAY; delay > 0; delay--)
-    {
-      /* Check if the PLL is locked on */
-
-      if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
-        {
-          /* Yes.. return now */
-
-          return;
-        }
-    }
-
-  /* If we get here, then PLL lock was not achieved */
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lm3s_clockconfig
- *
- * Description:
- *   Called to change to new clock based on desired rcc and rcc2 settings.
- *   This is use to set up the initial clocking but can be used later to
- *   support slow clocked, low power consumption modes.
- *
- ****************************************************************************/
-
-void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2)
-{
-  uint32_t rcc;
-  uint32_t rcc2;
-
-  /* Get the current values of the RCC and RCC2 registers */
-
-  rcc  = getreg32(LM3S_SYSCON_RCC);
-  rcc2 = getreg32(LM3S_SYSCON_RCC2);
-
-  /* Temporarily bypass the PLL and system clock dividers */
-
-  rcc |= SYSCON_RCC_BYPASS;
-  rcc &= ~(SYSCON_RCC_USESYSDIV);
-  putreg32(rcc, LM3S_SYSCON_RCC);
-
-  rcc2 |= SYSCON_RCC2_BYPASS2;
-  putreg32(rcc2, LM3S_SYSCON_RCC2);
-
-  /* We are probably using the main oscillator.  The main oscillator is disabled on
-   * reset and so probably must be enabled here.  The internal oscillator is enabled
-   * on rest and if that is selected, most likely nothing needs to be done.
-   */
-
-  if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) ||
-      ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS)))
-    {
-      /* Enable any selected osciallators (but don't disable any yet) */
-
-      rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
-      putreg32(rcc, LM3S_SYSCON_RCC);
-
-      /* Wait for the newly selected oscillator(s) to settle.  This is tricky because
-       * the time that we wait can be significant and is determined by the previous
-       * clock setting, not the one that we are configuring.
-       */
-
-      lm3s_oscdelay(rcc, rcc2);
-    }
-
-  /* Set the new crystal value, oscillator source and PLL configuration */
-
-  rcc  &= ~RCC_XTALMASK;
-  rcc  |= newrcc & RCC_XTALMASK;
-
-  rcc2 &= ~RCC2_XTALMASK;
-  rcc2 |= newrcc2 & RCC2_XTALMASK;
-
-  /* Clear the PLL lock interrupt */
-
-  putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC);
-
-  /* Write the new RCC/RCC2 values.  Order depends upon whether RCC2 or RCC
-   * is currently enabled.
-   */
-
-  if (rcc2 & SYSCON_RCC2_USERCC2)
-    {
-      putreg32(rcc2, LM3S_SYSCON_RCC2);
-      putreg32(rcc, LM3S_SYSCON_RCC);
-    }
-    else
-    {
-      putreg32(rcc, LM3S_SYSCON_RCC);
-      putreg32(rcc2, LM3S_SYSCON_RCC2);
-    }
-
-  /* Wait for the new crystal value and oscillator source to take effect */
-
-  lm3s_delay(16);
-
-  /* Set the requested system divider and disable the non-selected osciallators */
-
-  rcc &= ~RCC_DIVMASK;
-  rcc |= newrcc & RCC_DIVMASK;
-
-  rcc2 &= ~RCC2_DIVMASK;
-  rcc2 |= newrcc2 & RCC2_DIVMASK;
-
-  /* Will the PLL output be used to clock the system? */
-
-  if ((newrcc & SYSCON_RCC_BYPASS) == 0)
-    {
-      /* Yes, wail untill the PLL is locked */
-
-      lm3s_plllock();
-
-      /* Then enable the PLL */
-
-      rcc  &= ~SYSCON_RCC_BYPASS;
-      rcc2 &= ~SYSCON_RCC2_BYPASS2;
-    }
-
-  /* Now we can set the final RCC/RCC2 values */
-
-  putreg32(rcc, LM3S_SYSCON_RCC);
-  putreg32(rcc2, LM3S_SYSCON_RCC2);
-
-  /* Wait for the system divider to be effective */
-
-  lm3s_delay(6);
-}
-
-/****************************************************************************
- * Name: up_clockconfig
- *
- * Description:
- *   Called early in the bootsequence (before .data and .bss are available)
- *   in order to configure initial clocking.
- *
- ****************************************************************************/
-
-void up_clockconfig(void)
-{
-#ifdef CONFIG_LM3S_REVA2
-  /* Some early silicon returned an increase LDO voltage or 2.75V to work
-   * around a PLL bug
-   */
-
-  putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL);
-#endif
-
-  /* Set the clocking to run with the default settings provided in the board.h
-   * header file
-   */
-
-  lm3s_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE);
-}
-
diff --git a/nuttx/arch/arm/src/lm/lm3s_timerisr.c b/nuttx/arch/arm/src/lm/lm3s_timerisr.c
deleted file mode 100644
index 823d810da..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_timerisr.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lm/lm3s_timerisr.c
- *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <time.h>
-#include <debug.h>
-#include <nuttx/arch.h>
-#include <arch/board/board.h>
-
-#include "nvic.h"
-#include "clock_internal.h"
-#include "up_internal.h"
-#include "up_arch.h"
-
-#include "chip.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* The desired timer interrupt frequency is provided by the definition
- * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
- * system clock ticks per second.  That value is a user configurable setting
- * that defaults to 100 (100 ticks per second = 10 MS interval).
- *
- * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h
- * header file.
- */
-
-#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1)
-
-/* The size of the reload field is 24 bits.  Verify taht the reload value
- * will fit in the reload register.
- */
-
-#if SYSTICK_RELOAD > 0x00ffffff
-#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
-#endif
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Global Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function:  up_timerisr
- *
- * Description:
- *   The timer ISR will perform a variety of services for various portions
- *   of the systems.
- *
- ****************************************************************************/
-
-int up_timerisr(int irq, uint32_t *regs)
-{
-   /* Process timer interrupt */
-
-   sched_process_timer();
-   return 0;
-}
-
-/****************************************************************************
- * Function:  up_timerinit
- *
- * Description:
- *   This function is called during start-up to initialize
- *   the timer interrupt.
- *
- ****************************************************************************/
-
-void up_timerinit(void)
-{
-  uint32_t regval;
-
-  /* Set the SysTick interrupt to the default priority */
-
-  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
-  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
-  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
-  putreg32(regval, NVIC_SYSH12_15_PRIORITY);
-
-  /* Configure SysTick to interrupt at the requested rate */
-
-  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
-
-  /* Attach the timer interrupt vector */
-
-  (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr);
-
-  /* Enable SysTick interrupts */
-
-  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
-
-  /* And enable the timer interrupt */
-
-  up_enable_irq(LM3S_IRQ_SYSTICK);
-}
diff --git a/nuttx/arch/arm/src/lm/lm3s_vectors.S b/nuttx/arch/arm/src/lm/lm3s_vectors.S
deleted file mode 100644
index fe92fc954..000000000
--- a/nuttx/arch/arm/src/lm/lm3s_vectors.S
+++ /dev/null
@@ -1,805 +0,0 @@
-/************************************************************************************
- * arch/arm/src/lm/lm3s_vectors.S
- * arch/arm/src/chip/lm3s_vectors.S
- *
- *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <arch/irq.h>
-
-/************************************************************************************
- * Preprocessor Definitions
- ************************************************************************************/
-
-/* Memory Map:
- *
- * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
- * 0x0002:0000 - Address of vectors if using bootloader
- * 0x0003:ffff - End of flash
- * 0x2000:0000 - Start of SRAM and start of .data (_sdata)
- *             - End of .data (_edata) abd start of .bss (_sbss)
- *             - End of .bss (_ebss) and bottom of idle stack
- *             - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap
- * 0x2000:ffff - End of SRAM and end of heap
- */
-
-#define IDLE_STACK		(_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
-#define HEAP_BASE		(_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
-
-/* The Cortex-M3 return from interrupt is unusual.  We provide the following special
- * address to the BX instruction.  The particular value also forces a return to
- * thread mode and covers state from the main stack point, the MSP (vs. the MSP).
- */
-
-#define EXC_RETURN		0xfffffff9
-
-/************************************************************************************
- * Global Symbols
- ************************************************************************************/
-
-	.globl		__start
-
-	.syntax		unified
-	.thumb
-	.file		"lm3s_vectors.S"
-
-/************************************************************************************
- * Macros
- ************************************************************************************/
-
-/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
- * registers on the stack, then branches to an instantantiation of the following
- * macro.  This macro simply loads the IRQ number into R0, then jumps to the common
- * IRQ handling logic.
- */
-
-	.macro	HANDLER, label, irqno
-	.thumb_func
-\label:
-	mov		r0, #\irqno
-	b		lm3s_irqcommon
-	.endm
-
-/************************************************************************************
- * Vectors
- ************************************************************************************/
-
-	.section	.vectors, "ax"
-	.code		16
-	.align		2
-	.globl		lm3s_vectors
-	.type		lm3s_vectors, function
-
-lm3s_vectors:
-
-/* Processor Exceptions */
-
-	.word	IDLE_STACK			/* Vector  0: Reset stack pointer */
-	.word	__start				/* Vector  1: Reset vector */
-	.word	lm3s_nmi			/* Vector  2: Non-Maskable Interrupt (NMI) */
-	.word	lm3s_hardfault		/* Vector  3: Hard fault */
-	.word	lm3s_mpu			/* Vector  4: Memory management (MPU) */
-	.word	lm3s_busfault		/* Vector  5: Bus fault */
-	.word	lm3s_usagefault		/* Vector  6: Usage fault */
-	.word	lm3s_reserved		/* Vector  7: Reserved */
-	.word	lm3s_reserved		/* Vector  8: Reserved */
-	.word	lm3s_reserved		/* Vector  9: Reserved */
-	.word	lm3s_reserved		/* Vector 10: Reserved */
-	.word	lm3s_svcall			/* Vector 11: SVC call */
-	.word	lm3s_dbgmonitor		/* Vector 12: Debug monitor */
-	.word	lm3s_reserved		/* Vector 13: Reserved */
-	.word	lm3s_pendsv			/* Vector 14: Pendable system service request */
-	.word	lm3s_systick		/* Vector 15: System tick */
-
-/* External Interrupts */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_reserved		/* Vector 25: Reserved */
-	.word	lm3s_reserved		/* Vector 26: Reserved */
-	.word	lm3s_reserved		/* Vector 27: Reserved */
-	.word	lm3s_reserved		/* Vector 28: Reserved */
-	.word	lm3s_reserved		/* Vector 29: Reserved */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
-	.word	lm3s_reserved		/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_gpioh			/* Vector 48: GPIO Port H */
-	.word	lm3s_reserved		/* Vector 49: Reserved */
-	.word	lm3s_ssi1			/* Vector 50: SSI 1 */
-	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
-	.word	lm3s_reserved		/* Vector 54: Reserved */
-	.word	lm3s_reserved		/* Vector 55: Reserved */
-	.word	lm3s_reserved		/* Vector 56: Reserved */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_hib			/* Vector 59: Hibernation Module */
-	.word	lm3s_reserved		/* Vector 60: Reserved */
-	.word	lm3s_reserved		/* Vector 61: Reserved */
-	.word	lm3s_reserved		/* Vector 62: Reserved */
-	.word	lm3s_reserved		/* Vector 63: Reserved */
-	.word	lm3s_reserved		/* Vector 64: Reserved */
-	.word	lm3s_reserved		/* Vector 65: Reserved */
-	.word	lm3s_reserved		/* Vector 66: Reserved */
-	.word	lm3s_reserved		/* Vector 67: Reserved */
-	.word	lm3s_reserved		/* Vector 68: Reserved */
-	.word	lm3s_reserved		/* Vector 69: Reserved */
-	.word	lm3s_reserved		/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_reserved		/* Vector 25: Reserved */
-	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
-	.word	lm3s_reserved		/* Vector 27: Reserved */
-	.word	lm3s_reserved		/* Vector 28: Reserved */
-	.word	lm3s_reserved		/* Vector 29: Reserved */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
-	.word	lm3s_reserved		/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_reserved		/* Vector 48: Reserved */
-	.word	lm3s_reserved		/* Vector 49: Reserved */
-	.word	lm3s_reserved		/* Vector 50: Reserved */
-	.word	lm3s_reserved		/* Vector 51: Reserved */
-	.word	lm3s_reserved		/* Vector 52: Reserved */
-	.word	lm3s_reserved		/* Vector 53: Reserved */
-	.word	lm3s_reserved		/* Vector 54: Reserved */
-	.word	lm3s_reserved		/* Vector 55: Reserved */
-	.word	lm3s_reserved		/* Vector 56: Reserved */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_reserved		/* Vector 59: Reserved */
-	.word	lm3s_reserved		/* Vector 60: Reserved */
-	.word	lm3s_reserved		/* Vector 61: Reserved */
-	.word	lm3s_reserved		/* Vector 62: Reserved */
-	.word	lm3s_reserved		/* Vector 63: Reserved */
-	.word	lm3s_reserved		/* Vector 64: Reserved */
-	.word	lm3s_reserved		/* Vector 65: Reserved */
-	.word	lm3s_reserved		/* Vector 66: Reserved */
-	.word	lm3s_reserved		/* Vector 67: Reserved */
-	.word	lm3s_reserved		/* Vector 68: Reserved */
-	.word	lm3s_reserved		/* Vector 69: Reserved */
-	.word	lm3s_reserved		/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
-	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
-	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
-	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
-	.word	lm3s_qei0			/* Vector 29: QEI0 */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
-	.word	lm3s_reserved		/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_reserved		/* Vector 48: Reserved */
-	.word	lm3s_uart2			/* Vector 49: UART 2 */
-	.word	lm3s_reserved		/* Vector 50: Reserved */
-	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
-	.word	lm3s_qei1			/* Vector 54: QEI1 */
-	.word	lm3s_reserved		/* Vector 55: Reserved */
-	.word	lm3s_reserved		/* Vector 56: Reserved */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_hib			/* Vector 59: Hibernation Module */
-	.word	lm3s_reserved		/* Vector 60: Reserved */
-	.word	lm3s_reserved		/* Vector 61: Reserved */
-	.word	lm3s_reserved		/* Vector 62: Reserved */
-	.word	lm3s_reserved		/* Vector 63: Reserved */
-	.word	lm3s_reserved		/* Vector 64: Reserved */
-	.word	lm3s_reserved		/* Vector 65: Reserved */
-	.word	lm3s_reserved		/* Vector 66: Reserved */
-	.word	lm3s_reserved		/* Vector 67: Reserved */
-	.word	lm3s_reserved		/* Vector 68: Reserved */
-	.word	lm3s_reserved		/* Vector 69: Reserved */
-	.word	lm3s_reserved		/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
-	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
-	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
-	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
-	.word	lm3s_qei0			/* Vector 29: QEI0 */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_cmp1			/* Vector 42: Analog Comparator 1 */
-	.word	lm3s_cmp2			/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_gpioh			/* Vector 48: GPIO Port H */
-	.word	lm3s_uart2			/* Vector 49: UART 2 */
-	.word	lm3s_ssi1			/* Vector 50: SSI 1 */
-	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm3s_i2c1			/* Vector 53: I2C 1 */
-	.word	lm3s_qei1			/* Vector 54: QEI1 */
-	.word	lm3s_can0			/* Vector 55: CAN 0 */
-	.word	lm3s_can1			/* Vector 56: CAN 1 */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_reserved		/* Vector 59: Reserved */
-	.word	lm3s_usb			/* Vector 60: USB */
-	.word	lm3s_pwm3			/* Vector 61: PWM 3 */
-	.word	lm3s_udmasoft		/* Vector 62: uDMA Software */
-	.word	lm3s_udmaerror		/* Vector 63: uDMA Error */
-	.word	lm3s_adc1_0			/* Vector 64: ADC1 Sequence 0 */
-	.word	lm3s_adc1_1			/* Vector 65: ADC1 Sequence 1 */
-	.word	lm3s_adc1_2			/* Vector 66: ADC1 Sequence 2 */
-	.word	lm3s_adc1_3			/* Vector 67: ADC1 Sequence 3 */
-	.word	lm3s_i2s0 			/* Vector 68: I2S 0 */
-	.word	lm3s_epi			/* Vector 69: Reserved */
-	.word	lm3s_gpioj			/* Vector 70: GPIO J */
-	.word	lm3s_reserved		/* Vector 71: Reserved */
-	#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-	.word	lm3s_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm3s_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm3s_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm3s_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm3s_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm3s_uart0			/* Vector 21: UART 0 */
-	.word	lm3s_uart1			/* Vector 22: UART 1 */
-	.word	lm3s_ssi0			/* Vector 23: SSI 0 */
-	.word	lm3s_i2c0			/* Vector 24: I2C 0 */
-	.word	lm3s_pwmfault		/* Vector 25: PWM Fault */
-	.word	lm3s_pwm0			/* Vector 26: PWM Generator 0 */
-	.word	lm3s_pwm1			/* Vector 27: PWM Generator 1 */
-	.word	lm3s_pwm2			/* Vector 28: PWM Generator 2 */
-	.word	lm3s_qei0			/* Vector 29: QEI0 */
-	.word	lm3s_adc0			/* Vector 30: ADC Sequence 0 */
-	.word	lm3s_adc1			/* Vector 31: ADC Sequence 1 */
-	.word	lm3s_adc2			/* Vector 32: ADC Sequence 2 */
-	.word	lm3s_adc3			/* Vector 33: ADC Sequence 3 */
-	.word	lm3s_wdog			/* Vector 34: Watchdog Timer */
-	.word	lm3s_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm3s_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm3s_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm3s_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm3s_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm3s_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm3s_cmp0			/* Vector 41: Analog Comparator 0 */
-	.word	lm3s_reserved		/* Vector 42: Reserved */
-	.word	lm3s_reserved		/* Vector 43: Reserved */
-	.word	lm3s_syscon			/* Vector 44: System Control */
-	.word	lm3s_flashcon		/* Vector 45: FLASH Control */
-	.word	lm3s_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm3s_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm3s_reserved		/* Vector 48: Reserved */
-	.word	lm3s_reserved		/* Vector 49: Reserved */
-	.word	lm3s_reserved		/* Vector 50: Reserved */
-	.word	lm3s_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm3s_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm3s_reserved		/* Vector 53: Reserved*/
-	.word	lm3s_qei1			/* Vector 54: QEI1 */
-	.word	lm3s_can0			/* Vector 55: Can Controller */
-	.word	lm3s_reserved		/* Vector 56: Reserved */
-	.word	lm3s_reserved		/* Vector 57: Reserved */
- 	.word	lm3s_eth			/* Vector 58: Ethernet Controller */
-	.word	lm3s_hib			/* Vector 59: Hibernation Module */
-	.word	lm3s_reserved		/* Vector 60: Reserved */
-	.word	lm3s_reserved		/* Vector 61: Reserved */
-	.word	lm3s_reserved		/* Vector 62: Reserved */
-	.word	lm3s_reserved		/* Vector 63: Reserved */
-	.word	lm3s_reserved		/* Vector 64: Reserved */
-	.word	lm3s_reserved		/* Vector 65: Reserved */
-	.word	lm3s_reserved		/* Vector 66: Reserved */
-	.word	lm3s_reserved		/* Vector 67: Reserved */
-	.word	lm3s_reserved		/* Vector 68: Reserved */
-	.word	lm3s_reserved		/* Vector 69: Reserved */
-	.word	lm3s_reserved		/* Vector 70: Reserved */
-#else
-#  error "Vectors not specified for this LM3S chip"
-#endif
-	.size	lm3s_vectors, .-lm3s_vectors
-
-/************************************************************************************
- * .text
- ************************************************************************************/
-
-	.text
-	.type	handlers, function
-	.thumb_func
-handlers:
-	HANDLER	lm3s_reserved, LM3S_IRQ_RESERVED		/* Unexpected/reserved vector */
-	HANDLER	lm3s_nmi, LM3S_IRQ_NMI					/* Vector  2: Non-Maskable Interrupt (NMI) */
-	HANDLER	lm3s_hardfault, LM3S_IRQ_HARDFAULT		/* Vector  3: Hard fault */
-	HANDLER	lm3s_mpu, LM3S_IRQ_MEMFAULT				/* Vector  4: Memory management (MPU) */
-	HANDLER	lm3s_busfault, LM3S_IRQ_BUSFAULT		/* Vector  5: Bus fault */
-	HANDLER	lm3s_usagefault, LM3S_IRQ_USAGEFAULT	/* Vector  6: Usage fault */
-	HANDLER	lm3s_svcall, LM3S_IRQ_SVCALL			/* Vector 11: SVC call */
-	HANDLER	lm3s_dbgmonitor, LM3S_IRQ_DBGMONITOR	/* Vector 12: Debug Monitor */
-	HANDLER	lm3s_pendsv, LM3S_IRQ_PENDSV			/* Vector 14: Penable system service request */
-	HANDLER	lm3s_systick, LM3S_IRQ_SYSTICK			/* Vector 15: System tick */
-
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm3s_gpioh, LM3S_IRQ_GPIOH				/* Vector 48: GPIO Port H */
-	HANDLER	lm3s_ssi1, LM3S_IRQ_SSI1				/* Vector 50: SSI 1 */
-	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
- 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
- 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm3s_uart2, LM3S_IRQ_UART1				/* Vector 49: UART 1 */
-	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
- 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm3s_uart2, LM3S_IRQ_UART1				/* Vector 49: UART 1 */
-	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER	lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
-	HANDLER	lm3s_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
- 	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm3s_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-	HANDLER	lm3s_gpioa, LM3S_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm3s_gpiob, LM3S_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm3s_gpioc, LM3S_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm3s_gpiod, LM3S_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm3s_gpioe, LM3S_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm3s_uart0, LM3S_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm3s_uart1, LM3S_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm3s_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm3s_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm3s_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm3s_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm3s_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm3s_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm3s_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm3s_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm3s_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm3s_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm3s_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm3s_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm3s_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm3s_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm3s_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm3s_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm3s_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm3s_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm3s_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm3s_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm3s_cmp2, LM3S_IRQ_COMPARE2			/* Vector 43: Analog Comparator 2 */
-	HANDLER	lm3s_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm3s_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm3s_gpiof, LM3S_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm3s_gpiog, LM3S_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm3s_gpioh, LM3S_IRQ_GPIOH				/* Vector 48: GPIO Port H */
-	HANDLER	lm3s_uart2, LM3S_IRQ_UART2				/* Vector 49: UART 2 */
-	HANDLER	lm3s_ssi1, LM3S_IRQ_SSI1				/* Vector 50: GPIO Port H */
-	HANDLER	lm3s_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm3s_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm3s_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER	lm3s_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
- 	HANDLER	lm3s_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
-	HANDLER	lm3s_can1, LM3S_IRQ_CAN1				/* Vector 56: CAN 1 */
-	HANDLER	lm3s_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
- 	HANDLER	lm3s_usb, LM3S_IRQ_USB					/* Vector 60: USB */
- 	HANDLER	lm3s_pwm3, LM3S_IRQ_PWM3				/* Vector 61: PWM 3  */
- 	HANDLER	lm3s_udmasoft, LM3S_IRQ_UDMASOFT		/* Vector 62: uDMA Software  */
- 	HANDLER	lm3s_udmaerror, LM3S_IRQ_UDMAERROR		/* Vector 63: uDMA Error */
- 	HANDLER	lm3s_adc1_0, LM3S_IRQ_ADC1_0			/* Vector 64: ADC1 Sequence 0 */
- 	HANDLER	lm3s_adc1_1, LM3S_IRQ_ADC1_1			/* Vector 65: ADC1 Sequence 1 */
- 	HANDLER	lm3s_adc1_2, LM3S_IRQ_ADC1_2			/* Vector 66: ADC1 Sequence 2 */
- 	HANDLER	lm3s_adc1_3, LM3S_IRQ_ADC1_3			/* Vector 67: ADC1 Sequence 3 */
- 	HANDLER	lm3s_i2s0, LM3S_IRQ_I2S0				/* Vector 68: I2S 0 */
- 	HANDLER	lm3s_epi, LM3S_IRQ_EPI					/* Vector 69: EPI  */
- 	HANDLER	lm3s_gpioj, LM3S_IRQ_GPIOJ				/* Vector 70: GPIO Port J */
-#else
-#  error "Vectors not specified for this LM3S chip"
-#endif
-
-/* Common IRQ handling logic.  On entry here, the return stack is on either
- * the PSP or the MSP and looks like the following:
- *
- *      REG_XPSR
- *      REG_R15
- *      REG_R14
- *      REG_R12
- *      REG_R3
- *      REG_R2
- *      REG_R1
- * MSP->REG_R0
- *
- * And
- *      R0 contains the IRQ number
- *      R14 Contains the EXC_RETURN value
- *      We are in handler mode and the current SP is the MSP
- */
-
-lm3s_irqcommon:
-
-	/* Complete the context save */
-
-#ifdef CONFIG_NUTTX_KERNEL
-	/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
-	 * (handler mode) if the state is on the MSP.  It can only be on the PSP if
-	 * EXC_RETURN is 0xfffffffd (unprivileged thread)
-	 */
-
-	adds	r2, r14, #3				/* If R14=0xfffffffd, then r2 == 0 */
-	ite		ne						/* Next two instructions are condition */
-	mrsne	r1, msp					/* R1=The main stack pointer */
-	mrseq	r1, psp					/* R1=The process stack pointer */
-#else
-	mrs		r1, msp					/* R1=The main stack pointer */
-#endif
-
-	mov		r2, r1					/* R2=Copy of the main/process stack pointer */
-	add		r2, #HW_XCPT_SIZE		/* R2=MSP/PSP before the interrupt was taken */
-	mrs		r3, primask				/* R3=Current PRIMASK setting */
-#ifdef CONFIG_NUTTX_KERNEL 
-	stmdb	r1!, {r2-r11,r14}		/* Save the remaining registers plus the SP value */
-#else
-	stmdb	r1!, {r2-r11}			/* Save the remaining registers plus the SP value */
-#endif
-
-	/* Disable interrupts, select the stack to use for interrupt handling
-	 * and call up_doirq to handle the interrupt
-	 */
-
-	cpsid	i						/* Disable further interrupts */
-
-	/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
-	 * stack pointer.  The way that this is done here prohibits nested interrupts!
-	 * Otherwise, we will re-use the main stack for interrupt level processing.
-	 */
-
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
-	ldr		sp, =g_intstackbase
-	str		r1, [sp, #-4]!			/* Save the MSP on the interrupt stack */
-	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */
-	ldr		r1, [sp, #+4]!			/* Recover R1=main stack pointer */
-#else
-	mov		sp, r1					/* We are using the main stack pointer */
-	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */
-	mov		r1, sp					/* Recover R1=main stack pointer */
-#endif
-
-	/* On return from up_doirq, R0 will hold a pointer to register context
-	 * array to use for the interrupt return.  If that return value is the same
-	 * as current stack pointer, then things are relatively easy.
-	 */
-
-	cmp		r0, r1					/* Context switch? */
-	beq		1f						/* Branch if no context switch */
-
-	/* We are returning with a pending context switch.  This case is different
-	 * because in this case, the register save structure does not lie on the
-	 * stack but, rather, are within a TCB structure.  We'll have to copy some
-	 * values to the stack.
-	 */
-
-	add		r1, r0, #SW_XCPT_SIZE	/* R1=Address of HW save area in reg array */
-	ldmia	r1, {r4-r11}			/* Fetch eight registers in HW save area */
-	ldr		r1, [r0, #(4*REG_SP)]	/* R1=Value of SP before interrupt */
-	stmdb	r1!, {r4-r11}			/* Store eight registers in HW save area */
-#ifdef CONFIG_NUTTX_KERNEL 
-	ldmia	r0, {r2-r11,r14}		/* Recover R4-R11, r14 + 2 temp values */
-#else
-	ldmia	r0, {r2-r11}			/* Recover R4-R11 + 2 temp values */
-#endif
-	b		2f						/* Re-join common logic */
-
-	/* We are returning with no context switch.  We simply need to "unwind"
-	 * the same stack frame that we created
-	 */
-1:
-#ifdef CONFIG_NUTTX_KERNEL 
-	ldmia	r1!, {r2-r11,r14}		/* Recover R4-R11, r14 + 2 temp values */
-#else
-	ldmia	r1!, {r2-r11}			/* Recover R4-R11 + 2 temp values */
-#endif
-2:
-#ifdef CONFIG_NUTTX_KERNEL
-	/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
-	 * (handler mode) if the state is on the MSP.  It can only be on the PSP if
-	 * EXC_RETURN is 0xfffffffd (unprivileged thread)
-	 */
-
-	adds	r0, r14, #3				/* If R14=0xfffffffd, then r0 == 0 */
-	ite		ne						/* Next two instructions are condition */
-	msrne	msp, r1					/* R1=The main stack pointer */
-	msreq	psp, r1					/* R1=The process stack pointer */
-#else
-	msr		msp, r1					/* Recover the return MSP value */
-
-	/* Preload r14 with the special return value first (so that the return
-	 * actually occurs with interrupts still disabled).
-	 */
-
-	ldr		r14, =EXC_RETURN		/* Load the special value */
-#endif
-
-    /* Restore the interrupt state */
-
-	msr		primask, r3				/* Restore interrupts */
-
-	/* Always return with R14 containing the special value that will: (1)
-	 * return to thread mode, and (2) continue to use the MSP
-	 */
-
-	bx		r14						/* And return */
-	.size	handlers, .-handlers
-
-/************************************************************************************
- *  Name: up_interruptstack/g_intstackbase
- *
- * Description:
- *   Shouldn't happen
- *
- ************************************************************************************/
-
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
-	.bss
-	.global	g_intstackbase
-	.align	4
-up_interruptstack:
-	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
-g_intstackbase:
-	.size	up_interruptstack, .-up_interruptstack
-#endif
-
-/************************************************************************************
- * .rodata
- ************************************************************************************/
-
-	.section	.rodata, "a"
-
-/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
- * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
- * and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE thread is the thread that
- * the system boots on and, eventually, becomes the idle, do nothing task that runs
- * only when there is nothing else to run.  The heap continues from there until the
- * end of memory.  See g_heapbase below.
- */
-
-	.globl	g_heapbase
-	.type	g_heapbase, object
-g_heapbase:
-	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
-	.size	g_heapbase, .-g_heapbase
-
-	.end
diff --git a/nuttx/arch/arm/src/lm/lm_dumpgpio.c b/nuttx/arch/arm/src/lm/lm_dumpgpio.c
new file mode 100644
index 000000000..a3190784b
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_dumpgpio.c
@@ -0,0 +1,167 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_dumpgpio.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lm_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* NOTE: this is duplicated in lm_gpio.c */
+
+#ifdef LM3S_GPIOH_BASE
+static const uint32_t g_gpiobase[8] =
+{
+  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
+  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
+};
+
+static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#else
+static const uint32_t g_gpiobase[8] =
+{
+  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
+  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
+};
+
+static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm_gpiobaseaddress
+ *
+ * Description:
+ *   Given a GPIO enumeration value, return the base address of the
+ *   associated GPIO registers.
+ *
+ ****************************************************************************/
+
+static inline uint32_t lm_gpiobaseaddress(int port)
+{
+  return g_gpiobase[port & 7];
+}
+
+/****************************************************************************
+ * Name: lm_gpioport
+ *
+ * Description:
+ *   Given a GPIO enumeration value, return the base address of the
+ *   associated GPIO registers.
+ *
+ ****************************************************************************/
+
+static inline uint8_t lm_gpioport(int port)
+{
+  return g_portchar[port & 7];
+}
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  lm_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the provided base address
+ *
+ ****************************************************************************/
+
+int lm_dumpgpio(uint32_t pinset, const char *msg)
+{
+  irqstate_t   flags;
+  unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  uint32_t     base;
+  uint32_t     rcgc2;
+  bool         enabled;
+
+  /* Get the base address associated with the GPIO port */
+
+  base = lm_gpiobaseaddress(port);
+  DEBUGASSERT(base != 0);
+
+  /* The following requires exclusive access to the GPIO registers */
+
+  flags   = irqsave();
+  rcgc2   = getreg32(LM3S_SYSCON_RCGC2);
+  enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
+
+  lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
+        lm_gpioport(port), pinset, base, msg);
+  lldbg("  RCGC2: %08x (%s)\n",
+        rcgc2, enabled ? "enabled" : "disabled" );
+
+  /* Don't bother with the rest unless the port is enabled */
+
+  if (enabled)
+    {
+      lldbg("  AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
+            getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET),
+            getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc));
+      lldbg("  IS:    %02x IBE: %02x IEV: %02x IM:  %02x RIS: %08x MIS: %08x\n",
+            getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET),
+            getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET));
+      lldbg("  2MA:   %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
+            getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET),
+            getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET),
+            getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET),
+            getreg32(base + LM3S_GPIO_SLR_OFFSET));
+    }
+  irqrestore(flags);
+  return OK;
+}
diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.c b/nuttx/arch/arm/src/lm/lm_ethernet.c
new file mode 100644
index 000000000..1d8def2e9
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_ethernet.c
@@ -0,0 +1,1472 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_ethernet.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#if defined(CONFIG_NET) && defined(CONFIG_LM_ETHERNET)
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <time.h>
+#include <string.h>
+#include <debug.h>
+#include <wdog.h>
+#include <errno.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+#include <nuttx/net/uip/uip.h>
+#include <nuttx/net/uip/uip-arp.h>
+#include <nuttx/net/uip/uip-arch.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "lm_gpio.h"
+#include "lm_ethernet.h"
+#include "chip/lm_pinmap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Half duplex can be forced if CONFIG_LM_ETHHDUPLEX is defined. */
+
+#ifdef CONFIG_LM_ETHHDUPLEX
+#  define LM3S_DUPLEX_SETBITS 0
+#  define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
+#else 
+#  define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX
+#  define LM3S_DUPLEX_CLRBITS 0
+#endif
+
+/* Auto CRC generation can be suppressed if CONFIG_LM_ETHNOAUTOCRC is definde */
+
+#ifdef CONFIG_LM_ETHNOAUTOCRC
+#  define LM3S_CRC_SETBITS 0
+#  define LM3S_CRC_CLRBITS MAC_TCTL_CRC
+#else 
+#  define LM3S_CRC_SETBITS MAC_TCTL_CRC
+#  define LM3S_CRC_CLRBITS 0
+#endif
+
+/* Tx padding can be suppressed if CONFIG_LM_ETHNOPAD is defined */
+
+#ifdef CONFIG_LM_ETHNOPAD
+#  define LM3S_PADEN_SETBITS 0
+#  define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN
+#else 
+#  define LM3S_PADEN_SETBITS MAC_TCTL_PADEN
+#  define LM3S_PADEN_CLRBITS 0
+#endif
+
+#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS)
+#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS)
+
+/* Multicast frames can be enabled by defining CONFIG_LM_MULTICAST */
+
+#ifdef CONFIG_LM_MULTICAST
+#  define LM3S_AMUL_SETBITS MAC_RCTL_AMUL
+#  define LM3S_AMUL_CLRBITS 0
+#else 
+#  define LM3S_AMUL_SETBITS 0
+#  define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL
+#endif
+
+/* Promiscuous mode can be enabled by defining CONFIG_LM_PROMISCUOUS */
+
+#ifdef CONFIG_LM_PROMISCUOUS
+#  define LM3S_PRMS_SETBITS MAC_RCTL_PRMS
+#  define LM3S_PRMS_CLRBITS 0
+#else 
+#  define LM3S_PRMS_SETBITS 0
+#  define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS
+#endif
+
+/* Bad CRC rejection can be enabled by define CONFIG_LM_BADCRC */
+
+#ifdef CONFIG_LM_BADCRC
+#  define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC
+#  define LM3S_BADCRC_CLRBITS 0
+#else 
+#  define LM3S_BADCRC_SETBITS 0
+#  define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC
+#endif
+
+#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS)
+#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS)
+
+/* CONFIG_LM_DUMPPACKET will dump the contents of each packet to the console. */
+
+#ifdef CONFIG_LM_DUMPPACKET
+#  define lm_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
+#else
+#  define lm_dumppacket(m,a,n)
+#endif
+
+/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
+
+#define LM3S_WDDELAY   (1*CLK_TCK)
+#define LM3S_POLLHSEC  (1*2)
+
+/* TX timeout = 1 minute */
+
+#define LM3S_TXTIMEOUT (60*CLK_TCK)
+
+/* This is a helper pointer for accessing the contents of the Ethernet header */
+
+#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf)
+
+#define LM32S_MAX_MDCCLK 2500000
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* EMAC statistics (debug only) */
+
+#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
+struct lm_statistics_s
+{
+  uint32_t rx_int;         /* Number of Rx interrupts received */
+  uint32_t rx_packets;     /* Number of packets received (sum of the following): */
+  uint32_t rx_ip;          /*   Number of Rx IP packets received */
+  uint32_t rx_arp;         /*   Number of Rx ARP packets received */
+  uint32_t rx_dropped;     /*   Number of dropped, unsupported Rx packets */
+  uint32_t rx_pktsize;     /*   Number of dropped, too small or too big */
+  uint32_t rx_errors;      /* Number of Rx errors (reception error) */
+  uint32_t rx_ovrerrors;   /* Number of Rx FIFO overrun errors */
+  uint32_t tx_int;         /* Number of Tx interrupts received */
+  uint32_t tx_packets;     /* Number of Tx packets queued */
+  uint32_t tx_errors;      /* Number of Tx errors (transmission error)*/
+  uint32_t tx_timeouts;    /* Number of Tx timeout errors */
+};
+#  define EMAC_STAT(priv,name) priv->ld_stat.name++
+#else
+#  define EMAC_STAT(priv,name)
+#endif
+
+/* The lm_driver_s encapsulates all state information for a single hardware
+ * interface
+ */
+
+struct lm_driver_s
+{
+  /* The following fields would only be necessary on chips that support
+   * multiple Ethernet controllers.
+   */
+
+#if LM3S_NETHCONTROLLERS > 1
+  uint32_t ld_base;             /* Ethernet controller base address */
+  int      ld_irq;              /* Ethernet controller IRQ */
+#endif
+
+  bool     ld_bifup;           /* true:ifup false:ifdown */
+  WDOG_ID  ld_txpoll;          /* TX poll timer */
+  WDOG_ID  ld_txtimeout;       /* TX timeout timer */
+
+#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
+  struct lm_statistics_s ld_stat;
+#endif
+
+  /* This holds the information visible to uIP/NuttX */
+
+  struct uip_driver_s ld_dev;  /* Interface understood by uIP */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct lm_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS];
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Miscellaneous low level helpers */
+
+#if LM3S_NETHCONTROLLERS > 1
+static uint32_t lm_ethin(struct lm_driver_s *priv, int offset);
+static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value);
+#else
+static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset);
+static inline void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value);
+#endif
+static void lm_ethreset(struct lm_driver_s *priv);
+#if 0 /* Not used */
+static void lm_phywrite(struct lm_driver_s *priv, int regaddr, uint16_t value);
+#endif
+static uint16_t lm_phyread(struct lm_driver_s *priv, int regaddr);
+
+/* Common TX logic */
+
+static int  lm_transmit(struct lm_driver_s *priv);
+static int  lm_uiptxpoll(struct uip_driver_s *dev);
+
+/* Interrupt handling */
+
+static void lm_receive(struct lm_driver_s *priv);
+static void lm_txdone(struct lm_driver_s *priv);
+static int  lm_interrupt(int irq, FAR void *context);
+
+/* Watchdog timer expirations */
+
+static void lm_polltimer(int argc, uint32_t arg, ...);
+static void lm_txtimeout(int argc, uint32_t arg, ...);
+
+/* NuttX callback functions */
+
+static int  lm_ifup(struct uip_driver_s *dev);
+static int  lm_ifdown(struct uip_driver_s *dev);
+static int  lm_txavail(struct uip_driver_s *dev);
+#ifdef CONFIG_NET_IGMP
+static int  lm_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
+static int  lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: lm_ethin
+ *
+ * Description:
+ *   Read a register from the Ethernet module
+ *
+ * Parameters:
+ *   priv   - Reference to the driver state structure
+ *   offset - Byte offset of the register from the ethernet base address
+ *
+ * Returned Value:
+ *   Register value
+ *
+ ****************************************************************************/
+
+#if LM3S_NETHCONTROLLERS > 1
+static uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
+{
+  return getreg32(priv->ld_base + offset);
+}
+#else
+static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
+{
+  return getreg32(LM3S_ETHCON_BASE + offset);
+}
+#endif
+
+/****************************************************************************
+ * Function: lm_ethout
+ *
+ * Description:
+ *   Write a register to the Ethernet module
+ *
+ * Parameters:
+ *   priv   - Reference to the driver state structure
+ *   offset - Byte offset of the register from the ethernet base address
+ *   value  - The value to write the Ethernet register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if LM3S_NETHCONTROLLERS > 1
+static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, priv->ld_base + offset);
+}
+#else
+static inline void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, LM3S_ETHCON_BASE + offset);
+}
+#endif
+
+/****************************************************************************
+ * Function: lm_ethreset
+ *
+ * Description:
+ *   Configure and reset the Ethernet module, leaving it in a disabled state.
+ *
+ * Parameters:
+ *   priv   - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm_ethreset(struct lm_driver_s *priv)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+#if LM3S_NETHCONTROLLERS > 1
+#  error "If multiple interfaces are supported, this function would have to be redesigned"
+#endif
+
+  /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
+
+  flags   = irqsave();
+  regval  = getreg32(LM3S_SYSCON_RCGC2);
+  regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
+  putreg32(regval, LM3S_SYSCON_RCGC2);
+  nllvdbg("RCGC2: %08x\n", regval);
+
+  /* Put the Ethernet controller into the reset state */
+
+  regval = getreg32(LM3S_SYSCON_SRCR2);
+  regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
+  putreg32(regval, LM3S_SYSCON_SRCR2);
+
+  /* Wait just a bit.  This is a much longer delay than necessary */
+
+  up_mdelay(2);
+
+  /* Then take the Ethernet controller out of the reset state */
+
+  regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
+  putreg32(regval, LM3S_SYSCON_SRCR2);
+  nllvdbg("SRCR2: %08x\n", regval);
+
+  /* Wait just a bit, again.  If we touch the ethernet too soon, we may busfault. */
+
+  up_mdelay(2);
+
+  /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */
+
+#ifdef CONFIG_LM_ETHLEDS
+  /* Configure the pins for the peripheral function */
+
+  lm_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
+  lm_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
+#endif
+
+  /* Disable all Ethernet controller interrupts */
+
+  regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval &= ~MAC_IM_ALLINTS;
+  lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+
+  /* Clear any pending interrupts (shouldn't be any) */
+
+  regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
+  lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Function: lm_phywrite
+ *
+ * Description:
+ *   Write a 16-bit word to a PHY register
+ *
+ * Parameters:
+ *   priv    - Reference to the driver state structure
+ *   regaddr - Address of the PHY register to write
+ *   value   - The value to write to the register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if 0 /* Not used */
+static void lm_phywrite(struct lm_driver_s *priv, int regaddr, uint16_t value)
+{
+  /* Wait for any MII transactions in progress to complete */
+
+  while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+
+  /* Set up the data to be written */
+
+  DEBUGASSERT(value < MAC_MTXD_MASK);
+  lm_ethout(priv, LM3S_MAC_MTXD_OFFSET, value);
+
+  /* Set up the PHY register address and start the write operation */
+
+  regaddr <<= MAC_MCTL_REGADR_SHIFT;
+  DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
+  lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
+
+  /* Wait for the write transaction to complete */
+
+  while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+}
+#endif
+
+/****************************************************************************
+ * Function: lm_phyread
+ *
+ * Description:
+ *   Write a 16-bit word to a PHY register
+ *
+ * Parameters:
+ *   priv    - Reference to the driver state structure
+ *   regaddr - Address of the PHY register to write
+ *   value   - The value to write to the register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static uint16_t lm_phyread(struct lm_driver_s *priv, int regaddr)
+{
+  /* Wait for any MII transactions in progress to complete */
+
+  while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+
+  /* Set up the PHY register address and start the read operation */
+
+  regaddr <<= MAC_MCTL_REGADR_SHIFT;
+  DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
+  lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
+
+  /* Wait for the write transaction to complete */
+
+  while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+
+  /* Read and return the PHY data */
+
+  return (uint16_t)(lm_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
+}
+
+/****************************************************************************
+ * Function: lm_transmit
+ *
+ * Description:
+ *   Start hardware transmission.  Called either from the txdone interrupt
+ *   handling or from watchdog based polling.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int lm_transmit(struct lm_driver_s *priv)
+{
+  irqstate_t flags;
+  uint32_t   regval;
+  uint8_t   *dbuf;
+  int        pktlen;
+  int        bytesleft;
+  int        ret = -EBUSY;
+
+  /* Verify that the hardware is ready to send another packet */
+
+  flags = irqsave();
+  if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+    {
+      /* Increment statistics */
+
+      EMAC_STAT(priv, tx_packets);
+      lm_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
+
+      /* Transfer the packet into the Tx FIFO.  The LS 16-bits of the first
+       * 32-bit word written to the Tx FIFO contains the Ethernet payload
+       * data length.  That is the full length of the message (d_len) minus
+       * the size of the Ethernet header (14).
+       */
+
+      pktlen     = priv->ld_dev.d_len;
+      nllvdbg("Sending packet, pktlen: %d\n", pktlen);
+      DEBUGASSERT(pktlen > UIP_LLH_LEN);
+
+      dbuf       = priv->ld_dev.d_buf;
+      regval     = (uint32_t)(pktlen - 14);
+      regval    |= ((uint32_t)(*dbuf++) << 16);
+      regval    |= ((uint32_t)(*dbuf++) << 24);
+      lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
+
+      /* Write all of the whole, 32-bit values in the middle of the packet */
+
+      for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4)
+        {
+          /* Transfer a whole word from the user buffer.  Note, the user
+           * buffer may be un-aligned.
+           */
+
+          lm_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
+        }
+
+      /* Write the last, partial word in the FIFO */
+
+      if (bytesleft > 0)
+        {
+          /* Write the last word */
+
+          regval = 0;
+          switch (bytesleft)
+            {
+              case 0:
+              default:
+                break;
+
+              case 3:
+                regval |= ((uint32_t)dbuf[2] << 16);
+              case 2:
+                regval |= ((uint32_t)dbuf[1] << 8);
+              case 1:
+                regval |= (uint32_t)dbuf[0];
+                break;
+            }
+          lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
+        }
+
+      /* Activate the transmitter */
+
+      lm_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX);
+
+      /* Setup the TX timeout watchdog (perhaps restarting the timer) */
+
+      (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm_txtimeout, 1, (uint32_t)priv);
+      ret = OK;
+    }
+
+  irqrestore(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Function: lm_uiptxpoll
+ *
+ * Description:
+ *   The transmitter is available, check if uIP has any outgoing packets ready
+ *   to send.  This is a callback from uip_poll().  uip_poll() may be called:
+ *
+ *   1. When the preceding TX packet send is complete,
+ *   2. When the preceding TX packet send timesout and the interface is reset
+ *   3. During normal TX polling
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int lm_uiptxpoll(struct uip_driver_s *dev)
+{
+  struct lm_driver_s *priv = (struct lm_driver_s *)dev->d_private;
+  int ret = OK;
+
+  /* If the polling resulted in data that should be sent out on the network,
+   * the field d_len is set to a value > 0.
+   */
+
+  nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len);
+  if (priv->ld_dev.d_len > 0)
+    {
+      /* Send the packet.  lm_transmit() will return zero if the
+       * packet was successfully handled.
+       */
+
+      DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+      uip_arp_out(&priv->ld_dev);
+      ret = lm_transmit(priv);
+    }
+
+  /* If zero is returned, the polling will continue until all connections have
+   * been examined.
+   */
+
+  return ret;
+}
+
+/****************************************************************************
+ * Function: lm_receive
+ *
+ * Description:
+ *   An interrupt was received indicating the availability of a new RX packet
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm_receive(struct lm_driver_s *priv)
+{
+  uint32_t regval;
+  uint8_t *dbuf;
+  int      pktlen;
+  int      bytesleft;
+
+  /* Loop while there are incoming packets to be processed */
+
+  while ((lm_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
+    {
+      /* Update statistics */
+
+      EMAC_STAT(priv, rx_packets);
+
+      /* Copy the data data from the hardware to priv->ld_dev.d_buf.  Set
+       * amount of data in priv->ld_dev.d_len
+       */
+
+      dbuf = priv->ld_dev.d_buf;
+
+      /* The packet frame length begins in the LS 16-bits of the first
+       * word from the FIFO followed by the Ethernet header beginning
+       * in the MS 16-bits of the first word.
+       *
+       * Pick off the packet length from the first word.  This packet length
+       * includes the len/type field (size 2) and the FCS (size 4).
+       */
+
+      regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
+      pktlen = (int)(regval & 0x0000ffff);
+      nllvdbg("Receiving packet, pktlen: %d\n", pktlen);
+
+      /* Check if the pktlen is valid.  It should be large enough to hold
+       * an Ethernet header and small enough to fit entirely in the I/O
+       * buffer.  Six is subtracted to acount for the 2-byte length/type
+       * and 4 byte FCS that are not copied into the uIP packet.
+       */
+
+      if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6))
+        {
+          int wordlen;
+
+          /* We will have to drop this packet */
+
+          nlldbg("Bad packet size dropped (%d)\n", pktlen);
+          EMAC_STAT(priv, rx_pktsize);
+
+          /* The number of bytes and words left to read is pktlen - 4 (including,
+           * the final, possibly partial word) because we've already read 4 bytes.
+           */
+
+          wordlen = (pktlen - 1) >> 2;
+
+          /* Read and discard the remaining words in the FIFO */
+
+          while (wordlen--)
+            {
+              (void)lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
+            }
+
+          /* Check for another packet */
+
+          continue;
+        }
+
+      /* Save the first two bytes from the first word */
+
+      *dbuf++   = (uint8_t)((regval >> 16) & 0xff);
+      *dbuf++   = (uint8_t)((regval >> 24) & 0xff);
+
+      /* Read all of the whole, 32-bit values in the middle of the packet.
+       * We've already read the length (2 bytes) plus the first two bytes
+       * of data.
+       */
+
+      for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4)
+        {
+          /* Transfer a whole word to the user buffer.  Note, the user
+           * buffer may be un-aligned.
+           */
+
+          *(uint32_t*)dbuf = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
+        }
+
+      /* Handle the last, partial word in the FIFO (0-3 bytes) and discard
+       * the 4-byte FCS.
+       */
+
+      for (; bytesleft > 0; bytesleft -= 4)
+        {
+          /* Read the last word.  And transfer all but the last four
+           * bytes of the FCS into the user buffer.
+           */
+
+          regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
+          switch (bytesleft)
+            {
+              default:
+                break;
+
+              case 7:
+                dbuf[2] = (regval >> 16) & 0xff;
+              case 6:
+                dbuf[1] = (regval >> 8) & 0xff;
+              case 5:
+                dbuf[0] = regval & 0xff;
+                break;
+            }
+        }
+
+      /* Pass the packet length to uIP MINUS 2 bytes for the length and
+       * 4 bytes for the FCS.
+       */
+
+      priv->ld_dev.d_len = pktlen - 6;
+      lm_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
+
+      /* We only accept IP packets of the configured type and ARP packets */
+
+#ifdef CONFIG_NET_IPv6
+      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6))
+#else
+      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP))
+#endif
+        {
+          nllvdbg("IP packet received (%02x)\n", ETHBUF->type);
+          EMAC_STAT(priv, rx_ip);
+
+          uip_arp_ipin(&priv->ld_dev);
+          uip_input(&priv->ld_dev);
+
+          /* If the above function invocation resulted in data that should be
+           * sent out on the network, the field  d_len will set to a value > 0.
+           */
+
+          if (priv->ld_dev.d_len > 0)
+            {
+              uip_arp_out(&priv->ld_dev);
+              lm_transmit(priv);
+            }
+        }
+      else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP))
+        {
+          nllvdbg("ARP packet received (%02x)\n", ETHBUF->type);
+          EMAC_STAT(priv, rx_arp);
+
+          uip_arp_arpin(&priv->ld_dev);
+
+          /* If the above function invocation resulted in data that should be
+           * sent out on the network, the field  d_len will set to a value > 0.
+           */
+
+           if (priv->ld_dev.d_len > 0)
+             {
+               lm_transmit(priv);
+             }
+        }
+#ifdef CONFIG_DEBUG
+      else
+        {
+          nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type));
+          EMAC_STAT(priv, rx_dropped);
+        }
+#endif
+    }
+}
+
+/****************************************************************************
+ * Function: lm_txdone
+ *
+ * Description:
+ *   An interrupt was received indicating that the last TX packet(s) is done
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm_txdone(struct lm_driver_s *priv)
+{
+  /* Cancel the TX timeout */
+
+  wd_cancel(priv->ld_txtimeout);
+
+  /* Verify that the Tx FIFO is not in use.  The NEWTX bit initiates an
+   * Ethernet transmission once the packet has been placed in the TX FIFO.
+   * This bit is cleared once the transmission has been completed.  Since
+   * we get here because of of TXEMP which indicates that the packet was
+   * transmitted and that the TX FIFO is empty, NEWTX should always be zero
+   * at this point.
+   */
+
+  DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+
+  /* Then poll uIP for new XMIT data */
+
+  (void)uip_poll(&priv->ld_dev, lm_uiptxpoll);
+}
+
+/****************************************************************************
+ * Function: lm_interrupt
+ *
+ * Description:
+ *   Hardware interrupt handler
+ *
+ * Parameters:
+ *   irq     - Number of the IRQ that generated the interrupt
+ *   context - Interrupt register state save info (architecture-specific)
+ *
+ * Returned Value:
+ *   OK on success
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int lm_interrupt(int irq, FAR void *context)
+{
+  register struct lm_driver_s *priv;
+  uint32_t ris;
+
+#if LM3S_NETHCONTROLLERS > 1
+# error "A mechanism to associate and interface with an IRQ is needed"
+#else
+  priv = &g_lm3sdev[0];
+#endif
+
+  /* Read the raw interrupt status register */
+
+  ris = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
+
+  /* Clear all pending interrupts */
+
+  lm_ethout(priv, LM3S_MAC_IACK_OFFSET, ris);
+
+  /* Check for errors */
+
+#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET)
+  if ((ris & MAC_RIS_TXER) != 0)
+    {
+      EMAC_STAT(priv, tx_errors);      /* Number of Tx errors */
+    }
+
+  if ((ris & MAC_RIS_FOV) != 0)
+    {
+      EMAC_STAT(priv, rx_ovrerrors);   /* Number of Rx FIFO overrun errors */
+    }
+
+  if ((ris & MAC_RIS_RXER) != 0)
+    {
+      EMAC_STAT(priv, rx_errors);      /* Number of Rx errors */
+    }
+#endif
+
+  /* Handle (unmasked) interrupts according to status bit settings */
+
+  ris &= lm_ethin(priv, LM3S_MAC_IM_OFFSET);
+
+  /* Is this an Rx interrupt (meaning that a packet has been received)? */
+
+  if ((ris & MAC_RIS_RXINT) != 0)
+    {
+      /* Handle the incoming packet */
+
+      EMAC_STAT(priv, rx_int);
+      lm_receive(priv);
+    }
+
+  /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */
+
+  if ((ris & MAC_RIS_TXEMP) != 0)
+    {
+       /* Handle the complete of the transmission */
+
+      EMAC_STAT(priv, tx_int);
+      lm_txdone(priv);
+    }
+
+  /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if 
+   * there are no pending transmissions).
+   */
+
+  return OK;
+}
+
+/****************************************************************************
+ * Function: lm_txtimeout
+ *
+ * Description:
+ *   Our TX watchdog timed out.  Called from the timer interrupt handler.
+ *   The last TX never completed.  Reset the hardware and start again.
+ *
+ * Parameters:
+ *   argc - The number of available arguments
+ *   arg  - The first argument
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm_txtimeout(int argc, uint32_t arg, ...)
+{
+  struct lm_driver_s *priv = (struct lm_driver_s *)arg;
+
+  /* Increment statistics */
+
+  nlldbg("Tx timeout\n");
+  EMAC_STAT(priv, tx_timeouts);
+
+  /* Then reset the hardware */
+
+  DEBUGASSERT(priv->ld_bifup);
+  lm_ifdown(&priv->ld_dev);
+  lm_ifup(&priv->ld_dev);
+
+  /* Then poll uIP for new XMIT data */
+
+  (void)uip_poll(&priv->ld_dev, lm_uiptxpoll);
+}
+
+/****************************************************************************
+ * Function: lm_polltimer
+ *
+ * Description:
+ *   Periodic timer handler.  Called from the timer interrupt handler.
+ *
+ * Parameters:
+ *   argc - The number of available arguments
+ *   arg  - The first argument
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void lm_polltimer(int argc, uint32_t arg, ...)
+{
+  struct lm_driver_s *priv = (struct lm_driver_s *)arg;
+
+  /* Check if we can send another Tx packet now.  The NEWTX bit initiates an
+   * Ethernet transmission once the packet has been placed in the TX FIFO.
+   * This bit is cleared once the transmission has been completed.
+   *
+   * NOTE: This can cause missing poll cycles and, hence, some timing
+   * inaccuracies.
+   */
+
+  if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+    {
+      /* If so, update TCP timing states and poll uIP for new XMIT data */
+
+      (void)uip_timer(&priv->ld_dev, lm_uiptxpoll, LM3S_POLLHSEC);
+
+      /* Setup the watchdog poll timer again */
+
+      (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, arg);
+    }
+}
+
+/****************************************************************************
+ * Function: lm_ifup
+ *
+ * Description:
+ *   NuttX Callback: Bring up the Ethernet interface when an IP address is
+ *   provided 
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int lm_ifup(struct uip_driver_s *dev)
+{
+  struct lm_driver_s *priv = (struct lm_driver_s *)dev->d_private;
+  irqstate_t flags;
+  uint32_t regval;
+  uint32_t div;
+  uint16_t phyreg;
+
+  nlldbg("Bringing up: %d.%d.%d.%d\n",
+       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
+
+  /* Enable and reset the Ethernet controller */
+
+  flags = irqsave();
+  lm_ethreset(priv);
+
+  /* Set the management clock divider register for access to the PHY
+   * register set. The MDC clock is divided down from the system clock per:
+   *
+   *   MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1))
+   *   div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1
+   *
+   * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000.  We will
+   * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded.
+   */
+
+  div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK;
+  lm_ethout(priv, LM3S_MAC_MDV_OFFSET, div);
+  nllvdbg("MDV:   %08x\n", div);
+
+  /* Then configure the Ethernet Controller for normal operation 
+   *
+   * Setup the transmit control register (Full duplex, TX CRC Auto Generation,
+   * TX Padding Enabled).
+   */
+
+  regval  = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET);
+  regval &= ~LM3S_TCTCL_CLRBITS;
+  regval |= LM3S_TCTCL_SETBITS;
+  lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+  nllvdbg("TCTL:  %08x\n", regval);
+
+  /* Setup the receive control register (Disable multicast frames, disable
+   * promiscuous mode, disable bad CRC rejection).
+   */
+
+  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval &= ~LM3S_RCTCL_CLRBITS;
+  regval |= LM3S_RCTCL_SETBITS;
+  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  nllvdbg("RCTL:  %08x\n", regval);
+
+  /* Setup the time stamp configuration register */
+
+#ifdef LM3S_ETHTS
+  regval = lm_ethin(priv, LM3S_MAC_TS_OFFSET);
+#ifdef CONFIG_LM_TIMESTAMP
+  regval |= MAC_TS_EN;
+#else
+  regval &= ~(MAC_TS_EN);
+#endif
+  lm_ethout(priv, LM3S_MAC_TS_OFFSET, regval);
+  nllvdbg("TS:    %08x\n", regval);
+#endif
+
+  /* Wait for the link to come up.  This following is not very conservative
+   * of system resources -- it really should wait gracefully on a semaphore
+   * and the interrupt handler should post the semaphore when LINKSTATUS is
+   * set
+   */
+
+  nlldbg("Waiting for link\n");
+  do
+    {
+      phyreg = lm_phyread(priv, MII_MSR);
+    }
+  while ((phyreg & MII_MSR_LINKSTATUS) == 0);
+  nlldbg("Link established\n");
+
+  /* Reset the receive FIFO */
+
+  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RSTFIFO;
+  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Enable the Ethernet receiver */
+
+  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RXEN;
+  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Enable the Ethernet transmitter */
+
+  regval  = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET);
+  regval |= MAC_TCTL_TXEN;
+  lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+
+  /* Reset the receive FIFO (again) */
+
+  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RSTFIFO;
+  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Enable the Ethernet interrupt */
+
+#if LM3S_NETHCONTROLLERS > 1
+  up_enable_irq(priv->irq);
+#else
+  up_enable_irq(LM3S_IRQ_ETHCON);
+#endif
+
+  /* Enable the Ethernet RX packet receipt interrupt */
+
+  regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval |= MAC_IM_RXINTM;
+  lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+
+  /* Program the hardware with it's MAC address (for filtering) */
+
+  regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 |
+           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 |
+           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 |
+           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0];
+  lm_ethout(priv, LM3S_MAC_IA0_OFFSET, regval);
+
+  regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 |
+           (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4];
+  lm_ethout(priv, LM3S_MAC_IA1_OFFSET, regval);
+
+  /* Set and activate a timer process */
+
+  (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, (uint32_t)priv);
+
+  priv->ld_bifup = true;
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: lm_ifdown
+ *
+ * Description:
+ *   NuttX Callback: Stop the interface.  The only way to restore normal
+ *   behavior is to call lm_ifup().
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int lm_ifdown(struct uip_driver_s *dev)
+{
+  struct lm_driver_s *priv = (struct lm_driver_s *)dev->d_private;
+  irqstate_t flags;
+  uint32_t regval;
+
+  nlldbg("Taking down: %d.%d.%d.%d\n",
+       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
+
+  /* Cancel the TX poll timer and TX timeout timers */
+
+  flags = irqsave();
+  wd_cancel(priv->ld_txpoll);
+  wd_cancel(priv->ld_txtimeout);
+
+  /* Disable the Ethernet interrupt */
+
+#if LM3S_NETHCONTROLLERS > 1
+  up_disable_irq(priv->irq);
+#else
+  up_disable_irq(LM3S_IRQ_ETHCON);
+#endif
+
+  /* Disable all Ethernet controller interrupt sources */
+
+  regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval &= ~MAC_IM_ALLINTS;
+  lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+
+  /* Reset the receive FIFO */
+
+  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RSTFIFO;
+  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Disable the Ethernet receiver */
+
+  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval &= ~MAC_RCTL_RXEN;
+  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Disable the Ethernet transmitter */
+
+  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval &= ~MAC_TCTL_TXEN;
+  lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+
+  /* Reset the receive FIFO (again) */
+
+  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval |= MAC_RCTL_RSTFIFO;
+  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+
+  /* Clear any pending interrupts */
+
+  regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
+  lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
+
+  /* The interface is now DOWN */
+
+  priv->ld_bifup = false;
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: lm_txavail
+ *
+ * Description:
+ *   Driver callback invoked when new TX data is available.  This is a 
+ *   stimulus perform an out-of-cycle poll and, thereby, reduce the TX
+ *   latency.
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Called in normal user mode
+ *
+ ****************************************************************************/
+
+static int lm_txavail(struct uip_driver_s *dev)
+{
+  struct lm_driver_s *priv = (struct lm_driver_s *)dev->d_private;
+  irqstate_t flags;
+
+  /* Ignore the notification if the interface is not yet up or if the Tx FIFO
+   * hardware is not available at this time.  The NEWTX bit initiates an
+   * Ethernet transmission once the packet has been placed in the TX FIFO.
+   * This bit is cleared once the transmission has been completed.  When the
+   * transmission completes, lm_txdone() will be called and the Tx polling
+   * will occur at that time.
+   */
+
+  flags = irqsave();
+  if (priv->ld_bifup && (lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+    {
+      /* If the interface is up and we can use the Tx FIFO, then poll uIP
+       * for new Tx data
+       */
+
+      (void)uip_poll(&priv->ld_dev, lm_uiptxpoll);
+    }
+
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: lm_addmac
+ *
+ * Description:
+ *   NuttX Callback: Add the specified MAC address to the hardware multicast
+ *   address filtering
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *   mac  - The MAC address to be added 
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_IGMP
+static int lm_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
+{
+  FAR struct lm_driver_s *priv = (FAR struct lm_driver_s *)dev->d_private;
+
+  /* Add the MAC address to the hardware multicast routing table */
+
+#warning "Multicast MAC support not implemented"
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Function: lm_rmmac
+ *
+ * Description:
+ *   NuttX Callback: Remove the specified MAC address from the hardware multicast
+ *   address filtering
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *   mac  - The MAC address to be removed 
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_IGMP
+static int lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
+{
+  FAR struct lm_driver_s *priv = (FAR struct lm_driver_s *)dev->d_private;
+
+  /* Add the MAC address to the hardware multicast routing table */
+
+#warning "Multicast MAC support not implemented"
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: lm_ethinitialize
+ *
+ * Description:
+ *   Initialize the Ethernet driver for one interface
+ *
+ * Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#if LM3S_NETHCONTROLLERS > 1
+int lm_ethinitialize(int intf)
+#else
+static inline int lm_ethinitialize(int intf)
+#endif
+{
+  struct lm_driver_s *priv = &g_lm3sdev[intf];
+  int ret;
+
+  /* Check if the Ethernet module is present */
+
+  ndbg("Setting up eth%d\n", intf);
+
+#if LM3S_NETHCONTROLLERS > 1
+# error "This debug check only works with one interface"
+#else
+  DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
+#endif
+  DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS);
+
+  /* Initialize the driver structure */
+
+  memset(priv, 0, sizeof(struct lm_driver_s));
+  priv->ld_dev.d_ifup    = lm_ifup;     /* I/F down callback */
+  priv->ld_dev.d_ifdown  = lm_ifdown;   /* I/F up (new IP address) callback */
+  priv->ld_dev.d_txavail = lm_txavail;  /* New TX data callback */
+#ifdef CONFIG_NET_IGMP
+  priv->ld_dev.d_addmac  = lm_addmac;   /* Add multicast MAC address */
+  priv->ld_dev.d_rmmac   = lm_rmmac;    /* Remove multicast MAC address */
+#endif
+  priv->ld_dev.d_private = (void*)priv; /* Used to recover private state from dev */
+
+  /* Create a watchdog for timing polling for and timing of transmisstions */
+
+#if LM3S_NETHCONTROLLERS > 1
+# error "A mechanism to associate base address an IRQ with an interface is needed"
+  priv->ld_base          = ??;          /* Ethernet controller base address */
+  priv->ld_irq           = ??;          /* Ethernet controller IRQ number */
+#endif
+  priv->ld_txpoll        = wd_create(); /* Create periodic poll timer */
+  priv->ld_txtimeout     = wd_create(); /* Create TX timeout timer */
+
+  /* If the board can provide us with a MAC address, get the address
+   * from the board now.  The MAC will not be applied until lm_ifup()
+   * is caleld (and the MAC can be overwritten with a netdev ioctl call). 
+   */
+
+#ifdef CONFIG_LM_BOARDMAC
+   lm_ethernetmac(&priv->ld_dev.d_mac);
+#endif
+
+  /* Perform minimal, one-time initialization -- just reset the controller and
+   * leave it disabled.  The Ethernet controller will be reset and properly
+   * re-initialized each time lm_ifup() is called.
+   */
+
+  lm_ethreset(priv);
+  lm_ifdown(&priv->ld_dev);
+
+  /* Attach the IRQ to the driver */
+
+#if LM3S_NETHCONTROLLERS > 1
+  ret = irq_attach(priv->irq, lm_interrupt);
+#else
+  ret = irq_attach(LM3S_IRQ_ETHCON, lm_interrupt);
+#endif
+  if (ret != 0)
+    {
+      /* We could not attach the ISR to the IRQ */
+
+      return -EAGAIN;
+    }
+
+  /* Register the device with the OS so that socket IOCTLs can be performed */
+
+  (void)netdev_register(&priv->ld_dev);
+  return OK;
+}
+
+
+/************************************************************************************
+ * Name: up_netinitialize
+ *
+ * Description:
+ *   Initialize the first network interface.  If there are more than one interface
+ *   in the chip, then board-specific logic will have to provide this function to
+ *   determine which, if any, Ethernet controllers should be initialized.
+ *
+ ************************************************************************************/
+
+#if LM3S_NETHCONTROLLERS == 1
+void up_netinitialize(void)
+{
+  (void)lm_ethinitialize(0);
+}
+#endif
+
+#endif /* CONFIG_NET && CONFIG_LM_ETHERNET */
+
diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.h b/nuttx/arch/arm/src/lm/lm_ethernet.h
index 29fe4fd17..e71e9d077 100644
--- a/nuttx/arch/arm/src/lm/lm_ethernet.h
+++ b/nuttx/arch/arm/src/lm/lm_ethernet.h
@@ -74,7 +74,7 @@ extern "C"
  ****************************************************************************/
 
 /****************************************************************************
- * Function: lm3s_ethinitialize
+ * Function: lm_ethinitialize
  *
  * Description:
  *   Initialize the Ethernet driver for one interface.  If the LM3S chip
@@ -92,7 +92,7 @@ extern "C"
  *
  ****************************************************************************/
 
-int lm3s_ethinitialize(int intf);
+int lm_ethinitialize(int intf);
 
 #if defined(__cplusplus)
 }
diff --git a/nuttx/arch/arm/src/lm/lm_gpio.c b/nuttx/arch/arm/src/lm/lm_gpio.c
new file mode 100644
index 000000000..499bf07a2
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_gpio.c
@@ -0,0 +1,854 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_gpio.c
+ * arch/arm/src/chip/lm_gpio.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "lm_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* These definitions are part of the implementation of the  GPIO pad
+ * configuration of Table 9-1 in the LM3S6918 data sheet.
+ */
+
+#define AFSEL_SHIFT            5
+#define AFSEL_1                (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */
+#define AFSEL_0                0
+#define AFSEL_X                0
+
+#define DIR_SHIFT              4
+#define DIR_1                  (1 << DIR_SHIFT)   /* Set/clear bit in GPIO DIR register */
+#define DIR_0                  0
+#define DIR_X                  0
+
+#define ODR_SHIFT              3
+#define ODR_1                  (1 << ODR_SHIFT)   /* Set/clear bit in GPIO ODR register */
+#define ODR_0                  0
+#define ODR_X                  0
+
+#define DEN_SHIFT              2
+#define DEN_1                  (1 << DEN_SHIFT)   /* Set/clear bit in GPIO DEN register */
+#define DEN_0                  0
+#define DEN_X                  0
+
+#define PUR_SHIFT              1
+#define PUR_1                  (1 << PUR_SHIFT)   /* Set/clear bit in GPIO PUR register */
+#define PUR_0                  0
+#define PUR_X                  0
+
+#define PDR_SHIFT              0
+#define PDR_1                  (1 << PDR_SHIFT)   /* Set/clear bit in GPIO PDR register */
+#define PDR_0                  0
+#define PDR_X                  0
+
+#define GPIO_INPUT_SETBITS     (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_INPUT_CLRBITS     (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_OUTPUT_SETBITS    (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_OUTPUT_CLRBITS    (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_ODINPUT_SETBITS   (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_ODINPUT_CLRBITS   (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_ODOUTPUT_SETBITS  (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_ODOUTPUT_CLRBITS  (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_PFODIO_SETBITS    (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_PFODIO_CLRBITS    (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_PFIO_SETBITS      (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_PFIO_CLRBITS      (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X)
+
+#define GPIO_ANINPUT_SETBITS   (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0)
+#define GPIO_ANINPUT_CLRBITS   (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1)
+
+#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X)
+#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct gpio_func_s
+{
+  uint8_t setbits;  /* A set of GPIO register bits to set */
+  uint8_t clrbits;  /* A set of GPIO register bits to clear */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct gpio_func_s g_funcbits[] =
+{
+  {GPIO_INPUT_SETBITS,     GPIO_INPUT_CLRBITS},     /* GPIO_FUNC_INPUT */
+  {GPIO_OUTPUT_SETBITS,    GPIO_OUTPUT_CLRBITS},    /* GPIO_FUNC_OUTPUT */
+  {GPIO_ODINPUT_SETBITS,   GPIO_ODINPUT_CLRBITS},   /* GPIO_FUNC_ODINPUT */
+  {GPIO_ODOUTPUT_SETBITS,  GPIO_ODOUTPUT_CLRBITS},  /* GPIO_FUNC_ODOUTPUT */
+  {GPIO_PFODIO_SETBITS,    GPIO_PFODIO_CLRBITS},    /* GPIO_FUNC_PFODIO */
+  {GPIO_PFIO_SETBITS,      GPIO_PFIO_CLRBITS},      /* GPIO_FUNC_PFIO */
+  {GPIO_ANINPUT_SETBITS,   GPIO_ANINPUT_CLRBITS},   /* GPIO_FUNC_ANINPUT */
+  {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
+};
+
+static const uint32_t g_gpiobase[LM3S_NPORTS] =
+{
+  /* All support LM3S parts have at least 7 ports, GPIOA-G */
+
+  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
+  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE,
+
+  /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
+
+#if LM3S_NPORTS > 7
+  LM3S_GPIOH_BASE,
+#endif
+
+  /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
+
+#if LM3S_NPORTS > 8
+  LM3S_GPIOJ_BASE,
+#endif
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm_gpiobaseaddress
+ *
+ * Description:
+ *   Given a GPIO enumeration value, return the base address of the
+ *   associated GPIO registers.
+ *
+ ****************************************************************************/
+
+static uint32_t lm_gpiobaseaddress(unsigned int port)
+{
+  uint32_t gpiobase = 0;
+  if (port < LM3S_NPORTS)
+    {
+      gpiobase = g_gpiobase[port];
+    }
+  return gpiobase;
+}
+
+/****************************************************************************
+ * Name: lm_gpiofunc
+ *
+ * Description:
+ *   Configure GPIO registers for a specific function
+ *
+ ****************************************************************************/
+
+static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func)
+{
+  uint32_t setbit;
+  uint32_t clrbit;
+  uint32_t regval;
+
+  /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain
+   * control register. Setting a bit in this register enables the open drain
+   * configuration of the corresponding GPIO pad. When open drain mode is enabled,
+   * the corresponding bit should also be set in the GPIO Digital Input Enable
+   * (GPIO DEN) register ... Corresponding bits in the drive strength registers
+   * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the
+   * desired rise and fall times. The GPIO acts as an open drain input if the
+   * corresponding bit in the GPIO DIR register is set to 0; and as an open
+   * drain output when set to 1."
+   */
+
+  setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
+
+  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
+  regval &= ~clrbit;
+  regval |= setbit;
+  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
+
+  /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
+   * register. When a bit is set to 1, it enables a weak pull-up resistor on the
+   * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
+   * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
+   */
+
+  setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno;
+
+  if (setbit || clrbit)
+    {
+      regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
+      regval &= ~clrbit;
+      regval |= setbit;
+      putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
+    }
+
+  /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
+   * register. When a bit is set to 1, it enables a weak pull-down resistor on the
+   * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
+   * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
+   */
+
+  setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno;
+
+  if (setbit || clrbit)
+    {
+      regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
+      regval &= ~clrbit;
+      regval |= setbit;
+      putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
+    }
+
+  /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
+   * register. By default, with the exception of the GPIO signals used for JTAG/SWD
+   * function, all other GPIO signals are configured out of reset to be undriven
+   * (tristate). Their digital function is disabled; they do not drive a logic
+   * value on the pin and they do not allow the pin voltage into the GPIO receiver.
+   * To use the pin in a digital function (either GPIO or alternate function), the
+   * corresponding GPIODEN bit must be set."
+   */
+
+  setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
+
+  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
+  regval &= ~clrbit;
+  regval |= setbit;
+  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
+
+  /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
+   * direction register. Bits set to 1 in the GPIODIR register configure
+   * the corresponding pin to be an output, while bits set to 0 configure the
+   * pins to be inputs. All bits are cleared by a reset, meaning all GPIO
+   * pins are inputs by default.
+   */
+
+  setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
+
+  regval = getreg32(base + LM3S_GPIO_DIR_OFFSET);
+  regval &= ~clrbit;
+  regval |= setbit;
+  putreg32(regval, base + LM3S_GPIO_DIR_OFFSET);
+
+  /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
+   * control select register. Writing a 1 to any bit in this register selects
+   * the hardware control for the corresponding GPIO line. All bits are cleared
+   * by a reset, therefore no GPIO line is set to hardware control by default."
+   *
+   * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit
+   * and unlock the GPIO.  That is not implemented here.
+   */
+
+  setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
+  clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
+
+  regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET);
+  regval &= ~clrbit;
+  regval |= setbit;
+  putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET);
+}
+
+/****************************************************************************
+ * Name: lm_gpiopadstrength
+ *
+ * Description:
+ *   Set up pad strength and pull-ups
+ *
+ ****************************************************************************/
+
+static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset)
+{
+  int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT;
+  uint32_t regoffset;
+  uint32_t regval;
+  uint32_t slrset;
+  uint32_t slrclr;
+
+  /* Prepare bits to disable slew */
+
+  slrset = 0;
+  slrclr = pin;
+
+  switch (strength)
+    {
+      case 0: /* 2mA pad drive strength */
+        {
+          /* "The GPIODR2R register is the 2-mA drive control register. It
+           * allows for each GPIO signal in the port to be individually configured
+           * without affecting the other pads. When writing a DRV2 bit for a GPIO
+           * signal, the corresponding DRV4 bit in the GPIO DR4R register and the
+           * DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
+           */
+
+          regoffset = LM3S_GPIO_DR2R_OFFSET;
+        }
+        break;
+
+      case 1: /* 4mA pad drive strength */
+        {
+          /* "The GPIODR4R register is the 4-mA drive control register. It allows
+           * for each GPIO signal in the port to be individually configured without
+           * affecting the other pads. When writing the DRV4 bit for a GPIO signal,
+           * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit
+           * in the GPIO DR8R register are automatically cleared by hardware."
+           */
+
+          regoffset = LM3S_GPIO_DR4R_OFFSET;
+        }
+        break;
+
+      case 3: /* 8mA Pad drive with slew rate control */
+        {
+          /* "The GPIOSLR register is the slew rate control register. Slew rate
+           * control is only available when using the 8-mA drive strength option
+           * via the GPIO 8-mA Drive Select (GPIODR8R) register..."
+           */
+
+          slrset = pin;
+          slrclr = 0;
+        }
+        /* Fall through */
+
+      case 2: /* 8mA pad drive strength (without slew rate control) */
+        {
+          /* "The GPIODR8R register is the 8-mA drive control register. It
+           * allows for each GPIO signal in the port to be individually configured
+           * without affecting the other pads. When writing the DRV8 bit for a GPIO
+           * signal, the corresponding DRV2 bit in the GPIO DR2R register and the
+           * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
+           */
+
+          regoffset = LM3S_GPIO_DR8R_OFFSET;
+        }
+        break;
+    }
+
+  /* Set the selected pad strength and set/clear optional slew rate control */
+
+  regval = getreg32(base + regoffset);
+  regval |= pin;
+  putreg32(regval, base + regoffset);
+
+  regval  = getreg32(base + LM3S_GPIO_SLR_OFFSET);
+  regval &= slrclr;
+  regval |= slrset;
+  putreg32(regval, base + LM3S_GPIO_SLR_OFFSET);
+}
+
+/****************************************************************************
+ * Name: lm_gpiopadtype
+ *
+ * Description:
+ *   Set up pad strength and pull-ups.  Some of these values may be over-
+ *   written by lm_gpiofunc, depending on the function selection.  Others
+ *   are optional for different function selections.
+ *
+ ****************************************************************************/
+
+static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
+{
+  int padtype  = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT;
+#if 0 /* always overwritten by lm_gpiofunc */
+  uint32_t odrset;
+  uint32_t odrclr;
+#endif
+  uint32_t purset;
+  uint32_t purclr;
+  uint32_t pdrset;
+  uint32_t pdrclr;
+#if 0 /* always overwritten by lm_gpiofunc */
+  uint32_t denset;
+  uint32_t denclr;
+#endif
+  uint32_t regval;
+
+  /* Assume digital GPIO function, push-pull with no pull-up or pull-down */
+
+#if 0 /* always overwritten by lm_gpiofunc */
+  odrset = 0;
+  odrclr = pin;
+#endif
+  purset = 0;
+  purclr = pin;
+  pdrset = 0;
+  pdrclr = pin;
+#if 0 /* always overwritten by lm_gpiofunc */
+  denset = pin;
+  denclr = 0;
+#endif
+
+  switch (padtype)
+    {
+      case 0: /* Push-pull */
+      default:
+        {
+        }
+        break;
+
+      case 1: /* Push-pull with weak pull-up */
+        {
+          purset = pin;
+          purclr = 0;
+        }
+        break;
+      case 2: /* Push-pull with weak pull-down */
+        {
+          pdrset = pin;
+          pdrclr = 0;
+        }
+        break;
+      case 3: /* Open-drain */
+        {
+#if 0 /* always overwritten by lm_gpiofunc */
+          odrset = pin;
+          odrclr = 0;
+#endif
+        }
+        break;
+      case 4: /* Open-drain with weak pull-up */
+        {
+#if 0 /* always overwritten by lm_gpiofunc */
+          odrset = pin;
+          odrclr = 0;
+#endif
+          purset = pin;
+          purclr = 0;
+        }
+        break;
+      case 5: /* Open-drain with weak pull-down */
+        {
+#if 0 /* always overwritten by lm_gpiofunc */
+          odrset = pin;
+          odrclr = 0;
+#endif
+          pdrset = pin;
+          pdrclr = 0;
+        }
+        break;
+      case 6: /* Analog comparator */
+        {
+#if 0 /* always overwritten by lm_gpiofunc */
+          denset = 0;
+          denclr = pin;
+#endif
+        }
+        break;
+    }
+
+  /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain
+   * control register. Setting a bit in this register enables the open drain
+   * configuration of the corresponding GPIO pad. When open drain mode is enabled,
+   * the corresponding bit should also be set in the GPIO Digital Input Enable
+   * (GPIO DEN) register ... Corresponding bits in the drive strength registers
+   * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the
+   * desired rise and fall times. The GPIO acts as an open drain input if the
+   * corresponding bit in the GPIO DIR register is set to 0; and as an open
+   * drain output when set to 1."
+   */
+
+#if 0 /* always overwritten by lm_gpiofunc */
+  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
+  regval &= ~odrclr;
+  regval |= odrset;
+  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
+#endif
+
+  /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
+   * register. When a bit is set to 1, it enables a weak pull-up resistor on the
+   * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
+   * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
+   */
+
+  regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
+  regval &= ~purclr;
+  regval |= purset;
+  putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
+
+  /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
+   * register. When a bit is set to 1, it enables a weak pull-down resistor on the
+   * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
+   * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
+   */
+
+  regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
+  regval &= ~pdrclr;
+  regval |= pdrset;
+  putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
+
+  /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
+   * register. By default, with the exception of the GPIO signals used for JTAG/SWD
+   * function, all other GPIO signals are configured out of reset to be undriven
+   * (tristate). Their digital function is disabled; they do not drive a logic
+   * value on the pin and they do not allow the pin voltage into the GPIO receiver.
+   * To use the pin in a digital function (either GPIO or alternate function), the
+   * corresponding GPIODEN bit must be set."
+   */
+
+#if 0 /* always overwritten by lm_gpiofunc */
+  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
+  regval &= ~denclr;
+  regval |= denset;
+  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
+#endif
+}
+
+/****************************************************************************
+ * Name: lm_initoutput
+ *
+ * Description:
+ *   Set the GPIO output value
+ *
+ ****************************************************************************/
+
+static inline void lm_initoutput(uint32_t cfgset)
+{
+  bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO);
+  lm_gpiowrite(cfgset, value);
+}
+
+/****************************************************************************
+ * Name: lm_interrupt
+ *
+ * Description:
+ *   Configure the interrupt pin.
+ *
+ ****************************************************************************/
+
+static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
+{
+  int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT;
+  uint32_t regval;
+  uint32_t isset;
+  uint32_t isclr;
+  uint32_t ibeset;
+  uint32_t ibeclr;
+  uint32_t iveset;
+  uint32_t iveclr;
+
+  /* Mask and clear the GPIO interrupt
+   *
+   * "The GPIOIM register is the interrupt mask register. Bits set to High in
+   * GPIO IM allow the corresponding pins to trigger their individual interrupts
+   * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering
+   * on that pin. All bits are cleared by a reset."
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+  regval &= ~pin;
+  putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+
+  /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
+   * in this register clears the corresponding interrupt edge detection logic
+   * register. Writing a 0 has no effect."
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_ICR_OFFSET);
+  regval |= pin;
+  putreg32(regval, base + LM3S_GPIO_ICR_OFFSET);
+
+  /* Assume rising edge */
+
+  isset  = 0;            /* Not level sensed */
+  isclr  = pin;
+  ibeset = 0;            /* Single edge */
+  ibeclr = pin;
+  iveset = pin;          /* Rising edge or high levels*/
+  iveclr = 0;
+
+  /* Then handle according to the selected interrupt type */
+
+  switch (inttype)
+    {
+      case 0:            /* Interrupt on falling edge */
+        {
+          iveset = 0;    /* Falling edge or low levels*/
+          iveclr = pin;
+        }
+        break;
+
+      case 1:           /* Interrupt on rising edge */
+      default:
+        break;
+
+      case 2:           /* Interrupt on both edges */
+        {
+          ibeset = pin; /* Both edges */
+          ibeclr = 0;
+        }
+        break;
+
+      case 3:           /* Interrupt on low level */
+        {
+          isset = pin;  /* Level sensed */
+          isclr = 0;
+          iveset = 0;   /* Falling edge or low levels*/
+          iveclr = pin;
+        }
+        break;
+
+      case 4:           /* Interrupt on high level */
+        {
+          isset = pin;  /* Level sensed */
+          isclr = 0;
+        }
+        break;
+    }
+
+  /* "The GPIO IS register is the interrupt sense register. Bits set to
+   * 1 in GPIOIS configure the corresponding pins to detect levels, while
+   * bits set to 0 configure the pins to detect edges. All bits are cleared
+   * by a reset.
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_IS_OFFSET);
+  regval &= isclr;
+  regval |= isset;
+  putreg32(regval, base + LM3S_GPIO_IS_OFFSET);
+
+  /* "The GPIO IBE register is the interrupt both-edges register. When the
+   * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
+   * set to detect edges, bits set to High in GPIO IBE configure the
+   * corresponding pin to detect both rising and falling edges, regardless
+   * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ...
+   * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits
+   * are cleared by a reset.
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_IBE_OFFSET);
+  regval &= ibeclr;
+  regval |= ibeset;
+  putreg32(regval, base + LM3S_GPIO_IBE_OFFSET);
+
+  /* "The GPIOIEV register is the interrupt event register. Bits set to
+   * High in GPIO IEV configure the corresponding pin to detect rising edges
+   * or high levels, depending on the corresponding bit value in the GPIO
+   * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to
+   * detect falling edges or low levels, depending on the corresponding bit
+   * value in GPIOIS. All bits are cleared by a reset.
+   */
+
+  regval  = getreg32(base + LM3S_GPIO_IEV_OFFSET);
+  regval &= iveclr;
+  regval |= iveset;
+  putreg32(regval, base + LM3S_GPIO_IEV_OFFSET);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int lm_configgpio(uint32_t cfgset)
+{
+  irqstate_t   flags;
+  unsigned int func;
+  unsigned int port;
+  unsigned int pinno;
+  uint32_t     pin;
+  uint32_t     base;
+  uint32_t     regval;
+
+  /* Decode the basics */
+
+  func  = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT;
+  port  = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  pinno = (cfgset & GPIO_NUMBER_MASK);
+  pin   = (1 <<pinno);
+
+  DEBUGASSERT(func <= GPIO_FUNC_MAX);
+
+  /* Get the base address associated with the GPIO port */
+
+  base = lm_gpiobaseaddress(port);
+  DEBUGASSERT(base != 0);
+
+  /* The following requires exclusive access to the GPIO registers */
+
+  flags = irqsave();
+
+  /* Enable clocking for this GPIO peripheral. "To use the GPIO, the peripheral
+   * clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn)
+   * in the RCGC2 register."
+   */
+
+  regval = getreg32(LM3S_SYSCON_RCGC2);
+  regval |= SYSCON_RCGC2_GPIO(port);
+  putreg32(regval, LM3S_SYSCON_RCGC2);
+
+  /* First, set the port to digital input.  This is the safest state in which
+   * to perform reconfiguration.
+   */
+
+  lm_gpiofunc(base, pinno, &g_funcbits[0]);
+
+  /* Then set up pad strengths and pull-ups.  These setups should be done before
+   * setting up the function because some function settings will over-ride these
+   * user options.
+   */
+
+  lm_gpiopadstrength(base, pin, cfgset);
+  lm_gpiopadtype(base, pin, cfgset);
+
+  /* Then set up the real pin function */
+
+  lm_gpiofunc(base, pinno, &g_funcbits[func]);
+
+  /* Special GPIO digital output pins */
+
+  if (func == 1 || func == 3)
+    {
+      lm_initoutput(cfgset);
+    }
+
+
+  /* Special setup for interrupt GPIO pins */
+
+  else if (func == 7)
+    {
+      lm_interrupt(base, pin, cfgset);
+    }
+
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: lm_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void lm_gpiowrite(uint32_t pinset, bool value)
+{
+  unsigned int port;
+  unsigned int pinno;
+  uint32_t     base;
+
+  /* Decode the basics */
+
+  port  = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  pinno = (pinset & GPIO_NUMBER_MASK);
+
+  /* Get the base address associated with the GPIO port */
+
+  base  = lm_gpiobaseaddress(port);
+
+  /* "The GPIO DATA register is the data register. In software control mode,
+   *  values written in the GPIO DATA register are transferred onto the GPIO
+   *  port pins if the respective pins have been configured as outputs through
+   *  the GPIO Direction (GPIO DIR) register ...
+   *
+   * "In order to write to GPIO DATA, the corresponding bits in the mask,
+   *  resulting from the address bus bits [9:2], must be High. Otherwise, the
+   *  bit values remain unchanged by the write. 
+   *
+   * "... All bits are cleared by a reset."
+   */
+
+  putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
+}
+
+/****************************************************************************
+ * Name: lm_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool lm_gpioread(uint32_t pinset, bool value)
+{
+  unsigned int port;
+  unsigned int pinno;
+  uint32_t     base;
+
+  /* Decode the basics */
+
+  port  = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  pinno = (pinset & GPIO_NUMBER_MASK);
+
+  /* Get the base address associated with the GPIO port */
+
+  base = lm_gpiobaseaddress(port);
+
+  /* "... the values read from this register are determined for each bit
+   *  by the mask bit derived from the address used to access the data register,
+   *  bits [9:2]. Bits that are 1 in the address mask cause the corresponding
+   *  bits in GPIODATA to be read, and bits that are 0 in the address mask cause
+   *  the corresponding bits in GPIO DATA to be read as 0, regardless of their
+   *  value.
+   *
+   * "A read from GPIO DATA returns the last bit value written if the respective
+   *  pins are configured as outputs, or it returns the value on the
+   *  corresponding input pin when these are configured as inputs. All bits
+   *  are cleared by a reset."
+   */
+
+  return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
+}
+
diff --git a/nuttx/arch/arm/src/lm/lm_gpio.h b/nuttx/arch/arm/src/lm/lm_gpio.h
index 9577fd926..1447eb065 100644
--- a/nuttx/arch/arm/src/lm/lm_gpio.h
+++ b/nuttx/arch/arm/src/lm/lm_gpio.h
@@ -53,7 +53,7 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
-/* Bit-encoded input to lm3s_configgpio() *******************************************/
+/* Bit-encoded input to lm_configgpio() *********************************************/
 
 /* Encoding:
  * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB
@@ -161,57 +161,57 @@ extern "C"
 {
 #endif
 
-/****************************************************************************
+/************************************************************************************
  * Public Function Prototypes
- ****************************************************************************/
+ ************************************************************************************/
 
-/****************************************************************************
- * Name: lm3s_configgpio
+/************************************************************************************
+ * Name: lm_configgpio
  *
  * Description:
  *   Configure a GPIO pin based on bit-encoded description of the pin.
  *
- ****************************************************************************/
+ ************************************************************************************/
 
-int lm3s_configgpio(uint32_t cfgset);
+int lm_configgpio(uint32_t cfgset);
 
-/****************************************************************************
- * Name: lm3s_gpiowrite
+/************************************************************************************
+ * Name: lm_gpiowrite
  *
  * Description:
  *   Write one or zero to the selected GPIO pin
  *
- ****************************************************************************/
+ ************************************************************************************/
 
-void lm3s_gpiowrite(uint32_t pinset, bool value);
+void lm_gpiowrite(uint32_t pinset, bool value);
 
-/****************************************************************************
- * Name: lm3s_gpioread
+/************************************************************************************
+ * Name: lm_gpioread
  *
  * Description:
  *   Read one or zero from the selected GPIO pin
  *
- ****************************************************************************/
+ ************************************************************************************/
 
-bool lm3s_gpioread(uint32_t pinset, bool value);
+bool lm_gpioread(uint32_t pinset, bool value);
 
-/****************************************************************************
- * Function:  lm3s_dumpgpio
+/************************************************************************************
+ * Function:  lm_dumpgpio
  *
  * Description:
  *   Dump all GPIO registers associated with the provided base address
  *
- ****************************************************************************/
+ ************************************************************************************/
 
-int lm3s_dumpgpio(uint32_t pinset, const char *msg);
+int lm_dumpgpio(uint32_t pinset, const char *msg);
 
-/****************************************************************************
+/************************************************************************************
  * Name: gpio_irqinitialize
  *
  * Description:
  *   Initialize all vectors to the unexpected interrupt handler
  *
- ****************************************************************************/
+ ************************************************************************************/
 
 int weak_function gpio_irqinitialize(void);
 
diff --git a/nuttx/arch/arm/src/lm/lm_gpioirq.c b/nuttx/arch/arm/src/lm/lm_gpioirq.c
new file mode 100644
index 000000000..f77f878de
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_gpioirq.c
@@ -0,0 +1,434 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_gpioirq.c
+ * arch/arm/src/chip/lm_gpioirq.c
+ *
+ *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "irq_internal.h"
+
+#include "lm_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* A table of handlers for each GPIO interrupt */
+
+static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
+
+/* A table that maps a GPIO group to a GPIO base address.  Overly complicated
+ * because we support disabling interrupt support for arbitrary ports.  This
+ * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h
+ */
+
+static const uint32_t g_gpiobase[] =
+{
+#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
+   LM3S_GPIOA_BASE,
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
+  LM3S_GPIOB_BASE,
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
+  LM3S_GPIOC_BASE,
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
+  LM3S_GPIOD_BASE,
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
+  LM3S_GPIOE_BASE,
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
+  LM3S_GPIOF_BASE,
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
+  LM3S_GPIOG_BASE,
+#endif
+
+  /* NOTE: Not all LM3S architectures support GPIOs above GPIOG.  If the chip
+   * does not support these higher ports, then they must be disabled in the
+   * configuration.  Otherwise, the following will likely cause compilation
+   * errors!
+   */
+
+#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
+  LM3S_GPIOH_BASE,
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
+  LM3S_GPIOJ_BASE,
+#endif
+};
+
+#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t))
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm_gpiobaseaddress
+ *
+ * Input:
+ *   gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS.
+ *
+ * Description:
+ *   Given a GPIO enumeration value, return the base address of the
+ *   associated GPIO registers.  NOTE that range checking was provided by
+ *   callee
+ *
+ ****************************************************************************/
+
+static uint32_t lm_gpiobaseaddress(unsigned int gpioirq)
+{
+  unsigned int ndx = gpioirq >> 3;
+  if (ndx < GPIO_NADDRS)
+    {
+      return g_gpiobase[ndx];
+    }
+  return 0;
+}
+
+/****************************************************************************
+ * Name: lm_gpio*handler
+ *
+ * Description:
+ *   Handle interrupts on each enabled GPIO port
+ *
+ ****************************************************************************/
+
+static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
+{
+  uint32_t mis;
+  int irq;
+  int pin;
+
+  /* Handle each pending GPIO interrupt.  "The GPIO MIS register is the masked
+   * interrupt status register. Bits read High in GPIO MIS reflect the status
+   * of input lines triggering an interrupt. Bits read as Low indicate that
+   * either no interrupt has been generated, or the interrupt is masked."
+   */
+
+  mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff;
+
+  /* Clear all GPIO interrupts that we are going to process.  "The GPIO ICR
+   * register is the interrupt clear register. Writing a 1 to a bit in this
+   * register clears the corresponding interrupt edge detection logic register.
+   * Writing a 0 has no effect."
+   */
+
+  putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET);
+
+  /* Now process each IRQ pending in the MIS */
+
+  for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1)
+    {
+      if ((mis & 1) != 0)
+        {
+          irq = irqbase + pin;
+          g_gpioirqvector[irq - NR_IRQS](irq, context);
+        }
+    }
+  return OK;
+}
+
+#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
+static int lm_gpioahandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
+static int lm_gpiobhandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
+static int lm_gpiochandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
+static int lm_gpiodhandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
+static int lm_gpioehandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
+static int lm_gpiofhandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
+static int lm_gpioghandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
+static int lm_gpiohhandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
+}
+#endif
+
+#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
+static int lm_gpiojhandler(int irq, FAR void *context)
+{
+  return lm_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: gpio_irqinitialize
+ *
+ * Description:
+ *   Initialize all vectors to the unexpected interrupt handler
+ *
+ ****************************************************************************/
+
+int gpio_irqinitialize(void)
+{
+  int i;
+
+  /* Point all interrupt vectors to the unexpected interrupt */
+
+  for (i = 0; i < NR_GPIO_IRQS; i++)
+    {
+      g_gpioirqvector[i] = irq_unexpected_isr;
+    }
+
+  /* Then attach each GPIO interrupt handlers and enable corresponding GPIO
+   * interrupts
+   */
+
+#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
+  irq_attach(LM3S_IRQ_GPIOA, lm_gpioahandler);
+  up_enable_irq(LM3S_IRQ_GPIOA);
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
+  irq_attach(LM3S_IRQ_GPIOB, lm_gpiobhandler);
+  up_enable_irq(LM3S_IRQ_GPIOB);
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
+  irq_attach(LM3S_IRQ_GPIOC, lm_gpiochandler);
+  up_enable_irq(LM3S_IRQ_GPIOC);
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
+  irq_attach(LM3S_IRQ_GPIOD, lm_gpiodhandler);
+  up_enable_irq(LM3S_IRQ_GPIOD);
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
+  irq_attach(LM3S_IRQ_GPIOE, lm_gpioehandler);
+  up_enable_irq(LM3S_IRQ_GPIOE);
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
+  irq_attach(LM3S_IRQ_GPIOF, lm_gpiofhandler);
+  up_enable_irq(LM3S_IRQ_GPIOF);
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
+  irq_attach(LM3S_IRQ_GPIOG, lm_gpioghandler);
+  up_enable_irq(LM3S_IRQ_GPIOG);
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
+  irq_attach(LM3S_IRQ_GPIOH, lm_gpiohhandler);
+  up_enable_irq(LM3S_IRQ_GPIOH);
+#endif
+#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
+  irq_attach(LM3S_IRQ_GPIOJ, lm_gpiojhandler);
+  up_enable_irq(LM3S_IRQ_GPIOJ);
+#endif
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: gpio_irqattach
+ *
+ * Description:
+ *   Attach in GPIO interrupt to the provide 'isr'
+ *
+ ****************************************************************************/
+
+int gpio_irqattach(int irq, xcpt_t isr)
+{
+  irqstate_t flags;
+  int        gpioirq = irq - NR_IRQS;
+  int        ret     = ERROR;
+
+  if ((unsigned)gpioirq < NR_GPIO_IRQS)
+    {
+      flags = irqsave();
+
+      /* If the new ISR is NULL, then the ISR is being detached.
+       * In this case, disable the ISR and direct any interrupts
+       * to the unexpected interrupt handler.
+       */
+
+      if (isr == NULL)
+        {
+#ifndef CONFIG_ARCH_NOINTC
+           gpio_irqdisable(gpioirq);
+#endif
+           isr = irq_unexpected_isr;
+        }
+
+      /* Save the new ISR in the table. */
+
+      g_irqvector[gpioirq] = isr;
+      irqrestore(flags);
+      ret = OK;
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: gpio_irqenable
+ *
+ * Description:
+ *   Enable the GPIO IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void gpio_irqenable(int irq)
+{
+  irqstate_t flags;
+  int        gpioirq = irq - NR_IRQS;
+  uint32_t   base;
+  uint32_t   regval;
+  int        pin;
+
+  if ((unsigned)gpioirq < NR_GPIO_IRQS)
+    {
+      /* Get the base address of the GPIO module associated with this IRQ */
+
+      base = lm_gpiobaseaddress(gpioirq);
+      DEBUGASSERT(base != 0);
+      pin  = (1 << (gpioirq & 7));
+
+      /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
+       * mask register. Bits set to High in GPIO IM allow the corresponding
+       * pins to trigger their individual interrupts and the combined GPIO INTR
+       * line. Clearing a bit disables interrupt triggering on that pin. All
+       * bits are cleared by a reset.
+       */
+
+      flags   = irqsave();
+      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+      regval |= pin;
+      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+      irqrestore(flags);
+    }
+}
+
+/****************************************************************************
+ * Name: gpio_irqdisable
+ *
+ * Description:
+ *   Disable the GPIO IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void gpio_irqdisable(int irq)
+{
+  irqstate_t flags;
+  int        gpioirq = irq - NR_IRQS;
+  uint32_t   base;
+  uint32_t   regval;
+  int        pin;
+
+  if ((unsigned)gpioirq < NR_GPIO_IRQS)
+    {
+      /* Get the base address of the GPIO module associated with this IRQ */
+
+      base = lm_gpiobaseaddress(gpioirq);
+      DEBUGASSERT(base != 0);
+      pin  = (1 << (gpioirq & 7));
+
+      /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
+       * mask register. Bits set to High in GPIO IM allow the corresponding
+       * pins to trigger their individual interrupts and the combined GPIO INTR
+       * line. Clearing a bit disables interrupt triggering on that pin. All
+       * bits are cleared by a reset.
+       */
+
+      flags   = irqsave();
+      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+      regval &= ~pin;
+      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+      irqrestore(flags);
+    }
+}
+
diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c
new file mode 100644
index 000000000..700944202
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_irq.c
@@ -0,0 +1,458 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_irq.c
+ * arch/arm/src/chip/lm_irq.c
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "nvic.h"
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+#include "chip.h"
+#include "lm_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Enable NVIC debug features that are probably only desireable during
+ * bringup
+ */
+
+#undef LM3S_IRQ_DEBUG
+
+/* Get a 32-bit version of the default priority */
+
+#define DEFPRIORITY32 \
+  (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
+   NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
+   NVIC_SYSH_PRIORITY_DEFAULT << 8  |\
+   NVIC_SYSH_PRIORITY_DEFAULT)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+volatile uint32_t *current_regs;
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm_dumpnvic
+ *
+ * Description:
+ *   Dump some interesting NVIC registers
+ *
+ ****************************************************************************/
+
+#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
+static void lm_dumpnvic(const char *msg, int irq)
+{
+  irqstate_t flags;
+
+  flags = irqsave();
+  slldbg("NVIC (%s, irq=%d):\n", msg, irq);
+  slldbg("  INTCTRL:    %08x VECTAB: %08x\n",
+         getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+#if 0
+  slldbg("  SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+         getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+         getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+#endif
+  slldbg("  IRQ ENABLE: %08x %08x\n",
+         getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
+  slldbg("  SYSH_PRIO:  %08x %08x %08x\n",
+         getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+         getreg32(NVIC_SYSH12_15_PRIORITY));
+  slldbg("  IRQ PRIO:   %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+        getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+        getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+        getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+  irqrestore(flags);
+}
+#else
+#  define lm_dumpnvic(msg, irq)
+#endif
+
+/****************************************************************************
+ * Name: lm_nmi, lm_busfault, lm_usagefault, lm_pendsv,
+ *       lm_dbgmonitor, lm_pendsv, lm_reserved
+ *
+ * Description:
+ *   Handlers for various execptions.  None are handled and all are fatal
+ *   error conditions.  The only advantage these provided over the default
+ *   unexpected interrupt handler is that they provide a diagnostic output.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+static int lm_nmi(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! NMI received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm_busfault(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Bus fault recived\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm_usagefault(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Usage fault received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm_pendsv(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! PendSV received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm_dbgmonitor(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Debug Monitor receieved\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lm_reserved(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Reserved interrupt\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: lm_irqinfo
+ *
+ * Description:
+ *   Given an IRQ number, provide the register and bit setting to enable or
+ *   disable the irq.
+ *
+ ****************************************************************************/
+
+static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
+{
+  DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS);
+
+  /* Check for external interrupt */
+
+  if (irq >= LM3S_IRQ_INTERRUPTS)
+    {
+      if (irq < LM3S_IRQ_INTERRUPTS + 32)
+        {
+           *regaddr = NVIC_IRQ0_31_ENABLE;
+           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS);
+        }
+      else if (irq < NR_IRQS)
+        {
+           *regaddr = NVIC_IRQ32_63_ENABLE;
+           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
+        }
+      else
+        {
+          return ERROR; /* Invalid interrupt */
+        }
+    }
+
+  /* Handler processor exceptions.  Only a few can be disabled */
+
+  else
+    {
+       *regaddr = NVIC_SYSHCON;
+       if (irq == LM3S_IRQ_MEMFAULT)
+        {
+          *bit = NVIC_SYSHCON_MEMFAULTENA;
+        }
+      else if (irq == LM3S_IRQ_BUSFAULT)
+        {
+          *bit = NVIC_SYSHCON_BUSFAULTENA;
+        }
+      else if (irq == LM3S_IRQ_USAGEFAULT)
+        {
+          *bit = NVIC_SYSHCON_USGFAULTENA;
+        }
+      else if (irq == LM3S_IRQ_SYSTICK)
+        {
+          *regaddr = NVIC_SYSTICK_CTRL;
+          *bit = NVIC_SYSTICK_CTRL_ENABLE;
+        }
+      else
+        {
+          return ERROR; /* Invalid or unsupported exception */
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  /* Disable all interrupts */
+
+  putreg32(0, NVIC_IRQ0_31_ENABLE);
+  putreg32(0, NVIC_IRQ32_63_ENABLE);
+
+  /* Set all interrrupts (and exceptions) to the default priority */
+
+  putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
+
+  putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* Initialize support for GPIO interrupts if included in this build */
+
+#ifndef CONFIG_LM_DISABLE_GPIO_IRQS
+#ifdef CONFIG_HAVE_WEAKFUNCTIONS
+  if (gpio_irqinitialize != NULL)
+#endif
+    {
+      gpio_irqinitialize();
+    }
+#endif
+
+  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
+   * exception is used for performing context switches; The Hard Fault
+   * must also be caught because a SVCall may show up as a Hard Fault
+   * under certain conditions.
+   */
+
+  irq_attach(LM3S_IRQ_SVCALL, up_svcall);
+  irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault);
+
+  /* Set the priority of the SVCall interrupt */
+
+#ifdef CONFIG_ARCH_IRQPRIO
+/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
+#endif
+
+  /* If the MPU is enabled, then attach and enable the Memory Management
+   * Fault handler.
+   */
+
+#ifdef CONFIG_ARMV7M_MPU
+  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
+  up_enable_irq(LM3S_IRQ_MEMFAULT);
+#endif
+
+  /* Attach all other processor exceptions (except reset and sys tick) */
+
+#ifdef CONFIG_DEBUG
+  irq_attach(LM3S_IRQ_NMI, lm_nmi);
+#ifndef CONFIG_ARMV7M_MPU
+  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
+#endif
+  irq_attach(LM3S_IRQ_BUSFAULT, lm_busfault);
+  irq_attach(LM3S_IRQ_USAGEFAULT, lm_usagefault);
+  irq_attach(LM3S_IRQ_PENDSV, lm_pendsv);
+  irq_attach(LM3S_IRQ_DBGMONITOR, lm_dbgmonitor);
+  irq_attach(LM3S_IRQ_RESERVED, lm_reserved);
+#endif
+
+  lm_dumpnvic("initial", NR_IRQS);
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+
+  /* And finally, enable interrupts */
+
+  setbasepri(NVIC_SYSH_PRIORITY_MAX);
+  irqrestore(0);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  uint32_t bit;
+
+  if (lm_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Clear the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval &= ~bit;
+      putreg32(regval, regaddr);
+    }
+  lm_dumpnvic("disable", irq);
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  uint32_t bit;
+
+  if (lm_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Set the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval |= bit;
+      putreg32(regval, regaddr);
+    }
+  lm_dumpnvic("enable", irq);
+}
+
+/****************************************************************************
+ * Name: up_maskack_irq
+ *
+ * Description:
+ *   Mask the IRQ and acknowledge it
+ *
+ ****************************************************************************/
+
+void up_maskack_irq(int irq)
+{
+  up_disable_irq(irq);
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   Set the priority of an IRQ.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  int shift;
+
+  DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
+
+  if (irq < LM3S_IRQ_INTERRUPTS)
+    {
+      irq    -= 4;
+      regaddr = NVIC_SYSH_PRIORITY(irq);
+    }
+  else
+    {
+      irq    -= LM3S_IRQ_INTERRUPTS;
+      regaddr = NVIC_IRQ_PRIORITY(irq);
+    }
+
+  regval      = getreg32(regaddr);
+  shift       = ((irq & 3) << 3);
+  regval     &= ~(0xff << shift);
+  regval     |= (priority << shift);
+  putreg32(regval, regaddr);
+
+  lm_dumpnvic("prioritize", irq);
+  return OK;
+}
+#endif
diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.c b/nuttx/arch/arm/src/lm/lm_lowputc.c
new file mode 100644
index 000000000..d2c1f5be5
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_lowputc.c
@@ -0,0 +1,309 @@
+/**************************************************************************
+ * arch/arm/src/lm/lm_lowputc.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "lm_gpio.h"
+#include "chip/lm_pinmap.h"
+
+#include "lm_lowputc.h"
+
+/**************************************************************************
+ * Pre-processor Definitions
+ **************************************************************************/
+
+/* Configuration **********************************************************/
+
+#if LM3S_NUARTS < 2
+#  undef  CONFIG_LM_UART1
+#  undef  CONFIG_UART1_SERIAL_CONSOLE
+#endif
+
+#if LM3S_NUARTS < 3
+#  undef  CONFIG_LM_UART2
+#  undef  CONFIG_UART2_SERIAL_CONSOLE
+#endif
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM_UART0)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM_UART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* Select UART parameters for the selected console */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define LM3S_CONSOLE_BASE     LM3S_UART0_BASE
+#  define LM3S_CONSOLE_BAUD     CONFIG_UART0_BAUD
+#  define LM3S_CONSOLE_BITS     CONFIG_UART0_BITS
+#  define LM3S_CONSOLE_PARITY   CONFIG_UART0_PARITY
+#  define LM3S_CONSOLE_2STOP    CONFIG_UART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define LM3S_CONSOLE_BASE     LM3S_UART1_BASE
+#  define LM3S_CONSOLE_BAUD     CONFIG_UART1_BAUD
+#  define LM3S_CONSOLE_BITS     CONFIG_UART1_BITS
+#  define LM3S_CONSOLE_PARITY   CONFIG_UART1_PARITY
+#  define LM3S_CONSOLE_2STOP    CONFIG_UART1_2STOP
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define LM3S_CONSOLE_BASE     LM3S_UART2_BASE
+#  define LM3S_CONSOLE_BAUD     CONFIG_UART2_BAUD
+#  define LM3S_CONSOLE_BITS     CONFIG_UART2_BITS
+#  define LM3S_CONSOLE_PARITY   CONFIG_UART2_PARITY
+#  define LM3S_CONSOLE_2STOP    CONFIG_UART2_2STOP
+#else
+#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Get LCRH settings */
+
+#if LM3S_CONSOLE_BITS == 5
+#  define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
+#elif LM3S_CONSOLE_BITS == 6
+#  define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
+#elif LM3S_CONSOLE_BITS == 7
+#  define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
+#elif LM3S_CONSOLE_BITS == 8
+#  define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
+#else
+#  error "Number of bits not supported"
+#endif
+
+#if LM3S_CONSOLE_PARITY == 0
+#  define UART_LCRH_PARITY (0)
+#elif LM3S_CONSOLE_PARITY == 1
+#  define UART_LCRH_PARITY UART_LCRH_PEN
+#elif LM3S_CONSOLE_PARITY == 2
+#  define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
+#else
+#  error "Invalid parity selection"
+#endif
+
+#if LM3S_CONSOLE_2STOP != 0
+#  define UART_LCRH_NSTOP UART_LCRH_STP2
+#else
+#  define UART_LCRH_NSTOP (0)
+#endif
+
+#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN)
+
+/* Calculate BAUD rate from the SYS clock:
+ *
+ * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit
+ *  fractional part. The number formed by these two values is used by the baud-rate generator
+ *  to determine the bit period. Having a fractional baud-rate divider allows the UART to
+ *  generate all the standard baud rates.
+ *
+ * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD)
+ *  register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
+ *  Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship
+ *  to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional
+ *  part, separated by a decimal place.):
+ *
+ *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
+ *
+ * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number
+ *  (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated
+ *  by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5
+ *  to account for rounding errors:
+ *
+ *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
+ *
+ * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred
+ *  to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is
+ *  used for error detection during receive operations.
+ *
+ * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and
+ *  UARTFBRD registers form an internal 30-bit register. This internal register is only
+ *  updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
+ *  divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
+ */
+
+#define LM3S_BRDDEN     (16 * LM3S_CONSOLE_BAUD)
+#define LM3S_BRDI       (SYSCLK_FREQUENCY / LM3S_BRDDEN)
+#define LM3S_REMAINDER  (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
+#define LM3S_DIVFRAC    ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
+
+/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
+ *
+ * LM3S_BRDDEN    = (16 * 115,200)                           = 1,843,200
+ * LM3S_BRDI      = 50,000,000 / 1,843,200                   = 27
+ * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27              = 233,600
+ * LM3S_DIVFRAC   = (233,600 * 64 + 921,600) / 1,843,200     = 8
+ *
+ * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
+ */
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ **************************************************************************/
+
+void up_lowputc(char ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Wait until the TX FIFO is not full */
+
+  while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
+
+  /* Then send the character */
+
+  putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET);
+#endif
+}
+
+/**************************************************************************
+ * Name: up_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ **************************************************************************/
+
+void up_lowsetup(void)
+{
+  uint32_t regval;
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  uint32_t ctl;
+#endif
+
+  /* Enable the selected UARTs and configure GPIO pins to need by the
+   * the selected UARTs.  NOTE: The serial driver later depends on
+   * this pin configuration -- whether or not a serial console is selected.
+   */
+
+#ifdef CONFIG_LM_UART0
+  regval  = getreg32(LM3S_SYSCON_RCGC1);
+  regval |= SYSCON_RCGC1_UART0;
+  putreg32(regval, LM3S_SYSCON_RCGC1);
+
+  lm_configgpio(GPIO_UART0_RX);
+  lm_configgpio(GPIO_UART0_TX);
+#endif
+
+#ifdef CONFIG_LM_UART1
+  regval  = getreg32(LM3S_SYSCON_RCGC1);
+  regval |= SYSCON_RCGC1_UART1;
+  putreg32(regval, LM3S_SYSCON_RCGC1);
+
+  lm_configgpio(GPIO_UART1_RX);
+  lm_configgpio(GPIO_UART1_TX);
+#endif
+
+  /* Enable the selected console device */
+
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
+
+  ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+  ctl &= ~UART_CTL_UARTEN;
+  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+
+  /* Write the integer portion of the BRD to the UART IBRD register */
+
+  putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
+
+  /* Write the fractional portion of the BRD to the UART FBRD register */
+
+  putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
+
+  /* Write the desired serial parameters to the UART LCRH register */
+
+  putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
+
+  /* Enable the UART by setting the UARTEN bit in the UART CTL register */
+
+  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
+  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+#endif
+
+}
+
+
diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.h b/nuttx/arch/arm/src/lm/lm_lowputc.h
index b384bbd80..49d6e2df9 100644
--- a/nuttx/arch/arm/src/lm/lm_lowputc.h
+++ b/nuttx/arch/arm/src/lm/lm_lowputc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lm/lm3s_lowputc.h
+ * arch/arm/src/lm/lm_lowputc.h
  *
  *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
diff --git a/nuttx/arch/arm/src/lm/lm_serial.c b/nuttx/arch/arm/src/lm/lm_serial.c
new file mode 100644
index 000000000..e9f604989
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_serial.c
@@ -0,0 +1,1064 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_serial.c
+ *
+ *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial/serial.h>
+
+#include <arch/serial.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "os_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Some sanity checks *******************************************************/
+
+#if LM3S_NUARTS < 2
+#  undef  CONFIG_LM_UART1
+#  undef  CONFIG_UART1_SERIAL_CONSOLE
+#endif
+
+#if LM3S_NUARTS < 3
+#  undef  CONFIG_LM_UART2
+#  undef  CONFIG_UART2_SERIAL_CONSOLE
+#endif
+
+/* Is there a UART enabled? */
+
+#if !defined(CONFIG_LM_UART0) && !defined(CONFIG_LM_UART1) && !defined(CONFIG_LM_UART2)
+#  error "No UARTs enabled"
+#endif
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM_UART0)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM_UART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* If we are not using the serial driver for the console, then we
+ * still must provide some minimal implementation of up_putc.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart0port     /* UART0 is console */
+#  define TTYS0_DEV       g_uart0port     /* UART0 is ttyS0 */
+#  ifdef CONFIG_LM_UART1
+#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
+#    ifdef CONFIG_LM_UART2
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifdef CONFIG_LM_UART2
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart1port     /* UART1 is console */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  ifdef CONFIG_LM_UART0
+#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
+#    ifdef CONFIG_LM_UART2
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifdef CONFIG_LM_UART2
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart2port     /* UART2 is console */
+#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
+#  ifdef CONFIG_LM_UART0
+#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
+#    ifdef CONFIG_LM_UART2
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifdef CONFIG_LM_UART2
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elifdefined(CONFIG_LM_UART0)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  ifdef CONFIG_LM_UART1
+#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
+#    ifdef CONFIG_LM_UART2
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifdef CONFIG_LM_UART2
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elifdefined(CONFIG_LM_UART1)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  undef TTYS2_DEV                        /* No ttyS2 */
+#  ifdef CONFIG_LM_UART2
+#    define TTYS1_DEV     g_uart2port     /* UART2 is ttyS1 */
+#  else
+#    undef TTYS1_DEV                      /* No ttyS1 */
+#  endif
+#elifdefined(CONFIG_LM_UART2)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
+#  undef  TTYS1_DEV                       /* No ttyS1 */
+#  undef  TTYS2_DEV                       /* No ttyS2 */
+#else
+#  error "No valid TTY devices"
+#  undef  CONSOLE_DEV                     /* No console device */
+#  undef  TTYS0_DEV                       /* No ttyS0 */
+#  undef  TTYS1_DEV                       /* No ttyS1 */
+#  undef  TTYS2_DEV                       /* No ttyS2 */
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uint32_t uartbase; /* Base address of UART registers */
+  uint32_t baud;     /* Configured baud */
+  uint32_t im;       /* Saved IM value */
+  uint8_t  irq;      /* IRQ associated with this UART */
+  uint8_t  parity;   /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;     /* Number of bits (7 or 8) */
+  bool    stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int  up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int  up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int  up_interrupt(int irq, void *context);
+static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+static bool up_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .attach         = up_attach,
+  .detach         = up_detach,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxavailable    = up_rxavailable,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txready        = up_txready,
+  .txempty        = up_txempty,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_LM_UART0
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+#endif
+#ifdef CONFIG_LM_UART1
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+#endif
+#ifdef CONFIG_LM_UART2
+static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
+static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
+#endif
+
+/* This describes the state of the LM3S uart0 port. */
+
+#ifdef CONFIG_LM_UART0
+static struct up_dev_s g_uart0priv =
+{
+  .uartbase       = LM3S_UART0_BASE,
+  .baud           = CONFIG_UART0_BAUD,
+  .irq            = LM3S_IRQ_UART0,
+  .parity         = CONFIG_UART0_PARITY,
+  .bits           = CONFIG_UART0_BITS,
+  .stopbits2      = CONFIG_UART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+#endif
+
+/* This describes the state of the LM3S uart1 port. */
+
+#ifdef CONFIG_LM_UART1
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase       = LM3S_UART1_BASE,
+  .baud           = CONFIG_UART1_BAUD,
+  .irq            = LM3S_IRQ_UART1,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+#endif
+
+/* This describes the state of the LM3S uart1 port. */
+
+#ifdef CONFIG_LM_UART2
+static struct up_dev_s g_uart2priv =
+{
+  .uartbase       = LM3S_UART2_BASE,
+  .baud           = CONFIG_UART2_BAUD,
+  .irq            = LM3S_IRQ_UART2,
+  .parity         = CONFIG_UART2_PARITY,
+  .bits           = CONFIG_UART2_BITS,
+  .stopbits2      = CONFIG_UART2_2STOP,
+};
+
+static uart_dev_t g_uart2port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART2_RXBUFSIZE,
+    .buffer = g_uart2rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART2_TXBUFSIZE,
+    .buffer = g_uart2txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart2priv,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg32(priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disableuartint
+ ****************************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
+{
+  /* Return the current interrupt mask value */
+
+  if (im)
+    {
+      *im = priv->im;
+    }
+
+  /* Disable all interrupts */
+
+  priv->im = 0;
+  up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
+}
+
+/****************************************************************************
+ * Name: up_restoreuartint
+ ****************************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
+{
+  priv->im = im;
+  up_serialout(priv, LM3S_UART_IM_OFFSET, im);
+}
+
+/****************************************************************************
+ * Name: up_waittxnotfull
+ ****************************************************************************/
+
+#ifdef HAVE_CONSOLE
+static inline void up_waittxnotfull(struct up_dev_s *priv)
+{
+  int tmp;
+
+  /* Limit how long we will wait for the TX available condition */
+
+  for (tmp = 1000 ; tmp > 0 ; tmp--)
+    {
+      /* Check Tx FIFO is full */
+
+      if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
+        {
+          /* The Tx FIFO is not full... return */
+
+          break;
+        }
+    }
+
+  /* If we get here, then the wait has timed out and the Tx FIFO remains
+   * full.
+   */
+}
+#endif
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This
+ *   method is called the first time that the serial port is
+ *   opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32_t lcrh;
+  uint32_t ctl;
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+  uint32_t den;
+  uint32_t brdi;
+  uint32_t remainder;
+  uint32_t divfrac;
+
+  /* Note:  The logic here depends on the fact that that the UART module
+   * was enabled and the GPIOs were configured in up_lowsetup().
+   */
+
+  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
+
+  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
+  ctl &= ~UART_CTL_UARTEN;
+  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
+
+  /* Calculate BAUD rate from the SYS clock:
+   *
+   * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer
+   *  and a 6-bit fractional part. The number formed by these two values is
+   *  used by the baud-rate generator to determine the bit period. Having a
+   *  fractional baud-rate divider allows the UART to generate all the standard
+   *  baud rates.
+   *
+   * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor
+   *  (UARTIBRD) register ... and the 6-bit fractional part is loaded with the
+   *  UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate
+   *  divisor (BRD) has the following relationship to the system clock (where
+   *  BRDI is the integer part of the BRD and BRDF is the fractional part,
+   *  separated by a decimal place.):
+   *
+   *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
+   *
+   * "where UARTSysClk is the system clock connected to the UART. The 6-bit
+   *  fractional number (that is to be loaded into the DIVFRAC bit field in the
+   *  UARTFBRD register) can be calculated by taking the fractional part of the
+   *  baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
+   *  rounding errors:
+   *
+   *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
+   *
+   * "The UART generates an internal baud-rate reference clock at 16x the baud-
+   *  rate (referred to as Baud16). This reference clock is divided by 16 to
+   *  generate the transmit clock, and is used for error detection during receive
+   *  operations.
+   *
+   * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the
+   *  UARTIBRD and UARTFBRD registers form an internal 30-bit register. This
+   *  internal register is only updated when a write operation to UARTLCRH is
+   *  performed, so any changes to the baud-rate divisor must be followed by a
+   *  write to the UARTLCRH register for the changes to take effect. ..."
+   */
+
+  den       = priv->baud << 4;
+  brdi      = SYSCLK_FREQUENCY / den;
+  remainder = SYSCLK_FREQUENCY - den * brdi;
+  divfrac   = ((remainder << 6) + (den >> 1)) / den;
+
+  up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
+  up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
+
+  /* Set up the LCRH register */
+
+  lcrh = 0;
+  switch (priv->bits)
+    {
+      case 5:
+        lcrh |= UART_LCRH_WLEN_5BITS;
+        break;
+      case 6:
+        lcrh |= UART_LCRH_WLEN_6BITS;
+        break;
+      case 7:
+        lcrh |= UART_LCRH_WLEN_7BITS;
+        break;
+      case 8:
+      default:
+        lcrh |= UART_LCRH_WLEN_8BITS;
+        break;
+    }
+
+  switch (priv->parity)
+    {
+      case 0:
+      default:
+        break;
+      case 1:
+        lcrh |= UART_LCRH_PEN;
+        break;
+      case 2:
+        lcrh |= UART_LCRH_PEN|UART_LCRH_EPS;
+        break;
+    }
+
+  if (priv->stopbits2)
+    {
+      lcrh |= UART_LCRH_STP2;
+    }
+
+  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
+#endif
+
+  /* Set the UART to interrupt whenever the TX FIFO is almost empty or when
+   * any character is received.
+   */
+
+  up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
+
+  /* Flush the Rx and Tx FIFOs -- How do you do that?*/
+
+  /* Enable Rx interrupts from the UART except for Tx interrupts.  We don't want
+   * Tx interrupts until we have something to send.  We will check for serial
+   * errors as part of Rx interrupt processing (no interrupts will be received
+   * yet because the interrupt is still disabled at the interrupt controller.
+   */
+
+  up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
+
+  /* Enable the FIFOs */
+
+#ifdef CONFIG_SUPPRESS_UART_CONFIG
+  lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
+#endif
+  lcrh |= UART_LCRH_FEN;
+  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
+
+  /* Enable Rx, Tx, and the UART */
+
+#ifdef CONFIG_SUPPRESS_UART_CONFIG
+  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
+#endif
+  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
+  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
+
+  /* Set up the cache IM value */
+
+  priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial
+ *   port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disableuartint(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the UART to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless the
+ *   hardware supports multiple levels of interrupt enabling).  The RX and TX
+ *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  int ret;
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, up_interrupt);
+  if (ret == OK)
+    {
+       /* Enable the interrupt (RX and TX interrupts are still disabled
+        * in the UART
+        */
+
+       up_enable_irq(priv->irq);
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach UART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception is
+ *   the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked
+ *   when an interrupt received on the 'irq'  It should call
+ *   uart_transmitchars or uart_receivechar to perform the
+ *   appropriate data transfers.  The interrupt handling logic\
+ *   must be able to map the 'irq' number into the approprite
+ *   uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  uint32_t           mis;
+  int                passes;
+  bool               handled;
+
+#ifdef CONFIG_LM_UART0
+  if (g_uart0priv.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+#endif
+#ifdef CONFIG_LM_UART1
+  if (g_uart1priv.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else
+#endif
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  handled = true;
+  for (passes = 0; passes < 256 && handled; passes++)
+    {
+      handled = false;
+
+      /* Get the masked UART status and clear the pending interrupts. */
+
+       mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
+       up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
+
+      /* Handle incoming, receive bytes (with or without timeout) */
+
+      if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0)
+        {
+           /* Rx buffer not empty ... process incoming bytes */
+
+           uart_recvchars(dev);
+           handled = true;
+        }
+
+      /* Handle outgoing, transmit bytes */
+
+      if ((mis & UART_MIS_TXMIS) != 0)
+        {
+           /* Tx FIFO not full ... process outgoing bytes */
+
+           uart_xmitchars(dev);
+           handled = true;
+        }
+    }
+    return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             ret = -EINVAL;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+
+    default:
+      ret = -ENOTTY;
+      break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32_t *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32_t rxd;
+
+  /* Get the Rx byte + 4 bits of error information.  Return those in status */
+
+  rxd     = up_serialin(priv, LM3S_UART_DR_OFFSET);
+  *status = rxd;
+
+  /* The lower 8bits of the Rx data is the actual recevied byte */
+
+  return rxd & 0xff;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+      /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx
+       * timeout occurs.
+       */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->im |= (UART_IM_RXIM|UART_IM_RTIM);
+#endif
+    }
+  else
+    {
+      priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
+    }
+  up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return true if the receive fifo is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  irqstate_t flags;
+
+  flags = irqsave();
+  if (enable)
+    {
+      /* Set to receive an interrupt when the TX fifo is half emptied */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->im |= UART_IM_TXIM;
+      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+
+      /* The serial driver wants an interrupt here, but will not get get
+       * one unless we "prime the pump."  I believe that this is because
+       * behave like a level interrupt and the LM3S interrupts behave
+       * (at least by default) like edge interrupts.
+       *
+       * In any event, faking a TX interrupt here solves the problem;
+       * Call uart_xmitchars() just as would have been done if we recieved
+       * the TX interrupt.
+       */
+
+      uart_xmitchars(dev);
+#endif
+    }
+  else
+    {
+      /* Disable the TX interrupt */
+
+      priv->im &= ~UART_IM_TXIM;
+      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+    }
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return true if the tranmsit fifo is not full
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
+}
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ *   Return true if the transmit fifo is empty
+ *
+ ****************************************************************************/
+
+static bool up_txempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in 
+ *   debug so that the serial console will be available
+ *   during bootup.  This must be called before up_serialinit.
+ *
+ ****************************************************************************/
+
+void up_earlyserialinit(void)
+{
+  /* NOTE:  All GPIO configuration for the UARTs was performed in
+   * up_lowsetup
+   */
+
+  /* Disable all UARTS */
+
+  up_disableuartint(TTYS0_DEV.priv, NULL);
+#ifdef TTYS1_DEV
+  up_disableuartint(TTYS1_DEV.priv, NULL);
+#endif
+#ifdef TTYS2_DEV
+  up_disableuartint(TTYS2_DEV.priv, NULL);
+#endif
+
+  /* Configuration whichever one is the console */
+
+#ifdef HAVE_CONSOLE
+  CONSOLE_DEV.isconsole = true;
+  up_setup(&CONSOLE_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+  /* Register the console */
+
+#ifdef HAVE_CONSOLE
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+  /* Register all UARTs */
+
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+#ifdef TTYS1_DEV
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+#ifdef TTYS2_DEV
+  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint32_t im;
+
+  up_disableuartint(priv, &im);
+  up_waittxnotfull(priv);
+  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_waittxnotfull(priv);
+      up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r');
+    }
+
+  up_waittxnotfull(priv);
+  up_restoreuartint(priv, im);
+#endif
+  return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
diff --git a/nuttx/arch/arm/src/lm/lm_ssi.c b/nuttx/arch/arm/src/lm/lm_ssi.c
new file mode 100644
index 000000000..c6f8dcdb1
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_ssi.c
@@ -0,0 +1,1580 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_ssi.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/spi.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lm_gpio.h"
+#include "lm_ssi.h"
+#include "chip/lm_pinmap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Enables debug output from this file (needs CONFIG_DEBUG with
+ * CONFIG_DEBUG_VERBOSE too)
+ */
+
+#undef SSI_DEBUG  /* Define to enable debug */
+
+#ifdef SSI_DEBUG
+#  define ssidbg  lldbg
+#  define ssivdbg llvdbg
+#else
+#  define ssidbg(x...)
+#  define ssivdbg(x...)
+#endif
+
+/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI
+ * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in
+ * such case, the following must be expanded).
+ */
+
+#if LM3S_NSSI == 0
+#  undef CONFIG_SSI0_DISABLE
+#  define CONFIG_SSI0_DISABLE 1
+#  undef CONFIG_SSI1_DISABLE
+#  define CONFIG_SSI1_DISABLE 1
+#elif LM3S_NSSI == 1
+#  undef CONFIG_SSI1_DISABLE
+#  define CONFIG_SSI1_DISABLE 1
+#endif
+
+/* Which SSI modules have been enabled? */
+
+#ifndef CONFIG_SSI0_DISABLE
+#  define SSI0_NDX 0             /* Index to SSI0 in g_ssidev[] */
+#  ifndef CONFIG_SSI1_DISABLE
+#   define SSI1_NDX 1            /* Index to SSI1 in g_ssidev[] */
+#   define NSSI_ENABLED 2        /* Two SSI interfaces: SSI0 & SSI1 */
+#  else
+#   define NSSI_ENABLED 1        /* One SSI interface: SSI0 */
+#   define SSI_BASE          LM3S_SSI0_BASE
+#   define SSI_IRQ           LM3S_IRQ_SSI0
+#  endif
+#else
+#  ifndef CONFIG_SSI1_DISABLE
+#   define SSI1_NDX 0            /* Index to SSI1 in g_ssidev[] */
+#   define NSSI_ENABLED 1        /* One SSI interface: SSI1 */
+#   define SSI_BASE          LM3S_SSI1_BASE
+#   define SSI_IRQ           LM3S_IRQ_SSI1
+#  else
+#   define NSSI_ENABLED 0        /* No SSI interfaces */
+#  endif
+#endif
+
+/* Compile the rest of the file only if at least one SSI interface has been
+ * enabled.
+ */
+
+#if NSSI_ENABLED > 0
+
+/* The number of (16-bit) words that will fit in the Tx FIFO */
+
+#define LM3S_TXFIFO_WORDS 8
+
+/* Configuration settings */
+
+#ifndef CONFIG_SSI_TXLIMIT
+#  define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2)
+#endif
+
+#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS
+#  error "Invalid range for CONFIG_SSI_TXLIMIT"
+#endif
+
+#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2)
+#  error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
+#endif
+
+/****************************************************************************
+ * Private Type Definitions
+ ****************************************************************************/
+
+struct lm_ssidev_s
+{
+  const struct spi_ops_s *ops;  /* Common SPI operations */
+#ifndef CONFIG_SSI_POLLWAIT
+  sem_t  xfrsem;                /* Wait for transfer to complete */
+#endif
+
+  /* These following are the source and destination buffers of the transfer.
+   * they are retained in this structure so that they will be accessible
+   * from an interrupt handler.  The actual type of the buffer is uint8_t if
+   * nbits <=8 and uint16_t if nbits >8.
+   */
+
+  void  *txbuffer;              /* Source buffer */
+  void  *rxbuffer;              /* Destination buffer */
+
+  /* These are functions pointers that are configured to perform the
+   * appropriate transfer for the particular kind of exchange that is
+   * occurring.  Differnt functions may be selected depending on (1)
+   * if the tx or txbuffer is NULL and depending on the number of bits
+   * per word.
+   */
+
+  void  (*txword)(struct lm_ssidev_s *priv);
+  void  (*rxword)(struct lm_ssidev_s *priv);
+
+#if NSSI_ENABLED > 1
+  uint32_t base;                /* SSI register base address */
+#endif
+
+  int      ntxwords;            /* Number of words left to transfer on the Tx FIFO */
+  int      nrxwords;            /* Number of words received on the Rx FIFO */
+  int      nwords;              /* Number of words to be exchanged */
+  uint8_t  nbits;               /* Current number of bits per word */
+
+#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
+  uint8_t  irq;                 /* SSI IRQ number */
+#endif
+
+  /* If there is more than one device on the SPI bus, then we have to enforce
+   * mutual exclusion and remember some configuration settings to reduce the
+   * overhead of constant SPI re-configuration.
+   */
+
+#ifndef CONFIG_SPI_OWNBUS
+  sem_t    exclsem;             /* For exclusive access to the SSI bus */
+  uint32_t frequency;           /* Current desired SCLK frequency */
+  uint32_t actual;              /* Current actual SCLK frequency */
+  uint8_t  mode;                /* Current mode 0,1,2,3 */
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SSI register access */
+
+static inline uint32_t ssi_getreg(struct lm_ssidev_s *priv,
+              unsigned int offset);
+static inline void ssi_putreg(struct lm_ssidev_s *priv, unsigned int offset,
+              uint32_t value);
+
+/* Misc helpers */
+
+static uint32_t ssi_disable(struct lm_ssidev_s *priv);
+static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable);
+
+#ifndef CONFIG_SSI_POLLWAIT
+static void ssi_semtake(sem_t *sem);
+#define ssi_semgive(s) sem_post(s);
+#endif
+
+/* SSI data transfer */
+
+static void ssi_txnull(struct lm_ssidev_s *priv);
+static void ssi_txuint16(struct lm_ssidev_s *priv);
+static void ssi_txuint8(struct lm_ssidev_s *priv);
+static void ssi_rxnull(struct lm_ssidev_s *priv);
+static void ssi_rxuint16(struct lm_ssidev_s *priv);
+static void ssi_rxuint8(struct lm_ssidev_s *priv);
+static inline bool ssi_txfifofull(struct lm_ssidev_s *priv);
+static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv);
+#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT)
+static inline int ssi_performtx(struct lm_ssidev_s *priv);
+#else
+static int  ssi_performtx(struct lm_ssidev_s *priv);
+#endif
+static inline void ssi_performrx(struct lm_ssidev_s *priv);
+static int  ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer,
+                         void *rxbuffer, unsigned int nwords);
+
+/* Interrupt handling */
+
+#ifndef CONFIG_SSI_POLLWAIT
+static inline struct lm_ssidev_s *ssi_mapirq(int irq);
+static int  ssi_interrupt(int irq, void *context);
+#endif
+
+/* SPI methods */
+
+#ifndef CONFIG_SPI_OWNBUS
+static int  ssi_lock(FAR struct spi_dev_s *dev, bool lock);
+#endif
+static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv,
+              uint32_t frequency);
+static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev,
+              uint32_t frequency);
+static void ssi_setmodeinternal(struct lm_ssidev_s *priv,
+              enum spi_mode_e mode);
+static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
+static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits);
+static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits);
+static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd);
+#ifdef CONFIG_SPI_EXCHANGE
+static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+                         FAR void *rxbuffer, size_t nwords);
+#else
+static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
+              size_t nwords);
+static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
+              size_t nwords);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Common SSI operations */
+
+static const struct spi_ops_s g_spiops =
+{
+#ifndef CONFIG_SPI_OWNBUS
+  .lock         = ssi_lock,
+#endif
+  .select       = lm_spiselect,    /* Provided externally by board logic */
+  .setfrequency = ssi_setfrequency,
+  .setmode      = ssi_setmode,
+  .setbits      = ssi_setbits,
+  .status       = lm_spistatus,    /* Provided externally by board logic */
+#ifdef CONFIG_SPI_CMDDATA
+  .cmddata      = lm_spicmddata,
+#endif
+  .send         = ssi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+  .exchange     = ssi_exchange,
+#else
+  .sndblock     = ssi_sndblock,
+  .recvblock    = ssi_recvblock,
+#endif
+};
+
+/* This supports is up to two SSI busses/ports */
+
+static struct lm_ssidev_s g_ssidev[] =
+{
+#ifndef CONFIG_SSI0_DISABLE
+  {
+    .ops  = &g_spiops,
+#if NSSI_ENABLED > 1
+    .base = LM3S_SSI0_BASE,
+#endif
+#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
+    .irq  = LM3S_IRQ_SSI0,
+#endif
+  },
+#endif
+#ifndef CONFIG_SSI1_DISABLE
+  {
+    .ops  = &g_spiops,
+#if NSSI_ENABLED > 1
+    .base = LM3S_SSI1_BASE,
+#endif
+#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
+    .irq  = LM3S_IRQ_SSI1,
+#endif
+  },
+#endif
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ssi_getreg
+ *
+ * Description:
+ *   Read the SSI register at this offeset
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   offset - Offset to the SSI register from the register base address
+ *
+ * Returned Value:
+ *   Value of the register at this offset
+ *
+ ****************************************************************************/
+
+static inline uint32_t ssi_getreg(struct lm_ssidev_s *priv, unsigned int offset)
+{
+#if NSSI_ENABLED > 1
+  return getreg32(priv->base + offset);
+#else
+  return getreg32(SSI_BASE + offset);
+#endif
+}
+
+/****************************************************************************
+ * Name: ssi_putreg
+ *
+ * Description:
+ *   Write the value to the SSI register at this offeset
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   offset - Offset to the SSI register from the register base address
+ *   value  - Value to write
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void ssi_putreg(struct lm_ssidev_s *priv, unsigned int offset, uint32_t value)
+{
+#if NSSI_ENABLED > 1
+  putreg32(value, priv->base + offset);
+#else
+  putreg32(value, SSI_BASE + offset);
+#endif
+}
+
+/****************************************************************************
+ * Name: ssi_disable
+ *
+ * Description:
+ *   Disable SSI operation.  NOTE: The SSI must be disabled before any control
+ *   registers can be re-programmed.
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   State of the SSI before the SSE was disabled
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static uint32_t ssi_disable(struct lm_ssidev_s *priv)
+{
+  uint32_t retval;
+  uint32_t regval;
+
+  retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
+  regval = (retval & ~SSI_CR1_SSE);
+  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
+  ssivdbg("CR1: %08x\n", regval);
+  return retval;
+}
+
+/****************************************************************************
+ * Name: ssi_enable
+ *
+ * Description:
+ *   Restore the SSI operational state
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   enable - The previous operational state
+ *
+ * Returned Value:
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable)
+{
+  uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
+  regval &= ~SSI_CR1_SSE;
+  regval  |= (enable & SSI_CR1_SSE);
+  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
+  ssivdbg("CR1: %08x\n", regval);
+}
+
+/****************************************************************************
+ * Name: ssi_semtake
+ *
+ * Description:
+ *   Wait for a semaphore (handling interruption by signals);
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   enable - The previous operational state
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SSI_POLLWAIT
+static void ssi_semtake(sem_t *sem)
+{
+  int ret;
+  do
+    {
+      ret = sem_wait(sem);
+    }
+  while (ret < 0 && errno == EINTR);
+  DEBUGASSERT(ret == 0);
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8
+ *
+ * Description:
+ *   Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer
+ *   pointer appropriately.  The selected function dependes on (1) if there
+ *   is a source txbuffer provided, and (2) if the number of bits per
+ *   word is <=8 or >8.
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void ssi_txnull(struct lm_ssidev_s *priv)
+{
+  ssivdbg("TX: ->0xffff\n");
+  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff);
+}
+
+static void ssi_txuint16(struct lm_ssidev_s *priv)
+{
+  uint16_t *ptr    = (uint16_t*)priv->txbuffer;
+  ssivdbg("TX: %p->%04x\n", ptr, *ptr);
+  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
+  priv->txbuffer = (void*)ptr;
+}
+
+static void ssi_txuint8(struct lm_ssidev_s *priv)
+{
+  uint8_t *ptr   = (uint8_t*)priv->txbuffer;
+  ssivdbg("TX: %p->%02x\n", ptr, *ptr);
+  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
+  priv->txbuffer = (void*)ptr;
+}
+
+/****************************************************************************
+ * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8
+ *
+ * Description:
+ *   Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the
+ *   user rxvbuffer and update the rxbuffer pointer appropriately.  The
+ *   selected function dependes on (1) if there is a desination rxbuffer
+ *   provided, and (2) if the number of bits per word is <=8 or >8.
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void ssi_rxnull(struct lm_ssidev_s *priv)
+{
+#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
+  uint32_t regval  = ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  ssivdbg("RX: discard %04x\n", regval);
+#else
+  (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+#endif
+}
+
+static void ssi_rxuint16(struct lm_ssidev_s *priv)
+{
+  uint16_t *ptr    = (uint16_t*)priv->rxbuffer;
+  *ptr           = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
+  priv->rxbuffer = (void*)(++ptr);
+}
+
+static void ssi_rxuint8(struct lm_ssidev_s *priv)
+{
+  uint8_t *ptr   = (uint8_t*)priv->rxbuffer;
+  *ptr           = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
+  priv->rxbuffer = (void*)(++ptr);
+}
+
+/****************************************************************************
+ * Name: ssi_txfifofull
+ *
+ * Description:
+ *   Return true if the Tx FIFO is full
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   true: Not full
+ *
+ ****************************************************************************/
+
+static inline bool ssi_txfifofull(struct lm_ssidev_s *priv)
+{
+  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
+}
+
+/****************************************************************************
+ * Name: ssi_rxfifoempty
+ *
+ * Description:
+ *   Return true if the Rx FIFO is empty
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   true: Not empty
+ *
+ ****************************************************************************/
+
+static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv)
+{
+  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
+}
+
+/****************************************************************************
+ * Name: ssi_performtx
+ *
+ * Description:
+ *   If the Tx FIFO is empty, then transfer as many words as we can to
+ *   the FIFO.
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   The number of words written to the Tx FIFO (a value from 0 to 8,
+ *   inclusive).
+ *
+ ****************************************************************************/
+
+#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT)
+static inline int ssi_performtx(struct lm_ssidev_s *priv)
+{
+  /* Check if the Tx FIFO is full and more data to transfer */
+
+  if (!ssi_txfifofull(priv) && priv->ntxwords > 0)
+    {
+      /* Transfer one word to the Tx FIFO */
+
+      priv->txword(priv);
+      priv->ntxwords--;
+      return 1;
+    }
+  return 0;
+}
+
+#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */
+
+static int ssi_performtx(struct lm_ssidev_s *priv)
+{
+#ifndef CONFIG_SSI_POLLWAIT
+  uint32_t regval;
+#endif
+  int ntxd = 0;  /* Number of words written to Tx FIFO */
+
+  /* Check if the Tx FIFO is full */
+
+  if (!ssi_txfifofull(priv))
+    {
+      /* Not full.. Check if all of the Tx words have been sent */
+
+      if (priv->ntxwords > 0)
+        {
+          /* No.. Transfer more words until either the Tx FIFO is full or
+           * until all of the user provided data has been sent.
+           */
+#ifdef CONFIG_SSI_TXLIMIT
+          /* Further limit the number of words that we put into the Tx
+           * FIFO to CONFIG_SSI_TXLIMIT.  Otherwise, we could
+           * overrun the Rx FIFO on a very fast SSI bus.
+           */
+          for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++)
+#else
+          for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++)
+#endif
+            {
+               priv->txword(priv);
+            }
+
+          /* Update the count of words to to transferred */
+
+          priv->ntxwords -= ntxd;
+        }
+
+      /* Check again... Now have all of the Tx words been sent? */
+
+#ifndef CONFIG_SSI_POLLWAIT
+      regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
+      if (priv->ntxwords > 0)
+        {
+          /* No.. Enable the Tx FIFO interrupt.  This interrupt occurs
+           * when the Tx FIFO is 1/2 full or less.
+           */
+
+#ifdef CONFIG_DEBUG
+          regval |= (SSI_IM_TX|SSI_RIS_ROR);
+#else
+          regval |= SSI_IM_TX;
+#endif
+        }
+      else
+        {
+          /* Yes.. Disable the Tx FIFO interrupt.  The final stages of
+           * the transfer will be driven by Rx FIFO interrupts.
+           */
+
+          regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
+        }
+      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
+#endif /* CONFIG_SSI_POLLWAIT */
+    }
+  return ntxd;
+}
+
+#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */
+
+/****************************************************************************
+ * Name: ssi_performrx
+ *
+ * Description:
+ *   Transfer as many bytes as possible from the Rx FIFO to the user Rx
+ *   buffer (if one was provided).
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void ssi_performrx(struct lm_ssidev_s *priv)
+{
+#ifndef CONFIG_SSI_POLLWAIT
+  uint32_t regval;
+#endif
+
+  /* Loop while data is available in the Rx FIFO */
+
+  while (!ssi_rxfifoempty(priv))
+    {
+      /* Have all of the requested words been transferred from the Rx FIFO? */
+
+      if (priv->nrxwords < priv->nwords)
+        {
+          /* No.. Read more data from Rx FIFO */
+
+          priv->rxword(priv);
+          priv->nrxwords++;
+        }
+    }
+
+  /* The Rx FIFO is now empty.  While there is Tx data to be sent, the
+   * transfer will be driven by Tx FIFO interrupts.  The final part
+   * of the transfer is driven by Rx FIFO interrupts only.
+   */
+
+#ifndef CONFIG_SSI_POLLWAIT
+  regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
+  if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
+    {
+       /* There are no more outgoing words to send, but there are
+        * additional incoming words expected (I would think that this
+        * a real corner case, be we will handle it with an extra 
+        * interrupt, probably an Rx timeout).
+        */
+
+#ifdef CONFIG_DEBUG
+      regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR);
+#else
+      regval |= (SSI_IM_RX|SSI_IM_RT);
+#endif
+    }
+  else
+    {
+      /* No.. there are either more Tx words to send or all Rx words
+       * have received.  Disable Rx FIFO interrupts.
+       */
+
+      regval &= ~(SSI_IM_RX|SSI_IM_RT);
+    }
+  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
+#endif /* CONFIG_SSI_POLLWAIT */
+}
+
+/****************************************************************************
+ * Name: ssi_transfer
+ *
+ * Description:
+ *   Exchange a block data with the SPI device
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   txbuffer - The buffer of data to send to the device (may be NULL).
+ *   rxbuffer - The buffer to receive data from the device (may be NULL).
+ *   nwords   - The total number of words to be exchanged.  If the interface
+ *              uses <= 8 bits per word, then this is the number of uint8_t's;
+ *              if the interface uses >8 bits per word, then this is the
+ *              number of uint16_t's
+ *
+ * Returned Value:
+ *   0: success, <0:Negated error number on failure
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer,
+                        void *rxbuffer, unsigned int nwords)
+{
+#ifndef CONFIG_SSI_POLLWAIT
+  irqstate_t flags;
+#endif
+  int ntxd;
+
+  ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords);
+
+  /* Set up to perform the transfer */
+
+  priv->txbuffer     = (uint8_t*)txbuffer; /* Source buffer */
+  priv->rxbuffer     = (uint8_t*)rxbuffer; /* Destination buffer */
+  priv->ntxwords     = nwords;             /* Number of words left to send */
+  priv->nrxwords     = 0;                  /* Number of words received */
+  priv->nwords       = nwords;             /* Total number of exchanges */
+
+  /* Set up the low-level data transfer function pointers */
+
+  if (priv->nbits > 8)
+    {
+      priv->txword = ssi_txuint16;
+      priv->rxword = ssi_rxuint16;
+    }
+  else
+    {
+      priv->txword = ssi_txuint8;
+      priv->rxword = ssi_rxuint8;
+    }
+
+  if (!txbuffer)
+    {
+      priv->txword = ssi_txnull;
+    }
+
+  if (!rxbuffer)
+    {
+      priv->rxword = ssi_rxnull;
+    }
+
+  /* Prime the Tx FIFO to start the sequence (saves one interrupt).
+   * At this point, all SSI interrupts should be disabled, but the
+   * operation of ssi_performtx() will set up the interrupts
+   * approapriately (if nwords > TxFIFO size).
+   */
+
+#ifndef CONFIG_SSI_POLLWAIT
+  flags = irqsave();
+  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
+          priv->ntxwords, priv->nrxwords, priv->nwords,
+          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
+
+  ntxd  = ssi_performtx(priv);
+
+  /* For the case where nwords < Tx FIFO size, ssi_performrx will
+   * configure interrupts correctly for the final phase of the
+   * the transfer.
+   */
+
+  ssi_performrx(priv);
+
+  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
+          priv->ntxwords, priv->nrxwords, priv->nwords,
+          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
+          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
+
+  /* Wait for the transfer to complete.  Since there is no handshake
+   * with SPI, the following should complete even if there are problems
+   * with the transfer, so it should be safe with no timeout.
+   */
+
+  ssivdbg("Waiting for transfer complete\n");
+  irqrestore(flags);
+  do
+    {
+      ssi_semtake(&priv->xfrsem);
+    }
+  while (priv->nrxwords < priv->nwords);
+  ssidbg("Transfer complete\n");
+
+#else
+  /* Perform the transfer using polling logic.  This will totally
+   * dominate the CPU until the transfer is complete.  Only recommended
+   * if (1) your SPI is very fast, and (2) if you only use very short
+   * transfers.
+   */
+
+  do
+    {
+      /* Handle outgoing Tx FIFO transfers */
+
+      ntxd = ssi_performtx(priv);
+
+      /* Handle incoming Rx FIFO transfers */
+
+      ssi_performrx(priv);
+
+      /* If there are other threads at this same priority level,
+       * the following may help:
+       */
+
+      sched_yield();
+    }
+  while (priv->nrxwords < priv->nwords);
+#endif
+  return OK;
+}
+
+/****************************************************************************
+ * Name: ssi_mapirq
+ *
+ * Description:
+ *   Map an IRQ number into the appropriate SSI device
+ *
+ * Input Parameters:
+ *   irq   - The IRQ number to be mapped
+ *
+ * Returned Value:
+ *   On success, a reference to the private data structgure for this IRQ.
+ *   NULL on failure.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SSI_POLLWAIT
+static inline struct lm_ssidev_s *ssi_mapirq(int irq)
+{
+  switch (irq)
+    {
+#ifndef CONFIG_SSI0_DISABLE
+      case LM3S_IRQ_SSI0:
+        return &g_ssidev[SSI0_NDX];
+#endif
+#ifndef CONFIG_SSI1_DISABLE
+      case LM3S_IRQ_SSI1:
+        return &g_ssidev[SSI1_NDX];
+#endif
+      default:
+        return NULL;
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_interrupt
+ *
+ * Description:
+ *   Exchange a block data with the SSI device
+ *
+ * Input Parameters:
+ *   priv   - Device-specific state data
+ *   txbuffer - The buffer of data to send to the device (may be NULL).
+ *   rxbuffer - The buffer to receive data from the device (may be NULL).
+ *   nwords   - The total number of words to be exchanged.  If the interface
+ *              uses <= 8 bits per word, then this is the number of uint8_t's;
+ *              if the interface uses >8 bits per word, then this is the
+ *              number of uint16_t's
+ *
+ * Returned Value:
+ *   0: success, <0:Negated error number on failure
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SSI_POLLWAIT
+static int ssi_interrupt(int irq, void *context)
+{
+  struct lm_ssidev_s *priv = ssi_mapirq(irq);
+  uint32_t regval;
+  int ntxd;
+
+  DEBUGASSERT(priv != NULL);
+
+  /* Clear pending interrupts */
+
+  regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET);
+  ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval);
+
+  /* Check for Rx FIFO overruns */
+
+#ifdef CONFIG_DEBUG
+  if ((regval & SSI_RIS_ROR) != 0)
+    {
+      lldbg("Rx FIFO Overrun!\n");
+    }
+#endif
+
+  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
+          priv->ntxwords, priv->nrxwords, priv->nwords,
+          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
+
+  /* Handle outgoing Tx FIFO transfers */
+
+  ntxd = ssi_performtx(priv);
+
+  /* Handle incoming Rx FIFO transfers */
+
+  ssi_performrx(priv);
+
+  ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
+          priv->ntxwords, priv->nrxwords, priv->nwords,
+          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
+          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
+
+  /* Check if the transfer is complete */
+
+  if (priv->nrxwords >= priv->nwords)
+    {
+      /* Yes.. Disable all SSI interrupt sources */
+
+      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
+
+      /* Wake up the waiting thread */
+
+      ssidbg("Transfer complete\n");
+      ssi_semgive(&priv->xfrsem);
+    }
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_lock
+ *
+ * Description:
+ *   On SPI busses where there are multiple devices, it will be necessary to
+ *   lock SPI to have exclusive access to the busses for a sequence of
+ *   transfers.  The bus should be locked before the chip is selected. After
+ *   locking the SPI bus, the caller should then also call the setfrequency,
+ *   setbits, and setmode methods to make sure that the SPI is properly
+ *   configured for the device.  If the SPI buss is being shared, then it
+ *   may have been left in an incompatible state.
+ *
+ * Input Parameters:
+ *   dev  - Device-specific state data
+ *   lock - true: Lock spi bus, false: unlock SPI bus
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_OWNBUS
+static int ssi_lock(FAR struct spi_dev_s *dev, bool lock)
+{
+  FAR struct lm_ssidev_s *priv = (FAR struct lm_ssidev_s *)dev;
+
+  if (lock)
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      while (sem_wait(&priv->exclsem) != 0)
+        {
+          /* The only case that an error should occur here is if the wait was awakened
+           * by a signal.
+           */
+
+          ASSERT(errno == EINTR);
+        }
+    }
+  else
+    {
+      (void)sem_post(&priv->exclsem);
+    }
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_setfrequency
+ *
+ * Description:
+ *   Set the SPI frequency.
+ *
+ * Input Parameters:
+ *   dev -       Device-specific state data
+ *   frequency - The SPI frequency requested
+ *
+ * Returned Value:
+ *   Returns the actual frequency selected
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv, uint32_t frequency)
+{
+  uint32_t maxdvsr;
+  uint32_t cpsdvsr;
+  uint32_t regval;
+  uint32_t scr;
+  uint32_t actual;
+
+  ssidbg("frequency: %d\n", frequency);
+  DEBUGASSERT(frequency);
+
+  /* Has the frequency changed? */
+
+#ifndef CONFIG_SPI_OWNBUS
+  if (frequency != priv->frequency)
+    {
+#endif
+      /* "The serial bit rate is derived by dividing down the input clock
+       *  (FSysClk). The clock is first divided by an even prescale value
+       *  CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
+       *  (SSI_CPSR) register ... The clock is further divided by a value
+       *  from 1 to 256, which is 1 + SCR, where SCR is the value programmed 
+       *  i n the SSI Control0 (SSICR0) register ...
+       *
+       * "The frequency of the output clock SSIClk is defined by:
+       *
+       *    "SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
+       *
+       * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz,
+       *  the module may not be able to operate at that speed. For master mode,
+       *  the system clock must be at least two times faster than the SSIClk.
+       *  For slave mode, the system clock must be at least 12 times faster
+       *  than the SSIClk."
+       */
+
+      if (frequency > SYSCLK_FREQUENCY/2)
+        {
+          frequency = SYSCLK_FREQUENCY/2;
+        }
+
+      /* Find optimal values for CPSDVSR and SCR.  This loop is inefficient,
+       * but should not have to execute many times.
+       *
+       * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000.
+       *
+       *   maxcvsr = 125
+       *   1. cpsdvsr = 2, scr = 61 -> DONE
+       *
+       *   This would correspond to an actual frequency of:
+       *   50,000,000 / (2 * (62)) = 403,226
+       *
+       * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000.
+       *
+       *   maxcvsr = 2
+       *   1. cpsdvsr = 2, scr = 0 -> DONE
+       *
+       *   This would correspond to an actual frequency of:
+       *   50,000,000 / (2 * (1)) = 25,000,000
+       */
+
+      maxdvsr = SYSCLK_FREQUENCY / frequency;
+      cpsdvsr = 0;
+      do
+        {
+          cpsdvsr += 2;
+          scr = (maxdvsr / cpsdvsr) - 1;
+        }
+      while (scr > 255);
+
+      /* Set CPDVSR */
+
+      DEBUGASSERT(cpsdvsr < 255);
+      ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr);
+
+      /* Set SCR */
+
+      regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval &= ~SSI_CR0_SCR_MASK;
+      regval |= (scr << SSI_CR0_SCR_SHIFT);
+      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
+
+      /* Calcluate the actual frequency */
+
+      actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1));
+
+      /* Save the frequency selection so that subsequent reconfigurations will be
+       * faster.
+       */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->frequency = frequency;
+      priv->actual    = actual;
+    }
+  return priv->actual;
+#else
+  return actual;
+#endif
+}
+
+static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
+{
+  struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev;
+  uint32_t enable;
+  uint32_t actual;
+
+  /* NOTE that the SSI must be disabled when setting any configuration registers. */
+
+  enable = ssi_disable(priv);
+  actual = ssi_setfrequencyinternal(priv, frequency);
+  ssi_enable(priv, enable);
+  return actual;
+}
+
+/****************************************************************************
+ * Name: ssi_setmode
+ *
+ * Description:
+ *   Set the SPI mode. Optional.  See enum spi_mode_e for mode definitions
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   mode - The SPI mode requested
+ *
+ * Returned Value:
+ *   none
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static void ssi_setmodeinternal(struct lm_ssidev_s *priv, enum spi_mode_e mode)
+{
+  uint32_t modebits;
+  uint32_t regval;
+
+  ssidbg("mode: %d\n", mode);
+  DEBUGASSERT(priv);
+
+  /* Has the number of bits per word changed? */
+
+#ifndef CONFIG_SPI_OWNBUS
+  if (mode != priv->mode)
+    {
+#endif
+      /* Select the CTL register bits based on the selected mode */
+
+      switch (mode)
+        {
+        case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
+          modebits = 0;
+          break;
+
+        case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
+          modebits = SSI_CR0_SPH;
+          break;
+
+        case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
+          modebits = SSI_CR0_SPO;
+         break;
+
+        case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
+          modebits = SSI_CR0_SPH|SSI_CR0_SPO;
+          break;
+
+        default:
+          return;
+        }
+
+      /* Then set the selected mode: Freescale SPI format, mode0-3 */
+
+      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
+      regval |= modebits;
+      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssivdbg("CR0: %08x\n", regval);
+
+      /* Save the mode so that subsequent re-configuratins will be faster */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->mode = mode;
+    }
+#endif
+}
+
+static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
+{
+  struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev;
+  uint32_t enable;
+
+  /* NOTE that the SSI must be disabled when setting any configuration registers. */
+
+  enable = ssi_disable(priv);
+  ssi_setmodeinternal(priv, mode);
+  ssi_enable(priv, enable);
+}
+
+/****************************************************************************
+ * Name: ssi_setbits
+ *
+ * Description:
+ *   Set the number if bits per word.
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   nbits - The number of bits requests
+ *
+ * Returned Value:
+ *   none
+ *
+ * Assumption:
+ *   Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined)
+ *
+ ****************************************************************************/
+
+static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits)
+{
+  uint32_t regval;
+
+  ssidbg("nbits: %d\n", nbits);
+  DEBUGASSERT(priv);
+  if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
+    {
+      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval &= ~SSI_CR0_DSS_MASK;
+      regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
+      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssivdbg("CR0: %08x\n", regval);
+
+      priv->nbits = nbits;
+    }
+}
+
+static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits)
+{
+  struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev;
+  uint32_t enable;
+
+  /* NOTE that the SSI must be disabled when setting any configuration registers. */
+
+  enable = ssi_disable(priv);
+  ssi_setbitsinternal(priv, nbits);
+  ssi_enable(priv, enable);
+}
+
+/****************************************************************************
+ * Name: ssi_send
+ *
+ * Description:
+ *   Exchange one word on SPI
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *   wd  - The word to send.  the size of the data is determined by the
+ *         number of bits selected for the SPI interface.
+ *
+ * Returned Value:
+ *   response
+ *
+ ****************************************************************************/
+
+static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd)
+{
+  struct lm_ssidev_s *priv = (struct lm_ssidev_s*)dev;
+  uint16_t response = 0;
+
+  (void)ssi_transfer(priv, &wd, &response, 1);
+  return response;
+}
+
+/****************************************************************************
+ * Name: SPI_EXCHANGE
+ *
+ * Description:
+ *   Exahange a block of data from SPI. Required.
+ *
+ * Input Parameters:
+ *   dev      - Device-specific state data
+ *   buffer   - A pointer to the buffer of data to be sent
+ *   rxbuffer - A pointer to the buffer in which to recieve data
+ *   nwords   - the length of data that to be exchanged in units of words.
+ *              The wordsize is determined by the number of bits-per-word
+ *              selected for the SPI interface.  If nbits <= 8, the data is
+ *              packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_EXCHANGE
+static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+                         FAR void *rxbuffer, size_t nwords)
+{
+  struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev;
+  (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords);
+}
+#endif
+
+/*************************************************************************
+ * Name: ssi_sndblock
+ *
+ * Description:
+ *   Send a block of data on SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer of data to be sent
+ *   nwords - the length of data to send from the buffer in number of words.
+ *            The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_EXCHANGE
+static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
+{
+  struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev;
+  (void)ssi_transfer(priv, buffer, NULL, nwords);
+}
+#endif
+
+/****************************************************************************
+ * Name: ssi_recvblock
+ *
+ * Description:
+ *   Revice a block of data from SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer in which to recieve data
+ *   nwords - the length of data that can be received in the buffer in number
+ *            of words.  The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_EXCHANGE
+static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
+{
+  struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev;
+  (void)ssi_transfer(priv, NULL, buffer, nwords);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_spiinitialize
+ *
+ * Description:
+ *   Initialize common parts the selected SPI port.  Initialization of
+ *   chip select GPIOs must have been performed by board specific logic
+ *   prior to calling this function.  Specifically:  GPIOs should have
+ *   been configured for output, and all chip selects disabled.
+ *
+ *   One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select.  However,
+ *   If multiple devices on on the bus, then multiple chip selects will be
+ *   required.  Theregore, all GPIO chip management is deferred to board-
+ *   specific logic.
+ *
+ * Input Parameter:
+ *   Port number (for hardware that has mutiple SSI interfaces)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *up_spiinitialize(int port)
+{
+  struct lm_ssidev_s *priv;
+  irqstate_t flags;
+  uint8_t regval;
+
+  ssidbg("port: %d\n", port);
+ 
+  /* Set up for the selected port */
+
+  flags = irqsave();
+  switch (port)
+    {
+#ifndef CONFIG_SSI0_DISABLE
+    case 0:
+      /* Select SSI0 */
+
+      priv = &g_ssidev[SSI0_NDX];
+
+      /* Enable the SSI0 peripheral */
+
+      regval = getreg32(LM3S_SYSCON_RCGC1);
+      regval |= SYSCON_RCGC1_SSI0;
+      putreg32(regval, LM3S_SYSCON_RCGC1);
+      ssivdbg("RCGC1: %08x\n", regval);
+
+      /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
+       * logic in this file makes no assumptions about chip select)
+       */
+
+      lm_configgpio(GPIO_SSI0_CLK);  /* PA2: SSI0 clock (SSI0Clk) */
+   /* lm_configgpio(GPIO_SSI0_FSS);     PA3: SSI0 frame (SSI0Fss) */
+      lm_configgpio(GPIO_SSI0_RX);   /* PA4: SSI0 receive (SSI0Rx) */
+      lm_configgpio(GPIO_SSI0_TX);   /* PA5: SSI0 transmit (SSI0Tx) */
+      break;
+#endif /* CONFIG_SSI0_DISABLE */
+
+#ifndef CONFIG_SSI1_DISABLE
+    case 1:
+      /* Select SSI0 */
+
+      priv = &g_ssidev[SSI1_NDX];
+
+      /* Enable the SSI1 peripheral */
+
+      regval = getreg32(LM3S_SYSCON_RCGC1);
+      regval |= SYSCON_RCGC1_SSI1;
+      putreg32(regval, LM3S_SYSCON_RCGC1);
+      ssivdbg("RCGC1: %08x\n", regval);
+
+      /* Configure SSI1 GPIOs */
+
+      lm_configgpio(GPIO_SSI1_CLK);  /* PE0: SSI1 clock (SSI1Clk) */
+   /* lm_configgpio(GPIO_SSI1_FSS);     PE1: SSI1 frame (SSI1Fss) */
+      lm_configgpio(GPIO_SSI1_RX);   /* PE2: SSI1 receive (SSI1Rx) */
+      lm_configgpio(GPIO_SSI1_TX);   /* PE3: SSI1 transmit (SSI1Tx) */
+      break;
+#endif /* CONFIG_SSI1_DISABLE */
+
+    default:
+      irqrestore(flags);
+      return NULL;
+    }
+
+  /* Initialize the state structure */
+
+#ifndef CONFIG_SSI_POLLWAIT
+  sem_init(&priv->xfrsem, 0, 0);
+#endif
+#ifndef CONFIG_SPI_OWNBUS
+  sem_init(&priv->exclsem, 0, 1);
+#endif
+
+  /* Set all CR1 fields to reset state.  This will be master mode. */
+
+  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0);
+
+  /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
+
+  ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0);
+
+  /* Set the initial mode to mode 0.  The application may override
+   * this initial setting using the setmode() method.
+   */
+
+  ssi_setmodeinternal(priv, SPIDEV_MODE0);
+
+  /* Set the initial data width to 8-bits.  The application may
+   * override this initial setting using the setbits() method.
+   */
+
+  ssi_setbitsinternal(priv, 8);
+
+  /* Pick some initialize clock frequency. 400,000Hz is the startup
+   * MMC/SD frequency used for card detection.  The application may
+   * override this setting using the setfrequency() method.
+   */
+
+  ssi_setfrequencyinternal(priv, 400000);
+
+  /* Disable all SSI interrupt sources.  They will be enabled only
+   * while there is an SSI transfer in progress.
+   */
+
+  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
+
+  /* Attach the interrupt */
+
+#ifndef CONFIG_SSI_POLLWAIT
+#if NSSI_ENABLED > 1
+  irq_attach(priv->irq, (xcpt_t)ssi_interrupt);
+#else
+  irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt);
+#endif
+#endif /* CONFIG_SSI_POLLWAIT */
+
+  /* Enable the SSI for operation */
+
+  ssi_enable(priv, SSI_CR1_SSE);
+
+  /* Enable SSI interrupts (They are still disabled at the source). */
+
+#ifndef CONFIG_SSI_POLLWAIT
+#if NSSI_ENABLED > 1
+  up_enable_irq(priv->irq);
+#else
+  up_enable_irq(SSI_IRQ);
+#endif
+#endif /* CONFIG_SSI_POLLWAIT */
+
+  irqrestore(flags);
+  return (FAR struct spi_dev_s *)priv;
+}
+
+#endif /* NSSI_ENABLED > 0 */
diff --git a/nuttx/arch/arm/src/lm/lm_ssi.h b/nuttx/arch/arm/src/lm/lm_ssi.h
index 4e7119898..07cd2ce77 100644
--- a/nuttx/arch/arm/src/lm/lm_ssi.h
+++ b/nuttx/arch/arm/src/lm/lm_ssi.h
@@ -73,20 +73,20 @@ extern "C"
  ****************************************************************************/
 
 /****************************************************************************
- * The external functions, lm3s_spiselect, lm3s_spistatus, and
- * lm3s_spicmddata must be provided by board-specific logic.  These are
+ * The external functions, lm_spiselect, lm_spistatus, and
+ * lm_spicmddata must be provided by board-specific logic.  These are
  * implementations of the select, status, and cmddata methods of the SPI
  * interface defined by struct spi_ops_s (see include/nuttx/spi.h).
  * All other methods (including up_spiinitialize()) are provided by common
  * logic.  To use this common SPI logic on your board:
  *
- *   1. Provide logic in lm3s_boardinitialize() to configure SPI chip select
+ *   1. Provide logic in lm_boardinitialize() to configure SPI chip select
  *      pins.
- *   2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
+ *   2. Provide lm_spiselect() and lm_spistatus() functions in your
  *      board-specific logic.  These functions will perform chip selection and
  *      status operations using GPIOs in the way your board is configured.
  *   3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide
- *      the lm3s_spicmddata() function in your board-specific logic.  This
+ *      the lm_spicmddata() function in your board-specific logic.  This
  *      functions will perform cmd/data selection operations using GPIOs in
  *      the way your board is configured.
  *   4. Add a call to up_spiinitialize() in your low level application
@@ -100,10 +100,10 @@ extern "C"
 
 struct spi_dev_s;
 enum spi_dev_e;
-void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
 #ifdef CONFIG_SPI_CMDDATA
-int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+int lm_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
 #endif
 
 #if defined(__cplusplus)
diff --git a/nuttx/arch/arm/src/lm/lm_start.c b/nuttx/arch/arm/src/lm/lm_start.c
new file mode 100644
index 000000000..f4985709e
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_start.c
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_start.c
+ * arch/arm/src/chip/lm_start.c
+ *
+ *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "lm_lowputc.h"
+#include "lm_syscontrol.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern void lm_vectors(void);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ *   Print a character on the UART to show boot status.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+#  define showprogress(c) up_lowputc(c)
+#else
+#  define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _start
+ *
+ * Description:
+ *   This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+  const uint32_t *src;
+  uint32_t *dest;
+
+  /* Configure the uart so that we can get debug output as soon as possible */
+
+  up_clockconfig();
+  up_lowsetup();
+  showprogress('A');
+
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+   * certain that there are no issues with the state of global variables.
+   */
+
+  for (dest = &_sbss; dest < &_ebss; )
+    {
+      *dest++ = 0;
+    }
+  showprogress('B');
+
+  /* Move the intialized data section from his temporary holding spot in
+   * FLASH into the correct place in SRAM.  The correct place in SRAM is
+   * give by _sdata and _edata.  The temporary location is in FLASH at the
+   * end of all of the other read-only data (.text, .rodata) at _eronly.
+   */
+
+  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
+    {
+      *dest++ = *src++;
+    }
+  showprogress('C');
+
+  /* Perform early serial initialization */
+
+#ifdef USE_EARLYSERIALINIT
+  up_earlyserialinit();
+#endif
+  showprogress('D');
+
+  /* Initialize onboard resources */
+
+  lm_boardinitialize();
+  showprogress('E');
+
+  /* Then start NuttX */
+
+  showprogress('\r');
+  showprogress('\n');
+  os_start();
+
+  /* Shoulnd't get here */
+
+  for(;;);
+}
diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.c b/nuttx/arch/arm/src/lm/lm_syscontrol.c
new file mode 100644
index 000000000..f0d0bd3c9
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_syscontrol.c
@@ -0,0 +1,315 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_syscontrol.c
+ * arch/arm/src/chip/lm_syscontrol.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "chip.h"
+#include "lm_syscontrol.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define RCC_OSCMASK   (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
+#define RCC_XTALMASK  (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN)
+#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2)
+#define RCC_DIVMASK   (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
+#define RCC2_DIVMASK  (SYSCON_RCC2_SYSDIV2_MASK)
+#define FAST_OSCDELAY (512*1024)
+#define SLOW_OSCDELAY (4*1024)
+#define PLLLOCK_DELAY (32*1024)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm_delay
+ *
+ * Description:
+ *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
+ *   the time that we wait can be significant and is determined by the previous
+ *   clock setting, not the one that we are configuring.
+ *
+ ****************************************************************************/
+
+static inline void lm_delay(uint32_t delay)
+{
+  __asm__ __volatile__("1:\n"
+                       "\tsubs  %0, #1\n"
+                       "\tbne   1b\n"
+                       : "=r"(delay) : "r"(delay));
+}
+
+/****************************************************************************
+ * Name: lm_oscdelay
+ *
+ * Description:
+ *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
+ *   the time that we wait can be significant and is determined by the previous
+ *   clock setting, not the one that we are configuring.
+ *
+ ****************************************************************************/
+
+static inline void lm_oscdelay(uint32_t rcc, uint32_t rcc2)
+{
+  /* Wait for the oscillator  to stabilize.  A smaller delay is used if the
+   * current clock rate is very slow.
+   */
+
+  uint32_t delay = FAST_OSCDELAY;
+
+  /* Are we currently using RCC2? */
+
+  if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
+    {
+      uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK;
+      if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) ||
+          (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ))
+        {
+          delay = SLOW_OSCDELAY;
+        }
+    }
+
+  /* No.. using srce in RCC */
+
+  else
+    {
+      uint32_t rccsrc  = rcc  & SYSCON_RCC_OSCSRC_MASK;
+      if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ)
+        {
+          delay = SLOW_OSCDELAY;
+        }
+    }
+
+  /* Then delay that number of loops */
+
+  lm_delay(delay);
+}
+
+/****************************************************************************
+ * Name: lm_plllock
+ *
+ * Description:
+ *   The new RCC values have been selected... wait for the PLL to lock on
+ *
+ ****************************************************************************/
+
+static inline void lm_plllock(void)
+{
+  volatile uint32_t delay;
+
+  /* Loop until the lock is achieved or until a timeout occurs */
+
+  for (delay = PLLLOCK_DELAY; delay > 0; delay--)
+    {
+      /* Check if the PLL is locked on */
+
+      if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
+        {
+          /* Yes.. return now */
+
+          return;
+        }
+    }
+
+  /* If we get here, then PLL lock was not achieved */
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm_clockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on desired rcc and rcc2 settings.
+ *   This is use to set up the initial clocking but can be used later to
+ *   support slow clocked, low power consumption modes.
+ *
+ ****************************************************************************/
+
+void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
+{
+  uint32_t rcc;
+  uint32_t rcc2;
+
+  /* Get the current values of the RCC and RCC2 registers */
+
+  rcc  = getreg32(LM3S_SYSCON_RCC);
+  rcc2 = getreg32(LM3S_SYSCON_RCC2);
+
+  /* Temporarily bypass the PLL and system clock dividers */
+
+  rcc |= SYSCON_RCC_BYPASS;
+  rcc &= ~(SYSCON_RCC_USESYSDIV);
+  putreg32(rcc, LM3S_SYSCON_RCC);
+
+  rcc2 |= SYSCON_RCC2_BYPASS2;
+  putreg32(rcc2, LM3S_SYSCON_RCC2);
+
+  /* We are probably using the main oscillator.  The main oscillator is disabled on
+   * reset and so probably must be enabled here.  The internal oscillator is enabled
+   * on rest and if that is selected, most likely nothing needs to be done.
+   */
+
+  if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) ||
+      ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS)))
+    {
+      /* Enable any selected osciallators (but don't disable any yet) */
+
+      rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
+      putreg32(rcc, LM3S_SYSCON_RCC);
+
+      /* Wait for the newly selected oscillator(s) to settle.  This is tricky because
+       * the time that we wait can be significant and is determined by the previous
+       * clock setting, not the one that we are configuring.
+       */
+
+      lm_oscdelay(rcc, rcc2);
+    }
+
+  /* Set the new crystal value, oscillator source and PLL configuration */
+
+  rcc  &= ~RCC_XTALMASK;
+  rcc  |= newrcc & RCC_XTALMASK;
+
+  rcc2 &= ~RCC2_XTALMASK;
+  rcc2 |= newrcc2 & RCC2_XTALMASK;
+
+  /* Clear the PLL lock interrupt */
+
+  putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC);
+
+  /* Write the new RCC/RCC2 values.  Order depends upon whether RCC2 or RCC
+   * is currently enabled.
+   */
+
+  if (rcc2 & SYSCON_RCC2_USERCC2)
+    {
+      putreg32(rcc2, LM3S_SYSCON_RCC2);
+      putreg32(rcc, LM3S_SYSCON_RCC);
+    }
+    else
+    {
+      putreg32(rcc, LM3S_SYSCON_RCC);
+      putreg32(rcc2, LM3S_SYSCON_RCC2);
+    }
+
+  /* Wait for the new crystal value and oscillator source to take effect */
+
+  lm_delay(16);
+
+  /* Set the requested system divider and disable the non-selected osciallators */
+
+  rcc &= ~RCC_DIVMASK;
+  rcc |= newrcc & RCC_DIVMASK;
+
+  rcc2 &= ~RCC2_DIVMASK;
+  rcc2 |= newrcc2 & RCC2_DIVMASK;
+
+  /* Will the PLL output be used to clock the system? */
+
+  if ((newrcc & SYSCON_RCC_BYPASS) == 0)
+    {
+      /* Yes, wail untill the PLL is locked */
+
+      lm_plllock();
+
+      /* Then enable the PLL */
+
+      rcc  &= ~SYSCON_RCC_BYPASS;
+      rcc2 &= ~SYSCON_RCC2_BYPASS2;
+    }
+
+  /* Now we can set the final RCC/RCC2 values */
+
+  putreg32(rcc, LM3S_SYSCON_RCC);
+  putreg32(rcc2, LM3S_SYSCON_RCC2);
+
+  /* Wait for the system divider to be effective */
+
+  lm_delay(6);
+}
+
+/****************************************************************************
+ * Name: up_clockconfig
+ *
+ * Description:
+ *   Called early in the bootsequence (before .data and .bss are available)
+ *   in order to configure initial clocking.
+ *
+ ****************************************************************************/
+
+void up_clockconfig(void)
+{
+#ifdef CONFIG_LM_REVA2
+  /* Some early silicon returned an increase LDO voltage or 2.75V to work
+   * around a PLL bug
+   */
+
+  putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL);
+#endif
+
+  /* Set the clocking to run with the default settings provided in the board.h
+   * header file
+   */
+
+  lm_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE);
+}
+
diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.h b/nuttx/arch/arm/src/lm/lm_syscontrol.h
index 79cc2349d..98fbc81cb 100644
--- a/nuttx/arch/arm/src/lm/lm_syscontrol.h
+++ b/nuttx/arch/arm/src/lm/lm_syscontrol.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lm/lm3s_syscontrol.h
+ * arch/arm/src/lm/lm_syscontrol.h
  *
  *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -70,7 +70,7 @@ extern "C"
  ****************************************************************************/
 
 /****************************************************************************
- * Name: lm3s_clockconfig
+ * Name: lm_clockconfig
  *
  * Description:
  *   Called to change to new clock based on desired rcc and rcc2 settings.
@@ -79,7 +79,7 @@ extern "C"
  *
  ****************************************************************************/
 
-void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2);
+void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2);
 
 /****************************************************************************
  * Name: up_clockconfig
diff --git a/nuttx/arch/arm/src/lm/lm_timerisr.c b/nuttx/arch/arm/src/lm/lm_timerisr.c
new file mode 100644
index 000000000..0469a473b
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_timerisr.c
@@ -0,0 +1,142 @@
+/****************************************************************************
+ * arch/arm/src/lm/lm_timerisr.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "nvic.h"
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ *
+ * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h
+ * header file.
+ */
+
+#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1)
+
+/* The size of the reload field is 24 bits.  Verify taht the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32_t *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+  uint32_t regval;
+
+  /* Set the SysTick interrupt to the default priority */
+
+  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
+  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
+  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
+  putreg32(regval, NVIC_SYSH12_15_PRIORITY);
+
+  /* Configure SysTick to interrupt at the requested rate */
+
+  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr);
+
+  /* Enable SysTick interrupts */
+
+  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(LM3S_IRQ_SYSTICK);
+}
diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S
new file mode 100644
index 000000000..93350a9ff
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/lm_vectors.S
@@ -0,0 +1,805 @@
+/************************************************************************************
+ * arch/arm/src/lm/lm_vectors.S
+ * arch/arm/src/chip/lm_vectors.S
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/irq.h>
+
+/************************************************************************************
+ * Preprocessor Definitions
+ ************************************************************************************/
+
+/* Memory Map:
+ *
+ * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
+ * 0x0002:0000 - Address of vectors if using bootloader
+ * 0x0003:ffff - End of flash
+ * 0x2000:0000 - Start of SRAM and start of .data (_sdata)
+ *             - End of .data (_edata) abd start of .bss (_sbss)
+ *             - End of .bss (_ebss) and bottom of idle stack
+ *             - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap
+ * 0x2000:ffff - End of SRAM and end of heap
+ */
+
+#define IDLE_STACK		(_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
+#define HEAP_BASE		(_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
+
+/* The Cortex-M3 return from interrupt is unusual.  We provide the following special
+ * address to the BX instruction.  The particular value also forces a return to
+ * thread mode and covers state from the main stack point, the MSP (vs. the MSP).
+ */
+
+#define EXC_RETURN		0xfffffff9
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.globl		__start
+
+	.syntax		unified
+	.thumb
+	.file		"lm_vectors.S"
+
+/************************************************************************************
+ * Macros
+ ************************************************************************************/
+
+/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
+ * registers on the stack, then branches to an instantantiation of the following
+ * macro.  This macro simply loads the IRQ number into R0, then jumps to the common
+ * IRQ handling logic.
+ */
+
+	.macro	HANDLER, label, irqno
+	.thumb_func
+\label:
+	mov		r0, #\irqno
+	b		lm_irqcommon
+	.endm
+
+/************************************************************************************
+ * Vectors
+ ************************************************************************************/
+
+	.section	.vectors, "ax"
+	.code		16
+	.align		2
+	.globl		lm_vectors
+	.type		lm_vectors, function
+
+lm_vectors:
+
+/* Processor Exceptions */
+
+	.word	IDLE_STACK			/* Vector  0: Reset stack pointer */
+	.word	__start				/* Vector  1: Reset vector */
+	.word	lm_nmi				/* Vector  2: Non-Maskable Interrupt (NMI) */
+	.word	lm_hardfault		/* Vector  3: Hard fault */
+	.word	lm_mpu				/* Vector  4: Memory management (MPU) */
+	.word	lm_busfault			/* Vector  5: Bus fault */
+	.word	lm_usagefault		/* Vector  6: Usage fault */
+	.word	lm_reserved			/* Vector  7: Reserved */
+	.word	lm_reserved			/* Vector  8: Reserved */
+	.word	lm_reserved			/* Vector  9: Reserved */
+	.word	lm_reserved			/* Vector 10: Reserved */
+	.word	lm_svcall			/* Vector 11: SVC call */
+	.word	lm_dbgmonitor		/* Vector 12: Debug monitor */
+	.word	lm_reserved			/* Vector 13: Reserved */
+	.word	lm_pendsv			/* Vector 14: Pendable system service request */
+	.word	lm_systick			/* Vector 15: System tick */
+
+/* External Interrupts */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+	.word	lm_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm_uart0			/* Vector 21: UART 0 */
+	.word	lm_uart1			/* Vector 22: UART 1 */
+	.word	lm_ssi0				/* Vector 23: SSI 0 */
+	.word	lm_i2c0				/* Vector 24: I2C 0 */
+	.word	lm_reserved			/* Vector 25: Reserved */
+	.word	lm_reserved			/* Vector 26: Reserved */
+	.word	lm_reserved			/* Vector 27: Reserved */
+	.word	lm_reserved			/* Vector 28: Reserved */
+	.word	lm_reserved			/* Vector 29: Reserved */
+	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
+	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
+	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
+	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
+	.word	lm_wdog				/* Vector 34: Watchdog Timer */
+	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
+	.word	lm_cmp1				/* Vector 42: Analog Comparator 1 */
+	.word	lm_reserved			/* Vector 43: Reserved */
+	.word	lm_syscon			/* Vector 44: System Control */
+	.word	lm_flashcon			/* Vector 45: FLASH Control */
+	.word	lm_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm_gpioh			/* Vector 48: GPIO Port H */
+	.word	lm_reserved			/* Vector 49: Reserved */
+	.word	lm_ssi1				/* Vector 50: SSI 1 */
+	.word	lm_tmr3a			/* Vector 51: Timer 3 A */
+	.word	lm_tmr3b			/* Vector 52: Timer 3 B */
+	.word	lm_i2c1				/* Vector 53: I2C 1 */
+	.word	lm_reserved			/* Vector 54: Reserved */
+	.word	lm_reserved			/* Vector 55: Reserved */
+	.word	lm_reserved			/* Vector 56: Reserved */
+	.word	lm_reserved			/* Vector 57: Reserved */
+ 	.word	lm_eth				/* Vector 58: Ethernet Controller */
+	.word	lm_hib				/* Vector 59: Hibernation Module */
+	.word	lm_reserved			/* Vector 60: Reserved */
+	.word	lm_reserved			/* Vector 61: Reserved */
+	.word	lm_reserved			/* Vector 62: Reserved */
+	.word	lm_reserved			/* Vector 63: Reserved */
+	.word	lm_reserved			/* Vector 64: Reserved */
+	.word	lm_reserved			/* Vector 65: Reserved */
+	.word	lm_reserved			/* Vector 66: Reserved */
+	.word	lm_reserved			/* Vector 67: Reserved */
+	.word	lm_reserved			/* Vector 68: Reserved */
+	.word	lm_reserved			/* Vector 69: Reserved */
+	.word	lm_reserved			/* Vector 70: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+	.word	lm_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm_uart0			/* Vector 21: UART 0 */
+	.word	lm_uart1			/* Vector 22: UART 1 */
+	.word	lm_ssi0				/* Vector 23: SSI 0 */
+	.word	lm_i2c0				/* Vector 24: I2C 0 */
+	.word	lm_reserved			/* Vector 25: Reserved */
+	.word	lm_pwm0				/* Vector 26: PWM Generator 0 */
+	.word	lm_reserved			/* Vector 27: Reserved */
+	.word	lm_reserved			/* Vector 28: Reserved */
+	.word	lm_reserved			/* Vector 29: Reserved */
+	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
+	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
+	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
+	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
+	.word	lm_wdog				/* Vector 34: Watchdog Timer */
+	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
+	.word	lm_cmp1				/* Vector 42: Analog Comparator 1 */
+	.word	lm_reserved			/* Vector 43: Reserved */
+	.word	lm_syscon			/* Vector 44: System Control */
+	.word	lm_flashcon			/* Vector 45: FLASH Control */
+	.word	lm_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm_reserved			/* Vector 48: Reserved */
+	.word	lm_reserved			/* Vector 49: Reserved */
+	.word	lm_reserved			/* Vector 50: Reserved */
+	.word	lm_reserved			/* Vector 51: Reserved */
+	.word	lm_reserved			/* Vector 52: Reserved */
+	.word	lm_reserved			/* Vector 53: Reserved */
+	.word	lm_reserved			/* Vector 54: Reserved */
+	.word	lm_reserved			/* Vector 55: Reserved */
+	.word	lm_reserved			/* Vector 56: Reserved */
+	.word	lm_reserved			/* Vector 57: Reserved */
+ 	.word	lm_eth				/* Vector 58: Ethernet Controller */
+	.word	lm_reserved			/* Vector 59: Reserved */
+	.word	lm_reserved			/* Vector 60: Reserved */
+	.word	lm_reserved			/* Vector 61: Reserved */
+	.word	lm_reserved			/* Vector 62: Reserved */
+	.word	lm_reserved			/* Vector 63: Reserved */
+	.word	lm_reserved			/* Vector 64: Reserved */
+	.word	lm_reserved			/* Vector 65: Reserved */
+	.word	lm_reserved			/* Vector 66: Reserved */
+	.word	lm_reserved			/* Vector 67: Reserved */
+	.word	lm_reserved			/* Vector 68: Reserved */
+	.word	lm_reserved			/* Vector 69: Reserved */
+	.word	lm_reserved			/* Vector 70: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+	.word	lm_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm_uart0			/* Vector 21: UART 0 */
+	.word	lm_uart1			/* Vector 22: UART 1 */
+	.word	lm_ssi0				/* Vector 23: SSI 0 */
+	.word	lm_i2c0				/* Vector 24: I2C 0 */
+	.word	lm_pwmfault			/* Vector 25: PWM Fault */
+	.word	lm_pwm0				/* Vector 26: PWM Generator 0 */
+	.word	lm_pwm1				/* Vector 27: PWM Generator 1 */
+	.word	lm_pwm2				/* Vector 28: PWM Generator 2 */
+	.word	lm_qei0				/* Vector 29: QEI0 */
+	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
+	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
+	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
+	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
+	.word	lm_wdog				/* Vector 34: Watchdog Timer */
+	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
+	.word	lm_cmp1				/* Vector 42: Analog Comparator 1 */
+	.word	lm_reserved			/* Vector 43: Reserved */
+	.word	lm_syscon			/* Vector 44: System Control */
+	.word	lm_flashcon			/* Vector 45: FLASH Control */
+	.word	lm_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm_reserved			/* Vector 48: Reserved */
+	.word	lm_uart2			/* Vector 49: UART 2 */
+	.word	lm_reserved			/* Vector 50: Reserved */
+	.word	lm_tmr3a			/* Vector 51: Timer 3 A */
+	.word	lm_tmr3b			/* Vector 52: Timer 3 B */
+	.word	lm_i2c1				/* Vector 53: I2C 1 */
+	.word	lm_qei1				/* Vector 54: QEI1 */
+	.word	lm_reserved			/* Vector 55: Reserved */
+	.word	lm_reserved			/* Vector 56: Reserved */
+	.word	lm_reserved			/* Vector 57: Reserved */
+ 	.word	lm_eth				/* Vector 58: Ethernet Controller */
+	.word	lm_hib				/* Vector 59: Hibernation Module */
+	.word	lm_reserved			/* Vector 60: Reserved */
+	.word	lm_reserved			/* Vector 61: Reserved */
+	.word	lm_reserved			/* Vector 62: Reserved */
+	.word	lm_reserved			/* Vector 63: Reserved */
+	.word	lm_reserved			/* Vector 64: Reserved */
+	.word	lm_reserved			/* Vector 65: Reserved */
+	.word	lm_reserved			/* Vector 66: Reserved */
+	.word	lm_reserved			/* Vector 67: Reserved */
+	.word	lm_reserved			/* Vector 68: Reserved */
+	.word	lm_reserved			/* Vector 69: Reserved */
+	.word	lm_reserved			/* Vector 70: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+	.word	lm_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm_uart0			/* Vector 21: UART 0 */
+	.word	lm_uart1			/* Vector 22: UART 1 */
+	.word	lm_ssi0				/* Vector 23: SSI 0 */
+	.word	lm_i2c0				/* Vector 24: I2C 0 */
+	.word	lm_pwmfault			/* Vector 25: PWM Fault */
+	.word	lm_pwm0				/* Vector 26: PWM Generator 0 */
+	.word	lm_pwm1				/* Vector 27: PWM Generator 1 */
+	.word	lm_pwm2				/* Vector 28: PWM Generator 2 */
+	.word	lm_qei0				/* Vector 29: QEI0 */
+	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
+	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
+	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
+	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
+	.word	lm_wdog				/* Vector 34: Watchdog Timer */
+	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
+	.word	lm_cmp1				/* Vector 42: Analog Comparator 1 */
+	.word	lm_cmp2				/* Vector 43: Reserved */
+	.word	lm_syscon			/* Vector 44: System Control */
+	.word	lm_flashcon			/* Vector 45: FLASH Control */
+	.word	lm_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm_gpioh			/* Vector 48: GPIO Port H */
+	.word	lm_uart2			/* Vector 49: UART 2 */
+	.word	lm_ssi1				/* Vector 50: SSI 1 */
+	.word	lm_tmr3a			/* Vector 51: Timer 3 A */
+	.word	lm_tmr3b			/* Vector 52: Timer 3 B */
+	.word	lm_i2c1				/* Vector 53: I2C 1 */
+	.word	lm_qei1				/* Vector 54: QEI1 */
+	.word	lm_can0				/* Vector 55: CAN 0 */
+	.word	lm_can1				/* Vector 56: CAN 1 */
+	.word	lm_reserved			/* Vector 57: Reserved */
+ 	.word	lm_eth				/* Vector 58: Ethernet Controller */
+	.word	lm_reserved			/* Vector 59: Reserved */
+	.word	lm_usb				/* Vector 60: USB */
+	.word	lm_pwm3				/* Vector 61: PWM 3 */
+	.word	lm_udmasoft			/* Vector 62: uDMA Software */
+	.word	lm_udmaerror		/* Vector 63: uDMA Error */
+	.word	lm_adc1_0			/* Vector 64: ADC1 Sequence 0 */
+	.word	lm_adc1_1			/* Vector 65: ADC1 Sequence 1 */
+	.word	lm_adc1_2			/* Vector 66: ADC1 Sequence 2 */
+	.word	lm_adc1_3			/* Vector 67: ADC1 Sequence 3 */
+	.word	lm_i2s0 			/* Vector 68: I2S 0 */
+	.word	lm_epi				/* Vector 69: Reserved */
+	.word	lm_gpioj			/* Vector 70: GPIO J */
+	.word	lm_reserved			/* Vector 71: Reserved */
+	#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+	.word	lm_gpioa			/* Vector 16: GPIO Port A */
+	.word	lm_gpiob			/* Vector 17: GPIO Port B */
+	.word	lm_gpioc			/* Vector 18: GPIO Port C */
+	.word	lm_gpiod			/* Vector 19: GPIO Port D */
+	.word	lm_gpioe			/* Vector 20: GPIO Port E */
+	.word	lm_uart0			/* Vector 21: UART 0 */
+	.word	lm_uart1			/* Vector 22: UART 1 */
+	.word	lm_ssi0				/* Vector 23: SSI 0 */
+	.word	lm_i2c0				/* Vector 24: I2C 0 */
+	.word	lm_pwmfault			/* Vector 25: PWM Fault */
+	.word	lm_pwm0				/* Vector 26: PWM Generator 0 */
+	.word	lm_pwm1				/* Vector 27: PWM Generator 1 */
+	.word	lm_pwm2				/* Vector 28: PWM Generator 2 */
+	.word	lm_qei0				/* Vector 29: QEI0 */
+	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
+	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
+	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
+	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
+	.word	lm_wdog				/* Vector 34: Watchdog Timer */
+	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
+	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
+	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
+	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
+	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
+	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
+	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
+	.word	lm_reserved			/* Vector 42: Reserved */
+	.word	lm_reserved			/* Vector 43: Reserved */
+	.word	lm_syscon			/* Vector 44: System Control */
+	.word	lm_flashcon			/* Vector 45: FLASH Control */
+	.word	lm_gpiof			/* Vector 46: GPIO Port F */
+	.word	lm_gpiog			/* Vector 47: GPIO Port G */
+	.word	lm_reserved			/* Vector 48: Reserved */
+	.word	lm_reserved			/* Vector 49: Reserved */
+	.word	lm_reserved			/* Vector 50: Reserved */
+	.word	lm_tmr3a			/* Vector 51: Timer 3 A */
+	.word	lm_tmr3b			/* Vector 52: Timer 3 B */
+	.word	lm_reserved			/* Vector 53: Reserved*/
+	.word	lm_qei1				/* Vector 54: QEI1 */
+	.word	lm_can0				/* Vector 55: Can Controller */
+	.word	lm_reserved			/* Vector 56: Reserved */
+	.word	lm_reserved			/* Vector 57: Reserved */
+ 	.word	lm_eth				/* Vector 58: Ethernet Controller */
+	.word	lm_hib				/* Vector 59: Hibernation Module */
+	.word	lm_reserved			/* Vector 60: Reserved */
+	.word	lm_reserved			/* Vector 61: Reserved */
+	.word	lm_reserved			/* Vector 62: Reserved */
+	.word	lm_reserved			/* Vector 63: Reserved */
+	.word	lm_reserved			/* Vector 64: Reserved */
+	.word	lm_reserved			/* Vector 65: Reserved */
+	.word	lm_reserved			/* Vector 66: Reserved */
+	.word	lm_reserved			/* Vector 67: Reserved */
+	.word	lm_reserved			/* Vector 68: Reserved */
+	.word	lm_reserved			/* Vector 69: Reserved */
+	.word	lm_reserved			/* Vector 70: Reserved */
+#else
+#  error "Vectors not specified for this LM3S chip"
+#endif
+	.size	lm_vectors, .-lm_vectors
+
+/************************************************************************************
+ * .text
+ ************************************************************************************/
+
+	.text
+	.type	handlers, function
+	.thumb_func
+handlers:
+	HANDLER	lm_reserved, LM3S_IRQ_RESERVED		/* Unexpected/reserved vector */
+	HANDLER	lm_nmi, LM3S_IRQ_NMI					/* Vector  2: Non-Maskable Interrupt (NMI) */
+	HANDLER	lm_hardfault, LM3S_IRQ_HARDFAULT		/* Vector  3: Hard fault */
+	HANDLER	lm_mpu, LM3S_IRQ_MEMFAULT				/* Vector  4: Memory management (MPU) */
+	HANDLER	lm_busfault, LM3S_IRQ_BUSFAULT		/* Vector  5: Bus fault */
+	HANDLER	lm_usagefault, LM3S_IRQ_USAGEFAULT	/* Vector  6: Usage fault */
+	HANDLER	lm_svcall, LM3S_IRQ_SVCALL			/* Vector 11: SVC call */
+	HANDLER	lm_dbgmonitor, LM3S_IRQ_DBGMONITOR	/* Vector 12: Debug Monitor */
+	HANDLER	lm_pendsv, LM3S_IRQ_PENDSV			/* Vector 14: Penable system service request */
+	HANDLER	lm_systick, LM3S_IRQ_SYSTICK			/* Vector 15: System tick */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
+	HANDLER	lm_gpioh, LM3S_IRQ_GPIOH			/* Vector 48: GPIO Port H */
+	HANDLER	lm_ssi1, LM3S_IRQ_SSI1				/* Vector 50: SSI 1 */
+	HANDLER	lm_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
+ 	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
+ 	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
+	HANDLER	lm_uart2, LM3S_IRQ_UART1			/* Vector 49: UART 1 */
+	HANDLER	lm_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER lm_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
+ 	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
+	HANDLER	lm_uart2, LM3S_IRQ_UART1			/* Vector 49: UART 1 */
+	HANDLER	lm_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER	lm_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
+	HANDLER	lm_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
+ 	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm_cmp2, LM3S_IRQ_COMPARE2			/* Vector 43: Analog Comparator 2 */
+	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
+	HANDLER	lm_gpioh, LM3S_IRQ_GPIOH			/* Vector 48: GPIO Port H */
+	HANDLER	lm_uart2, LM3S_IRQ_UART2			/* Vector 49: UART 2 */
+	HANDLER	lm_ssi1, LM3S_IRQ_SSI1				/* Vector 50: GPIO Port H */
+	HANDLER	lm_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER	lm_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
+ 	HANDLER	lm_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
+	HANDLER	lm_can1, LM3S_IRQ_CAN1				/* Vector 56: CAN 1 */
+	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+ 	HANDLER	lm_usb, LM3S_IRQ_USB				/* Vector 60: USB */
+ 	HANDLER	lm_pwm3, LM3S_IRQ_PWM3				/* Vector 61: PWM 3  */
+ 	HANDLER	lm_udmasoft, LM3S_IRQ_UDMASOFT		/* Vector 62: uDMA Software  */
+ 	HANDLER	lm_udmaerror, LM3S_IRQ_UDMAERROR	/* Vector 63: uDMA Error */
+ 	HANDLER	lm_adc1_0, LM3S_IRQ_ADC1_0			/* Vector 64: ADC1 Sequence 0 */
+ 	HANDLER	lm_adc1_1, LM3S_IRQ_ADC1_1			/* Vector 65: ADC1 Sequence 1 */
+ 	HANDLER	lm_adc1_2, LM3S_IRQ_ADC1_2			/* Vector 66: ADC1 Sequence 2 */
+ 	HANDLER	lm_adc1_3, LM3S_IRQ_ADC1_3			/* Vector 67: ADC1 Sequence 3 */
+ 	HANDLER	lm_i2s0, LM3S_IRQ_I2S0				/* Vector 68: I2S 0 */
+ 	HANDLER	lm_epi, LM3S_IRQ_EPI				/* Vector 69: EPI  */
+ 	HANDLER	lm_gpioj, LM3S_IRQ_GPIOJ			/* Vector 70: GPIO Port J */
+#else
+#  error "Vectors not specified for this LM3S chip"
+#endif
+
+/* Common IRQ handling logic.  On entry here, the return stack is on either
+ * the PSP or the MSP and looks like the following:
+ *
+ *      REG_XPSR
+ *      REG_R15
+ *      REG_R14
+ *      REG_R12
+ *      REG_R3
+ *      REG_R2
+ *      REG_R1
+ * MSP->REG_R0
+ *
+ * And
+ *      R0 contains the IRQ number
+ *      R14 Contains the EXC_RETURN value
+ *      We are in handler mode and the current SP is the MSP
+ */
+
+lm_irqcommon:
+
+	/* Complete the context save */
+
+#ifdef CONFIG_NUTTX_KERNEL
+	/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
+	 * (handler mode) if the state is on the MSP.  It can only be on the PSP if
+	 * EXC_RETURN is 0xfffffffd (unprivileged thread)
+	 */
+
+	adds	r2, r14, #3				/* If R14=0xfffffffd, then r2 == 0 */
+	ite		ne						/* Next two instructions are condition */
+	mrsne	r1, msp					/* R1=The main stack pointer */
+	mrseq	r1, psp					/* R1=The process stack pointer */
+#else
+	mrs		r1, msp					/* R1=The main stack pointer */
+#endif
+
+	mov		r2, r1					/* R2=Copy of the main/process stack pointer */
+	add		r2, #HW_XCPT_SIZE		/* R2=MSP/PSP before the interrupt was taken */
+	mrs		r3, primask				/* R3=Current PRIMASK setting */
+#ifdef CONFIG_NUTTX_KERNEL 
+	stmdb	r1!, {r2-r11,r14}		/* Save the remaining registers plus the SP value */
+#else
+	stmdb	r1!, {r2-r11}			/* Save the remaining registers plus the SP value */
+#endif
+
+	/* Disable interrupts, select the stack to use for interrupt handling
+	 * and call up_doirq to handle the interrupt
+	 */
+
+	cpsid	i						/* Disable further interrupts */
+
+	/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
+	 * stack pointer.  The way that this is done here prohibits nested interrupts!
+	 * Otherwise, we will re-use the main stack for interrupt level processing.
+	 */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	ldr		sp, =g_intstackbase
+	str		r1, [sp, #-4]!			/* Save the MSP on the interrupt stack */
+	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */
+	ldr		r1, [sp, #+4]!			/* Recover R1=main stack pointer */
+#else
+	mov		sp, r1					/* We are using the main stack pointer */
+	bl		up_doirq				/* R0=IRQ, R1=register save (msp) */
+	mov		r1, sp					/* Recover R1=main stack pointer */
+#endif
+
+	/* On return from up_doirq, R0 will hold a pointer to register context
+	 * array to use for the interrupt return.  If that return value is the same
+	 * as current stack pointer, then things are relatively easy.
+	 */
+
+	cmp		r0, r1					/* Context switch? */
+	beq		1f						/* Branch if no context switch */
+
+	/* We are returning with a pending context switch.  This case is different
+	 * because in this case, the register save structure does not lie on the
+	 * stack but, rather, are within a TCB structure.  We'll have to copy some
+	 * values to the stack.
+	 */
+
+	add		r1, r0, #SW_XCPT_SIZE	/* R1=Address of HW save area in reg array */
+	ldmia	r1, {r4-r11}			/* Fetch eight registers in HW save area */
+	ldr		r1, [r0, #(4*REG_SP)]	/* R1=Value of SP before interrupt */
+	stmdb	r1!, {r4-r11}			/* Store eight registers in HW save area */
+#ifdef CONFIG_NUTTX_KERNEL 
+	ldmia	r0, {r2-r11,r14}		/* Recover R4-R11, r14 + 2 temp values */
+#else
+	ldmia	r0, {r2-r11}			/* Recover R4-R11 + 2 temp values */
+#endif
+	b		2f						/* Re-join common logic */
+
+	/* We are returning with no context switch.  We simply need to "unwind"
+	 * the same stack frame that we created
+	 */
+1:
+#ifdef CONFIG_NUTTX_KERNEL 
+	ldmia	r1!, {r2-r11,r14}		/* Recover R4-R11, r14 + 2 temp values */
+#else
+	ldmia	r1!, {r2-r11}			/* Recover R4-R11 + 2 temp values */
+#endif
+2:
+#ifdef CONFIG_NUTTX_KERNEL
+	/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
+	 * (handler mode) if the state is on the MSP.  It can only be on the PSP if
+	 * EXC_RETURN is 0xfffffffd (unprivileged thread)
+	 */
+
+	adds	r0, r14, #3				/* If R14=0xfffffffd, then r0 == 0 */
+	ite		ne						/* Next two instructions are condition */
+	msrne	msp, r1					/* R1=The main stack pointer */
+	msreq	psp, r1					/* R1=The process stack pointer */
+#else
+	msr		msp, r1					/* Recover the return MSP value */
+
+	/* Preload r14 with the special return value first (so that the return
+	 * actually occurs with interrupts still disabled).
+	 */
+
+	ldr		r14, =EXC_RETURN		/* Load the special value */
+#endif
+
+    /* Restore the interrupt state */
+
+	msr		primask, r3				/* Restore interrupts */
+
+	/* Always return with R14 containing the special value that will: (1)
+	 * return to thread mode, and (2) continue to use the MSP
+	 */
+
+	bx		r14						/* And return */
+	.size	handlers, .-handlers
+
+/************************************************************************************
+ *  Name: up_interruptstack/g_intstackbase
+ *
+ * Description:
+ *   Shouldn't happen
+ *
+ ************************************************************************************/
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	.bss
+	.global	g_intstackbase
+	.align	4
+up_interruptstack:
+	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
+g_intstackbase:
+	.size	up_interruptstack, .-up_interruptstack
+#endif
+
+/************************************************************************************
+ * .rodata
+ ************************************************************************************/
+
+	.section	.rodata, "a"
+
+/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
+ * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
+ * and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE thread is the thread that
+ * the system boots on and, eventually, becomes the idle, do nothing task that runs
+ * only when there is nothing else to run.  The heap continues from there until the
+ * end of memory.  See g_heapbase below.
+ */
+
+	.globl	g_heapbase
+	.type	g_heapbase, object
+g_heapbase:
+	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
+	.size	g_heapbase, .-g_heapbase
+
+	.end
diff --git a/nuttx/configs/eagle100/README.txt b/nuttx/configs/eagle100/README.txt
index 3f9da652b..378f5a25b 100644
--- a/nuttx/configs/eagle100/README.txt
+++ b/nuttx/configs/eagle100/README.txt
@@ -334,15 +334,15 @@ Eagle100-specific Configuration Options
   Additional interrupt support can be disabled if desired to reduce memory
   footprint.
 
-    CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-    CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+    CONFIG_LM_DISABLE_GPIOA_IRQS=n
+    CONFIG_LM_DISABLE_GPIOB_IRQS=n
+    CONFIG_LM_DISABLE_GPIOC_IRQS=n
+    CONFIG_LM_DISABLE_GPIOD_IRQS=n
+    CONFIG_LM_DISABLE_GPIOE_IRQS=n
+    CONFIG_LM_DISABLE_GPIOF_IRQS=n
+    CONFIG_LM_DISABLE_GPIOG_IRQS=n
+    CONFIG_LM_DISABLE_GPIOH_IRQS=y
+    CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
   LM3S6818 specific device driver settings
 
@@ -367,18 +367,18 @@ Eagle100-specific Configuration Options
       value is large, then larger values of this setting may cause
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
-    CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET)
+    CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
       to build the LM3S Ethernet driver
-    CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
-    CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
+    CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
+    CONFIG_LM_BOARDMAC - If the board-specific logic can provide
       a MAC address (via lm_ethernetmac()), then this should be selected.
-    CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
-    CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
-    CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
-    CONFIG_LM3S_MULTICAST - Set to enable multicast frames
-    CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
-    CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
-    CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console.
+    CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation
+    CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation
+    CONFIG_LM_ETHNOPAD - Set to suppress Tx padding
+    CONFIG_LM_MULTICAST - Set to enable multicast frames
+    CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode
+    CONFIG_LM_BADCRC - Set to enable bad CRC rejection.
+    CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console.
 
 Configurations
 ^^^^^^^^^^^^^^
diff --git a/nuttx/configs/eagle100/httpd/defconfig b/nuttx/configs/eagle100/httpd/defconfig
index cf4f97930..bd0ac7664 100644
--- a/nuttx/configs/eagle100/httpd/defconfig
+++ b/nuttx/configs/eagle100/httpd/defconfig
@@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n
 # Disable support for interrupts on GPIOJ which does not
 # exist on the LM3S6918.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=n
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART0_TXBUFSIZE=256
@@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=y
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=y
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/eagle100/include/board.h b/nuttx/configs/eagle100/include/board.h
index 40a12327f..597f801ac 100644
--- a/nuttx/configs/eagle100/include/board.h
+++ b/nuttx/configs/eagle100/include/board.h
@@ -112,7 +112,7 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -121,21 +121,21 @@
  *
  ************************************************************************************/
 
-extern void lm3s_boardinitialize(void);
+extern void lm_boardinitialize(void);
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
+#ifdef CONFIG_LM_BOARDMAC
 struct ether_addr;
-extern void lm3s_ethernetmac(struct ether_addr *ethaddr);
+extern void lm_ethernetmac(struct ether_addr *ethaddr);
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/nuttx/configs/eagle100/nettest/defconfig b/nuttx/configs/eagle100/nettest/defconfig
index a3b50ead6..9b1f616c6 100644
--- a/nuttx/configs/eagle100/nettest/defconfig
+++ b/nuttx/configs/eagle100/nettest/defconfig
@@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n
 # Disable support for interrupts on GPIOJ which does not
 # exist on the LM3S6918.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=n
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART0_TXBUFSIZE=256
@@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=y
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=y
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/eagle100/nsh/defconfig b/nuttx/configs/eagle100/nsh/defconfig
index 342023d6a..079bbc60e 100644
--- a/nuttx/configs/eagle100/nsh/defconfig
+++ b/nuttx/configs/eagle100/nsh/defconfig
@@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n
 # Disable support for interrupts on GPIOJ which does not
 # exist on the LM3S6918.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=n
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART0_TXBUFSIZE=256
@@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=y
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=y
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/eagle100/nxflat/defconfig b/nuttx/configs/eagle100/nxflat/defconfig
index fe02ab4b9..110f906cb 100644
--- a/nuttx/configs/eagle100/nxflat/defconfig
+++ b/nuttx/configs/eagle100/nxflat/defconfig
@@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n
 # Disable support for interrupts on GPIOJ which does not
 # exist on the LM3S6918.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=n
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART0_TXBUFSIZE=256
@@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=n
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=n
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig
index 52496c4a3..6d3b4ddad 100644
--- a/nuttx/configs/eagle100/ostest/defconfig
+++ b/nuttx/configs/eagle100/ostest/defconfig
@@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n
 # Disable support for interrupts on GPIOJ which does not
 # exist on the LM3S6918.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=n
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART0_TXBUFSIZE=256
@@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=n
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=n
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/eagle100/src/eagle100_internal.h b/nuttx/configs/eagle100/src/eagle100_internal.h
index d8bcd6a81..8a76e2eb5 100644
--- a/nuttx/configs/eagle100/src/eagle100_internal.h
+++ b/nuttx/configs/eagle100/src/eagle100_internal.h
@@ -81,14 +81,14 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the Eagle100 board.
  *
  ************************************************************************************/
 
-extern void weak_function lm3s_ssiinitialize(void);
+extern void weak_function lm_ssiinitialize(void);
 
 /****************************************************************************
  * Name: up_ledinit
diff --git a/nuttx/configs/eagle100/src/up_boot.c b/nuttx/configs/eagle100/src/up_boot.c
index 44f003e0b..8fed389f8 100644
--- a/nuttx/configs/eagle100/src/up_boot.c
+++ b/nuttx/configs/eagle100/src/up_boot.c
@@ -60,7 +60,7 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -68,18 +68,18 @@
  *   and mapped but before any devices have been initialized.
  ************************************************************************************/
 
-void lm3s_boardinitialize(void)
+void lm_boardinitialize(void)
 {
   /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function
-   * lm3s_ssiinitialize() has been brought into the link.
+   * lm_ssiinitialize() has been brought into the link.
    */
 
 /* The Eagle100 microSD CS is on SSI0 */
 
 #if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */
-  if (lm3s_ssiinitialize)
+  if (lm_ssiinitialize)
     {
-      lm3s_ssiinitialize();
+      lm_ssiinitialize();
     }
 #endif
 
diff --git a/nuttx/configs/eagle100/src/up_ethernet.c b/nuttx/configs/eagle100/src/up_ethernet.c
index a071fcca9..42876b3b5 100644
--- a/nuttx/configs/eagle100/src/up_ethernet.c
+++ b/nuttx/configs/eagle100/src/up_ethernet.c
@@ -63,17 +63,17 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
-void lm3s_ethernetmac(struct ether_addr *ethaddr)
+#ifdef CONFIG_LM_BOARDMAC
+void lm_ethernetmac(struct ether_addr *ethaddr)
 {
   uint32_t user0;
   uint32_t user1;
diff --git a/nuttx/configs/eagle100/src/up_leds.c b/nuttx/configs/eagle100/src/up_leds.c
index 0124b964b..5566b58b2 100644
--- a/nuttx/configs/eagle100/src/up_leds.c
+++ b/nuttx/configs/eagle100/src/up_leds.c
@@ -72,7 +72,7 @@
 /* Dump GPIO registers */
 
 #ifdef LED_DEBUG
-#  define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m)
+#  define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m)
 #else
 #  define led_dumpgpio(m)
 #endif
@@ -106,9 +106,9 @@ void up_ledinit(void)
 
   /* Configure Port E, Bit 1 as an output, initial value=OFF */
 
-  led_dumpgpio("up_ledinit before lm3s_configgpio()");
-  lm3s_configgpio(LED_GPIO);
-  led_dumpgpio("up_ledinit after lm3s_configgpio()");
+  led_dumpgpio("up_ledinit before lm_configgpio()");
+  lm_configgpio(LED_GPIO);
+  led_dumpgpio("up_ledinit after lm_configgpio()");
   g_nest = 0;
 }
 
@@ -132,9 +132,9 @@ void up_ledon(int led)
         g_nest++;
       case LED_IRQSENABLED:
       case LED_STACKCREATED:
-        led_dumpgpio("up_ledon: before lm3s_gpiowrite()");
-        lm3s_gpiowrite(LED_GPIO, false);
-        led_dumpgpio("up_ledon: after lm3s_gpiowrite()");
+        led_dumpgpio("up_ledon: before lm_gpiowrite()");
+        lm_gpiowrite(LED_GPIO, false);
+        led_dumpgpio("up_ledon: after lm_gpiowrite()");
         break;
     }
 }
@@ -160,9 +160,9 @@ void up_ledoff(int led)
       case LED_PANIC:
         if (--g_nest <= 0)
           {
-            led_dumpgpio("up_ledoff: before lm3s_gpiowrite()");
-            lm3s_gpiowrite(LED_GPIO, true);
-            led_dumpgpio("up_ledoff: after lm3s_gpiowrite()");
+            led_dumpgpio("up_ledoff: before lm_gpiowrite()");
+            lm_gpiowrite(LED_GPIO, true);
+            led_dumpgpio("up_ledoff: after lm_gpiowrite()");
           }
         break;
     }
diff --git a/nuttx/configs/eagle100/src/up_ssi.c b/nuttx/configs/eagle100/src/up_ssi.c
index b78a0d67c..c18cf52a5 100644
--- a/nuttx/configs/eagle100/src/up_ssi.c
+++ b/nuttx/configs/eagle100/src/up_ssi.c
@@ -81,7 +81,7 @@
 /* Dump GPIO registers */
 
 #ifdef SSI_VERBOSE
-#  define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m)
+#  define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m)
 #else
 #  define ssi_dumpgpio(m)
 #endif
@@ -95,30 +95,30 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the Eagle100 board.
  *
  ************************************************************************************/
 
-void weak_function lm3s_ssiinitialize(void)
+void weak_function lm_ssiinitialize(void)
 {
   /* Configure the SPI-based microSD CS GPIO */
 
-  ssi_dumpgpio("lm3s_ssiinitialize() before lm3s_configgpio()");
-  lm3s_configgpio(SDCCS_GPIO);
-  ssi_dumpgpio("lm3s_ssiinitialize() after lm3s_configgpio()");
+  ssi_dumpgpio("lm_ssiinitialize() before lm_configgpio()");
+  lm_configgpio(SDCCS_GPIO);
+  ssi_dumpgpio("lm_ssiinitialize() after lm_configgpio()");
 }
 
 /****************************************************************************
- * The external functions, lm3s_spiselect and lm3s_spistatus must be provided
+ * The external functions, lm_spiselect and lm_spistatus must be provided
  * by board-specific logic.  The are implementations of the select and status
  * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h).
  * All othermethods (including up_spiinitialize()) are provided by common
  * logic.  To use this common SPI logic on your board:
  *
- *   1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
+ *   1. Provide lm_spiselect() and lm_spistatus() functions in your
  *      board-specific logic.  This function will perform chip selection and
  *      status operations using GPIOs in the way your board is configured.
  *   2. Add a call to up_spiinitialize() in your low level initialization
@@ -130,20 +130,20 @@ void weak_function lm3s_ssiinitialize(void)
  *
  ****************************************************************************/
 
-void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
   ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
   if (devid == SPIDEV_MMCSD)
     {
       /* Assert the CS pin to the card */
 
-      ssi_dumpgpio("lm3s_spiselect() before lm3s_gpiowrite()");
-      lm3s_gpiowrite(SDCCS_GPIO, !selected);
-      ssi_dumpgpio("lm3s_spiselect() after lm3s_gpiowrite()");
+      ssi_dumpgpio("lm_spiselect() before lm_gpiowrite()");
+      lm_gpiowrite(SDCCS_GPIO, !selected);
+      ssi_dumpgpio("lm_spiselect() after lm_gpiowrite()");
     }
 }
 
-uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 {
   ssidbg("Returning SPI_STATUS_PRESENT\n");
   return SPI_STATUS_PRESENT;
diff --git a/nuttx/configs/eagle100/thttpd/defconfig b/nuttx/configs/eagle100/thttpd/defconfig
index 7efbbed11..2aca2582e 100644
--- a/nuttx/configs/eagle100/thttpd/defconfig
+++ b/nuttx/configs/eagle100/thttpd/defconfig
@@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n
 # Disable support for interrupts on GPIOJ which does not
 # exist on the LM3S6918.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=n
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART0_TXBUFSIZE=256
@@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6918 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=y
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=y
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/ekk-lm3s9b96/README.txt b/nuttx/configs/ekk-lm3s9b96/README.txt
index f7896118e..78f7f7b8c 100644
--- a/nuttx/configs/ekk-lm3s9b96/README.txt
+++ b/nuttx/configs/ekk-lm3s9b96/README.txt
@@ -102,12 +102,12 @@ GNU Toolchain Options
   the CodeSourcery or devkitARM, you simply need to add one of the following
   configuration options to your .config (or defconfig) file:
 
-    CONFIG_LM3S_CODESOURCERYW=y   : CodeSourcery under Windows
-    CONFIG_LM3S_CODESOURCERYL=y   : CodeSourcery under Linux
-    CONFIG_LM3S_DEVKITARM=y       : devkitARM under Windows
-    CONFIG_LM3S_BUILDROOT=y       : NuttX buildroot under Linux or Cygwin (default)
+    CONFIG_LM_CODESOURCERYW=y   : CodeSourcery under Windows
+    CONFIG_LM_CODESOURCERYL=y   : CodeSourcery under Linux
+    CONFIG_LM_DEVKITARM=y       : devkitARM under Windows
+    CONFIG_LM_BUILDROOT=y       : NuttX buildroot under Linux or Cygwin (default)
 
-  If you are not using CONFIG_LM3S_BUILDROOT, then you may also have to modify
+  If you are not using CONFIG_LM_BUILDROOT, then you may also have to modify
   the PATH in the setenv.h file if your make cannot find the tools.
 
   NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains.
@@ -352,15 +352,15 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
   Additional interrupt support can be disabled if desired to reduce memory
   footprint.
 
-    CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+    CONFIG_LM_DISABLE_GPIOA_IRQS=n
+    CONFIG_LM_DISABLE_GPIOB_IRQS=n
+    CONFIG_LM_DISABLE_GPIOC_IRQS=n
+    CONFIG_LM_DISABLE_GPIOD_IRQS=n
+    CONFIG_LM_DISABLE_GPIOE_IRQS=n
+    CONFIG_LM_DISABLE_GPIOF_IRQS=n
+    CONFIG_LM_DISABLE_GPIOG_IRQS=n
+    CONFIG_LM_DISABLE_GPIOH_IRQS=n
+    CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
   LM3S6818 specific device driver settings
 
@@ -385,18 +385,18 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
       value is large, then larger values of this setting may cause
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
-    CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET)
+    CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
       to build the LM3S Ethernet driver
-    CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
-    CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
+    CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
+    CONFIG_LM_BOARDMAC - If the board-specific logic can provide
       a MAC address (via lm_ethernetmac()), then this should be selected.
-    CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
-    CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
-    CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
-    CONFIG_LM3S_MULTICAST - Set to enable multicast frames
-    CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
-    CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
-    CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console.
+    CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation
+    CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation
+    CONFIG_LM_ETHNOPAD - Set to suppress Tx padding
+    CONFIG_LM_MULTICAST - Set to enable multicast frames
+    CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode
+    CONFIG_LM_BADCRC - Set to enable bad CRC rejection.
+    CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console.
 
 Configurations
 ^^^^^^^^^^^^^^
diff --git a/nuttx/configs/ekk-lm3s9b96/include/board.h b/nuttx/configs/ekk-lm3s9b96/include/board.h
index 2e6cd93f1..f5c997539 100644
--- a/nuttx/configs/ekk-lm3s9b96/include/board.h
+++ b/nuttx/configs/ekk-lm3s9b96/include/board.h
@@ -113,7 +113,7 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -122,21 +122,21 @@
  *
  ************************************************************************************/
 
-extern void lm3s_boardinitialize(void);
+extern void lm_boardinitialize(void);
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
+#ifdef CONFIG_LM_BOARDMAC
 struct ether_addr;
-extern void lm3s_ethernetmac(struct ether_addr *ethaddr);
+extern void lm_ethernetmac(struct ether_addr *ethaddr);
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
index b614c0316..adb9bb5fa 100644
--- a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
+++ b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig
@@ -57,32 +57,32 @@ CONFIG_ARCH_CALIBRATION=n
 #
 # Identify toolchain and linker options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=n
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=y
-CONFIG_LM3S_DFU=y
+CONFIG_LM_CODESOURCERYW=n
+CONFIG_LM_CODESOURCERYL=n
+CONFIG_LM_DEVKITARM=n
+CONFIG_LM_BUILDROOT=y
+CONFIG_LM_DFU=y
 
 #
 # Disable support for interrupts on GPIOH and GPIOJ which do not
 # exist on the LM3S6B96.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6B96 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
-CONFIG_LM3S_UART2=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
+CONFIG_LM_UART2=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART2_SERIAL_CONSOLE=n
@@ -116,16 +116,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6B96 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=y
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=n
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=y
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=n
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
index df5622360..821502036 100644
--- a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
+++ b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig
@@ -57,32 +57,32 @@ CONFIG_ARCH_CALIBRATION=n
 #
 # Identify toolchain and linker options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=n
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=y
-CONFIG_LM3S_DFU=y
+CONFIG_LM_CODESOURCERYW=n
+CONFIG_LM_CODESOURCERYL=n
+CONFIG_LM_DEVKITARM=n
+CONFIG_LM_BUILDROOT=y
+CONFIG_LM_DFU=y
 
 #
 # Disable support for interrupts on GPIOH and GPIOJ which do not
 # exist on the LM3S6B96.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6B96 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
-CONFIG_LM3S_UART2=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
+CONFIG_LM_UART2=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART2_SERIAL_CONSOLE=n
@@ -116,16 +116,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6B96 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=n
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=n
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
index 17b0d0e27..d7ab916c8 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
+++ b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
@@ -102,14 +102,14 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit.
  *
  ************************************************************************************/
 
-extern void weak_function lm3s_ssiinitialize(void);
+extern void weak_function lm_ssiinitialize(void);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __CONFIGS_EKK_LM3S9B96_SRC_EKKLM3S9B96_INTERNAL_H */
diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_boot.c b/nuttx/configs/ekk-lm3s9b96/src/up_boot.c
index 528d150e1..16057ccb9 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/up_boot.c
+++ b/nuttx/configs/ekk-lm3s9b96/src/up_boot.c
@@ -62,7 +62,7 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -70,16 +70,16 @@
  *   and mapped but before any devices have been initialized.
  ************************************************************************************/
 
-void lm3s_boardinitialize(void)
+void lm_boardinitialize(void)
 {
   /* Configure chip selects if 1) SSI is not disabled, and 2) the weak function
-   * lm3s_ssiinitialize() has been brought into the link.
+   * lm_ssiinitialize() has been brought into the link.
    */
 
 #if !defined(CONFIG_SSI0_DISABLE)  || !defined(CONFIG_SSI1_DISABLE) 
-  if (lm3s_ssiinitialize)
+  if (lm_ssiinitialize)
     {
-      lm3s_ssiinitialize();
+      lm_ssiinitialize();
     }
 #endif
 
diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c b/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c
index a1963f0d5..bc4149082 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c
+++ b/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c
@@ -64,17 +64,17 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
-void lm3s_ethernetmac(struct ether_addr *ethaddr)
+#ifdef CONFIG_LM_BOARDMAC
+void lm_ethernetmac(struct ether_addr *ethaddr)
 {
   uint32_t user0;
   uint32_t user1;
diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_leds.c b/nuttx/configs/ekk-lm3s9b96/src/up_leds.c
index 7628fcfe0..e6abe1a8a 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/up_leds.c
+++ b/nuttx/configs/ekk-lm3s9b96/src/up_leds.c
@@ -73,7 +73,7 @@
 /* Dump GPIO registers */
 
 #ifdef LED_DEBUG
-#  define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m)
+#  define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m)
 #else
 #  define led_dumpgpio(m)
 #endif
@@ -103,9 +103,9 @@ void up_ledinit(void)
 
   /* Configure Port D, Bit 0 as an output, initial value=OFF */
 
-  led_dumpgpio("up_ledinit before lm3s_configgpio()");
-  lm3s_configgpio(LED_GPIO);
-  led_dumpgpio("up_ledinit after lm3s_configgpio()");
+  led_dumpgpio("up_ledinit before lm_configgpio()");
+  lm_configgpio(LED_GPIO);
+  led_dumpgpio("up_ledinit after lm_configgpio()");
   g_nest = 0;
 }
 
@@ -129,9 +129,9 @@ void up_ledon(int led)
         g_nest++;
       case LED_IRQSENABLED:
       case LED_STACKCREATED:
-        led_dumpgpio("up_ledon: before lm3s_gpiowrite()");
-        lm3s_gpiowrite(LED_GPIO, false);
-        led_dumpgpio("up_ledon: after lm3s_gpiowrite()");
+        led_dumpgpio("up_ledon: before lm_gpiowrite()");
+        lm_gpiowrite(LED_GPIO, false);
+        led_dumpgpio("up_ledon: after lm_gpiowrite()");
         break;
     }
 }
@@ -157,9 +157,9 @@ void up_ledoff(int led)
       case LED_PANIC:
         if (--g_nest <= 0)
           {
-            led_dumpgpio("up_ledoff: before lm3s_gpiowrite()");
-            lm3s_gpiowrite(LED_GPIO, true);
-            led_dumpgpio("up_ledoff: after lm3s_gpiowrite()");
+            led_dumpgpio("up_ledoff: before lm_gpiowrite()");
+            lm_gpiowrite(LED_GPIO, true);
+            led_dumpgpio("up_ledoff: after lm_gpiowrite()");
           }
         break;
     }
diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c b/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c
index 8f297e7a7..d7ee0ef16 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c
+++ b/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c
@@ -81,7 +81,7 @@
 
 #ifdef SSI_VERBOSE
 #if 0
-#  define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m)
+#  define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m)
 #endif
 #else
 #  define ssi_dumpgpio(m)
@@ -96,31 +96,31 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure chip select GPIO pins for the LM3S9B96 Eval board.
  *
  ************************************************************************************/
 
-void weak_function lm3s_ssiinitialize(void)
+void weak_function lm_ssiinitialize(void)
 {
   /* Configure the CS GPIO */
 #if 0
-  ssi_dumpgpio("lm3s_ssiinitialize() Entry");
-  ssi_dumpgpio("lm3s_ssiinitialize() Exit");
+  ssi_dumpgpio("lm_ssiinitialize() Entry");
+  ssi_dumpgpio("lm_ssiinitialize() Exit");
 #endif
 }
 
 #if 0
 /****************************************************************************
- * The external functions, lm3s_spiselect and lm3s_spistatus must be provided
+ * The external functions, lm_spiselect and lm_spistatus must be provided
  * by board-specific logic.  The are implementations of the select and status
  * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h).
  * All othermethods (including up_spiinitialize()) are provided by common
  * logic.  To use this common SPI logic on your board:
  *
- *   1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
+ *   1. Provide lm_spiselect() and lm_spistatus() functions in your
  *      board-specific logic.  This function will perform chip selection and
  *      status operations using GPIOs in the way your board is configured.
  *   2. Add a call to up_spiinitialize() in your low level initialization
@@ -132,28 +132,28 @@ void weak_function lm3s_ssiinitialize(void)
  *
  ****************************************************************************/
 
-void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
   ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-  ssi_dumpgpio("lm3s_spiselect() Entry");
+  ssi_dumpgpio("lm_spiselect() Entry");
   if (devid == SPIDEV_MMCSD)
     {
       /* Assert the CS pin to the card */
 
-      lm3s_gpiowrite(SDCCS_GPIO, !selected);
+      lm_gpiowrite(SDCCS_GPIO, !selected);
     }
 #ifdef CONFIG_NX_LCDDRIVER
   else if (devid == SPIDEV_DISPLAY)
     {
       /* Assert the CS pin to the display */
 
-      lm3s_gpiowrite(OLEDCS_GPIO, !selected);
+      lm_gpiowrite(OLEDCS_GPIO, !selected);
     }
 #endif
-  ssi_dumpgpio("lm3s_spiselect() Exit");
+  ssi_dumpgpio("lm_spiselect() Exit");
 }
 
-uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 {
   ssidbg("Returning SPI_STATUS_PRESENT\n");
   return SPI_STATUS_PRESENT;
diff --git a/nuttx/configs/lm3s6432-s2e/README.txt b/nuttx/configs/lm3s6432-s2e/README.txt
index 669708c16..29cf80fae 100644
--- a/nuttx/configs/lm3s6432-s2e/README.txt
+++ b/nuttx/configs/lm3s6432-s2e/README.txt
@@ -97,12 +97,12 @@ GNU Toolchain Options
   To use a specific toolchain, you simply need to add one of the following
   configuration options to your .config (or defconfig) file:
 
-    CONFIG_LM3S_CODESOURCERYW=y   : CodeSourcery under Windows
-    CONFIG_LM3S_CODESOURCERYL=y   : CodeSourcery under Linux or on Mac OS X.
-    CONFIG_LM3S_DEVKITARM=y       : devkitARM under Windows
-    CONFIG_LM3S_BUILDROOT=y       : NuttX buildroot under Linux or Cygwin (default)
+    CONFIG_LM_CODESOURCERYW=y   : CodeSourcery under Windows
+    CONFIG_LM_CODESOURCERYL=y   : CodeSourcery under Linux or on Mac OS X.
+    CONFIG_LM_DEVKITARM=y       : devkitARM under Windows
+    CONFIG_LM_BUILDROOT=y       : NuttX buildroot under Linux or Cygwin (default)
 
-  If you are not using CONFIG_LM3S_BUILDROOT, then you may also have to modify
+  If you are not using CONFIG_LM_BUILDROOT, then you may also have to modify
   the PATH in the setenv.h file if your make cannot find the tools.
 
   NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains.
@@ -346,15 +346,15 @@ Stellaris MDL-S2E Reference Design Configuration Options
   Additional interrupt support can be disabled if desired to reduce memory
   footprint - GPIOs C-G are not pinned out on the MDL-S2E board.
 
-    CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOC_IRQS=y
-    CONFIG_LM3S_DISABLE_GPIOD_IRQS=y
-    CONFIG_LM3S_DISABLE_GPIOE_IRQS=y
-    CONFIG_LM3S_DISABLE_GPIOF_IRQS=y
-    CONFIG_LM3S_DISABLE_GPIOG_IRQS=y
-    CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-    CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+    CONFIG_LM_DISABLE_GPIOA_IRQS=n
+    CONFIG_LM_DISABLE_GPIOB_IRQS=n
+    CONFIG_LM_DISABLE_GPIOC_IRQS=y
+    CONFIG_LM_DISABLE_GPIOD_IRQS=y
+    CONFIG_LM_DISABLE_GPIOE_IRQS=y
+    CONFIG_LM_DISABLE_GPIOF_IRQS=y
+    CONFIG_LM_DISABLE_GPIOG_IRQS=y
+    CONFIG_LM_DISABLE_GPIOH_IRQS=y
+    CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
   LM3S6432 specific device driver settings
 
@@ -388,18 +388,18 @@ Stellaris MDL-S2E Reference Design Configuration Options
       value is large, then larger values of this setting may cause
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
-    CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET)
+    CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
       to build the LM3S Ethernet driver
-    CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
-    CONFIG_LM3S_BOARDMAC - This should be set in order to use the
+    CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
+    CONFIG_LM_BOARDMAC - This should be set in order to use the
       MAC address configured in the flash USER registers.
-    CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
-    CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
-    CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
-    CONFIG_LM3S_MULTICAST - Set to enable multicast frames
-    CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
-    CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
-    CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console.
+    CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation
+    CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation
+    CONFIG_LM_ETHNOPAD - Set to suppress Tx padding
+    CONFIG_LM_MULTICAST - Set to enable multicast frames
+    CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode
+    CONFIG_LM_BADCRC - Set to enable bad CRC rejection.
+    CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console.
 
 Configurations
 ^^^^^^^^^^^^^^
diff --git a/nuttx/configs/lm3s6432-s2e/include/board.h b/nuttx/configs/lm3s6432-s2e/include/board.h
index 06504ec4f..7fdcabf76 100644
--- a/nuttx/configs/lm3s6432-s2e/include/board.h
+++ b/nuttx/configs/lm3s6432-s2e/include/board.h
@@ -114,7 +114,7 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -123,21 +123,21 @@
  *
  ************************************************************************************/
 
-extern void lm3s_boardinitialize(void);
+extern void lm_boardinitialize(void);
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the MDL-S2E Reference Design, the MAC address will be stored in the 
- *   non-volatile USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, 
+ *   non-volatile USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, 
  *   this function will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
+#ifdef CONFIG_LM_BOARDMAC
 struct ether_addr;
-extern void lm3s_ethernetmac(struct ether_addr *ethaddr);
+extern void lm_ethernetmac(struct ether_addr *ethaddr);
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/nuttx/configs/lm3s6432-s2e/nsh/defconfig b/nuttx/configs/lm3s6432-s2e/nsh/defconfig
index edd61eacc..a09bc6717 100644
--- a/nuttx/configs/lm3s6432-s2e/nsh/defconfig
+++ b/nuttx/configs/lm3s6432-s2e/nsh/defconfig
@@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n
 #
 # Identify toolchain and linker options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=y
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=n
+CONFIG_LM_CODESOURCERYW=n
+CONFIG_LM_CODESOURCERYL=y
+CONFIG_LM_DEVKITARM=n
+CONFIG_LM_BUILDROOT=n
 
 #
 # Disable support for interrupts on GPIOs which do not
 # exist on the LM3S6432 or are not pinned anywhere useful
 # on the S2E.
 #
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=y
+CONFIG_LM_DISABLE_GPIOD_IRQS=y
+CONFIG_LM_DISABLE_GPIOE_IRQS=y
+CONFIG_LM_DISABLE_GPIOF_IRQS=y
+CONFIG_LM_DISABLE_GPIOG_IRQS=y
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6432 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=y
-CONFIG_LM3S_UART2=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=y
+CONFIG_LM_UART2=n
 CONFIG_UART0_SERIAL_CONSOLE=n
 CONFIG_UART1_SERIAL_CONSOLE=y
 CONFIG_UART2_SERIAL_CONSOLE=n
@@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6432 specific ethernet device driver settings
 #
-CONFIG_LM3S_ETHERNET=y
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=y
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/lm3s6432-s2e/ostest/defconfig b/nuttx/configs/lm3s6432-s2e/ostest/defconfig
index 2d32db81c..9387fd086 100644
--- a/nuttx/configs/lm3s6432-s2e/ostest/defconfig
+++ b/nuttx/configs/lm3s6432-s2e/ostest/defconfig
@@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n
 #
 # Identify toolchain and linker options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=y
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=n
+CONFIG_LM_CODESOURCERYW=n
+CONFIG_LM_CODESOURCERYL=y
+CONFIG_LM_DEVKITARM=n
+CONFIG_LM_BUILDROOT=n
 
 #
 # Disable support for interrupts on GPIOs which do not
 # exist on the LM3S6432 or are not pinned anywhere useful
 # on the S2E.
 #
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=y
+CONFIG_LM_DISABLE_GPIOD_IRQS=y
+CONFIG_LM_DISABLE_GPIOE_IRQS=y
+CONFIG_LM_DISABLE_GPIOF_IRQS=y
+CONFIG_LM_DISABLE_GPIOG_IRQS=y
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S6432 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=y
-CONFIG_LM3S_UART2=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=y
+CONFIG_LM_UART2=n
 CONFIG_UART0_SERIAL_CONSOLE=n
 CONFIG_UART1_SERIAL_CONSOLE=y
 CONFIG_UART2_SERIAL_CONSOLE=n
@@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S6432 specific ethernet device driver settings
 #
-CONFIG_LM3S_ETHERNET=n
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=n
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
index f54403c7a..f95b118ad 100644
--- a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
+++ b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
@@ -112,14 +112,14 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the MDL-S2E.
  *
  ************************************************************************************/
 
-extern void weak_function lm3s_ssiinitialize(void);
+extern void weak_function lm_ssiinitialize(void);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __CONFIGS_LM3S6432_S2E_SRC_LM3S6432S2E_INTERNAL_H */
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_boot.c b/nuttx/configs/lm3s6432-s2e/src/up_boot.c
index 184529638..da900282f 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_boot.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_boot.c
@@ -54,7 +54,7 @@
  * Definitions
  ************************************************************************************/
 
-#if defined(CONFIG_LM3S_UART1) && !defined(CONFIG_SSI0_DISABLE)
+#if defined(CONFIG_LM_UART1) && !defined(CONFIG_SSI0_DISABLE)
 #  error Only one of UART1 and SSI0 can be enabled on this board.
 #endif
 
@@ -67,7 +67,7 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -75,16 +75,16 @@
  *   and mapped but before any devices have been initialized.
  ************************************************************************************/
 
-void lm3s_boardinitialize(void)
+void lm_boardinitialize(void)
 {
   /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function
-   * lm3s_ssiinitialize() has been brought into the link.
+   * lm_ssiinitialize() has been brought into the link.
    */
 
 #if !defined(CONFIG_SSI0_DISABLE)
-  if (lm3s_ssiinitialize)
+  if (lm_ssiinitialize)
     {
-      lm3s_ssiinitialize();
+      lm_ssiinitialize();
     }
 #endif
 
@@ -96,8 +96,8 @@ void lm3s_boardinitialize(void)
 
   /* Configure serial transciever */
   
-  lm3s_configgpio(XCVR_INV_GPIO);
-  lm3s_configgpio(XCVR_ENA_GPIO);
-  lm3s_configgpio(XCVR_ON_GPIO);
-  lm3s_configgpio(XCVR_OFF_GPIO);
+  lm_configgpio(XCVR_INV_GPIO);
+  lm_configgpio(XCVR_ENA_GPIO);
+  lm_configgpio(XCVR_ON_GPIO);
+  lm_configgpio(XCVR_OFF_GPIO);
 }
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c b/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c
index 09d5040c4..434ffe2c5 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c
@@ -63,17 +63,17 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
-void lm3s_ethernetmac(struct ether_addr *ethaddr)
+#ifdef CONFIG_LM_BOARDMAC
+void lm_ethernetmac(struct ether_addr *ethaddr)
 {
   uint32_t user0;
   uint32_t user1;
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_leds.c b/nuttx/configs/lm3s6432-s2e/src/up_leds.c
index 81610db34..e0dd53f28 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_leds.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_leds.c
@@ -72,7 +72,7 @@
 /* Dump GPIO registers */
 
 #ifdef LED_DEBUG
-#  define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m)
+#  define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m)
 #else
 #  define led_dumpgpio(m)
 #endif
@@ -102,10 +102,10 @@ void up_ledinit(void)
 
   /* Configure Port F, Bit 2 as an output, initial value=OFF */
 
-  led_dumpgpio("up_ledinit before lm3s_configgpio()");
-  lm3s_configgpio(LED0_GPIO);
-  lm3s_configgpio(LED1_GPIO);
-  led_dumpgpio("up_ledinit after lm3s_configgpio()");
+  led_dumpgpio("up_ledinit before lm_configgpio()");
+  lm_configgpio(LED0_GPIO);
+  lm_configgpio(LED1_GPIO);
+  led_dumpgpio("up_ledinit after lm_configgpio()");
   g_nest = 0;
 }
 
@@ -129,9 +129,9 @@ void up_ledon(int led)
         g_nest++;
       case LED_IRQSENABLED:
       case LED_STACKCREATED:
-        led_dumpgpio("up_ledon: before lm3s_gpiowrite()");
-        lm3s_gpiowrite(LED1_GPIO, false);
-        led_dumpgpio("up_ledon: after lm3s_gpiowrite()");
+        led_dumpgpio("up_ledon: before lm_gpiowrite()");
+        lm_gpiowrite(LED1_GPIO, false);
+        led_dumpgpio("up_ledon: after lm_gpiowrite()");
         break;
     }
 }
@@ -157,9 +157,9 @@ void up_ledoff(int led)
       case LED_PANIC:
         if (--g_nest <= 0)
           {
-            led_dumpgpio("up_ledoff: before lm3s_gpiowrite()");
-            lm3s_gpiowrite(LED1_GPIO, true);
-            led_dumpgpio("up_ledoff: after lm3s_gpiowrite()");
+            led_dumpgpio("up_ledoff: before lm_gpiowrite()");
+            lm_gpiowrite(LED1_GPIO, true);
+            led_dumpgpio("up_ledoff: after lm_gpiowrite()");
           }
         break;
     }
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_ssi.c b/nuttx/configs/lm3s6432-s2e/src/up_ssi.c
index a7844a979..5468e2b4d 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_ssi.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_ssi.c
@@ -79,7 +79,7 @@
 /* Dump GPIO registers */
 
 #ifdef SSI_VERBOSE
-#  define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m)
+#  define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m)
 #else
 #  define ssi_dumpgpio(m)
 #endif
@@ -93,30 +93,30 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the MDL-S2E.
  *
  ************************************************************************************/
 
-void weak_function lm3s_ssiinitialize(void)
+void weak_function lm_ssiinitialize(void)
 {
   /* Configure the SPI CS GPIO */
 
-  ssi_dumpgpio("lm3s_ssiinitialize() Entry)");
-  lm3s_configgpio(SSICS_GPIO);
-  ssi_dumpgpio("lm3s_ssiinitialize() Exit");
+  ssi_dumpgpio("lm_ssiinitialize() Entry)");
+  lm_configgpio(SSICS_GPIO);
+  ssi_dumpgpio("lm_ssiinitialize() Exit");
 }
 
 /****************************************************************************
- * The external functions, lm3s_spiselect and lm3s_spistatus must be provided
+ * The external functions, lm_spiselect and lm_spistatus must be provided
  * by board-specific logic.  The are implementations of the select and status
  * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h).
  * All othermethods (including up_spiinitialize()) are provided by common
  * logic.  To use this common SPI logic on your board:
  *
- *   1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
+ *   1. Provide lm_spiselect() and lm_spistatus() functions in your
  *      board-specific logic.  This function will perform chip selection and
  *      status operations using GPIOs in the way your board is configured.
  *   2. Add a call to up_spiinitialize() in your low level initialization
@@ -128,21 +128,21 @@ void weak_function lm3s_ssiinitialize(void)
  *
  ****************************************************************************/
 
-void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
   ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-  ssi_dumpgpio("lm3s_spiselect() Entry");
+  ssi_dumpgpio("lm_spiselect() Entry");
 
   if (devid == SPIDEV_MMCSD)
     {
       /* Assert the CS pin to the card */
 
-      lm3s_gpiowrite(SDCCS_GPIO, !selected);
+      lm_gpiowrite(SDCCS_GPIO, !selected);
     }
-  ssi_dumpgpio("lm3s_spiselect() Exit");
+  ssi_dumpgpio("lm_spiselect() Exit");
 }
 
-uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 {
   ssidbg("Returning SPI_STATUS_PRESENT\n");
   return SPI_STATUS_PRESENT;
diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt
index e0349f5de..813e11467 100644
--- a/nuttx/configs/lm3s6965-ek/README.txt
+++ b/nuttx/configs/lm3s6965-ek/README.txt
@@ -126,12 +126,12 @@ GNU Toolchain Options
   the CodeSourcery or devkitARM, you simply need to add one of the following
   configuration options to your .config (or defconfig) file:
 
-    CONFIG_LM3S_CODESOURCERYW=y   : CodeSourcery under Windows
-    CONFIG_LM3S_CODESOURCERYL=y   : CodeSourcery under Linux
-    CONFIG_LM3S_DEVKITARM=y       : devkitARM under Windows
-    CONFIG_LM3S_BUILDROOT=y       : NuttX buildroot under Linux or Cygwin (default)
+    CONFIG_LM_CODESOURCERYW=y   : CodeSourcery under Windows
+    CONFIG_LM_CODESOURCERYL=y   : CodeSourcery under Linux
+    CONFIG_LM_DEVKITARM=y       : devkitARM under Windows
+    CONFIG_LM_BUILDROOT=y       : NuttX buildroot under Linux or Cygwin (default)
 
-  If you are not using CONFIG_LM3S_BUILDROOT, then you may also have to modify
+  If you are not using CONFIG_LM_BUILDROOT, then you may also have to modify
   the PATH in the setenv.h file if your make cannot find the tools.
 
   NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains.
@@ -415,15 +415,15 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
   Additional interrupt support can be disabled if desired to reduce memory
   footprint.
 
-    CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+    CONFIG_LM_DISABLE_GPIOA_IRQS=n
+    CONFIG_LM_DISABLE_GPIOB_IRQS=n
+    CONFIG_LM_DISABLE_GPIOC_IRQS=n
+    CONFIG_LM_DISABLE_GPIOD_IRQS=n
+    CONFIG_LM_DISABLE_GPIOE_IRQS=n
+    CONFIG_LM_DISABLE_GPIOF_IRQS=n
+    CONFIG_LM_DISABLE_GPIOG_IRQS=n
+    CONFIG_LM_DISABLE_GPIOH_IRQS=n
+    CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
   LM3S6818 specific device driver settings
 
@@ -448,18 +448,18 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
       value is large, then larger values of this setting may cause
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
-    CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET)
+    CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
       to build the LM3S Ethernet driver
-    CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
-    CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
+    CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
+    CONFIG_LM_BOARDMAC - If the board-specific logic can provide
       a MAC address (via lm_ethernetmac()), then this should be selected.
-    CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
-    CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
-    CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
-    CONFIG_LM3S_MULTICAST - Set to enable multicast frames
-    CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
-    CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
-    CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console.
+    CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation
+    CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation
+    CONFIG_LM_ETHNOPAD - Set to suppress Tx padding
+    CONFIG_LM_MULTICAST - Set to enable multicast frames
+    CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode
+    CONFIG_LM_BADCRC - Set to enable bad CRC rejection.
+    CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console.
 
 Configurations
 ^^^^^^^^^^^^^^
diff --git a/nuttx/configs/lm3s6965-ek/include/board.h b/nuttx/configs/lm3s6965-ek/include/board.h
index e8eaf9dd1..808d009cc 100644
--- a/nuttx/configs/lm3s6965-ek/include/board.h
+++ b/nuttx/configs/lm3s6965-ek/include/board.h
@@ -112,7 +112,7 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -121,21 +121,21 @@
  *
  ************************************************************************************/
 
-extern void lm3s_boardinitialize(void);
+extern void lm_boardinitialize(void);
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
+#ifdef CONFIG_LM_BOARDMAC
 struct ether_addr;
-extern void lm3s_ethernetmac(struct ether_addr *ethaddr);
+extern void lm_ethernetmac(struct ether_addr *ethaddr);
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig
index c1827920b..99f2f50ab 100755
--- a/nuttx/configs/lm3s6965-ek/nsh/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig
@@ -100,44 +100,44 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 # CONFIG_ARCH_CHIP_LM3S6432 is not set
 CONFIG_ARCH_CHIP_LM3S6965=y
 # CONFIG_ARCH_CHIP_LM3S8962 is not set
-# CONFIG_LM3S_REVA2 is not set
-CONFIG_LM3S_DFU=y
+# CONFIG_LM_REVA2 is not set
+CONFIG_LM_DFU=y
 
 #
 # Select LM3S Peripheral Support
 #
-CONFIG_LM3S_UART0=y
-# CONFIG_LM3S_UART1 is not set
+CONFIG_LM_UART0=y
+# CONFIG_LM_UART1 is not set
 # CONFIG_SSI0_DISABLE is not set
 CONFIG_SSI1_DISABLE=y
-# CONFIG_LM3S_UART2 is not set
-CONFIG_LM3S_ETHERNET=y
+# CONFIG_LM_UART2 is not set
+CONFIG_LM_ETHERNET=y
 
 #
 # Disable GPIO Interrupts
 #
-# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+# CONFIG_LM_DISABLE_GPIOA_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOB_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOC_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOD_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOE_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOF_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOG_IRQS is not set
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S Ethernet Configuration
 #
-# CONFIG_LM3S_ETHLEDS is not set
-# CONFIG_LM3S_BOARDMAC is not set
-# CONFIG_LM3S_ETHHDUPLEX is not set
-# CONFIG_LM3S_ETHNOAUTOCRC is not set
-# CONFIG_LM3S_ETHNOPAD is not set
-# CONFIG_LM3S_MULTICAST is not set
-# CONFIG_LM3S_PROMISCUOUS is not set
-# CONFIG_LM3S_TIMESTAMP is not set
-# CONFIG_LM3S_BADCRC is not set
+# CONFIG_LM_ETHLEDS is not set
+# CONFIG_LM_BOARDMAC is not set
+# CONFIG_LM_ETHHDUPLEX is not set
+# CONFIG_LM_ETHNOAUTOCRC is not set
+# CONFIG_LM_ETHNOPAD is not set
+# CONFIG_LM_MULTICAST is not set
+# CONFIG_LM_PROMISCUOUS is not set
+# CONFIG_LM_TIMESTAMP is not set
+# CONFIG_LM_BADCRC is not set
 # CONFIG_M3S_DUMPPACKET is not set
 
 #
diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig
index e3cac8dd7..b86d06dc9 100755
--- a/nuttx/configs/lm3s6965-ek/nx/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nx/defconfig
@@ -100,31 +100,31 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 # CONFIG_ARCH_CHIP_LM3S6432 is not set
 CONFIG_ARCH_CHIP_LM3S6965=y
 # CONFIG_ARCH_CHIP_LM3S8962 is not set
-# CONFIG_LM3S_REVA2 is not set
-CONFIG_LM3S_DFU=y
+# CONFIG_LM_REVA2 is not set
+CONFIG_LM_DFU=y
 
 #
 # Select LM3S Peripheral Support
 #
-CONFIG_LM3S_UART0=y
-# CONFIG_LM3S_UART1 is not set
+CONFIG_LM_UART0=y
+# CONFIG_LM_UART1 is not set
 # CONFIG_SSI0_DISABLE is not set
 CONFIG_SSI1_DISABLE=y
-# CONFIG_LM3S_UART2 is not set
-# CONFIG_LM3S_ETHERNET is not set
+# CONFIG_LM_UART2 is not set
+# CONFIG_LM_ETHERNET is not set
 
 #
 # Disable GPIO Interrupts
 #
-# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+# CONFIG_LM_DISABLE_GPIOA_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOB_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOC_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOD_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOE_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOF_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOG_IRQS is not set
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S SSI Configuration
diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig
index 81247c795..bc433e116 100755
--- a/nuttx/configs/lm3s6965-ek/ostest/defconfig
+++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig
@@ -100,31 +100,31 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 # CONFIG_ARCH_CHIP_LM3S6432 is not set
 CONFIG_ARCH_CHIP_LM3S6965=y
 # CONFIG_ARCH_CHIP_LM3S8962 is not set
-# CONFIG_LM3S_REVA2 is not set
-CONFIG_LM3S_DFU=y
+# CONFIG_LM_REVA2 is not set
+CONFIG_LM_DFU=y
 
 #
 # Select LM3S Peripheral Support
 #
-CONFIG_LM3S_UART0=y
-# CONFIG_LM3S_UART1 is not set
+CONFIG_LM_UART0=y
+# CONFIG_LM_UART1 is not set
 # CONFIG_SSI0_DISABLE is not set
 CONFIG_SSI1_DISABLE=y
-# CONFIG_LM3S_UART2 is not set
-# CONFIG_LM3S_ETHERNET is not set
+# CONFIG_LM_UART2 is not set
+# CONFIG_LM_ETHERNET is not set
 
 #
 # Disable GPIO Interrupts
 #
-# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set
-# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+# CONFIG_LM_DISABLE_GPIOA_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOB_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOC_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOD_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOE_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOF_IRQS is not set
+# CONFIG_LM_DISABLE_GPIOG_IRQS is not set
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S SSI Configuration
diff --git a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
index 4cd2eddc7..c2fc50df1 100644
--- a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
+++ b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
@@ -123,14 +123,14 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit.
  *
  ************************************************************************************/
 
-extern void weak_function lm3s_ssiinitialize(void);
+extern void weak_function lm_ssiinitialize(void);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __CONFIGS_LM3S6965_EK_SRC_LM3S6965EK_INTERNAL_H */
diff --git a/nuttx/configs/lm3s6965-ek/src/up_boot.c b/nuttx/configs/lm3s6965-ek/src/up_boot.c
index 7f887be62..7ffd37f17 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_boot.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_boot.c
@@ -61,7 +61,7 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -69,18 +69,18 @@
  *   and mapped but before any devices have been initialized.
  ************************************************************************************/
 
-void lm3s_boardinitialize(void)
+void lm_boardinitialize(void)
 {
   /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function
-   * lm3s_ssiinitialize() has been brought into the link.
+   * lm_ssiinitialize() has been brought into the link.
    */
 
   /* The LM3S6965 Eval Kit microSD CS and OLED are on SSI0 (Duh! There is no SSI1) */
 
 #if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */
-  if (lm3s_ssiinitialize)
+  if (lm_ssiinitialize)
     {
-      lm3s_ssiinitialize();
+      lm_ssiinitialize();
     }
 #endif
 
diff --git a/nuttx/configs/lm3s6965-ek/src/up_ethernet.c b/nuttx/configs/lm3s6965-ek/src/up_ethernet.c
index 4f402cae7..2d114baaa 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_ethernet.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_ethernet.c
@@ -63,17 +63,17 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
-void lm3s_ethernetmac(struct ether_addr *ethaddr)
+#ifdef CONFIG_LM_BOARDMAC
+void lm_ethernetmac(struct ether_addr *ethaddr)
 {
   uint32_t user0;
   uint32_t user1;
diff --git a/nuttx/configs/lm3s6965-ek/src/up_leds.c b/nuttx/configs/lm3s6965-ek/src/up_leds.c
index efa1eb738..0e6c5e50f 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_leds.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_leds.c
@@ -72,7 +72,7 @@
 /* Dump GPIO registers */
 
 #ifdef LED_DEBUG
-#  define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m)
+#  define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m)
 #else
 #  define led_dumpgpio(m)
 #endif
@@ -102,9 +102,9 @@ void up_ledinit(void)
 
   /* Configure Port E, Bit 1 as an output, initial value=OFF */
 
-  led_dumpgpio("up_ledinit before lm3s_configgpio()");
-  lm3s_configgpio(LED_GPIO);
-  led_dumpgpio("up_ledinit after lm3s_configgpio()");
+  led_dumpgpio("up_ledinit before lm_configgpio()");
+  lm_configgpio(LED_GPIO);
+  led_dumpgpio("up_ledinit after lm_configgpio()");
   g_nest = 0;
 }
 
@@ -128,9 +128,9 @@ void up_ledon(int led)
         g_nest++;
       case LED_IRQSENABLED:
       case LED_STACKCREATED:
-        led_dumpgpio("up_ledon: before lm3s_gpiowrite()");
-        lm3s_gpiowrite(LED_GPIO, false);
-        led_dumpgpio("up_ledon: after lm3s_gpiowrite()");
+        led_dumpgpio("up_ledon: before lm_gpiowrite()");
+        lm_gpiowrite(LED_GPIO, false);
+        led_dumpgpio("up_ledon: after lm_gpiowrite()");
         break;
     }
 }
@@ -156,9 +156,9 @@ void up_ledoff(int led)
       case LED_PANIC:
         if (--g_nest <= 0)
           {
-            led_dumpgpio("up_ledoff: before lm3s_gpiowrite()");
-            lm3s_gpiowrite(LED_GPIO, true);
-            led_dumpgpio("up_ledoff: after lm3s_gpiowrite()");
+            led_dumpgpio("up_ledoff: before lm_gpiowrite()");
+            lm_gpiowrite(LED_GPIO, true);
+            led_dumpgpio("up_ledoff: after lm_gpiowrite()");
           }
         break;
     }
diff --git a/nuttx/configs/lm3s6965-ek/src/up_oled.c b/nuttx/configs/lm3s6965-ek/src/up_oled.c
index 23ce7e036..07e7859b4 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_oled.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_oled.c
@@ -72,8 +72,8 @@
 
 #ifdef CONFIG_LCD_RITDEBUG
 #  define ritdbg(format, arg...)  vdbg(format, ##arg)
-#  define oleddc_dumpgpio(m) lm3s_dumpgpio(OLEDDC_GPIO, m)
-#  define oledcs_dumpgpio(m) lm3s_dumpgpio(OLEDCS_GPIO, m)
+#  define oleddc_dumpgpio(m) lm_dumpgpio(OLEDDC_GPIO, m)
+#  define oledcs_dumpgpio(m) lm_dumpgpio(OLEDCS_GPIO, m)
 #else
 #  define ritdbg(x...)
 #  define oleddc_dumpgpio(m)
@@ -102,8 +102,8 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno)
   oledcs_dumpgpio("up_nxdrvinit: After OLEDCS setup");
   oleddc_dumpgpio("up_nxdrvinit: On entry");
 
-  lm3s_configgpio(OLEDDC_GPIO); /* PC7: OLED display data/control select (D/Cn) */
-  lm3s_configgpio(OLEDEN_GPIO); /* PC6: Enable +15V needed by OLED (EN+15V) */
+  lm_configgpio(OLEDDC_GPIO); /* PC7: OLED display data/control select (D/Cn) */
+  lm_configgpio(OLEDEN_GPIO); /* PC6: Enable +15V needed by OLED (EN+15V) */
 
   oleddc_dumpgpio("up_nxdrvinit: After OLEDDC/EN setup");
 
@@ -137,7 +137,7 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno)
 }
 
 /******************************************************************************
- * Name:  lm3s_spicmddata
+ * Name:  lm_spicmddata
  *
  * Description:
  *   Set or clear the SD1329 D/Cn bit to select data (true) or command
@@ -159,13 +159,13 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno)
  *
  ******************************************************************************/
 
-int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+int lm_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
 {
   if (devid == SPIDEV_DISPLAY)
     {
       /* Set GPIO to 1 for data, 0 for command */
 
-      lm3s_gpiowrite(OLEDDC_GPIO, !cmd);
+      lm_gpiowrite(OLEDDC_GPIO, !cmd);
       return OK;
     }
   return -ENODEV;
diff --git a/nuttx/configs/lm3s6965-ek/src/up_ssi.c b/nuttx/configs/lm3s6965-ek/src/up_ssi.c
index b52116f14..92138f3a6 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_ssi.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_ssi.c
@@ -81,7 +81,7 @@
 /* Dump GPIO registers */
 
 #ifdef SSI_VERBOSE
-#  define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m)
+#  define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m)
 #else
 #  define ssi_dumpgpio(m)
 #endif
@@ -95,33 +95,33 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit.
  *
  ************************************************************************************/
 
-void weak_function lm3s_ssiinitialize(void)
+void weak_function lm_ssiinitialize(void)
 {
   /* Configure the SPI-based microSD CS GPIO */
 
-  ssi_dumpgpio("lm3s_ssiinitialize() Entry)");
-  lm3s_configgpio(SDCCS_GPIO);
+  ssi_dumpgpio("lm_ssiinitialize() Entry)");
+  lm_configgpio(SDCCS_GPIO);
 #ifdef CONFIG_NX_LCDDRIVER
-  lm3s_configgpio(OLEDCS_GPIO);
+  lm_configgpio(OLEDCS_GPIO);
 #endif
-  ssi_dumpgpio("lm3s_ssiinitialize() Exit");
+  ssi_dumpgpio("lm_ssiinitialize() Exit");
 }
 
 /****************************************************************************
- * The external functions, lm3s_spiselect and lm3s_spistatus must be provided
+ * The external functions, lm_spiselect and lm_spistatus must be provided
  * by board-specific logic.  The are implementations of the select and status
  * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h).
  * All othermethods (including up_spiinitialize()) are provided by common
  * logic.  To use this common SPI logic on your board:
  *
- *   1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
+ *   1. Provide lm_spiselect() and lm_spistatus() functions in your
  *      board-specific logic.  This function will perform chip selection and
  *      status operations using GPIOs in the way your board is configured.
  *   2. Add a call to up_spiinitialize() in your low level initialization
@@ -133,29 +133,29 @@ void weak_function lm3s_ssiinitialize(void)
  *
  ****************************************************************************/
 
-void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
   ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-  ssi_dumpgpio("lm3s_spiselect() Entry");
+  ssi_dumpgpio("lm_spiselect() Entry");
 
   if (devid == SPIDEV_MMCSD)
     {
       /* Assert the CS pin to the card */
 
-      lm3s_gpiowrite(SDCCS_GPIO, !selected);
+      lm_gpiowrite(SDCCS_GPIO, !selected);
     }
 #ifdef CONFIG_NX_LCDDRIVER
   else if (devid == SPIDEV_DISPLAY)
     {
       /* Assert the CS pin to the display */
 
-      lm3s_gpiowrite(OLEDCS_GPIO, !selected);
+      lm_gpiowrite(OLEDCS_GPIO, !selected);
     }
 #endif
-  ssi_dumpgpio("lm3s_spiselect() Exit");
+  ssi_dumpgpio("lm_spiselect() Exit");
 }
 
-uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 {
   ssidbg("Returning SPI_STATUS_PRESENT\n");
   return SPI_STATUS_PRESENT;
diff --git a/nuttx/configs/lm3s8962-ek/README.txt b/nuttx/configs/lm3s8962-ek/README.txt
index 0f796e38d..38ed76aea 100644
--- a/nuttx/configs/lm3s8962-ek/README.txt
+++ b/nuttx/configs/lm3s8962-ek/README.txt
@@ -126,12 +126,12 @@ GNU Toolchain Options
   the CodeSourcery or devkitARM, you simply need to add one of the following
   configuration options to your .config (or defconfig) file:
 
-    CONFIG_LM3S_CODESOURCERYW=y   : CodeSourcery under Windows
-    CONFIG_LM3S_CODESOURCERYL=y   : CodeSourcery under Linux
-    CONFIG_LM3S_DEVKITARM=y       : devkitARM under Windows
-    CONFIG_LM3S_BUILDROOT=y       : NuttX buildroot under Linux or Cygwin (default)
+    CONFIG_LM_CODESOURCERYW=y   : CodeSourcery under Windows
+    CONFIG_LM_CODESOURCERYL=y   : CodeSourcery under Linux
+    CONFIG_LM_DEVKITARM=y       : devkitARM under Windows
+    CONFIG_LM_BUILDROOT=y       : NuttX buildroot under Linux or Cygwin (default)
 
-  If you are not using CONFIG_LM3S_BUILDROOT, then you may also have to modify
+  If you are not using CONFIG_LM_BUILDROOT, then you may also have to modify
   the PATH in the setenv.h file if your make cannot find the tools.
 
   NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains.
@@ -399,15 +399,15 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
   Additional interrupt support can be disabled if desired to reduce memory
   footprint.
 
-    CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOH_IRQS=n
-    CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+    CONFIG_LM_DISABLE_GPIOA_IRQS=n
+    CONFIG_LM_DISABLE_GPIOB_IRQS=n
+    CONFIG_LM_DISABLE_GPIOC_IRQS=n
+    CONFIG_LM_DISABLE_GPIOD_IRQS=n
+    CONFIG_LM_DISABLE_GPIOE_IRQS=n
+    CONFIG_LM_DISABLE_GPIOF_IRQS=n
+    CONFIG_LM_DISABLE_GPIOG_IRQS=n
+    CONFIG_LM_DISABLE_GPIOH_IRQS=n
+    CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
   LM3S6818 specific device driver settings
 
@@ -432,18 +432,18 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
       value is large, then larger values of this setting may cause
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
-    CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET)
+    CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
       to build the LM3S Ethernet driver
-    CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board.
-    CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide
+    CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
+    CONFIG_LM_BOARDMAC - If the board-specific logic can provide
       a MAC address (via lm_ethernetmac()), then this should be selected.
-    CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation
-    CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation
-    CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding
-    CONFIG_LM3S_MULTICAST - Set to enable multicast frames
-    CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode
-    CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection.
-    CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console.
+    CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation
+    CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation
+    CONFIG_LM_ETHNOPAD - Set to suppress Tx padding
+    CONFIG_LM_MULTICAST - Set to enable multicast frames
+    CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode
+    CONFIG_LM_BADCRC - Set to enable bad CRC rejection.
+    CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console.
 
 Configurations
 ^^^^^^^^^^^^^^
diff --git a/nuttx/configs/lm3s8962-ek/include/board.h b/nuttx/configs/lm3s8962-ek/include/board.h
index 0b03f96f0..4d6a0c302 100644
--- a/nuttx/configs/lm3s8962-ek/include/board.h
+++ b/nuttx/configs/lm3s8962-ek/include/board.h
@@ -112,7 +112,7 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -121,21 +121,21 @@
  *
  ************************************************************************************/
 
-extern void lm3s_boardinitialize(void);
+extern void lm_boardinitialize(void);
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
+#ifdef CONFIG_LM_BOARDMAC
 struct ether_addr;
-extern void lm3s_ethernetmac(struct ether_addr *ethaddr);
+extern void lm_ethernetmac(struct ether_addr *ethaddr);
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/nuttx/configs/lm3s8962-ek/nsh/defconfig b/nuttx/configs/lm3s8962-ek/nsh/defconfig
index 1d3df2fa7..4a35f8d4a 100755
--- a/nuttx/configs/lm3s8962-ek/nsh/defconfig
+++ b/nuttx/configs/lm3s8962-ek/nsh/defconfig
@@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n
 #
 # Identify toolchain and linker options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=n
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=y
-CONFIG_LM3S_DFU=y
+CONFIG_LM_CODESOURCERYW=n
+CONFIG_LM_CODESOURCERYL=n
+CONFIG_LM_DEVKITARM=n
+CONFIG_LM_BUILDROOT=y
+CONFIG_LM_DFU=y
 
 #
 # Disable support for interrupts on GPIOH and GPIOJ which do not
 # exist on the LM3S6B96.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S8962 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
-CONFIG_LM3S_UART2=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
+CONFIG_LM_UART2=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART2_SERIAL_CONSOLE=n
@@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S8962 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=y
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=n
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=y
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=n
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/lm3s8962-ek/nx/defconfig b/nuttx/configs/lm3s8962-ek/nx/defconfig
index 37fc8903d..3ca6ade21 100755
--- a/nuttx/configs/lm3s8962-ek/nx/defconfig
+++ b/nuttx/configs/lm3s8962-ek/nx/defconfig
@@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n
 #
 # Identify toolchain and linker options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=n
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=y
-CONFIG_LM3S_DFU=y
+CONFIG_LM_CODESOURCERYW=n
+CONFIG_LM_CODESOURCERYL=n
+CONFIG_LM_DEVKITARM=n
+CONFIG_LM_BUILDROOT=y
+CONFIG_LM_DFU=y
 
 #
 # Disable support for interrupts on GPIOH and GPIOJ which do not
 # exist on the LM3S6B96.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S8962 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
-CONFIG_LM3S_UART2=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
+CONFIG_LM_UART2=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART2_SERIAL_CONSOLE=n
@@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S8962 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=n
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=n
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/lm3s8962-ek/ostest/defconfig b/nuttx/configs/lm3s8962-ek/ostest/defconfig
index 731003fd0..169ac9c8f 100755
--- a/nuttx/configs/lm3s8962-ek/ostest/defconfig
+++ b/nuttx/configs/lm3s8962-ek/ostest/defconfig
@@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n
 #
 # Identify toolchain and linker options
 #
-CONFIG_LM3S_CODESOURCERYW=n
-CONFIG_LM3S_CODESOURCERYL=n
-CONFIG_LM3S_DEVKITARM=n
-CONFIG_LM3S_BUILDROOT=y
-CONFIG_LM3S_DFU=y
+CONFIG_LM_CODESOURCERYW=n
+CONFIG_LM_CODESOURCERYL=n
+CONFIG_LM_DEVKITARM=n
+CONFIG_LM_BUILDROOT=y
+CONFIG_LM_DFU=y
 
 #
 # Disable support for interrupts on GPIOH and GPIOJ which do not
 # exist on the LM3S6B96.  Additional interrupt support can be
 # disabled if desired to reduce memory footprint.
-CONFIG_LM3S_DISABLE_GPIOA_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOB_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOC_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOD_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOE_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOF_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOG_IRQS=n
-CONFIG_LM3S_DISABLE_GPIOH_IRQS=y
-CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y
+CONFIG_LM_DISABLE_GPIOA_IRQS=n
+CONFIG_LM_DISABLE_GPIOB_IRQS=n
+CONFIG_LM_DISABLE_GPIOC_IRQS=n
+CONFIG_LM_DISABLE_GPIOD_IRQS=n
+CONFIG_LM_DISABLE_GPIOE_IRQS=n
+CONFIG_LM_DISABLE_GPIOF_IRQS=n
+CONFIG_LM_DISABLE_GPIOG_IRQS=n
+CONFIG_LM_DISABLE_GPIOH_IRQS=y
+CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
 # LM3S8962 specific serial device driver settings
 #
-CONFIG_LM3S_UART0=y
-CONFIG_LM3S_UART1=n
-CONFIG_LM3S_UART2=n
+CONFIG_LM_UART0=y
+CONFIG_LM_UART1=n
+CONFIG_LM_UART2=n
 CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_UART1_SERIAL_CONSOLE=n
 CONFIG_UART2_SERIAL_CONSOLE=n
@@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y
 #
 # LM3S8962 specific serial device driver settings
 #
-CONFIG_LM3S_ETHERNET=n
-CONFIG_LM3S_ETHLEDS=n
-CONFIG_LM3S_BOARDMAC=y
-CONFIG_LM3S_ETHHDUPLEX=n
-CONFIG_LM3S_ETHNOAUTOCRC=n
-CONFIG_LM3S_ETHNOPAD=n
-CONFIG_LM3S_MULTICAST=n
-CONFIG_LM3S_PROMISCUOUS=n
-CONFIG_LM3S_BADCRC=n
-CONFIG_LM3S_DUMPPACKET=n
+CONFIG_LM_ETHERNET=n
+CONFIG_LM_ETHLEDS=n
+CONFIG_LM_BOARDMAC=y
+CONFIG_LM_ETHHDUPLEX=n
+CONFIG_LM_ETHNOAUTOCRC=n
+CONFIG_LM_ETHNOPAD=n
+CONFIG_LM_MULTICAST=n
+CONFIG_LM_PROMISCUOUS=n
+CONFIG_LM_BADCRC=n
+CONFIG_LM_DUMPPACKET=n
 
 #
 # General build options
diff --git a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
index 689472f15..7fc8fa331 100644
--- a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
+++ b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
@@ -123,14 +123,14 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the LM3S8962 Eval Kit.
  *
  ************************************************************************************/
 
-extern void weak_function lm3s_ssiinitialize(void);
+extern void weak_function lm_ssiinitialize(void);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __CONFIGS_LM3S8962_EK_SRC_LM3S8962EK_INTERNAL_H */
diff --git a/nuttx/configs/lm3s8962-ek/src/up_boot.c b/nuttx/configs/lm3s8962-ek/src/up_boot.c
index 0a976e857..8dc5b81cc 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_boot.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_boot.c
@@ -61,7 +61,7 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_boardinitialize
+ * Name: lm_boardinitialize
  *
  * Description:
  *   All LM3S architectures must provide the following entry point.  This entry point
@@ -69,18 +69,18 @@
  *   and mapped but before any devices have been initialized.
  ************************************************************************************/
 
-void lm3s_boardinitialize(void)
+void lm_boardinitialize(void)
 {
   /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function
-   * lm3s_ssiinitialize() has been brought into the link.
+   * lm_ssiinitialize() has been brought into the link.
    */
 
   /* The LM3S8962 Eval Kit microSD CS and OLED are on SSI0 (Duh! There is no SSI1) */
 
 #if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */
-  if (lm3s_ssiinitialize)
+  if (lm_ssiinitialize)
     {
-      lm3s_ssiinitialize();
+      lm_ssiinitialize();
     }
 #endif
 
diff --git a/nuttx/configs/lm3s8962-ek/src/up_ethernet.c b/nuttx/configs/lm3s8962-ek/src/up_ethernet.c
index 2cad50bef..0d73233a4 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_ethernet.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_ethernet.c
@@ -63,17 +63,17 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ethernetmac
+ * Name: lm_ethernetmac
  *
  * Description:
  *   For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
- *   USER0 and USER1 registers.  If CONFIG_LM3S_BOARDMAC is defined, this function
+ *   USER0 and USER1 registers.  If CONFIG_LM_BOARDMAC is defined, this function
  *   will obtain the MAC address from these registers.
  *
  ************************************************************************************/
 
-#ifdef CONFIG_LM3S_BOARDMAC
-void lm3s_ethernetmac(struct ether_addr *ethaddr)
+#ifdef CONFIG_LM_BOARDMAC
+void lm_ethernetmac(struct ether_addr *ethaddr)
 {
   uint32_t user0;
   uint32_t user1;
diff --git a/nuttx/configs/lm3s8962-ek/src/up_leds.c b/nuttx/configs/lm3s8962-ek/src/up_leds.c
index d5000d037..a20617f1e 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_leds.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_leds.c
@@ -72,7 +72,7 @@
 /* Dump GPIO registers */
 
 #ifdef LED_DEBUG
-#  define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m)
+#  define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m)
 #else
 #  define led_dumpgpio(m)
 #endif
@@ -102,9 +102,9 @@ void up_ledinit(void)
 
   /* Configure Port E, Bit 1 as an output, initial value=OFF */
 
-  led_dumpgpio("up_ledinit before lm3s_configgpio()");
-  lm3s_configgpio(LED_GPIO);
-  led_dumpgpio("up_ledinit after lm3s_configgpio()");
+  led_dumpgpio("up_ledinit before lm_configgpio()");
+  lm_configgpio(LED_GPIO);
+  led_dumpgpio("up_ledinit after lm_configgpio()");
   g_nest = 0;
 }
 
@@ -128,9 +128,9 @@ void up_ledon(int led)
         g_nest++;
       case LED_IRQSENABLED:
       case LED_STACKCREATED:
-        led_dumpgpio("up_ledon: before lm3s_gpiowrite()");
-        lm3s_gpiowrite(LED_GPIO, false);
-        led_dumpgpio("up_ledon: after lm3s_gpiowrite()");
+        led_dumpgpio("up_ledon: before lm_gpiowrite()");
+        lm_gpiowrite(LED_GPIO, false);
+        led_dumpgpio("up_ledon: after lm_gpiowrite()");
         break;
     }
 }
@@ -156,9 +156,9 @@ void up_ledoff(int led)
       case LED_PANIC:
         if (--g_nest <= 0)
           {
-            led_dumpgpio("up_ledoff: before lm3s_gpiowrite()");
-            lm3s_gpiowrite(LED_GPIO, true);
-            led_dumpgpio("up_ledoff: after lm3s_gpiowrite()");
+            led_dumpgpio("up_ledoff: before lm_gpiowrite()");
+            lm_gpiowrite(LED_GPIO, true);
+            led_dumpgpio("up_ledoff: after lm_gpiowrite()");
           }
         break;
     }
diff --git a/nuttx/configs/lm3s8962-ek/src/up_oled.c b/nuttx/configs/lm3s8962-ek/src/up_oled.c
index 3324b3897..05934e8bd 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_oled.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_oled.c
@@ -72,8 +72,8 @@
 
 #ifdef CONFIG_LCD_RITDEBUG
 #  define ritdbg(format, arg...)  vdbg(format, ##arg)
-#  define oleddc_dumpgpio(m) lm3s_dumpgpio(OLEDDC_GPIO, m)
-#  define oledcs_dumpgpio(m) lm3s_dumpgpio(OLEDCS_GPIO, m)
+#  define oleddc_dumpgpio(m) lm_dumpgpio(OLEDDC_GPIO, m)
+#  define oledcs_dumpgpio(m) lm_dumpgpio(OLEDCS_GPIO, m)
 #else
 #  define ritdbg(x...)
 #  define oleddc_dumpgpio(m)
@@ -102,8 +102,8 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno)
   oledcs_dumpgpio("up_nxdrvinit: After OLEDCS setup");
   oleddc_dumpgpio("up_nxdrvinit: On entry");
 
-  lm3s_configgpio(OLEDDC_GPIO); /* PC7: OLED display data/control select (D/Cn) */
-  lm3s_configgpio(OLEDEN_GPIO); /* PC6: Enable +15V needed by OLED (EN+15V) */
+  lm_configgpio(OLEDDC_GPIO); /* PC7: OLED display data/control select (D/Cn) */
+  lm_configgpio(OLEDEN_GPIO); /* PC6: Enable +15V needed by OLED (EN+15V) */
 
   oleddc_dumpgpio("up_nxdrvinit: After OLEDDC/EN setup");
 
@@ -137,7 +137,7 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno)
 }
 
 /******************************************************************************
- * Name:  lm3s_spicmddata
+ * Name:  lm_spicmddata
  *
  * Description:
  *   Set or clear the SD1329 D/Cn bit to select data (true) or command
@@ -159,13 +159,13 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno)
  *
  ******************************************************************************/
 
-int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+int lm_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
 {
   if (devid == SPIDEV_DISPLAY)
     {
       /* Set GPIO to 1 for data, 0 for command */
 
-      lm3s_gpiowrite(OLEDDC_GPIO, !cmd);
+      lm_gpiowrite(OLEDDC_GPIO, !cmd);
       return OK;
     }
   return -ENODEV;
diff --git a/nuttx/configs/lm3s8962-ek/src/up_ssi.c b/nuttx/configs/lm3s8962-ek/src/up_ssi.c
index 7f78b3477..50344857a 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_ssi.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_ssi.c
@@ -81,7 +81,7 @@
 /* Dump GPIO registers */
 
 #ifdef SSI_VERBOSE
-#  define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m)
+#  define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m)
 #else
 #  define ssi_dumpgpio(m)
 #endif
@@ -95,33 +95,33 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: lm3s_ssiinitialize
+ * Name: lm_ssiinitialize
  *
  * Description:
  *   Called to configure SPI chip select GPIO pins for the LM3S8962 Eval Kit.
  *
  ************************************************************************************/
 
-void weak_function lm3s_ssiinitialize(void)
+void weak_function lm_ssiinitialize(void)
 {
   /* Configure the SPI-based microSD CS GPIO */
 
-  ssi_dumpgpio("lm3s_ssiinitialize() Entry)");
-  lm3s_configgpio(SDCCS_GPIO);
+  ssi_dumpgpio("lm_ssiinitialize() Entry)");
+  lm_configgpio(SDCCS_GPIO);
 #ifdef CONFIG_NX_LCDDRIVER
-  lm3s_configgpio(OLEDCS_GPIO);
+  lm_configgpio(OLEDCS_GPIO);
 #endif
-  ssi_dumpgpio("lm3s_ssiinitialize() Exit");
+  ssi_dumpgpio("lm_ssiinitialize() Exit");
 }
 
 /****************************************************************************
- * The external functions, lm3s_spiselect and lm3s_spistatus must be provided
+ * The external functions, lm_spiselect and lm_spistatus must be provided
  * by board-specific logic.  The are implementations of the select and status
  * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h).
  * All othermethods (including up_spiinitialize()) are provided by common
  * logic.  To use this common SPI logic on your board:
  *
- *   1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your
+ *   1. Provide lm_spiselect() and lm_spistatus() functions in your
  *      board-specific logic.  This function will perform chip selection and
  *      status operations using GPIOs in the way your board is configured.
  *   2. Add a call to up_spiinitialize() in your low level initialization
@@ -133,29 +133,29 @@ void weak_function lm3s_ssiinitialize(void)
  *
  ****************************************************************************/
 
-void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
   ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-  ssi_dumpgpio("lm3s_spiselect() Entry");
+  ssi_dumpgpio("lm_spiselect() Entry");
 
   if (devid == SPIDEV_MMCSD)
     {
       /* Assert the CS pin to the card */
 
-      lm3s_gpiowrite(SDCCS_GPIO, !selected);
+      lm_gpiowrite(SDCCS_GPIO, !selected);
     }
 #ifdef CONFIG_NX_LCDDRIVER
   else if (devid == SPIDEV_DISPLAY)
     {
       /* Assert the CS pin to the display */
 
-      lm3s_gpiowrite(OLEDCS_GPIO, !selected);
+      lm_gpiowrite(OLEDCS_GPIO, !selected);
     }
 #endif
-  ssi_dumpgpio("lm3s_spiselect() Exit");
+  ssi_dumpgpio("lm_spiselect() Exit");
 }
 
-uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 {
   ssidbg("Returning SPI_STATUS_PRESENT\n");
   return SPI_STATUS_PRESENT;
-- 
cgit v1.2.3


From 35cc14be43ed9ed33da6eb63d66627765cf9f157 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Wed, 9 Jan 2013 18:15:02 +0000
Subject: Change naming of all Stellaris pre-processor symbols from LM3S_ to
 LM_ to make room in the namespace for LM4F

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5498 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/arch/arm/include/lm/chip.h                   | 104 ++--
 nuttx/arch/arm/include/lm/irq.h                    | 650 ++++++++++-----------
 nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h        | 506 ++++++++--------
 nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h           |   2 +-
 nuttx/arch/arm/src/lm/chip/lm_epi.h                |  26 +-
 nuttx/arch/arm/src/lm/chip/lm_ethernet.h           | 100 ++--
 nuttx/arch/arm/src/lm/chip/lm_flash.h              |  94 +--
 nuttx/arch/arm/src/lm/chip/lm_gpio.h               | 646 ++++++++++----------
 nuttx/arch/arm/src/lm/chip/lm_i2c.h                | 142 ++---
 nuttx/arch/arm/src/lm/chip/lm_pinmap.h             |   2 +-
 nuttx/arch/arm/src/lm/chip/lm_ssi.h                | 268 ++++-----
 nuttx/arch/arm/src/lm/chip/lm_syscontrol.h         | 122 ++--
 nuttx/arch/arm/src/lm/chip/lm_timer.h              |  40 +-
 nuttx/arch/arm/src/lm/chip/lm_uart.h               | 260 ++++-----
 nuttx/arch/arm/src/lm/lm_dumpgpio.c                |  28 +-
 nuttx/arch/arm/src/lm/lm_ethernet.c                | 252 ++++----
 nuttx/arch/arm/src/lm/lm_ethernet.h                |   6 +-
 nuttx/arch/arm/src/lm/lm_gpio.c                    |  96 +--
 nuttx/arch/arm/src/lm/lm_gpioirq.c                 |  91 ++-
 nuttx/arch/arm/src/lm/lm_irq.c                     |  52 +-
 nuttx/arch/arm/src/lm/lm_lowputc.c                 |  92 +--
 nuttx/arch/arm/src/lm/lm_serial.c                  |  78 +--
 nuttx/arch/arm/src/lm/lm_ssi.c                     | 112 ++--
 nuttx/arch/arm/src/lm/lm_syscontrol.c              |  30 +-
 nuttx/arch/arm/src/lm/lm_timerisr.c                |   4 +-
 nuttx/arch/arm/src/lm/lm_vectors.S                 | 402 ++++++-------
 nuttx/configs/avr32dev1/README.txt                 |   6 +-
 nuttx/configs/eagle100/README.txt                  |   4 +-
 nuttx/configs/eagle100/include/board.h             |  12 +-
 nuttx/configs/eagle100/src/eagle100_internal.h     |   4 +-
 nuttx/configs/eagle100/src/up_boot.c               |   7 +-
 nuttx/configs/eagle100/src/up_ethernet.c           |   4 +-
 nuttx/configs/ekk-lm3s9b96/README.txt              |   8 +-
 nuttx/configs/ekk-lm3s9b96/include/board.h         |  12 +-
 .../ekk-lm3s9b96/src/ekklm3s9b96_internal.h        |   4 +-
 nuttx/configs/ekk-lm3s9b96/src/up_boot.c           |   7 +-
 nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c       |   4 +-
 nuttx/configs/lm3s6432-s2e/README.txt              |   4 +-
 nuttx/configs/lm3s6432-s2e/include/board.h         |  12 +-
 .../lm3s6432-s2e/src/lm3s6432s2e_internal.h        |   2 +-
 nuttx/configs/lm3s6432-s2e/src/up_boot.c           |   7 +-
 nuttx/configs/lm3s6432-s2e/src/up_ethernet.c       |   4 +-
 nuttx/configs/lm3s6965-ek/README.txt               |   8 +-
 nuttx/configs/lm3s6965-ek/include/board.h          |  12 +-
 nuttx/configs/lm3s6965-ek/nsh/defconfig            |   8 +-
 nuttx/configs/lm3s6965-ek/nx/defconfig             |   6 +-
 nuttx/configs/lm3s6965-ek/ostest/defconfig         |   6 +-
 .../configs/lm3s6965-ek/src/lm3s6965ek_internal.h  |   4 +-
 nuttx/configs/lm3s6965-ek/src/up_boot.c            |   7 +-
 nuttx/configs/lm3s6965-ek/src/up_ethernet.c        |   4 +-
 nuttx/configs/lm3s8962-ek/README.txt               |   8 +-
 nuttx/configs/lm3s8962-ek/include/board.h          |  12 +-
 .../configs/lm3s8962-ek/src/lm3s8962ek_internal.h  |   4 +-
 nuttx/configs/lm3s8962-ek/src/up_boot.c            |   7 +-
 nuttx/configs/lm3s8962-ek/src/up_ethernet.c        |   4 +-
 nuttx/configs/lpcxpresso-lpc1768/README.txt        |   2 +-
 nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c      |   4 +-
 nuttx/configs/nucleus2g/src/up_ssp.c               |   4 +-
 nuttx/include/nuttx/net/mii.h                      | 168 +++---
 59 files changed, 2288 insertions(+), 2286 deletions(-)

(limited to 'nuttx/arch')

diff --git a/nuttx/arch/arm/include/lm/chip.h b/nuttx/arch/arm/include/lm/chip.h
index 9eee51922..8293c7938 100644
--- a/nuttx/arch/arm/include/lm/chip.h
+++ b/nuttx/arch/arm/include/lm/chip.h
@@ -49,63 +49,63 @@
 /* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
 
 #if defined(CONFIG_ARCH_CHIP_LM3S6918)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            2  /* Two SSI modules */
-#  define LM3S_NUARTS          2  /* Two UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            0  /* No PWM generator modules */
-#  define LM3S_NQEI            0  /* No quadrature encoders */
-#  define LM3S_NPORTS          8  /* 8 Ports (GPIOA-H) 5-38 GPIOs */
+#  define LM_NTIMERS         4  /* Four general purpose timers */
+#  define LM_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM_ETHTS              /* No timestamp register */
+#  define LM_NSSI            2  /* Two SSI modules */
+#  define LM_NUARTS          2  /* Two UART modules */
+#  define LM_NI2C            2  /* Two I2C modules */
+#  define LM_NADC            1  /* One ADC module */
+#  define LM_NPWM            0  /* No PWM generator modules */
+#  define LM_NQEI            0  /* No quadrature encoders */
+#  define LM_NPORTS          8  /* 8 Ports (GPIOA-H) 5-38 GPIOs */
 #elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-#  define LM3S_NTIMERS         3  /* Three general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          2  /* Two UART modules */
-#  define LM3S_NI2C            1  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            1  /* One PWM generator module */
-#  define LM3S_NQEI            0  /* No quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
+#  define LM_NTIMERS         3  /* Three general purpose timers */
+#  define LM_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM_ETHTS              /* No timestamp register */
+#  define LM_NSSI            1  /* One SSI module */
+#  define LM_NUARTS          2  /* Two UART modules */
+#  define LM_NI2C            1  /* Two I2C modules */
+#  define LM_NADC            1  /* One ADC module */
+#  define LM_NPWM            1  /* One PWM generator module */
+#  define LM_NQEI            0  /* No quadrature encoders */
+#  define LM_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
 #elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          3  /* Three UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            3  /* Three PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
+#  define LM_NTIMERS         4  /* Four general purpose timers */
+#  define LM_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM_ETHTS              /* No timestamp register */
+#  define LM_NSSI            1  /* One SSI module */
+#  define LM_NUARTS          3  /* Three UART modules */
+#  define LM_NI2C            2  /* Two I2C modules */
+#  define LM_NADC            1  /* One ADC module */
+#  define LM_NPWM            3  /* Three PWM generator modules */
+#  define LM_NQEI            2  /* Two quadrature encoders */
+#  define LM_NPORTS          7  /* 7 Ports (GPIOA-G), 0-42 GPIOs */
 #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  undef  LM3S_ETHTS              /* No timestamp register */
-#  define LM3S_NSSI            2  /* Two SSI modules */
-#  define LM3S_NUARTS          3  /* Three UART modules */
-#  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NADC            2  /* Two ADC module */
-#  define LM3S_CAN             2  /* Two CAN module */
-#  define LM3S_NPWM            4  /* Four PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          9  /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
+#  define LM_NTIMERS         4  /* Four general purpose timers */
+#  define LM_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LM_ETHTS              /* No timestamp register */
+#  define LM_NSSI            2  /* Two SSI modules */
+#  define LM_NUARTS          3  /* Three UART modules */
+#  define LM_NI2C            2  /* Two I2C modules */
+#  define LM_NADC            2  /* Two ADC module */
+#  define LM_CAN             2  /* Two CAN module */
+#  define LM_NPWM            4  /* Four PWM generator modules */
+#  define LM_NQEI            2  /* Two quadrature encoders */
+#  define LM_NPORTS          9  /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
 #elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM3S_NTIMERS         4  /* Four general purpose timers */
-#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LM3S_NSSI            1  /* One SSI module */
-#  define LM3S_NUARTS          3  /* Two UART modules */
-#  define LM3S_NI2C            2  /* One I2C module */
-#  define LM3S_NADC            1  /* One ADC module */
-#  define LM2S_NPWM            3  /* Three PWM generator modules */
-#  define LM3S_NQEI            2  /* Two quadrature encoders */
-#  define LM3S_NPORTS          7  /* 7 Ports (GPIOA-G), 5-42 GPIOs */
-#  define LC3S_CANCONTROLLER   1  /* One CAN controller */
+#  define LM_NTIMERS         4  /* Four general purpose timers */
+#  define LM_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LM_NSSI            1  /* One SSI module */
+#  define LM_NUARTS          3  /* Two UART modules */
+#  define LM_NI2C            2  /* One I2C module */
+#  define LM_NADC            1  /* One ADC module */
+#  define LM_NPWM            3  /* Three PWM generator modules */
+#  define LM_NQEI            2  /* Two quadrature encoders */
+#  define LM_NPORTS          7  /* 7 Ports (GPIOA-G), 5-42 GPIOs */
+#  define LM_CANCONTROLLER   1  /* One CAN controller */
 #else
-#  error "Capabilities not specified for this LM3S chip"
+#  error "Capabilities not specified for this Stellaris chip"
 #endif
 
 /************************************************************************************
diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h
index 136496fef..9a5a3d153 100644
--- a/nuttx/arch/arm/include/lm/irq.h
+++ b/nuttx/arch/arm/include/lm/irq.h
@@ -58,250 +58,250 @@
 
 /* Processor Exceptions (vectors 0-15) */
 
-#define LM3S_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
-                                  /* Vector  0: Reset stack pointer value */
-                                  /* Vector  1: Reset (not handler as an IRQ) */
-#define LM3S_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define LM3S_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
-#define LM3S_IRQ_MEMFAULT     (4) /* Vector  4: Memory management (MPU) */
-#define LM3S_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
-#define LM3S_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
-#define LM3S_IRQ_SVCALL      (11) /* Vector 11: SVC call */
-#define LM3S_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
-                                  /* Vector 13: Reserved */
-#define LM3S_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
-#define LM3S_IRQ_SYSTICK     (15) /* Vector 15: System tick */
+#define LM_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+                                /* Vector  0: Reset stack pointer value */
+                                /* Vector  1: Reset (not handler as an IRQ) */
+#define LM_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define LM_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
+#define LM_IRQ_MEMFAULT     (4) /* Vector  4: Memory management (MPU) */
+#define LM_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
+#define LM_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
+#define LM_IRQ_SVCALL      (11) /* Vector 11: SVC call */
+#define LM_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
+                                /* Vector 13: Reserved */
+#define LM_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
+#define LM_IRQ_SYSTICK     (15) /* Vector 15: System tick */
 
 /* External interrupts (vectors >= 16) */
 
-#define LM3S_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
+#define LM_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
 #if defined(CONFIG_ARCH_CHIP_LM3S6918)
 
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-                                  /* Vector 25-29: Reserved */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                  /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-#  define LM3S_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
-                                  /* Vector 49: Reserved */
-#  define LM3S_IRQ_SSI1      (50) /* Vector 50: SSI 1 */
-#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-                                  /* Vectors 54-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                  /* Vectors 60-70: Reserved */
-#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+                                /* Vector 25-29: Reserved */
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+                                /* Vector 43: Reserved */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
+                                /* Vector 49: Reserved */
+#  define LM_IRQ_SSI1      (50) /* Vector 50: SSI 1 */
+#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+                                /* Vectors 54-57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+                                /* Vectors 60-70: Reserved */
+#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
 #elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-                                  /* Vector 25: Reserved */
-#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-                                  /* Vectors 27-29: Reserved */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                  /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                  /* Vectors 48-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-                                  /* Vectors 59-70: Reserved */
-#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+                                /* Vector 25: Reserved */
+#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+                                /* Vectors 27-29: Reserved */
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+                                /* Vector 43: Reserved */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+                                /* Vectors 48-57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+                                /* Vectors 59-70: Reserved */
+#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
 #elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                  /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                  /* Vector 48: Reserved */
-#  define LM3S_IRQ_UART2     (49) /* Vector 49: UART 2 */
-                                  /* Vector 50: Reserved */
-#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-                                  /* Vectors 55-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                  /* Vectors 60-70: Reserved */
-#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+                                /* Vector 43: Reserved */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+                                /* Vector 48: Reserved */
+#  define LM_IRQ_UART2     (49) /* Vector 49: UART 2 */
+                                /* Vector 50: Reserved */
+#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+                                /* Vectors 55-57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+                                /* Vectors 60-70: Reserved */
+#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
 #elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC0 Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC0 Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC0 Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC0 Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-#  define LM3S_IRQ_COMPARE2  (43) /* Vector 43: Analog Comparator 3 */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-#  define LM3S_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
-#  define LM3S_IRQ_UART2     (49) /* Vector 49: UART 2 */
-#  define LM3S_IRQ_SSI1      (50) /* Vector 50: SSI 1  */
-#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-#  define LM3S_IRQ_CAN0      (55) /* Vector 55: CAN 1 */
-#  define LM3S_IRQ_CAN1      (56) /* Vector 56: CAN 2 */
-                                  /* Vector 57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-                                  /* Vector 59: Reserved */
-#  define LM3S_IRQ_USB       (60) /* Vector 60: USB */
-#  define LM3S_IRQ_PWM3      (61) /* Vector 61: PWM Generator 3 */
-#  define LM3S_IRQ_UDMASOFT  (62) /* Vector 62: uDMA Software */
-#  define LM3S_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
-#  define LM3S_IRQ_ADC1_0    (64) /* Vector 64: ADC1 Sequence 0 */
-#  define LM3S_IRQ_ADC1_1    (65) /* Vector 65: ADC1 Sequence 1 */
-#  define LM3S_IRQ_ADC1_2    (66) /* Vector 66: ADC1 Sequence 2 */
-#  define LM3S_IRQ_ADC1_3    (67) /* Vector 67: ADC1 Sequence 3 */
-#  define LM3S_IRQ_I2S0      (68) /* Vector 68: I2S0 */
-#  define LM3S_IRQ_EPI       (69) /* Vector 69: EPI */
-#  define LM3S_IRQ_GPIOJ     (70) /* Vector 70: GPIO Port J */
-                                  /* Vector 71: Reserved */
-#  define NR_IRQS            (71) /* (Really less because of reserved vectors) */
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC0 Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC0 Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC0 Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC0 Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+#  define LM_IRQ_COMPARE2  (43) /* Vector 43: Analog Comparator 3 */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
+#  define LM_IRQ_UART2     (49) /* Vector 49: UART 2 */
+#  define LM_IRQ_SSI1      (50) /* Vector 50: SSI 1  */
+#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+#  define LM_IRQ_CAN0      (55) /* Vector 55: CAN 1 */
+#  define LM_IRQ_CAN1      (56) /* Vector 56: CAN 2 */
+                                /* Vector 57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+                                /* Vector 59: Reserved */
+#  define LM_IRQ_USB       (60) /* Vector 60: USB */
+#  define LM_IRQ_PWM3      (61) /* Vector 61: PWM Generator 3 */
+#  define LM_IRQ_UDMASOFT  (62) /* Vector 62: uDMA Software */
+#  define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
+#  define LM_IRQ_ADC1_0    (64) /* Vector 64: ADC1 Sequence 0 */
+#  define LM_IRQ_ADC1_1    (65) /* Vector 65: ADC1 Sequence 1 */
+#  define LM_IRQ_ADC1_2    (66) /* Vector 66: ADC1 Sequence 2 */
+#  define LM_IRQ_ADC1_3    (67) /* Vector 67: ADC1 Sequence 3 */
+#  define LM_IRQ_I2S0      (68) /* Vector 68: I2S0 */
+#  define LM_IRQ_EPI       (69) /* Vector 69: EPI */
+#  define LM_IRQ_GPIOJ     (70) /* Vector 70: GPIO Port J */
+                                /* Vector 71: Reserved */
+#  define NR_IRQS          (71) /* (Really less because of reserved vectors) */
 #elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-                                  /* Vector 42: Reserved */
-                                  /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                  /* Vector 48: Reserved */
-                                  /* Vector 49: Reserved */
-                                  /* Vector 50: Reserved */
-#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-#  define LM3S_IRQ_CAN0      (54) /* Vector 55: CAN0 */
-                                  /* Vectors 56-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                  /* Vectors 60-70: Reserved */
-#  define NR_IRQS            (60) /* (Really less because of reserved vectors) */
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+                                /* Vector 42: Reserved */
+                                /* Vector 43: Reserved */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+                                /* Vector 48: Reserved */
+                                /* Vector 49: Reserved */
+                                /* Vector 50: Reserved */
+#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+#  define LM_IRQ_CAN0      (54) /* Vector 55: CAN0 */
+                                /* Vectors 56-57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+                                /* Vectors 60-70: Reserved */
+#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
 #else
-#  error "IRQ Numbers not specified for this LM3S chip"
+#  error "IRQ Numbers not specified for this Stellaris chip"
 #endif
 
 /* GPIO IRQs -- Note that support for individual GPIO ports can
@@ -309,132 +309,132 @@
  */
 
 #ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
-#  define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0)
-#  define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1)
-#  define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2)
-#  define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3)
-#  define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4)
-#  define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5)
-#  define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6)
-#  define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7)
-#  define _NGPIOAIRQS      (NR_IRQS + 8)
+#  define LM_IRQ_GPIOA_0 (NR_IRQS + 0)
+#  define LM_IRQ_GPIOA_1 (NR_IRQS + 1)
+#  define LM_IRQ_GPIOA_2 (NR_IRQS + 2)
+#  define LM_IRQ_GPIOA_3 (NR_IRQS + 3)
+#  define LM_IRQ_GPIOA_4 (NR_IRQS + 4)
+#  define LM_IRQ_GPIOA_5 (NR_IRQS + 5)
+#  define LM_IRQ_GPIOA_6 (NR_IRQS + 6)
+#  define LM_IRQ_GPIOA_7 (NR_IRQS + 7)
+#  define _NGPIOAIRQS    (NR_IRQS + 8)
 #else
-#  define _NGPIOAIRQS      NR_IRQS
+#  define _NGPIOAIRQS    NR_IRQS
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
-#  define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
-#  define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
-#  define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
-#  define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
-#  define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
-#  define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
-#  define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
-#  define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
-#  define _NGPIOBIRQS      (_NGPIOAIRQS + 8)
+#  define LM_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
+#  define LM_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
+#  define LM_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
+#  define LM_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
+#  define LM_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
+#  define LM_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
+#  define LM_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
+#  define LM_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
+#  define _NGPIOBIRQS    (_NGPIOAIRQS + 8)
 #else
-#  define _NGPIOBIRQS      _NGPIOAIRQS
+#  define _NGPIOBIRQS    _NGPIOAIRQS
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
-#  define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
-#  define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
-#  define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
-#  define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
-#  define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
-#  define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
-#  define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
-#  define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
-#  define _NGPIOCIRQS      (_NGPIOBIRQS + 8)
+#  define LM_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
+#  define LM_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
+#  define LM_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
+#  define LM_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
+#  define LM_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
+#  define LM_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
+#  define LM_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
+#  define LM_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
+#  define _NGPIOCIRQS    (_NGPIOBIRQS + 8)
 #else
-#  define _NGPIOCIRQS      _NGPIOBIRQS
+#  define _NGPIOCIRQS    _NGPIOBIRQS
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
-#  define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
-#  define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
-#  define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
-#  define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
-#  define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
-#  define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
-#  define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
-#  define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
-#  define _NGPIODIRQS      (_NGPIOCIRQS + 8)
+#  define LM_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
+#  define LM_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
+#  define LM_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
+#  define LM_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
+#  define LM_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
+#  define LM_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
+#  define LM_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
+#  define LM_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
+#  define _NGPIODIRQS    (_NGPIOCIRQS + 8)
 #else
-#  define _NGPIODIRQS      _NGPIOCIRQS
+#  define _NGPIODIRQS    _NGPIOCIRQS
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
-#  define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
-#  define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
-#  define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
-#  define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
-#  define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
-#  define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
-#  define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
-#  define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
-#  define _NGPIOEIRQS      (_NGPIODIRQS + 8)
+#  define LM_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
+#  define LM_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
+#  define LM_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
+#  define LM_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
+#  define LM_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
+#  define LM_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
+#  define LM_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
+#  define LM_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
+#  define _NGPIOEIRQS    (_NGPIODIRQS + 8)
 #else
-#  define _NGPIOEIRQS      _NGPIODIRQS
+#  define _NGPIOEIRQS    _NGPIODIRQS
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
-#  define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
-#  define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
-#  define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
-#  define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
-#  define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
-#  define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
-#  define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
-#  define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
-#  define _NGPIOFIRQS      (_NGPIOEIRQS + 8)
+#  define LM_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
+#  define LM_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
+#  define LM_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
+#  define LM_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
+#  define LM_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
+#  define LM_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
+#  define LM_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
+#  define LM_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
+#  define _NGPIOFIRQS    (_NGPIOEIRQS + 8)
 #else
-#  define _NGPIOFIRQS      _NGPIOEIRQS
+#  define _NGPIOFIRQS    _NGPIOEIRQS
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
-#  define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
-#  define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
-#  define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
-#  define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
-#  define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
-#  define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
-#  define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
-#  define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
-#  define _NGPIOGIRQS      (_NGPIOFIRQS + 8)
+#  define LM_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
+#  define LM_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
+#  define LM_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
+#  define LM_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
+#  define LM_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
+#  define LM_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
+#  define LM_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
+#  define LM_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
+#  define _NGPIOGIRQS    (_NGPIOFIRQS + 8)
 #else
-#  define _NGPIOGIRQS      _NGPIOFIRQS
+#  define _NGPIOGIRQS    _NGPIOFIRQS
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
-#  define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
-#  define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
-#  define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
-#  define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
-#  define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
-#  define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
-#  define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
-#  define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
-#  define _NGPIOHIRQS      (_NGPIOGIRQS + 8)
+#  define LM_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
+#  define LM_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
+#  define LM_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
+#  define LM_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
+#  define LM_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
+#  define LM_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
+#  define LM_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
+#  define LM_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
+#  define _NGPIOHIRQS    (_NGPIOGIRQS + 8)
 #else
-#  define _NGPIOHIRQS      _NGPIOGIRQS
+#  define _NGPIOHIRQS    _NGPIOGIRQS
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
-#  define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
-#  define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
-#  define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
-#  define LM3S_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
-#  define LM3S_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
-#  define LM3S_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
-#  define LM3S_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
-#  define LM3S_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
-#  define _NGPIOJIRQS      (_NGPIOHIRQS + 8)
+#  define LM_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
+#  define LM_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
+#  define LM_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
+#  define LM_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
+#  define LM_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
+#  define LM_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
+#  define LM_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
+#  define LM_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
+#  define _NGPIOJIRQS    (_NGPIOHIRQS + 8)
 #else
-#  define _NGPIOJIRQS      _NGPIOHIRQS
+#  define _NGPIOJIRQS    _NGPIOHIRQS
 #endif
 
-#define NR_GPIO_IRQS       (_NGPIOJIRQS - NR_IRQS)
+#define NR_GPIO_IRQS     (_NGPIOJIRQS - NR_IRQS)
 
 /************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h
index 51de04a2b..32b7a9f18 100644
--- a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h
@@ -50,44 +50,44 @@
  
 #if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
     defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
-                                         /* -0x1fffffff: Reserved */
-#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
-                                         /* -0x21ffffff: Reserved */
-#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
-                                         /* -0x3fffffff: Reserved */
-#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
-                                         /* -0x41ffffff: Peripherals */
-#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
-                                         /* -0xdfffffff: Reserved */
-#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
-#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
-#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
-                                         /* -0xe000dfff: Reserved */
-#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
-                                         /* -0xe003ffff: Reserved */
-#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
-                                         /* -0xffffffff: Reserved */
+#  define LM_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
+                                       /* -0x1fffffff: Reserved */
+#  define LM_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
+                                       /* -0x21ffffff: Reserved */
+#  define LM_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
+                                       /* -0x3fffffff: Reserved */
+#  define LM_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
+                                       /* -0x41ffffff: Peripherals */
+#  define LM_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
+                                       /* -0xdfffffff: Reserved */
+#  define LM_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
+#  define LM_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
+#  define LM_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
+                                       /* -0xe000dfff: Reserved */
+#  define LM_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
+                                       /* -0xe003ffff: Reserved */
+#  define LM_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
+                                       /* -0xffffffff: Reserved */
 #elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-#  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
-                                         /* -0x1fffffff: Reserved */
-#  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
-                                         /* -0x21ffffff: Reserved */
-#  define LM3S_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
-                                         /* -0x3fffffff: Reserved */
-#  define LM3S_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
-                                         /* -0x41ffffff: Peripherals */
-#  define LM3S_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
-                                         /* -0x5fffffff: Reserved */
-#  define LM3S_EPI0RAM_BASE   0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */
-#  define LM3S_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
-#  define LM3S_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
-#  define LM3S_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
-                                         /* -0xe000dfff: Reserved */
-#  define LM3S_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
-                                         /* -0xe003ffff: Reserved */
-#  define LM3S_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
-                                         /* -0xffffffff: Reserved */
+#  define LM_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
+                                       /* -0x1fffffff: Reserved */
+#  define LM_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
+                                       /* -0x21ffffff: Reserved */
+#  define LM_ASRAM_BASE     0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
+                                       /* -0x3fffffff: Reserved */
+#  define LM_PERIPH_BASE    0x40000000 /* -0x4001ffff: FiRM Peripherals */
+                                       /* -0x41ffffff: Peripherals */
+#  define LM_APERIPH_BASE   0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
+                                       /* -0x5fffffff: Reserved */
+#  define LM_EPI0RAM_BASE   0x60000000 /* -0xdfffffff: EPI0 mapped peripheral and RAM */
+#  define LM_ITM_BASE       0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
+#  define LM_DWT_BASE       0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
+#  define LM_FPB_BASE       0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
+                                       /* -0xe000dfff: Reserved */
+#  define LM_NVIC_BASE      0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
+                                       /* -0xe003ffff: Reserved */
+#  define LM_TPIU_BASE      0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
+                                       /* -0xffffffff: Reserved */
 #else
 #  error "Memory map not specified for this LM3S chip"
 #endif
@@ -102,247 +102,247 @@
 #if defined(CONFIG_ARCH_CHIP_LM3S6918)
 /* FiRM Peripheral Base Addresses */
 
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
+#  define LM_WDOG_BASE      (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                       /* -0x03fff: Reserved */
+#  define LM_GPIOA_BASE     (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM_GPIOB_BASE     (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM_GPIOC_BASE     (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM_GPIOD_BASE     (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM_SSI0_BASE      (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+#  define LM_SSI1_BASE      (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
+                                                       /* -0x0bfff: Reserved */
+#  define LM_UART0_BASE     (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM_UART1_BASE     (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                       /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
+#  define LM_I2CM0_BASE     (LM_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM_I2CS0_BASE     (LM_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM_I2CM1_BASE     (LM_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM_I2CS1_BASE     (LM_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                        /* -0x23fff: Reserved */
+#  define LM_GPIOE_BASE     (LM_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM_GPIOF_BASE     (LM_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM_GPIOG_BASE     (LM_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+#  define LM_GPIOH_BASE     (LM_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
+                                                        /* -0x2ffff: Reserved */
+#  define LM_TIMER0_BASE    (LM_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM_TIMER1_BASE    (LM_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM_TIMER2_BASE    (LM_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM_TIMER3_BASE    (LM_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                        /* -0x37fff: Reserved */
+#  define LM_ADC_BASE       (LM_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                        /* -0x3bfff: Reserved */
+#  define LM_COMPARE_BASE   (LM_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                        /* -0x47fff: Reserved */
+#  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                        /* -0xfcfff: Reserved */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                        /* -0x1ffffff: Reserved */
 #elif defined(CONFIG_ARCH_CHIP_LM3S6432)
 /* FiRM Peripheral Base Addresses */
 
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
+#  define LM_WDOG_BASE      (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                       /* -0x03fff: Reserved */
+#  define LM_GPIOA_BASE     (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM_GPIOB_BASE     (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM_GPIOC_BASE     (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM_GPIOD_BASE     (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM_SSI0_BASE      (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                       /* -0x0bfff: Reserved */
+#  define LM_UART0_BASE     (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM_UART1_BASE     (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                       /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
+#  define LM_I2CM0_BASE     (LM_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM_I2CS0_BASE     (LM_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+                                                        /* -0x23fff: Reserved */
+#  define LM_GPIOE_BASE     (LM_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM_GPIOF_BASE     (LM_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM_GPIOG_BASE     (LM_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                        /* -0x27fff: Reserved */
+#  define LM_PWM0_BASE      (LM_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                        /* -0x2ffff: Reserved */
+#  define LM_TIMER0_BASE    (LM_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM_TIMER1_BASE    (LM_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM_TIMER2_BASE    (LM_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+                                                        /* -0x37fff: Reserved */
+#  define LM_ADC_BASE       (LM_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                        /* -0x3bfff: Reserved */
+#  define LM_COMPARE_BASE   (LM_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                        /* -0x47fff: Reserved */
+#  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                        /* -0xfcfff: Reserved */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                        /* -0x1ffffff: Reserved */
 
 #elif defined(CONFIG_ARCH_CHIP_LM3S6965)
 /* FiRM Peripheral Base Addresses */
 
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
-                                                           /* -0x1ffff: Reserved */
+#  define LM_WDOG_BASE      (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                       /* -0x03fff: Reserved */
+#  define LM_GPIOA_BASE     (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM_GPIOB_BASE     (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM_GPIOC_BASE     (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM_GPIOD_BASE     (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM_SSI0_BASE      (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                       /* -0x0bfff: Reserved */
+#  define LM_UART0_BASE     (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM_UART1_BASE     (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define LM_UART2_BASE     (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
+                                                       /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
+#  define LM_I2CM0_BASE     (LM_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM_I2CS0_BASE     (LM_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM_I2CM1_BASE     (LM_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM_I2CS1_BASE     (LM_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                        /* -0x23fff: Reserved */
+#  define LM_GPIOE_BASE     (LM_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM_GPIOF_BASE     (LM_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM_GPIOG_BASE     (LM_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                        /* -0x27fff: Reserved */
+#  define LM_PWM0_BASE      (LM_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                        /* -0x2bfff: Reserved */
+#  define LM_QEI0_BASE      (LM_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM_QEI1_BASE      (LM_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                        /* -0x2ffff: Reserved */
+#  define LM_TIMER0_BASE    (LM_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM_TIMER1_BASE    (LM_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM_TIMER2_BASE    (LM_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM_TIMER3_BASE    (LM_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                        /* -0x37fff: Reserved */
+#  define LM_ADC_BASE       (LM_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                        /* -0x3bfff: Reserved */
+#  define LM_COMPARE_BASE   (LM_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                        /* -0x47fff: Reserved */
+#  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                        /* -0xfcfff: Reserved */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                        /* -0x1ffffff: Reserved */
 #elif defined(CONFIG_ARCH_CHIP_LM3S8962)
 /* FiRM Peripheral Base Addresses */
 
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-                                                           /* -0x1ffff: Reserved */
+#  define LM_WDOG_BASE      (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                       /* -0x03fff: Reserved */
+#  define LM_GPIOA_BASE     (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM_GPIOB_BASE     (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM_GPIOC_BASE     (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM_GPIOD_BASE     (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM_SSI0_BASE      (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                       /* -0x0bfff: Reserved */
+#  define LM_UART0_BASE     (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM_UART1_BASE     (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+                                                       /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-                                                            /* -0x27fff: Reserved */
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-                                                            /* -0x3fffff: Reserved */
-#  define LM3S_CANCON_BASE    (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN Controller */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-                                                            /* -0x1ffffff: Reserved */
+#  define LM_I2CM0_BASE     (LM_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM_I2CS0_BASE     (LM_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+                                                        /* -0x23fff: Reserved */
+#  define LM_GPIOE_BASE     (LM_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM_GPIOF_BASE     (LM_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM_GPIOG_BASE     (LM_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                        /* -0x27fff: Reserved */
+#  define LM_PWM0_BASE      (LM_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                        /* -0x2bfff: Reserved */
+#  define LM_QEI0_BASE      (LM_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM_QEI1_BASE      (LM_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                        /* -0x2ffff: Reserved */
+#  define LM_TIMER0_BASE    (LM_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM_TIMER1_BASE    (LM_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM_TIMER2_BASE    (LM_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM_TIMER3_BASE    (LM_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                        /* -0x37fff: Reserved */
+#  define LM_ADC_BASE       (LM_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                        /* -0x3bfff: Reserved */
+#  define LM_COMPARE_BASE   (LM_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                        /* -0x3fffff: Reserved */
+#  define LM_CANCON_BASE    (LM_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN Controller */
+                                                        /* -0x47fff: Reserved */
+#  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                        /* -0xfcfff: Reserved */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
+#  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                        /* -0x1ffffff: Reserved */
 #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) 
 /* FiRM Peripheral Base Addresses */
 
-#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
-                                                           /* -0x03fff: Reserved */
-#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-#  define LM3S_SSI1_BASE      (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
-                                                           /* -0x0bfff: Reserved */
-#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
-#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
-                                                           /* -0x1ffff: Reserved */
+#  define LM_WDOG_BASE      (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                       /* -0x03fff: Reserved */
+#  define LM_GPIOA_BASE     (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM_GPIOB_BASE     (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM_GPIOC_BASE     (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM_GPIOD_BASE     (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM_SSI0_BASE      (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+#  define LM_SSI1_BASE      (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
+                                                       /* -0x0bfff: Reserved */
+#  define LM_UART0_BASE     (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM_UART1_BASE     (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define LM_UART2_BASE     (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
+                                                       /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
-                                                            /* -0x23fff: Reserved */
-#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
-#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
-#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
-#  define LM3S_GPIOH_BASE     (LM3S_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
+#  define LM_I2CM0_BASE     (LM_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM_I2CS0_BASE     (LM_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM_I2CM1_BASE     (LM_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM_I2CS1_BASE     (LM_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                        /* -0x23fff: Reserved */
+#  define LM_GPIOE_BASE     (LM_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM_GPIOF_BASE     (LM_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM_GPIOG_BASE     (LM_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+#  define LM_GPIOH_BASE     (LM_PERIPH_BASE + 0x27000)  /* -0x27fff: GPIO Port H */
 
-#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
-                                                            /* -0x2bfff: Reserved */
-#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
-#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
-                                                            /* -0x2ffff: Reserved */
-#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
-#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
-#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
-#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
-                                                            /* -0x37fff: Reserved */
-#  define LM3S_ADC0_BASE       (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
-#  define LM3S_ADC1_BASE       (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
-                                                            /* -0x3bfff: Reserved */
-#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
-#  define LM3S_GPIOJ_BASE     (LM3S_PERIPH_BASE + 0x3d000)  /* -0x3dfff: GPIO Port J */
-                                                            /* -0x3ffff: Reserved */
-#  define LM3S_CAN0_BASE      (LM3S_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN 0 */
-#  define LM3S_CAN1_BASE      (LM3S_PERIPH_BASE + 0x41000)  /* -0x41fff: CAN 1 */
-                                                            /* -0x47fff: Reserved */
-#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
-                                                            /* -0x49fff: Reserved */
-#  define LM3S_USB_BASE       (LM3S_PERIPH_BASE + 0x50000)  /* -0x50fff: USB */
-                                                            /* -0x53fff: Reserved */
-#  define LM3S_I2S0_BASE      (LM3S_PERIPH_BASE + 0x54000)  /* -0x54fff: I2S 0 */
-                                                            /* -0x57fff: Reserved */
-#  define LM3S_GPIOAAHB_BASE  (LM3S_PERIPH_BASE + 0x58000)  /* -0x58fff: GPIO Port A (AHB aperture) */
-#  define LM3S_GPIOBAHB_BASE  (LM3S_PERIPH_BASE + 0x59000)  /* -0x59fff: GPIO Port B (AHB aperture) */
-#  define LM3S_GPIOCAHB_BASE  (LM3S_PERIPH_BASE + 0x5A000)  /* -0x5afff: GPIO Port C (AHB aperture) */
-#  define LM3S_GPIODAHB_BASE  (LM3S_PERIPH_BASE + 0x5B000)  /* -0x5bfff: GPIO Port D (AHB aperture) */
-#  define LM3S_GPIOEAHB_BASE  (LM3S_PERIPH_BASE + 0x5C000)  /* -0x5cfff: GPIO Port E (AHB aperture) */
-#  define LM3S_GPIOFAHB_BASE  (LM3S_PERIPH_BASE + 0x5D000)  /* -0x5dfff: GPIO Port F (AHB aperture) */
-#  define LM3S_GPIOGAHB_BASE  (LM3S_PERIPH_BASE + 0x5E000)  /* -0x5efff: GPIO Port G (AHB aperture) */
-#  define LM3S_GPIOHAHB_BASE  (LM3S_PERIPH_BASE + 0x5F000)  /* -0x5ffff: GPIO Port H (AHB aperture) */
-#  define LM3S_GPIOJAHB_BASE  (LM3S_PERIPH_BASE + 0x60000)  /* -0x60fff: GPIO Port J (AHB aperture) */
-                                                            /* -0xcffff: Reserved */
-#  define LM3S_EPI0_BASE      (LM3S_PERIPH_BASE + 0xD0000)  /* -0xd0fff: EPI 0 */
-                                                            /* -0xfcfff: Reserved */
-#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
-#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
-#  define LM3S_UDMA_BASE      (LM3S_PERIPH_BASE + 0xff000)  /* -0xfffff: System Control */
-                                                            /* -0x1ffffff: Reserved */
+#  define LM_PWM0_BASE      (LM_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                        /* -0x2bfff: Reserved */
+#  define LM_QEI0_BASE      (LM_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM_QEI1_BASE      (LM_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                        /* -0x2ffff: Reserved */
+#  define LM_TIMER0_BASE    (LM_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM_TIMER1_BASE    (LM_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM_TIMER2_BASE    (LM_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM_TIMER3_BASE    (LM_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                        /* -0x37fff: Reserved */
+#  define LM_ADC0_BASE       (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
+#  define LM_ADC1_BASE       (LM_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
+                                                        /* -0x3bfff: Reserved */
+#  define LM_COMPARE_BASE   (LM_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+#  define LM_GPIOJ_BASE     (LM_PERIPH_BASE + 0x3d000)  /* -0x3dfff: GPIO Port J */
+                                                        /* -0x3ffff: Reserved */
+#  define LM_CAN0_BASE      (LM_PERIPH_BASE + 0x40000)  /* -0x40fff: CAN 0 */
+#  define LM_CAN1_BASE      (LM_PERIPH_BASE + 0x41000)  /* -0x41fff: CAN 1 */
+                                                        /* -0x47fff: Reserved */
+#  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                        /* -0x49fff: Reserved */
+#  define LM_USB_BASE       (LM_PERIPH_BASE + 0x50000)  /* -0x50fff: USB */
+                                                        /* -0x53fff: Reserved */
+#  define LM_I2S0_BASE      (LM_PERIPH_BASE + 0x54000)  /* -0x54fff: I2S 0 */
+                                                        /* -0x57fff: Reserved */
+#  define LM_GPIOAAHB_BASE  (LM_PERIPH_BASE + 0x58000)  /* -0x58fff: GPIO Port A (AHB aperture) */
+#  define LM_GPIOBAHB_BASE  (LM_PERIPH_BASE + 0x59000)  /* -0x59fff: GPIO Port B (AHB aperture) */
+#  define LM_GPIOCAHB_BASE  (LM_PERIPH_BASE + 0x5A000)  /* -0x5afff: GPIO Port C (AHB aperture) */
+#  define LM_GPIODAHB_BASE  (LM_PERIPH_BASE + 0x5B000)  /* -0x5bfff: GPIO Port D (AHB aperture) */
+#  define LM_GPIOEAHB_BASE  (LM_PERIPH_BASE + 0x5C000)  /* -0x5cfff: GPIO Port E (AHB aperture) */
+#  define LM_GPIOFAHB_BASE  (LM_PERIPH_BASE + 0x5D000)  /* -0x5dfff: GPIO Port F (AHB aperture) */
+#  define LM_GPIOGAHB_BASE  (LM_PERIPH_BASE + 0x5E000)  /* -0x5efff: GPIO Port G (AHB aperture) */
+#  define LM_GPIOHAHB_BASE  (LM_PERIPH_BASE + 0x5F000)  /* -0x5ffff: GPIO Port H (AHB aperture) */
+#  define LM_GPIOJAHB_BASE  (LM_PERIPH_BASE + 0x60000)  /* -0x60fff: GPIO Port J (AHB aperture) */
+                                                        /* -0xcffff: Reserved */
+#  define LM_EPI0_BASE      (LM_PERIPH_BASE + 0xD0000)  /* -0xd0fff: EPI 0 */
+                                                        /* -0xfcfff: Reserved */
+#  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+#  define LM_UDMA_BASE      (LM_PERIPH_BASE + 0xff000)  /* -0xfffff: System Control */
+                                                        /* -0x1ffffff: Reserved */
 #else
-#  error "Peripheral base addresses not specified for this LM3S chip"
+#  error "Peripheral base addresses not specified for this Stellaris chip"
 #endif
 
 /************************************************************************************
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
index a478304b0..ca1d53064 100644
--- a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h
@@ -263,7 +263,7 @@
 #  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT  | GPIO_PORTF | 3)       /* PF3: LED0 */
 #  define GPIO_PWM0_1     (GPIO_FUNC_PFOUTPUT  | GPIO_PORTG | 1)       /* PG1:PWM Generator 0, PWM1 */
 #else
-#  error "Unknown LM3S chip"
+#  error "Unknown Stellaris chip"
 #endif
 
 /************************************************************************************
diff --git a/nuttx/arch/arm/src/lm/chip/lm_epi.h b/nuttx/arch/arm/src/lm/chip/lm_epi.h
index e36986079..47d790615 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_epi.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_epi.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H
 
 /************************************************************************************
  * Included Files
@@ -46,19 +46,19 @@
 
 /* External Peripheral Interface Register Offsets ***********************************/
 
-#define LM3S_EPI_CFG_OFFSET           0x000
-#define LM3S_EPI_SDRAMCFG_OFFSET      0x010
-#define LM3S_EPI_ADDRMAP_OFFSET       0x01C
-#define LM3S_EPI_STAT_OFFSET          0x060
-#define LM3S_EPI_BAUD_OFFSET          0x004
+#define LM_EPI_CFG_OFFSET             0x000
+#define LM_EPI_SDRAMCFG_OFFSET        0x010
+#define LM_EPI_ADDRMAP_OFFSET         0x01C
+#define LM_EPI_STAT_OFFSET            0x060
+#define LM_EPI_BAUD_OFFSET            0x004
 
 /* External Peripheral Interface Register Addresses *********************************/
 
-#define LM3S_EPI0_CFG                 (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
-#define LM3S_EPI0_SDRAMCFG            (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
-#define LM3S_EPI0_ADDRMAP             (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
-#define LM3S_EPI0_STAT                (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
-#define LM3S_EPI0_BAUD                (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
+#define LM_EPI0_CFG                   (LM_EPI0_BASE + LM_EPI_CFG_OFFSET)
+#define LM_EPI0_SDRAMCFG              (LM_EPI0_BASE + LM_EPI_SDRAMCFG_OFFSET)
+#define LM_EPI0_ADDRMAP               (LM_EPI0_BASE + LM_EPI_ADDRMAP_OFFSET)
+#define LM_EPI0_STAT                  (LM_EPI0_BASE + LM_EPI_STAT_OFFSET)
+#define LM_EPI0_BAUD                  (LM_EPI0_BASE + LM_EPI_BAUD_OFFSET)
 
 /* External Peripheral Interface Register Bit Definitions ***************************/
 
@@ -110,4 +110,4 @@
 #define EPI_BAUD_COUNT0_MASK          (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
 #  define EPI_BAUD_COUNT0(n)          ((n) << EPI_BAUD_COUNT0_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h
index 46a101005..02908d222 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_ethernet.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H
 
 /************************************************************************************
  * Included Files
@@ -53,63 +53,63 @@
 
 /* Ethernet MAC Register Offsets */
 
-#define LM3S_MAC_RIS_OFFSET   0x000 /* Ethernet MAC Raw Interrupt Status */
-#define LM3S_MAC_IACK_OFFSET  0x000 /* Ethernet MAC Acknowledge */
-#define LM3S_MAC_IM_OFFSET    0x004 /* Ethernet MAC Interrupt Mask */
-#define LM3S_MAC_RCTL_OFFSET  0x008 /* Ethernet MAC Receive Control */
-#define LM3S_MAC_TCTL_OFFSET  0x00c /* Ethernet MAC Transmit Control */
-#define LM3S_MAC_DATA_OFFSET  0x010 /* Ethernet MAC Data */
-#define LM3S_MAC_IA0_OFFSET   0x014 /* Ethernet MAC Individual Address 0 */
-#define LM3S_MAC_IA1_OFFSET   0x018 /* Ethernet MAC Individual Address 1 */
-#define LM3S_MAC_THR_OFFSET   0x01c /* Ethernet MAC Threshold */
-#define LM3S_MAC_MCTL_OFFSET  0x020 /* Ethernet MAC Management Control */
-#define LM3S_MAC_MDV_OFFSET   0x024 /* Ethernet MAC Management Divider */
-#define LM3S_MAC_MTXD_OFFSET  0x02c /* Ethernet MAC Management Transmit Data */
-#define LM3S_MAC_MRXD_OFFSET  0x030 /* Ethernet MAC Management Receive Data */
-#define LM3S_MAC_NP_OFFSET    0x034 /* Ethernet MAC Number of Packets */
-#define LM3S_MAC_TR_OFFSET    0x038 /* Ethernet MAC Transmission Request */
-#ifdef LM3S_ETHTS
-#  define LM3S_MAC_TS_OFFSET  0x03c /* Ethernet MAC Time Stamp Configuration */
+#define LM_MAC_RIS_OFFSET     0x000 /* Ethernet MAC Raw Interrupt Status */
+#define LM_MAC_IACK_OFFSET    0x000 /* Ethernet MAC Acknowledge */
+#define LM_MAC_IM_OFFSET      0x004 /* Ethernet MAC Interrupt Mask */
+#define LM_MAC_RCTL_OFFSET    0x008 /* Ethernet MAC Receive Control */
+#define LM_MAC_TCTL_OFFSET    0x00c /* Ethernet MAC Transmit Control */
+#define LM_MAC_DATA_OFFSET    0x010 /* Ethernet MAC Data */
+#define LM_MAC_IA0_OFFSET     0x014 /* Ethernet MAC Individual Address 0 */
+#define LM_MAC_IA1_OFFSET     0x018 /* Ethernet MAC Individual Address 1 */
+#define LM_MAC_THR_OFFSET     0x01c /* Ethernet MAC Threshold */
+#define LM_MAC_MCTL_OFFSET    0x020 /* Ethernet MAC Management Control */
+#define LM_MAC_MDV_OFFSET     0x024 /* Ethernet MAC Management Divider */
+#define LM_MAC_MTXD_OFFSET    0x02c /* Ethernet MAC Management Transmit Data */
+#define LM_MAC_MRXD_OFFSET    0x030 /* Ethernet MAC Management Receive Data */
+#define LM_MAC_NP_OFFSET      0x034 /* Ethernet MAC Number of Packets */
+#define LM_MAC_TR_OFFSET      0x038 /* Ethernet MAC Transmission Request */
+#ifdef LM_ETHTS
+#  define LM_MAC_TS_OFFSET    0x03c /* Ethernet MAC Time Stamp Configuration */
 #endif
 
 /* MII Management Register Offsets (see include/nuttx/net/mii.h) */
 
 /* Ethernet Controller Register Addresses *******************************************/
 
-#define LM3S_MAC_RIS          (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
-#define LM3S_MAC_IACK         (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
-#define LM3S_MAC_IM           (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
-#define LM3S_MAC_RCTL         (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
-#define LM3S_MAC_TCTL         (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
-#define LM3S_MAC_DATA         (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
-#define LM3S_MAC_IA0          (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
-#define LM3S_MAC_IA1          (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
-#define LM3S_MAC_THR          (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
-#define LM3S_MAC_MCTL         (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
-#define LM3S_MAC_MDV          (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
-#define LM3S_MAC_MTXD         (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
-#define LM3S_MAC_MRXD         (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
-#define LM3S_MAC_NP           (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
-#define LM3S_MAC_TR           (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
-#ifdef LM3S_ETHTS
-#  define LM3S_MAC_TS         (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
+#define LM_MAC_RIS            (LM_ETHCON_BASE + LM_MAC_RIS_OFFSET)
+#define LM_MAC_IACK           (LM_ETHCON_BASE + LM_MAC_IACK_OFFSET)
+#define LM_MAC_IM             (LM_ETHCON_BASE + LM_MAC_IM_OFFSET)
+#define LM_MAC_RCTL           (LM_ETHCON_BASE + LM_MAC_RCTL_OFFSET)
+#define LM_MAC_TCTL           (LM_ETHCON_BASE + LM_MAC_TCTL_OFFSET)
+#define LM_MAC_DATA           (LM_ETHCON_BASE + LM_MAC_DATA_OFFSET)
+#define LM_MAC_IA0            (LM_ETHCON_BASE + LM_MAC_IA0_OFFSET)
+#define LM_MAC_IA1            (LM_ETHCON_BASE + LM_MAC_IA1_OFFSET)
+#define LM_MAC_THR            (LM_ETHCON_BASE + LM_MAC_THR_OFFSET)
+#define LM_MAC_MCTL           (LM_ETHCON_BASE + LM_MAC_MCTL_OFFSET)
+#define LM_MAC_MDV            (LM_ETHCON_BASE + LM_MAC_MDV_OFFSET)
+#define LM_MAC_MTXD           (LM_ETHCON_BASE + LM_MAC_MTXD_OFFSET)
+#define LM_MAC_MRXD           (LM_ETHCON_BASE + LM_MAC_MRXD_OFFSET)
+#define LM_MAC_NP             (LM_ETHCON_BASE + LM_MAC_NP_OFFSET)
+#define LM_MAC_TR             (LM_ETHCON_BASE + LM_MAC_TR_OFFSET)
+#ifdef LM_ETHTS
+#  define LM_MAC_TS           (LM_ETHCON_BASE + LM_MAC_TS_OFFSET)
 #endif
 
 /* Memory Mapped MII Management Registers */
 
-#define MAC_MII_MCR           (LM3S_ETHCON_BASE + MII_MCR)
-#define MAC_MII_MSR           (LM3S_ETHCON_BASE + MII_MSR)
-#define MAC_MII_PHYID1        (LM3S_ETHCON_BASE + MII_PHYID1)
-#define MAC_MII_PHYID2        (LM3S_ETHCON_BASE + MII_PHYID2)
-#define MAC_MII_ADVERTISE     (LM3S_ETHCON_BASE + MII_ADVERTISE)
-#define MAC_MII_LPA           (LM3S_ETHCON_BASE + MII_LPA)
-#define MAC_MII_EXPANSION     (LM3S_ETHCON_BASE + MII_EXPANSION)
-#define MAC_MII_VSPECIFIC     (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
-#define MAC_MII_INTCS         (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
-#define MAC_MII_DIAGNOSTIC    (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
-#define MAC_MII_XCVRCONTROL   (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
-#define MAC_MII_LEDCONFIG     (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
-#define MAC_MII_MDICONTROL    (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
+#define MAC_MII_MCR           (LM_ETHCON_BASE + MII_MCR)
+#define MAC_MII_MSR           (LM_ETHCON_BASE + MII_MSR)
+#define MAC_MII_PHYID1        (LM_ETHCON_BASE + MII_PHYID1)
+#define MAC_MII_PHYID2        (LM_ETHCON_BASE + MII_PHYID2)
+#define MAC_MII_ADVERTISE     (LM_ETHCON_BASE + MII_ADVERTISE)
+#define MAC_MII_LPA           (LM_ETHCON_BASE + MII_LPA)
+#define MAC_MII_EXPANSION     (LM_ETHCON_BASE + MII_EXPANSION)
+#define MAC_MII_VSPECIFIC     (LM_ETHCON_BASE + MII_LM_VSPECIFIC)
+#define MAC_MII_INTCS         (LM_ETHCON_BASE + MII_LM_INTCS)
+#define MAC_MII_DIAGNOSTIC    (LM_ETHCON_BASE + MII_LM_DIAGNOSTIC)
+#define MAC_MII_XCVRCONTROL   (LM_ETHCON_BASE + MII_LM_XCVRCONTROL)
+#define MAC_MII_LEDCONFIG     (LM_ETHCON_BASE + MII_LM_LEDCONFIG)
+#define MAC_MII_MDICONTROL    (LM_ETHCON_BASE + MII_LM_MDICONTROL)
 
 /* Ethernet Controller Register Bit Definitions *************************************/
 
@@ -200,4 +200,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_flash.h b/nuttx/arch/arm/src/lm/chip/lm_flash.h
index 0d4808526..e5869bb0e 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_flash.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_flash.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -49,66 +49,66 @@
 /* FLASH register offsets ***********************************************************/
 
 /* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
- * control base address of LM3S_FLASHCON_BASE.
+ * control base address of LM_FLASHCON_BASE.
  */
 
-#define LM3S_FLASH_FMA_OFFSET       0x000 /* Flash memory address */
-#define LM3S_FLASH_FMD_OFFSET       0x004 /* Flash memory data */
-#define LM3S_FLASH_FMC_OFFSET       0x008 /* Flash memory control */
-#define LM3S_FLASH_FCRIS_OFFSET     0x00c /* Flash controller raw interrupt status */
-#define LM3S_FLASH_FCIM_OFFSET      0x010 /* Flash controller interrupt mask */
-#define LM3S_FLASH_FCMISC_OFFSET    0x014 /* Flash controller masked interrupt status and clear */ */
+#define LM_FLASH_FMA_OFFSET       0x000 /* Flash memory address */
+#define LM_FLASH_FMD_OFFSET       0x004 /* Flash memory data */
+#define LM_FLASH_FMC_OFFSET       0x008 /* Flash memory control */
+#define LM_FLASH_FCRIS_OFFSET     0x00c /* Flash controller raw interrupt status */
+#define LM_FLASH_FCIM_OFFSET      0x010 /* Flash controller interrupt mask */
+#define LM_FLASH_FCMISC_OFFSET    0x014 /* Flash controller masked interrupt status and clear */
 
 /* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
- * System Control base address of LM3S_SYSCON_BASE
+ * System Control base address of LM_SYSCON_BASE
  */
 
-#define LM3S_FLASH_FMPRE_OFFSET     0x130 /* Flash memory protection read enable */
-#define LM3S_FLASH_FMPPE_OFFSET     0x134 /* Flash memory protection program enable */
-#define LM3S_FLASH_USECRL_OFFSET    0x140 /* USec Reload */
-#define LM3S_FLASH_USERDBG_OFFSET   0x1d0 /* User Debug */
-#define LM3S_FLASH_USERREG0_OFFSET  0x1e0 /* User Register 0 */
-#define LM3S_FLASH_USERREG1_OFFSET  0x1e4 /* User Register 1 */
-#define LM3S_FLASH_FMPRE0_OFFSET    0x200 /* Flash Memory Protection Read Enable 0 */
-#define LM3S_FLASH_FMPRE1_OFFSET    0x204 /* Flash Memory Protection Read Enable 1 */
-#define LM3S_FLASH_FMPRE2_OFFSET    0x208 /* Flash Memory Protection Read Enable 2 */
-#define LM3S_FLASH_FMPRE3_OFFSET    0x20c /* Flash Memory Protection Read Enable 3 */
-#define LM3S_FLASH_FMPPE0_OFFSET    0x400 /* Flash Memory Protection Program Enable 0 */
-#define LM3S_FLASH_FMPPE1_OFFSET    0x404 /* Flash Memory Protection Program Enable 1 */
-#define LM3S_FLASH_FMPPE2_OFFSET    0x408 /* Flash Memory Protection Program Enable 2 */
-#define LM3S_FLASH_FMPPE3_OFFSET    0x40c /*  Flash Memory Protection Program Enable 3 */
+#define LM_FLASH_FMPRE_OFFSET     0x130 /* Flash memory protection read enable */
+#define LM_FLASH_FMPPE_OFFSET     0x134 /* Flash memory protection program enable */
+#define LM_FLASH_USECRL_OFFSET    0x140 /* USec Reload */
+#define LM_FLASH_USERDBG_OFFSET   0x1d0 /* User Debug */
+#define LM_FLASH_USERREG0_OFFSET  0x1e0 /* User Register 0 */
+#define LM_FLASH_USERREG1_OFFSET  0x1e4 /* User Register 1 */
+#define LM_FLASH_FMPRE0_OFFSET    0x200 /* Flash Memory Protection Read Enable 0 */
+#define LM_FLASH_FMPRE1_OFFSET    0x204 /* Flash Memory Protection Read Enable 1 */
+#define LM_FLASH_FMPRE2_OFFSET    0x208 /* Flash Memory Protection Read Enable 2 */
+#define LM_FLASH_FMPRE3_OFFSET    0x20c /* Flash Memory Protection Read Enable 3 */
+#define LM_FLASH_FMPPE0_OFFSET    0x400 /* Flash Memory Protection Program Enable 0 */
+#define LM_FLASH_FMPPE1_OFFSET    0x404 /* Flash Memory Protection Program Enable 1 */
+#define LM_FLASH_FMPPE2_OFFSET    0x408 /* Flash Memory Protection Program Enable 2 */
+#define LM_FLASH_FMPPE3_OFFSET    0x40c /*  Flash Memory Protection Program Enable 3 */
 
 /* FLASH register addresses *********************************************************/
 
 /* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
- * control base address of LM3S_FLASHCON_BASE.
+ * control base address of LM_FLASHCON_BASE.
  */
 
-#define LM3S_FLASH_FMA              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
-#define LM3S_FLASH_FMD              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
-#define LM3S_FLASH_FMC              (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
-#define LM3S_FLASH_FCRIS            (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
-#define LM3S_FLASH_FCIM             (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
-#define LM3S_FLASH_FCMISC           (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
+#define LM_FLASH_FMA              (LM_FLASHCON_BASE + LM_FLASH_FMA_OFFSET)
+#define LM_FLASH_FMD              (LM_FLASHCON_BASE + LM_FLASH_FMD_OFFSET)
+#define LM_FLASH_FMC              (LM_FLASHCON_BASE + LM_FLASH_FMC_OFFSET)
+#define LM_FLASH_FCRIS            (LM_FLASHCON_BASE + LM_FLASH_FCRIS_OFFSET)
+#define LM_FLASH_FCIM             (LM_FLASHCON_BASE + LM_FLASH_FCIM_OFFSET)
+#define LM_FLASH_FCMISC           (LM_FLASHCON_BASE + LM_FLASH_FCMISC_OFFSET)
 
 /* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
- * System Control base address of LM3S_SYSCON_BASE
+ * System Control base address of LM_SYSCON_BASE
  */
 
-#define LM3S_FLASH_FMPRE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
-#define LM3S_FLASH_FMPPE            (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
-#define LM3S_FLASH_USECRL           (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
-#define LM3S_FLASH_USERDBG          (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
-#define LM3S_FLASH_USERREG0         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
-#define LM3S_FLASH_USERREG1         (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
-#define LM3S_FLASH_FMPRE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
-#define LM3S_FLASH_FMPRE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
-#define LM3S_FLASH_FMPRE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
-#define LM3S_FLASH_FMPRE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
-#define LM3S_FLASH_FMPPE0           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
-#define LM3S_FLASH_FMPPE1           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
-#define LM3S_FLASH_FMPPE2           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
-#define LM3S_FLASH_FMPPE3           (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
+#define LM_FLASH_FMPRE            (LM_SYSCON_BASE + LM_FLASH_FMPRE_OFFSET)
+#define LM_FLASH_FMPPE            (LM_SYSCON_BASE + LM_FLASH_FMPPE_OFFSET)
+#define LM_FLASH_USECRL           (LM_SYSCON_BASE + LM_FLASH_USECRL_OFFSET)
+#define LM_FLASH_USERDBG          (LM_SYSCON_BASE + LM_FLASH_USERDBG_OFFSET)
+#define LM_FLASH_USERREG0         (LM_SYSCON_BASE + LM_FLASH_USERREG0_OFFSET)
+#define LM_FLASH_USERREG1         (LM_SYSCON_BASE + LM_FLASH_USERREG1_OFFSET)
+#define LM_FLASH_FMPRE0           (LM_SYSCON_BASE + LM_FLASH_FMPRE0_OFFSET)
+#define LM_FLASH_FMPRE1           (LM_SYSCON_BASE + LM_FLASH_FMPRE1_OFFSET)
+#define LM_FLASH_FMPRE2           (LM_SYSCON_BASE + LM_FLASH_FMPRE2_OFFSET)
+#define LM_FLASH_FMPRE3           (LM_SYSCON_BASE + LM_FLASH_FMPRE3_OFFSET)
+#define LM_FLASH_FMPPE0           (LM_SYSCON_BASE + LM_FLASH_FMPPE0_OFFSET)
+#define LM_FLASH_FMPPE1           (LM_SYSCON_BASE + LM_FLASH_FMPPE1_OFFSET)
+#define LM_FLASH_FMPPE2           (LM_SYSCON_BASE + LM_FLASH_FMPPE2_OFFSET)
+#define LM_FLASH_FMPPE3           (LM_SYSCON_BASE + LM_FLASH_FMPPE3_OFFSET)
 
 /* FLASH register bit defitiions ****************************************************/
 /* To be provided */
@@ -125,4 +125,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_gpio.h b/nuttx/arch/arm/src/lm/chip/lm_gpio.h
index 4ca8e8ff9..30b850fca 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_gpio.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_gpio.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -48,337 +48,337 @@
 
 /* GPIO Register Offsets ************************************************************/
 
-#define LM3S_GPIO_DATA_OFFSET         0x000 /* GPIO Data */
-#define LM3S_GPIO_DIR_OFFSET          0x400 /* GPIO Direction */
-#define LM3S_GPIO_IS_OFFSET           0x404 /* GPIO Interrupt Sense */
-#define LM3S_GPIO_IBE_OFFSET          0x408 /* GPIO Interrupt Both Edges */
-#define LM3S_GPIO_IEV_OFFSET          0x40c /* GPIO Interrupt Event */
-#define LM3S_GPIO_IM_OFFSET           0x410 /* GPIO Interrupt Mask */
-#define LM3S_GPIO_RIS_OFFSET          0x414 /* GPIO Raw Interrupt Status */
-#define LM3S_GPIO_MIS_OFFSET          0x418 /* GPIO Masked Interrupt Status */
-#define LM3S_GPIO_ICR_OFFSET          0x41c /* GPIO Interrupt Clear */
-#define LM3S_GPIO_AFSEL_OFFSET        0x420 /* GPIO Alternate Function */
-#define LM3S_GPIO_DR2R_OFFSET         0x500 /* Select GPIO 2-mA Drive Select */
-#define LM3S_GPIO_DR4R_OFFSET         0x504 /* GPIO 4-mA Drive Select */
-#define LM3S_GPIO_DR8R_OFFSET         0x508 /* GPIO 8-mA Drive Select */
-#define LM3S_GPIO_ODR_OFFSET          0x50c /* GPIO Open Drain Select */
-#define LM3S_GPIO_PUR_OFFSET          0x510 /* GPIO Pull-Up Select */
-#define LM3S_GPIO_PDR_OFFSET          0x514 /* GPIO Pull-Down Select */
-#define LM3S_GPIO_SLR_OFFSET          0x518 /* GPIO Slew Rate Control Select */
-#define LM3S_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
-#define LM3S_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
-#define LM3S_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
-#define LM3S_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
-#define LM3S_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
-#define LM3S_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
-#define LM3S_GPIO_PERIPHID7_OFFSET    0xfdc /* GPIO Peripheral Identification 7 */
-#define LM3S_GPIO_PERIPHID0_OFFSET    0xfe0 /* GPIO Peripheral Identification 0 */
-#define LM3S_GPIO_PERIPHID1_OFFSET    0xfe4 /* GPIO Peripheral Identification 1 */
-#define LM3S_GPIO_PERIPHID2_OFFSET    0xfe8 /* GPIO Peripheral Identification 2 */
-#define LM3S_GPIO_PERIPHID3_OFFSET    0xfec /* GPIO Peripheral Identification 3 */
-#define LM3S_GPIO_PCELLID0_OFFSET     0xff0 /* GPIO PrimeCell Identification 0 */
-#define LM3S_GPIO_PCELLID1_OFFSET     0xff4 /* GPIO PrimeCell Identification 1 */
-#define LM3S_GPIO_PCELLID2_OFFSET     0xff8 /* GPIO PrimeCell Identification 2 */
-#define LM3S_GPIO_PCELLID3_OFFSET     0xffc /* GPIO PrimeCell Identification 3*/
+#define LM_GPIO_DATA_OFFSET         0x000 /* GPIO Data */
+#define LM_GPIO_DIR_OFFSET          0x400 /* GPIO Direction */
+#define LM_GPIO_IS_OFFSET           0x404 /* GPIO Interrupt Sense */
+#define LM_GPIO_IBE_OFFSET          0x408 /* GPIO Interrupt Both Edges */
+#define LM_GPIO_IEV_OFFSET          0x40c /* GPIO Interrupt Event */
+#define LM_GPIO_IM_OFFSET           0x410 /* GPIO Interrupt Mask */
+#define LM_GPIO_RIS_OFFSET          0x414 /* GPIO Raw Interrupt Status */
+#define LM_GPIO_MIS_OFFSET          0x418 /* GPIO Masked Interrupt Status */
+#define LM_GPIO_ICR_OFFSET          0x41c /* GPIO Interrupt Clear */
+#define LM_GPIO_AFSEL_OFFSET        0x420 /* GPIO Alternate Function */
+#define LM_GPIO_DR2R_OFFSET         0x500 /* Select GPIO 2-mA Drive Select */
+#define LM_GPIO_DR4R_OFFSET         0x504 /* GPIO 4-mA Drive Select */
+#define LM_GPIO_DR8R_OFFSET         0x508 /* GPIO 8-mA Drive Select */
+#define LM_GPIO_ODR_OFFSET          0x50c /* GPIO Open Drain Select */
+#define LM_GPIO_PUR_OFFSET          0x510 /* GPIO Pull-Up Select */
+#define LM_GPIO_PDR_OFFSET          0x514 /* GPIO Pull-Down Select */
+#define LM_GPIO_SLR_OFFSET          0x518 /* GPIO Slew Rate Control Select */
+#define LM_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
+#define LM_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
+#define LM_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
+#define LM_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
+#define LM_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
+#define LM_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
+#define LM_GPIO_PERIPHID7_OFFSET    0xfdc /* GPIO Peripheral Identification 7 */
+#define LM_GPIO_PERIPHID0_OFFSET    0xfe0 /* GPIO Peripheral Identification 0 */
+#define LM_GPIO_PERIPHID1_OFFSET    0xfe4 /* GPIO Peripheral Identification 1 */
+#define LM_GPIO_PERIPHID2_OFFSET    0xfe8 /* GPIO Peripheral Identification 2 */
+#define LM_GPIO_PERIPHID3_OFFSET    0xfec /* GPIO Peripheral Identification 3 */
+#define LM_GPIO_PCELLID0_OFFSET     0xff0 /* GPIO PrimeCell Identification 0 */
+#define LM_GPIO_PCELLID1_OFFSET     0xff4 /* GPIO PrimeCell Identification 1 */
+#define LM_GPIO_PCELLID2_OFFSET     0xff8 /* GPIO PrimeCell Identification 2 */
+#define LM_GPIO_PCELLID3_OFFSET     0xffc /* GPIO PrimeCell Identification 3*/
 
 /* GPIO Register Addresses **********************************************************/
 
-#define LM3S_GPIOA_DATA               (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOA_DIR                (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOA_IS                 (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOA_IBE                (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOA_IEV                (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOA_IM                 (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOA_RIS                (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOA_MIS                (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOA_ICR                (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOA_AFSEL              (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOA_DR2R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOA_DR4R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOA_DR8R               (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOA_ODR                (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOA_PUR                (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOA_PDR                (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOA_SLR                (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOA_DEN                (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOA_LOCK               (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOA_CR                 (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOA_PERIPHID4          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOA_PERIPHID5          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOA_PERIPHID6          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOA_PERIPHID7          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOA_PERIPHID0          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOA_PERIPHID1          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOA_PERIPHID2          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOA_PERIPHID3          (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOA_PCELLID0           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOA_PCELLID1           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOA_PCELLID2           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOA_PCELLID3           (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOA_DATA               (LM_GPIOA_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOA_DIR                (LM_GPIOA_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOA_IS                 (LM_GPIOA_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOA_IBE                (LM_GPIOA_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOA_IEV                (LM_GPIOA_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOA_IM                 (LM_GPIOA_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOA_RIS                (LM_GPIOA_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOA_MIS                (LM_GPIOA_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOA_ICR                (LM_GPIOA_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOA_AFSEL              (LM_GPIOA_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOA_DR2R               (LM_GPIOA_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOA_DR4R               (LM_GPIOA_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOA_DR8R               (LM_GPIOA_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOA_ODR                (LM_GPIOA_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOA_PUR                (LM_GPIOA_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOA_PDR                (LM_GPIOA_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOA_SLR                (LM_GPIOA_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOA_DEN                (LM_GPIOA_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOA_LOCK               (LM_GPIOA_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOA_CR                 (LM_GPIOA_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOA_PERIPHID4          (LM_GPIOA_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOA_PERIPHID5          (LM_GPIOA_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOA_PERIPHID6          (LM_GPIOA_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOA_PERIPHID7          (LM_GPIOA_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOA_PERIPHID0          (LM_GPIOA_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOA_PERIPHID1          (LM_GPIOA_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOA_PERIPHID2          (LM_GPIOA_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOA_PERIPHID3          (LM_GPIOA_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOA_PCELLID0           (LM_GPIOA_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOA_PCELLID1           (LM_GPIOA_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOA_PCELLID2           (LM_GPIOA_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOA_PCELLID3           (LM_GPIOA_BASE + LM_GPIO_PCELLID3_OFFSET)
 
-#define LM3S_GPIOB_DATA               (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOB_DIR                (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOB_IS                 (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOB_IBE                (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOB_IEV                (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOB_IM                 (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOB_RIS                (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOB_MIS                (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOB_ICR                (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOB_AFSEL              (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOB_DR2R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOB_DR4R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOB_DR8R               (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOB_ODR                (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOB_PUR                (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOB_PDR                (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOB_SLR                (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOB_DEN                (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOB_LOCK               (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOB_CR                 (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOB_PERIPHID4          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOB_PERIPHID5          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOB_PERIPHID6          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOB_PERIPHID7          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOB_PERIPHID0          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOB_PERIPHID1          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOB_PERIPHID2          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOB_PERIPHID3          (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOB_PCELLID0           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOB_PCELLID1           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOB_PCELLID2           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOB_PCELLID3           (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOB_DATA               (LM_GPIOB_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOB_DIR                (LM_GPIOB_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOB_IS                 (LM_GPIOB_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOB_IBE                (LM_GPIOB_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOB_IEV                (LM_GPIOB_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOB_IM                 (LM_GPIOB_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOB_RIS                (LM_GPIOB_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOB_MIS                (LM_GPIOB_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOB_ICR                (LM_GPIOB_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOB_AFSEL              (LM_GPIOB_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOB_DR2R               (LM_GPIOB_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOB_DR4R               (LM_GPIOB_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOB_DR8R               (LM_GPIOB_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOB_ODR                (LM_GPIOB_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOB_PUR                (LM_GPIOB_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOB_PDR                (LM_GPIOB_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOB_SLR                (LM_GPIOB_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOB_DEN                (LM_GPIOB_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOB_LOCK               (LM_GPIOB_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOB_CR                 (LM_GPIOB_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOB_PERIPHID4          (LM_GPIOB_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOB_PERIPHID5          (LM_GPIOB_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOB_PERIPHID6          (LM_GPIOB_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOB_PERIPHID7          (LM_GPIOB_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOB_PERIPHID0          (LM_GPIOB_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOB_PERIPHID1          (LM_GPIOB_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOB_PERIPHID2          (LM_GPIOB_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOB_PERIPHID3          (LM_GPIOB_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOB_PCELLID0           (LM_GPIOB_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOB_PCELLID1           (LM_GPIOB_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOB_PCELLID2           (LM_GPIOB_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOB_PCELLID3           (LM_GPIOB_BASE + LM_GPIO_PCELLID3_OFFSET)
 
-#define LM3S_GPIOC_DATA               (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOC_DIR                (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOC_IS                 (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOC_IBE                (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOC_IEV                (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOC_IM                 (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOC_RIS                (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOC_MIS                (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOC_ICR                (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOC_AFSEL              (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOC_DR2R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOC_DR4R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOC_DR8R               (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOC_ODR                (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOC_PUR                (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOC_PDR                (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOC_SLR                (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOC_DEN                (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOC_LOCK               (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOC_CR                 (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOC_PERIPHID4          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOC_PERIPHID5          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOC_PERIPHID6          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOC_PERIPHID7          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOC_PERIPHID0          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOC_PERIPHID1          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOC_PERIPHID2          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOC_PERIPHID3          (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOC_PCELLID0           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOC_PCELLID1           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOC_PCELLID2           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOC_PCELLID3           (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOC_DATA               (LM_GPIOC_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOC_DIR                (LM_GPIOC_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOC_IS                 (LM_GPIOC_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOC_IBE                (LM_GPIOC_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOC_IEV                (LM_GPIOC_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOC_IM                 (LM_GPIOC_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOC_RIS                (LM_GPIOC_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOC_MIS                (LM_GPIOC_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOC_ICR                (LM_GPIOC_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOC_AFSEL              (LM_GPIOC_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOC_DR2R               (LM_GPIOC_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOC_DR4R               (LM_GPIOC_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOC_DR8R               (LM_GPIOC_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOC_ODR                (LM_GPIOC_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOC_PUR                (LM_GPIOC_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOC_PDR                (LM_GPIOC_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOC_SLR                (LM_GPIOC_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOC_DEN                (LM_GPIOC_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOC_LOCK               (LM_GPIOC_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOC_CR                 (LM_GPIOC_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOC_PERIPHID4          (LM_GPIOC_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOC_PERIPHID5          (LM_GPIOC_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOC_PERIPHID6          (LM_GPIOC_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOC_PERIPHID7          (LM_GPIOC_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOC_PERIPHID0          (LM_GPIOC_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOC_PERIPHID1          (LM_GPIOC_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOC_PERIPHID2          (LM_GPIOC_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOC_PERIPHID3          (LM_GPIOC_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOC_PCELLID0           (LM_GPIOC_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOC_PCELLID1           (LM_GPIOC_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOC_PCELLID2           (LM_GPIOC_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOC_PCELLID3           (LM_GPIOC_BASE + LM_GPIO_PCELLID3_OFFSET)
 
-#define LM3S_GPIOD_DATA               (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOD_DIR                (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOD_IS                 (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOD_IBE                (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOD_IEV                (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOD_IM                 (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOD_RIS                (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOD_MIS                (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOD_ICR                (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOD_AFSEL              (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOD_DR2R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOD_DR4R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOD_DR8R               (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOD_ODR                (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOD_PUR                (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOD_PDR                (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOD_SLR                (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOD_DEN                (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOD_LOCK               (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOD_CR                 (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOD_PERIPHID4          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOD_PERIPHID5          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOD_PERIPHID6          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOD_PERIPHID7          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOD_PERIPHID0          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOD_PERIPHID1          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOD_PERIPHID2          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOD_PERIPHID3          (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOD_PCELLID0           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOD_PCELLID1           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOD_PCELLID2           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOD_PCELLID3           (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOD_DATA               (LM_GPIOD_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOD_DIR                (LM_GPIOD_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOD_IS                 (LM_GPIOD_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOD_IBE                (LM_GPIOD_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOD_IEV                (LM_GPIOD_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOD_IM                 (LM_GPIOD_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOD_RIS                (LM_GPIOD_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOD_MIS                (LM_GPIOD_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOD_ICR                (LM_GPIOD_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOD_AFSEL              (LM_GPIOD_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOD_DR2R               (LM_GPIOD_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOD_DR4R               (LM_GPIOD_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOD_DR8R               (LM_GPIOD_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOD_ODR                (LM_GPIOD_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOD_PUR                (LM_GPIOD_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOD_PDR                (LM_GPIOD_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOD_SLR                (LM_GPIOD_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOD_DEN                (LM_GPIOD_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOD_LOCK               (LM_GPIOD_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOD_CR                 (LM_GPIOD_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOD_PERIPHID4          (LM_GPIOD_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOD_PERIPHID5          (LM_GPIOD_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOD_PERIPHID6          (LM_GPIOD_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOD_PERIPHID7          (LM_GPIOD_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOD_PERIPHID0          (LM_GPIOD_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOD_PERIPHID1          (LM_GPIOD_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOD_PERIPHID2          (LM_GPIOD_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOD_PERIPHID3          (LM_GPIOD_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOD_PCELLID0           (LM_GPIOD_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOD_PCELLID1           (LM_GPIOD_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOD_PCELLID2           (LM_GPIOD_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOD_PCELLID3           (LM_GPIOD_BASE + LM_GPIO_PCELLID3_OFFSET)
 
-#define LM3S_GPIOE_DATA               (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOE_DIR                (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOE_IS                 (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOE_IBE                (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOE_IEV                (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOE_IM                 (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOE_RIS                (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOE_MIS                (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOE_ICR                (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOE_AFSEL              (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOE_DR2R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOE_DR4R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOE_DR8R               (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOE_ODR                (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOE_PUR                (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOE_PDR                (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOE_SLR                (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOE_DEN                (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOE_LOCK               (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOE_CR                 (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOE_PERIPHID4          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOE_PERIPHID5          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOE_PERIPHID6          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOE_PERIPHID7          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOE_PERIPHID0          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOE_PERIPHID1          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOE_PERIPHID2          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOE_PERIPHID3          (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOE_PCELLID0           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOE_PCELLID1           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOE_PCELLID2           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOE_PCELLID3           (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOE_DATA               (LM_GPIOE_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOE_DIR                (LM_GPIOE_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOE_IS                 (LM_GPIOE_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOE_IBE                (LM_GPIOE_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOE_IEV                (LM_GPIOE_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOE_IM                 (LM_GPIOE_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOE_RIS                (LM_GPIOE_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOE_MIS                (LM_GPIOE_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOE_ICR                (LM_GPIOE_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOE_AFSEL              (LM_GPIOE_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOE_DR2R               (LM_GPIOE_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOE_DR4R               (LM_GPIOE_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOE_DR8R               (LM_GPIOE_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOE_ODR                (LM_GPIOE_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOE_PUR                (LM_GPIOE_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOE_PDR                (LM_GPIOE_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOE_SLR                (LM_GPIOE_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOE_DEN                (LM_GPIOE_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOE_LOCK               (LM_GPIOE_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOE_CR                 (LM_GPIOE_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOE_PERIPHID4          (LM_GPIOE_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOE_PERIPHID5          (LM_GPIOE_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOE_PERIPHID6          (LM_GPIOE_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOE_PERIPHID7          (LM_GPIOE_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOE_PERIPHID0          (LM_GPIOE_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOE_PERIPHID1          (LM_GPIOE_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOE_PERIPHID2          (LM_GPIOE_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOE_PERIPHID3          (LM_GPIOE_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOE_PCELLID0           (LM_GPIOE_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOE_PCELLID1           (LM_GPIOE_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOE_PCELLID2           (LM_GPIOE_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOE_PCELLID3           (LM_GPIOE_BASE + LM_GPIO_PCELLID3_OFFSET)
 
-#define LM3S_GPIOF_DATA               (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOF_DIR                (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOF_IS                 (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOF_IBE                (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOF_IEV                (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOF_IM                 (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOF_RIS                (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOF_MIS                (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOF_ICR                (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOF_AFSEL              (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOF_DR2R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOF_DR4R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOF_DR8R               (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOF_ODR                (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOF_PUR                (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOF_PDR                (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOF_SLR                (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOF_DEN                (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOF_LOCK               (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOF_CR                 (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOF_PERIPHID4          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOF_PERIPHID5          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOF_PERIPHID6          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOF_PERIPHID7          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOF_PERIPHID0          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOF_PERIPHID1          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOF_PERIPHID2          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOF_PERIPHID3          (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOF_PCELLID0           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOF_PCELLID1           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOF_PCELLID2           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOF_PCELLID3           (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOF_DATA               (LM_GPIOF_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOF_DIR                (LM_GPIOF_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOF_IS                 (LM_GPIOF_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOF_IBE                (LM_GPIOF_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOF_IEV                (LM_GPIOF_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOF_IM                 (LM_GPIOF_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOF_RIS                (LM_GPIOF_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOF_MIS                (LM_GPIOF_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOF_ICR                (LM_GPIOF_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOF_AFSEL              (LM_GPIOF_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOF_DR2R               (LM_GPIOF_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOF_DR4R               (LM_GPIOF_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOF_DR8R               (LM_GPIOF_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOF_ODR                (LM_GPIOF_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOF_PUR                (LM_GPIOF_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOF_PDR                (LM_GPIOF_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOF_SLR                (LM_GPIOF_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOF_DEN                (LM_GPIOF_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOF_LOCK               (LM_GPIOF_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOF_CR                 (LM_GPIOF_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOF_PERIPHID4          (LM_GPIOF_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOF_PERIPHID5          (LM_GPIOF_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOF_PERIPHID6          (LM_GPIOF_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOF_PERIPHID7          (LM_GPIOF_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOF_PERIPHID0          (LM_GPIOF_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOF_PERIPHID1          (LM_GPIOF_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOF_PERIPHID2          (LM_GPIOF_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOF_PERIPHID3          (LM_GPIOF_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOF_PCELLID0           (LM_GPIOF_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOF_PCELLID1           (LM_GPIOF_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOF_PCELLID2           (LM_GPIOF_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOF_PCELLID3           (LM_GPIOF_BASE + LM_GPIO_PCELLID3_OFFSET)
 
-#define LM3S_GPIOG_DATA               (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOG_DIR                (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOG_IS                 (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOG_IBE                (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOG_IEV                (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOG_IM                 (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOG_RIS                (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOG_MIS                (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOG_ICR                (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOG_AFSEL              (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOG_DR2R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOG_DR4R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOG_DR8R               (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOG_ODR                (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOG_PUR                (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOG_PDR                (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOG_SLR                (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOG_DEN                (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOG_LOCK               (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOG_CR                 (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOG_PERIPHID4          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOG_PERIPHID5          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOG_PERIPHID6          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOG_PERIPHID7          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOG_PERIPHID0          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOG_PERIPHID1          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOG_PERIPHID2          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOG_PERIPHID3          (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOG_PCELLID0           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOG_PCELLID1           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOG_PCELLID2           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOG_PCELLID3           (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOG_DATA               (LM_GPIOG_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOG_DIR                (LM_GPIOG_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOG_IS                 (LM_GPIOG_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOG_IBE                (LM_GPIOG_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOG_IEV                (LM_GPIOG_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOG_IM                 (LM_GPIOG_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOG_RIS                (LM_GPIOG_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOG_MIS                (LM_GPIOG_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOG_ICR                (LM_GPIOG_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOG_AFSEL              (LM_GPIOG_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOG_DR2R               (LM_GPIOG_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOG_DR4R               (LM_GPIOG_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOG_DR8R               (LM_GPIOG_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOG_ODR                (LM_GPIOG_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOG_PUR                (LM_GPIOG_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOG_PDR                (LM_GPIOG_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOG_SLR                (LM_GPIOG_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOG_DEN                (LM_GPIOG_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOG_LOCK               (LM_GPIOG_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOG_CR                 (LM_GPIOG_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOG_PERIPHID4          (LM_GPIOG_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOG_PERIPHID5          (LM_GPIOG_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOG_PERIPHID6          (LM_GPIOG_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOG_PERIPHID7          (LM_GPIOG_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOG_PERIPHID0          (LM_GPIOG_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOG_PERIPHID1          (LM_GPIOG_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOG_PERIPHID2          (LM_GPIOG_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOG_PERIPHID3          (LM_GPIOG_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOG_PCELLID0           (LM_GPIOG_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOG_PCELLID1           (LM_GPIOG_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOG_PCELLID2           (LM_GPIOG_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOG_PCELLID3           (LM_GPIOG_BASE + LM_GPIO_PCELLID3_OFFSET)
 
-#define LM3S_GPIOH_DATA               (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOH_DIR                (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOH_IS                 (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOH_IBE                (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOH_IEV                (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOH_IM                 (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOH_RIS                (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOH_MIS                (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOH_ICR                (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOH_AFSEL              (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOH_DR2R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOH_DR4R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOH_DR8R               (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOH_ODR                (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOH_PUR                (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOH_PDR                (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOH_SLR                (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOH_DEN                (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOH_LOCK               (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOH_CR                 (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOH_PERIPHID4          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOH_PERIPHID5          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOH_PERIPHID6          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOH_PERIPHID7          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOH_PERIPHID0          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOH_PERIPHID1          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOH_PERIPHID2          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOH_PERIPHID3          (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOH_PCELLID0           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOH_PCELLID1           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOH_PCELLID2           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOH_PCELLID3           (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOH_DATA               (LM_GPIOH_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOH_DIR                (LM_GPIOH_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOH_IS                 (LM_GPIOH_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOH_IBE                (LM_GPIOH_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOH_IEV                (LM_GPIOH_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOH_IM                 (LM_GPIOH_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOH_RIS                (LM_GPIOH_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOH_MIS                (LM_GPIOH_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOH_ICR                (LM_GPIOH_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOH_AFSEL              (LM_GPIOH_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOH_DR2R               (LM_GPIOH_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOH_DR4R               (LM_GPIOH_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOH_DR8R               (LM_GPIOH_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOH_ODR                (LM_GPIOH_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOH_PUR                (LM_GPIOH_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOH_PDR                (LM_GPIOH_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOH_SLR                (LM_GPIOH_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOH_DEN                (LM_GPIOH_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOH_LOCK               (LM_GPIOH_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOH_CR                 (LM_GPIOH_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOH_PERIPHID4          (LM_GPIOH_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOH_PERIPHID5          (LM_GPIOH_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOH_PERIPHID6          (LM_GPIOH_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOH_PERIPHID7          (LM_GPIOH_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOH_PERIPHID0          (LM_GPIOH_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOH_PERIPHID1          (LM_GPIOH_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOH_PERIPHID2          (LM_GPIOH_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOH_PERIPHID3          (LM_GPIOH_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOH_PCELLID0           (LM_GPIOH_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOH_PCELLID1           (LM_GPIOH_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOH_PCELLID2           (LM_GPIOH_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOH_PCELLID3           (LM_GPIOH_BASE + LM_GPIO_PCELLID3_OFFSET)
 
-#define LM3S_GPIOJ_DATA               (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET)
-#define LM3S_GPIOJ_DIR                (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET)
-#define LM3S_GPIOJ_IS                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET)
-#define LM3S_GPIOJ_IBE                (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET)
-#define LM3S_GPIOJ_IEV                (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET)
-#define LM3S_GPIOJ_IM                 (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET)
-#define LM3S_GPIOJ_RIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET)
-#define LM3S_GPIOJ_MIS                (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET)
-#define LM3S_GPIOJ_ICR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET)
-#define LM3S_GPIOJ_AFSEL              (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET)
-#define LM3S_GPIOJ_DR2R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET)
-#define LM3S_GPIOJ_DR4R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET)
-#define LM3S_GPIOJ_DR8R               (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET)
-#define LM3S_GPIOJ_ODR                (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET)
-#define LM3S_GPIOJ_PUR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET)
-#define LM3S_GPIOJ_PDR                (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET)
-#define LM3S_GPIOJ_SLR                (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET)
-#define LM3S_GPIOJ_DEN                (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET)
-#define LM3S_GPIOJ_LOCK               (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET)
-#define LM3S_GPIOJ_CR                 (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET)
-#define LM3S_GPIOJ_PERIPHID4          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
-#define LM3S_GPIOJ_PERIPHID5          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
-#define LM3S_GPIOJ_PERIPHID6          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
-#define LM3S_GPIOJ_PERIPHID7          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
-#define LM3S_GPIOJ_PERIPHID0          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
-#define LM3S_GPIOJ_PERIPHID1          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
-#define LM3S_GPIOJ_PERIPHID2          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
-#define LM3S_GPIOJ_PERIPHID3          (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
-#define LM3S_GPIOJ_PCELLID0           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET)
-#define LM3S_GPIOJ_PCELLID1           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET)
-#define LM3S_GPIOJ_PCELLID2           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET)
-#define LM3S_GPIOJ_PCELLID3           (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET)
+#define LM_GPIOJ_DATA               (LM_GPIOJ_BASE + LM_GPIO_DATA_OFFSET)
+#define LM_GPIOJ_DIR                (LM_GPIOJ_BASE + LM_GPIO_DIR_OFFSET)
+#define LM_GPIOJ_IS                 (LM_GPIOJ_BASE + LM_GPIO_IS_OFFSET)
+#define LM_GPIOJ_IBE                (LM_GPIOJ_BASE + LM_GPIO_IBE_OFFSET)
+#define LM_GPIOJ_IEV                (LM_GPIOJ_BASE + LM_GPIO_IEV_OFFSET)
+#define LM_GPIOJ_IM                 (LM_GPIOJ_BASE + LM_GPIO_IM_OFFSET)
+#define LM_GPIOJ_RIS                (LM_GPIOJ_BASE + LM_GPIO_RIS_OFFSET)
+#define LM_GPIOJ_MIS                (LM_GPIOJ_BASE + LM_GPIO_MIS_OFFSET)
+#define LM_GPIOJ_ICR                (LM_GPIOJ_BASE + LM_GPIO_ICR_OFFSET)
+#define LM_GPIOJ_AFSEL              (LM_GPIOJ_BASE + LM_GPIO_AFSEL_OFFSET)
+#define LM_GPIOJ_DR2R               (LM_GPIOJ_BASE + LM_GPIO_DR2R_OFFSET)
+#define LM_GPIOJ_DR4R               (LM_GPIOJ_BASE + LM_GPIO_DR4R_OFFSET)
+#define LM_GPIOJ_DR8R               (LM_GPIOJ_BASE + LM_GPIO_DR8R_OFFSET)
+#define LM_GPIOJ_ODR                (LM_GPIOJ_BASE + LM_GPIO_ODR_OFFSET)
+#define LM_GPIOJ_PUR                (LM_GPIOJ_BASE + LM_GPIO_PUR_OFFSET)
+#define LM_GPIOJ_PDR                (LM_GPIOJ_BASE + LM_GPIO_PDR_OFFSET)
+#define LM_GPIOJ_SLR                (LM_GPIOJ_BASE + LM_GPIO_SLR_OFFSET)
+#define LM_GPIOJ_DEN                (LM_GPIOJ_BASE + LM_GPIO_DEN_OFFSET)
+#define LM_GPIOJ_LOCK               (LM_GPIOJ_BASE + LM_GPIO_LOCK_OFFSET)
+#define LM_GPIOJ_CR                 (LM_GPIOJ_BASE + LM_GPIO_CR_OFFSET)
+#define LM_GPIOJ_PERIPHID4          (LM_GPIOJ_BASE + LM_GPIO_PERIPHID4_OFFSET)
+#define LM_GPIOJ_PERIPHID5          (LM_GPIOJ_BASE + LM_GPIO_PERIPHID5_OFFSET)
+#define LM_GPIOJ_PERIPHID6          (LM_GPIOJ_BASE + LM_GPIO_PERIPHID6_OFFSET)
+#define LM_GPIOJ_PERIPHID7          (LM_GPIOJ_BASE + LM_GPIO_PERIPHID7_OFFSET)
+#define LM_GPIOJ_PERIPHID0          (LM_GPIOJ_BASE + LM_GPIO_PERIPHID0_OFFSET)
+#define LM_GPIOJ_PERIPHID1          (LM_GPIOJ_BASE + LM_GPIO_PERIPHID1_OFFSET)
+#define LM_GPIOJ_PERIPHID2          (LM_GPIOJ_BASE + LM_GPIO_PERIPHID2_OFFSET)
+#define LM_GPIOJ_PERIPHID3          (LM_GPIOJ_BASE + LM_GPIO_PERIPHID3_OFFSET)
+#define LM_GPIOJ_PCELLID0           (LM_GPIOJ_BASE + LM_GPIO_PCELLID0_OFFSET)
+#define LM_GPIOJ_PCELLID1           (LM_GPIOJ_BASE + LM_GPIO_PCELLID1_OFFSET)
+#define LM_GPIOJ_PCELLID2           (LM_GPIOJ_BASE + LM_GPIO_PCELLID2_OFFSET)
+#define LM_GPIOJ_PCELLID3           (LM_GPIOJ_BASE + LM_GPIO_PCELLID3_OFFSET)
 
 /************************************************************************************
  * Public Types
@@ -392,4 +392,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_i2c.h b/nuttx/arch/arm/src/lm/chip/lm_i2c.h
index 919ac1348..88ce31b77 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_i2c.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_i2c.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H
 
 /************************************************************************************
  * Included Files
@@ -50,99 +50,99 @@
 
 /* I2C Master */
 
-#define LM3S_I2CM_SA_OFFSET  0x000 /* I2C Master Slave Address */
-#define LM3S_I2CM_CS_OFFSET  0x004 /* I2C Master Control/Status */
-#define LM3S_I2CM_DR_OFFSET  0x008 /* I2C Master Data */
-#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
-#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
-#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
-#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
-#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
-#define LM3S_I2CM_CR_OFFSET  0x020 /* I2C Master Configuration */
+#define LM_I2CM_SA_OFFSET    0x000 /* I2C Master Slave Address */
+#define LM_I2CM_CS_OFFSET    0x004 /* I2C Master Control/Status */
+#define LM_I2CM_DR_OFFSET    0x008 /* I2C Master Data */
+#define LM_I2CM_TPR_OFFSET   0x00c /* I2C Master Timer Period */
+#define LM_I2CM_IMR_OFFSET   0x010 /* I2C Master Interrupt Mask */
+#define LM_I2CM_RIS_OFFSET   0x014 /* I2C Master Raw Interrupt Status */
+#define LM_I2CM_MIS_OFFSET   0x018 /* I2C Master Masked Interrupt Status */
+#define LM_I2CM_ICR_OFFSET   0x01c /* I2C Master Interrupt Clear */
+#define LM_I2CM_CR_OFFSET    0x020 /* I2C Master Configuration */
 
 /* I2C Slave */
 
-#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
-#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
-#define LM3S_I2CS_DR_OFFSET  0x008 /* I2C Slave Data */
-#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
-#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
-#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
-#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
+#define LM_I2CS_OAR_OFFSET   0x000 /* I2C Slave Own Address */
+#define LM_I2CS_CSR_OFFSET   0x004 /* I2C Slave Control/Status */
+#define LM_I2CS_DR_OFFSET    0x008 /* I2C Slave Data */
+#define LM_I2CS_IMR_OFFSET   0x00c /* I2C Slave Interrupt Mask */
+#define LM_I2CS_RIS_OFFSET   0x010 /* I2C Slave Raw Interrupt Status */
+#define LM_I2CS_MIS_OFFSET   0x014 /* I2C Slave Masked Interrupt Status */
+#define LM_I2CS_ICR_OFFSET   0x018 /* I2C Slave Interrupt Clear */
 
 /* I2C Register Addresses ***********************************************************/
 
-#if LM3S_NI2C > 0
+#if LM_NI2C > 0
 
 /* I2C Master */
 
-#define LM3S_I2CM_BASE(n)    (LM3S_I2CM0_BASE + (n)*0x1000)
-#define LM3S_I2CM_SA(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM_CS(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM_DR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM_TPR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM_IMR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM_RIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM_MIS(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM_ICR(n)     (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM_CR(n)      (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
+#define LM_I2CM_BASE(n)      (LM_I2CM0_BASE + (n)*0x1000)
+#define LM_I2CM_SA(n)        (LM_I2CM_BASE(n) + LM_I2CM_SA_OFFSET)
+#define LM_I2CM_CS(n)        (LM_I2CM_BASE(n) + LM_I2CM_CS_OFFSET)
+#define LM_I2CM_DR(n)        (LM_I2CM_BASE(n) + LM_I2CM_DR_OFFSET)
+#define LM_I2CM_TPR(n)       (LM_I2CM_BASE(n) + LM_I2CM_TPR_OFFSET)
+#define LM_I2CM_IMR(n)       (LM_I2CM_BASE(n) + LM_I2CM_IMR_OFFSET)
+#define LM_I2CM_RIS(n)       (LM_I2CM_BASE(n) + LM_I2CM_RIS_OFFSET)
+#define LM_I2CM_MIS(n)       (LM_I2CM_BASE(n) + LM_I2CM_MIS_OFFSET)
+#define LM_I2CM_ICR(n)       (LM_I2CM_BASE(n) + LM_I2CM_ICR_OFFSET)
+#define LM_I2CM_CR(n)        (LM_I2CM_BASE(n) + LM_I2CM_CR_OFFSET)
 
 /* I2C Slave */
 
-#define LM3S_I2CS_BASE(n)    (LM3S_I2CS0_BASE + (n)*0x1000)
-#define LM3S_I2CS_OAR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS_CSR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS_DR(n)      (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS_IMR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS_RIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS_MIS(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS_ICR(n)     (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
+#define LM_I2CS_BASE(n)      (LM_I2CS0_BASE + (n)*0x1000)
+#define LM_I2CS_OAR(n)       (LM_I2CS_BASE(n) + LM_I2CS_OAR_OFFSET)
+#define LM_I2CS_CSR(n)       (LM_I2CS_BASE(n) + LM_I2CS_CSR_OFFSET)
+#define LM_I2CS_DR(n)        (LM_I2CS_BASE(n) + LM_I2CS_DR_OFFSET)
+#define LM_I2CS_IMR(n)       (LM_I2CS_BASE(n) + LM_I2CS_IMR_OFFSET)
+#define LM_I2CS_RIS(n)       (LM_I2CS_BASE(n) + LM_I2CS_RIS_OFFSET)
+#define LM_I2CS_MIS(n)       (LM_I2CS_BASE(n) + LM_I2CS_MIS_OFFSET)
+#define LM_I2CS_ICR(n)       (LM_I2CS_BASE(n) + LM_I2CS_ICR_OFFSET)
 
 /* I2C0 Master */
 
-#define LM3S_I2CM0_SA        (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM0_CS        (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM0_DR        (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM0_TPR       (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM0_IMR       (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM0_RIS       (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM0_MIS       (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM0_ICR       (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM0_CR        (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
+#define LM_I2CM0_SA          (LM_I2CM0_BASE + LM_I2CM_SA_OFFSET)
+#define LM_I2CM0_CS          (LM_I2CM0_BASE + LM_I2CM_CS_OFFSET)
+#define LM_I2CM0_DR          (LM_I2CM0_BASE + LM_I2CM_DR_OFFSET)
+#define LM_I2CM0_TPR         (LM_I2CM0_BASE + LM_I2CM_TPR_OFFSET)
+#define LM_I2CM0_IMR         (LM_I2CM0_BASE + LM_I2CM_IMR_OFFSET)
+#define LM_I2CM0_RIS         (LM_I2CM0_BASE + LM_I2CM_RIS_OFFSET)
+#define LM_I2CM0_MIS         (LM_I2CM0_BASE + LM_I2CM_MIS_OFFSET)
+#define LM_I2CM0_ICR         (LM_I2CM0_BASE + LM_I2CM_ICR_OFFSET)
+#define LM_I2CM0_CR          (LM_I2CM0_BASE + LM_I2CM_CR_OFFSET)
 
 /* I2C0 Slave */
 
-#define LM3S_I2CS0_OAR       (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS0_CSR       (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS0_DR        (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS0_IMR       (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS0_RIS       (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS0_MIS       (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS0_ICR       (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
+#define LM_I2CS0_OAR         (LM_I2CS0_BASE + LM_I2CS_OAR_OFFSET)
+#define LM_I2CS0_CSR         (LM_I2CS0_BASE + LM_I2CS_CSR_OFFSET)
+#define LM_I2CS0_DR          (LM_I2CS0_BASE + LM_I2CS_DR_OFFSET)
+#define LM_I2CS0_IMR         (LM_I2CS0_BASE + LM_I2CS_IMR_OFFSET)
+#define LM_I2CS0_RIS         (LM_I2CS0_BASE + LM_I2CS_RIS_OFFSET)
+#define LM_I2CS0_MIS         (LM_I2CS0_BASE + LM_I2CS_MIS_OFFSET)
+#define LM_I2CS0_ICR         (LM_I2CS0_BASE + LM_I2CS_ICR_OFFSET)
 
-#if LM3S_NI2C > 1
+#if LM_NI2C > 1
 
 /* I2C1 Master */
 
-#define LM3S_I2CM1_SA        (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
-#define LM3S_I2CM1_CS        (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
-#define LM3S_I2CM1_DR        (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
-#define LM3S_I2CM1_TPR       (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
-#define LM3S_I2CM1_IMR       (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
-#define LM3S_I2CM1_RIS       (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
-#define LM3S_I2CM1_MIS       (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
-#define LM3S_I2CM1_ICR       (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
-#define LM3S_I2CM1_CR        (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
+#define LM_I2CM1_SA          (LM_I2CM1_BASE + LM_I2CM_SA_OFFSET)
+#define LM_I2CM1_CS          (LM_I2CM1_BASE + LM_I2CM_CS_OFFSET)
+#define LM_I2CM1_DR          (LM_I2CM1_BASE + LM_I2CM_DR_OFFSET)
+#define LM_I2CM1_TPR         (LM_I2CM1_BASE + LM_I2CM_TPR_OFFSET)
+#define LM_I2CM1_IMR         (LM_I2CM1_BASE + LM_I2CM_IMR_OFFSET)
+#define LM_I2CM1_RIS         (LM_I2CM1_BASE + LM_I2CM_RIS_OFFSET)
+#define LM_I2CM1_MIS         (LM_I2CM1_BASE + LM_I2CM_MIS_OFFSET)
+#define LM_I2CM1_ICR         (LM_I2CM1_BASE + LM_I2CM_ICR_OFFSET)
+#define LM_I2CM1_CR          (LM_I2CM1_BASE + LM_I2CM_CR_OFFSET)
 
 /* I2C1 Slave */
 
-#define LM3S_I2CS1_OAR       (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
-#define LM3S_I2CS1_CSR       (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
-#define LM3S_I2CS1_DR        (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
-#define LM3S_I2CS1_IMR       (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
-#define LM3S_I2CS1_RIS       (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
-#define LM3S_I2CS1_MIS       (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
-#define LM3S_I2CS1_ICR       (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
+#define LM_I2CS1_OAR         (LM_I2CS1_BASE + LM_I2CS_OAR_OFFSET)
+#define LM_I2CS1_CSR         (LM_I2CS1_BASE + LM_I2CS_CSR_OFFSET)
+#define LM_I2CS1_DR          (LM_I2CS1_BASE + LM_I2CS_DR_OFFSET)
+#define LM_I2CS1_IMR         (LM_I2CS1_BASE + LM_I2CS_IMR_OFFSET)
+#define LM_I2CS1_RIS         (LM_I2CS1_BASE + LM_I2CS_RIS_OFFSET)
+#define LM_I2CS1_MIS         (LM_I2CS1_BASE + LM_I2CS_MIS_OFFSET)
+#define LM_I2CS1_ICR         (LM_I2CS1_BASE + LM_I2CS_ICR_OFFSET)
 
 #endif
 #endif
@@ -244,4 +244,4 @@
  * Public Function Prototypes
  ****************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h
index b8154dd9f..311d6fcdc 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h
@@ -42,7 +42,7 @@
 
 #include <nuttx/config.h>
 
-/* Include the memory map file for the specific Stellaris chip */
+/* Include the pin mapping file for the specific Stellaris chip */
 
 #ifdef CONFIG_ARCH_CHIP_LM3S
 #  include "chip/lm3s_pinmap.h"
diff --git a/nuttx/arch/arm/src/lm/chip/lm_ssi.h b/nuttx/arch/arm/src/lm/chip/lm_ssi.h
index b58aec733..5243bf112 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_ssi.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_ssi.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include <nuttx/config.h>
 #include <sys/types.h>
 
-#if LM3S_NSSI > 0
+#if LM_NSSI > 0
 
 /************************************************************************************
  * Definitions
@@ -51,173 +51,173 @@
 
 /* SSI register offsets *************************************************************/
 
-#define LM3S_SSI_CR0_OFFSET       0x000 /* SSI Control 0 */
-#define LM3S_SSI_CR1_OFFSET       0x004 /* SSI Control 1 */
-#define LM3S_SSI_DR_OFFSET        0x008 /* SSI Data */
-#define LM3S_SSI_SR_OFFSET        0x00c /* SSI Status */
-#define LM3S_SSI_CPSR_OFFSET      0x010 /* SSI Clock Prescale */
-#define LM3S_SSI_IM_OFFSET        0x014 /* SSI Interrupt Mask */
-#define LM3S_SSI_RIS_OFFSET       0x018 /* SSI Raw Interrupt Status */
-#define LM3S_SSI_MIS_OFFSET       0x01c /* SSI Masked Interrupt Status */
-#define LM3S_SSI_ICR_OFFSET       0x020 /* SSI Interrupt Clear */
-#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
-#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
-#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
-#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
-#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
-#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
-#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
-#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
-#define LM3S_SSI_PCELLID0_OFFSET  0xff0 /* SSI PrimeCell Identification 0 */
-#define LM3S_SSI_PCELLID1_OFFSET  0xff4 /* SSI PrimeCell Identification 1 */
-#define LM3S_SSI_PCELLID2_OFFSET  0xff8 /* SSI PrimeCell Identification 2 */
-#define LM3S_SSI_PCELLID3_OFFSET  0xffc /* SSI PrimeCell Identification 3 */
+#define LM_SSI_CR0_OFFSET       0x000 /* SSI Control 0 */
+#define LM_SSI_CR1_OFFSET       0x004 /* SSI Control 1 */
+#define LM_SSI_DR_OFFSET        0x008 /* SSI Data */
+#define LM_SSI_SR_OFFSET        0x00c /* SSI Status */
+#define LM_SSI_CPSR_OFFSET      0x010 /* SSI Clock Prescale */
+#define LM_SSI_IM_OFFSET        0x014 /* SSI Interrupt Mask */
+#define LM_SSI_RIS_OFFSET       0x018 /* SSI Raw Interrupt Status */
+#define LM_SSI_MIS_OFFSET       0x01c /* SSI Masked Interrupt Status */
+#define LM_SSI_ICR_OFFSET       0x020 /* SSI Interrupt Clear */
+#define LM_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
+#define LM_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
+#define LM_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
+#define LM_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
+#define LM_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
+#define LM_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
+#define LM_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
+#define LM_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
+#define LM_SSI_PCELLID0_OFFSET  0xff0 /* SSI PrimeCell Identification 0 */
+#define LM_SSI_PCELLID1_OFFSET  0xff4 /* SSI PrimeCell Identification 1 */
+#define LM_SSI_PCELLID2_OFFSET  0xff8 /* SSI PrimeCell Identification 2 */
+#define LM_SSI_PCELLID3_OFFSET  0xffc /* SSI PrimeCell Identification 3 */
 
 /* SSI register addresses ***********************************************************/
 
-#define LM3S_SSI0_CR0             (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI0_CR1             (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI0_DR              (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI0_SR              (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI0_CPSR            (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI0_IM              (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI0_RIS             (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI0_MIS             (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI0_ICR             (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI0_PERIPHID4       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI0_PERIPHID5       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI0_PERIPHID6       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI0_PERIPHID7       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI0_PERIPHID0       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI0_PERIPHID1       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI0_PERIPHID2       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI0_PERIPHID3       (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI0_PCELLID0        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI0_PCELLID1        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI0_PCELLID2        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI0_PCELLID3        (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
-
-#if LM3S_NSSI > 1
-#define LM3S_SSI1_CR0             (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI1_CR1             (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI1_DR              (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI1_SR              (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI1_CPSR            (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI1_IM              (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI1_RIS             (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI1_MIS             (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI1_ICR             (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI1_PERIPHID4       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI1_PERIPHID5       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI1_PERIPHID6       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI1_PERIPHID7       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI1_PERIPHID0       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI1_PERIPHID1       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI1_PERIPHID2       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI1_PERIPHID3       (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI1_PCELLID0        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI1_PCELLID1        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI1_PCELLID2        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI1_PCELLID3        (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
-
-#define LM3S_SSI_BASE(n)          (LM3S_SSI0_BASE + (n)*0x01000)
-
-#define LM3S_SSI_CR0(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
-#define LM3S_SSI_CR1(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
-#define LM3S_SSI_DR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
-#define LM3S_SSI_SR(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
-#define LM3S_SSI_CPSR(n)          (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
-#define LM3S_SSI_IM(n)            (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
-#define LM3S_SSI_RIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
-#define LM3S_SSI_MIS(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
-#define LM3S_SSI_ICR(n)           (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
-#define LM3S_SSI_PERIPHID4(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
-#define LM3S_SSI_PERIPHID5(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
-#define LM3S_SSI_PERIPHID6(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
-#define LM3S_SSI_PERIPHID7(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
-#define LM3S_SSI_PERIPHID0(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
-#define LM3S_SSI_PERIPHID1(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
-#define LM3S_SSI_PERIPHID2(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
-#define LM3S_SSI_PERIPHID3(n)     (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
-#define LM3S_SSI_PCELLID0(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
-#define LM3S_SSI_PCELLID1(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
-#define LM3S_SSI_PCELLID2(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
-#define LM3S_SSI_PCELLID3(n)      (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
-#endif /* LM3S_NSSI > 1 */
+#define LM_SSI0_CR0             (LM_SSI0_BASE + LM_SSI_CR0_OFFSET)
+#define LM_SSI0_CR1             (LM_SSI0_BASE + LM_SSI_CR1_OFFSET)
+#define LM_SSI0_DR              (LM_SSI0_BASE + LM_SSI_DR_OFFSET)
+#define LM_SSI0_SR              (LM_SSI0_BASE + LM_SSI_SR_OFFSET)
+#define LM_SSI0_CPSR            (LM_SSI0_BASE + LM_SSI_CPSR_OFFSET)
+#define LM_SSI0_IM              (LM_SSI0_BASE + LM_SSI_IM_OFFSET)
+#define LM_SSI0_RIS             (LM_SSI0_BASE + LM_SSI_RIS_OFFSET)
+#define LM_SSI0_MIS             (LM_SSI0_BASE + LM_SSI_MIS_OFFSET)
+#define LM_SSI0_ICR             (LM_SSI0_BASE + LM_SSI_ICR_OFFSET)
+#define LM_SSI0_PERIPHID4       (LM_SSI0_BASE + LM_SSI_PERIPHID4_OFFSET)
+#define LM_SSI0_PERIPHID5       (LM_SSI0_BASE + LM_SSI_PERIPHID5_OFFSET)
+#define LM_SSI0_PERIPHID6       (LM_SSI0_BASE + LM_SSI_PERIPHID6_OFFSET)
+#define LM_SSI0_PERIPHID7       (LM_SSI0_BASE + LM_SSI_PERIPHID7_OFFSET)
+#define LM_SSI0_PERIPHID0       (LM_SSI0_BASE + LM_SSI_PERIPHID0_OFFSET)
+#define LM_SSI0_PERIPHID1       (LM_SSI0_BASE + LM_SSI_PERIPHID1_OFFSET)
+#define LM_SSI0_PERIPHID2       (LM_SSI0_BASE + LM_SSI_PERIPHID2_OFFSET)
+#define LM_SSI0_PERIPHID3       (LM_SSI0_BASE + LM_SSI_PERIPHID3_OFFSET)
+#define LM_SSI0_PCELLID0        (LM_SSI0_BASE + LM_SSI_PCELLID0_OFFSET)
+#define LM_SSI0_PCELLID1        (LM_SSI0_BASE + LM_SSI_PCELLID1_OFFSET)
+#define LM_SSI0_PCELLID2        (LM_SSI0_BASE + LM_SSI_PCELLID2_OFFSET)
+#define LM_SSI0_PCELLID3        (LM_SSI0_BASE + LM_SSI_PCELLID3_OFFSET)
+
+#if LM_NSSI > 1
+#define LM_SSI1_CR0             (LM_SSI1_BASE + LM_SSI_CR0_OFFSET)
+#define LM_SSI1_CR1             (LM_SSI1_BASE + LM_SSI_CR1_OFFSET)
+#define LM_SSI1_DR              (LM_SSI1_BASE + LM_SSI_DR_OFFSET)
+#define LM_SSI1_SR              (LM_SSI1_BASE + LM_SSI_SR_OFFSET)
+#define LM_SSI1_CPSR            (LM_SSI1_BASE + LM_SSI_CPSR_OFFSET)
+#define LM_SSI1_IM              (LM_SSI1_BASE + LM_SSI_IM_OFFSET)
+#define LM_SSI1_RIS             (LM_SSI1_BASE + LM_SSI_RIS_OFFSET)
+#define LM_SSI1_MIS             (LM_SSI1_BASE + LM_SSI_MIS_OFFSET)
+#define LM_SSI1_ICR             (LM_SSI1_BASE + LM_SSI_ICR_OFFSET)
+#define LM_SSI1_PERIPHID4       (LM_SSI1_BASE + LM_SSI_PERIPHID4_OFFSET)
+#define LM_SSI1_PERIPHID5       (LM_SSI1_BASE + LM_SSI_PERIPHID5_OFFSET)
+#define LM_SSI1_PERIPHID6       (LM_SSI1_BASE + LM_SSI_PERIPHID6_OFFSET)
+#define LM_SSI1_PERIPHID7       (LM_SSI1_BASE + LM_SSI_PERIPHID7_OFFSET)
+#define LM_SSI1_PERIPHID0       (LM_SSI1_BASE + LM_SSI_PERIPHID0_OFFSET)
+#define LM_SSI1_PERIPHID1       (LM_SSI1_BASE + LM_SSI_PERIPHID1_OFFSET)
+#define LM_SSI1_PERIPHID2       (LM_SSI1_BASE + LM_SSI_PERIPHID2_OFFSET)
+#define LM_SSI1_PERIPHID3       (LM_SSI1_BASE + LM_SSI_PERIPHID3_OFFSET)
+#define LM_SSI1_PCELLID0        (LM_SSI1_BASE + LM_SSI_PCELLID0_OFFSET)
+#define LM_SSI1_PCELLID1        (LM_SSI1_BASE + LM_SSI_PCELLID1_OFFSET)
+#define LM_SSI1_PCELLID2        (LM_SSI1_BASE + LM_SSI_PCELLID2_OFFSET)
+#define LM_SSI1_PCELLID3        (LM_SSI1_BASE + LM_SSI_PCELLID3_OFFSET)
+
+#define LM_SSI_BASE(n)          (LM_SSI0_BASE + (n)*0x01000)
+
+#define LM_SSI_CR0(n)           (LM_SSI_BASE(n) + LM_SSI_CR0_OFFSET)
+#define LM_SSI_CR1(n)           (LM_SSI_BASE(n) + LM_SSI_CR1_OFFSET)
+#define LM_SSI_DR(n)            (LM_SSI_BASE(n) + LM_SSI_DR_OFFSET)
+#define LM_SSI_SR(n)            (LM_SSI_BASE(n) + LM_SSI_SR_OFFSET)
+#define LM_SSI_CPSR(n)          (LM_SSI_BASE(n) + LM_SSI_CPSR_OFFSET)
+#define LM_SSI_IM(n)            (LM_SSI_BASE(n) + LM_SSI_IM_OFFSET)
+#define LM_SSI_RIS(n)           (LM_SSI_BASE(n) + LM_SSI_RIS_OFFSET)
+#define LM_SSI_MIS(n)           (LM_SSI_BASE(n) + LM_SSI_MIS_OFFSET)
+#define LM_SSI_ICR(n)           (LM_SSI_BASE(n) + LM_SSI_ICR_OFFSET)
+#define LM_SSI_PERIPHID4(n)     (LM_SSI_BASE(n) + LM_SSI_PERIPHID4_OFFSET)
+#define LM_SSI_PERIPHID5(n)     (LM_SSI_BASE(n) + LM_SSI_PERIPHID5_OFFSET)
+#define LM_SSI_PERIPHID6(n)     (LM_SSI_BASE(n) + LM_SSI_PERIPHID6_OFFSET)
+#define LM_SSI_PERIPHID7(n)     (LM_SSI_BASE(n) + LM_SSI_PERIPHID7_OFFSET)
+#define LM_SSI_PERIPHID0(n)     (LM_SSI_BASE(n) + LM_SSI_PERIPHID0_OFFSET)
+#define LM_SSI_PERIPHID1(n)     (LM_SSI_BASE(n) + LM_SSI_PERIPHID1_OFFSET)
+#define LM_SSI_PERIPHID2(n)     (LM_SSI_BASE(n) + LM_SSI_PERIPHID2_OFFSET)
+#define LM_SSI_PERIPHID3(n)     (LM_SSI_BASE(n) + LM_SSI_PERIPHID3_OFFSET)
+#define LM_SSI_PCELLID0(n)      (LM_SSI_BASE(n) + LM_SSI_PCELLID0_OFFSET)
+#define LM_SSI_PCELLID1(n)      (LM_SSI_BASE(n) + LM_SSI_PCELLID1_OFFSET)
+#define LM_SSI_PCELLID2(n)      (LM_SSI_BASE(n) + LM_SSI_PCELLID2_OFFSET)
+#define LM_SSI_PCELLID3(n)      (LM_SSI_BASE(n) + LM_SSI_PCELLID3_OFFSET)
+#endif /* LM_NSSI > 1 */
 
 /* SSI register bit defitiions ******************************************************/
 
 /* SSI Control 0 (SSICR0), offset 0x000 */
 
-#define SSI_CR0_DSS_SHIFT         0         /* Bits 3-0: SSI Data Size Select */
-#define SSI_CR0_DSS_MASK          (0x0f << SSI_CR0_DSS_SHIFT)
-#define   SSI_CR0_DSS(n)          ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
-#define SSI_CR0_FRF_SHIFT         4         /* Bits 5-4: SSI Frame Format Select */
-#define SSI_CR0_FRF_MASK          (3 << SSI_CR0_FRF_SHIFT)
-#define   SSI_CR0_FRF_SPI         (0 << SSI_CR0_FRF_SHIFT)     /* Freescale SPI format */
-#define   SSI_CR0_FRF_SSFF        (1 << SSI_CR0_FRF_SHIFT)     /* TI synchronous serial fram format */
-#define   SSI_CR0_FRF_UWIRE       (2 << SSI_CR0_FRF_SHIFT)     /* MICROWIRE frame format */
-#define SSI_CR0_SPO               (1 << 6)  /* Bit 6:  SSI Serial Clock Polarity */
-#define SSI_CR0_SPH               (1 << 7)  /* Bit 7:  SSI Serial Clock Phase */
-#define SSI_CR0_SCR_SHIFT         8         /* Bits 15-8: SSI Serial Clock Rate */
-#define SSI_CR0_SCR_MASK          (0xff << SSI_CR0_SCR_SHIFT)
+#define SSI_CR0_DSS_SHIFT       0         /* Bits 3-0: SSI Data Size Select */
+#define SSI_CR0_DSS_MASK        (0x0f << SSI_CR0_DSS_SHIFT)
+#define   SSI_CR0_DSS(n)        ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
+#define SSI_CR0_FRF_SHIFT       4         /* Bits 5-4: SSI Frame Format Select */
+#define SSI_CR0_FRF_MASK        (3 << SSI_CR0_FRF_SHIFT)
+#define   SSI_CR0_FRF_SPI       (0 << SSI_CR0_FRF_SHIFT)     /* Freescale SPI format */
+#define   SSI_CR0_FRF_SSFF      (1 << SSI_CR0_FRF_SHIFT)     /* TI synchronous serial fram format */
+#define   SSI_CR0_FRF_UWIRE     (2 << SSI_CR0_FRF_SHIFT)     /* MICROWIRE frame format */
+#define SSI_CR0_SPO             (1 << 6)  /* Bit 6:  SSI Serial Clock Polarity */
+#define SSI_CR0_SPH             (1 << 7)  /* Bit 7:  SSI Serial Clock Phase */
+#define SSI_CR0_SCR_SHIFT       8         /* Bits 15-8: SSI Serial Clock Rate */
+#define SSI_CR0_SCR_MASK        (0xff << SSI_CR0_SCR_SHIFT)
 
 /* SSI Control 1 (SSICR1), offset 0x004 */
 
-#define SSI_CR1_LBM               (1 << 0)  /* Bit 0:  SSI Loopback Mode */
-#define SSI_CR1_SSE               (1 << 1)  /* Bit 1:  SSI Synchronous Serial Port Enable */
-#define SSI_CR1_MS                (1 << 2)  /* Bit 2:  SSI Master/Slave Select slave */
-#define SSI_CR1_SOD               (1 << 3)  /* Bit 3:  SSI Slave Mode Output Disable */
+#define SSI_CR1_LBM             (1 << 0)  /* Bit 0:  SSI Loopback Mode */
+#define SSI_CR1_SSE             (1 << 1)  /* Bit 1:  SSI Synchronous Serial Port Enable */
+#define SSI_CR1_MS              (1 << 2)  /* Bit 2:  SSI Master/Slave Select slave */
+#define SSI_CR1_SOD             (1 << 3)  /* Bit 3:  SSI Slave Mode Output Disable */
 
 /* SSI Data (SSIDR), offset 0x008 */
 
-#define SSI_DR_MASK               0xffff    /* Bits 15-0: SSI data */
+#define SSI_DR_MASK             0xffff    /* Bits 15-0: SSI data */
 
 /* SSI Status (SSISR), offset 0x00c */
 
-#define SSI_SR_TFE                (1 << 0)  /* Bit 0:  SSI Transmit FIFO Empty */
-#define SSI_SR_TNF                (1 << 1)  /* Bit 1:  SSI Transmit FIFO Not Full */
-#define SSI_SR_RNE                (1 << 2)  /* Bit 2:  SSI Receive FIFO Not Empty */
-#define SSI_SR_RFF                (1 << 3)  /* Bit 3:  SSI Receive FIFO Full */
-#define SSI_SR_BSY                (1 << 4)  /* Bit 4:  SSI Busy Bit */
+#define SSI_SR_TFE              (1 << 0)  /* Bit 0:  SSI Transmit FIFO Empty */
+#define SSI_SR_TNF              (1 << 1)  /* Bit 1:  SSI Transmit FIFO Not Full */
+#define SSI_SR_RNE              (1 << 2)  /* Bit 2:  SSI Receive FIFO Not Empty */
+#define SSI_SR_RFF              (1 << 3)  /* Bit 3:  SSI Receive FIFO Full */
+#define SSI_SR_BSY              (1 << 4)  /* Bit 4:  SSI Busy Bit */
 
 /* SSI Clock Prescale (SSICPSR), offset 0x010 */
 
-#define SSI_CPSR_DIV_MASK         0xff      /* Bits 7-0: SSI Clock Prescale Divisor */
+#define SSI_CPSR_DIV_MASK       0xff      /* Bits 7-0: SSI Clock Prescale Divisor */
 
 /* SSI Interrupt Mask (SSIIM), offset 0x014 */
 
-#define SSI_IM_ROR                (1 << 0)  /* Bit 0:  SSI Receive Overrun Interrupt Mask */
-#define SSI_IM_RT                 (1 << 1)  /* Bit 1:  SSI Receive Time-Out Interrupt Mask */
-#define SSI_IM_RX                 (1 << 2)  /* Bit 2:  SSI Receive FIFO Interrupt Mask */
-#define SSI_IM_TX                 (1 << 3)  /* Bit 3:  SSI Transmit FIFO Interrupt Mask */
+#define SSI_IM_ROR              (1 << 0)  /* Bit 0:  SSI Receive Overrun Interrupt Mask */
+#define SSI_IM_RT               (1 << 1)  /* Bit 1:  SSI Receive Time-Out Interrupt Mask */
+#define SSI_IM_RX               (1 << 2)  /* Bit 2:  SSI Receive FIFO Interrupt Mask */
+#define SSI_IM_TX               (1 << 3)  /* Bit 3:  SSI Transmit FIFO Interrupt Mask */
 
 /* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
 
-#define SSI_RIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Raw Interrupt Status */
-#define SSI_RIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Raw Interrupt Status */
-#define SSI_RIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Raw Interrupt Status */
-#define SSI_RIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Raw Interrupt Status */
+#define SSI_RIS_ROR             (1 << 0)  /* Bit 0:  SSI Receive Overrun Raw Interrupt Status */
+#define SSI_RIS_RT              (1 << 1)  /* Bit 1:  SSI Receive Time-Out Raw Interrupt Status */
+#define SSI_RIS_RX              (1 << 2)  /* Bit 2:  SSI Receive FIFO Raw Interrupt Status */
+#define SSI_RIS_TX              (1 << 3)  /* Bit 3:  SSI Transmit FIFO Raw Interrupt Status */
 
 /* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
 
-#define SSI_MIS_ROR               (1 << 0)  /* Bit 0:  SSI Receive Overrun Masked Interrupt Status */
-#define SSI_MIS_RT                (1 << 1)  /* Bit 1:  SSI Receive Time-Out Masked Interrupt Status */
-#define SSI_MIS_RX                (1 << 2)  /* Bit 2:  SSI Receive FIFO Masked Interrupt Status */
-#define SSI_MIS_TX                (1 << 3)  /* Bit 3:  SSI Transmit FIFO Masked Interrupt Status */
+#define SSI_MIS_ROR             (1 << 0)  /* Bit 0:  SSI Receive Overrun Masked Interrupt Status */
+#define SSI_MIS_RT              (1 << 1)  /* Bit 1:  SSI Receive Time-Out Masked Interrupt Status */
+#define SSI_MIS_RX              (1 << 2)  /* Bit 2:  SSI Receive FIFO Masked Interrupt Status */
+#define SSI_MIS_TX              (1 << 3)  /* Bit 3:  SSI Transmit FIFO Masked Interrupt Status */
 
 /* SSI Interrupt Clear (SSIICR), offset 0x020 */
 
-#define SSI_ICR_ROR               (1 << 0)  /* Bit 0: SSI Receive Overrun Interrupt Clear */
-#define SSI_ICR_RT                (1 << 1)  /* Bit 1: SSI Receive Time-Out Interrupt Clear */
+#define SSI_ICR_ROR             (1 << 0)  /* Bit 0: SSI Receive Overrun Interrupt Clear */
+#define SSI_ICR_RT              (1 << 1)  /* Bit 1: SSI Receive Time-Out Interrupt Clear */
 
 /* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
 
-#define SSI_PERIPHID_MASK         0xff      /* Bits 7-0: SSI Peripheral ID n */
+#define SSI_PERIPHID_MASK       0xff      /* Bits 7-0: SSI Peripheral ID n */
 
 /* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
 
-#define SSI_PCELLID_MASK          0xff      /* Bits 7-0: SSI Prime cell ID */
+#define SSI_PCELLID_MASK        0xff      /* Bits 7-0: SSI Prime cell ID */
 
 /************************************************************************************
  * Public Types
@@ -231,5 +231,5 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* LM3S_NSSI > 0 */
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */
+#endif /* LM_NSSI > 0 */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h
index 6ca8ac3ff..444a1271c 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H
 
 /************************************************************************************
  * Included Files
@@ -48,67 +48,67 @@
 
 /* System Control Register Offsets **************************************************/
 
-#define LM3S_SYSCON_DID0_OFFSET       0x000 /* Device Identification 0 */
-#define LM3S_SYSCON_DID1_OFFSET       0x004 /* Device Identification 1 */
-#define LM3S_SYSCON_DC0_OFFSET        0x008 /* Device Capabilities 0 */
-#define LM3S_SYSCON_DC1_OFFSET        0x010 /* Device Capabilities 1 */
-#define LM3S_SYSCON_DC2_OFFSET        0x014 /* Device Capabilities 2 */
-#define LM3S_SYSCON_DC3_OFFSET        0x018 /* Device Capabilities 3 */
-#define LM3S_SYSCON_DC4_OFFSET        0x01c /* Device Capabilities 4 */
-#define LM3S_SYSCON_PBORCTL_OFFSET    0x030 /* Brown-Out Reset Control */
-#define LM3S_SYSCON_LDOPCTL_OFFSET    0x034 /* LDO Power Control */
-#define LM3S_SYSCON_SRCR0_OFFSET      0x040 /* Software Reset Control 0 */
-#define LM3S_SYSCON_SRCR1_OFFSET      0x044 /* Software Reset Control 1 */
-#define LM3S_SYSCON_SRCR2_OFFSET      0x048 /* Software Reset Control 2*/
-#define LM3S_SYSCON_RIS_OFFSET        0x050 /* Raw Interrupt Status */
-#define LM3S_SYSCON_IMC_OFFSET        0x054 /* Interrupt Mask Control */
-#define LM3S_SYSCON_MISC_OFFSET       0x058 /* Masked Interrupt Status and Clear */
-#define LM3S_SYSCON_RESC_OFFSET       0x05c /* Reset Cause */
-#define LM3S_SYSCON_RCC_OFFSET        0x060 /* Run-Mode Clock Configuration */
-#define LM3S_SYSCON_PLLCFG_OFFSET     0x064 /* XTAL to PLL Translation */
-#define LM3S_SYSCON_RCC2_OFFSET       0x070 /* Run-Mode Clock Configuration 2 */
-#define LM3S_SYSCON_RCGC0_OFFSET      0x100 /* Run Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_RCGC1_OFFSET      0x104 /* Run Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_RCGC2_OFFSET      0x108 /* Run Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_SCGC0_OFFSET      0x110 /* Sleep Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_SCGC1_OFFSET      0x114 /* Sleep Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_SCGC2_OFFSET      0x118 /* Sleep Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_DCGC0_OFFSET      0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
-#define LM3S_SYSCON_DCGC1_OFFSET      0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
-#define LM3S_SYSCON_DCGC2_OFFSET      0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
-#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
+#define LM_SYSCON_DID0_OFFSET         0x000 /* Device Identification 0 */
+#define LM_SYSCON_DID1_OFFSET         0x004 /* Device Identification 1 */
+#define LM_SYSCON_DC0_OFFSET          0x008 /* Device Capabilities 0 */
+#define LM_SYSCON_DC1_OFFSET          0x010 /* Device Capabilities 1 */
+#define LM_SYSCON_DC2_OFFSET          0x014 /* Device Capabilities 2 */
+#define LM_SYSCON_DC3_OFFSET          0x018 /* Device Capabilities 3 */
+#define LM_SYSCON_DC4_OFFSET          0x01c /* Device Capabilities 4 */
+#define LM_SYSCON_PBORCTL_OFFSET      0x030 /* Brown-Out Reset Control */
+#define LM_SYSCON_LDOPCTL_OFFSET      0x034 /* LDO Power Control */
+#define LM_SYSCON_SRCR0_OFFSET        0x040 /* Software Reset Control 0 */
+#define LM_SYSCON_SRCR1_OFFSET        0x044 /* Software Reset Control 1 */
+#define LM_SYSCON_SRCR2_OFFSET        0x048 /* Software Reset Control 2*/
+#define LM_SYSCON_RIS_OFFSET          0x050 /* Raw Interrupt Status */
+#define LM_SYSCON_IMC_OFFSET          0x054 /* Interrupt Mask Control */
+#define LM_SYSCON_MISC_OFFSET         0x058 /* Masked Interrupt Status and Clear */
+#define LM_SYSCON_RESC_OFFSET         0x05c /* Reset Cause */
+#define LM_SYSCON_RCC_OFFSET          0x060 /* Run-Mode Clock Configuration */
+#define LM_SYSCON_PLLCFG_OFFSET       0x064 /* XTAL to PLL Translation */
+#define LM_SYSCON_RCC2_OFFSET         0x070 /* Run-Mode Clock Configuration 2 */
+#define LM_SYSCON_RCGC0_OFFSET        0x100 /* Run Mode Clock Gating Control Register 0 */
+#define LM_SYSCON_RCGC1_OFFSET        0x104 /* Run Mode Clock Gating Control Register 1 */
+#define LM_SYSCON_RCGC2_OFFSET        0x108 /* Run Mode Clock Gating Control Register 2 */
+#define LM_SYSCON_SCGC0_OFFSET        0x110 /* Sleep Mode Clock Gating Control Register 0 */
+#define LM_SYSCON_SCGC1_OFFSET        0x114 /* Sleep Mode Clock Gating Control Register 1 */
+#define LM_SYSCON_SCGC2_OFFSET        0x118 /* Sleep Mode Clock Gating Control Register 2 */
+#define LM_SYSCON_DCGC0_OFFSET        0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
+#define LM_SYSCON_DCGC1_OFFSET        0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
+#define LM_SYSCON_DCGC2_OFFSET        0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
+#define LM_SYSCON_DSLPCLKCFG_OFFSET   0x144 /* Deep Sleep Clock Configuration*/
 
 /* System Control Register Addresses ************************************************/
 
-#define LM3S_SYSCON_DID0              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
-#define LM3S_SYSCON_DID1              (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
-#define LM3S_SYSCON_DC0               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
-#define LM3S_SYSCON_DC1               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
-#define LM3S_SYSCON_DC2               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
-#define LM3S_SYSCON_DC3               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
-#define LM3S_SYSCON_DC4               (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
-#define LM3S_SYSCON_PBORCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
-#define LM3S_SYSCON_LDOPCTL           (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
-#define LM3S_SYSCON_SRCR0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
-#define LM3S_SYSCON_SRCR1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
-#define LM3S_SYSCON_SRCR2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
-#define LM3S_SYSCON_RIS               (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
-#define LM3S_SYSCON_IMC               (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
-#define LM3S_SYSCON_MISC              (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
-#define LM3S_SYSCON_RESC              (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
-#define LM3S_SYSCON_RCC               (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
-#define LM3S_SYSCON_PLLCFG            (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
-#define LM3S_SYSCON_RCC2              (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
-#define LM3S_SYSCON_RCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
-#define LM3S_SYSCON_RCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
-#define LM3S_SYSCON_RCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
-#define LM3S_SYSCON_SCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
-#define LM3S_SYSCON_SCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
-#define LM3S_SYSCON_SCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
-#define LM3S_SYSCON_DCGC0             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
-#define LM3S_SYSCON_DCGC1             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
-#define LM3S_SYSCON_DCGC2             (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
-#define LM3S_SYSCON_DSLPCLKCFG        (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
+#define LM_SYSCON_DID0                (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET)
+#define LM_SYSCON_DID1                (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET)
+#define LM_SYSCON_DC0                 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET)
+#define LM_SYSCON_DC1                 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET)
+#define LM_SYSCON_DC2                 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET)
+#define LM_SYSCON_DC3                 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET)
+#define LM_SYSCON_DC4                 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET)
+#define LM_SYSCON_PBORCTL             (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET)
+#define LM_SYSCON_LDOPCTL             (LM_SYSCON_BASE + LM_SYSCON_LDOPCTL_OFFSET)
+#define LM_SYSCON_SRCR0               (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET)
+#define LM_SYSCON_SRCR1               (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET)
+#define LM_SYSCON_SRCR2               (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET)
+#define LM_SYSCON_RIS                 (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET)
+#define LM_SYSCON_IMC                 (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET)
+#define LM_SYSCON_MISC                (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET)
+#define LM_SYSCON_RESC                (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET)
+#define LM_SYSCON_RCC                 (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET)
+#define LM_SYSCON_PLLCFG              (LM_SYSCON_BASE + LM_SYSCON_PLLCFG_OFFSET)
+#define LM_SYSCON_RCC2                (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET)
+#define LM_SYSCON_RCGC0               (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET)
+#define LM_SYSCON_RCGC1               (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET)
+#define LM_SYSCON_RCGC2               (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET)
+#define LM_SYSCON_SCGC0               (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET)
+#define LM_SYSCON_SCGC1               (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET)
+#define LM_SYSCON_SCGC2               (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET)
+#define LM_SYSCON_DCGC0               (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET)
+#define LM_SYSCON_DCGC1               (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET)
+#define LM_SYSCON_DCGC2               (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET)
+#define LM_SYSCON_DSLPCLKCFG          (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET)
 
 /* System Control Register Bit Definitions ******************************************/
 
@@ -492,4 +492,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_timer.h b/nuttx/arch/arm/src/lm/chip/lm_timer.h
index f2824ce1f..5ed68f13a 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_timer.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_timer.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H
 
 /************************************************************************************
  * Included Files
@@ -46,27 +46,27 @@
 
 /* Timer register offsets ***********************************************************/
 
-#define TIMER_GPTMCFG_OFFSET             0x000
-#define TIMER_GPTMTAMR_OFFSET            0x004
-#define TIMER_GPTMCTL_OFFSET             0x00C
-#define TIMER_GPTMIMR_OFFSET             0x018
-#define TIMER_GPTMRIS_OFFSET             0x01C
-#define TIMER_GPTMICR_OFFSET             0x024
-#define TIMER_GPTMTAILR_OFFSET           0x028
-#define TIMER_GPTMTAR_OFFSET             0x048
+#define LM_TIMER_GPTMCFG_OFFSET          0x000
+#define LM_TIMER_GPTMTAMR_OFFSET         0x004
+#define LM_TIMER_GPTMCTL_OFFSET          0x00c
+#define LM_TIMER_GPTMIMR_OFFSET          0x018
+#define LM_TIMER_GPTMRIS_OFFSET          0x01c
+#define LM_TIMER_GPTMICR_OFFSET          0x024
+#define LM_TIMER_GPTMTAILR_OFFSET        0x028
+#define LM_TIMER_GPTMTAR_OFFSET          0x048
 
 /* SSI register addresses ***********************************************************/
 
-#define LM3S_TIMER_BASE(n)               (LM3S_TIMER0_BASE + (n)*0x01000)
+#define LM_TIMER_BASE(n)                 (LM_TIMER0_BASE + (n)*0x01000)
 
-#define LM3S_TIMER_GPTMCFG(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
-#define LM3S_TIMER_GPTMTAMR(n)           (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
-#define LM3S_TIMER_GPTMCTL(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
-#define LM3S_TIMER_GPTMIMR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
-#define LM3S_TIMER_GPTMRIS(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
-#define LM3S_TIMER_GPTMICR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
-#define LM3S_TIMER_GPTMTAILR(n)          (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
-#define LM3S_TIMER_GPTMTAR(n)            (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
+#define LM_TIMER_GPTMCFG(n)              (LM_TIMER_BASE(n) + LM_TIMER_GPTMCFG_OFFSET)
+#define LM_TIMER_GPTMTAMR(n)             (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAMR_OFFSET)
+#define LM_TIMER_GPTMCTL(n)              (LM_TIMER_BASE(n) + LM_TIMER_GPTMCTL_OFFSET)
+#define LM_TIMER_GPTMIMR(n)              (LM_TIMER_BASE(n) + LM_TIMER_GPTMIMR_OFFSET)
+#define LM_TIMER_GPTMRIS(n)              (LM_TIMER_BASE(n) + LM_TIMER_GPTMRIS_OFFSET)
+#define LM_TIMER_GPTMICR(n)              (LM_TIMER_BASE(n) + LM_TIMER_GPTMICR_OFFSET)
+#define LM_TIMER_GPTMTAILR(n)            (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAILR_OFFSET)
+#define LM_TIMER_GPTMTAR(n)              (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAR_OFFSET)
 
 /* SSI register bit defitiions ******************************************************/
 
@@ -122,4 +122,4 @@
 #define TIMER_GPTMICR_TATOCINT_SHIFT     0    /* Bits 0:   GPTM Timer A Time-Out Raw Interrupt Clear*/
 #define TIMER_GPTMICR_TATOCINT_MASK      (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H */
diff --git a/nuttx/arch/arm/src/lm/chip/lm_uart.h b/nuttx/arch/arm/src/lm/chip/lm_uart.h
index 9a03ff063..2ad065294 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_uart.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_uart.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
-#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
+#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_UART_H
+#define __ARCH_ARM_SRC_LM_CHIP_LM_UART_H
 
 /************************************************************************************
  * Included Files
@@ -48,117 +48,117 @@
 
 /* UART register offsets ************************************************************/
 
-#define LM3S_UART_DR_OFFSET        0x000 /* UART Data */
-#define LM3S_UART_RSR_OFFSET       0x004 /* UART Receive Status */
-#define LM3S_UART_ECR_OFFSET       0x004 /* UART Error Clear */
-#define LM3S_UART_FR_OFFSET        0x018 /* UART Flag */
-#define LM3S_UART_ILPR_OFFSET      0x020 /* UART IrDA Low-Power Register */
-#define LM3S_UART_IBRD_OFFSET      0x024 /* UART Integer Baud-Rate Divisor*/
-#define LM3S_UART_FBRD_OFFSET      0x028 /* UART Fractional Baud-Rate Divisor */
-#define LM3S_UART_LCRH_OFFSET      0x02c /* UART Line Control */
-#define LM3S_UART_CTL_OFFSET       0x030 /* UART Control */
-#define LM3S_UART_IFLS_OFFSET      0x034 /* UART Interrupt FIFO Level Select */
-#define LM3S_UART_IM_OFFSET        0x038 /* UART Interrupt Mask */
-#define LM3S_UART_RIS_OFFSET       0x03c /* UART Raw Interrupt Status */
-#define LM3S_UART_MIS_OFFSET       0x040 /* UART Masked Interrupt Status */
-#define LM3S_UART_ICR_OFFSET       0x044 /* UART Interrupt Clear */
-#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
-#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
-#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
-#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
-#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
-#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
-#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
-#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
-#define LM3S_UART_PCELLID0_OFFSET  0xff0 /* UART PrimeCell Identification 0 */
-#define LM3S_UART_PCELLID1_OFFSET  0xff4 /* UART PrimeCell Identification 1 */
-#define LM3S_UART_PCELLID2_OFFSET  0xff8 /* UART PrimeCell Identification 2 */
-#define LM3S_UART_PCELLID3_OFFSET  0xffc /* UART PrimeCell Identification 3 */
+#define LM_UART_DR_OFFSET          0x000 /* UART Data */
+#define LM_UART_RSR_OFFSET         0x004 /* UART Receive Status */
+#define LM_UART_ECR_OFFSET         0x004 /* UART Error Clear */
+#define LM_UART_FR_OFFSET          0x018 /* UART Flag */
+#define LM_UART_ILPR_OFFSET        0x020 /* UART IrDA Low-Power Register */
+#define LM_UART_IBRD_OFFSET        0x024 /* UART Integer Baud-Rate Divisor*/
+#define LM_UART_FBRD_OFFSET        0x028 /* UART Fractional Baud-Rate Divisor */
+#define LM_UART_LCRH_OFFSET        0x02c /* UART Line Control */
+#define LM_UART_CTL_OFFSET         0x030 /* UART Control */
+#define LM_UART_IFLS_OFFSET        0x034 /* UART Interrupt FIFO Level Select */
+#define LM_UART_IM_OFFSET          0x038 /* UART Interrupt Mask */
+#define LM_UART_RIS_OFFSET         0x03c /* UART Raw Interrupt Status */
+#define LM_UART_MIS_OFFSET         0x040 /* UART Masked Interrupt Status */
+#define LM_UART_ICR_OFFSET         0x044 /* UART Interrupt Clear */
+#define LM_UART_PERIPHID4_OFFSET   0xfd0 /* UART Peripheral Identification 4 */
+#define LM_UART_PERIPHID5_OFFSET   0xfd4 /* UART Peripheral Identification 5 */
+#define LM_UART_PERIPHID6_OFFSET   0xfd8 /* UART Peripheral Identification 6 */
+#define LM_UART_PERIPHID7_OFFSET   0xfdc /* UART Peripheral Identification 7 */
+#define LM_UART_PERIPHID0_OFFSET   0xfe0 /* UART Peripheral Identification 0 */
+#define LM_UART_PERIPHID1_OFFSET   0xfe4 /* UART Peripheral Identification 1 */
+#define LM_UART_PERIPHID2_OFFSET   0xfe8 /* UART Peripheral Identification 2 */
+#define LM_UART_PERIPHID3_OFFSET   0xfec /* UART Peripheral Identification 3 */
+#define LM_UART_PCELLID0_OFFSET    0xff0 /* UART PrimeCell Identification 0 */
+#define LM_UART_PCELLID1_OFFSET    0xff4 /* UART PrimeCell Identification 1 */
+#define LM_UART_PCELLID2_OFFSET    0xff8 /* UART PrimeCell Identification 2 */
+#define LM_UART_PCELLID3_OFFSET    0xffc /* UART PrimeCell Identification 3 */
 
 /* UART register addresses **********************************************************/
 
-#define LM3S_UART_BASE(n)          (LM3S_UART0_BASE + (n)*0x01000)
-
-#define LM3S_UART_DR(n)            (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
-#define LM3S_UART_RSR(n)           (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART_ECR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART_FR(n)            (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
-#define LM3S_UART_ILPR(n)          (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART_IBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART_FBRD(n)          (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART_LCRH(n)          (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART_CTL(n)           (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART_IFLS(n)          (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART_IM(n)            (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
-#define LM3S_UART_RIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART_MIS(n)           (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART_ICR(n)           (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART_PERIPHID4(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART_PERIPHID5(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART_PERIPHID6(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART_PERIPHID7(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART_PERIPHID0(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART_PERIPHID1(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART_PERIPHID2(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART_PERIPHID3(n)     (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART_PCELLID0(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART_PCELLID1(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART_PCELLID2(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART_PCELLID3(n)      (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
-
-#define LM3S_UART0_DR              (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
-#define LM3S_UART0_RSR             (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART0_ECR             (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART0_FR              (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
-#define LM3S_UART0_ILPR            (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART0_IBRD            (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART0_FBRD            (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART0_LCRH            (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART0_CTL             (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART0_IFLS            (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART0_IM              (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
-#define LM3S_UART0_RIS             (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART0_MIS             (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART0_ICR             (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART0_PERIPHID4       (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART0_PERIPHID5       (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART0_PERIPHID6       (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART0_PERIPHID7       (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART0_PERIPHID0       (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART0_PERIPHID1       (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART0_PERIPHID2       (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART0_PERIPHID3       (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART0_PCELLID0        (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART0_PCELLID1        (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART0_PCELLID2        (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART0_PCELLID3        (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
-
-#define LM3S_UART1_DR              (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
-#define LM3S_UART1_RSR             (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
-#define LM3S_UART1_ECR             (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
-#define LM3S_UART1_FR              (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
-#define LM3S_UART1_ILPR            (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
-#define LM3S_UART1_IBRD            (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
-#define LM3S_UART1_FBRD            (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
-#define LM3S_UART1_LCRH            (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
-#define LM3S_UART1_CTL             (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
-#define LM3S_UART1_IFLS            (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
-#define LM3S_UART1_IM              (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
-#define LM3S_UART1_RIS             (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
-#define LM3S_UART1_MIS             (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
-#define LM3S_UART1_ICR             (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
-#define LM3S_UART1_PERIPHID4       (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
-#define LM3S_UART1_PERIPHID5       (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
-#define LM3S_UART1_PERIPHID6       (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
-#define LM3S_UART1_PERIPHID7       (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
-#define LM3S_UART1_PERIPHID0       (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
-#define LM3S_UART1_PERIPHID1       (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
-#define LM3S_UART1_PERIPHID2       (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
-#define LM3S_UART1_PERIPHID3       (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
-#define LM3S_UART1_PCELLID0        (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
-#define LM3S_UART1_PCELLID1        (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
-#define LM3S_UART1_PCELLID2        (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
-#define LM3S_UART1_PCELLID3        (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
+#define LM_UART_BASE(n)            (LM_UART0_BASE + (n)*0x01000)
+
+#define LM_UART_DR(n)              (LM_UART_BASE(n) + LM_UART_DR_OFFSET)
+#define LM_UART_RSR(n)             (LM_UART_BASE(n) + LM_UART_RSR_OFFSET)
+#define LM_UART_ECR(n)             (LM_UART_BASE(n) + LM_UART_ECR_OFFSET)
+#define LM_UART_FR(n)              (LM_UART_BASE(n) + LM_UART_FR_OFFSET)
+#define LM_UART_ILPR(n)            (LM_UART_BASE(n) + LM_UART_ILPR_OFFSET)
+#define LM_UART_IBRD(n)            (LM_UART_BASE(n) + LM_UART_IBRD_OFFSET)
+#define LM_UART_FBRD(n)            (LM_UART_BASE(n) + LM_UART_FBRD_OFFSET)
+#define LM_UART_LCRH(n)            (LM_UART_BASE(n) + LM_UART_LCRH_OFFSET)
+#define LM_UART_CTL(n)             (LM_UART_BASE(n) + LM_UART_CTL_OFFSET)
+#define LM_UART_IFLS(n)            (LM_UART_BASE(n) + LM_UART_IFLS_OFFSET)
+#define LM_UART_IM(n)              (LM_UART_BASE(n) + LM_UART_IM_OFFSET)
+#define LM_UART_RIS(n)             (LM_UART_BASE(n) + LM_UART_RIS_OFFSET)
+#define LM_UART_MIS(n)             (LM_UART_BASE(n) + LM_UART_MIS_OFFSET)
+#define LM_UART_ICR(n)             (LM_UART_BASE(n) + LM_UART_ICR_OFFSET)
+#define LM_UART_PERIPHID4(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID4_OFFSET)
+#define LM_UART_PERIPHID5(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID5_OFFSET)
+#define LM_UART_PERIPHID6(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID6_OFFSET)
+#define LM_UART_PERIPHID7(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID7_OFFSET)
+#define LM_UART_PERIPHID0(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID0_OFFSET)
+#define LM_UART_PERIPHID1(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID1_OFFSET)
+#define LM_UART_PERIPHID2(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID2_OFFSET)
+#define LM_UART_PERIPHID3(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID3_OFFSET)
+#define LM_UART_PCELLID0(n)        (LM_UART_BASE(n) + LM_UART_PCELLID0_OFFSET)
+#define LM_UART_PCELLID1(n)        (LM_UART_BASE(n) + LM_UART_PCELLID1_OFFSET)
+#define LM_UART_PCELLID2(n)        (LM_UART_BASE(n) + LM_UART_PCELLID2_OFFSET)
+#define LM_UART_PCELLID3(n)        (LM_UART_BASE(n) + LM_UART_PCELLID3_OFFSET)
+
+#define LM_UART0_DR                (LM_UART0_BASE + LM_UART_TDR_OFFSET)
+#define LM_UART0_RSR               (LM_UART0_BASE + LM_UART_RSR_OFFSET)
+#define LM_UART0_ECR               (LM_UART0_BASE + LM_UART_ECR_OFFSET)
+#define LM_UART0_FR                (LM_UART0_BASE + LM_UART_FR_OFFSET)
+#define LM_UART0_ILPR              (LM_UART0_BASE + LM_UART_ILPR_OFFSET)
+#define LM_UART0_IBRD              (LM_UART0_BASE + LM_UART_IBRD_OFFSET)
+#define LM_UART0_FBRD              (LM_UART0_BASE + LM_UART_FBRD_OFFSET)
+#define LM_UART0_LCRH              (LM_UART0_BASE + LM_UART_LCRH_OFFSET)
+#define LM_UART0_CTL               (LM_UART0_BASE + LM_UART_CTL_OFFSET)
+#define LM_UART0_IFLS              (LM_UART0_BASE + LM_UART_IFLS_OFFSET)
+#define LM_UART0_IM                (LM_UART0_BASE + LM_UART_IM_OFFSET)
+#define LM_UART0_RIS               (LM_UART0_BASE + LM_UART_RIS_OFFSET)
+#define LM_UART0_MIS               (LM_UART0_BASE + LM_UART_MIS_OFFSET)
+#define LM_UART0_ICR               (LM_UART0_BASE + LM_UART_ICR_OFFSET)
+#define LM_UART0_PERIPHID4         (LM_UART0_BASE + LM_UART_PERIPHID4_OFFSET)
+#define LM_UART0_PERIPHID5         (LM_UART0_BASE + LM_UART_PERIPHID5_OFFSET)
+#define LM_UART0_PERIPHID6         (LM_UART0_BASE + LM_UART_PERIPHID6_OFFSET)
+#define LM_UART0_PERIPHID7         (LM_UART0_BASE + LM_UART_PERIPHID7_OFFSET)
+#define LM_UART0_PERIPHID0         (LM_UART0_BASE + LM_UART_PERIPHID0_OFFSET)
+#define LM_UART0_PERIPHID1         (LM_UART0_BASE + LM_UART_PERIPHID1_OFFSET)
+#define LM_UART0_PERIPHID2         (LM_UART0_BASE + LM_UART_PERIPHID2_OFFSET)
+#define LM_UART0_PERIPHID3         (LM_UART0_BASE + LM_UART_PERIPHID3_OFFSET)
+#define LM_UART0_PCELLID0          (LM_UART0_BASE + LM_UART_PCELLID0_OFFSET)
+#define LM_UART0_PCELLID1          (LM_UART0_BASE + LM_UART_PCELLID1_OFFSET)
+#define LM_UART0_PCELLID2          (LM_UART0_BASE + LM_UART_PCELLID2_OFFSET)
+#define LM_UART0_PCELLID3          (LM_UART0_BASE + LM_UART_PCELLID3_OFFSET)
+
+#define LM_UART1_DR                (LM_UART1_BASE + LM_UART_DR_OFFSET)
+#define LM_UART1_RSR               (LM_UART1_BASE + LM_UART_RSR_OFFSET)
+#define LM_UART1_ECR               (LM_UART1_BASE + LM_UART_ECR_OFFSET)
+#define LM_UART1_FR                (LM_UART1_BASE + LM_UART_FR_OFFSET)
+#define LM_UART1_ILPR              (LM_UART1_BASE + LM_UART_ILPR_OFFSET)
+#define LM_UART1_IBRD              (LM_UART1_BASE + LM_UART_IBRD_OFFSET)
+#define LM_UART1_FBRD              (LM_UART1_BASE + LM_UART_FBRD_OFFSET)
+#define LM_UART1_LCRH              (LM_UART1_BASE + LM_UART_LCRH_OFFSET)
+#define LM_UART1_CTL               (LM_UART1_BASE + LM_UART_CTL_OFFSET)
+#define LM_UART1_IFLS              (LM_UART1_BASE + LM_UART_IFLS_OFFSET)
+#define LM_UART1_IM                (LM_UART1_BASE + LM_UART_IM_OFFSET)
+#define LM_UART1_RIS               (LM_UART1_BASE + LM_UART_RIS_OFFSET)
+#define LM_UART1_MIS               (LM_UART1_BASE + LM_UART_MIS_OFFSET)
+#define LM_UART1_ICR               (LM_UART1_BASE + LM_UART_ICR_OFFSET)
+#define LM_UART1_PERIPHID4         (LM_UART1_BASE + LM_UART_PERIPHID4_OFFSET)
+#define LM_UART1_PERIPHID5         (LM_UART1_BASE + LM_UART_PERIPHID5_OFFSET)
+#define LM_UART1_PERIPHID6         (LM_UART1_BASE + LM_UART_PERIPHID6_OFFSET)
+#define LM_UART1_PERIPHID7         (LM_UART1_BASE + LM_UART_PERIPHID7_OFFSET)
+#define LM_UART1_PERIPHID0         (LM_UART1_BASE + LM_UART_PERIPHID0_OFFSET)
+#define LM_UART1_PERIPHID1         (LM_UART1_BASE + LM_UART_PERIPHID1_OFFSET)
+#define LM_UART1_PERIPHID2         (LM_UART1_BASE + LM_UART_PERIPHID2_OFFSET)
+#define LM_UART1_PERIPHID3         (LM_UART1_BASE + LM_UART_PERIPHID3_OFFSET)
+#define LM_UART1_PCELLID0          (LM_UART1_BASE + LM_UART_PCELLID0_OFFSET)
+#define LM_UART1_PCELLID1          (LM_UART1_BASE + LM_UART_PCELLID1_OFFSET)
+#define LM_UART1_PCELLID2          (LM_UART1_BASE + LM_UART_PCELLID2_OFFSET)
+#define LM_UART1_PCELLID3          (LM_UART1_BASE + LM_UART_PCELLID3_OFFSET)
 
 /* UART register bit settings *******************************************************/
 
@@ -275,62 +275,62 @@
 
 /* UART Interrupt Clear (ICR), offset 0x044 */
 
-#define UART_ICR_RXIC             (1 << 4)  /* Bit 4:  Receive Interrupt Clear */
-#define UART_ICR_TXIC             (1 << 5)  /* Bit 5:  Transmit Interrupt Clear */
-#define UART_ICR_RTIC             (1 << 6)  /* Bit 6:  Receive Time-Out Interrupt Clear */
-#define UART_ICR_FEIC             (1 << 7)  /* Bit 7:  Framing Error Interrupt Clear */
-#define UART_ICR_PEIC             (1 << 8)  /* Bit 8:  Parity Error Interrupt Clear */
-#define UART_ICR_BEIC             (1 << 9)  /* Bit 9:  Break Error Interrupt Clear */
-#define UART_ICR_OEIC             (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
+#define UART_ICR_RXIC              (1 << 4)  /* Bit 4:  Receive Interrupt Clear */
+#define UART_ICR_TXIC              (1 << 5)  /* Bit 5:  Transmit Interrupt Clear */
+#define UART_ICR_RTIC              (1 << 6)  /* Bit 6:  Receive Time-Out Interrupt Clear */
+#define UART_ICR_FEIC              (1 << 7)  /* Bit 7:  Framing Error Interrupt Clear */
+#define UART_ICR_PEIC              (1 << 8)  /* Bit 8:  Parity Error Interrupt Clear */
+#define UART_ICR_BEIC              (1 << 9)  /* Bit 9:  Break Error Interrupt Clear */
+#define UART_ICR_OEIC              (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
  */
 
 /* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
 
-#define UART_PERIPHID4_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
+#define UART_PERIPHID4_MASK        (0xff)    /* UART Peripheral ID Register[7:0] */
 
 /* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
 
-#define UART_PERIPHID5_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
+#define UART_PERIPHID5_MASK        (0xff)    /* UART Peripheral ID Register[15:8] */
 
 /* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
 
-#define UART_PERIPHID6_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
+#define UART_PERIPHID6_MASK        (0xff)    /* UART Peripheral ID Register[23:16] */
 
 /* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
 
-#define UART_PERIPHID7_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
+#define UART_PERIPHID7_MASK        (0xff)    /* UART Peripheral ID Register[31:24] */
 
 /* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
 
-#define UART_PERIPHID0_MASK       (0xff)    /* UART Peripheral ID Register[7:0] */
+#define UART_PERIPHID0_MASK        (0xff)    /* UART Peripheral ID Register[7:0] */
 
 /* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
 
-#define UART_PERIPHID1_MASK       (0xff)    /* UART Peripheral ID Register[15:8] */
+#define UART_PERIPHID1_MASK        (0xff)    /* UART Peripheral ID Register[15:8] */
 
 /* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
 
-#define UART_PERIPHID2_MASK       (0xff)    /* UART Peripheral ID Register[23:16] */
+#define UART_PERIPHID2_MASK        (0xff)    /* UART Peripheral ID Register[23:16] */
 
 /* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
 
-#define UART_PERIPHID3_MASK       (0xff)    /* UART Peripheral ID Register[31:24] */
+#define UART_PERIPHID3_MASK        (0xff)    /* UART Peripheral ID Register[31:24] */
 
 /* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
 
-#define UART_CELLID0_MASK         (0xff)    /* UART PrimeCell ID Register[7:0] */
+#define UART_CELLID0_MASK          (0xff)    /* UART PrimeCell ID Register[7:0] */
 
 /* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
 
-#define UART_CELLID1_MASK         (0xff)    /* UART PrimeCell ID Register[15:8] */
+#define UART_CELLID1_MASK          (0xff)    /* UART PrimeCell ID Register[15:8] */
 
 /* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
 
-#define UART_CELLID02MASK         (0xff)    /* UART PrimeCell ID Register[23:16] */
+#define UART_CELLID02MASK          (0xff)    /* UART PrimeCell ID Register[23:16] */
 
 /* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
 
-#define UART_CELLID3_MASK         (0xff)    /* UART PrimeCell ID Register[31:24] */
+#define UART_CELLID3_MASK          (0xff)    /* UART PrimeCell ID Register[31:24] */
 
 /************************************************************************************
  * Public Types
@@ -344,4 +344,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */
+#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_UART_H */
diff --git a/nuttx/arch/arm/src/lm/lm_dumpgpio.c b/nuttx/arch/arm/src/lm/lm_dumpgpio.c
index a3190784b..f71e9c9a0 100644
--- a/nuttx/arch/arm/src/lm/lm_dumpgpio.c
+++ b/nuttx/arch/arm/src/lm/lm_dumpgpio.c
@@ -60,19 +60,19 @@
 
 /* NOTE: this is duplicated in lm_gpio.c */
 
-#ifdef LM3S_GPIOH_BASE
+#ifdef LM_GPIOH_BASE
 static const uint32_t g_gpiobase[8] =
 {
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
+  LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
+  LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, LM_GPIOH_BASE,
 };
 
 static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
 #else
 static const uint32_t g_gpiobase[8] =
 {
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
+  LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
+  LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, 0,
 };
 
 static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
@@ -138,7 +138,7 @@ int lm_dumpgpio(uint32_t pinset, const char *msg)
   /* The following requires exclusive access to the GPIO registers */
 
   flags   = irqsave();
-  rcgc2   = getreg32(LM3S_SYSCON_RCGC2);
+  rcgc2   = getreg32(LM_SYSCON_RCGC2);
   enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
 
   lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
@@ -151,16 +151,16 @@ int lm_dumpgpio(uint32_t pinset, const char *msg)
   if (enabled)
     {
       lldbg("  AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
-            getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET),
-            getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc));
+            getreg32(base + LM_GPIO_AFSEL_OFFSET), getreg32(base + LM_GPIO_DEN_OFFSET),
+            getreg32(base + LM_GPIO_DIR_OFFSET), getreg32(base + LM_GPIO_DATA_OFFSET + 0x3fc));
       lldbg("  IS:    %02x IBE: %02x IEV: %02x IM:  %02x RIS: %08x MIS: %08x\n",
-            getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET),
-            getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET));
+            getreg32(base + LM_GPIO_IEV_OFFSET), getreg32(base + LM_GPIO_IM_OFFSET),
+            getreg32(base + LM_GPIO_RIS_OFFSET), getreg32(base + LM_GPIO_MIS_OFFSET));
       lldbg("  2MA:   %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
-            getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET),
-            getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET),
-            getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET),
-            getreg32(base + LM3S_GPIO_SLR_OFFSET));
+            getreg32(base + LM_GPIO_DR2R_OFFSET), getreg32(base + LM_GPIO_DR4R_OFFSET),
+            getreg32(base + LM_GPIO_DR8R_OFFSET), getreg32(base + LM_GPIO_ODR_OFFSET),
+            getreg32(base + LM_GPIO_PUR_OFFSET), getreg32(base + LM_GPIO_PDR_OFFSET),
+            getreg32(base + LM_GPIO_SLR_OFFSET));
     }
   irqrestore(flags);
   return OK;
diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.c b/nuttx/arch/arm/src/lm/lm_ethernet.c
index 1d8def2e9..861d64d95 100644
--- a/nuttx/arch/arm/src/lm/lm_ethernet.c
+++ b/nuttx/arch/arm/src/lm/lm_ethernet.c
@@ -69,68 +69,68 @@
 /* Half duplex can be forced if CONFIG_LM_ETHHDUPLEX is defined. */
 
 #ifdef CONFIG_LM_ETHHDUPLEX
-#  define LM3S_DUPLEX_SETBITS 0
-#  define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
+#  define LM_DUPLEX_SETBITS 0
+#  define LM_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
 #else 
-#  define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX
-#  define LM3S_DUPLEX_CLRBITS 0
+#  define LM_DUPLEX_SETBITS MAC_TCTL_DUPLEX
+#  define LM_DUPLEX_CLRBITS 0
 #endif
 
 /* Auto CRC generation can be suppressed if CONFIG_LM_ETHNOAUTOCRC is definde */
 
 #ifdef CONFIG_LM_ETHNOAUTOCRC
-#  define LM3S_CRC_SETBITS 0
-#  define LM3S_CRC_CLRBITS MAC_TCTL_CRC
+#  define LM_CRC_SETBITS 0
+#  define LM_CRC_CLRBITS MAC_TCTL_CRC
 #else 
-#  define LM3S_CRC_SETBITS MAC_TCTL_CRC
-#  define LM3S_CRC_CLRBITS 0
+#  define LM_CRC_SETBITS MAC_TCTL_CRC
+#  define LM_CRC_CLRBITS 0
 #endif
 
 /* Tx padding can be suppressed if CONFIG_LM_ETHNOPAD is defined */
 
 #ifdef CONFIG_LM_ETHNOPAD
-#  define LM3S_PADEN_SETBITS 0
-#  define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN
+#  define LM_PADEN_SETBITS 0
+#  define LM_PADEN_CLRBITS MAC_TCTL_PADEN
 #else 
-#  define LM3S_PADEN_SETBITS MAC_TCTL_PADEN
-#  define LM3S_PADEN_CLRBITS 0
+#  define LM_PADEN_SETBITS MAC_TCTL_PADEN
+#  define LM_PADEN_CLRBITS 0
 #endif
 
-#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS)
-#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS)
+#define LM_TCTCL_SETBITS (LM_DUPLEX_SETBITS|LM_CRC_SETBITS|LM_PADEN_SETBITS)
+#define LM_TCTCL_CLRBITS (LM_DUPLEX_CLRBITS|LM_CRC_CLRBITS|LM_PADEN_CLRBITS)
 
 /* Multicast frames can be enabled by defining CONFIG_LM_MULTICAST */
 
 #ifdef CONFIG_LM_MULTICAST
-#  define LM3S_AMUL_SETBITS MAC_RCTL_AMUL
-#  define LM3S_AMUL_CLRBITS 0
+#  define LM_AMUL_SETBITS MAC_RCTL_AMUL
+#  define LM_AMUL_CLRBITS 0
 #else 
-#  define LM3S_AMUL_SETBITS 0
-#  define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL
+#  define LM_AMUL_SETBITS 0
+#  define LM_AMUL_CLRBITS MAC_RCTL_AMUL
 #endif
 
 /* Promiscuous mode can be enabled by defining CONFIG_LM_PROMISCUOUS */
 
 #ifdef CONFIG_LM_PROMISCUOUS
-#  define LM3S_PRMS_SETBITS MAC_RCTL_PRMS
-#  define LM3S_PRMS_CLRBITS 0
+#  define LM_PRMS_SETBITS MAC_RCTL_PRMS
+#  define LM_PRMS_CLRBITS 0
 #else 
-#  define LM3S_PRMS_SETBITS 0
-#  define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS
+#  define LM_PRMS_SETBITS 0
+#  define LM_PRMS_CLRBITS MAC_RCTL_PRMS
 #endif
 
 /* Bad CRC rejection can be enabled by define CONFIG_LM_BADCRC */
 
 #ifdef CONFIG_LM_BADCRC
-#  define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC
-#  define LM3S_BADCRC_CLRBITS 0
+#  define LM_BADCRC_SETBITS MAC_RCTL_BADCRC
+#  define LM_BADCRC_CLRBITS 0
 #else 
-#  define LM3S_BADCRC_SETBITS 0
-#  define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC
+#  define LM_BADCRC_SETBITS 0
+#  define LM_BADCRC_CLRBITS MAC_RCTL_BADCRC
 #endif
 
-#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS)
-#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS)
+#define LM_RCTCL_SETBITS (LM_AMUL_SETBITS|LM_PRMS_SETBITS|LM_BADCRC_SETBITS)
+#define LM_RCTCL_CLRBITS (LM_AMUL_CLRBITS|LM_PRMS_CLRBITS|LM_BADCRC_CLRBITS)
 
 /* CONFIG_LM_DUMPPACKET will dump the contents of each packet to the console. */
 
@@ -142,12 +142,12 @@
 
 /* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
 
-#define LM3S_WDDELAY   (1*CLK_TCK)
-#define LM3S_POLLHSEC  (1*2)
+#define LM_WDDELAY   (1*CLK_TCK)
+#define LM_POLLHSEC  (1*2)
 
 /* TX timeout = 1 minute */
 
-#define LM3S_TXTIMEOUT (60*CLK_TCK)
+#define LM_TXTIMEOUT (60*CLK_TCK)
 
 /* This is a helper pointer for accessing the contents of the Ethernet header */
 
@@ -192,7 +192,7 @@ struct lm_driver_s
    * multiple Ethernet controllers.
    */
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
   uint32_t ld_base;             /* Ethernet controller base address */
   int      ld_irq;              /* Ethernet controller IRQ */
 #endif
@@ -214,7 +214,7 @@ struct lm_driver_s
  * Private Data
  ****************************************************************************/
 
-static struct lm_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS];
+static struct lm_driver_s g_lm3sdev[LM_NETHCONTROLLERS];
 
 /****************************************************************************
  * Private Function Prototypes
@@ -222,7 +222,7 @@ static struct lm_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS];
 
 /* Miscellaneous low level helpers */
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 static uint32_t lm_ethin(struct lm_driver_s *priv, int offset);
 static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value);
 #else
@@ -280,7 +280,7 @@ static int  lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
  *
  ****************************************************************************/
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 static uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
 {
   return getreg32(priv->ld_base + offset);
@@ -288,7 +288,7 @@ static uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
 #else
 static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
 {
-  return getreg32(LM3S_ETHCON_BASE + offset);
+  return getreg32(LM_ETHCON_BASE + offset);
 }
 #endif
 
@@ -308,7 +308,7 @@ static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
  *
  ****************************************************************************/
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value)
 {
   putreg32(value, priv->ld_base + offset);
@@ -316,7 +316,7 @@ static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value)
 #else
 static inline void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value)
 {
-  putreg32(value, LM3S_ETHCON_BASE + offset);
+  putreg32(value, LM_ETHCON_BASE + offset);
 }
 #endif
 
@@ -341,23 +341,23 @@ static void lm_ethreset(struct lm_driver_s *priv)
   irqstate_t flags;
   uint32_t regval;
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 #  error "If multiple interfaces are supported, this function would have to be redesigned"
 #endif
 
   /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
 
   flags   = irqsave();
-  regval  = getreg32(LM3S_SYSCON_RCGC2);
+  regval  = getreg32(LM_SYSCON_RCGC2);
   regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_RCGC2);
+  putreg32(regval, LM_SYSCON_RCGC2);
   nllvdbg("RCGC2: %08x\n", regval);
 
   /* Put the Ethernet controller into the reset state */
 
-  regval = getreg32(LM3S_SYSCON_SRCR2);
+  regval = getreg32(LM_SYSCON_SRCR2);
   regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_SRCR2);
+  putreg32(regval, LM_SYSCON_SRCR2);
 
   /* Wait just a bit.  This is a much longer delay than necessary */
 
@@ -366,7 +366,7 @@ static void lm_ethreset(struct lm_driver_s *priv)
   /* Then take the Ethernet controller out of the reset state */
 
   regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
-  putreg32(regval, LM3S_SYSCON_SRCR2);
+  putreg32(regval, LM_SYSCON_SRCR2);
   nllvdbg("SRCR2: %08x\n", regval);
 
   /* Wait just a bit, again.  If we touch the ethernet too soon, we may busfault. */
@@ -384,14 +384,14 @@ static void lm_ethreset(struct lm_driver_s *priv)
 
   /* Disable all Ethernet controller interrupts */
 
-  regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval = lm_ethin(priv, LM_MAC_IM_OFFSET);
   regval &= ~MAC_IM_ALLINTS;
-  lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_IM_OFFSET, regval);
 
   /* Clear any pending interrupts (shouldn't be any) */
 
-  regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
-  lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
+  regval = lm_ethin(priv, LM_MAC_RIS_OFFSET);
+  lm_ethout(priv, LM_MAC_IACK_OFFSET, regval);
   irqrestore(flags);
 }
 
@@ -416,22 +416,22 @@ static void lm_phywrite(struct lm_driver_s *priv, int regaddr, uint16_t value)
 {
   /* Wait for any MII transactions in progress to complete */
 
-  while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+  while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
 
   /* Set up the data to be written */
 
   DEBUGASSERT(value < MAC_MTXD_MASK);
-  lm_ethout(priv, LM3S_MAC_MTXD_OFFSET, value);
+  lm_ethout(priv, LM_MAC_MTXD_OFFSET, value);
 
   /* Set up the PHY register address and start the write operation */
 
   regaddr <<= MAC_MCTL_REGADR_SHIFT;
   DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
-  lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
+  lm_ethout(priv, LM_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
 
   /* Wait for the write transaction to complete */
 
-  while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+  while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
 }
 #endif
 
@@ -455,21 +455,21 @@ static uint16_t lm_phyread(struct lm_driver_s *priv, int regaddr)
 {
   /* Wait for any MII transactions in progress to complete */
 
-  while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+  while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
 
   /* Set up the PHY register address and start the read operation */
 
   regaddr <<= MAC_MCTL_REGADR_SHIFT;
   DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
-  lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
+  lm_ethout(priv, LM_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
 
   /* Wait for the write transaction to complete */
 
-  while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
+  while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
 
   /* Read and return the PHY data */
 
-  return (uint16_t)(lm_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
+  return (uint16_t)(lm_ethin(priv, LM_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
 }
 
 /****************************************************************************
@@ -499,7 +499,7 @@ static int lm_transmit(struct lm_driver_s *priv)
   /* Verify that the hardware is ready to send another packet */
 
   flags = irqsave();
-  if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+  if ((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
     {
       /* Increment statistics */
 
@@ -520,7 +520,7 @@ static int lm_transmit(struct lm_driver_s *priv)
       regval     = (uint32_t)(pktlen - 14);
       regval    |= ((uint32_t)(*dbuf++) << 16);
       regval    |= ((uint32_t)(*dbuf++) << 24);
-      lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
+      lm_ethout(priv, LM_MAC_DATA_OFFSET, regval);
 
       /* Write all of the whole, 32-bit values in the middle of the packet */
 
@@ -530,7 +530,7 @@ static int lm_transmit(struct lm_driver_s *priv)
            * buffer may be un-aligned.
            */
 
-          lm_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
+          lm_ethout(priv, LM_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
         }
 
       /* Write the last, partial word in the FIFO */
@@ -554,16 +554,16 @@ static int lm_transmit(struct lm_driver_s *priv)
                 regval |= (uint32_t)dbuf[0];
                 break;
             }
-          lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
+          lm_ethout(priv, LM_MAC_DATA_OFFSET, regval);
         }
 
       /* Activate the transmitter */
 
-      lm_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX);
+      lm_ethout(priv, LM_MAC_TR_OFFSET, MAC_TR_NEWTX);
 
       /* Setup the TX timeout watchdog (perhaps restarting the timer) */
 
-      (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm_txtimeout, 1, (uint32_t)priv);
+      (void)wd_start(priv->ld_txtimeout, LM_TXTIMEOUT, lm_txtimeout, 1, (uint32_t)priv);
       ret = OK;
     }
 
@@ -608,7 +608,7 @@ static int lm_uiptxpoll(struct uip_driver_s *dev)
        * packet was successfully handled.
        */
 
-      DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+      DEBUGASSERT((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
       uip_arp_out(&priv->ld_dev);
       ret = lm_transmit(priv);
     }
@@ -645,7 +645,7 @@ static void lm_receive(struct lm_driver_s *priv)
 
   /* Loop while there are incoming packets to be processed */
 
-  while ((lm_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
+  while ((lm_ethin(priv, LM_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
     {
       /* Update statistics */
 
@@ -665,7 +665,7 @@ static void lm_receive(struct lm_driver_s *priv)
        * includes the len/type field (size 2) and the FCS (size 4).
        */
 
-      regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
+      regval = lm_ethin(priv, LM_MAC_DATA_OFFSET);
       pktlen = (int)(regval & 0x0000ffff);
       nllvdbg("Receiving packet, pktlen: %d\n", pktlen);
 
@@ -694,7 +694,7 @@ static void lm_receive(struct lm_driver_s *priv)
 
           while (wordlen--)
             {
-              (void)lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
+              (void)lm_ethin(priv, LM_MAC_DATA_OFFSET);
             }
 
           /* Check for another packet */
@@ -718,7 +718,7 @@ static void lm_receive(struct lm_driver_s *priv)
            * buffer may be un-aligned.
            */
 
-          *(uint32_t*)dbuf = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
+          *(uint32_t*)dbuf = lm_ethin(priv, LM_MAC_DATA_OFFSET);
         }
 
       /* Handle the last, partial word in the FIFO (0-3 bytes) and discard
@@ -731,7 +731,7 @@ static void lm_receive(struct lm_driver_s *priv)
            * bytes of the FCS into the user buffer.
            */
 
-          regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
+          regval = lm_ethin(priv, LM_MAC_DATA_OFFSET);
           switch (bytesleft)
             {
               default:
@@ -834,7 +834,7 @@ static void lm_txdone(struct lm_driver_s *priv)
    * at this point.
    */
 
-  DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+  DEBUGASSERT((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
 
   /* Then poll uIP for new XMIT data */
 
@@ -863,7 +863,7 @@ static int lm_interrupt(int irq, FAR void *context)
   register struct lm_driver_s *priv;
   uint32_t ris;
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 # error "A mechanism to associate and interface with an IRQ is needed"
 #else
   priv = &g_lm3sdev[0];
@@ -871,11 +871,11 @@ static int lm_interrupt(int irq, FAR void *context)
 
   /* Read the raw interrupt status register */
 
-  ris = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
+  ris = lm_ethin(priv, LM_MAC_RIS_OFFSET);
 
   /* Clear all pending interrupts */
 
-  lm_ethout(priv, LM3S_MAC_IACK_OFFSET, ris);
+  lm_ethout(priv, LM_MAC_IACK_OFFSET, ris);
 
   /* Check for errors */
 
@@ -898,7 +898,7 @@ static int lm_interrupt(int irq, FAR void *context)
 
   /* Handle (unmasked) interrupts according to status bit settings */
 
-  ris &= lm_ethin(priv, LM3S_MAC_IM_OFFSET);
+  ris &= lm_ethin(priv, LM_MAC_IM_OFFSET);
 
   /* Is this an Rx interrupt (meaning that a packet has been received)? */
 
@@ -994,15 +994,15 @@ static void lm_polltimer(int argc, uint32_t arg, ...)
    * inaccuracies.
    */
 
-  if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+  if ((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
     {
       /* If so, update TCP timing states and poll uIP for new XMIT data */
 
-      (void)uip_timer(&priv->ld_dev, lm_uiptxpoll, LM3S_POLLHSEC);
+      (void)uip_timer(&priv->ld_dev, lm_uiptxpoll, LM_POLLHSEC);
 
       /* Setup the watchdog poll timer again */
 
-      (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, arg);
+      (void)wd_start(priv->ld_txpoll, LM_WDDELAY, lm_polltimer, 1, arg);
     }
 }
 
@@ -1051,7 +1051,7 @@ static int lm_ifup(struct uip_driver_s *dev)
    */
 
   div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK;
-  lm_ethout(priv, LM3S_MAC_MDV_OFFSET, div);
+  lm_ethout(priv, LM_MAC_MDV_OFFSET, div);
   nllvdbg("MDV:   %08x\n", div);
 
   /* Then configure the Ethernet Controller for normal operation 
@@ -1060,32 +1060,32 @@ static int lm_ifup(struct uip_driver_s *dev)
    * TX Padding Enabled).
    */
 
-  regval  = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET);
-  regval &= ~LM3S_TCTCL_CLRBITS;
-  regval |= LM3S_TCTCL_SETBITS;
-  lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+  regval  = lm_ethin(priv, LM_MAC_TCTL_OFFSET);
+  regval &= ~LM_TCTCL_CLRBITS;
+  regval |= LM_TCTCL_SETBITS;
+  lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
   nllvdbg("TCTL:  %08x\n", regval);
 
   /* Setup the receive control register (Disable multicast frames, disable
    * promiscuous mode, disable bad CRC rejection).
    */
 
-  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
-  regval &= ~LM3S_RCTCL_CLRBITS;
-  regval |= LM3S_RCTCL_SETBITS;
-  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  regval  = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
+  regval &= ~LM_RCTCL_CLRBITS;
+  regval |= LM_RCTCL_SETBITS;
+  lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
   nllvdbg("RCTL:  %08x\n", regval);
 
   /* Setup the time stamp configuration register */
 
-#ifdef LM3S_ETHTS
-  regval = lm_ethin(priv, LM3S_MAC_TS_OFFSET);
+#ifdef LM_ETHTS
+  regval = lm_ethin(priv, LM_MAC_TS_OFFSET);
 #ifdef CONFIG_LM_TIMESTAMP
   regval |= MAC_TS_EN;
 #else
   regval &= ~(MAC_TS_EN);
 #endif
-  lm_ethout(priv, LM3S_MAC_TS_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_TS_OFFSET, regval);
   nllvdbg("TS:    %08x\n", regval);
 #endif
 
@@ -1105,41 +1105,41 @@ static int lm_ifup(struct uip_driver_s *dev)
 
   /* Reset the receive FIFO */
 
-  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval  = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
   regval |= MAC_RCTL_RSTFIFO;
-  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
 
   /* Enable the Ethernet receiver */
 
-  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval  = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
   regval |= MAC_RCTL_RXEN;
-  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
 
   /* Enable the Ethernet transmitter */
 
-  regval  = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET);
+  regval  = lm_ethin(priv, LM_MAC_TCTL_OFFSET);
   regval |= MAC_TCTL_TXEN;
-  lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
 
   /* Reset the receive FIFO (again) */
 
-  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval  = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
   regval |= MAC_RCTL_RSTFIFO;
-  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
 
   /* Enable the Ethernet interrupt */
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
   up_enable_irq(priv->irq);
 #else
-  up_enable_irq(LM3S_IRQ_ETHCON);
+  up_enable_irq(LM_IRQ_ETHCON);
 #endif
 
   /* Enable the Ethernet RX packet receipt interrupt */
 
-  regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval = lm_ethin(priv, LM_MAC_IM_OFFSET);
   regval |= MAC_IM_RXINTM;
-  lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_IM_OFFSET, regval);
 
   /* Program the hardware with it's MAC address (for filtering) */
 
@@ -1147,15 +1147,15 @@ static int lm_ifup(struct uip_driver_s *dev)
            (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 |
            (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 |
            (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0];
-  lm_ethout(priv, LM3S_MAC_IA0_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_IA0_OFFSET, regval);
 
   regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 |
            (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4];
-  lm_ethout(priv, LM3S_MAC_IA1_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_IA1_OFFSET, regval);
 
   /* Set and activate a timer process */
 
-  (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, (uint32_t)priv);
+  (void)wd_start(priv->ld_txpoll, LM_WDDELAY, lm_polltimer, 1, (uint32_t)priv);
 
   priv->ld_bifup = true;
   irqrestore(flags);
@@ -1197,46 +1197,46 @@ static int lm_ifdown(struct uip_driver_s *dev)
 
   /* Disable the Ethernet interrupt */
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
   up_disable_irq(priv->irq);
 #else
-  up_disable_irq(LM3S_IRQ_ETHCON);
+  up_disable_irq(LM_IRQ_ETHCON);
 #endif
 
   /* Disable all Ethernet controller interrupt sources */
 
-  regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
+  regval = lm_ethin(priv, LM_MAC_IM_OFFSET);
   regval &= ~MAC_IM_ALLINTS;
-  lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_IM_OFFSET, regval);
 
   /* Reset the receive FIFO */
 
-  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval  = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
   regval |= MAC_RCTL_RSTFIFO;
-  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
 
   /* Disable the Ethernet receiver */
 
-  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval  = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
   regval &= ~MAC_RCTL_RXEN;
-  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
 
   /* Disable the Ethernet transmitter */
 
-  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval  = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
   regval &= ~MAC_TCTL_TXEN;
-  lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
 
   /* Reset the receive FIFO (again) */
 
-  regval  = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
+  regval  = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
   regval |= MAC_RCTL_RSTFIFO;
-  lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
+  lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
 
   /* Clear any pending interrupts */
 
-  regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
-  lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
+  regval = lm_ethin(priv, LM_MAC_RIS_OFFSET);
+  lm_ethout(priv, LM_MAC_IACK_OFFSET, regval);
 
   /* The interface is now DOWN */
 
@@ -1278,7 +1278,7 @@ static int lm_txavail(struct uip_driver_s *dev)
    */
 
   flags = irqsave();
-  if (priv->ld_bifup && (lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
+  if (priv->ld_bifup && (lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
     {
       /* If the interface is up and we can use the Tx FIFO, then poll uIP
        * for new Tx data
@@ -1371,7 +1371,7 @@ static int lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
  *
  ****************************************************************************/
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 int lm_ethinitialize(int intf)
 #else
 static inline int lm_ethinitialize(int intf)
@@ -1384,12 +1384,12 @@ static inline int lm_ethinitialize(int intf)
 
   ndbg("Setting up eth%d\n", intf);
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 # error "This debug check only works with one interface"
 #else
-  DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
+  DEBUGASSERT((getreg32(LM_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
 #endif
-  DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS);
+  DEBUGASSERT((unsigned)intf < LM_NETHCONTROLLERS);
 
   /* Initialize the driver structure */
 
@@ -1405,7 +1405,7 @@ static inline int lm_ethinitialize(int intf)
 
   /* Create a watchdog for timing polling for and timing of transmisstions */
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 # error "A mechanism to associate base address an IRQ with an interface is needed"
   priv->ld_base          = ??;          /* Ethernet controller base address */
   priv->ld_irq           = ??;          /* Ethernet controller IRQ number */
@@ -1432,10 +1432,10 @@ static inline int lm_ethinitialize(int intf)
 
   /* Attach the IRQ to the driver */
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
   ret = irq_attach(priv->irq, lm_interrupt);
 #else
-  ret = irq_attach(LM3S_IRQ_ETHCON, lm_interrupt);
+  ret = irq_attach(LM_IRQ_ETHCON, lm_interrupt);
 #endif
   if (ret != 0)
     {
@@ -1461,7 +1461,7 @@ static inline int lm_ethinitialize(int intf)
  *
  ************************************************************************************/
 
-#if LM3S_NETHCONTROLLERS == 1
+#if LM_NETHCONTROLLERS == 1
 void up_netinitialize(void)
 {
   (void)lm_ethinitialize(0);
diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.h b/nuttx/arch/arm/src/lm/lm_ethernet.h
index e71e9d077..e3cc65067 100644
--- a/nuttx/arch/arm/src/lm/lm_ethernet.h
+++ b/nuttx/arch/arm/src/lm/lm_ethernet.h
@@ -44,7 +44,7 @@
 
 #include "chip.h"
 
-#if LM3S_NETHCONTROLLERS > 1
+#if LM_NETHCONTROLLERS > 1
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -77,7 +77,7 @@ extern "C"
  * Function: lm_ethinitialize
  *
  * Description:
- *   Initialize the Ethernet driver for one interface.  If the LM3S chip
+ *   Initialize the Ethernet driver for one interface.  If the Stellaris chip
  *   supports multiple Ethernet controllers, then bould specific logic
  *   must implement up_netinitialize() and call this function to initialize
  *   the desiresed interfaces.
@@ -99,5 +99,5 @@ int lm_ethinitialize(int intf);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* LM3S_NETHCONTROLLERS > 1 */
+#endif /* LM_NETHCONTROLLERS > 1 */
 #endif /* __ARCH_ARM_SRC_LM_LM_ETHERNET_H */
diff --git a/nuttx/arch/arm/src/lm/lm_gpio.c b/nuttx/arch/arm/src/lm/lm_gpio.c
index 499bf07a2..be851e67c 100644
--- a/nuttx/arch/arm/src/lm/lm_gpio.c
+++ b/nuttx/arch/arm/src/lm/lm_gpio.c
@@ -140,23 +140,23 @@ static const struct gpio_func_s g_funcbits[] =
   {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
 };
 
-static const uint32_t g_gpiobase[LM3S_NPORTS] =
+static const uint32_t g_gpiobase[LM_NPORTS] =
 {
-  /* All support LM3S parts have at least 7 ports, GPIOA-G */
+  /* All support Stellaris parts have at least 7 ports, GPIOA-G */
 
-  LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
-  LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE,
+  LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
+  LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE,
 
   /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
 
-#if LM3S_NPORTS > 7
-  LM3S_GPIOH_BASE,
+#if LM_NPORTS > 7
+  LM_GPIOH_BASE,
 #endif
 
   /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
 
-#if LM3S_NPORTS > 8
-  LM3S_GPIOJ_BASE,
+#if LM_NPORTS > 8
+  LM_GPIOJ_BASE,
 #endif
 };
 
@@ -180,7 +180,7 @@ static const uint32_t g_gpiobase[LM3S_NPORTS] =
 static uint32_t lm_gpiobaseaddress(unsigned int port)
 {
   uint32_t gpiobase = 0;
-  if (port < LM3S_NPORTS)
+  if (port < LM_NPORTS)
     {
       gpiobase = g_gpiobase[port];
     }
@@ -215,10 +215,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
   setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
   clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
 
-  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
+  regval = getreg32(base + LM_GPIO_ODR_OFFSET);
   regval &= ~clrbit;
   regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
+  putreg32(regval, base + LM_GPIO_ODR_OFFSET);
 
   /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
    * register. When a bit is set to 1, it enables a weak pull-up resistor on the
@@ -231,10 +231,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
 
   if (setbit || clrbit)
     {
-      regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
+      regval = getreg32(base + LM_GPIO_PUR_OFFSET);
       regval &= ~clrbit;
       regval |= setbit;
-      putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
+      putreg32(regval, base + LM_GPIO_PUR_OFFSET);
     }
 
   /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
@@ -248,10 +248,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
 
   if (setbit || clrbit)
     {
-      regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
+      regval = getreg32(base + LM_GPIO_PDR_OFFSET);
       regval &= ~clrbit;
       regval |= setbit;
-      putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
+      putreg32(regval, base + LM_GPIO_PDR_OFFSET);
     }
 
   /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
@@ -266,10 +266,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
   setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
   clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
 
-  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
+  regval = getreg32(base + LM_GPIO_DEN_OFFSET);
   regval &= ~clrbit;
   regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
+  putreg32(regval, base + LM_GPIO_DEN_OFFSET);
 
   /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
    * direction register. Bits set to 1 in the GPIODIR register configure
@@ -281,10 +281,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
   setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
   clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
 
-  regval = getreg32(base + LM3S_GPIO_DIR_OFFSET);
+  regval = getreg32(base + LM_GPIO_DIR_OFFSET);
   regval &= ~clrbit;
   regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_DIR_OFFSET);
+  putreg32(regval, base + LM_GPIO_DIR_OFFSET);
 
   /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
    * control select register. Writing a 1 to any bit in this register selects
@@ -298,10 +298,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
   setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
   clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
 
-  regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET);
+  regval = getreg32(base + LM_GPIO_AFSEL_OFFSET);
   regval &= ~clrbit;
   regval |= setbit;
-  putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET);
+  putreg32(regval, base + LM_GPIO_AFSEL_OFFSET);
 }
 
 /****************************************************************************
@@ -336,7 +336,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
            * DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
            */
 
-          regoffset = LM3S_GPIO_DR2R_OFFSET;
+          regoffset = LM_GPIO_DR2R_OFFSET;
         }
         break;
 
@@ -349,7 +349,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
            * in the GPIO DR8R register are automatically cleared by hardware."
            */
 
-          regoffset = LM3S_GPIO_DR4R_OFFSET;
+          regoffset = LM_GPIO_DR4R_OFFSET;
         }
         break;
 
@@ -374,7 +374,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
            * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
            */
 
-          regoffset = LM3S_GPIO_DR8R_OFFSET;
+          regoffset = LM_GPIO_DR8R_OFFSET;
         }
         break;
     }
@@ -385,10 +385,10 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
   regval |= pin;
   putreg32(regval, base + regoffset);
 
-  regval  = getreg32(base + LM3S_GPIO_SLR_OFFSET);
+  regval  = getreg32(base + LM_GPIO_SLR_OFFSET);
   regval &= slrclr;
   regval |= slrset;
-  putreg32(regval, base + LM3S_GPIO_SLR_OFFSET);
+  putreg32(regval, base + LM_GPIO_SLR_OFFSET);
 }
 
 /****************************************************************************
@@ -503,10 +503,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
    */
 
 #if 0 /* always overwritten by lm_gpiofunc */
-  regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
+  regval = getreg32(base + LM_GPIO_ODR_OFFSET);
   regval &= ~odrclr;
   regval |= odrset;
-  putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
+  putreg32(regval, base + LM_GPIO_ODR_OFFSET);
 #endif
 
   /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
@@ -515,10 +515,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
    * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
    */
 
-  regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
+  regval = getreg32(base + LM_GPIO_PUR_OFFSET);
   regval &= ~purclr;
   regval |= purset;
-  putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
+  putreg32(regval, base + LM_GPIO_PUR_OFFSET);
 
   /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
    * register. When a bit is set to 1, it enables a weak pull-down resistor on the
@@ -526,10 +526,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
    * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
    */
 
-  regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
+  regval = getreg32(base + LM_GPIO_PDR_OFFSET);
   regval &= ~pdrclr;
   regval |= pdrset;
-  putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
+  putreg32(regval, base + LM_GPIO_PDR_OFFSET);
 
   /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
    * register. By default, with the exception of the GPIO signals used for JTAG/SWD
@@ -541,10 +541,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
    */
 
 #if 0 /* always overwritten by lm_gpiofunc */
-  regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
+  regval = getreg32(base + LM_GPIO_DEN_OFFSET);
   regval &= ~denclr;
   regval |= denset;
-  putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
+  putreg32(regval, base + LM_GPIO_DEN_OFFSET);
 #endif
 }
 
@@ -589,18 +589,18 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
    * on that pin. All bits are cleared by a reset."
    */
 
-  regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+  regval  = getreg32(base + LM_GPIO_IM_OFFSET);
   regval &= ~pin;
-  putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+  putreg32(regval, base + LM_GPIO_IM_OFFSET);
 
   /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
    * in this register clears the corresponding interrupt edge detection logic
    * register. Writing a 0 has no effect."
    */
 
-  regval  = getreg32(base + LM3S_GPIO_ICR_OFFSET);
+  regval  = getreg32(base + LM_GPIO_ICR_OFFSET);
   regval |= pin;
-  putreg32(regval, base + LM3S_GPIO_ICR_OFFSET);
+  putreg32(regval, base + LM_GPIO_ICR_OFFSET);
 
   /* Assume rising edge */
 
@@ -656,10 +656,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
    * by a reset.
    */
 
-  regval  = getreg32(base + LM3S_GPIO_IS_OFFSET);
+  regval  = getreg32(base + LM_GPIO_IS_OFFSET);
   regval &= isclr;
   regval |= isset;
-  putreg32(regval, base + LM3S_GPIO_IS_OFFSET);
+  putreg32(regval, base + LM_GPIO_IS_OFFSET);
 
   /* "The GPIO IBE register is the interrupt both-edges register. When the
    * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
@@ -670,10 +670,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
    * are cleared by a reset.
    */
 
-  regval  = getreg32(base + LM3S_GPIO_IBE_OFFSET);
+  regval  = getreg32(base + LM_GPIO_IBE_OFFSET);
   regval &= ibeclr;
   regval |= ibeset;
-  putreg32(regval, base + LM3S_GPIO_IBE_OFFSET);
+  putreg32(regval, base + LM_GPIO_IBE_OFFSET);
 
   /* "The GPIOIEV register is the interrupt event register. Bits set to
    * High in GPIO IEV configure the corresponding pin to detect rising edges
@@ -683,10 +683,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
    * value in GPIOIS. All bits are cleared by a reset.
    */
 
-  regval  = getreg32(base + LM3S_GPIO_IEV_OFFSET);
+  regval  = getreg32(base + LM_GPIO_IEV_OFFSET);
   regval &= iveclr;
   regval |= iveset;
-  putreg32(regval, base + LM3S_GPIO_IEV_OFFSET);
+  putreg32(regval, base + LM_GPIO_IEV_OFFSET);
 }
 
 /****************************************************************************
@@ -734,9 +734,9 @@ int lm_configgpio(uint32_t cfgset)
    * in the RCGC2 register."
    */
 
-  regval = getreg32(LM3S_SYSCON_RCGC2);
+  regval = getreg32(LM_SYSCON_RCGC2);
   regval |= SYSCON_RCGC2_GPIO(port);
-  putreg32(regval, LM3S_SYSCON_RCGC2);
+  putreg32(regval, LM_SYSCON_RCGC2);
 
   /* First, set the port to digital input.  This is the safest state in which
    * to perform reconfiguration.
@@ -810,7 +810,7 @@ void lm_gpiowrite(uint32_t pinset, bool value)
    * "... All bits are cleared by a reset."
    */
 
-  putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
+  putreg32((uint32_t)value << pinno, base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
 }
 
 /****************************************************************************
@@ -849,6 +849,6 @@ bool lm_gpioread(uint32_t pinset, bool value)
    *  are cleared by a reset."
    */
 
-  return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
+  return (getreg32(base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
 }
 
diff --git a/nuttx/arch/arm/src/lm/lm_gpioirq.c b/nuttx/arch/arm/src/lm/lm_gpioirq.c
index f77f878de..e8423f4c0 100644
--- a/nuttx/arch/arm/src/lm/lm_gpioirq.c
+++ b/nuttx/arch/arm/src/lm/lm_gpioirq.c
@@ -73,38 +73,38 @@ static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
 static const uint32_t g_gpiobase[] =
 {
 #ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
-   LM3S_GPIOA_BASE,
+   LM_GPIOA_BASE,
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
-  LM3S_GPIOB_BASE,
+  LM_GPIOB_BASE,
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
-  LM3S_GPIOC_BASE,
+  LM_GPIOC_BASE,
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
-  LM3S_GPIOD_BASE,
+  LM_GPIOD_BASE,
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
-  LM3S_GPIOE_BASE,
+  LM_GPIOE_BASE,
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
-  LM3S_GPIOF_BASE,
+  LM_GPIOF_BASE,
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
-  LM3S_GPIOG_BASE,
+  LM_GPIOG_BASE,
 #endif
 
-  /* NOTE: Not all LM3S architectures support GPIOs above GPIOG.  If the chip
-   * does not support these higher ports, then they must be disabled in the
-   * configuration.  Otherwise, the following will likely cause compilation
+  /* NOTE: Not all Stellaris architectures support GPIOs above GPIOG.  If the
+   * chip does not support these higher ports, then they must be disabled in
+   * the configuration.  Otherwise, the following will likely cause compilation
    * errors!
    */
 
 #ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
-  LM3S_GPIOH_BASE,
+  LM_GPIOH_BASE,
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
-  LM3S_GPIOJ_BASE,
+  LM_GPIOJ_BASE,
 #endif
 };
 
@@ -161,7 +161,7 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
    * either no interrupt has been generated, or the interrupt is masked."
    */
 
-  mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff;
+  mis = getreg32(regbase + LM_GPIO_MIS_OFFSET) & 0xff;
 
   /* Clear all GPIO interrupts that we are going to process.  "The GPIO ICR
    * register is the interrupt clear register. Writing a 1 to a bit in this
@@ -169,7 +169,7 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
    * Writing a 0 has no effect."
    */
 
-  putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET);
+  putreg32(mis, regbase + LM_GPIO_ICR_OFFSET);
 
   /* Now process each IRQ pending in the MIS */
 
@@ -187,63 +187,63 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
 #ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
 static int lm_gpioahandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context);
+  return lm_gpiohandler(LM_GPIOA_BASE, LM_IRQ_GPIOA_0, context);
 }
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
 static int lm_gpiobhandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context);
+  return lm_gpiohandler(LM_GPIOB_BASE, LM_IRQ_GPIOB_0, context);
 }
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
 static int lm_gpiochandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context);
+  return lm_gpiohandler(LM_GPIOC_BASE, LM_IRQ_GPIOC_0, context);
 }
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
 static int lm_gpiodhandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context);
+  return lm_gpiohandler(LM_GPIOD_BASE, LM_IRQ_GPIOD_0, context);
 }
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
 static int lm_gpioehandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context);
+  return lm_gpiohandler(LM_GPIOE_BASE, LM_IRQ_GPIOE_0, context);
 }
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
 static int lm_gpiofhandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context);
+  return lm_gpiohandler(LM_GPIOF_BASE, LM_IRQ_GPIOF_0, context);
 }
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
 static int lm_gpioghandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context);
+  return lm_gpiohandler(LM_GPIOG_BASE, LM_IRQ_GPIOG_0, context);
 }
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
 static int lm_gpiohhandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
+  return lm_gpiohandler(LM_GPIOH_BASE, LM_IRQ_GPIOH_0, context);
 }
 #endif
 
 #ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
 static int lm_gpiojhandler(int irq, FAR void *context)
 {
-  return lm_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context);
+  return lm_gpiohandler(LM_GPIOJ_BASE, LM_IRQ_GPIOJ_0, context);
 }
 #endif
 
@@ -275,40 +275,40 @@ int gpio_irqinitialize(void)
    */
 
 #ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
-  irq_attach(LM3S_IRQ_GPIOA, lm_gpioahandler);
-  up_enable_irq(LM3S_IRQ_GPIOA);
+  irq_attach(LM_IRQ_GPIOA, lm_gpioahandler);
+  up_enable_irq(LM_IRQ_GPIOA);
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
-  irq_attach(LM3S_IRQ_GPIOB, lm_gpiobhandler);
-  up_enable_irq(LM3S_IRQ_GPIOB);
+  irq_attach(LM_IRQ_GPIOB, lm_gpiobhandler);
+  up_enable_irq(LM_IRQ_GPIOB);
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
-  irq_attach(LM3S_IRQ_GPIOC, lm_gpiochandler);
-  up_enable_irq(LM3S_IRQ_GPIOC);
+  irq_attach(LM_IRQ_GPIOC, lm_gpiochandler);
+  up_enable_irq(LM_IRQ_GPIOC);
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
-  irq_attach(LM3S_IRQ_GPIOD, lm_gpiodhandler);
-  up_enable_irq(LM3S_IRQ_GPIOD);
+  irq_attach(LM_IRQ_GPIOD, lm_gpiodhandler);
+  up_enable_irq(LM_IRQ_GPIOD);
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
-  irq_attach(LM3S_IRQ_GPIOE, lm_gpioehandler);
-  up_enable_irq(LM3S_IRQ_GPIOE);
+  irq_attach(LM_IRQ_GPIOE, lm_gpioehandler);
+  up_enable_irq(LM_IRQ_GPIOE);
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
-  irq_attach(LM3S_IRQ_GPIOF, lm_gpiofhandler);
-  up_enable_irq(LM3S_IRQ_GPIOF);
+  irq_attach(LM_IRQ_GPIOF, lm_gpiofhandler);
+  up_enable_irq(LM_IRQ_GPIOF);
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
-  irq_attach(LM3S_IRQ_GPIOG, lm_gpioghandler);
-  up_enable_irq(LM3S_IRQ_GPIOG);
+  irq_attach(LM_IRQ_GPIOG, lm_gpioghandler);
+  up_enable_irq(LM_IRQ_GPIOG);
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
-  irq_attach(LM3S_IRQ_GPIOH, lm_gpiohhandler);
-  up_enable_irq(LM3S_IRQ_GPIOH);
+  irq_attach(LM_IRQ_GPIOH, lm_gpiohhandler);
+  up_enable_irq(LM_IRQ_GPIOH);
 #endif
 #ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
-  irq_attach(LM3S_IRQ_GPIOJ, lm_gpiojhandler);
-  up_enable_irq(LM3S_IRQ_GPIOJ);
+  irq_attach(LM_IRQ_GPIOJ, lm_gpiojhandler);
+  up_enable_irq(LM_IRQ_GPIOJ);
 #endif
 
   return OK;
@@ -386,9 +386,9 @@ void gpio_irqenable(int irq)
        */
 
       flags   = irqsave();
-      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+      regval  = getreg32(base + LM_GPIO_IM_OFFSET);
       regval |= pin;
-      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+      putreg32(regval, base + LM_GPIO_IM_OFFSET);
       irqrestore(flags);
     }
 }
@@ -425,10 +425,9 @@ void gpio_irqdisable(int irq)
        */
 
       flags   = irqsave();
-      regval  = getreg32(base + LM3S_GPIO_IM_OFFSET);
+      regval  = getreg32(base + LM_GPIO_IM_OFFSET);
       regval &= ~pin;
-      putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
+      putreg32(regval, base + LM_GPIO_IM_OFFSET);
       irqrestore(flags);
     }
 }
-
diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c
index 700944202..fa8e271bc 100644
--- a/nuttx/arch/arm/src/lm/lm_irq.c
+++ b/nuttx/arch/arm/src/lm/lm_irq.c
@@ -63,7 +63,7 @@
  * bringup
  */
 
-#undef LM3S_IRQ_DEBUG
+#undef LM_IRQ_DEBUG
 
 /* Get a 32-bit version of the default priority */
 
@@ -95,7 +95,7 @@ volatile uint32_t *current_regs;
  *
  ****************************************************************************/
 
-#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
+#if defined(LM_IRQ_DEBUG) && defined (CONFIG_DEBUG)
 static void lm_dumpnvic(const char *msg, int irq)
 {
   irqstate_t flags;
@@ -201,21 +201,21 @@ static int lm_reserved(int irq, FAR void *context)
 
 static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
 {
-  DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS);
+  DEBUGASSERT(irq >= LM_IRQ_NMI && irq < NR_IRQS);
 
   /* Check for external interrupt */
 
-  if (irq >= LM3S_IRQ_INTERRUPTS)
+  if (irq >= LM_IRQ_INTERRUPTS)
     {
-      if (irq < LM3S_IRQ_INTERRUPTS + 32)
+      if (irq < LM_IRQ_INTERRUPTS + 32)
         {
            *regaddr = NVIC_IRQ0_31_ENABLE;
-           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS);
+           *bit     = 1 << (irq - LM_IRQ_INTERRUPTS);
         }
       else if (irq < NR_IRQS)
         {
            *regaddr = NVIC_IRQ32_63_ENABLE;
-           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
+           *bit     = 1 << (irq - LM_IRQ_INTERRUPTS - 32);
         }
       else
         {
@@ -228,19 +228,19 @@ static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
   else
     {
        *regaddr = NVIC_SYSHCON;
-       if (irq == LM3S_IRQ_MEMFAULT)
+       if (irq == LM_IRQ_MEMFAULT)
         {
           *bit = NVIC_SYSHCON_MEMFAULTENA;
         }
-      else if (irq == LM3S_IRQ_BUSFAULT)
+      else if (irq == LM_IRQ_BUSFAULT)
         {
           *bit = NVIC_SYSHCON_BUSFAULTENA;
         }
-      else if (irq == LM3S_IRQ_USAGEFAULT)
+      else if (irq == LM_IRQ_USAGEFAULT)
         {
           *bit = NVIC_SYSHCON_USGFAULTENA;
         }
-      else if (irq == LM3S_IRQ_SYSTICK)
+      else if (irq == LM_IRQ_SYSTICK)
         {
           *regaddr = NVIC_SYSTICK_CTRL;
           *bit = NVIC_SYSTICK_CTRL_ENABLE;
@@ -309,13 +309,13 @@ void up_irqinitialize(void)
    * under certain conditions.
    */
 
-  irq_attach(LM3S_IRQ_SVCALL, up_svcall);
-  irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault);
+  irq_attach(LM_IRQ_SVCALL, up_svcall);
+  irq_attach(LM_IRQ_HARDFAULT, up_hardfault);
 
   /* Set the priority of the SVCall interrupt */
 
 #ifdef CONFIG_ARCH_IRQPRIO
-/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
+/* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
 #endif
 
   /* If the MPU is enabled, then attach and enable the Memory Management
@@ -323,22 +323,22 @@ void up_irqinitialize(void)
    */
 
 #ifdef CONFIG_ARMV7M_MPU
-  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
-  up_enable_irq(LM3S_IRQ_MEMFAULT);
+  irq_attach(LM_IRQ_MEMFAULT, up_memfault);
+  up_enable_irq(LM_IRQ_MEMFAULT);
 #endif
 
   /* Attach all other processor exceptions (except reset and sys tick) */
 
 #ifdef CONFIG_DEBUG
-  irq_attach(LM3S_IRQ_NMI, lm_nmi);
+  irq_attach(LM_IRQ_NMI, lm_nmi);
 #ifndef CONFIG_ARMV7M_MPU
-  irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
+  irq_attach(LM_IRQ_MEMFAULT, up_memfault);
 #endif
-  irq_attach(LM3S_IRQ_BUSFAULT, lm_busfault);
-  irq_attach(LM3S_IRQ_USAGEFAULT, lm_usagefault);
-  irq_attach(LM3S_IRQ_PENDSV, lm_pendsv);
-  irq_attach(LM3S_IRQ_DBGMONITOR, lm_dbgmonitor);
-  irq_attach(LM3S_IRQ_RESERVED, lm_reserved);
+  irq_attach(LM_IRQ_BUSFAULT, lm_busfault);
+  irq_attach(LM_IRQ_USAGEFAULT, lm_usagefault);
+  irq_attach(LM_IRQ_PENDSV, lm_pendsv);
+  irq_attach(LM_IRQ_DBGMONITOR, lm_dbgmonitor);
+  irq_attach(LM_IRQ_RESERVED, lm_reserved);
 #endif
 
   lm_dumpnvic("initial", NR_IRQS);
@@ -433,16 +433,16 @@ int up_prioritize_irq(int irq, int priority)
   uint32_t regval;
   int shift;
 
-  DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
+  DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
 
-  if (irq < LM3S_IRQ_INTERRUPTS)
+  if (irq < LM_IRQ_INTERRUPTS)
     {
       irq    -= 4;
       regaddr = NVIC_SYSH_PRIORITY(irq);
     }
   else
     {
-      irq    -= LM3S_IRQ_INTERRUPTS;
+      irq    -= LM_IRQ_INTERRUPTS;
       regaddr = NVIC_IRQ_PRIORITY(irq);
     }
 
diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.c b/nuttx/arch/arm/src/lm/lm_lowputc.c
index d2c1f5be5..d461cd52e 100644
--- a/nuttx/arch/arm/src/lm/lm_lowputc.c
+++ b/nuttx/arch/arm/src/lm/lm_lowputc.c
@@ -57,12 +57,12 @@
 
 /* Configuration **********************************************************/
 
-#if LM3S_NUARTS < 2
+#if LM_NUARTS < 2
 #  undef  CONFIG_LM_UART1
 #  undef  CONFIG_UART1_SERIAL_CONSOLE
 #endif
 
-#if LM3S_NUARTS < 3
+#if LM_NUARTS < 3
 #  undef  CONFIG_LM_UART2
 #  undef  CONFIG_UART2_SERIAL_CONSOLE
 #endif
@@ -92,52 +92,52 @@
 /* Select UART parameters for the selected console */
 
 #if defined(CONFIG_UART0_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART0_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART0_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART0_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART0_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART0_2STOP
+#  define LM_CONSOLE_BASE     LM_UART0_BASE
+#  define LM_CONSOLE_BAUD     CONFIG_UART0_BAUD
+#  define LM_CONSOLE_BITS     CONFIG_UART0_BITS
+#  define LM_CONSOLE_PARITY   CONFIG_UART0_PARITY
+#  define LM_CONSOLE_2STOP    CONFIG_UART0_2STOP
 #elif defined(CONFIG_UART1_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART1_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART1_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART1_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART1_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART1_2STOP
+#  define LM_CONSOLE_BASE     LM_UART1_BASE
+#  define LM_CONSOLE_BAUD     CONFIG_UART1_BAUD
+#  define LM_CONSOLE_BITS     CONFIG_UART1_BITS
+#  define LM_CONSOLE_PARITY   CONFIG_UART1_PARITY
+#  define LM_CONSOLE_2STOP    CONFIG_UART1_2STOP
 #elif defined(CONFIG_UART2_SERIAL_CONSOLE)
-#  define LM3S_CONSOLE_BASE     LM3S_UART2_BASE
-#  define LM3S_CONSOLE_BAUD     CONFIG_UART2_BAUD
-#  define LM3S_CONSOLE_BITS     CONFIG_UART2_BITS
-#  define LM3S_CONSOLE_PARITY   CONFIG_UART2_PARITY
-#  define LM3S_CONSOLE_2STOP    CONFIG_UART2_2STOP
+#  define LM_CONSOLE_BASE     LM_UART2_BASE
+#  define LM_CONSOLE_BAUD     CONFIG_UART2_BAUD
+#  define LM_CONSOLE_BITS     CONFIG_UART2_BITS
+#  define LM_CONSOLE_PARITY   CONFIG_UART2_PARITY
+#  define LM_CONSOLE_2STOP    CONFIG_UART2_2STOP
 #else
 #  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
 #endif
 
 /* Get LCRH settings */
 
-#if LM3S_CONSOLE_BITS == 5
+#if LM_CONSOLE_BITS == 5
 #  define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
-#elif LM3S_CONSOLE_BITS == 6
+#elif LM_CONSOLE_BITS == 6
 #  define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
-#elif LM3S_CONSOLE_BITS == 7
+#elif LM_CONSOLE_BITS == 7
 #  define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
-#elif LM3S_CONSOLE_BITS == 8
+#elif LM_CONSOLE_BITS == 8
 #  define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
 #else
 #  error "Number of bits not supported"
 #endif
 
-#if LM3S_CONSOLE_PARITY == 0
+#if LM_CONSOLE_PARITY == 0
 #  define UART_LCRH_PARITY (0)
-#elif LM3S_CONSOLE_PARITY == 1
+#elif LM_CONSOLE_PARITY == 1
 #  define UART_LCRH_PARITY UART_LCRH_PEN
-#elif LM3S_CONSOLE_PARITY == 2
+#elif LM_CONSOLE_PARITY == 2
 #  define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
 #else
 #  error "Invalid parity selection"
 #endif
 
-#if LM3S_CONSOLE_2STOP != 0
+#if LM_CONSOLE_2STOP != 0
 #  define UART_LCRH_NSTOP UART_LCRH_STP2
 #else
 #  define UART_LCRH_NSTOP (0)
@@ -177,17 +177,17 @@
  *  divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
  */
 
-#define LM3S_BRDDEN     (16 * LM3S_CONSOLE_BAUD)
-#define LM3S_BRDI       (SYSCLK_FREQUENCY / LM3S_BRDDEN)
-#define LM3S_REMAINDER  (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
-#define LM3S_DIVFRAC    ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
+#define LM_BRDDEN     (16 * LM_CONSOLE_BAUD)
+#define LM_BRDI       (SYSCLK_FREQUENCY / LM_BRDDEN)
+#define LM_REMAINDER  (SYSCLK_FREQUENCY - LM_BRDDEN * LM_BRDI)
+#define LM_DIVFRAC    ((LM_REMAINDER * 64 + (LM_BRDDEN/2)) / LM_BRDDEN)
 
-/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
+/* For example: LM_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
  *
- * LM3S_BRDDEN    = (16 * 115,200)                           = 1,843,200
- * LM3S_BRDI      = 50,000,000 / 1,843,200                   = 27
- * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27              = 233,600
- * LM3S_DIVFRAC   = (233,600 * 64 + 921,600) / 1,843,200     = 8
+ * LM_BRDDEN    = (16 * 115,200)                           = 1,843,200
+ * LM_BRDI      = 50,000,000 / 1,843,200                   = 27
+ * LM_REMAINDER = 50,000,000 - 1,843,200 * 27              = 233,600
+ * LM_DIVFRAC   = (233,600 * 64 + 921,600) / 1,843,200     = 8
  *
  * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
  */
@@ -229,11 +229,11 @@ void up_lowputc(char ch)
 #ifdef HAVE_CONSOLE
   /* Wait until the TX FIFO is not full */
 
-  while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
+  while ((getreg32(LM_CONSOLE_BASE+LM_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
 
   /* Then send the character */
 
-  putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET);
+  putreg32((uint32_t)ch, LM_CONSOLE_BASE+LM_UART_DR_OFFSET);
 #endif
 }
 
@@ -260,18 +260,18 @@ void up_lowsetup(void)
    */
 
 #ifdef CONFIG_LM_UART0
-  regval  = getreg32(LM3S_SYSCON_RCGC1);
+  regval  = getreg32(LM_SYSCON_RCGC1);
   regval |= SYSCON_RCGC1_UART0;
-  putreg32(regval, LM3S_SYSCON_RCGC1);
+  putreg32(regval, LM_SYSCON_RCGC1);
 
   lm_configgpio(GPIO_UART0_RX);
   lm_configgpio(GPIO_UART0_TX);
 #endif
 
 #ifdef CONFIG_LM_UART1
-  regval  = getreg32(LM3S_SYSCON_RCGC1);
+  regval  = getreg32(LM_SYSCON_RCGC1);
   regval |= SYSCON_RCGC1_UART1;
-  putreg32(regval, LM3S_SYSCON_RCGC1);
+  putreg32(regval, LM_SYSCON_RCGC1);
 
   lm_configgpio(GPIO_UART1_RX);
   lm_configgpio(GPIO_UART1_TX);
@@ -282,26 +282,26 @@ void up_lowsetup(void)
 #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
   /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
 
-  ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+  ctl = getreg32(LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
   ctl &= ~UART_CTL_UARTEN;
-  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+  putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
 
   /* Write the integer portion of the BRD to the UART IBRD register */
 
-  putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
+  putreg32(LM_BRDI, LM_CONSOLE_BASE+LM_UART_IBRD_OFFSET);
 
   /* Write the fractional portion of the BRD to the UART FBRD register */
 
-  putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
+  putreg32(LM_DIVFRAC, LM_CONSOLE_BASE+LM_UART_FBRD_OFFSET);
 
   /* Write the desired serial parameters to the UART LCRH register */
 
-  putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
+  putreg32(UART_LCRH_VALUE, LM_CONSOLE_BASE+LM_UART_LCRH_OFFSET);
 
   /* Enable the UART by setting the UARTEN bit in the UART CTL register */
 
   ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
-  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+  putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
 #endif
 
 }
diff --git a/nuttx/arch/arm/src/lm/lm_serial.c b/nuttx/arch/arm/src/lm/lm_serial.c
index e9f604989..ede47a8ca 100644
--- a/nuttx/arch/arm/src/lm/lm_serial.c
+++ b/nuttx/arch/arm/src/lm/lm_serial.c
@@ -66,12 +66,12 @@
 
 /* Some sanity checks *******************************************************/
 
-#if LM3S_NUARTS < 2
+#if LM_NUARTS < 2
 #  undef  CONFIG_LM_UART1
 #  undef  CONFIG_UART1_SERIAL_CONSOLE
 #endif
 
-#if LM3S_NUARTS < 3
+#if LM_NUARTS < 3
 #  undef  CONFIG_LM_UART2
 #  undef  CONFIG_UART2_SERIAL_CONSOLE
 #endif
@@ -274,14 +274,14 @@ static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
 static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
 #endif
 
-/* This describes the state of the LM3S uart0 port. */
+/* This describes the state of the Stellaris uart0 port. */
 
 #ifdef CONFIG_LM_UART0
 static struct up_dev_s g_uart0priv =
 {
-  .uartbase       = LM3S_UART0_BASE,
+  .uartbase       = LM_UART0_BASE,
   .baud           = CONFIG_UART0_BAUD,
-  .irq            = LM3S_IRQ_UART0,
+  .irq            = LM_IRQ_UART0,
   .parity         = CONFIG_UART0_PARITY,
   .bits           = CONFIG_UART0_BITS,
   .stopbits2      = CONFIG_UART0_2STOP,
@@ -304,14 +304,14 @@ static uart_dev_t g_uart0port =
 };
 #endif
 
-/* This describes the state of the LM3S uart1 port. */
+/* This describes the state of the Stellaris uart1 port. */
 
 #ifdef CONFIG_LM_UART1
 static struct up_dev_s g_uart1priv =
 {
-  .uartbase       = LM3S_UART1_BASE,
+  .uartbase       = LM_UART1_BASE,
   .baud           = CONFIG_UART1_BAUD,
-  .irq            = LM3S_IRQ_UART1,
+  .irq            = LM_IRQ_UART1,
   .parity         = CONFIG_UART1_PARITY,
   .bits           = CONFIG_UART1_BITS,
   .stopbits2      = CONFIG_UART1_2STOP,
@@ -334,14 +334,14 @@ static uart_dev_t g_uart1port =
 };
 #endif
 
-/* This describes the state of the LM3S uart1 port. */
+/* This describes the state of the Stellaris uart1 port. */
 
 #ifdef CONFIG_LM_UART2
 static struct up_dev_s g_uart2priv =
 {
-  .uartbase       = LM3S_UART2_BASE,
+  .uartbase       = LM_UART2_BASE,
   .baud           = CONFIG_UART2_BAUD,
-  .irq            = LM3S_IRQ_UART2,
+  .irq            = LM_IRQ_UART2,
   .parity         = CONFIG_UART2_PARITY,
   .bits           = CONFIG_UART2_BITS,
   .stopbits2      = CONFIG_UART2_2STOP,
@@ -402,7 +402,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
   /* Disable all interrupts */
 
   priv->im = 0;
-  up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
+  up_serialout(priv, LM_UART_IM_OFFSET, 0);
 }
 
 /****************************************************************************
@@ -412,7 +412,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
 static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
 {
   priv->im = im;
-  up_serialout(priv, LM3S_UART_IM_OFFSET, im);
+  up_serialout(priv, LM_UART_IM_OFFSET, im);
 }
 
 /****************************************************************************
@@ -430,7 +430,7 @@ static inline void up_waittxnotfull(struct up_dev_s *priv)
     {
       /* Check Tx FIFO is full */
 
-      if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
+      if ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
         {
           /* The Tx FIFO is not full... return */
 
@@ -471,9 +471,9 @@ static int up_setup(struct uart_dev_s *dev)
 
   /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
 
-  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
+  ctl = up_serialin(priv, LM_UART_CTL_OFFSET);
   ctl &= ~UART_CTL_UARTEN;
-  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
+  up_serialout(priv, LM_UART_CTL_OFFSET, ctl);
 
   /* Calculate BAUD rate from the SYS clock:
    *
@@ -517,8 +517,8 @@ static int up_setup(struct uart_dev_s *dev)
   remainder = SYSCLK_FREQUENCY - den * brdi;
   divfrac   = ((remainder << 6) + (den >> 1)) / den;
 
-  up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
-  up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
+  up_serialout(priv, LM_UART_IBRD_OFFSET, brdi);
+  up_serialout(priv, LM_UART_FBRD_OFFSET, divfrac);
 
   /* Set up the LCRH register */
 
@@ -558,14 +558,14 @@ static int up_setup(struct uart_dev_s *dev)
       lcrh |= UART_LCRH_STP2;
     }
 
-  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
+  up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh);
 #endif
 
   /* Set the UART to interrupt whenever the TX FIFO is almost empty or when
    * any character is received.
    */
 
-  up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
+  up_serialout(priv, LM_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
 
   /* Flush the Rx and Tx FIFOs -- How do you do that?*/
 
@@ -575,27 +575,27 @@ static int up_setup(struct uart_dev_s *dev)
    * yet because the interrupt is still disabled at the interrupt controller.
    */
 
-  up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
+  up_serialout(priv, LM_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
 
   /* Enable the FIFOs */
 
 #ifdef CONFIG_SUPPRESS_UART_CONFIG
-  lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
+  lcrh = up_serialin(priv, LM_UART_LCRH_OFFSET);
 #endif
   lcrh |= UART_LCRH_FEN;
-  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
+  up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh);
 
   /* Enable Rx, Tx, and the UART */
 
 #ifdef CONFIG_SUPPRESS_UART_CONFIG
-  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
+  ctl = up_serialin(priv, LM_UART_CTL_OFFSET);
 #endif
   ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
-  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
+  up_serialout(priv, LM_UART_CTL_OFFSET, ctl);
 
   /* Set up the cache IM value */
 
-  priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
+  priv->im = up_serialin(priv, LM_UART_IM_OFFSET);
   return OK;
 }
 
@@ -716,8 +716,8 @@ static int up_interrupt(int irq, void *context)
 
       /* Get the masked UART status and clear the pending interrupts. */
 
-       mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
-       up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
+       mis = up_serialin(priv, LM_UART_MIS_OFFSET);
+       up_serialout(priv, LM_UART_ICR_OFFSET, mis);
 
       /* Handle incoming, receive bytes (with or without timeout) */
 
@@ -797,7 +797,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
 
   /* Get the Rx byte + 4 bits of error information.  Return those in status */
 
-  rxd     = up_serialin(priv, LM3S_UART_DR_OFFSET);
+  rxd     = up_serialin(priv, LM_UART_DR_OFFSET);
   *status = rxd;
 
   /* The lower 8bits of the Rx data is the actual recevied byte */
@@ -830,7 +830,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
     {
       priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
     }
-  up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+  up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
 }
 
 /****************************************************************************
@@ -844,7 +844,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
 static bool up_rxavailable(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
+  return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
 }
 
 /****************************************************************************
@@ -858,7 +858,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
 static void up_send(struct uart_dev_s *dev, int ch)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
+  up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch);
 }
 
 /****************************************************************************
@@ -881,11 +881,11 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
       priv->im |= UART_IM_TXIM;
-      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+      up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
 
       /* The serial driver wants an interrupt here, but will not get get
        * one unless we "prime the pump."  I believe that this is because
-       * behave like a level interrupt and the LM3S interrupts behave
+       * behave like a level interrupt and the Stellaris interrupts behave
        * (at least by default) like edge interrupts.
        *
        * In any event, faking a TX interrupt here solves the problem;
@@ -901,7 +901,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
       /* Disable the TX interrupt */
 
       priv->im &= ~UART_IM_TXIM;
-      up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+      up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
     }
   irqrestore(flags);
 }
@@ -917,7 +917,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 static bool up_txready(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
+  return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
 }
 
 /****************************************************************************
@@ -931,7 +931,7 @@ static bool up_txready(struct uart_dev_s *dev)
 static bool up_txempty(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
+  return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
 }
 
 /****************************************************************************
@@ -1016,7 +1016,7 @@ int up_putc(int ch)
 
   up_disableuartint(priv, &im);
   up_waittxnotfull(priv);
-  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
+  up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch);
 
   /* Check for LF */
 
@@ -1025,7 +1025,7 @@ int up_putc(int ch)
       /* Add CR */
 
       up_waittxnotfull(priv);
-      up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r');
+      up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)'\r');
     }
 
   up_waittxnotfull(priv);
diff --git a/nuttx/arch/arm/src/lm/lm_ssi.c b/nuttx/arch/arm/src/lm/lm_ssi.c
index c6f8dcdb1..dae08e092 100644
--- a/nuttx/arch/arm/src/lm/lm_ssi.c
+++ b/nuttx/arch/arm/src/lm/lm_ssi.c
@@ -83,12 +83,12 @@
  * such case, the following must be expanded).
  */
 
-#if LM3S_NSSI == 0
+#if LM_NSSI == 0
 #  undef CONFIG_SSI0_DISABLE
 #  define CONFIG_SSI0_DISABLE 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
-#elif LM3S_NSSI == 1
+#elif LM_NSSI == 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
 #endif
@@ -102,15 +102,15 @@
 #   define NSSI_ENABLED 2        /* Two SSI interfaces: SSI0 & SSI1 */
 #  else
 #   define NSSI_ENABLED 1        /* One SSI interface: SSI0 */
-#   define SSI_BASE          LM3S_SSI0_BASE
-#   define SSI_IRQ           LM3S_IRQ_SSI0
+#   define SSI_BASE          LM_SSI0_BASE
+#   define SSI_IRQ           LM_IRQ_SSI0
 #  endif
 #else
 #  ifndef CONFIG_SSI1_DISABLE
 #   define SSI1_NDX 0            /* Index to SSI1 in g_ssidev[] */
 #   define NSSI_ENABLED 1        /* One SSI interface: SSI1 */
-#   define SSI_BASE          LM3S_SSI1_BASE
-#   define SSI_IRQ           LM3S_IRQ_SSI1
+#   define SSI_BASE          LM_SSI1_BASE
+#   define SSI_IRQ           LM_IRQ_SSI1
 #  else
 #   define NSSI_ENABLED 0        /* No SSI interfaces */
 #  endif
@@ -124,19 +124,19 @@
 
 /* The number of (16-bit) words that will fit in the Tx FIFO */
 
-#define LM3S_TXFIFO_WORDS 8
+#define LM_TXFIFO_WORDS 8
 
 /* Configuration settings */
 
 #ifndef CONFIG_SSI_TXLIMIT
-#  define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2)
+#  define CONFIG_SSI_TXLIMIT (LM_TXFIFO_WORDS/2)
 #endif
 
-#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS
+#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM_TXFIFO_WORDS
 #  error "Invalid range for CONFIG_SSI_TXLIMIT"
 #endif
 
-#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2)
+#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM_TXFIFO_WORDS/2)
 #  error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
 #endif
 
@@ -304,10 +304,10 @@ static struct lm_ssidev_s g_ssidev[] =
   {
     .ops  = &g_spiops,
 #if NSSI_ENABLED > 1
-    .base = LM3S_SSI0_BASE,
+    .base = LM_SSI0_BASE,
 #endif
 #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
-    .irq  = LM3S_IRQ_SSI0,
+    .irq  = LM_IRQ_SSI0,
 #endif
   },
 #endif
@@ -315,10 +315,10 @@ static struct lm_ssidev_s g_ssidev[] =
   {
     .ops  = &g_spiops,
 #if NSSI_ENABLED > 1
-    .base = LM3S_SSI1_BASE,
+    .base = LM_SSI1_BASE,
 #endif
 #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
-    .irq  = LM3S_IRQ_SSI1,
+    .irq  = LM_IRQ_SSI1,
 #endif
   },
 #endif
@@ -404,9 +404,9 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv)
   uint32_t retval;
   uint32_t regval;
 
-  retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
+  retval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
   regval = (retval & ~SSI_CR1_SSE);
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
+  ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
   ssivdbg("CR1: %08x\n", regval);
   return retval;
 }
@@ -430,10 +430,10 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv)
 
 static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable)
 {
-  uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
+  uint32_t regval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
   regval &= ~SSI_CR1_SSE;
   regval  |= (enable & SSI_CR1_SSE);
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
+  ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
   ssivdbg("CR1: %08x\n", regval);
 }
 
@@ -484,14 +484,14 @@ static void ssi_semtake(sem_t *sem)
 static void ssi_txnull(struct lm_ssidev_s *priv)
 {
   ssivdbg("TX: ->0xffff\n");
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff);
+  ssi_putreg(priv, LM_SSI_DR_OFFSET, 0xffff);
 }
 
 static void ssi_txuint16(struct lm_ssidev_s *priv)
 {
   uint16_t *ptr    = (uint16_t*)priv->txbuffer;
   ssivdbg("TX: %p->%04x\n", ptr, *ptr);
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
+  ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
   priv->txbuffer = (void*)ptr;
 }
 
@@ -499,7 +499,7 @@ static void ssi_txuint8(struct lm_ssidev_s *priv)
 {
   uint8_t *ptr   = (uint8_t*)priv->txbuffer;
   ssivdbg("TX: %p->%02x\n", ptr, *ptr);
-  ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
+  ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
   priv->txbuffer = (void*)ptr;
 }
 
@@ -523,17 +523,17 @@ static void ssi_txuint8(struct lm_ssidev_s *priv)
 static void ssi_rxnull(struct lm_ssidev_s *priv)
 {
 #if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
-  uint32_t regval  = ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  uint32_t regval  = ssi_getreg(priv, LM_SSI_DR_OFFSET);
   ssivdbg("RX: discard %04x\n", regval);
 #else
-  (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  (void)ssi_getreg(priv, LM_SSI_DR_OFFSET);
 #endif
 }
 
 static void ssi_rxuint16(struct lm_ssidev_s *priv)
 {
   uint16_t *ptr    = (uint16_t*)priv->rxbuffer;
-  *ptr           = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  *ptr           = (uint16_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
   ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
   priv->rxbuffer = (void*)(++ptr);
 }
@@ -541,7 +541,7 @@ static void ssi_rxuint16(struct lm_ssidev_s *priv)
 static void ssi_rxuint8(struct lm_ssidev_s *priv)
 {
   uint8_t *ptr   = (uint8_t*)priv->rxbuffer;
-  *ptr           = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
+  *ptr           = (uint8_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
   ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
   priv->rxbuffer = (void*)(++ptr);
 }
@@ -562,7 +562,7 @@ static void ssi_rxuint8(struct lm_ssidev_s *priv)
 
 static inline bool ssi_txfifofull(struct lm_ssidev_s *priv)
 {
-  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
+  return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
 }
 
 /****************************************************************************
@@ -581,7 +581,7 @@ static inline bool ssi_txfifofull(struct lm_ssidev_s *priv)
 
 static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv)
 {
-  return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
+  return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
 }
 
 /****************************************************************************
@@ -657,7 +657,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv)
       /* Check again... Now have all of the Tx words been sent? */
 
 #ifndef CONFIG_SSI_POLLWAIT
-      regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
+      regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
       if (priv->ntxwords > 0)
         {
           /* No.. Enable the Tx FIFO interrupt.  This interrupt occurs
@@ -678,7 +678,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv)
 
           regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
         }
-      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
+      ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
 #endif /* CONFIG_SSI_POLLWAIT */
     }
   return ntxd;
@@ -728,7 +728,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv)
    */
 
 #ifndef CONFIG_SSI_POLLWAIT
-  regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
+  regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
   if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
     {
        /* There are no more outgoing words to send, but there are
@@ -751,7 +751,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv)
 
       regval &= ~(SSI_IM_RX|SSI_IM_RT);
     }
-  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
+  ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
 #endif /* CONFIG_SSI_POLLWAIT */
 }
 
@@ -829,7 +829,7 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer,
   flags = irqsave();
   ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
           priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
+          ssi_getreg(priv, LM_SSI_SR_OFFSET));
 
   ntxd  = ssi_performtx(priv);
 
@@ -842,8 +842,8 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer,
 
   ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
           priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
-          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
+          ssi_getreg(priv, LM_SSI_SR_OFFSET),
+          ssi_getreg(priv, LM_SSI_IM_OFFSET));
 
   /* Wait for the transfer to complete.  Since there is no handshake
    * with SPI, the following should complete even if there are problems
@@ -908,11 +908,11 @@ static inline struct lm_ssidev_s *ssi_mapirq(int irq)
   switch (irq)
     {
 #ifndef CONFIG_SSI0_DISABLE
-      case LM3S_IRQ_SSI0:
+      case LM_IRQ_SSI0:
         return &g_ssidev[SSI0_NDX];
 #endif
 #ifndef CONFIG_SSI1_DISABLE
-      case LM3S_IRQ_SSI1:
+      case LM_IRQ_SSI1:
         return &g_ssidev[SSI1_NDX];
 #endif
       default:
@@ -952,8 +952,8 @@ static int ssi_interrupt(int irq, void *context)
 
   /* Clear pending interrupts */
 
-  regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET);
-  ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval);
+  regval = ssi_getreg(priv, LM_SSI_RIS_OFFSET);
+  ssi_putreg(priv, LM_SSI_ICR_OFFSET, regval);
 
   /* Check for Rx FIFO overruns */
 
@@ -966,7 +966,7 @@ static int ssi_interrupt(int irq, void *context)
 
   ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
           priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
+          ssi_getreg(priv, LM_SSI_SR_OFFSET));
 
   /* Handle outgoing Tx FIFO transfers */
 
@@ -978,8 +978,8 @@ static int ssi_interrupt(int irq, void *context)
 
   ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
           priv->ntxwords, priv->nrxwords, priv->nwords,
-          ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
-          ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
+          ssi_getreg(priv, LM_SSI_SR_OFFSET),
+          ssi_getreg(priv, LM_SSI_IM_OFFSET));
 
   /* Check if the transfer is complete */
 
@@ -987,7 +987,7 @@ static int ssi_interrupt(int irq, void *context)
     {
       /* Yes.. Disable all SSI interrupt sources */
 
-      ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
+      ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
 
       /* Wake up the waiting thread */
 
@@ -1135,14 +1135,14 @@ static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv, uint32_t freq
       /* Set CPDVSR */
 
       DEBUGASSERT(cpsdvsr < 255);
-      ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr);
+      ssi_putreg(priv, LM_SSI_CPSR_OFFSET, cpsdvsr);
 
       /* Set SCR */
 
-      regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
       regval &= ~SSI_CR0_SCR_MASK;
       regval |= (scr << SSI_CR0_SCR_SHIFT);
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
       ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
 
       /* Calcluate the actual frequency */
@@ -1235,10 +1235,10 @@ static void ssi_setmodeinternal(struct lm_ssidev_s *priv, enum spi_mode_e mode)
 
       /* Then set the selected mode: Freescale SPI format, mode0-3 */
 
-      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval  = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
       regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
       regval |= modebits;
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
       ssivdbg("CR0: %08x\n", regval);
 
       /* Save the mode so that subsequent re-configuratins will be faster */
@@ -1287,10 +1287,10 @@ static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits)
   DEBUGASSERT(priv);
   if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
     {
-      regval  = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
+      regval  = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
       regval &= ~SSI_CR0_DSS_MASK;
       regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
-      ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
+      ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
       ssivdbg("CR0: %08x\n", regval);
 
       priv->nbits = nbits;
@@ -1464,9 +1464,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       /* Enable the SSI0 peripheral */
 
-      regval = getreg32(LM3S_SYSCON_RCGC1);
+      regval = getreg32(LM_SYSCON_RCGC1);
       regval |= SYSCON_RCGC1_SSI0;
-      putreg32(regval, LM3S_SYSCON_RCGC1);
+      putreg32(regval, LM_SYSCON_RCGC1);
       ssivdbg("RCGC1: %08x\n", regval);
 
       /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
@@ -1488,9 +1488,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       /* Enable the SSI1 peripheral */
 
-      regval = getreg32(LM3S_SYSCON_RCGC1);
+      regval = getreg32(LM_SYSCON_RCGC1);
       regval |= SYSCON_RCGC1_SSI1;
-      putreg32(regval, LM3S_SYSCON_RCGC1);
+      putreg32(regval, LM_SYSCON_RCGC1);
       ssivdbg("RCGC1: %08x\n", regval);
 
       /* Configure SSI1 GPIOs */
@@ -1518,11 +1518,11 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
   /* Set all CR1 fields to reset state.  This will be master mode. */
 
-  ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0);
+  ssi_putreg(priv, LM_SSI_CR1_OFFSET, 0);
 
   /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
 
-  ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0);
+  ssi_putreg(priv, LM_SSI_CR0_OFFSET, 0);
 
   /* Set the initial mode to mode 0.  The application may override
    * this initial setting using the setmode() method.
@@ -1547,7 +1547,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
    * while there is an SSI transfer in progress.
    */
 
-  ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
+  ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
 
   /* Attach the interrupt */
 
diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.c b/nuttx/arch/arm/src/lm/lm_syscontrol.c
index f0d0bd3c9..2ded66c8e 100644
--- a/nuttx/arch/arm/src/lm/lm_syscontrol.c
+++ b/nuttx/arch/arm/src/lm/lm_syscontrol.c
@@ -159,7 +159,7 @@ static inline void lm_plllock(void)
     {
       /* Check if the PLL is locked on */
 
-      if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
+      if ((getreg32(LM_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
         {
           /* Yes.. return now */
 
@@ -191,17 +191,17 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
 
   /* Get the current values of the RCC and RCC2 registers */
 
-  rcc  = getreg32(LM3S_SYSCON_RCC);
-  rcc2 = getreg32(LM3S_SYSCON_RCC2);
+  rcc  = getreg32(LM_SYSCON_RCC);
+  rcc2 = getreg32(LM_SYSCON_RCC2);
 
   /* Temporarily bypass the PLL and system clock dividers */
 
   rcc |= SYSCON_RCC_BYPASS;
   rcc &= ~(SYSCON_RCC_USESYSDIV);
-  putreg32(rcc, LM3S_SYSCON_RCC);
+  putreg32(rcc, LM_SYSCON_RCC);
 
   rcc2 |= SYSCON_RCC2_BYPASS2;
-  putreg32(rcc2, LM3S_SYSCON_RCC2);
+  putreg32(rcc2, LM_SYSCON_RCC2);
 
   /* We are probably using the main oscillator.  The main oscillator is disabled on
    * reset and so probably must be enabled here.  The internal oscillator is enabled
@@ -214,7 +214,7 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
       /* Enable any selected osciallators (but don't disable any yet) */
 
       rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
-      putreg32(rcc, LM3S_SYSCON_RCC);
+      putreg32(rcc, LM_SYSCON_RCC);
 
       /* Wait for the newly selected oscillator(s) to settle.  This is tricky because
        * the time that we wait can be significant and is determined by the previous
@@ -234,7 +234,7 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
 
   /* Clear the PLL lock interrupt */
 
-  putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC);
+  putreg32(SYSCON_MISC_PLLLMIS, LM_SYSCON_MISC);
 
   /* Write the new RCC/RCC2 values.  Order depends upon whether RCC2 or RCC
    * is currently enabled.
@@ -242,13 +242,13 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
 
   if (rcc2 & SYSCON_RCC2_USERCC2)
     {
-      putreg32(rcc2, LM3S_SYSCON_RCC2);
-      putreg32(rcc, LM3S_SYSCON_RCC);
+      putreg32(rcc2, LM_SYSCON_RCC2);
+      putreg32(rcc, LM_SYSCON_RCC);
     }
     else
     {
-      putreg32(rcc, LM3S_SYSCON_RCC);
-      putreg32(rcc2, LM3S_SYSCON_RCC2);
+      putreg32(rcc, LM_SYSCON_RCC);
+      putreg32(rcc2, LM_SYSCON_RCC2);
     }
 
   /* Wait for the new crystal value and oscillator source to take effect */
@@ -279,8 +279,8 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
 
   /* Now we can set the final RCC/RCC2 values */
 
-  putreg32(rcc, LM3S_SYSCON_RCC);
-  putreg32(rcc2, LM3S_SYSCON_RCC2);
+  putreg32(rcc, LM_SYSCON_RCC);
+  putreg32(rcc2, LM_SYSCON_RCC2);
 
   /* Wait for the system divider to be effective */
 
@@ -303,13 +303,13 @@ void up_clockconfig(void)
    * around a PLL bug
    */
 
-  putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL);
+  putreg32(SYSCON_LPDOPCTL_2750MV, LM_SYSCON_LDOPCTL);
 #endif
 
   /* Set the clocking to run with the default settings provided in the board.h
    * header file
    */
 
-  lm_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE);
+  lm_clockconfig(LM_RCC_VALUE, LM_RCC2_VALUE);
 }
 
diff --git a/nuttx/arch/arm/src/lm/lm_timerisr.c b/nuttx/arch/arm/src/lm/lm_timerisr.c
index 0469a473b..49e11e5c5 100644
--- a/nuttx/arch/arm/src/lm/lm_timerisr.c
+++ b/nuttx/arch/arm/src/lm/lm_timerisr.c
@@ -130,7 +130,7 @@ void up_timerinit(void)
 
   /* Attach the timer interrupt vector */
 
-  (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr);
+  (void)irq_attach(LM_IRQ_SYSTICK, (xcpt_t)up_timerisr);
 
   /* Enable SysTick interrupts */
 
@@ -138,5 +138,5 @@ void up_timerinit(void)
 
   /* And enable the timer interrupt */
 
-  up_enable_irq(LM3S_IRQ_SYSTICK);
+  up_enable_irq(LM_IRQ_SYSTICK);
 }
diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S
index 93350a9ff..fecff0428 100644
--- a/nuttx/arch/arm/src/lm/lm_vectors.S
+++ b/nuttx/arch/arm/src/lm/lm_vectors.S
@@ -421,214 +421,214 @@ lm_vectors:
 	.type	handlers, function
 	.thumb_func
 handlers:
-	HANDLER	lm_reserved, LM3S_IRQ_RESERVED		/* Unexpected/reserved vector */
-	HANDLER	lm_nmi, LM3S_IRQ_NMI					/* Vector  2: Non-Maskable Interrupt (NMI) */
-	HANDLER	lm_hardfault, LM3S_IRQ_HARDFAULT		/* Vector  3: Hard fault */
-	HANDLER	lm_mpu, LM3S_IRQ_MEMFAULT				/* Vector  4: Memory management (MPU) */
-	HANDLER	lm_busfault, LM3S_IRQ_BUSFAULT		/* Vector  5: Bus fault */
-	HANDLER	lm_usagefault, LM3S_IRQ_USAGEFAULT	/* Vector  6: Usage fault */
-	HANDLER	lm_svcall, LM3S_IRQ_SVCALL			/* Vector 11: SVC call */
-	HANDLER	lm_dbgmonitor, LM3S_IRQ_DBGMONITOR	/* Vector 12: Debug Monitor */
-	HANDLER	lm_pendsv, LM3S_IRQ_PENDSV			/* Vector 14: Penable system service request */
-	HANDLER	lm_systick, LM3S_IRQ_SYSTICK			/* Vector 15: System tick */
+	HANDLER	lm_reserved, LM_IRQ_RESERVED		/* Unexpected/reserved vector */
+	HANDLER	lm_nmi, LM_IRQ_NMI					/* Vector  2: Non-Maskable Interrupt (NMI) */
+	HANDLER	lm_hardfault, LM_IRQ_HARDFAULT		/* Vector  3: Hard fault */
+	HANDLER	lm_mpu, LM_IRQ_MEMFAULT				/* Vector  4: Memory management (MPU) */
+	HANDLER	lm_busfault, LM_IRQ_BUSFAULT		/* Vector  5: Bus fault */
+	HANDLER	lm_usagefault, LM_IRQ_USAGEFAULT	/* Vector  6: Usage fault */
+	HANDLER	lm_svcall, LM_IRQ_SVCALL			/* Vector 11: SVC call */
+	HANDLER	lm_dbgmonitor, LM_IRQ_DBGMONITOR	/* Vector 12: Debug Monitor */
+	HANDLER	lm_pendsv, LM_IRQ_PENDSV			/* Vector 14: Penable system service request */
+	HANDLER	lm_systick, LM_IRQ_SYSTICK			/* Vector 15: System tick */
 
 #if defined(CONFIG_ARCH_CHIP_LM3S6918)
-	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
-	HANDLER	lm_gpioh, LM3S_IRQ_GPIOH			/* Vector 48: GPIO Port H */
-	HANDLER	lm_ssi1, LM3S_IRQ_SSI1				/* Vector 50: SSI 1 */
-	HANDLER	lm_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
- 	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_cmp1, LM_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+	HANDLER	lm_gpioh, LM_IRQ_GPIOH				/* Vector 48: GPIO Port H */
+	HANDLER	lm_ssi1, LM_IRQ_SSI1				/* Vector 50: SSI 1 */
+	HANDLER	lm_tmr3a, LM_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm_tmr3b, LM_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm_i2c1, LM_IRQ_I2C1				/* Vector 53: I2C 1 */
+ 	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm_hib, LM_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
 #elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
- 	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_pwm0, LM_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_cmp1, LM_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+ 	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
 #elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
-	HANDLER	lm_uart2, LM3S_IRQ_UART1			/* Vector 49: UART 1 */
-	HANDLER	lm_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER lm_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
- 	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_pwmfault, LM_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm_pwm0, LM_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm_pwm1, LM_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm_pwm2, LM_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm_qei0, LM_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_cmp1, LM_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+	HANDLER	lm_uart2, LM_IRQ_UART1				/* Vector 49: UART 1 */
+	HANDLER	lm_tmr3a, LM_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm_tmr3b, LM_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm_i2c1, LM_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER lm_qei1, LM_IRQ_QEI1				/* Vector 54: QEI 1 */
+ 	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm_hib, LM_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
 #elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
-	HANDLER	lm_uart2, LM3S_IRQ_UART1			/* Vector 49: UART 1 */
-	HANDLER	lm_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER	lm_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
-	HANDLER	lm_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
- 	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm_hib, LM3S_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
+	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_pwmfault, LM_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm_pwm0, LM_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm_pwm1, LM_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm_pwm2, LM_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm_qei0, LM_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+	HANDLER	lm_uart2, LM_IRQ_UART1				/* Vector 49: UART 1 */
+	HANDLER	lm_tmr3a, LM_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm_tmr3b, LM_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm_i2c1, LM_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER	lm_qei1, LM_IRQ_QEI1				/* Vector 54: QEI 1 */
+	HANDLER	lm_can0, LM_IRQ_CAN0				/* Vector 55: CAN 0 */
+ 	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+	HANDLER	lm_hib, LM_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
 #elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-	HANDLER	lm_gpioa, LM3S_IRQ_GPIOA			/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM3S_IRQ_GPIOB			/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM3S_IRQ_GPIOC			/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM3S_IRQ_GPIOD			/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM3S_IRQ_GPIOE			/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM3S_IRQ_UART0			/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM3S_IRQ_UART1			/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM3S_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM3S_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_pwmfault, LM3S_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm_pwm0, LM3S_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm_pwm1, LM3S_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm_pwm2, LM3S_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm_qei0, LM3S_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm_adc0, LM3S_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM3S_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM3S_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM3S_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM3S_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM3S_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM3S_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM3S_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM3S_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM3S_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM3S_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM3S_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_cmp1, LM3S_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm_cmp2, LM3S_IRQ_COMPARE2			/* Vector 43: Analog Comparator 2 */
-	HANDLER	lm_syscon, LM3S_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM3S_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM3S_IRQ_GPIOF			/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM3S_IRQ_GPIOG			/* Vector 47: GPIO Port G */
-	HANDLER	lm_gpioh, LM3S_IRQ_GPIOH			/* Vector 48: GPIO Port H */
-	HANDLER	lm_uart2, LM3S_IRQ_UART2			/* Vector 49: UART 2 */
-	HANDLER	lm_ssi1, LM3S_IRQ_SSI1				/* Vector 50: GPIO Port H */
-	HANDLER	lm_tmr3a, LM3S_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm_tmr3b, LM3S_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm_i2c1, LM3S_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER	lm_qei1, LM3S_IRQ_QEI1				/* Vector 54: QEI 1 */
- 	HANDLER	lm_can0, LM3S_IRQ_CAN0				/* Vector 55: CAN 0 */
-	HANDLER	lm_can1, LM3S_IRQ_CAN1				/* Vector 56: CAN 1 */
-	HANDLER	lm_eth, LM3S_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
- 	HANDLER	lm_usb, LM3S_IRQ_USB				/* Vector 60: USB */
- 	HANDLER	lm_pwm3, LM3S_IRQ_PWM3				/* Vector 61: PWM 3  */
- 	HANDLER	lm_udmasoft, LM3S_IRQ_UDMASOFT		/* Vector 62: uDMA Software  */
- 	HANDLER	lm_udmaerror, LM3S_IRQ_UDMAERROR	/* Vector 63: uDMA Error */
- 	HANDLER	lm_adc1_0, LM3S_IRQ_ADC1_0			/* Vector 64: ADC1 Sequence 0 */
- 	HANDLER	lm_adc1_1, LM3S_IRQ_ADC1_1			/* Vector 65: ADC1 Sequence 1 */
- 	HANDLER	lm_adc1_2, LM3S_IRQ_ADC1_2			/* Vector 66: ADC1 Sequence 2 */
- 	HANDLER	lm_adc1_3, LM3S_IRQ_ADC1_3			/* Vector 67: ADC1 Sequence 3 */
- 	HANDLER	lm_i2s0, LM3S_IRQ_I2S0				/* Vector 68: I2S 0 */
- 	HANDLER	lm_epi, LM3S_IRQ_EPI				/* Vector 69: EPI  */
- 	HANDLER	lm_gpioj, LM3S_IRQ_GPIOJ			/* Vector 70: GPIO Port J */
+	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
+	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
+	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
+	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
+	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
+	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
+	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
+	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
+	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
+	HANDLER	lm_pwmfault, LM_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
+	HANDLER	lm_pwm0, LM_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
+	HANDLER	lm_pwm1, LM_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
+	HANDLER	lm_pwm2, LM_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
+	HANDLER	lm_qei0, LM_IRQ_QEI0				/* Vector 29: QEI 0 */
+	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
+	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
+	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
+	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
+	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
+	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
+	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
+	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
+	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
+	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
+	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
+	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
+	HANDLER	lm_cmp1, LM_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
+	HANDLER	lm_cmp2, LM_IRQ_COMPARE2			/* Vector 43: Analog Comparator 2 */
+	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
+	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
+	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
+	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
+	HANDLER	lm_gpioh, LM_IRQ_GPIOH				/* Vector 48: GPIO Port H */
+	HANDLER	lm_uart2, LM_IRQ_UART2				/* Vector 49: UART 2 */
+	HANDLER	lm_ssi1, LM_IRQ_SSI1				/* Vector 50: GPIO Port H */
+	HANDLER	lm_tmr3a, LM_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
+	HANDLER	lm_tmr3b, LM_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
+	HANDLER	lm_i2c1, LM_IRQ_I2C1				/* Vector 53: I2C 1 */
+	HANDLER	lm_qei1, LM_IRQ_QEI1				/* Vector 54: QEI 1 */
+ 	HANDLER	lm_can0, LM_IRQ_CAN0				/* Vector 55: CAN 0 */
+	HANDLER	lm_can1, LM_IRQ_CAN1				/* Vector 56: CAN 1 */
+	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
+ 	HANDLER	lm_usb, LM_IRQ_USB					/* Vector 60: USB */
+ 	HANDLER	lm_pwm3, LM_IRQ_PWM3				/* Vector 61: PWM 3  */
+ 	HANDLER	lm_udmasoft, LM_IRQ_UDMASOFT		/* Vector 62: uDMA Software  */
+ 	HANDLER	lm_udmaerror, LM_IRQ_UDMAERROR		/* Vector 63: uDMA Error */
+ 	HANDLER	lm_adc1_0, LM_IRQ_ADC1_0			/* Vector 64: ADC1 Sequence 0 */
+ 	HANDLER	lm_adc1_1, LM_IRQ_ADC1_1			/* Vector 65: ADC1 Sequence 1 */
+ 	HANDLER	lm_adc1_2, LM_IRQ_ADC1_2			/* Vector 66: ADC1 Sequence 2 */
+ 	HANDLER	lm_adc1_3, LM_IRQ_ADC1_3			/* Vector 67: ADC1 Sequence 3 */
+ 	HANDLER	lm_i2s0, LM_IRQ_I2S0				/* Vector 68: I2S 0 */
+ 	HANDLER	lm_epi, LM_IRQ_EPI					/* Vector 69: EPI  */
+ 	HANDLER	lm_gpioj, LM_IRQ_GPIOJ				/* Vector 70: GPIO Port J */
 #else
-#  error "Vectors not specified for this LM3S chip"
+#  error "Vectors not specified for this Stellaris chip"
 #endif
 
 /* Common IRQ handling logic.  On entry here, the return stack is on either
diff --git a/nuttx/configs/avr32dev1/README.txt b/nuttx/configs/avr32dev1/README.txt
index 37e15dc9b..1f52ff0c2 100644
--- a/nuttx/configs/avr32dev1/README.txt
+++ b/nuttx/configs/avr32dev1/README.txt
@@ -431,14 +431,16 @@ AVR32DEV1 Configuration Options
 Configurations
 ^^^^^^^^^^^^^^
 
-Each Stellaris LM3S6965 Evaluation Kit configuration is maintained in a
-sudirectory and can be selected as follow:
+Each Atmel AVR32DEV configuration is maintained in a sudirectory and
+can be selected as follow:
 
     cd tools
     ./configure.sh avr32dev1/<subdir>
     cd -
     . ./setenv.sh
 
+(Or configure.bat in a native Windows environment).
+
 Where <subdir> is one of the following:
 
   nsh:
diff --git a/nuttx/configs/eagle100/README.txt b/nuttx/configs/eagle100/README.txt
index 378f5a25b..8ed581e98 100644
--- a/nuttx/configs/eagle100/README.txt
+++ b/nuttx/configs/eagle100/README.txt
@@ -344,7 +344,7 @@ Eagle100-specific Configuration Options
     CONFIG_LM_DISABLE_GPIOH_IRQS=y
     CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
-  LM3S6818 specific device driver settings
+  LM3S6918 specific device driver settings
 
     CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
        console and ttys0 (default is the UART0).
@@ -368,7 +368,7 @@ Eagle100-specific Configuration Options
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
     CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
-      to build the LM3S Ethernet driver
+      to build the Stellaris Ethernet driver
     CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM_BOARDMAC - If the board-specific logic can provide
       a MAC address (via lm_ethernetmac()), then this should be selected.
diff --git a/nuttx/configs/eagle100/include/board.h b/nuttx/configs/eagle100/include/board.h
index 597f801ac..e7d9414a0 100644
--- a/nuttx/configs/eagle100/include/board.h
+++ b/nuttx/configs/eagle100/include/board.h
@@ -63,7 +63,7 @@
  * of (400 / 2) / 4 = 50MHz
  */
 
-#define LM3S_SYSDIV          4
+#define LM_SYSDIV            4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
 /* Other RCC settings:
@@ -74,7 +74,7 @@
  * - No auto-clock gating reset
  */
 
-#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
 
 /* RCC2 settings -- RCC2 not used.  Other RCC2 settings
  *
@@ -83,7 +83,7 @@
  * - Not using RCC2
  */
 
-#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
 
 /* LED definitions ******************************************************************/
 
@@ -115,9 +115,9 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
  *
  ************************************************************************************/
 
diff --git a/nuttx/configs/eagle100/src/eagle100_internal.h b/nuttx/configs/eagle100/src/eagle100_internal.h
index 8a76e2eb5..48da6b9f7 100644
--- a/nuttx/configs/eagle100/src/eagle100_internal.h
+++ b/nuttx/configs/eagle100/src/eagle100_internal.h
@@ -56,12 +56,12 @@
  * expanded).
  */
 
-#if LM3S_NSSI == 0
+#if LM_NSSI == 0
 #  undef CONFIG_SSI0_DISABLE
 #  define CONFIG_SSI0_DISABLE 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
-#elif LM3S_NSSI == 1
+#elif LM_NSSI == 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
 #endif
diff --git a/nuttx/configs/eagle100/src/up_boot.c b/nuttx/configs/eagle100/src/up_boot.c
index 8fed389f8..bd46bf288 100644
--- a/nuttx/configs/eagle100/src/up_boot.c
+++ b/nuttx/configs/eagle100/src/up_boot.c
@@ -63,9 +63,10 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
+ *
  ************************************************************************************/
 
 void lm_boardinitialize(void)
diff --git a/nuttx/configs/eagle100/src/up_ethernet.c b/nuttx/configs/eagle100/src/up_ethernet.c
index 42876b3b5..c3cea86e8 100644
--- a/nuttx/configs/eagle100/src/up_ethernet.c
+++ b/nuttx/configs/eagle100/src/up_ethernet.c
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
 
   /* Get the current value of the user registers */
 
-  user0 = getreg32(LM3S_FLASH_USERREG0);
-  user1 = getreg32(LM3S_FLASH_USERREG1);
+  user0 = getreg32(LM_FLASH_USERREG0);
+  user1 = getreg32(LM_FLASH_USERREG1);
 
   nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
diff --git a/nuttx/configs/ekk-lm3s9b96/README.txt b/nuttx/configs/ekk-lm3s9b96/README.txt
index 78f7f7b8c..01aa1496c 100644
--- a/nuttx/configs/ekk-lm3s9b96/README.txt
+++ b/nuttx/configs/ekk-lm3s9b96/README.txt
@@ -324,7 +324,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
 
        CONFIG_DRAM_START=0x20000000
 
-    CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
+    CONFIG_ARCH_IRQPRIO - The LM3S9B96 supports interrupt prioritization
 
        CONFIG_ARCH_IRQPRIO=y
 
@@ -348,7 +348,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
        the delay actually is 100 seconds.
 
   There are configurations for disabling support for interrupts GPIO ports.
-  GPIOJ must be disabled because it does not exist on the LM3S6918.
+  GPIOJ must be disabled because it does not exist on the LM3S9B96.
   Additional interrupt support can be disabled if desired to reduce memory
   footprint.
 
@@ -362,7 +362,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
     CONFIG_LM_DISABLE_GPIOH_IRQS=n
     CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
-  LM3S6818 specific device driver settings
+  LM3S9B96 specific device driver settings
 
     CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
        console and ttys0 (default is the UART0).
@@ -386,7 +386,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
     CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
-      to build the LM3S Ethernet driver
+      to build the Stellaris Ethernet driver
     CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM_BOARDMAC - If the board-specific logic can provide
       a MAC address (via lm_ethernetmac()), then this should be selected.
diff --git a/nuttx/configs/ekk-lm3s9b96/include/board.h b/nuttx/configs/ekk-lm3s9b96/include/board.h
index f5c997539..c2fe521c7 100644
--- a/nuttx/configs/ekk-lm3s9b96/include/board.h
+++ b/nuttx/configs/ekk-lm3s9b96/include/board.h
@@ -64,7 +64,7 @@
  * of (400 / 2) / 4 = 50MHz
  */
 
-#define LM3S_SYSDIV          4
+#define LM_SYSDIV            4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
 /* Other RCC settings:
@@ -75,7 +75,7 @@
  * - No auto-clock gating reset
  */
 
-#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
 
 /* RCC2 settings -- RCC2 not used.  Other RCC2 settings
  *
@@ -84,7 +84,7 @@
  * - Not using RCC2
  */
 
-#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
 
 /* LED definitions ******************************************************************/
 
@@ -116,9 +116,9 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
  *
  ************************************************************************************/
 
diff --git a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
index d7ab916c8..a353020b8 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
+++ b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
@@ -57,12 +57,12 @@
  * expanded).
  */
 
-#if LM3S_NSSI == 0
+#if LM_NSSI == 0
 #  undef CONFIG_SSI0_DISABLE
 #  define CONFIG_SSI0_DISABLE 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
-#elif LM3S_NSSI == 1
+#elif LM_NSSI == 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
 #endif
diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_boot.c b/nuttx/configs/ekk-lm3s9b96/src/up_boot.c
index 16057ccb9..312f63adc 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/up_boot.c
+++ b/nuttx/configs/ekk-lm3s9b96/src/up_boot.c
@@ -65,9 +65,10 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
+ *
  ************************************************************************************/
 
 void lm_boardinitialize(void)
diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c b/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c
index bc4149082..735073803 100644
--- a/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c
+++ b/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c
@@ -81,8 +81,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
 
   /* Get the current value of the user registers */
 
-  user0 = getreg32(LM3S_FLASH_USERREG0);
-  user1 = getreg32(LM3S_FLASH_USERREG1);
+  user0 = getreg32(LM_FLASH_USERREG0);
+  user1 = getreg32(LM_FLASH_USERREG1);
 
   nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
diff --git a/nuttx/configs/lm3s6432-s2e/README.txt b/nuttx/configs/lm3s6432-s2e/README.txt
index 29cf80fae..7241856b0 100644
--- a/nuttx/configs/lm3s6432-s2e/README.txt
+++ b/nuttx/configs/lm3s6432-s2e/README.txt
@@ -318,7 +318,7 @@ Stellaris MDL-S2E Reference Design Configuration Options
 
        CONFIG_DRAM_START=0x20000000
 
-    CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
+    CONFIG_ARCH_IRQPRIO - The LM3S6432 supports interrupt prioritization
 
        CONFIG_ARCH_IRQPRIO=y
 
@@ -389,7 +389,7 @@ Stellaris MDL-S2E Reference Design Configuration Options
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
     CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
-      to build the LM3S Ethernet driver
+      to build the Stellaris Ethernet driver
     CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM_BOARDMAC - This should be set in order to use the
       MAC address configured in the flash USER registers.
diff --git a/nuttx/configs/lm3s6432-s2e/include/board.h b/nuttx/configs/lm3s6432-s2e/include/board.h
index 7fdcabf76..a3d560361 100644
--- a/nuttx/configs/lm3s6432-s2e/include/board.h
+++ b/nuttx/configs/lm3s6432-s2e/include/board.h
@@ -63,7 +63,7 @@
  * of (400 / 2) / 4 = 50MHz
  */
 
-#define LM3S_SYSDIV          4
+#define LM_SYSDIV          4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
 /* Other RCC settings:
@@ -74,7 +74,7 @@
  * - No auto-clock gating reset
  */
 
-#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
 
 /* RCC2 settings -- RCC2 not used.  Other RCC2 settings
  *
@@ -83,7 +83,7 @@
  * - Not using RCC2
  */
 
-#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
 
 /* LED definitions ******************************************************************/
 
@@ -117,9 +117,9 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
  *
  ************************************************************************************/
 
diff --git a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
index f95b118ad..3f05bdc63 100644
--- a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
+++ b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
@@ -55,7 +55,7 @@
  * expanded).
  */
 
-#if LM3S_NSSI == 0
+#if LM_NSSI == 0
 #  undef CONFIG_SSI0_DISABLE
 #  define CONFIG_SSI0_DISABLE 1
 #endif
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_boot.c b/nuttx/configs/lm3s6432-s2e/src/up_boot.c
index da900282f..60be9c3cf 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_boot.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_boot.c
@@ -70,9 +70,10 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
+ *
  ************************************************************************************/
 
 void lm_boardinitialize(void)
diff --git a/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c b/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c
index 434ffe2c5..54c88a37b 100644
--- a/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c
+++ b/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
 
   /* Get the current value of the user registers */
 
-  user0 = getreg32(LM3S_FLASH_USERREG0);
-  user1 = getreg32(LM3S_FLASH_USERREG1);
+  user0 = getreg32(LM_FLASH_USERREG0);
+  user1 = getreg32(LM_FLASH_USERREG1);
 
   nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt
index 813e11467..77f034bf5 100644
--- a/nuttx/configs/lm3s6965-ek/README.txt
+++ b/nuttx/configs/lm3s6965-ek/README.txt
@@ -387,7 +387,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
 
        CONFIG_DRAM_START=0x20000000
 
-    CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
+    CONFIG_ARCH_IRQPRIO - The LM3S6965 supports interrupt prioritization
 
        CONFIG_ARCH_IRQPRIO=y
 
@@ -411,7 +411,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
        the delay actually is 100 seconds.
 
   There are configurations for disabling support for interrupts GPIO ports.
-  GPIOJ must be disabled because it does not exist on the LM3S6918.
+  GPIOJ must be disabled because it does not exist on the LM3S6965.
   Additional interrupt support can be disabled if desired to reduce memory
   footprint.
 
@@ -425,7 +425,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
     CONFIG_LM_DISABLE_GPIOH_IRQS=n
     CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
-  LM3S6818 specific device driver settings
+  LM3S6965 specific device driver settings
 
     CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
        console and ttys0 (default is the UART0).
@@ -449,7 +449,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
     CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
-      to build the LM3S Ethernet driver
+      to build the Stellaris Ethernet driver
     CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM_BOARDMAC - If the board-specific logic can provide
       a MAC address (via lm_ethernetmac()), then this should be selected.
diff --git a/nuttx/configs/lm3s6965-ek/include/board.h b/nuttx/configs/lm3s6965-ek/include/board.h
index 808d009cc..112c40b7a 100644
--- a/nuttx/configs/lm3s6965-ek/include/board.h
+++ b/nuttx/configs/lm3s6965-ek/include/board.h
@@ -63,7 +63,7 @@
  * of (400 / 2) / 4 = 50MHz
  */
 
-#define LM3S_SYSDIV          4
+#define LM_SYSDIV            4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
 /* Other RCC settings:
@@ -74,7 +74,7 @@
  * - No auto-clock gating reset
  */
 
-#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
 
 /* RCC2 settings -- RCC2 not used.  Other RCC2 settings
  *
@@ -83,7 +83,7 @@
  * - Not using RCC2
  */
 
-#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
 
 /* LED definitions ******************************************************************/
 
@@ -115,9 +115,9 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
  *
  ************************************************************************************/
 
diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig
index 99f2f50ab..5c288f95d 100755
--- a/nuttx/configs/lm3s6965-ek/nsh/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 
 #
-# LM3S Configuration Options
+# Stellaris Configuration Options
 #
 # CONFIG_ARCH_CHIP_LM3S6918 is not set
 # CONFIG_ARCH_CHIP_LM3S9B96 is not set
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
 CONFIG_LM_DFU=y
 
 #
-# Select LM3S Peripheral Support
+# Select Stellaris Peripheral Support
 #
 CONFIG_LM_UART0=y
 # CONFIG_LM_UART1 is not set
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
 CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
-# LM3S Ethernet Configuration
+# Stellaris Ethernet Configuration
 #
 # CONFIG_LM_ETHLEDS is not set
 # CONFIG_LM_BOARDMAC is not set
@@ -141,7 +141,7 @@ CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 # CONFIG_M3S_DUMPPACKET is not set
 
 #
-# LM3S SSI Configuration
+# Stellaris SSI Configuration
 #
 CONFIG_SSI_POLLWAIT=y
 CONFIG_SSI_TXLIMIT=4
diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig
index b86d06dc9..b123800e0 100755
--- a/nuttx/configs/lm3s6965-ek/nx/defconfig
+++ b/nuttx/configs/lm3s6965-ek/nx/defconfig
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 
 #
-# LM3S Configuration Options
+# Stellaris Configuration Options
 #
 # CONFIG_ARCH_CHIP_LM3S6918 is not set
 # CONFIG_ARCH_CHIP_LM3S9B96 is not set
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
 CONFIG_LM_DFU=y
 
 #
-# Select LM3S Peripheral Support
+# Select Stellaris Peripheral Support
 #
 CONFIG_LM_UART0=y
 # CONFIG_LM_UART1 is not set
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
 CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
-# LM3S SSI Configuration
+# Stellaris SSI Configuration
 #
 CONFIG_SSI_POLLWAIT=y
 CONFIG_SSI_TXLIMIT=4
diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig
index bc433e116..67633c916 100755
--- a/nuttx/configs/lm3s6965-ek/ostest/defconfig
+++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 
 #
-# LM3S Configuration Options
+# Stellaris Configuration Options
 #
 # CONFIG_ARCH_CHIP_LM3S6918 is not set
 # CONFIG_ARCH_CHIP_LM3S9B96 is not set
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
 CONFIG_LM_DFU=y
 
 #
-# Select LM3S Peripheral Support
+# Select Stellaris Peripheral Support
 #
 CONFIG_LM_UART0=y
 # CONFIG_LM_UART1 is not set
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
 CONFIG_LM_DISABLE_GPIOJ_IRQS=y
 
 #
-# LM3S SSI Configuration
+# Stellaris SSI Configuration
 #
 CONFIG_SSI_POLLWAIT=y
 CONFIG_SSI_TXLIMIT=4
diff --git a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
index c2fc50df1..00d55ed40 100644
--- a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
+++ b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h
@@ -56,12 +56,12 @@
  * expanded).
  */
 
-#if LM3S_NSSI == 0
+#if LM_NSSI == 0
 #  undef CONFIG_SSI0_DISABLE
 #  define CONFIG_SSI0_DISABLE 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
-#elif LM3S_NSSI == 1
+#elif LM_NSSI == 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
 #endif
diff --git a/nuttx/configs/lm3s6965-ek/src/up_boot.c b/nuttx/configs/lm3s6965-ek/src/up_boot.c
index 7ffd37f17..6229a2a59 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_boot.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_boot.c
@@ -64,9 +64,10 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
+ *
  ************************************************************************************/
 
 void lm_boardinitialize(void)
diff --git a/nuttx/configs/lm3s6965-ek/src/up_ethernet.c b/nuttx/configs/lm3s6965-ek/src/up_ethernet.c
index 2d114baaa..81d6cda26 100644
--- a/nuttx/configs/lm3s6965-ek/src/up_ethernet.c
+++ b/nuttx/configs/lm3s6965-ek/src/up_ethernet.c
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
 
   /* Get the current value of the user registers */
 
-  user0 = getreg32(LM3S_FLASH_USERREG0);
-  user1 = getreg32(LM3S_FLASH_USERREG1);
+  user0 = getreg32(LM_FLASH_USERREG0);
+  user1 = getreg32(LM_FLASH_USERREG1);
 
   nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
diff --git a/nuttx/configs/lm3s8962-ek/README.txt b/nuttx/configs/lm3s8962-ek/README.txt
index 38ed76aea..e8a0091c6 100644
--- a/nuttx/configs/lm3s8962-ek/README.txt
+++ b/nuttx/configs/lm3s8962-ek/README.txt
@@ -371,7 +371,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
 
        CONFIG_DRAM_START=0x20000000
 
-    CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
+    CONFIG_ARCH_IRQPRIO - The LM3S8962 supports interrupt prioritization
 
        CONFIG_ARCH_IRQPRIO=y
 
@@ -395,7 +395,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
        the delay actually is 100 seconds.
 
   There are configurations for disabling support for interrupts GPIO ports.
-  GPIOJ must be disabled because it does not exist on the LM3S6918.
+  GPIOJ must be disabled because it does not exist on the LM3S8962.
   Additional interrupt support can be disabled if desired to reduce memory
   footprint.
 
@@ -409,7 +409,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
     CONFIG_LM_DISABLE_GPIOH_IRQS=n
     CONFIG_LM_DISABLE_GPIOJ_IRQS=y
  
-  LM3S6818 specific device driver settings
+  LM3S8962 specific device driver settings
 
     CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
        console and ttys0 (default is the UART0).
@@ -433,7 +433,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
       Rx FIFO overrun errors.  Default: half of the Tx FIFO size (4).
 
     CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
-      to build the LM3S Ethernet driver
+      to build the Stellaris Ethernet driver
     CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
     CONFIG_LM_BOARDMAC - If the board-specific logic can provide
       a MAC address (via lm_ethernetmac()), then this should be selected.
diff --git a/nuttx/configs/lm3s8962-ek/include/board.h b/nuttx/configs/lm3s8962-ek/include/board.h
index 4d6a0c302..9c4adeaa7 100644
--- a/nuttx/configs/lm3s8962-ek/include/board.h
+++ b/nuttx/configs/lm3s8962-ek/include/board.h
@@ -63,7 +63,7 @@
  * of (400 / 2) / 4 = 50MHz
  */
 
-#define LM3S_SYSDIV          4
+#define LM_SYSDIV            4
 #define SYSCLK_FREQUENCY     50000000  /* 50MHz */
 
 /* Other RCC settings:
@@ -74,7 +74,7 @@
  * - No auto-clock gating reset
  */
 
-#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
 
 /* RCC2 settings -- RCC2 not used.  Other RCC2 settings
  *
@@ -83,7 +83,7 @@
  * - Not using RCC2
  */
 
-#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
+#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
 
 /* LED definitions ******************************************************************/
 
@@ -115,9 +115,9 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
  *
  ************************************************************************************/
 
diff --git a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
index 7fc8fa331..3f989bc13 100644
--- a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
+++ b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h
@@ -56,12 +56,12 @@
  * expanded).
  */
 
-#if LM3S_NSSI == 0
+#if LM_NSSI == 0
 #  undef CONFIG_SSI0_DISABLE
 #  define CONFIG_SSI0_DISABLE 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
-#elif LM3S_NSSI == 1
+#elif LM_NSSI == 1
 #  undef CONFIG_SSI1_DISABLE
 #  define CONFIG_SSI1_DISABLE 1
 #endif
diff --git a/nuttx/configs/lm3s8962-ek/src/up_boot.c b/nuttx/configs/lm3s8962-ek/src/up_boot.c
index 8dc5b81cc..655aa6993 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_boot.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_boot.c
@@ -64,9 +64,10 @@
  * Name: lm_boardinitialize
  *
  * Description:
- *   All LM3S architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
- *   and mapped but before any devices have been initialized.
+ *   All Stellaris architectures must provide the following entry point.  This entry
+ *   point is called early in the intitialization -- after all memory has been
+ *   configured and mapped but before any devices have been initialized.
+ *
  ************************************************************************************/
 
 void lm_boardinitialize(void)
diff --git a/nuttx/configs/lm3s8962-ek/src/up_ethernet.c b/nuttx/configs/lm3s8962-ek/src/up_ethernet.c
index 0d73233a4..63c681af9 100644
--- a/nuttx/configs/lm3s8962-ek/src/up_ethernet.c
+++ b/nuttx/configs/lm3s8962-ek/src/up_ethernet.c
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
 
   /* Get the current value of the user registers */
 
-  user0 = getreg32(LM3S_FLASH_USERREG0);
-  user1 = getreg32(LM3S_FLASH_USERREG1);
+  user0 = getreg32(LM_FLASH_USERREG0);
+  user1 = getreg32(LM_FLASH_USERREG1);
 
   nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
diff --git a/nuttx/configs/lpcxpresso-lpc1768/README.txt b/nuttx/configs/lpcxpresso-lpc1768/README.txt
index ca0c0fdbd..1d9c0cbc2 100644
--- a/nuttx/configs/lpcxpresso-lpc1768/README.txt
+++ b/nuttx/configs/lpcxpresso-lpc1768/README.txt
@@ -361,7 +361,7 @@ Code Red IDE
     crt_emu_cm3_nxp (for LPC17xx parts)
     crt_emu_a7_nxp (for LPC21/22/23/24 parts)
     crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts)
-    crt_emu_cm3_lmi (for TI Stellaris LM3S parts
+    crt_emu_cm3_lmi (for TI Stellaris parts)
 
   wire is one of:
 
diff --git a/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c b/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c
index 894404cc2..7b5f02e31 100644
--- a/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c
+++ b/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c
@@ -52,8 +52,6 @@
 #include "lpc17_internal.h"
 #include "lpcxpresso_internal.h"
 
-/* The LM3S6965 Eval Kit microSD CS is on SSI0 */
-
 #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
 
 /************************************************************************************
@@ -98,7 +96,7 @@
  * Name: lpc17_sspinitialize
  *
  * Description:
- *   Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit.
+ *   Called to configure SPI chip select GPIO pins for the LPCXpresso.
  *
  ************************************************************************************/
 
diff --git a/nuttx/configs/nucleus2g/src/up_ssp.c b/nuttx/configs/nucleus2g/src/up_ssp.c
index 5515d4968..13a768130 100644
--- a/nuttx/configs/nucleus2g/src/up_ssp.c
+++ b/nuttx/configs/nucleus2g/src/up_ssp.c
@@ -52,8 +52,6 @@
 #include "lpc17_internal.h"
 #include "nucleus2g_internal.h"
 
-/* The LM3S6965 Eval Kit microSD CS is on SSI0 */
-
 #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
 
 /************************************************************************************
@@ -98,7 +96,7 @@
  * Name: lpc17_sspinitialize
  *
  * Description:
- *   Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit.
+ *   Called to configure SPI chip select GPIO pins for the Nucleus 2G.
  *
  ************************************************************************************/
 
diff --git a/nuttx/include/nuttx/net/mii.h b/nuttx/include/nuttx/net/mii.h
index 6a5fc6e89..de4dcdfd7 100644
--- a/nuttx/include/nuttx/net/mii.h
+++ b/nuttx/include/nuttx/net/mii.h
@@ -112,12 +112,12 @@
 
 /* Luminary LM3S6918 built-in PHY: 0x07-0x0f, 0x14-0x16, 0x19-0x1f reserved */
 
-#define MII_LM3S_VSPECIFIC           0x10      /* Vendor-Specific */
-#define MII_LM3S_INTCS               0x11      /* Interrupt control/status */
-#define MII_LM3S_DIAGNOSTIC          0x12      /* Diagnostic */
-#define MII_LM3S_XCVRCONTROL         0x13      /* Transceiver Control */
-#define MII_LM3S_LEDCONFIG           0x17      /* LED Configuration */
-#define MII_LM3S_MDICONTROL          0x18      /* Ethernet PHY Management MDI/MDIX Control */
+#define MII_LM_VSPECIFIC             0x10      /* Vendor-Specific */
+#define MII_LM_INTCS                 0x11      /* Interrupt control/status */
+#define MII_LM_DIAGNOSTIC            0x12      /* Diagnostic */
+#define MII_LM_XCVRCONTROL           0x13      /* Transceiver Control */
+#define MII_LM_LEDCONFIG             0x17      /* LED Configuration */
+#define MII_LM_MDICONTROL            0x18      /* Ethernet PHY Management MDI/MDIX Control */
 
 /* Micrel KS8721: 0x15, 0x1b, and 0x1f */
 
@@ -323,79 +323,79 @@
 /* LM3S6918-specific register bit settings **********************************/
 /* LM3S6918 Vendor-Specific, address 0x10 */
 
-#define LM3S_VSPECIFIC_RXCC          (1 << 0)  /* Bit 0:  Receive Clock Control*/
-#define LM3S_VSPECIFIC_PCSBP         (1 << 1)  /* Bit 1:  PCS Bypass */
-#define LM3S_VSPECIFIC_RVSPOL        (1 << 4)  /* Bit 4:  Receive Data Polarity */
-#define LM3S_VSPECIFIC_APOL          (1 << 5)  /* Bit 5:  Auto-Polarity Disable */
-#define LM3S_VSPECIFIC_NL10          (1 << 10) /* Bit 10: Natural Loopback Mode */
-#define LM3S_VSPECIFIC_SQEI          (1 << 11) /* Bit 11: SQE Inhibit Testing */
-#define LM3S_VSPECIFIC_TXHIM         (1 << 12) /* Bit 12: Transmit High Impedance Mode */
-#define LM3S_VSPECIFIC_INPOL         (1 << 14) /* Bit 14: Interrupt Polarity Value*/
-#define LM3S_VSPECIFIC_RPTR          (1 << 15) /* Bit 15: Repeater mode*/
+#define LM_VSPECIFIC_RXCC            (1 << 0)  /* Bit 0:  Receive Clock Control*/
+#define LM_VSPECIFIC_PCSBP           (1 << 1)  /* Bit 1:  PCS Bypass */
+#define LM_VSPECIFIC_RVSPOL          (1 << 4)  /* Bit 4:  Receive Data Polarity */
+#define LM_VSPECIFIC_APOL            (1 << 5)  /* Bit 5:  Auto-Polarity Disable */
+#define LM_VSPECIFIC_NL10            (1 << 10) /* Bit 10: Natural Loopback Mode */
+#define LM_VSPECIFIC_SQEI            (1 << 11) /* Bit 11: SQE Inhibit Testing */
+#define LM_VSPECIFIC_TXHIM           (1 << 12) /* Bit 12: Transmit High Impedance Mode */
+#define LM_VSPECIFIC_INPOL           (1 << 14) /* Bit 14: Interrupt Polarity Value*/
+#define LM_VSPECIFIC_RPTR            (1 << 15) /* Bit 15: Repeater mode*/
 
 /* LM3S6918 Interrupt Control/Status, address 0x11 */
 
-#define LM3S_INTCS_ANEGCOMPINT       (1 << 0)  /* Bit 0:  Auto-Negotiation Complete Interrupt */
-#define LM3S_INTCS_RFAULTINT         (1 << 1)  /* Bit 1:  Remote Fault Interrupt */
-#define LM3S_INTCS_LSCHGINT          (1 << 2)  /* Bit 2:  Link Status Change Interrupt */
-#define LM3S_INTCS_LPACKINT          (1 << 3)  /* Bit 3:  LP Acknowledge Interrupt */
-#define LM3S_INTCS_PDFINT            (1 << 4)  /* Bit 4:  Parallel Detection Fault Interrupt */
-#define LM3S_INTCS_PRXINT            (1 << 5)  /* Bit 5:  Page Receive Interrupt */
-#define LM3S_INTCS_RXERINT           (1 << 6)  /* Bit 6:  Receive Error Interrupt */
-#define LM3S_INTCS_JABBERINT         (1 << 7)  /* Bit 7:  Jabber Event Interrupt */
-#define LM3S_INTCS_ANEGCOMPIE        (1 << 8)  /* Bit 8:  Auto-Negotiation Complete Interrupt Enable */
-#define LM3S_INTCS_RFAULTIE          (1 << 9)  /* Bit 9:  Remote Fault Interrupt Enable */
-#define LM3S_INTCS_LSCHGIE           (1 << 10) /* Bit 10: Link Status Change Interrupt Enable */
-#define LM3S_INTCS_LPACKIE           (1 << 11) /* Bit 11: LP Acknowledge Interrupt Enable */
-#define LM3S_INTCS_PDFIE             (1 << 12) /* Bit 12: Parallel Detection Fault Interrupt Enable */
-#define LM3S_INTCS_PRXIE             (1 << 13) /* Bit 13: Page Received Interrupt Enable */
-#define LM3S_INTCS_RXERIE            (1 << 14) /* Bit 14: Receive Error Interrupt Enable */
-#define LM3S_INTCS_JABBERIE          (1 << 15) /* Bit 15: Jabber Interrupt Enable */
+#define LM_INTCS_ANEGCOMPINT         (1 << 0)  /* Bit 0:  Auto-Negotiation Complete Interrupt */
+#define LM_INTCS_RFAULTINT           (1 << 1)  /* Bit 1:  Remote Fault Interrupt */
+#define LM_INTCS_LSCHGINT            (1 << 2)  /* Bit 2:  Link Status Change Interrupt */
+#define LM_INTCS_LPACKINT            (1 << 3)  /* Bit 3:  LP Acknowledge Interrupt */
+#define LM_INTCS_PDFINT              (1 << 4)  /* Bit 4:  Parallel Detection Fault Interrupt */
+#define LM_INTCS_PRXINT              (1 << 5)  /* Bit 5:  Page Receive Interrupt */
+#define LM_INTCS_RXERINT             (1 << 6)  /* Bit 6:  Receive Error Interrupt */
+#define LM_INTCS_JABBERINT           (1 << 7)  /* Bit 7:  Jabber Event Interrupt */
+#define LM_INTCS_ANEGCOMPIE          (1 << 8)  /* Bit 8:  Auto-Negotiation Complete Interrupt Enable */
+#define LM_INTCS_RFAULTIE            (1 << 9)  /* Bit 9:  Remote Fault Interrupt Enable */
+#define LM_INTCS_LSCHGIE             (1 << 10) /* Bit 10: Link Status Change Interrupt Enable */
+#define LM_INTCS_LPACKIE             (1 << 11) /* Bit 11: LP Acknowledge Interrupt Enable */
+#define LM_INTCS_PDFIE               (1 << 12) /* Bit 12: Parallel Detection Fault Interrupt Enable */
+#define LM_INTCS_PRXIE               (1 << 13) /* Bit 13: Page Received Interrupt Enable */
+#define LM_INTCS_RXERIE              (1 << 14) /* Bit 14: Receive Error Interrupt Enable */
+#define LM_INTCS_JABBERIE            (1 << 15) /* Bit 15: Jabber Interrupt Enable */
 
 /* LM3S6918 Diagnostic, address 0x12 */
 
-#define LM3S_DIAGNOSTIC_RX_LOCK      (1 << 8)  /* Bit 8:  Receive PLL Lock */
-#define LM3S_DIAGNOSTIC_RXSD         (1 << 9)  /* Bit 9:  Receive Detection */
-#define LM3S_DIAGNOSTIC_RATE         (1 << 10) /* Bit 10: Rate */
-#define LM3S_DIAGNOSTIC_DPLX         (1 << 11) /* Bit 11: Duplex Mode */
-#define LM3S_DIAGNOSTIC_ANEGF        (1 << 12) /* Bit 12: Auto-Negotiation Failure */
+#define LM_DIAGNOSTIC_RX_LOCK        (1 << 8)  /* Bit 8:  Receive PLL Lock */
+#define LM_DIAGNOSTIC_RXSD           (1 << 9)  /* Bit 9:  Receive Detection */
+#define LM_DIAGNOSTIC_RATE           (1 << 10) /* Bit 10: Rate */
+#define LM_DIAGNOSTIC_DPLX           (1 << 11) /* Bit 11: Duplex Mode */
+#define LM_DIAGNOSTIC_ANEGF          (1 << 12) /* Bit 12: Auto-Negotiation Failure */
 
 /* LM3S6918 Transceiver Control, address 0x13 */
 
-#define LM3S_XCVRCONTROL_TXO_SHIFT   14        /* Bits 15-14: Transmit Amplitude Selection */
-#define LM3S_XCVRCONTROL_TXO_MASK    (3 << LM3S_XCVRCONTROL_TXO_SHIFT)
-#define LM3S_XCVRCONTROL_TXO_00DB    (0 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.0dB of insertion loss */
-#define LM3S_XCVRCONTROL_TXO_04DB    (1 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.4dB of insertion loss */
-#define LM3S_XCVRCONTROL_TXO_08DB    (2 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.8dB of insertion loss */
-#define LM3S_XCVRCONTROL_TXO_12DB    (3 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 1.2dB of insertion loss */
+#define LM_XCVRCONTROL_TXO_SHIFT     14        /* Bits 15-14: Transmit Amplitude Selection */
+#define LM_XCVRCONTROL_TXO_MASK      (3 << LM_XCVRCONTROL_TXO_SHIFT)
+#define LM_XCVRCONTROL_TXO_00DB      (0 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.0dB of insertion loss */
+#define LM_XCVRCONTROL_TXO_04DB      (1 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.4dB of insertion loss */
+#define LM_XCVRCONTROL_TXO_08DB      (2 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.8dB of insertion loss */
+#define LM_XCVRCONTROL_TXO_12DB      (3 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 1.2dB of insertion loss */
 
 /* LM3S6918 LED Configuration, address 0x17 */
 
-#define LM3S_LEDCONFIG_LED0_SHIFT    (0)       /* Bits 3-0: LED0 Source */
-#define LM3S_LEDCONFIG_LED0_MASK     (0x0f << LM3S_LEDCONFIG_LED0_SHIFT)
-#define LM3S_LEDCONFIG_LED0_LINKOK   (0 << LM3S_LEDCONFIG_LED0_SHIFT)  /* Link OK */
-#define LM3S_LEDCONFIG_LED0_RXTX     (1 << LM3S_LEDCONFIG_LED0_SHIFT)  /* RX or TX activity */
-#define LM3S_LEDCONFIG_LED0_100BASET (5 << LM3S_LEDCONFIG_LED0_SHIFT)  /* 100BASE-TX mode */
-#define LM3S_LEDCONFIG_LED0_10BASET  (6 << LM3S_LEDCONFIG_LED0_SHIFT)  /* 10BASE-T mode */
-#define LM3S_LEDCONFIG_LED0_FDUPLEX  (7 << LM3S_LEDCONFIG_LED0_SHIFT)  /* Full duplex */
-#define LM3S_LEDCONFIG_LED0_OKRXTX   (8 << LM3S_LEDCONFIG_LED0_SHIFT)  /* Full duplex */
-#define LM3S_LEDCONFIG_LED1_SHIFT    (4)        /* Bits 7-4: LED1 Source */
-#define LM3S_LEDCONFIG_LED1_MASK     (0x0f << LM3S_LEDCONFIG_LED1_SHIFT)
-#define LM3S_LEDCONFIG_LED1_LINKOK   (0 << LM3S_LEDCONFIG_LED1_SHIFT)  /* Link OK */
-#define LM3S_LEDCONFIG_LED1_RXTX     (1 << LM3S_LEDCONFIG_LED1_SHIFT)  /* RX or TX activity */
-#define LM3S_LEDCONFIG_LED1_100BASET (5 << LM3S_LEDCONFIG_LED1_SHIFT)  /* 100BASE-TX mode */
-#define LM3S_LEDCONFIG_LED1_10BASET  (6 << LM3S_LEDCONFIG_LED1_SHIFT)  /* 10BASE-T mode */
-#define LM3S_LEDCONFIG_LED1_FDUPLEX  (7 << LM3S_LEDCONFIG_LED1_SHIFT)  /* Full duplex */
-#define LM3S_LEDCONFIG_LED1_OKRXTX   (8 << LM3S_LEDCONFIG_LED1_SHIFT)  /* Full duplex */
+#define LM_LEDCONFIG_LED0_SHIFT      (0)       /* Bits 3-0: LED0 Source */
+#define LM_LEDCONFIG_LED0_MASK       (0x0f << LM_LEDCONFIG_LED0_SHIFT)
+#define LM_LEDCONFIG_LED0_LINKOK     (0 << LM_LEDCONFIG_LED0_SHIFT)  /* Link OK */
+#define LM_LEDCONFIG_LED0_RXTX       (1 << LM_LEDCONFIG_LED0_SHIFT)  /* RX or TX activity */
+#define LM_LEDCONFIG_LED0_100BASET   (5 << LM_LEDCONFIG_LED0_SHIFT)  /* 100BASE-TX mode */
+#define LM_LEDCONFIG_LED0_10BASET    (6 << LM_LEDCONFIG_LED0_SHIFT)  /* 10BASE-T mode */
+#define LM_LEDCONFIG_LED0_FDUPLEX    (7 << LM_LEDCONFIG_LED0_SHIFT)  /* Full duplex */
+#define LM_LEDCONFIG_LED0_OKRXTX     (8 << LM_LEDCONFIG_LED0_SHIFT)  /* Full duplex */
+#define LM_LEDCONFIG_LED1_SHIFT      (4)        /* Bits 7-4: LED1 Source */
+#define LM_LEDCONFIG_LED1_MASK       (0x0f << LM_LEDCONFIG_LED1_SHIFT)
+#define LM_LEDCONFIG_LED1_LINKOK     (0 << LM_LEDCONFIG_LED1_SHIFT)  /* Link OK */
+#define LM_LEDCONFIG_LED1_RXTX       (1 << LM_LEDCONFIG_LED1_SHIFT)  /* RX or TX activity */
+#define LM_LEDCONFIG_LED1_100BASET   (5 << LM_LEDCONFIG_LED1_SHIFT)  /* 100BASE-TX mode */
+#define LM_LEDCONFIG_LED1_10BASET    (6 << LM_LEDCONFIG_LED1_SHIFT)  /* 10BASE-T mode */
+#define LM_LEDCONFIG_LED1_FDUPLEX    (7 << LM_LEDCONFIG_LED1_SHIFT)  /* Full duplex */
+#define LM_LEDCONFIG_LED1_OKRXTX     (8 << LM_LEDCONFIG_LED1_SHIFT)  /* Full duplex */
 
 /* LM3S6918 MDI/MDIX Control, address 0x18 */
 
-#define LM3S_MDICONTROL_MDIXSD_SHIFT (0)        /* Bits 3-0: Auto-Switching Seed */
-#define LM3S_MDICONTROL_MDIXSD_MASK  (0x0f << LM3S_MDICONTROL_MDIXSD_SHIFT)
-#define LM3S_MDICONTROL_MDIXCM       (1 << 4)  /* Bit 4:  Auto-Switching Complete */
-#define LM3S_MDICONTROL_MDIX         (1 << 5)  /* Bit 5:  Auto-Switching Configuration */
-#define LM3S_MDICONTROL_AUTOSW       (1 << 6)  /* Bit 6:  Auto-Switching Enable */
-#define LM3S_MDICONTROL_PDMODE       (1 << 7)  /* Bit 7:  Parallel Detection Mode */
+#define LM_MDICONTROL_MDIXSD_SHIFT   (0)        /* Bits 3-0: Auto-Switching Seed */
+#define LM_MDICONTROL_MDIXSD_MASK    (0x0f << LM_MDICONTROL_MDIXSD_SHIFT)
+#define LM_MDICONTROL_MDIXCM         (1 << 4)  /* Bit 4:  Auto-Switching Complete */
+#define LM_MDICONTROL_MDIX           (1 << 5)  /* Bit 5:  Auto-Switching Configuration */
+#define LM_MDICONTROL_AUTOSW         (1 << 6)  /* Bit 6:  Auto-Switching Enable */
+#define LM_MDICONTROL_PDMODE         (1 << 7)  /* Bit 7:  Parallel Detection Mode */
 
 /* KS8921-specific register bit settings ************************************/
 /* KS8921 MII Control register bit definitions (not in 802.3) */
@@ -430,26 +430,26 @@
 
 /* KS8921 10BASE-TX PHY control register */
 
-#define KS8721_10BTCR_BIT0            (1 << 0)  /* Bit 0:  xxx */
-#define KS8721_10BTCR_BIT1            (1 << 1)  /* Bit 1:  xxx */
-#define KS8721_10BTCR_MODE_SHIFT      (2)       /* Bits 2-4:  Operation Mode Indication */
-#define KS8721_10BTCR_MODE_MASK       (7 << KS8721_10BTCR_MODE_SHIFT)
-#  define KS8721_10BTCR_MODE_ANEG     (0 << KS8721_10BTCR_MODE_SHIFT) /* Still in auto-negotiation */
-#  define KS8721_10BTCR_MODE_10BTHD   (1 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T half-duplex */
-#  define KS8721_10BTCR_MODE_100BTHD  (2 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE_t half-duplex */
-#  define KS8721_10BTCR_MODE_DEFAULT  (3 << KS8721_10BTCR_MODE_SHIFT) /* Default */
-#  define KS8721_10BTCR_MODE_10BTFD   (5 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T full duplex */
-#  define KS8721_10BTCR_MODE_100BTFD  (6 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE-T full duplex */
-#  define KS8721_10BTCR_MODE_ISOLATE  (7 << KS8721_10BTCR_MODE_SHIFT) /* PHY/MII isolate */
-#define KS8721_10BTCR_ISOLATE         (1 << 5)  /* Bit 5:  PHY isolate */
-#define KS8721_10BTCR_PAUSE           (1 << 6)  /* Bit 6:  Enable pause */
-#define KS8721_10BTCR_ANEGCOMP        (1 << 7)  /* Bit 7:  Auto-negotiation complete */
-#define KS8721_10BTCR_JABBERE         (1 << 8)  /* Bit 8:  Enable Jabber */
-#define KS8721_10BTCR_INTLVL          (1 << 9)  /* Bit 9:  Interrupt level */
-#define KS8721_10BTCR_POWER           (1 << 10) /* Bit 10: Power saving */
-#define KS8721_10BTCR_FORCE           (1 << 11) /* Bit 11: Force link */
-#define KS8721_10BTCR_ENERGY          (1 << 12) /* Bit 12: Energy detect */
-#define KS8721_10BTCR_PAIRSWAPD       (1 << 13) /* Bit 13: Pairswap disable */
+#define KS8721_10BTCR_BIT0           (1 << 0)  /* Bit 0:  xxx */
+#define KS8721_10BTCR_BIT1           (1 << 1)  /* Bit 1:  xxx */
+#define KS8721_10BTCR_MODE_SHIFT     (2)       /* Bits 2-4:  Operation Mode Indication */
+#define KS8721_10BTCR_MODE_MASK      (7 << KS8721_10BTCR_MODE_SHIFT)
+#  define KS8721_10BTCR_MODE_ANEG    (0 << KS8721_10BTCR_MODE_SHIFT) /* Still in auto-negotiation */
+#  define KS8721_10BTCR_MODE_10BTHD  (1 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T half-duplex */
+#  define KS8721_10BTCR_MODE_100BTHD (2 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE_t half-duplex */
+#  define KS8721_10BTCR_MODE_DEFAULT (3 << KS8721_10BTCR_MODE_SHIFT) /* Default */
+#  define KS8721_10BTCR_MODE_10BTFD  (5 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T full duplex */
+#  define KS8721_10BTCR_MODE_100BTFD (6 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE-T full duplex */
+#  define KS8721_10BTCR_MODE_ISOLATE (7 << KS8721_10BTCR_MODE_SHIFT) /* PHY/MII isolate */
+#define KS8721_10BTCR_ISOLATE        (1 << 5)  /* Bit 5:  PHY isolate */
+#define KS8721_10BTCR_PAUSE          (1 << 6)  /* Bit 6:  Enable pause */
+#define KS8721_10BTCR_ANEGCOMP       (1 << 7)  /* Bit 7:  Auto-negotiation complete */
+#define KS8721_10BTCR_JABBERE        (1 << 8)  /* Bit 8:  Enable Jabber */
+#define KS8721_10BTCR_INTLVL         (1 << 9)  /* Bit 9:  Interrupt level */
+#define KS8721_10BTCR_POWER          (1 << 10) /* Bit 10: Power saving */
+#define KS8721_10BTCR_FORCE          (1 << 11) /* Bit 11: Force link */
+#define KS8721_10BTCR_ENERGY         (1 << 12) /* Bit 12: Energy detect */
+#define KS8721_10BTCR_PAIRSWAPD      (1 << 13) /* Bit 13: Pairswap disable */
 
 /****************************************************************************
  * Type Definitions
-- 
cgit v1.2.3


From d844f61f8ad81de5bf2b4353763ca92634fb73f4 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Wed, 9 Jan 2013 19:49:16 +0000
Subject: Re-partition Stellaris vector logic

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5499 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/arch/arm/include/lm/irq.h           | 281 +----------------
 nuttx/arch/arm/include/lm/lm3s_irq.h      | 424 +++++++++++++++++++++++++
 nuttx/arch/arm/src/lm/chip/lm3s_vectors.h | 439 ++++++++++++++++++++++++++
 nuttx/arch/arm/src/lm/chip/lm_memorymap.h |   4 +-
 nuttx/arch/arm/src/lm/chip/lm_pinmap.h    |   4 +-
 nuttx/arch/arm/src/lm/chip/lm_vectors.h   |  64 ++++
 nuttx/arch/arm/src/lm/lm_vectors.S        | 498 +-----------------------------
 7 files changed, 963 insertions(+), 751 deletions(-)
 create mode 100644 nuttx/arch/arm/include/lm/lm3s_irq.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_vectors.h
 create mode 100644 nuttx/arch/arm/src/lm/chip/lm_vectors.h

(limited to 'nuttx/arch')

diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h
index 9a5a3d153..3b984a826 100644
--- a/nuttx/arch/arm/include/lm/irq.h
+++ b/nuttx/arch/arm/include/lm/irq.h
@@ -33,10 +33,6 @@
  *
  ************************************************************************************/
 
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
- */
-
 #ifndef __ARCH_ARM_INCLUDE_LM_IRQ_H
 #define __ARCH_ARM_INCLUDE_LM_IRQ_H
 
@@ -47,263 +43,18 @@
 #include <nuttx/config.h>
 #include <nuttx/irq.h>
 
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
- * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
- */
-
-/* Processor Exceptions (vectors 0-15) */
-
-#define LM_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
-                                /* Vector  0: Reset stack pointer value */
-                                /* Vector  1: Reset (not handler as an IRQ) */
-#define LM_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define LM_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
-#define LM_IRQ_MEMFAULT     (4) /* Vector  4: Memory management (MPU) */
-#define LM_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
-#define LM_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
-#define LM_IRQ_SVCALL      (11) /* Vector 11: SVC call */
-#define LM_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
-                                /* Vector 13: Reserved */
-#define LM_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
-#define LM_IRQ_SYSTICK     (15) /* Vector 15: System tick */
-
-/* External interrupts (vectors >= 16) */
-
-#define LM_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-
-#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-                                /* Vector 25-29: Reserved */
-#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                /* Vector 43: Reserved */
-#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-#  define LM_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
-                                /* Vector 49: Reserved */
-#  define LM_IRQ_SSI1      (50) /* Vector 50: SSI 1 */
-#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-                                /* Vectors 54-57: Reserved */
-#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                /* Vectors 60-70: Reserved */
-#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-                                /* Vector 25: Reserved */
-#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-                                /* Vectors 27-29: Reserved */
-#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                /* Vector 43: Reserved */
-#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                /* Vectors 48-57: Reserved */
-#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-                                /* Vectors 59-70: Reserved */
-#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-                                /* Vector 43: Reserved */
-#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                /* Vector 48: Reserved */
-#  define LM_IRQ_UART2     (49) /* Vector 49: UART 2 */
-                                /* Vector 50: Reserved */
-#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-                                /* Vectors 55-57: Reserved */
-#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                /* Vectors 60-70: Reserved */
-#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC0 Sequence 0 */
-#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC0 Sequence 1 */
-#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC0 Sequence 2 */
-#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC0 Sequence 3 */
-#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
-#  define LM_IRQ_COMPARE2  (43) /* Vector 43: Analog Comparator 3 */
-#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-#  define LM_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
-#  define LM_IRQ_UART2     (49) /* Vector 49: UART 2 */
-#  define LM_IRQ_SSI1      (50) /* Vector 50: SSI 1  */
-#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-#  define LM_IRQ_CAN0      (55) /* Vector 55: CAN 1 */
-#  define LM_IRQ_CAN1      (56) /* Vector 56: CAN 2 */
-                                /* Vector 57: Reserved */
-#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-                                /* Vector 59: Reserved */
-#  define LM_IRQ_USB       (60) /* Vector 60: USB */
-#  define LM_IRQ_PWM3      (61) /* Vector 61: PWM Generator 3 */
-#  define LM_IRQ_UDMASOFT  (62) /* Vector 62: uDMA Software */
-#  define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
-#  define LM_IRQ_ADC1_0    (64) /* Vector 64: ADC1 Sequence 0 */
-#  define LM_IRQ_ADC1_1    (65) /* Vector 65: ADC1 Sequence 1 */
-#  define LM_IRQ_ADC1_2    (66) /* Vector 66: ADC1 Sequence 2 */
-#  define LM_IRQ_ADC1_3    (67) /* Vector 67: ADC1 Sequence 3 */
-#  define LM_IRQ_I2S0      (68) /* Vector 68: I2S0 */
-#  define LM_IRQ_EPI       (69) /* Vector 69: EPI */
-#  define LM_IRQ_GPIOJ     (70) /* Vector 70: GPIO Port J */
-                                /* Vector 71: Reserved */
-#  define NR_IRQS          (71) /* (Really less because of reserved vectors) */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
-#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
-#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
-#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
-#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
-#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
-#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
-#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
-#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
-#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
-#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
-#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
-#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
-#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
-#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
-#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
-#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
-#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
-#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
-#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
-#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
-#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
-#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
-#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
-#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
-#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
-                                /* Vector 42: Reserved */
-                                /* Vector 43: Reserved */
-#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
-#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
-#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
-#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
-                                /* Vector 48: Reserved */
-                                /* Vector 49: Reserved */
-                                /* Vector 50: Reserved */
-#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
-#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
-#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
-#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
-#  define LM_IRQ_CAN0      (54) /* Vector 55: CAN0 */
-                                /* Vectors 56-57: Reserved */
-#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
-#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
-                                /* Vectors 60-70: Reserved */
-#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
+#if defined(CONFIG_ARCH_CHIP_LM3S)
+#  include <arch/lm/lm3s_irq.h>
+#elif defined(CONFIG_ARCH_CHIP_LM4F)
+#  include <arch/lm/lm4f_irq.h>
 #else
-#  error "IRQ Numbers not specified for this Stellaris chip"
+#  error "Unsupported Stellaris IRQ file"
 #endif
 
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
 /* GPIO IRQs -- Note that support for individual GPIO ports can
  * be disabled in order to reduce the size of the implemenation.
  */
@@ -446,10 +197,8 @@
 
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
+extern "C"
+{
 #endif
 
 /************************************************************************************
@@ -464,7 +213,7 @@ extern "C" {
  *
  ****************************************************************************/
 
-EXTERN int gpio_irqattach(int irq, xcpt_t isr);
+int gpio_irqattach(int irq, xcpt_t isr);
 #define gpio_irqdetach(isr) gpio_irqattach(isr, NULL)
 
 /****************************************************************************
@@ -475,7 +224,7 @@ EXTERN int gpio_irqattach(int irq, xcpt_t isr);
  *
  ****************************************************************************/
 
-EXTERN void gpio_irqenable(int irq);
+void gpio_irqenable(int irq);
 
 /****************************************************************************
  * Name: gpio_irqdisable
@@ -485,13 +234,11 @@ EXTERN void gpio_irqenable(int irq);
  *
  ****************************************************************************/
 
-EXTERN void gpio_irqdisable(int irq);
+void gpio_irqdisable(int irq);
 
-#undef EXTERN
 #ifdef __cplusplus
 }
 #endif
 #endif
 
 #endif /* __ARCH_ARM_INCLUDE_LM_IRQ_H */
-
diff --git a/nuttx/arch/arm/include/lm/lm3s_irq.h b/nuttx/arch/arm/include/lm/lm3s_irq.h
new file mode 100644
index 000000000..a9d0640d9
--- /dev/null
+++ b/nuttx/arch/arm/include/lm/lm3s_irq.h
@@ -0,0 +1,424 @@
+/************************************************************************************
+ * arch/arm/include/lm/lm3s_irq.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H
+#define __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define LM_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+                                /* Vector  0: Reset stack pointer value */
+                                /* Vector  1: Reset (not handler as an IRQ) */
+#define LM_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define LM_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
+#define LM_IRQ_MEMFAULT     (4) /* Vector  4: Memory management (MPU) */
+#define LM_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
+#define LM_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
+#define LM_IRQ_SVCALL      (11) /* Vector 11: SVC call */
+#define LM_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
+                                /* Vector 13: Reserved */
+#define LM_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
+#define LM_IRQ_SYSTICK     (15) /* Vector 15: System tick */
+
+/* External interrupts (vectors >= 16) */
+
+#define LM_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM_RESERVED_25   (25) /* Vector 25: Reserved */
+#  define LM_RESERVED_26   (26) /* Vector 26: Reserved */
+#  define LM_RESERVED_27   (27) /* Vector 27: Reserved */
+#  define LM_RESERVED_28   (28) /* Vector 28: Reserved */
+#  define LM_RESERVED_29   (29) /* Vector 29: Reserved */
+
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+#  define LM_RESERVED_43   (43) /* Vector 43: Reserved */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
+#  define LM_RESERVED_49   (49) /* Vector 49: Reserved */
+
+#  define LM_IRQ_SSI1      (50) /* Vector 50: SSI 1 */
+#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM_RESERVED_54   (54) /* Vector 54: Reserved */
+#  define LM_RESERVED_55   (55) /* Vector 55: Reserved */
+#  define LM_RESERVED_56   (56) /* Vector 56: Reserved */
+#  define LM_RESERVED_57   (57) /* Vector 57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+
+#  define LM_RESERVED_60   (60) /* Vector 60: Reserved */
+#  define LM_RESERVED_61   (61) /* Vector 61: Reserved */
+#  define LM_RESERVED_62   (62) /* Vector 62: Reserved */
+#  define LM_RESERVED_63   (63) /* Vector 63: Reserved */
+#  define LM_RESERVED_64   (64) /* Vector 64: Reserved */
+#  define LM_RESERVED_65   (65) /* Vector 65: Reserved */
+#  define LM_RESERVED_66   (66) /* Vector 66: Reserved */
+#  define LM_RESERVED_67   (67) /* Vector 67: Reserved */
+#  define LM_RESERVED_68   (68) /* Vector 68: Reserved */
+#  define LM_RESERVED_69   (69) /* Vector 69: Reserved */
+
+#  define LM_RESERVED_70   (70) /* Vector 70: Reserved */
+
+#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM_RESERVED_25   (25) /* Vector 25: Reserved */
+#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM_RESERVED_27   (27) /* Vector 27: Reserved */
+#  define LM_RESERVED_28   (28) /* Vector 28: Reserved */
+#  define LM_RESERVED_29   (29) /* Vector 29: Reserved */
+
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+#  define LM_RESERVED_43   (43) /* Vector 43: Reserved */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM_RESERVED_48   (48) /* Vector 48: Reserved */
+#  define LM_RESERVED_49   (49) /* Vector 49: Reserved */
+
+#  define LM_RESERVED_50   (50) /* Vector 50: Reserved */
+#  define LM_RESERVED_51   (51) /* Vector 51: Reserved */
+#  define LM_RESERVED_52   (52) /* Vector 52: Reserved */
+#  define LM_RESERVED_53   (53) /* Vector 53: Reserved */
+#  define LM_RESERVED_54   (54) /* Vector 54: Reserved */
+#  define LM_RESERVED_55   (55) /* Vector 55: Reserved */
+#  define LM_RESERVED_56   (56) /* Vector 56: Reserved */
+#  define LM_RESERVED_57   (57) /* Vector 57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM_RESERVED_59   (59) /* Vector 59: Reserved */
+
+#  define LM_RESERVED_60   (60) /* Vector 60: Reserved */
+#  define LM_RESERVED_61   (61) /* Vector 61: Reserved */
+#  define LM_RESERVED_62   (62) /* Vector 62: Reserved */
+#  define LM_RESERVED_63   (63) /* Vector 63: Reserved */
+#  define LM_RESERVED_64   (64) /* Vector 64: Reserved */
+#  define LM_RESERVED_65   (65) /* Vector 65: Reserved */
+#  define LM_RESERVED_66   (66) /* Vector 66: Reserved */
+#  define LM_RESERVED_67   (67) /* Vector 67: Reserved */
+#  define LM_RESERVED_68   (68) /* Vector 68: Reserved */
+#  define LM_RESERVED_69   (69) /* Vector 69: Reserved */
+
+#  define LM_RESERVED_70   (70) /* Vector 70: Reserved */
+
+#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+#  define LM_RESERVED_43   (43) /* Vector 43: Reserved */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM_RESERVED_48   (48) /* Vector 48: Reserved */
+#  define LM_IRQ_UART2     (49) /* Vector 49: UART 2 */
+
+#  define LM_RESERVED_50   (50) /* Vector 50: Reserved */
+#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+#  define LM_RESERVED_55   (55) /* Vector 55: Reserved */
+#  define LM_RESERVED_56   (56) /* Vector 56: Reserved */
+#  define LM_RESERVED_57   (57) /* Vector 57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+
+#  define LM_RESERVED_60   (60) /* Vector 60: Reserved */
+#  define LM_RESERVED_61   (61) /* Vector 61: Reserved */
+#  define LM_RESERVED_62   (62) /* Vector 62: Reserved */
+#  define LM_RESERVED_63   (63) /* Vector 63: Reserved */
+#  define LM_RESERVED_64   (64) /* Vector 64: Reserved */
+#  define LM_RESERVED_65   (65) /* Vector 65: Reserved */
+#  define LM_RESERVED_66   (66) /* Vector 66: Reserved */
+#  define LM_RESERVED_67   (67) /* Vector 67: Reserved */
+#  define LM_RESERVED_68   (68) /* Vector 68: Reserved */
+#  define LM_RESERVED_69   (69) /* Vector 69: Reserved */
+
+#  define LM_RESERVED_70   (70) /* Vector 70: Reserved */
+
+#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC0 Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC0 Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC0 Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC0 Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+#  define LM_IRQ_COMPARE2  (43) /* Vector 43: Analog Comparator 3 */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
+#  define LM_IRQ_UART2     (49) /* Vector 49: UART 2 */
+
+#  define LM_IRQ_SSI1      (50) /* Vector 50: SSI 1  */
+#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+#  define LM_IRQ_CAN0      (55) /* Vector 55: CAN 1 */
+#  define LM_IRQ_CAN1      (56) /* Vector 56: CAN 2 */
+#  define LM_RESERVED_57   (57) /* Vector 57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM_RESERVED_59   (59) /* Vector 59: Reserved */
+
+#  define LM_IRQ_USB       (60) /* Vector 60: USB */
+#  define LM_IRQ_PWM3      (61) /* Vector 61: PWM Generator 3 */
+#  define LM_IRQ_UDMASOFT  (62) /* Vector 62: uDMA Software */
+#  define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
+#  define LM_IRQ_ADC1_0    (64) /* Vector 64: ADC1 Sequence 0 */
+#  define LM_IRQ_ADC1_1    (65) /* Vector 65: ADC1 Sequence 1 */
+#  define LM_IRQ_ADC1_2    (66) /* Vector 66: ADC1 Sequence 2 */
+#  define LM_IRQ_ADC1_3    (67) /* Vector 67: ADC1 Sequence 3 */
+#  define LM_IRQ_I2S0      (68) /* Vector 68: I2S0 */
+#  define LM_IRQ_EPI       (69) /* Vector 69: EPI */
+
+#  define LM_IRQ_GPIOJ     (70) /* Vector 70: GPIO Port J */
+#  define LM_RESERVED_71   (71) /* Vector 71: Reserved */
+
+#  define NR_IRQS          (71) /* (Really less because of reserved vectors) */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+#  define LM_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+
+#  define LM_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+
+#  define LM_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+
+#  define LM_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM_RESERVED_42   (42) /* Vector 42: Reserved */
+#  define LM_RESERVED_43   (43) /* Vector 43: Reserved */
+#  define LM_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM_RESERVED_48   (48) /* Vector 48: Reserved */
+#  define LM_RESERVED_49   (49) /* Vector 49: Reserved */
+
+#  define LM_RESERVED_50   (50) /* Vector 50: Reserved */
+#  define LM_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+#  define LM_IRQ_CAN0      (54) /* Vector 55: CAN0 */
+#  define LM_RESERVED_56   (56) /* Vector 56: Reserved */
+#  define LM_RESERVED_57   (57) /* Vector 57: Reserved */
+#  define LM_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+
+#  define LM_RESERVED_60   (60) /* Vector 60: Reserved */
+#  define LM_RESERVED_61   (61) /* Vector 61: Reserved */
+#  define LM_RESERVED_62   (62) /* Vector 62: Reserved */
+#  define LM_RESERVED_63   (63) /* Vector 63: Reserved */
+#  define LM_RESERVED_64   (64) /* Vector 64: Reserved */
+#  define LM_RESERVED_65   (65) /* Vector 65: Reserved */
+#  define LM_RESERVED_66   (66) /* Vector 66: Reserved */
+#  define LM_RESERVED_67   (67) /* Vector 67: Reserved */
+#  define LM_RESERVED_68   (68) /* Vector 68: Reserved */
+#  define LM_RESERVED_69   (69) /* Vector 69: Reserved */
+
+#  define LM_RESERVED_70   (70) /* Vector 70: Reserved */
+
+#  define NR_IRQS          (60) /* (Really less because of reserved vectors) */
+#else
+#  error "IRQ Numbers not specified for this Stellaris chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H */
+
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h b/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h
new file mode 100644
index 000000000..58447793d
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h
@@ -0,0 +1,439 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm3s_vectors.S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Preprocessor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Vectors
+ ************************************************************************************/
+
+/* This file is included by lm_vectors.S.  It provides the macro VECTOR that
+ * supplies ach Stellaris vector in terms of a (lower-case) ISR label and an
+ * (upper-case) IRQ number as defined in arch/arm/include/lm/lm3s_irq.h.
+ * lm_vectors.S will define the VECTOR in different ways in order to generate
+ * the interrupt vectors and handlers in their final form.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 71 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 71
+
+#else
+
+VECTOR(lm_gpioa, LM_IRQ_GPIOA)       /* Vector 16: GPIO Port A */
+VECTOR(lm_gpiob, LM_IRQ_GPIOB)       /* Vector 17: GPIO Port B */
+VECTOR(lm_gpioc, LM_IRQ_GPIOC)       /* Vector 18: GPIO Port C */
+VECTOR(lm_gpiod, LM_IRQ_GPIOD)       /* Vector 19: GPIO Port D */
+
+VECTOR(lm_gpioe, LM_IRQ_GPIOE)       /* Vector 20: GPIO Port E */
+VECTOR(lm_uart0, LM_IRQ_UART0)       /* Vector 21: UART 0 */
+VECTOR(lm_uart1, LM_IRQ_UART1)       /* Vector 22: UART 1 */
+VECTOR(lm_ssi0, LM_IRQ_SSI0)         /* Vector 23: SSI 0 */
+VECTOR(lm_i2c0, LM_IRQ_I2C0)         /* Vector 24: I2C 0 */
+UNUSED(LM_RESERVED_25)               /* Vector 25: Reserved */
+UNUSED(LM_RESERVED_26)               /* Vector 26: Reserved */
+UNUSED(LM_RESERVED_27)               /* Vector 27: Reserved */
+UNUSED(LM_RESERVED_28)               /* Vector 28: Reserved */
+UNUSED(LM_RESERVED_29)               /* Vector 29: Reserved */
+
+VECTOR(lm_adc0, LM_IRQ_ADC0)         /* Vector 30: ADC Sequence 0 */
+VECTOR(lm_adc1, LM_IRQ_ADC1)         /* Vector 31: ADC Sequence 1 */
+VECTOR(lm_adc2, LM_IRQ_ADC2)         /* Vector 32: ADC Sequence 2 */
+VECTOR(lm_adc3, LM_IRQ_ADC3)         /* Vector 33: ADC Sequence 3 */
+VECTOR(lm_wdog, LM_IRQ_WDOG)         /* Vector 34: Watchdog Timer */
+VECTOR(lm_tmr0a, LM_IRQ_TIMER0A)     /* Vector 35: Timer 0 A */
+VECTOR(lm_tmr0b, LM_IRQ_TIMER0B)     /* Vector 36: Timer 0 B */
+VECTOR(lm_tmr1a, LM_IRQ_TIMER1A)     /* Vector 37: Timer 1 A */
+VECTOR(lm_tmr1b, LM_IRQ_TIMER1B)     /* Vector 38: Timer 1 B */
+VECTOR(lm_tmr2a, LM_IRQ_TIMER2A)     /* Vector 39: Timer 2 A */
+
+VECTOR(lm_tmr2b, LM_IRQ_TIMER2B)     /* Vector 40: Timer 3 B */
+VECTOR(lm_cmp0, LM_IRQ_COMPARE0)     /* Vector 41: Analog Comparator 0 */
+VECTOR(lm_cmp1, LM_IRQ_COMPARE1)     /* Vector 42: Analog Comparator 1 */
+UNUSED(LM_RESERVED_43)               /* Vector 43: Reserved */
+VECTOR(lm_syscon, LM_IRQ_SYSCON)     /* Vector 44: System Control */
+VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
+VECTOR(lm_gpiof, LM_IRQ_GPIOF)       /* Vector 46: GPIO Port F */
+VECTOR(lm_gpiog, LM_IRQ_GPIOG)       /* Vector 47: GPIO Port G */
+VECTOR(lm_gpioh, LM_IRQ_GPIOH)       /* Vector 48: GPIO Port H */
+UNUSED(LM_RESERVED_49)               /* Vector 49: Reserved */
+
+VECTOR(lm_ssi1, LM_IRQ_SSI1)         /* Vector 50: SSI 1 */
+VECTOR(lm_tmr3a, LM_IRQ_TIMER3A)     /* Vector 51: Timer 3 A */
+VECTOR(lm_tmr3b, LM_IRQ_TIMER3B)     /* Vector 52: Timer 3 B */
+VECTOR(lm_i2c1, LM_IRQ_I2C1)         /* Vector 53: I2C 1 */
+UNUSED(LM_RESERVED_54)               /* Vector 54: Reserved */
+UNUSED(LM_RESERVED_55)               /* Vector 55: Reserved */
+UNUSED(LM_RESERVED_56)               /* Vector 56: Reserved */
+UNUSED(LM_RESERVED_57)               /* Vector 57: Reserved */
+VECTOR(lm_eth, LM_IRQ_ETHCON)        /* Vector 58: Ethernet Controller */
+VECTOR(lm_hib, LM_IRQ_HIBERNATE)     /* Vector 59: Hibernation Module */
+
+UNUSED(LM_RESERVED_60)               /* Vector 60: Reserved */
+UNUSED(LM_RESERVED_61)               /* Vector 61: Reserved */
+UNUSED(LM_RESERVED_62)               /* Vector 62: Reserved */
+UNUSED(LM_RESERVED_63)               /* Vector 63: Reserved */
+UNUSED(LM_RESERVED_64)               /* Vector 64: Reserved */
+UNUSED(LM_RESERVED_65)               /* Vector 65: Reserved */
+UNUSED(LM_RESERVED_66)               /* Vector 66: Reserved */
+UNUSED(LM_RESERVED_67)               /* Vector 67: Reserved */
+UNUSED(LM_RESERVED_68)               /* Vector 68: Reserved */
+UNUSED(LM_RESERVED_69)               /* Vector 69: Reserved */
+
+UNUSED(LM_RESERVED_70)               /* Vector 70: Reserved */
+#endif
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 71 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 71
+
+#else
+
+VECTOR(lm_gpioa, LM_IRQ_GPIOA)       /* Vector 16: GPIO Port A */
+VECTOR(lm_gpiob, LM_IRQ_GPIOB)       /* Vector 17: GPIO Port B */
+VECTOR(lm_gpioc, LM_IRQ_GPIOC)       /* Vector 18: GPIO Port C */
+VECTOR(lm_gpiod, LM_IRQ_GPIOD)       /* Vector 19: GPIO Port D */
+
+VECTOR(lm_gpioe, LM_IRQ_GPIOE)       /* Vector 20: GPIO Port E */
+VECTOR(lm_uart0, LM_IRQ_UART0)       /* Vector 21: UART 0 */
+VECTOR(lm_uart1, LM_IRQ_UART1)       /* Vector 22: UART 1 */
+VECTOR(lm_ssi0, LM_IRQ_SSI0)         /* Vector 23: SSI 0 */
+VECTOR(lm_i2c0, LM_IRQ_I2C0)         /* Vector 24: I2C 0 */
+UNUSED(LM_RESERVED_25)               /* Vector 25: Reserved */
+VECTOR(lm_pwm0, LM_IRQ_PWM0)         /* Vector 26: PWM Generator 0 */
+UNUSED(LM_RESERVED_27)               /* Vector 27: Reserved */
+UNUSED(LM_RESERVED_28)               /* Vector 28: Reserved */
+UNUSED(LM_RESERVED_29)               /* Vector 29: Reserved */
+
+VECTOR(lm_adc0, LM_IRQ_ADC0)         /* Vector 30: ADC Sequence 0 */
+VECTOR(lm_adc1, LM_IRQ_ADC1)         /* Vector 31: ADC Sequence 1 */
+VECTOR(lm_adc2, LM_IRQ_ADC2)         /* Vector 32: ADC Sequence 2 */
+VECTOR(lm_adc3, LM_IRQ_ADC3)         /* Vector 33: ADC Sequence 3 */
+VECTOR(lm_wdog, LM_IRQ_WDOG)         /* Vector 34: Watchdog Timer */
+VECTOR(lm_tmr0a, LM_IRQ_TIMER0A)     /* Vector 35: Timer 0 A */
+VECTOR(lm_tmr0b, LM_IRQ_TIMER0B)     /* Vector 36: Timer 0 B */
+VECTOR(lm_tmr1a, LM_IRQ_TIMER1A)     /* Vector 37: Timer 1 A */
+VECTOR(lm_tmr1b, LM_IRQ_TIMER1B)     /* Vector 38: Timer 1 B */
+VECTOR(lm_tmr2a, LM_IRQ_TIMER2A)     /* Vector 39: Timer 2 A */
+
+VECTOR(lm_tmr2b, LM_IRQ_TIMER2B)     /* Vector 40: Timer 3 B */
+VECTOR(lm_cmp0, LM_IRQ_COMPARE0)     /* Vector 41: Analog Comparator 0 */
+VECTOR(lm_cmp1, LM_IRQ_COMPARE1)     /* Vector 42: Analog Comparator 1 */
+UNUSED(LM_RESERVED_43)               /* Vector 43: Reserved */
+VECTOR(lm_syscon, LM_IRQ_SYSCON)     /* Vector 44: System Control */
+VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
+VECTOR(lm_gpiof, LM_IRQ_GPIOF)       /* Vector 46: GPIO Port F */
+VECTOR(lm_gpiog, LM_IRQ_GPIOG)       /* Vector 47: GPIO Port G */
+UNUSED(LM_RESERVED_48)               /* Vector 48: Reserved */
+UNUSED(LM_RESERVED_49)               /* Vector 49: Reserved */
+
+UNUSED(LM_RESERVED_50)               /* Vector 50: Reserved */
+UNUSED(LM_RESERVED_51)               /* Vector 51: Reserved */
+UNUSED(LM_RESERVED_52)               /* Vector 52: Reserved */
+UNUSED(LM_RESERVED_53)               /* Vector 53: Reserved */
+UNUSED(LM_RESERVED_54)               /* Vector 54: Reserved */
+UNUSED(LM_RESERVED_55)               /* Vector 55: Reserved */
+UNUSED(LM_RESERVED_56)               /* Vector 56: Reserved */
+UNUSED(LM_RESERVED_57)               /* Vector 57: Reserved */
+VECTOR(lm_eth, LM_IRQ_ETHCON)        /* Vector 58: Ethernet Controller */
+UNUSED(LM_RESERVED_59)               /* Vector 59: Reserved */
+
+UNUSED(LM_RESERVED_60)               /* Vector 60: Reserved */
+UNUSED(LM_RESERVED_61)               /* Vector 61: Reserved */
+UNUSED(LM_RESERVED_62)               /* Vector 62: Reserved */
+UNUSED(LM_RESERVED_63)               /* Vector 63: Reserved */
+UNUSED(LM_RESERVED_64)               /* Vector 64: Reserved */
+UNUSED(LM_RESERVED_65)               /* Vector 65: Reserved */
+UNUSED(LM_RESERVED_66)               /* Vector 66: Reserved */
+UNUSED(LM_RESERVED_67)               /* Vector 67: Reserved */
+UNUSED(LM_RESERVED_68)               /* Vector 68: Reserved */
+UNUSED(LM_RESERVED_69)               /* Vector 69: Reserved */
+
+UNUSED(LM_RESERVED_70)               /* Vector 70: Reserved */
+#endif
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 71 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 71
+
+#else
+
+VECTOR(lm_gpioa, LM_IRQ_GPIOA)       /* Vector 16: GPIO Port A */
+VECTOR(lm_gpiob, LM_IRQ_GPIOB)       /* Vector 17: GPIO Port B */
+VECTOR(lm_gpioc, LM_IRQ_GPIOC)       /* Vector 18: GPIO Port C */
+VECTOR(lm_gpiod, LM_IRQ_GPIOD)       /* Vector 19: GPIO Port D */
+
+VECTOR(lm_gpioe, LM_IRQ_GPIOE)       /* Vector 20: GPIO Port E */
+VECTOR(lm_uart0, LM_IRQ_UART0)       /* Vector 21: UART 0 */
+VECTOR(lm_uart1, LM_IRQ_UART1)       /* Vector 22: UART 1 */
+VECTOR(lm_ssi0, LM_IRQ_SSI0)         /* Vector 23: SSI 0 */
+VECTOR(lm_i2c0, LM_IRQ_I2C0)         /* Vector 24: I2C 0 */
+VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
+VECTOR(lm_pwm0, LM_IRQ_PWM0)         /* Vector 26: PWM Generator 0 */
+VECTOR(lm_pwm1, LM_IRQ_PWM1)         /* Vector 27: PWM Generator 1 */
+VECTOR(lm_pwm2, LM_IRQ_PWM2)         /* Vector 28: PWM Generator 2 */
+VECTOR(lm_qei0, LM_IRQ_QEI0)         /* Vector 29: QEI 0 */
+
+VECTOR(lm_adc0, LM_IRQ_ADC0)         /* Vector 30: ADC Sequence 0 */
+VECTOR(lm_adc1, LM_IRQ_ADC1)         /* Vector 31: ADC Sequence 1 */
+VECTOR(lm_adc2, LM_IRQ_ADC2)         /* Vector 32: ADC Sequence 2 */
+VECTOR(lm_adc3, LM_IRQ_ADC3)         /* Vector 33: ADC Sequence 3 */
+VECTOR(lm_wdog, LM_IRQ_WDOG)         /* Vector 34: Watchdog Timer */
+VECTOR(lm_tmr0a, LM_IRQ_TIMER0A)     /* Vector 35: Timer 0 A */
+VECTOR(lm_tmr0b, LM_IRQ_TIMER0B)     /* Vector 36: Timer 0 B */
+VECTOR(lm_tmr1a, LM_IRQ_TIMER1A)     /* Vector 37: Timer 1 A */
+VECTOR(lm_tmr1b, LM_IRQ_TIMER1B)     /* Vector 38: Timer 1 B */
+VECTOR(lm_tmr2a, LM_IRQ_TIMER2A)     /* Vector 39: Timer 2 A */
+
+VECTOR(lm_tmr2b, LM_IRQ_TIMER2B)     /* Vector 40: Timer 3 B */
+VECTOR(lm_cmp0, LM_IRQ_COMPARE0)     /* Vector 41: Analog Comparator 0 */
+VECTOR(lm_cmp1, LM_IRQ_COMPARE1)     /* Vector 42: Analog Comparator 1 */
+UNUSED(LM_RESERVED_43)               /* Vector 43: Reserved */
+VECTOR(lm_syscon, LM_IRQ_SYSCON)     /* Vector 44: System Control */
+VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
+VECTOR(lm_gpiof, LM_IRQ_GPIOF)       /* Vector 46: GPIO Port F */
+VECTOR(lm_gpiog, LM_IRQ_GPIOG)       /* Vector 47: GPIO Port G */
+UNUSED(LM_RESERVED_48)               /* Vector 48: Reserved */
+VECTOR(lm_uart2, LM_IRQ_UART1)       /* Vector 49: UART 1 */
+
+UNUSED(LM_RESERVED_50)               /* Vector 50: Reserved */
+VECTOR(lm_tmr3a, LM_IRQ_TIMER3A)     /* Vector 51: Timer 3 A */
+VECTOR(lm_tmr3b, LM_IRQ_TIMER3B)     /* Vector 52: Timer 3 B */
+VECTOR(lm_i2c1, LM_IRQ_I2C1)         /* Vector 53: I2C 1 */
+VECTOR(lm_qei1, LM_IRQ_QEI1)         /* Vector 54: QEI 1 */
+UNUSED(LM_RESERVED_55)               /* Vector 55: Reserved */
+UNUSED(LM_RESERVED_56)               /* Vector 56: Reserved */
+UNUSED(LM_RESERVED_57)               /* Vector 57: Reserved */
+VECTOR(lm_eth, LM_IRQ_ETHCON)        /* Vector 58: Ethernet Controller */
+VECTOR(lm_hib, LM_IRQ_HIBERNATE)     /* Vector 59: Hibernation Module */
+
+UNUSED(LM_RESERVED_60)               /* Vector 60: Reserved */
+UNUSED(LM_RESERVED_61)               /* Vector 61: Reserved */
+UNUSED(LM_RESERVED_62)               /* Vector 62: Reserved */
+UNUSED(LM_RESERVED_63)               /* Vector 63: Reserved */
+UNUSED(LM_RESERVED_64)               /* Vector 64: Reserved */
+UNUSED(LM_RESERVED_65)               /* Vector 65: Reserved */
+UNUSED(LM_RESERVED_66)               /* Vector 66: Reserved */
+UNUSED(LM_RESERVED_67)               /* Vector 67: Reserved */
+UNUSED(LM_RESERVED_68)               /* Vector 68: Reserved */
+UNUSED(LM_RESERVED_69)               /* Vector 69: Reserved */
+
+UNUSED(LM_RESERVED_70)               /* Vector 70: Reserved */
+#endif
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 71 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 71
+
+#else
+
+VECTOR(lm_gpioa, LM_IRQ_GPIOA)       /* Vector 16: GPIO Port A */
+VECTOR(lm_gpiob, LM_IRQ_GPIOB)       /* Vector 17: GPIO Port B */
+VECTOR(lm_gpioc, LM_IRQ_GPIOC)       /* Vector 18: GPIO Port C */
+VECTOR(lm_gpiod, LM_IRQ_GPIOD)       /* Vector 19: GPIO Port D */
+
+VECTOR(lm_gpioe, LM_IRQ_GPIOE)       /* Vector 20: GPIO Port E */
+VECTOR(lm_uart0, LM_IRQ_UART0)       /* Vector 21: UART 0 */
+VECTOR(lm_uart1, LM_IRQ_UART1)       /* Vector 22: UART 1 */
+VECTOR(lm_ssi0, LM_IRQ_SSI0)         /* Vector 23: SSI 0 */
+VECTOR(lm_i2c0, LM_IRQ_I2C0)         /* Vector 24: I2C 0 */
+VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
+VECTOR(lm_pwm0, LM_IRQ_PWM0)         /* Vector 26: PWM Generator 0 */
+VECTOR(lm_pwm1, LM_IRQ_PWM1)         /* Vector 27: PWM Generator 1 */
+VECTOR(lm_pwm2, LM_IRQ_PWM2)         /* Vector 28: PWM Generator 2 */
+VECTOR(lm_qei0, LM_IRQ_QEI0)         /* Vector 29: QEI 0 */
+
+VECTOR(lm_adc0, LM_IRQ_ADC0)         /* Vector 30: ADC Sequence 0 */
+VECTOR(lm_adc1, LM_IRQ_ADC1)         /* Vector 31: ADC Sequence 1 */
+VECTOR(lm_adc2, LM_IRQ_ADC2)         /* Vector 32: ADC Sequence 2 */
+VECTOR(lm_adc3, LM_IRQ_ADC3)         /* Vector 33: ADC Sequence 3 */
+VECTOR(lm_wdog, LM_IRQ_WDOG)         /* Vector 34: Watchdog Timer */
+VECTOR(lm_tmr0a, LM_IRQ_TIMER0A)     /* Vector 35: Timer 0 A */
+VECTOR(lm_tmr0b, LM_IRQ_TIMER0B)     /* Vector 36: Timer 0 B */
+VECTOR(lm_tmr1a, LM_IRQ_TIMER1A)     /* Vector 37: Timer 1 A */
+VECTOR(lm_tmr1b, LM_IRQ_TIMER1B)     /* Vector 38: Timer 1 B */
+VECTOR(lm_tmr2a, LM_IRQ_TIMER2A)     /* Vector 39: Timer 2 A */
+
+VECTOR(lm_tmr2b, LM_IRQ_TIMER2B)     /* Vector 40: Timer 3 B */
+VECTOR(lm_cmp0, LM_IRQ_COMPARE0)     /* Vector 41: Analog Comparator 0 */
+UNUSED(LM_RESERVED_42)               /* Vector 42: Reserved */
+UNUSED(LM_RESERVED_43)               /* Vector 43: Reserved */
+VECTOR(lm_syscon, LM_IRQ_SYSCON)     /* Vector 44: System Control */
+VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
+VECTOR(lm_gpiof, LM_IRQ_GPIOF)       /* Vector 46: GPIO Port F */
+VECTOR(lm_gpiog, LM_IRQ_GPIOG)       /* Vector 47: GPIO Port G */
+UNUSED(LM_RESERVED_48)               /* Vector 48: Reserved */
+UNUSED(LM_RESERVED_49)               /* Vector 49: Reserved */
+
+UNUSED(LM_RESERVED_50)               /* Vector 50: Reserved */
+VECTOR(lm_tmr3a, LM_IRQ_TIMER3A)     /* Vector 51: Timer 3 A */
+VECTOR(lm_tmr3b, LM_IRQ_TIMER3B)     /* Vector 52: Timer 3 B */
+VECTOR(lm_i2c1, LM_IRQ_I2C1)         /* Vector 53: I2C 1 */
+VECTOR(lm_qei1, LM_IRQ_QEI1)         /* Vector 54: QEI 1 */
+VECTOR(lm_can0, LM_IRQ_CAN0)         /* Vector 55: CAN 0 */
+UNUSED(LM_RESERVED_56)               /* Vector 56: Reserved */
+UNUSED(LM_RESERVED_57)               /* Vector 57: Reserved */
+VECTOR(lm_eth, LM_IRQ_ETHCON)        /* Vector 58: Ethernet Controller */
+VECTOR(lm_hib, LM_IRQ_HIBERNATE)     /* Vector 59: Hibernation Module */
+
+UNUSED(LM_RESERVED_60)               /* Vector 60: Reserved */
+UNUSED(LM_RESERVED_61)               /* Vector 61: Reserved */
+UNUSED(LM_RESERVED_62)               /* Vector 62: Reserved */
+UNUSED(LM_RESERVED_63)               /* Vector 63: Reserved */
+UNUSED(LM_RESERVED_64)               /* Vector 64: Reserved */
+UNUSED(LM_RESERVED_65)               /* Vector 65: Reserved */
+UNUSED(LM_RESERVED_66)               /* Vector 66: Reserved */
+UNUSED(LM_RESERVED_67)               /* Vector 67: Reserved */
+UNUSED(LM_RESERVED_68)               /* Vector 68: Reserved */
+UNUSED(LM_RESERVED_69)               /* Vector 69: Reserved */
+
+UNUSED(LM_RESERVED_70)               /* Vector 70: Reserved */
+#endif
+
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 72 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 72
+
+#else
+
+VECTOR(lm_gpioa, LM_IRQ_GPIOA)       /* Vector 16: GPIO Port A */
+VECTOR(lm_gpiob, LM_IRQ_GPIOB)       /* Vector 17: GPIO Port B */
+VECTOR(lm_gpioc, LM_IRQ_GPIOC)       /* Vector 18: GPIO Port C */
+VECTOR(lm_gpiod, LM_IRQ_GPIOD)       /* Vector 19: GPIO Port D */
+VECTOR(lm_gpioe, LM_IRQ_GPIOE)       /* Vector 20: GPIO Port E */
+
+VECTOR(lm_uart0, LM_IRQ_UART0)       /* Vector 21: UART 0 */
+VECTOR(lm_uart1, LM_IRQ_UART1)       /* Vector 22: UART 1 */
+VECTOR(lm_ssi0, LM_IRQ_SSI0)         /* Vector 23: SSI 0 */
+VECTOR(lm_i2c0, LM_IRQ_I2C0)         /* Vector 24: I2C 0 */
+VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
+VECTOR(lm_pwm0, LM_IRQ_PWM0)         /* Vector 26: PWM Generator 0 */
+VECTOR(lm_pwm1, LM_IRQ_PWM1)         /* Vector 27: PWM Generator 1 */
+VECTOR(lm_pwm2, LM_IRQ_PWM2)         /* Vector 28: PWM Generator 2 */
+VECTOR(lm_qei0, LM_IRQ_QEI0)         /* Vector 29: QEI 0 */
+
+VECTOR(lm_adc0, LM_IRQ_ADC0)         /* Vector 30: ADC Sequence 0 */
+VECTOR(lm_adc1, LM_IRQ_ADC1)         /* Vector 31: ADC Sequence 1 */
+VECTOR(lm_adc2, LM_IRQ_ADC2)         /* Vector 32: ADC Sequence 2 */
+VECTOR(lm_adc3, LM_IRQ_ADC3)         /* Vector 33: ADC Sequence 3 */
+VECTOR(lm_wdog, LM_IRQ_WDOG)         /* Vector 34: Watchdog Timer */
+VECTOR(lm_tmr0a, LM_IRQ_TIMER0A)     /* Vector 35: Timer 0 A */
+VECTOR(lm_tmr0b, LM_IRQ_TIMER0B)     /* Vector 36: Timer 0 B */
+VECTOR(lm_tmr1a, LM_IRQ_TIMER1A)     /* Vector 37: Timer 1 A */
+VECTOR(lm_tmr1b, LM_IRQ_TIMER1B)     /* Vector 38: Timer 1 B */
+VECTOR(lm_tmr2a, LM_IRQ_TIMER2A)     /* Vector 39: Timer 2 A */
+
+VECTOR(lm_tmr2b, LM_IRQ_TIMER2B)     /* Vector 40: Timer 3 B */
+VECTOR(lm_cmp0, LM_IRQ_COMPARE0)     /* Vector 41: Analog Comparator 0 */
+VECTOR(lm_cmp1, LM_IRQ_COMPARE1)     /* Vector 42: Analog Comparator 1 */
+VECTOR(lm_cmp2, LM_IRQ_COMPARE2)     /* Vector 43: Analog Comparator 2 */
+VECTOR(lm_syscon, LM_IRQ_SYSCON)     /* Vector 44: System Control */
+VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
+VECTOR(lm_gpiof, LM_IRQ_GPIOF)       /* Vector 46: GPIO Port F */
+VECTOR(lm_gpiog, LM_IRQ_GPIOG)       /* Vector 47: GPIO Port G */
+VECTOR(lm_gpioh, LM_IRQ_GPIOH)       /* Vector 48: GPIO Port H */
+VECTOR(lm_uart2, LM_IRQ_UART2)       /* Vector 49: UART 2 */
+
+VECTOR(lm_ssi1, LM_IRQ_SSI1)         /* Vector 50: GPIO Port H */
+VECTOR(lm_tmr3a, LM_IRQ_TIMER3A)     /* Vector 51: Timer 3 A */
+VECTOR(lm_tmr3b, LM_IRQ_TIMER3B)     /* Vector 52: Timer 3 B */
+VECTOR(lm_i2c1, LM_IRQ_I2C1)         /* Vector 53: I2C 1 */
+VECTOR(lm_qei1, LM_IRQ_QEI1)         /* Vector 54: QEI 1 */
+VECTOR(lm_can0, LM_IRQ_CAN0)         /* Vector 55: CAN 0 */
+VECTOR(lm_can1, LM_IRQ_CAN1)         /* Vector 56: CAN 1 */
+UNUSED(LM_RESERVED_57)               /* Vector 57: Reserved */
+VECTOR(lm_eth, LM_IRQ_ETHCON)        /* Vector 58: Ethernet Controller */
+UNUSED(LM_RESERVED_59)               /* Vector 59: Reserved */
+
+VECTOR(lm_usb, LM_IRQ_USB)           /* Vector 60: USB */
+VECTOR(lm_pwm3, LM_IRQ_PWM3)         /* Vector 61: PWM 3  */
+VECTOR(lm_udmasoft, LM_IRQ_UDMASOFT) /* Vector 62: uDMA Software  */
+VECTOR(lm_udmaerror, LM_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
+VECTOR(lm_adc1_0, LM_IRQ_ADC1_0)     /* Vector 64: ADC1 Sequence 0 */
+VECTOR(lm_adc1_1, LM_IRQ_ADC1_1)     /* Vector 65: ADC1 Sequence 1 */
+VECTOR(lm_adc1_2, LM_IRQ_ADC1_2)     /* Vector 66: ADC1 Sequence 2 */
+VECTOR(lm_adc1_3, LM_IRQ_ADC1_3)     /* Vector 67: ADC1 Sequence 3 */
+VECTOR(lm_i2s0, LM_IRQ_I2S0)         /* Vector 68: I2S 0 */
+VECTOR(lm_epi, LM_IRQ_EPI)           /* Vector 69: EPI  */
+
+VECTOR(lm_gpioj, LM_IRQ_GPIOJ)       /* Vector 70: GPIO Port J */
+UNUSED(LM_RESERVED_71)               /* Vector 71: Reserved */
+#endif
+
+#else
+#  error "Vectors not specified for this Stellaris chip"
+#endif
diff --git a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h
index 530ecdf64..d8257fc02 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h
@@ -44,8 +44,10 @@
 
 /* Include the memory map file for the specific Stellaris chip */
 
-#ifdef CONFIG_ARCH_CHIP_LM3S
+#if defined(CONFIG_ARCH_CHIP_LM3S)
 #  include "chip/lm3s_memorymap.h"
+#elif defined(CONFIG_ARCH_CHIP_LM4F)
+#  include "chip/lm4f_memorymap.h"
 #else
 #  error "Unsupported Stellaris memory map"
 #endif
diff --git a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h
index 311d6fcdc..00b42e73b 100644
--- a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h
+++ b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h
@@ -44,8 +44,10 @@
 
 /* Include the pin mapping file for the specific Stellaris chip */
 
-#ifdef CONFIG_ARCH_CHIP_LM3S
+#if defined(CONFIG_ARCH_CHIP_LM3S)
 #  include "chip/lm3s_pinmap.h"
+#elif defined(CONFIG_ARCH_CHIP_LM4F)
+#  include "chip/lm4f_pinmap.h"
 #else
 #  error "Unsupported Stellaris PIN mapping"
 #endif
diff --git a/nuttx/arch/arm/src/lm/chip/lm_vectors.h b/nuttx/arch/arm/src/lm/chip/lm_vectors.h
new file mode 100644
index 000000000..97227bf29
--- /dev/null
+++ b/nuttx/arch/arm/src/lm/chip/lm_vectors.h
@@ -0,0 +1,64 @@
+/************************************************************************************
+ * arch/arm/src/lm/chip/lm_vectors.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/* Include the vector file for the specific Stellaris chip */
+
+#if defined(CONFIG_ARCH_CHIP_LM3S)
+#  include "chip/lm3s_vectors.h"
+#elif defined(CONFIG_ARCH_CHIP_LM4F)
+#  include "chip/lm4f_vectors.h"
+#else
+#  error "Unsupported Stellaris vector file"
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S
index fecff0428..d3798fbb7 100644
--- a/nuttx/arch/arm/src/lm/lm_vectors.S
+++ b/nuttx/arch/arm/src/lm/lm_vectors.S
@@ -127,290 +127,15 @@ lm_vectors:
 
 /* External Interrupts */
 
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-	.word	lm_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm_uart0			/* Vector 21: UART 0 */
-	.word	lm_uart1			/* Vector 22: UART 1 */
-	.word	lm_ssi0				/* Vector 23: SSI 0 */
-	.word	lm_i2c0				/* Vector 24: I2C 0 */
-	.word	lm_reserved			/* Vector 25: Reserved */
-	.word	lm_reserved			/* Vector 26: Reserved */
-	.word	lm_reserved			/* Vector 27: Reserved */
-	.word	lm_reserved			/* Vector 28: Reserved */
-	.word	lm_reserved			/* Vector 29: Reserved */
-	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
-	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
-	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
-	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
-	.word	lm_wdog				/* Vector 34: Watchdog Timer */
-	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
-	.word	lm_cmp1				/* Vector 42: Analog Comparator 1 */
-	.word	lm_reserved			/* Vector 43: Reserved */
-	.word	lm_syscon			/* Vector 44: System Control */
-	.word	lm_flashcon			/* Vector 45: FLASH Control */
-	.word	lm_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm_gpioh			/* Vector 48: GPIO Port H */
-	.word	lm_reserved			/* Vector 49: Reserved */
-	.word	lm_ssi1				/* Vector 50: SSI 1 */
-	.word	lm_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm_i2c1				/* Vector 53: I2C 1 */
-	.word	lm_reserved			/* Vector 54: Reserved */
-	.word	lm_reserved			/* Vector 55: Reserved */
-	.word	lm_reserved			/* Vector 56: Reserved */
-	.word	lm_reserved			/* Vector 57: Reserved */
- 	.word	lm_eth				/* Vector 58: Ethernet Controller */
-	.word	lm_hib				/* Vector 59: Hibernation Module */
-	.word	lm_reserved			/* Vector 60: Reserved */
-	.word	lm_reserved			/* Vector 61: Reserved */
-	.word	lm_reserved			/* Vector 62: Reserved */
-	.word	lm_reserved			/* Vector 63: Reserved */
-	.word	lm_reserved			/* Vector 64: Reserved */
-	.word	lm_reserved			/* Vector 65: Reserved */
-	.word	lm_reserved			/* Vector 66: Reserved */
-	.word	lm_reserved			/* Vector 67: Reserved */
-	.word	lm_reserved			/* Vector 68: Reserved */
-	.word	lm_reserved			/* Vector 69: Reserved */
-	.word	lm_reserved			/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-	.word	lm_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm_uart0			/* Vector 21: UART 0 */
-	.word	lm_uart1			/* Vector 22: UART 1 */
-	.word	lm_ssi0				/* Vector 23: SSI 0 */
-	.word	lm_i2c0				/* Vector 24: I2C 0 */
-	.word	lm_reserved			/* Vector 25: Reserved */
-	.word	lm_pwm0				/* Vector 26: PWM Generator 0 */
-	.word	lm_reserved			/* Vector 27: Reserved */
-	.word	lm_reserved			/* Vector 28: Reserved */
-	.word	lm_reserved			/* Vector 29: Reserved */
-	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
-	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
-	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
-	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
-	.word	lm_wdog				/* Vector 34: Watchdog Timer */
-	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
-	.word	lm_cmp1				/* Vector 42: Analog Comparator 1 */
-	.word	lm_reserved			/* Vector 43: Reserved */
-	.word	lm_syscon			/* Vector 44: System Control */
-	.word	lm_flashcon			/* Vector 45: FLASH Control */
-	.word	lm_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm_reserved			/* Vector 48: Reserved */
-	.word	lm_reserved			/* Vector 49: Reserved */
-	.word	lm_reserved			/* Vector 50: Reserved */
-	.word	lm_reserved			/* Vector 51: Reserved */
-	.word	lm_reserved			/* Vector 52: Reserved */
-	.word	lm_reserved			/* Vector 53: Reserved */
-	.word	lm_reserved			/* Vector 54: Reserved */
-	.word	lm_reserved			/* Vector 55: Reserved */
-	.word	lm_reserved			/* Vector 56: Reserved */
-	.word	lm_reserved			/* Vector 57: Reserved */
- 	.word	lm_eth				/* Vector 58: Ethernet Controller */
-	.word	lm_reserved			/* Vector 59: Reserved */
-	.word	lm_reserved			/* Vector 60: Reserved */
-	.word	lm_reserved			/* Vector 61: Reserved */
-	.word	lm_reserved			/* Vector 62: Reserved */
-	.word	lm_reserved			/* Vector 63: Reserved */
-	.word	lm_reserved			/* Vector 64: Reserved */
-	.word	lm_reserved			/* Vector 65: Reserved */
-	.word	lm_reserved			/* Vector 66: Reserved */
-	.word	lm_reserved			/* Vector 67: Reserved */
-	.word	lm_reserved			/* Vector 68: Reserved */
-	.word	lm_reserved			/* Vector 69: Reserved */
-	.word	lm_reserved			/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-	.word	lm_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm_uart0			/* Vector 21: UART 0 */
-	.word	lm_uart1			/* Vector 22: UART 1 */
-	.word	lm_ssi0				/* Vector 23: SSI 0 */
-	.word	lm_i2c0				/* Vector 24: I2C 0 */
-	.word	lm_pwmfault			/* Vector 25: PWM Fault */
-	.word	lm_pwm0				/* Vector 26: PWM Generator 0 */
-	.word	lm_pwm1				/* Vector 27: PWM Generator 1 */
-	.word	lm_pwm2				/* Vector 28: PWM Generator 2 */
-	.word	lm_qei0				/* Vector 29: QEI0 */
-	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
-	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
-	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
-	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
-	.word	lm_wdog				/* Vector 34: Watchdog Timer */
-	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
-	.word	lm_cmp1				/* Vector 42: Analog Comparator 1 */
-	.word	lm_reserved			/* Vector 43: Reserved */
-	.word	lm_syscon			/* Vector 44: System Control */
-	.word	lm_flashcon			/* Vector 45: FLASH Control */
-	.word	lm_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm_reserved			/* Vector 48: Reserved */
-	.word	lm_uart2			/* Vector 49: UART 2 */
-	.word	lm_reserved			/* Vector 50: Reserved */
-	.word	lm_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm_i2c1				/* Vector 53: I2C 1 */
-	.word	lm_qei1				/* Vector 54: QEI1 */
-	.word	lm_reserved			/* Vector 55: Reserved */
-	.word	lm_reserved			/* Vector 56: Reserved */
-	.word	lm_reserved			/* Vector 57: Reserved */
- 	.word	lm_eth				/* Vector 58: Ethernet Controller */
-	.word	lm_hib				/* Vector 59: Hibernation Module */
-	.word	lm_reserved			/* Vector 60: Reserved */
-	.word	lm_reserved			/* Vector 61: Reserved */
-	.word	lm_reserved			/* Vector 62: Reserved */
-	.word	lm_reserved			/* Vector 63: Reserved */
-	.word	lm_reserved			/* Vector 64: Reserved */
-	.word	lm_reserved			/* Vector 65: Reserved */
-	.word	lm_reserved			/* Vector 66: Reserved */
-	.word	lm_reserved			/* Vector 67: Reserved */
-	.word	lm_reserved			/* Vector 68: Reserved */
-	.word	lm_reserved			/* Vector 69: Reserved */
-	.word	lm_reserved			/* Vector 70: Reserved */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-	.word	lm_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm_uart0			/* Vector 21: UART 0 */
-	.word	lm_uart1			/* Vector 22: UART 1 */
-	.word	lm_ssi0				/* Vector 23: SSI 0 */
-	.word	lm_i2c0				/* Vector 24: I2C 0 */
-	.word	lm_pwmfault			/* Vector 25: PWM Fault */
-	.word	lm_pwm0				/* Vector 26: PWM Generator 0 */
-	.word	lm_pwm1				/* Vector 27: PWM Generator 1 */
-	.word	lm_pwm2				/* Vector 28: PWM Generator 2 */
-	.word	lm_qei0				/* Vector 29: QEI0 */
-	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
-	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
-	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
-	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
-	.word	lm_wdog				/* Vector 34: Watchdog Timer */
-	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
-	.word	lm_cmp1				/* Vector 42: Analog Comparator 1 */
-	.word	lm_cmp2				/* Vector 43: Reserved */
-	.word	lm_syscon			/* Vector 44: System Control */
-	.word	lm_flashcon			/* Vector 45: FLASH Control */
-	.word	lm_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm_gpioh			/* Vector 48: GPIO Port H */
-	.word	lm_uart2			/* Vector 49: UART 2 */
-	.word	lm_ssi1				/* Vector 50: SSI 1 */
-	.word	lm_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm_i2c1				/* Vector 53: I2C 1 */
-	.word	lm_qei1				/* Vector 54: QEI1 */
-	.word	lm_can0				/* Vector 55: CAN 0 */
-	.word	lm_can1				/* Vector 56: CAN 1 */
-	.word	lm_reserved			/* Vector 57: Reserved */
- 	.word	lm_eth				/* Vector 58: Ethernet Controller */
-	.word	lm_reserved			/* Vector 59: Reserved */
-	.word	lm_usb				/* Vector 60: USB */
-	.word	lm_pwm3				/* Vector 61: PWM 3 */
-	.word	lm_udmasoft			/* Vector 62: uDMA Software */
-	.word	lm_udmaerror		/* Vector 63: uDMA Error */
-	.word	lm_adc1_0			/* Vector 64: ADC1 Sequence 0 */
-	.word	lm_adc1_1			/* Vector 65: ADC1 Sequence 1 */
-	.word	lm_adc1_2			/* Vector 66: ADC1 Sequence 2 */
-	.word	lm_adc1_3			/* Vector 67: ADC1 Sequence 3 */
-	.word	lm_i2s0 			/* Vector 68: I2S 0 */
-	.word	lm_epi				/* Vector 69: Reserved */
-	.word	lm_gpioj			/* Vector 70: GPIO J */
-	.word	lm_reserved			/* Vector 71: Reserved */
-	#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-	.word	lm_gpioa			/* Vector 16: GPIO Port A */
-	.word	lm_gpiob			/* Vector 17: GPIO Port B */
-	.word	lm_gpioc			/* Vector 18: GPIO Port C */
-	.word	lm_gpiod			/* Vector 19: GPIO Port D */
-	.word	lm_gpioe			/* Vector 20: GPIO Port E */
-	.word	lm_uart0			/* Vector 21: UART 0 */
-	.word	lm_uart1			/* Vector 22: UART 1 */
-	.word	lm_ssi0				/* Vector 23: SSI 0 */
-	.word	lm_i2c0				/* Vector 24: I2C 0 */
-	.word	lm_pwmfault			/* Vector 25: PWM Fault */
-	.word	lm_pwm0				/* Vector 26: PWM Generator 0 */
-	.word	lm_pwm1				/* Vector 27: PWM Generator 1 */
-	.word	lm_pwm2				/* Vector 28: PWM Generator 2 */
-	.word	lm_qei0				/* Vector 29: QEI0 */
-	.word	lm_adc0				/* Vector 30: ADC Sequence 0 */
-	.word	lm_adc1				/* Vector 31: ADC Sequence 1 */
-	.word	lm_adc2				/* Vector 32: ADC Sequence 2 */
-	.word	lm_adc3				/* Vector 33: ADC Sequence 3 */
-	.word	lm_wdog				/* Vector 34: Watchdog Timer */
-	.word	lm_tmr0a			/* Vector 35: Timer 0 A */
-	.word	lm_tmr0b			/* Vector 36: Timer 0 B */
-	.word	lm_tmr1a			/* Vector 37: Timer 1 A */
-	.word	lm_tmr1b			/* Vector 38: Timer 1 B */
-	.word	lm_tmr2a			/* Vector 39: Timer 2 A */
-	.word	lm_tmr2b			/* Vector 40: Timer 3 B */
-	.word	lm_cmp0				/* Vector 41: Analog Comparator 0 */
-	.word	lm_reserved			/* Vector 42: Reserved */
-	.word	lm_reserved			/* Vector 43: Reserved */
-	.word	lm_syscon			/* Vector 44: System Control */
-	.word	lm_flashcon			/* Vector 45: FLASH Control */
-	.word	lm_gpiof			/* Vector 46: GPIO Port F */
-	.word	lm_gpiog			/* Vector 47: GPIO Port G */
-	.word	lm_reserved			/* Vector 48: Reserved */
-	.word	lm_reserved			/* Vector 49: Reserved */
-	.word	lm_reserved			/* Vector 50: Reserved */
-	.word	lm_tmr3a			/* Vector 51: Timer 3 A */
-	.word	lm_tmr3b			/* Vector 52: Timer 3 B */
-	.word	lm_reserved			/* Vector 53: Reserved*/
-	.word	lm_qei1				/* Vector 54: QEI1 */
-	.word	lm_can0				/* Vector 55: Can Controller */
-	.word	lm_reserved			/* Vector 56: Reserved */
-	.word	lm_reserved			/* Vector 57: Reserved */
- 	.word	lm_eth				/* Vector 58: Ethernet Controller */
-	.word	lm_hib				/* Vector 59: Hibernation Module */
-	.word	lm_reserved			/* Vector 60: Reserved */
-	.word	lm_reserved			/* Vector 61: Reserved */
-	.word	lm_reserved			/* Vector 62: Reserved */
-	.word	lm_reserved			/* Vector 63: Reserved */
-	.word	lm_reserved			/* Vector 64: Reserved */
-	.word	lm_reserved			/* Vector 65: Reserved */
-	.word	lm_reserved			/* Vector 66: Reserved */
-	.word	lm_reserved			/* Vector 67: Reserved */
-	.word	lm_reserved			/* Vector 68: Reserved */
-	.word	lm_reserved			/* Vector 69: Reserved */
-	.word	lm_reserved			/* Vector 70: Reserved */
-#else
-#  error "Vectors not specified for this LM3S chip"
-#endif
+/* External Interrupts */
+
+#undef VECTOR
+#define VECTOR(l,i) .word l
+
+#undef UNUSED
+#define UNUSED(i) .word lm_reserved
+
+#include "chip/chip/lm_vectors.h"
 	.size	lm_vectors, .-lm_vectors
 
 /************************************************************************************
@@ -432,204 +157,13 @@ handlers:
 	HANDLER	lm_pendsv, LM_IRQ_PENDSV			/* Vector 14: Penable system service request */
 	HANDLER	lm_systick, LM_IRQ_SYSTICK			/* Vector 15: System tick */
 
-#if defined(CONFIG_ARCH_CHIP_LM3S6918)
-	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_cmp1, LM_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm_gpioh, LM_IRQ_GPIOH				/* Vector 48: GPIO Port H */
-	HANDLER	lm_ssi1, LM_IRQ_SSI1				/* Vector 50: SSI 1 */
-	HANDLER	lm_tmr3a, LM_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm_tmr3b, LM_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm_i2c1, LM_IRQ_I2C1				/* Vector 53: I2C 1 */
- 	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm_hib, LM_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
-	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_pwm0, LM_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_cmp1, LM_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
- 	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
-	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_pwmfault, LM_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm_pwm0, LM_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm_pwm1, LM_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm_pwm2, LM_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm_qei0, LM_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_cmp1, LM_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm_uart2, LM_IRQ_UART1				/* Vector 49: UART 1 */
-	HANDLER	lm_tmr3a, LM_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm_tmr3b, LM_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm_i2c1, LM_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER lm_qei1, LM_IRQ_QEI1				/* Vector 54: QEI 1 */
- 	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm_hib, LM_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
-	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_pwmfault, LM_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm_pwm0, LM_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm_pwm1, LM_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm_pwm2, LM_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm_qei0, LM_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm_uart2, LM_IRQ_UART1				/* Vector 49: UART 1 */
-	HANDLER	lm_tmr3a, LM_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm_tmr3b, LM_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm_i2c1, LM_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER	lm_qei1, LM_IRQ_QEI1				/* Vector 54: QEI 1 */
-	HANDLER	lm_can0, LM_IRQ_CAN0				/* Vector 55: CAN 0 */
- 	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
-	HANDLER	lm_hib, LM_IRQ_HIBERNATE			/* Vector 59: Hibernation Module */
-#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
-	HANDLER	lm_gpioa, LM_IRQ_GPIOA				/* Vector 16: GPIO Port A */
-	HANDLER	lm_gpiob, LM_IRQ_GPIOB				/* Vector 17: GPIO Port B */
-	HANDLER	lm_gpioc, LM_IRQ_GPIOC				/* Vector 18: GPIO Port C */
-	HANDLER	lm_gpiod, LM_IRQ_GPIOD				/* Vector 19: GPIO Port D */
-	HANDLER	lm_gpioe, LM_IRQ_GPIOE				/* Vector 20: GPIO Port E */
-	HANDLER	lm_uart0, LM_IRQ_UART0				/* Vector 21: UART 0 */
-	HANDLER	lm_uart1, LM_IRQ_UART1				/* Vector 22: UART 1 */
-	HANDLER	lm_ssi0, LM_IRQ_SSI0				/* Vector 23: SSI 0 */
-	HANDLER	lm_i2c0, LM_IRQ_I2C0				/* Vector 24: I2C 0 */
-	HANDLER	lm_pwmfault, LM_IRQ_PWMFAULT		/* Vector 25: PWM Fault */
-	HANDLER	lm_pwm0, LM_IRQ_PWM0				/* Vector 26: PWM Generator 0 */
-	HANDLER	lm_pwm1, LM_IRQ_PWM1				/* Vector 27: PWM Generator 1 */
-	HANDLER	lm_pwm2, LM_IRQ_PWM2				/* Vector 28: PWM Generator 2 */
-	HANDLER	lm_qei0, LM_IRQ_QEI0				/* Vector 29: QEI 0 */
-	HANDLER	lm_adc0, LM_IRQ_ADC0				/* Vector 30: ADC Sequence 0 */
-	HANDLER	lm_adc1, LM_IRQ_ADC1				/* Vector 31: ADC Sequence 1 */
-	HANDLER	lm_adc2, LM_IRQ_ADC2				/* Vector 32: ADC Sequence 2 */
-	HANDLER	lm_adc3, LM_IRQ_ADC3				/* Vector 33: ADC Sequence 3 */
-	HANDLER	lm_wdog, LM_IRQ_WDOG				/* Vector 34: Watchdog Timer */
-	HANDLER	lm_tmr0a, LM_IRQ_TIMER0A			/* Vector 35: Timer 0 A */
-	HANDLER	lm_tmr0b, LM_IRQ_TIMER0B			/* Vector 36: Timer 0 B */
-	HANDLER	lm_tmr1a, LM_IRQ_TIMER1A			/* Vector 37: Timer 1 A */
-	HANDLER	lm_tmr1b, LM_IRQ_TIMER1B			/* Vector 38: Timer 1 B */
-	HANDLER	lm_tmr2a, LM_IRQ_TIMER2A			/* Vector 39: Timer 2 A */
-	HANDLER	lm_tmr2b, LM_IRQ_TIMER2B			/* Vector 40: Timer 3 B */
-	HANDLER	lm_cmp0, LM_IRQ_COMPARE0			/* Vector 41: Analog Comparator 0 */
-	HANDLER	lm_cmp1, LM_IRQ_COMPARE1			/* Vector 42: Analog Comparator 1 */
-	HANDLER	lm_cmp2, LM_IRQ_COMPARE2			/* Vector 43: Analog Comparator 2 */
-	HANDLER	lm_syscon, LM_IRQ_SYSCON			/* Vector 44: System Control */
-	HANDLER	lm_flashcon, LM_IRQ_FLASHCON		/* Vector 45: FLASH Control */
-	HANDLER	lm_gpiof, LM_IRQ_GPIOF				/* Vector 46: GPIO Port F */
-	HANDLER	lm_gpiog, LM_IRQ_GPIOG				/* Vector 47: GPIO Port G */
-	HANDLER	lm_gpioh, LM_IRQ_GPIOH				/* Vector 48: GPIO Port H */
-	HANDLER	lm_uart2, LM_IRQ_UART2				/* Vector 49: UART 2 */
-	HANDLER	lm_ssi1, LM_IRQ_SSI1				/* Vector 50: GPIO Port H */
-	HANDLER	lm_tmr3a, LM_IRQ_TIMER3A			/* Vector 51: Timer 3 A */
-	HANDLER	lm_tmr3b, LM_IRQ_TIMER3B			/* Vector 52: Timer 3 B */
-	HANDLER	lm_i2c1, LM_IRQ_I2C1				/* Vector 53: I2C 1 */
-	HANDLER	lm_qei1, LM_IRQ_QEI1				/* Vector 54: QEI 1 */
- 	HANDLER	lm_can0, LM_IRQ_CAN0				/* Vector 55: CAN 0 */
-	HANDLER	lm_can1, LM_IRQ_CAN1				/* Vector 56: CAN 1 */
-	HANDLER	lm_eth, LM_IRQ_ETHCON				/* Vector 58: Ethernet Controller */
- 	HANDLER	lm_usb, LM_IRQ_USB					/* Vector 60: USB */
- 	HANDLER	lm_pwm3, LM_IRQ_PWM3				/* Vector 61: PWM 3  */
- 	HANDLER	lm_udmasoft, LM_IRQ_UDMASOFT		/* Vector 62: uDMA Software  */
- 	HANDLER	lm_udmaerror, LM_IRQ_UDMAERROR		/* Vector 63: uDMA Error */
- 	HANDLER	lm_adc1_0, LM_IRQ_ADC1_0			/* Vector 64: ADC1 Sequence 0 */
- 	HANDLER	lm_adc1_1, LM_IRQ_ADC1_1			/* Vector 65: ADC1 Sequence 1 */
- 	HANDLER	lm_adc1_2, LM_IRQ_ADC1_2			/* Vector 66: ADC1 Sequence 2 */
- 	HANDLER	lm_adc1_3, LM_IRQ_ADC1_3			/* Vector 67: ADC1 Sequence 3 */
- 	HANDLER	lm_i2s0, LM_IRQ_I2S0				/* Vector 68: I2S 0 */
- 	HANDLER	lm_epi, LM_IRQ_EPI					/* Vector 69: EPI  */
- 	HANDLER	lm_gpioj, LM_IRQ_GPIOJ				/* Vector 70: GPIO Port J */
-#else
-#  error "Vectors not specified for this Stellaris chip"
-#endif
+#undef VECTOR
+#define VECTOR(l,i) HANDLER l, i
+
+#undef UNUSED
+#define UNUSED(i)
+
+#include "chip/chip/lm_vectors.h"
 
 /* Common IRQ handling logic.  On entry here, the return stack is on either
  * the PSP or the MSP and looks like the following:
-- 
cgit v1.2.3


From b26d1e14537568d79c5d805939408ecfca966072 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Fri, 11 Jan 2013 13:30:23 +0000
Subject: Update STM32 F1 DMA to parity with F2/F4

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5509 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/arch/arm/src/stm32/stm32_serial.c    | 121 +++++++++++++++++++----------
 nuttx/arch/arm/src/stm32/stm32_uart.h      |   7 +-
 nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c |  56 ++++++++++---
 nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c |  11 ++-
 4 files changed, 137 insertions(+), 58 deletions(-)

(limited to 'nuttx/arch')

diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c
index c7f97b25a..e86fbcf6f 100644
--- a/nuttx/arch/arm/src/stm32/stm32_serial.c
+++ b/nuttx/arch/arm/src/stm32/stm32_serial.c
@@ -79,22 +79,22 @@
 
 #if SERIAL_HAVE_DMA
 
-/* Verify that DMA has been enabled an the DMA channel has been defined.
- * NOTE:  These assignments may only be true for the F4.
+#  if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+/* Verify that DMA has been enabled and the DMA channel has been defined.
  */
 
-#  if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA)
-#    ifndef CONFIG_STM32_DMA2
-#      error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2
+#    if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA)
+#      ifndef CONFIG_STM32_DMA2
+#        error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2
+#      endif
 #    endif
-#  endif
 
-#  if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \
+#    if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \
       defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA)
-#    ifndef CONFIG_STM32_DMA1
-#      error STM32 USART2/3/4/5 receive DMA requires CONFIG_STM32_DMA1
+#      ifndef CONFIG_STM32_DMA1
+#        error STM32 USART2/3/4/5 receive DMA requires CONFIG_STM32_DMA1
+#      endif
 #    endif
-#  endif
 
 /* Currently RS-485 support cannot be enabled when RXDMA is in use due to lack
  * of testing - RS-485 support was developed on STM32F1x
@@ -114,28 +114,52 @@
  * the following in the board.h file.
  */
 
-#  if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX)
-#    error "USART1 DMA channel not defined (DMAMAP_USART1_RX)"
-#  endif
+#    if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX)
+#      error "USART1 DMA channel not defined (DMAMAP_USART1_RX)"
+#    endif
 
-#  if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX)
-#    error "USART2 DMA channel not defined (DMAMAP_USART2_RX)"
-#  endif
+#    if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX)
+#      error "USART2 DMA channel not defined (DMAMAP_USART2_RX)"
+#    endif
 
-#  if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX)
-#    error "USART3 DMA channel not defined (DMAMAP_USART3_RX)"
-#  endif
+#    if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX)
+#      error "USART3 DMA channel not defined (DMAMAP_USART3_RX)"
+#    endif
 
-#  if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX)
-#    error "UART4 DMA channel not defined (DMAMAP_UART4_RX)"
-#  endif
+#    if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX)
+#      error "UART4 DMA channel not defined (DMAMAP_UART4_RX)"
+#    endif
 
-#  if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX)
-#    error "UART5 DMA channel not defined (DMAMAP_UART5_RX)"
-#  endif
+#    if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX)
+#      error "UART5 DMA channel not defined (DMAMAP_UART5_RX)"
+#    endif
+
+#    if defined(CONFIG_USART6_RXDMA) && !defined(DMAMAP_USART6_RX)
+#      error "USART6 DMA channel not defined (DMAMAP_USART6_RX)"
+#    endif
+
+#  elif defined(CONFIG_STM32_STM32F10XX)
+
+#    if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
+      defined(CONFIG_USART3_RXDMA)
+#      ifndef CONFIG_STM32_DMA1
+#        error STM32 USART1/2/3 receive DMA requires CONFIG_STM32_DMA1
+#      endif
+#    endif
+
+#    if defined(CONFIG_UART4_RXDMA)
+#      ifndef CONFIG_STM32_DMA2
+#        error STM32 USART4 receive DMA requires CONFIG_STM32_DMA2
+#      endif
+#    endif
+
+/* There are no optional DMA channel assignments for the F1 */
+
+#    define DMAMAP_USART1_RX  DMACHAN_USART1_RX
+#    define DMAMAP_USART2_RX  DMACHAN_USART2_RX
+#    define DMAMAP_USART3_RX  DMACHAN_USART3_RX
+#    define DMAMAP_UART4_RX   DMACHAN_USART4_RX
 
-#  if defined(CONFIG_USART6_RXDMA) && !defined(DMAMAP_USART6_RX)
-#    error "USART6 DMA channel not defined (DMAMAP_USART6_RX)"
 #  endif
 
 /* The DMA buffer size when using RX DMA to emulate a FIFO.
@@ -169,6 +193,27 @@
 #    error "Unknown STM32 DMA"
 #  endif
 
+/* DMA control word */
+
+#  if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#    define SERIAL_DMA_CONTROL_WORD      \
+                (DMA_SCR_DIR_P2M       | \
+                 DMA_SCR_CIRC          | \
+                 DMA_SCR_MINC          | \
+                 DMA_SCR_PSIZE_8BITS   | \
+                 DMA_SCR_MSIZE_8BITS   | \
+                 CONFIG_USART_DMAPRIO  | \
+                 DMA_SCR_PBURST_SINGLE | \
+                 DMA_SCR_MBURST_SINGLE)
+#  else
+#    define SERIAL_DMA_CONTROL_WORD      \
+                (DMA_CCR_CIRC          | \
+                 DMA_CCR_MINC          | \
+                 DMA_CCR_PSIZE_8BITS   | \
+                 DMA_CCR_MSIZE_8BITS   | \
+                 CONFIG_USART_DMAPRIO)
+# endif
+
 #endif
 
 /* Power management definitions */
@@ -1056,12 +1101,15 @@ static int up_dma_setup(struct uart_dev_s *dev)
   int result;
   uint32_t regval;
 
-  /* Do the basic UART setup first */
+  /* Do the basic UART setup first, unless we are the console */
 
-  result = up_setup(dev);
-  if (result != OK)
-    {
-      return result;
+  if (!dev->isconsole)
+    {    
+      result = up_setup(dev);
+      if (result != OK)
+        {
+          return result;
+        }
     }
 
   /* Acquire the DMA channel.  This should always succeed. */
@@ -1074,14 +1122,7 @@ static int up_dma_setup(struct uart_dev_s *dev)
                  priv->usartbase + STM32_USART_DR_OFFSET,
                  (uint32_t)priv->rxfifo,
                  RXDMA_BUFFER_SIZE,
-                 DMA_SCR_DIR_P2M       |
-                 DMA_SCR_CIRC          |
-                 DMA_SCR_MINC          |
-                 DMA_SCR_PSIZE_8BITS   |
-                 DMA_SCR_MSIZE_8BITS   |
-                 CONFIG_USART_DMAPRIO  |
-                 DMA_SCR_PBURST_SINGLE |
-                 DMA_SCR_MBURST_SINGLE);
+                 SERIAL_DMA_CONTROL_WORD);
 
   /* Reset our DMA shadow pointer to match the address just
    * programmed above.
diff --git a/nuttx/arch/arm/src/stm32/stm32_uart.h b/nuttx/arch/arm/src/stm32/stm32_uart.h
index 8ff6a9975..a26ea2009 100644
--- a/nuttx/arch/arm/src/stm32/stm32_uart.h
+++ b/nuttx/arch/arm/src/stm32/stm32_uart.h
@@ -140,12 +140,9 @@
 #  undef HAVE_CONSOLE
 #endif
 
-/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration.
- * Furthermore, DMA support is currently only implemented for the F4 (but could be
- * extended to the F1 and F2 with a little effort in the DMA code.
- */
+/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration */
 
-#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) || !defined(CONFIG_STM32_STM32F40XX)
+#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA)
 #  undef CONFIG_USART1_RXDMA
 #  undef CONFIG_USART2_RXDMA
 #  undef CONFIG_USART3_RXDMA
diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c
index 89b279bea..13324b8ac 100644
--- a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c
+++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c
@@ -303,13 +303,13 @@ static int stm32_dmainterrupt(int irq, void *context)
     }
   dmach = &g_dma[chndx];
 
-  /* Get the interrupt status (for this channel only) -- not currently used */
+  /* Get the interrupt status (for this channel only) */
 
   isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan);
 
-  /* Disable the DMA channel */
+  /* Clear the interrupts we are handling */
 
-  stm32_dmachandisable(dmach);
+  dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
 
   /* Invoke the callback */
 
@@ -528,14 +528,34 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
   ccr  = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
   ccr |= DMA_CCR_EN;
 
-  /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
-   * set and an interrupt is generated if the Half-Transfer Interrupt Enable
-   * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
-   * (TCIF) is set and an interrupt is generated if the Transfer Complete
-   * Interrupt Enable bit (TCIE) is set.
+  /* In normal mode, interrupt at either half or full completion. In circular mode,
+   * always interrupt on buffer wrap, and optionally interrupt at the halfway point.
    */
 
-  ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE));
+  if ((ccr & DMA_CCR_CIRC) == 0)
+    {
+      /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
+       * set and an interrupt is generated if the Half-Transfer Interrupt Enable
+       * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
+       * (TCIF) is set and an interrupt is generated if the Transfer Complete
+       * Interrupt Enable bit (TCIE) is set.
+       */
+
+      ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE));
+
+    }
+  else
+    {
+      /* In nonstop mode, when the transfer completes it immediately resets
+       * and starts again.  The transfer-complete interrupt is thus always
+       * enabled, and the half-complete interrupt can be used in circular 
+       * mode to determine when the buffer is half-full, or in double-buffered
+       * mode to determine when one of the two buffers is full.
+       */
+
+      ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE;
+    }
+
   dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr);
 }
 
@@ -558,6 +578,24 @@ void stm32_dmastop(DMA_HANDLE handle)
   stm32_dmachandisable(dmach);
 }
 
+/****************************************************************************
+ * Name: stm32_dmaresidual
+ *
+ * Description:
+ *   Returns the number of bytes remaining to be transferred
+ *
+ * Assumptions:
+ *   - DMA handle allocated by stm32_dmachannel()
+ *
+ ****************************************************************************/
+
+size_t stm32_dmaresidual(DMA_HANDLE handle)
+{
+  struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
+
+  return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET);
+}
+
 /****************************************************************************
  * Name: stm32_dmasample
  *
diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c
index dcbbf1856..40fce8cb5 100644
--- a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c
+++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c
@@ -94,7 +94,6 @@ struct stm32_dma_s
   uint8_t        irq;      /* DMA stream IRQ number */
   uint8_t        shift;    /* ISR/IFCR bit shift value */
   uint8_t        channel;  /* DMA channel number (0-7) */
-  bool           nonstop;  /* Stream is configured in a non-stopping mode. */
   sem_t          sem;      /* Used to wait for DMA channel to become available */
   uint32_t       base;     /* DMA register channel base address */
   dma_callback_t callback; /* Callback invoked when the DMA completes */
@@ -728,7 +727,6 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
               DMA_SCR_DBM|DMA_SCR_CIRC|
               DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
   regval |= scr;
-  dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0;
   dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
 }
 
@@ -764,7 +762,12 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
   scr  = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
   scr |= DMA_SCR_EN;
 
-  if (!dmast->nonstop)
+  /* In normal mode, interrupt at either half or full completion. In circular
+   * and double-buffered modes, always interrupt on buffer wrap, and optionally
+   * interrupt at the halfway point.
+   */
+
+  if ((scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) == 0)
     {
       /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
        * set and an interrupt is generated if the Half-Transfer Interrupt Enable
@@ -777,7 +780,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
     }
   else
     {
-      /* In nonstop mode, when the transfer completes it immediately resets
+      /* In non-stop modes, when the transfer completes it immediately resets
        * and starts again.  The transfer-complete interrupt is thus always
        * enabled, and the half-complete interrupt can be used in circular 
        * mode to determine when the buffer is half-full, or in double-buffered
-- 
cgit v1.2.3


From 87b33d354695294b519f7f6f1275592faf4fee46 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Mon, 14 Jan 2013 22:06:19 +0000
Subject: Configre configs/ubw32/ostest to use kconfig-frontends

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5518 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                                  |   6 +-
 nuttx/arch/Kconfig                               |  18 +
 nuttx/arch/arm/Kconfig                           |   2 +
 nuttx/arch/arm/src/common/up_internal.h          |   4 +-
 nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c |   4 +-
 nuttx/arch/arm/src/kinetis/kinetis_start.c       |   2 +-
 nuttx/arch/mips/Kconfig                          |   2 +
 nuttx/arch/mips/src/common/up_internal.h         |   4 +-
 nuttx/arch/mips/src/pic32mx/Kconfig              |   6 +-
 nuttx/arch/mips/src/pic32mx/pic32mx-head.S       |  21 +-
 nuttx/configs/README.txt                         |   2 +-
 nuttx/configs/kwikstik-k40/ostest/defconfig      |   2 +-
 nuttx/configs/mirtoo/nsh/defconfig               |   6 +-
 nuttx/configs/mirtoo/nxffs/defconfig             |   6 +-
 nuttx/configs/mirtoo/ostest/defconfig            |   6 +-
 nuttx/configs/pcblogic-pic32mx/nsh/defconfig     |  10 +-
 nuttx/configs/pcblogic-pic32mx/ostest/defconfig  |  10 +-
 nuttx/configs/pic32-starterkit/nsh/defconfig     |  10 +-
 nuttx/configs/pic32-starterkit/nsh2/defconfig    |  10 +-
 nuttx/configs/pic32-starterkit/ostest/defconfig  |  10 +-
 nuttx/configs/pic32mx7mmb/nsh/defconfig          |  10 +-
 nuttx/configs/pic32mx7mmb/ostest/defconfig       |  10 +-
 nuttx/configs/sure-pic32mx/nsh/defconfig         |  10 +-
 nuttx/configs/sure-pic32mx/ostest/defconfig      |  10 +-
 nuttx/configs/sure-pic32mx/usbnsh/defconfig      |  10 +-
 nuttx/configs/twr-k60n512/nsh/defconfig          |   2 +-
 nuttx/configs/twr-k60n512/ostest/defconfig       |   2 +-
 nuttx/configs/ubw32/README.txt                   |  27 +-
 nuttx/configs/ubw32/nsh/Make.defs                |   4 +-
 nuttx/configs/ubw32/nsh/defconfig                |  10 +-
 nuttx/configs/ubw32/nsh/ld.script                | 317 --------
 nuttx/configs/ubw32/ostest/Make.defs             |   4 +-
 nuttx/configs/ubw32/ostest/appconfig             |  39 -
 nuttx/configs/ubw32/ostest/defconfig             | 927 +++++++++++++----------
 nuttx/configs/ubw32/ostest/ld.script             | 317 --------
 nuttx/configs/ubw32/scripts/ld.script            | 317 ++++++++
 36 files changed, 945 insertions(+), 1212 deletions(-)
 delete mode 100644 nuttx/configs/ubw32/nsh/ld.script
 delete mode 100644 nuttx/configs/ubw32/ostest/appconfig
 delete mode 100644 nuttx/configs/ubw32/ostest/ld.script
 create mode 100644 nuttx/configs/ubw32/scripts/ld.script

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 4ba0fe985..41ac95db0 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3948,4 +3948,8 @@
 	* sched/sig_timedwait.c:  sigtimedwait() would return a bad signal
 	  number if the signal was already pending when the function was
 	  called.
-	  called.
+	* configs/ubw32/scripts:  All common linker scripts moved to this
+	  scripts sub-directory
+	* configs/ubw32/ostest:  Configuration configured to use the
+	  kconfig-frontends tools.
+
diff --git a/nuttx/arch/Kconfig b/nuttx/arch/Kconfig
index 7d34b56f4..d43137adb 100644
--- a/nuttx/arch/Kconfig
+++ b/nuttx/arch/Kconfig
@@ -109,6 +109,10 @@ config ARCH_NOINTC
 	bool
 	default n
 
+config ARCH_VECNOTIRQ
+	bool
+	default n
+
 config ARCH_DMA
 	bool
 	default n
@@ -141,6 +145,20 @@ config ENDIAN_BIG
 	---help---
 		Select if architecture operates using big-endian byte ordering.
 
+config ARCH_HAVE_RAMFUNCS
+	bool
+	default n
+
+config ARCH_RAMFUNCS
+	bool "Copy functions to RAM on startup"
+	default n
+	depends on ARCH_HAVE_RAMFUNCS
+	---help---
+		Copy some functions to RAM at boot time.  This is done in some
+		architectures to improve performance.  In other cases, it is done
+		so that FLASH can be reconfigured while the MCU executes out of
+		SRAM.
+
 comment "Board Settings"
 
 config BOARD_LOOPSPERMSEC
diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig
index bc7634695..36343e319 100644
--- a/nuttx/arch/arm/Kconfig
+++ b/nuttx/arch/arm/Kconfig
@@ -47,6 +47,8 @@ config ARCH_CHIP_KINETIS
 	select ARCH_CORTEXM4
 	select ARCH_HAVE_MPU
 	select ARCH_IRQPRIO
+	select ARCH_HAVE_RAMFUNCS
+	select ARCH_RAMFUNCS
 	---help---
 		Freescale Kinetis Architectures (ARM Cortex-M4)
 
diff --git a/nuttx/arch/arm/src/common/up_internal.h b/nuttx/arch/arm/src/common/up_internal.h
index 0d3c5b1f2..55071345f 100644
--- a/nuttx/arch/arm/src/common/up_internal.h
+++ b/nuttx/arch/arm/src/common/up_internal.h
@@ -188,7 +188,7 @@ extern uint32_t _ebss;            /* End+1 of .bss */
  * will create a function named foo that will execute from RAM.
  */
  
-#ifdef CONFIG_BOOT_RAMFUNCS
+#ifdef CONFIG_ARCH_RAMFUNCS
 
 #  define __ramfunc__ __attribute__ ((section(".ramfunc")))
 
@@ -204,7 +204,7 @@ extern const uint32_t _framfuncs; /* Copy source address in FLASH */
 extern uint32_t _sramfuncs;       /* Copy destination start address in RAM */
 extern uint32_t _eramfuncs;       /* Copy destination start address in RAM */
 
-#endif /* CONFIG_BOOT_RAMFUNCS */
+#endif /* CONFIG_ARCH_RAMFUNCS */
 #endif /* __ASSEMBLY__ */
 
 /****************************************************************************
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c b/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c
index 31ea235d2..ad6e42884 100644
--- a/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c
+++ b/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c
@@ -55,8 +55,8 @@
  * Private Definitions
  ****************************************************************************/
 
-#ifndef CONFIG_BOOT_RAMFUNCS
-# error "CONFIG_BOOT_RAMFUNCS must be defined for this logic"
+#ifndef CONFIG_ARCH_RAMFUNCS
+# error "CONFIG_ARCH_RAMFUNCS must be defined for this logic"
 #endif
 
 /****************************************************************************
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_start.c b/nuttx/arch/arm/src/kinetis/kinetis_start.c
index c8f20fbdd..2f73cb2e6 100644
--- a/nuttx/arch/arm/src/kinetis/kinetis_start.c
+++ b/nuttx/arch/arm/src/kinetis/kinetis_start.c
@@ -116,7 +116,7 @@ void __start(void)
    * at _framfuncs
    */
 
-#ifdef CONFIG_BOOT_RAMFUNCS
+#ifdef CONFIG_ARCH_RAMFUNCS
   for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; )
     {
       *dest++ = *src++;
diff --git a/nuttx/arch/mips/Kconfig b/nuttx/arch/mips/Kconfig
index 772b6f663..1b10e26ae 100644
--- a/nuttx/arch/mips/Kconfig
+++ b/nuttx/arch/mips/Kconfig
@@ -12,6 +12,8 @@ config ARCH_CHIP_PIC32MX
 	bool "PIC32MX"
 	select ARCH_MIPS32
 	select ARCH_IRQPRIO
+	select ARCH_VECNOTIRQ
+	select ARCH_HAVE_RAMFUNCS
 	---help---
 		Microchip PIC32MX320F032H (MIPS32)
 
diff --git a/nuttx/arch/mips/src/common/up_internal.h b/nuttx/arch/mips/src/common/up_internal.h
index 0eb1ed6a0..b284961b0 100644
--- a/nuttx/arch/mips/src/common/up_internal.h
+++ b/nuttx/arch/mips/src/common/up_internal.h
@@ -152,7 +152,7 @@ extern uint32_t _sdata;             /* Start of .data */
 extern uint32_t _edata;             /* End+1 of .data */
 extern uint32_t _sbss;              /* Start of .bss */
 extern uint32_t _ebss;              /* End+1 of .bss */
-#ifdef CONFIG_PIC32MX_RAMFUNCS
+#ifdef CONFIG_ARCH_RAMFUNCS
 extern uint32_t _sramfunc;          /* Start of ramfuncs */
 extern uint32_t _eramfunc;          /* End+1 of ramfuncs */
 extern uint32_t _ramfunc_loadaddr;  /* Start of ramfuncs in FLASH */
@@ -160,7 +160,7 @@ extern uint32_t _ramfunc_sizeof;    /* Size of ramfuncs */
 extern uint32_t _bmxdkpba_address;  /* BMX register setting */
 extern uint32_t _bmxdudba_address;  /* BMX register setting */
 extern uint32_t _bmxdupba_address;  /* BMX register setting */
-#endif /* CONFIG_PIC32MX_RAMFUNCS */
+#endif /* CONFIG_ARCH_RAMFUNCS */
 #endif /* __ASSEMBLY__ */
 
 /****************************************************************************
diff --git a/nuttx/arch/mips/src/pic32mx/Kconfig b/nuttx/arch/mips/src/pic32mx/Kconfig
index bcb99cf6d..6ac10608b 100644
--- a/nuttx/arch/mips/src/pic32mx/Kconfig
+++ b/nuttx/arch/mips/src/pic32mx/Kconfig
@@ -533,10 +533,14 @@ config PIC32MX_CM1
 	bool "Comparator 1 (CM1)"
 	default n
 
-config PIC32MX_CM2 
+config PIC32MX_CM2
 	bool "Comparator 2 (CM2)"
 	default n
 
+config PIC32MX_CM3
+	bool "Comparator 3 (CM3)"
+	default n
+
 config PIC32MX_RTCC
 	bool "Real-Time Clock and Calendar (RTCC)"
 	default n
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-head.S b/nuttx/arch/mips/src/pic32mx/pic32mx-head.S
index 7224ee122..2e1a34080 100644
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-head.S
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-head.S
@@ -367,7 +367,7 @@ __start:
 	 * initializing bus matrix registers.
 	 */
 
-#ifdef CONFIG_PIC32MX_RAMFUNCS
+#ifdef CONFIG_ARCH_RAMFUNCS
 	la		t1, _ramfunc_sizeof
 	beqz	t1, .Lnoramfuncs
 	nop
@@ -598,17 +598,26 @@ halt:
 devconfig:
 devconfig3:
 #if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
+
 	.long	CONFIG_PIC32MX_USERID  << DEVCFG3_USERID_SHIFT | \
 			CONFIG_PIC32MX_PMDL1WAY << 28 | CONFIG_PIC32MX_IOL1WAY << 29 | \
 			CONFIG_PIC32MX_USBIDO  << 30 | CONFIG_PIC32MX_VBUSIO  << 31 | \
 			DEVCFG3_UNUSED
-#else
+
+#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
+
+	.long	CONFIG_PIC32MX_USERID  << DEVCFG3_USERID_SHIFT | \
+			DEVCFG3_UNUSED
+
+#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+
 	.long	CONFIG_PIC32MX_USERID  << DEVCFG3_USERID_SHIFT | \
 			CONFIG_PIC32MX_SRSSEL  << DEVCFG3_FSRSSEL_SHIFT | \
 			CONFIG_PIC32MX_FMIIEN  << 24 | CONFIG_PIC32MX_FETHIO  << 25 | \
 			CONFIG_PIC32MX_FCANIO  << 26 | CONFIG_PIC32MX_FSCM1IO << 29 | \
 			CONFIG_PIC32MX_USBIDO  << 30 | CONFIG_PIC32MX_VBUSIO  << 31 | \
 			DEVCFG3_UNUSED
+
 #endif
 
 devconfig2:
@@ -618,22 +627,27 @@ devconfig2:
 
 devconfig1:
 #if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
+
 	.long	CONFIG_PIC32MX_FNOSC    | CONFIG_PIC32MX_FSOSCEN  | \
 			CONFIG_PIC32MX_IESO     | CONFIG_PIC32MX_POSCMOD  | \
 			CONFIG_PIC32MX_OSCOUT << 10 | \
 			CONFIG_PIC32MX_PBDIV    | CONFIG_PIC32MX_FCKSM    | \
 			DEVCFG1_WINDIS          | CONFIG_PIC32MX_WDENABLE | \
 			DEVCFG1_FWDTWINSZ_75    | DEVCFG1_UNUSED
+
 #else
+
 	.long	CONFIG_PIC32MX_FNOSC    | CONFIG_PIC32MX_FSOSCEN | \
 			CONFIG_PIC32MX_IESO     | CONFIG_PIC32MX_POSCMOD | \
 			CONFIG_PIC32MX_OSCOUT << 10 | \
 			CONFIG_PIC32MX_PBDIV    | CONFIG_PIC32MX_FCKSM   | \
 			CONFIG_PIC32MX_WDENABLE | DEVCFG1_UNUSED
+
 #endif
 
 devconfig0:
 #if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
+
 	.long	CONFIG_PIC32MX_DEBUGGER    << DEVCFG0_DEBUG_SHIFT | \
 			DEVCFG0_JTAGEN | \
 			CONFIG_PIC32MX_ICESEL      << DEVCFG0_ICESEL_SHIFT | \
@@ -641,13 +655,16 @@ devconfig0:
 			CONFIG_PIC32MX_BOOTFLASHWP << 24 | \
 			CONFIG_PIC32MX_CODEWP      << 28 | \
 			DEVCFG0_UNUSED
+
 #else
+
 	.long	CONFIG_PIC32MX_DEBUGGER    << DEVCFG0_DEBUG_SHIFT | \
 			CONFIG_PIC32MX_ICESEL      << 3 | \
 			CONFIG_PIC32MX_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \
 			CONFIG_PIC32MX_BOOTFLASHWP << 24 | \
 			CONFIG_PIC32MX_CODEWP      << 28 | \
 			DEVCFG0_UNUSED
+
 #endif
 	.size	devconfig, .-devconfig
 
diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt
index 4800f02ee..babdf7330 100644
--- a/nuttx/configs/README.txt
+++ b/nuttx/configs/README.txt
@@ -1590,7 +1590,7 @@ defconfig -- This is a configuration file similar to the Linux
       operation from FLASH but must copy initialized .data sections to RAM.
     CONFIG_BOOT_COPYTORAM -  Some configurations boot in FLASH
       but copy themselves entirely into RAM for better performance.
-    CONFIG_BOOT_RAMFUNCS - Other configurations may copy just some functions
+    CONFIG_ARCH_RAMFUNCS - Other configurations may copy just some functions
       into RAM, either for better performance or for errata workarounds.
     CONFIG_STACK_ALIGNMENT - Set if the your application has specific
       stack alignment requirements (may not be supported
diff --git a/nuttx/configs/kwikstik-k40/ostest/defconfig b/nuttx/configs/kwikstik-k40/ostest/defconfig
index 5f0291ced..ff8c39c1f 100755
--- a/nuttx/configs/kwikstik-k40/ostest/defconfig
+++ b/nuttx/configs/kwikstik-k40/ostest/defconfig
@@ -460,7 +460,7 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
 #
 CONFIG_BOOT_RUNFROMFLASH=n
 CONFIG_BOOT_COPYTORAM=n
-CONFIG_BOOT_RAMFUNCS=y
+CONFIG_ARCH_RAMFUNCS=y
 CONFIG_CUSTOM_STACK=n
 CONFIG_IDLETHREAD_STACKSIZE=1024
 CONFIG_USERMAIN_STACKSIZE=2048
diff --git a/nuttx/configs/mirtoo/nsh/defconfig b/nuttx/configs/mirtoo/nsh/defconfig
index 94a6b8b17..6e0d3bf70 100644
--- a/nuttx/configs/mirtoo/nsh/defconfig
+++ b/nuttx/configs/mirtoo/nsh/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in linker scripts as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -105,7 +105,6 @@ CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
 CONFIG_PIC32MX_CM3=n
 CONFIG_PIC32MX_RTCC=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -113,9 +112,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=n
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
 
 #
 # Mirtoo Board Settings
diff --git a/nuttx/configs/mirtoo/nxffs/defconfig b/nuttx/configs/mirtoo/nxffs/defconfig
index d633e56d9..ed50e0325 100644
--- a/nuttx/configs/mirtoo/nxffs/defconfig
+++ b/nuttx/configs/mirtoo/nxffs/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in linker scripts as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -105,7 +105,6 @@ CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
 CONFIG_PIC32MX_CM3=n
 CONFIG_PIC32MX_RTCC=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -113,9 +112,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=n
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
 
 #
 # Mirtoo Board Settings
diff --git a/nuttx/configs/mirtoo/ostest/defconfig b/nuttx/configs/mirtoo/ostest/defconfig
index 471dab444..5c8b69785 100644
--- a/nuttx/configs/mirtoo/ostest/defconfig
+++ b/nuttx/configs/mirtoo/ostest/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in linker scripts as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -105,7 +105,6 @@ CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
 CONFIG_PIC32MX_CM3=n
 CONFIG_PIC32MX_RTCC=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -113,9 +112,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=n
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig
index 7bce554ac..6f1ef7dc9 100644
--- a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig
+++ b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -102,7 +102,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -110,13 +109,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=n
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig
index 730b8134a..1df428f8a 100644
--- a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig
+++ b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -102,7 +102,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -110,13 +109,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=n
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/pic32-starterkit/nsh/defconfig b/nuttx/configs/pic32-starterkit/nsh/defconfig
index 32220d89b..f1c543e5f 100644
--- a/nuttx/configs/pic32-starterkit/nsh/defconfig
+++ b/nuttx/configs/pic32-starterkit/nsh/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n
 CONFIG_PIC32MX_CAN1=n
 CONFIG_PIC32MX_CAN2=n
 CONFIG_PIC32MX_ETHERNET=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/pic32-starterkit/nsh2/defconfig b/nuttx/configs/pic32-starterkit/nsh2/defconfig
index a7a1ff18a..f681b7689 100644
--- a/nuttx/configs/pic32-starterkit/nsh2/defconfig
+++ b/nuttx/configs/pic32-starterkit/nsh2/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n
 CONFIG_PIC32MX_CAN1=n
 CONFIG_PIC32MX_CAN2=n
 CONFIG_PIC32MX_ETHERNET=y
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/pic32-starterkit/ostest/defconfig b/nuttx/configs/pic32-starterkit/ostest/defconfig
index 3a55de491..6a077f209 100644
--- a/nuttx/configs/pic32-starterkit/ostest/defconfig
+++ b/nuttx/configs/pic32-starterkit/ostest/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n
 CONFIG_PIC32MX_CAN1=n
 CONFIG_PIC32MX_CAN2=n
 CONFIG_PIC32MX_ETHERNET=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/pic32mx7mmb/nsh/defconfig b/nuttx/configs/pic32mx7mmb/nsh/defconfig
index d39f8bc40..66cd240e2 100644
--- a/nuttx/configs/pic32mx7mmb/nsh/defconfig
+++ b/nuttx/configs/pic32mx7mmb/nsh/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n
 CONFIG_PIC32MX_CAN1=n
 CONFIG_PIC32MX_CAN2=n
 CONFIG_PIC32MX_ETHERNET=y
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/pic32mx7mmb/ostest/defconfig b/nuttx/configs/pic32mx7mmb/ostest/defconfig
index b3cecf98d..7cb71995e 100644
--- a/nuttx/configs/pic32mx7mmb/ostest/defconfig
+++ b/nuttx/configs/pic32mx7mmb/ostest/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n
 CONFIG_PIC32MX_CAN1=n
 CONFIG_PIC32MX_CAN2=n
 CONFIG_PIC32MX_ETHERNET=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/sure-pic32mx/nsh/defconfig b/nuttx/configs/sure-pic32mx/nsh/defconfig
index 60c4dc53d..07b31a1ae 100644
--- a/nuttx/configs/sure-pic32mx/nsh/defconfig
+++ b/nuttx/configs/sure-pic32mx/nsh/defconfig
@@ -62,7 +62,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -103,7 +103,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -111,13 +110,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=n
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/sure-pic32mx/ostest/defconfig b/nuttx/configs/sure-pic32mx/ostest/defconfig
index 1bca11c47..86bb3b307 100644
--- a/nuttx/configs/sure-pic32mx/ostest/defconfig
+++ b/nuttx/configs/sure-pic32mx/ostest/defconfig
@@ -62,7 +62,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -103,7 +103,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -111,13 +110,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=n
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/sure-pic32mx/usbnsh/defconfig b/nuttx/configs/sure-pic32mx/usbnsh/defconfig
index 978e16541..9f6046f21 100644
--- a/nuttx/configs/sure-pic32mx/usbnsh/defconfig
+++ b/nuttx/configs/sure-pic32mx/usbnsh/defconfig
@@ -62,7 +62,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -103,7 +103,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -111,13 +110,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=y
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/twr-k60n512/nsh/defconfig b/nuttx/configs/twr-k60n512/nsh/defconfig
index 7a4bb3b3a..3f272b55a 100644
--- a/nuttx/configs/twr-k60n512/nsh/defconfig
+++ b/nuttx/configs/twr-k60n512/nsh/defconfig
@@ -462,7 +462,7 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
 #
 CONFIG_BOOT_RUNFROMFLASH=n
 CONFIG_BOOT_COPYTORAM=n
-CONFIG_BOOT_RAMFUNCS=y
+CONFIG_ARCH_RAMFUNCS=y
 CONFIG_CUSTOM_STACK=n
 CONFIG_IDLETHREAD_STACKSIZE=1024
 CONFIG_USERMAIN_STACKSIZE=2048
diff --git a/nuttx/configs/twr-k60n512/ostest/defconfig b/nuttx/configs/twr-k60n512/ostest/defconfig
index 355e5773b..fd27ffc2b 100644
--- a/nuttx/configs/twr-k60n512/ostest/defconfig
+++ b/nuttx/configs/twr-k60n512/ostest/defconfig
@@ -459,7 +459,7 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
 #
 CONFIG_BOOT_RUNFROMFLASH=n
 CONFIG_BOOT_COPYTORAM=n
-CONFIG_BOOT_RAMFUNCS=y
+CONFIG_ARCH_RAMFUNCS=y
 CONFIG_CUSTOM_STACK=n
 CONFIG_IDLETHREAD_STACKSIZE=1024
 CONFIG_USERMAIN_STACKSIZE=2048
diff --git a/nuttx/configs/ubw32/README.txt b/nuttx/configs/ubw32/README.txt
index 801be39a9..63cb1bb54 100644
--- a/nuttx/configs/ubw32/README.txt
+++ b/nuttx/configs/ubw32/README.txt
@@ -586,15 +586,26 @@ Where <subdir> is one of the following:
     This configuration directory, performs a simple OS test using
     apps/examples/ostest.
 
-    Serial Output.
-    --------------
-    The OS test produces all of its test output on the serial console.
-    This configuration has UART1 enabled as a serial console. 
+    NOTES:
+    ------ 
+    1. This configuration uses the mconf-based configuration tool.  To
+       change this configuration using that tool, you should:
 
-    TX  -- J4 pin 31: U1TX/RF8
-    RX  -- J4 pin 30: U1RX/RF2
-    GND -- J4 pin 40: GND
-    Vcc -- J4 pin 39: 5V
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
+
+       b. Execute 'make menuconfig' in nuttx/ in order to start the
+          reconfiguration process.
+
+    2. Serial Output.
+
+       The OS test produces all of its test output on the serial console.
+       This configuration has UART1 enabled as a serial console. 
+
+       TX  -- J4 pin 31: U1TX/RF8
+       RX  -- J4 pin 30: U1RX/RF2
+       GND -- J4 pin 40: GND
+       Vcc -- J4 pin 39: 5V
  
   nsh:
   ====
diff --git a/nuttx/configs/ubw32/nsh/Make.defs b/nuttx/configs/ubw32/nsh/Make.defs
index ae0e44ae4..f393bbfdf 100644
--- a/nuttx/configs/ubw32/nsh/Make.defs
+++ b/nuttx/configs/ubw32/nsh/Make.defs
@@ -44,13 +44,13 @@ ifeq ($(WINTOOL),y)
   MKDEP = $(TOPDIR)/tools/mknulldeps.sh
   ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
   ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
-  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/nsh/ld.script}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}"
 else
   # Linux/Cygwin-native toolchain 
   MKDEP = $(TOPDIR)/tools/mkdeps.sh
   ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
   ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
-  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/nsh/ld.script
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script
 endif
 
 CC = $(CROSSDEV)gcc
diff --git a/nuttx/configs/ubw32/nsh/defconfig b/nuttx/configs/ubw32/nsh/defconfig
index ad18c12b6..89afd5912 100644
--- a/nuttx/configs/ubw32/nsh/defconfig
+++ b/nuttx/configs/ubw32/nsh/defconfig
@@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n
 # Enable support for RAM-based functions
 # (If selected, then modifications are needed in ld.script as well)
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+CONFIG_ARCH_RAMFUNCS=n
 
 #
 # Identify toolchain and linker options
@@ -102,7 +102,6 @@ CONFIG_PIC32MX_ADC=n
 CONFIG_PIC32MX_CVR=n
 CONFIG_PIC32MX_CM1=n
 CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
 CONFIG_PIC32MX_DDP=n
 CONFIG_PIC32MX_FLASH=n
 CONFIG_PIC32MX_BMX=n
@@ -110,13 +109,6 @@ CONFIG_PIC32MX_DMA=n
 CONFIG_PIC32MX_CHE=n
 CONFIG_PIC32MX_USBDEV=n
 CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
 
 #
 # PIC32MX Configuration Settings
diff --git a/nuttx/configs/ubw32/nsh/ld.script b/nuttx/configs/ubw32/nsh/ld.script
deleted file mode 100644
index 43e64a51b..000000000
--- a/nuttx/configs/ubw32/nsh/ld.script
+++ /dev/null
@@ -1,317 +0,0 @@
-/****************************************************************************
- * configs/ubw32/nsh/ld.script
- *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *	notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *	notice, this list of conditions and the following disclaimer in
- *	the documentation and/or other materials provided with the
- *	distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *	used to endorse or promote products derived from this software
- *	without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-/* Memory Regions ***********************************************************/
-
-MEMORY
-{
-	/* The PIC32MX460F512L has 512Kb of program FLASH at physical address
-	 * 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000
-	 */
-
-	kseg0_progmem  (rx) : ORIGIN = 0x9d000000, LENGTH = 512K
-
-	/* The PIC32MX460F512L has 12Kb of boot FLASH at physical address
-	 * 0x1fc00000.  The initial reset vector is in KSEG1, but all other
-	 * accesses are in KSEG0.
-	 *
-	 *   REGION        PHYSICAL   KSEG   SIZE
-	 *   DESCRIPTION   START ADDR        (BYTES)
-	 *   ------------- ---------- ------ ----------------------
-	 *   Exceptions:*
-	 *     Reset       0x1fc00000 KSEG1  512         512
-	 *     TLB Refill  0x1fc00200 KSEG1  256         768
-	 *     Cache Error 0x1fc00300 KSEG1  128         896
-	 *     Others      0x1fc00380 KSEG1  128        1024 (1Kb)
-	 *     Interrupt   0x1fc00400 KSEG1  128        1152
-	 *     JTAG        0x1fc00480 KSEG1  16         1168
-	 *   Exceptions    0x1fc00490 KSEG0  8192-1168  8192 (4Kb)
-	 *   Debug code    0x1fc02000 KSEG1  4096-16   12272
-	 *   DEVCFG3-0     0x1fc02ff0 KSEG1  16        12288 (12Kb)
-	 *
-	 * Exceptions assume:
-	 *
-	 *   STATUS: BEV=0/1 and EXL=0
-	 *   CAUSE:  IV=1
-	 *   JTAG:   ProbEn=0
-	 *   And multi-vector support disabled
-	 */
-
-	kseg1_reset    (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
-	kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
-	kseg1_ebexcpt  (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
-	kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
-	kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
-	kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
-	kseg0_bootmem  (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
-	kseg1_dbgcode  (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
-	kseg1_devcfg    (r) : ORIGIN = 0xbfc02ff0, LENGTH = 16
-
-	/* The PIC32MX460F512L has 32Kb of data memory at physical address
-	 * 0x00000000.  Since the PIC32MX has no data cache, this memory is
-	 * always accessed through KSEG1.
-	 *
-	 * When used with MPLAB, we need to set aside 512 bytes of memory
-	 * for use by MPLAB.
-	 */
-
-	kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512
-}
-
-OUTPUT_FORMAT("elf32-tradlittlemips")
-OUTPUT_ARCH(pic32mx)
-ENTRY(__start)
-
-SECTIONS
-{
-	/* Boot FLASH sections */
-
-	.reset :
-	{
-		KEEP (*(.reset))
-	} > kseg1_reset
-
-	/* Exception handlers.  The following is assumed:
-	 *
-	 *   STATUS: BEV=1 and EXL=0
-	 *   CAUSE:  IV=1
-	 *   JTAG:   ProbEn=0
-	 *   And multi-vector support disabled
-	 *
-	 * In that configuration, the vector locations become:
-	 *
-	 *   Reset, Soft Reset  bfc0:0000
-	 *   TLB Refill         bfc0:0200
-	 *   Cache Error        bfc0:0300
-	 *   All others         bfc0:0380
-	 *   Interrupt          bfc0:0400
-	 *   EJTAG Debug        bfc0:0480
-	 */
-
-	 /* KSEG1 exception handler "trampolines" */
-
-	.gen_excpt :
-	{
-		KEEP (*(.gen_excpt))
-	} > kseg1_genexcpt
-
-	.ebase_excpt :
-	{
-		KEEP (*(.ebase_excpt))
-	} > kseg1_ebexcpt
-
-	.bev_excpt :
-	{
-		KEEP (*(.bev_excpt))
-	} > kseg1_bevexcpt
-
-	.int_excpt :
-	{
-		KEEP (*(.int_excpt))
-	} > kseg1_intexcpt
-
-	.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
-
-	.start :
-	{
-		/* KSEG0 Reset startup logic */
-
-		*(.start)
-
-		/* KSEG0 exception handlers */
-
-		*(.nmi_handler)
-		*(.bev_handler)
-		*(.int_handler)
-	} > kseg0_bootmem
-
-	.dbg_code = ORIGIN(kseg1_dbgcode);
-
-	.devcfg :
-	{
-		KEEP (*(.devcfg))
-	} > kseg1_devcfg
-
-	/* Program FLASH sections */
-
-	.text :
-	{
-		_stext = ABSOLUTE(.);
-		*(.text .text.*)
-		*(.stub)
-		KEEP (*(.text.*personality*))
-		*(.gnu.linkonce.t.*)
-		*(.gnu.warning)
-		*(.mips16.fn.*)
-		*(.mips16.call.*)
-
-		/* Read-only data is included in the text section */
-
-		*(.rodata .rodata.*)
-		*(.rodata1)
-		*(.gnu.linkonce.r.*)
-
-		/* Small initialized constant global and static data */
-
-		*(.sdata2 .sdata2.*)
-		*(.gnu.linkonce.s2.*)
-
-		/* Uninitialized constant global and static data */
-
-		*(.sbss2 .sbss2.*)
-		*(.gnu.linkonce.sb2.*)
-		_etext = ABSOLUTE(.);
-	} > kseg0_progmem
-
-	/* Initialization data begins here in progmem */
-
-	_data_loaddr = LOADADDR(.data);
-
-	.eh_frame_hdr : { *(.eh_frame_hdr) }
-	.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
-
-	/* RAM functions are positioned at the beginning of RAM so that
-	 * they can be guaranteed to satisfy the 2Kb alignment requirement.
-	 */
-
-/* This causes failures if there are no RAM functions
-	.ramfunc ALIGN(2K) :
-	{
-		_sramfunc =  ABSOLUTE(.);
-		*(.ramfunc	.ramfunc.*)
-		_eramfunc =  ABSOLUTE(.);
-	} > kseg1_datamem AT > kseg0_progmem
-
-	_ramfunc_loadaddr = LOADADDR(.ramfunc);
-	_ramfunc_sizeof   = SIZEOF(.ramfunc);
-	_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
-	_bmxdudba_address = LENGTH(kseg1_datamem) ;
-	_bmxdupba_address = LENGTH(kseg1_datamem) ;
-*/
-
-	.data :
-	{
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		KEEP (*(.gnu.linkonce.d.*personality*))
-		*(.data1)
-	} > kseg1_datamem AT > kseg0_progmem
-
-	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
-	_gp = ALIGN(16) + 0x7FF0 ;
-
-	.got :
-	{
-		*(.got.plt) *(.got)
-	} > kseg1_datamem AT > kseg0_progmem
-
-	.sdata :
-	{
-		*(.sdata .sdata.* .gnu.linkonce.s.*)
-	} > kseg1_datamem AT > kseg0_progmem
-
-	.lit8 :
-	{
-		*(.lit8)
-	} > kseg1_datamem AT > kseg0_progmem
-
-	.lit4 :
-	{
-		*(.lit4)
-		_edata = ABSOLUTE(.);
-	} >kseg1_datamem AT>kseg0_progmem
-
-	.sbss :
-	{
-		_sbss = ABSOLUTE(.);
-		*(.dynsbss)
-		*(.sbss .sbss.* .gnu.linkonce.sb.*)
-		*(.scommon)
-	} >kseg1_datamem
-
-	.bss :
-	{
-		*(.dynbss)
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > kseg1_datamem
-
-	/* Stabs debugging sections */
-
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-
-	/* DWARF debug sections */
-	/* DWARF 1 */
-
-	.debug 0 : { *(.debug) }
-	.line 0 : { *(.line) }
-
-	/* GNU DWARF 1 extensions */
-
-	.debug_srcinfo 0 : { *(.debug_srcinfo) }
-	.debug_sfnames 0 : { *(.debug_sfnames) }
-
-	/* DWARF 1.1 and DWARF 2 */
-
-	.debug_aranges 0 : { *(.debug_aranges) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-
-	/* DWARF 2 */
-
-	.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_frame 0 : { *(.debug_frame) }
-	.debug_str 0 : { *(.debug_str) }
-	.debug_loc 0 : { *(.debug_loc) }
-	.debug_macinfo 0 : { *(.debug_macinfo) }
-
-	/* SGI/MIPS DWARF 2 extensions */
-
-	.debug_weaknames 0 : { *(.debug_weaknames) }
-	.debug_funcnames 0 : { *(.debug_funcnames) }
-	.debug_typenames 0 : { *(.debug_typenames) }
-	.debug_varnames 0 : { *(.debug_varnames) }
-
-	/DISCARD/ : { *(.note.GNU-stack) }
-}
diff --git a/nuttx/configs/ubw32/ostest/Make.defs b/nuttx/configs/ubw32/ostest/Make.defs
index 54276acf7..b46589913 100644
--- a/nuttx/configs/ubw32/ostest/Make.defs
+++ b/nuttx/configs/ubw32/ostest/Make.defs
@@ -44,13 +44,13 @@ ifeq ($(WINTOOL),y)
   MKDEP = $(TOPDIR)/tools/mknulldeps.sh
   ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
   ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
-  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}"
 else
   # Linux/Cygwin-native toolchain 
   MKDEP = $(TOPDIR)/tools/mkdeps.sh
   ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
   ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
-  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script
 endif
 
 CC = $(CROSSDEV)gcc
diff --git a/nuttx/configs/ubw32/ostest/appconfig b/nuttx/configs/ubw32/ostest/appconfig
deleted file mode 100644
index 6278529fa..000000000
--- a/nuttx/configs/ubw32/ostest/appconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-############################################################################
-# configs/ubw32/ostest/appconfig
-#
-#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-# Path to example in apps/examples containing the user_start entry point
-
-CONFIGURED_APPS += examples/ostest
-
diff --git a/nuttx/configs/ubw32/ostest/defconfig b/nuttx/configs/ubw32/ostest/defconfig
index 60322d4f6..3a387ab99 100644
--- a/nuttx/configs/ubw32/ostest/defconfig
+++ b/nuttx/configs/ubw32/ostest/defconfig
@@ -1,249 +1,334 @@
-############################################################################
-# configs/ubw32/ostest/defconfig
-#
-#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-#
-# Architecture Selection
 #
-CONFIG_ARCH="mips"
-CONFIG_ARCH_MIPS=y
-CONFIG_ARCH_MIPS32=y
-CONFIG_ARCH_CHIP="pic32mx"
-CONFIG_ARCH_CHIP_PIC32MX460F512L=y
-CONFIG_ARCH_BOARD="ubw32"
-CONFIG_ARCH_BOARD_UBW32=y
-CONFIG_BOARD_LOOPSPERMSEC=8079
-CONFIG_DRAM_SIZE=32768
-CONFIG_DRAM_START=0xa0000000
-CONFIG_ARCH_NOINTC=n
-CONFIG_ARCH_VECNOTIRQ=y
-CONFIG_ARCH_IRQPRIO=y
-CONFIG_ARCH_INTERRUPTSTACK=0
-CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARCH_BOOTLOADER=n
-CONFIG_ARCH_LEDS=y
-CONFIG_ARCH_BUTTONS=n
-CONFIG_ARCH_CALIBRATION=n
-CONFIG_ARCH_DMA=n
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+CONFIG_NUTTX_NEWCONFIG=y
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+# CONFIG_HOST_LINUX is not set
+# CONFIG_HOST_OSX is not set
+CONFIG_HOST_WINDOWS=y
+# CONFIG_HOST_OTHER is not set
+# CONFIG_WINDOWS_NATIVE is not set
+CONFIG_WINDOWS_CYGWIN=y
+# CONFIG_WINDOWS_MSYS is not set
+# CONFIG_WINDOWS_OTHER is not set
+
+#
+# Build Configuration
+#
+# CONFIG_APPS_DIR="../apps"
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+CONFIG_INTELHEX_BINARY=y
+# CONFIG_MOTOROLA_SREC is not set
+# CONFIG_RAW_BINARY is not set
 
 #
-# Enable support for RAM-based functions
-# (If selected, then modifications are needed in ld.script as well)
+# Customize Header Files
 #
-CONFIG_PIC32MX_RAMFUNCS=n
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
 
 #
-# Identify toolchain and linker options
+# Debug Options
 #
-CONFIG_PIC32MX_MICROCHIPW=n
-CONFIG_PIC32MX_MICROCHIPL=n
-CONFIG_PIC32MX_MICROCHIPW_LITE=y
-CONFIG_PIC32MX_MICROCHIPL_LITE=n
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_SYMBOLS is not set
 
 #
-# Individual subsystems can be enabled:
+# System Type
 #
+# CONFIG_ARCH_8051 is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+CONFIG_ARCH_MIPS=y
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="mips"
+CONFIG_ARCH_FAMILY="mips32"
+CONFIG_ARCH_CHIP="pic32mx"
+CONFIG_BOARD_LOOPSPERMSEC=8079
+# CONFIG_ARCH_CALIBRATION is not set
+# CONFIG_SERIAL_TERMIOS is not set
+CONFIG_ARCH_CHIP_PIC32MX=y
+CONFIG_ARCH_MIPS32=y
 
-CONFIG_PIC32MX_WDT=n
-CONFIG_PIC32MX_RTCC=n
-CONFIG_PIC32MX_TIMER1=n
-CONFIG_PIC32MX_TIMER2=n
-CONFIG_PIC32MX_TIMER3=n
-CONFIG_PIC32MX_TIMER4=n
-CONFIG_PIC32MX_TIMER5=n
-CONFIG_PIC32MX_IC1=n
-CONFIG_PIC32MX_IC2=n
-CONFIG_PIC32MX_IC3=n
-CONFIG_PIC32MX_IC4=n
-CONFIG_PIC32MX_IC5=n
-CONFIG_PIC32MX_OC1=n
-CONFIG_PIC32MX_OC2=n
-CONFIG_PIC32MX_OC3=n
-CONFIG_PIC32MX_OC4=n
-CONFIG_PIC32MX_OC5=n
-CONFIG_PIC32MX_I2C1=n
-CONFIG_PIC32MX_I2C2=n
-CONFIG_PIC32MX_SPI1=n
-CONFIG_PIC32MX_SPI2=n
+#
+# MIPS32 Configuration Options
+#
+# CONFIG_MIPS32_TOOLCHAIN_GNU_ELF is not set
+# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL is not set
+# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_LITE is not set
+# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW is not set
+CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_LITE=y
+# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPOPENL is not set
+# CONFIG_MIPS32_TOOLCHAIN_PINGUINOW is not set
+# CONFIG_MIPS32_TOOLCHAIN_PINGUINOL is not set
+
+#
+# PIC32MX Configuration Options
+#
+# CONFIG_ARCH_CHIP_PIC32MX110F016B is not set
+# CONFIG_ARCH_CHIP_PIC32MX110F016C is not set
+# CONFIG_ARCH_CHIP_PIC32MX110F016D is not set
+# CONFIG_ARCH_CHIP_PIC32MX120F032B is not set
+# CONFIG_ARCH_CHIP_PIC32MX120F032C is not set
+# CONFIG_ARCH_CHIP_PIC32MX120F032D is not set
+# CONFIG_ARCH_CHIP_PIC32MX130F064B is not set
+# CONFIG_ARCH_CHIP_PIC32MX130F064C is not set
+# CONFIG_ARCH_CHIP_PIC32MX130F064D is not set
+# CONFIG_ARCH_CHIP_PIC32MX150F128B is not set
+# CONFIG_ARCH_CHIP_PIC32MX150F128C is not set
+# CONFIG_ARCH_CHIP_PIC32MX150F128D is not set
+# CONFIG_ARCH_CHIP_PIC32MX210F016B is not set
+# CONFIG_ARCH_CHIP_PIC32MX210F016C is not set
+# CONFIG_ARCH_CHIP_PIC32MX210F016D is not set
+# CONFIG_ARCH_CHIP_PIC32MX220F032B is not set
+# CONFIG_ARCH_CHIP_PIC32MX220F032C is not set
+# CONFIG_ARCH_CHIP_PIC32MX220F032D is not set
+# CONFIG_ARCH_CHIP_PIC32MX230F064B is not set
+# CONFIG_ARCH_CHIP_PIC32MX230F064C is not set
+# CONFIG_ARCH_CHIP_PIC32MX230F064D is not set
+# CONFIG_ARCH_CHIP_PIC32MX250F128B is not set
+# CONFIG_ARCH_CHIP_PIC32MX250F128C is not set
+# CONFIG_ARCH_CHIP_PIC32MX250F128D is not set
+# CONFIG_ARCH_CHIP_PIC32MX320F032H is not set
+# CONFIG_ARCH_CHIP_PIC32MX320F064H is not set
+# CONFIG_ARCH_CHIP_PIC32MX320F128H is not set
+# CONFIG_ARCH_CHIP_PIC32MX320F128L is not set
+# CONFIG_ARCH_CHIP_PIC32MX340F128H is not set
+# CONFIG_ARCH_CHIP_PIC32MX340F256H is not set
+# CONFIG_ARCH_CHIP_PIC32MX340F512H is not set
+# CONFIG_ARCH_CHIP_PIC32MX340F128L is not set
+# CONFIG_ARCH_CHIP_PIC32MX360F256L is not set
+# CONFIG_ARCH_CHIP_PIC32MX360F512L is not set
+# CONFIG_ARCH_CHIP_PIC32MX420F032H is not set
+# CONFIG_ARCH_CHIP_PIC32MX440F128H is not set
+# CONFIG_ARCH_CHIP_PIC32MX440F128L is not set
+# CONFIG_ARCH_CHIP_PIC32MX440F256H is not set
+# CONFIG_ARCH_CHIP_PIC32MX440F512H is not set
+# CONFIG_ARCH_CHIP_PIC32MX460F256L is not set
+CONFIG_ARCH_CHIP_PIC32MX460F512L=y
+# CONFIG_ARCH_CHIP_PIC32MX534F064H is not set
+# CONFIG_ARCH_CHIP_PIC32MX534F064L is not set
+# CONFIG_ARCH_CHIP_PIC32MX564F064H is not set
+# CONFIG_ARCH_CHIP_PIC32MX564F064L is not set
+# CONFIG_ARCH_CHIP_PIC32MX564F128H is not set
+# CONFIG_ARCH_CHIP_PIC32MX564F128L is not set
+# CONFIG_ARCH_CHIP_PIC32MX575F256H is not set
+# CONFIG_ARCH_CHIP_PIC32MX575F256L is not set
+# CONFIG_ARCH_CHIP_PIC32MX575F512H is not set
+# CONFIG_ARCH_CHIP_PIC32MX575F512L is not set
+# CONFIG_ARCH_CHIP_PIC32MX664F064H is not set
+# CONFIG_ARCH_CHIP_PIC32MX664F064L is not set
+# CONFIG_ARCH_CHIP_PIC32MX664F128H is not set
+# CONFIG_ARCH_CHIP_PIC32MX664F128L is not set
+# CONFIG_ARCH_CHIP_PIC32MX675F256H is not set
+# CONFIG_ARCH_CHIP_PIC32MX675F256L is not set
+# CONFIG_ARCH_CHIP_PIC32MX675F512H is not set
+# CONFIG_ARCH_CHIP_PIC32MX675F512L is not set
+# CONFIG_ARCH_CHIP_PIC32MX695F512H is not set
+# CONFIG_ARCH_CHIP_PIC32MX695F512L is not set
+# CONFIG_ARCH_CHIP_PIC32MX764F128H is not set
+# CONFIG_ARCH_CHIP_PIC32MX764F128L is not set
+# CONFIG_ARCH_CHIP_PIC32MX775F256H is not set
+# CONFIG_ARCH_CHIP_PIC32MX775F256L is not set
+# CONFIG_ARCH_CHIP_PIC32MX775F512H is not set
+# CONFIG_ARCH_CHIP_PIC32MX775F512L is not set
+# CONFIG_ARCH_CHIP_PIC32MX795F512H is not set
+# CONFIG_ARCH_CHIP_PIC32MX795F512L is not set
+CONFIG_ARCH_CHIP_PIC32MX4=y
+# CONFIG_PIC32MX_MVEC is not set
+CONFIG_PIC32MX_T1=y
+
+#
+# PIC32MX Peripheral Support
+#
+# CONFIG_PIC32MX_WDT is not set
+# CONFIG_PIC32MX_T2 is not set
+# CONFIG_PIC32MX_T3 is not set
+# CONFIG_PIC32MX_T4 is not set
+# CONFIG_PIC32MX_T5 is not set
+# CONFIG_PIC32MX_IC1 is not set
+# CONFIG_PIC32MX_IC2 is not set
+# CONFIG_PIC32MX_IC3 is not set
+# CONFIG_PIC32MX_IC4 is not set
+# CONFIG_PIC32MX_IC5 is not set
+# CONFIG_PIC32MX_OC1 is not set
+# CONFIG_PIC32MX_OC2 is not set
+# CONFIG_PIC32MX_OC3 is not set
+# CONFIG_PIC32MX_OC4 is not set
+# CONFIG_PIC32MX_OC5 is not set
+# CONFIG_PIC32MX_I2C1 is not set
+# CONFIG_PIC32MX_I2C2 is not set
+# CONFIG_PIC32MX_I2C3 is not set
+# CONFIG_PIC32MX_I2C4 is not set
+# CONFIG_PIC32MX_I2C5 is not set
+# CONFIG_PIC32MX_SPI1 is not set
+# CONFIG_PIC32MX_SPI2 is not set
+# CONFIG_PIC32MX_SPI3 is not set
+# CONFIG_PIC32MX_SPI4 is not set
 CONFIG_PIC32MX_UART1=y
-CONFIG_PIC32MX_UART2=n
-CONFIG_PIC32MX_PMP=n
-CONFIG_PIC32MX_ADC=n
-CONFIG_PIC32MX_CVR=n
-CONFIG_PIC32MX_CM1=n
-CONFIG_PIC32MX_CM2=n
-CONFIG_PIC32MX_OSC=y
-CONFIG_PIC32MX_DDP=n
-CONFIG_PIC32MX_FLASH=n
-CONFIG_PIC32MX_BMX=n
-CONFIG_PIC32MX_DMA=n
-CONFIG_PIC32MX_CHE=n
-CONFIG_PIC32MX_USBDEV=n
-CONFIG_PIC32MX_USBHOST=n
-CONFIG_PIC32MX_IOPORTA=y
-CONFIG_PIC32MX_IOPORTB=y
-CONFIG_PIC32MX_IOPORTC=y
-CONFIG_PIC32MX_IOPORTD=y
-CONFIG_PIC32MX_IOPORTE=y
-CONFIG_PIC32MX_IOPORTF=y
-CONFIG_PIC32MX_IOPORTG=y
-
-#
-# PIC32MX Configuration Settings
+# CONFIG_PIC32MX_UART2 is not set
+# CONFIG_PIC32MX_UART3 is not set
+# CONFIG_PIC32MX_UART4 is not set
+# CONFIG_PIC32MX_UART5 is not set
+# CONFIG_PIC32MX_UART6 is not set
+# CONFIG_PIC32MX_ADC is not set
+# CONFIG_PIC32MX_PMP is not set
+# CONFIG_PIC32MX_CM1 is not set
+# CONFIG_PIC32MX_CM2 is not set
+# CONFIG_PIC32MX_CM3 is not set
+# CONFIG_PIC32MX_RTCC is not set
+# CONFIG_PIC32MX_DMA is not set
+# CONFIG_PIC32MX_FLASH is not set
+# CONFIG_PIC32MX_USBDEV is not set
+# CONFIG_PIC32MX_USBHOST is not set
+# CONFIG_PIC32MX_CAN1 is not set
+# CONFIG_PIC32MX_CAN2 is not set
+# CONFIG_PIC32MX_ETHERNET is not set
+# CONFIG_PIC32MX_CTMU is not set
+
+#
+# PIC32MX Peripheral Interrupt Priorities
+#
+CONFIG_PIC32MX_CTPRIO=16
+CONFIG_PIC32MX_CS0PRIO=16
+CONFIG_PIC32MX_CS1PRIO=16
+CONFIG_PIC32MX_INT0PRIO=16
+CONFIG_PIC32MX_INT1PRIO=16
+CONFIG_PIC32MX_INT2PRIO=16
+CONFIG_PIC32MX_INT3PRIO=16
+CONFIG_PIC32MX_INT4PRIO=16
+CONFIG_PIC32MX_T1PRIO=16
+CONFIG_PIC32MX_UART1PRIO=16
+
+#
+# Device Configuration 0 (DEVCFG0)
 #
 CONFIG_PIC32MX_DEBUGGER=2
 CONFIG_PIC32MX_ICESEL=1
+CONFIG_PIC32MX_PROGFLASHWP=0xff
+CONFIG_PIC32MX_BOOTFLASHWP=1
+CONFIG_PIC32MX_CODEWP=1
 
 #
-# PIC32MX specific serial device driver settings
+# Device Configuration 3 (DEVCFG3)
 #
-CONFIG_UART1_SERIAL_CONSOLE=y
-CONFIG_UART2_SERIAL_CONSOLE=n
-
-CONFIG_UART1_TXBUFSIZE=256
-CONFIG_UART2_TXBUFSIZE=256
-
-CONFIG_UART1_RXBUFSIZE=256
-CONFIG_UART2_RXBUFSIZE=256
+CONFIG_PIC32MX_USBIDO=0
+CONFIG_PIC32MX_VBUSIO=0
+# CONFIG_PIC32MX_WDENABLE is not set
+CONFIG_PIC32MX_FETHIO=1
+CONFIG_PIC32MX_FMIIEN=1
 
-CONFIG_UART1_BAUD=115200
-CONFIG_UART2_BAUD=115200
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+CONFIG_ARCH_VECNOTIRQ=y
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_IRQPRIO=y
+# CONFIG_CUSTOM_STACK is not set
+# CONFIG_ADDRENV is not set
+# CONFIG_ARCH_HAVE_VFORK is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
+CONFIG_ARCH_HAVE_RAMFUNCS=y
+# CONFIG_ARCH_RAMFUNCS is not set
 
-CONFIG_UART1_BITS=8
-CONFIG_UART2_BITS=8
+#
+# Board Settings
+#
+CONFIG_DRAM_START=0xa0000000
+CONFIG_DRAM_SIZE=32768
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
 
-CONFIG_UART1_PARITY=0
-CONFIG_UART2_PARITY=0
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
 
-CONFIG_UART1_2STOP=0
-CONFIG_UART2_2STOP=0
+#
+# Board Selection
+#
+# CONFIG_ARCH_BOARD_PCBLOGICPIC32MX is not set
+CONFIG_ARCH_BOARD_UBW32=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="ubw32"
 
 #
-# General build options
+# Common Board Options
 #
-CONFIG_RRLOAD_BINARY=n
-CONFIG_INTELHEX_BINARY=y
-CONFIG_MOTOROLA_SREC=n
-CONFIG_RAW_BINARY=n
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_HAVE_BUTTONS=y
+# CONFIG_ARCH_BUTTONS is not set
+CONFIG_ARCH_HAVE_IRQBUTTONS=y
 
 #
-# General OS setup
+# Board-Specific Options
 #
-CONFIG_USER_ENTRYPOINT="ostest_main"
-CONFIG_DEBUG=n
-CONFIG_DEBUG_VERBOSE=n
-CONFIG_DEBUG_SYMBOLS=n
-CONFIG_DEBUG_SCHED=n
 
-CONFIG_MM_REGIONS=1
-CONFIG_ARCH_LOWPUTC=y
+#
+# RTOS Features
+#
+CONFIG_MSEC_PER_TICK=10
 CONFIG_RR_INTERVAL=0
-CONFIG_SCHED_INSTRUMENTATION=n
+# CONFIG_SCHED_INSTRUMENTATION is not set
 CONFIG_TASK_NAME_SIZE=0
+# CONFIG_SCHED_HAVE_PARENT is not set
+# CONFIG_JULIAN_TIME is not set
 CONFIG_START_YEAR=2012
 CONFIG_START_MONTH=4
 CONFIG_START_DAY=26
-CONFIG_GREGORIAN_TIME=n
-CONFIG_JULIAN_TIME=n
 CONFIG_DEV_CONSOLE=y
-CONFIG_DEV_LOWCONSOLE=y
-CONFIG_MUTEX_TYPES=n
-CONFIG_PRIORITY_INHERITANCE=n
-CONFIG_SEM_PREALLOCHOLDERS=0
-CONFIG_SEM_NNESTPRIO=0
-CONFIG_FDCLONE_DISABLE=n
-CONFIG_FDCLONE_STDIO=n
+# CONFIG_MUTEX_TYPES is not set
+# CONFIG_PRIORITY_INHERITANCE is not set
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SCHED_WORKQUEUE=n
-CONFIG_SCHED_WORKPRIORITY=192
-CONFIG_SCHED_WORKPERIOD=50000
-CONFIG_SCHED_WORKSTACKSIZE=1024
-CONFIG_SIG_SIGWORK=17
-CONFIG_SCHED_WAITPID=n
-CONFIG_SCHED_ATEXIT=n
-
-#
-# Settings for nxflat
-#
-CONFIG_NXFLAT=n
-CONFIG_NXFLAT_DUMPBUFFER=n
-CONFIG_SYMTAB_ORDEREDBYNAME=y
-
-#
-# The following can be used to disable categories of
-# APIs supported by the OS.  If the compiler supports
-# weak functions, then it should not be necessary to
-# disable functions unless you want to restrict usage
-# of those APIs.
-#
-# There are certain dependency relationships in these
-# features.
-#
-# o mq_notify logic depends on signals to awaken tasks
-#   waiting for queues to become full or empty.
-# o pthread_condtimedwait() depends on signals to wake
-#   up waiting tasks.
-#
-CONFIG_DISABLE_CLOCK=n
-CONFIG_DISABLE_POSIX_TIMERS=n
-CONFIG_DISABLE_PTHREAD=n
-CONFIG_DISABLE_SIGNALS=n
-CONFIG_DISABLE_MQUEUE=n
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_WAITPID is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+CONFIG_USER_ENTRYPOINT="ostest_main"
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_CLOCK is not set
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_POLL=y
 
 #
-# Misc libc settings
-#
-CONFIG_NOPRINTF_FIELDWIDTH=n
-
-#
-# Allow for architecture optimized implementations
-#
-# The architecture can provide optimized versions of the
-# following to improve system performance
+# Signal Numbers
 #
-CONFIG_ARCH_MEMCPY=n
-CONFIG_ARCH_MEMCMP=n
-CONFIG_ARCH_MEMMOVE=n
-CONFIG_ARCH_MEMSET=n
-CONFIG_ARCH_STRCMP=n
-CONFIG_ARCH_STRCPY=n
-CONFIG_ARCH_STRNCPY=n
-CONFIG_ARCH_STRLEN=n
-CONFIG_ARCH_STRNLEN=n
-CONFIG_ARCH_BZERO=n
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGALARM=3
+CONFIG_SIG_SIGCONDTIMEDOUT=16
 
 #
 # Sizes of configurable things (0 disables)
@@ -254,9 +339,6 @@ CONFIG_NPTHREAD_KEYS=4
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NAME_MAX=32
-CONFIG_STDIO_BUFFER_SIZE=256
-CONFIG_STDIO_LINEBUFFER=y
-CONFIG_NUNGET_CHARS=2
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_MQ_MAXMSGSIZE=32
 CONFIG_MAX_WDOGPARMS=2
@@ -264,250 +346,299 @@ CONFIG_PREALLOC_WDOGS=4
 CONFIG_PREALLOC_TIMERS=4
 
 #
-# Filesystem configuration
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+
+#
+# Device Drivers
+#
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_LOOP is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_PWM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_LCD is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MTD is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+CONFIG_DEV_LOWCONSOLE=y
+# CONFIG_16550_UART is not set
+CONFIG_ARCH_HAVE_UART1=y
+CONFIG_MCU_SERIAL=y
+CONFIG_UART1_SERIAL_CONSOLE=y
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# UART1 Configuration
+#
+CONFIG_UART1_RXBUFSIZE=256
+CONFIG_UART1_TXBUFSIZE=256
+CONFIG_UART1_BAUD=115200
+CONFIG_UART1_BITS=8
+CONFIG_UART1_PARITY=0
+CONFIG_UART1_2STOP=0
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+
+#
+# Networking Support
 #
-CONFIG_FS_FAT=n
-CONFIG_FAT_LCNAMES=y
-CONFIG_FAT_LFN=y
-CONFIG_FAT_MAXFNAME=32
-CONFIG_FS_NXFFS=n
-CONFIG_FS_ROMFS=n
+# CONFIG_NET is not set
 
 #
-# Maintain legacy build behavior (revisit)
+# File Systems
 #
 
-CONFIG_MMCSD=y
-CONFIG_MMCSD_SPI=y
-CONFIG_MMCSD_SDIO=y
+#
+# File system configuration
+#
+# CONFIG_FS_RAMMAP is not set
 
 #
-# SPI-based MMC/SD driver
+# System Logging
 #
-CONFIG_MMCSD_NSLOTS=1
-CONFIG_MMCSD_READONLY=n
-CONFIG_MMCSD_SPICLOCK=12500000
+# CONFIG_SYSLOG is not set
 
 #
-# Block driver buffering
+# Graphics Support
 #
-CONFIG_FS_READAHEAD=n
-CONFIG_FS_WRITEBUFFER=n
+# CONFIG_NX is not set
 
 #
-# SDIO-based MMC/SD driver
+# Memory Management
 #
-CONFIG_SDIO_DMA=n
-CONFIG_MMCSD_MMCSUPPORT=n
-CONFIG_MMCSD_HAVECARDDETECT=n
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_GRAN is not set
 
 #
-# TCP/IP and UDP support via uIP
+# Binary Formats
 #
-CONFIG_NET=n
-CONFIG_NET_IPv6=n
-CONFIG_NSOCKET_DESCRIPTORS=0
-CONFIG_NET_SOCKOPTS=y
-CONFIG_NET_BUFSIZE=420
-CONFIG_NET_TCP=n
-CONFIG_NET_TCP_CONNS=40
-CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_UDP=n
-CONFIG_NET_UDP_CHECKSUMS=y
-#CONFIG_NET_UDP_CONNS=10
-CONFIG_NET_ICMP=n
-CONFIG_NET_ICMP_PING=n
-#CONFIG_NET_PINGADDRCONF=0
-CONFIG_NET_STATISTICS=y
-#CONFIG_NET_RECEIVE_WINDOW=
-#CONFIG_NET_ARPTAB_SIZE=8
-CONFIG_NET_BROADCAST=n
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+# CONFIG_PIC is not set
+CONFIG_SYMTAB_ORDEREDBYNAME=y
 
 #
-# UIP Network Utilities
+# Library Routines
 #
-CONFIG_NET_DHCP_LIGHT=n
-CONFIG_NET_RESOLV_ENTRIES=4
 
 #
-# USB Device Configuration
+# Standard C Library Options
 #
-CONFIG_USBDEV=n
-CONFIG_USBDEV_ISOCHRONOUS=n
-CONFIG_USBDEV_DUALSPEED=n
-CONFIG_USBDEV_SELFPOWERED=y
-CONFIG_USBDEV_REMOTEWAKEUP=n
-CONFIG_USBDEV_MAXPOWER=100
-CONFIG_USBDEV_TRACE=n
-CONFIG_USBDEV_TRACE_NRECORDS=128
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_EXECFUNCS is not set
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
 
 #
-# USB Serial Device Configuration
+# Non-standard Helper Functions
 #
-CONFIG_PL2303=n
-CONFIG_PL2303_EPINTIN=1
-CONFIG_PL2303_EPBULKOUT=2
-CONFIG_PL2303_EPBULKIN=5
-CONFIG_PL2303_NWRREQS=4
-CONFIG_PL2303_NRDREQS=4
-CONFIG_PL2303_VENDORID=0x067b
-CONFIG_PL2303_PRODUCTID=0x2303
-CONFIG_PL2303_VENDORSTR="Nuttx"
-CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
-CONFIG_PL2303_RXBUFSIZE=512
-CONFIG_PL2303_TXBUFSIZE=512
+# CONFIG_LIB_KBDCODEC is not set
 
 #
-# USB serial device class driver (Standard CDC ACM class)
+# Basic CXX Support
 #
-CONFIG_CDCACM=n
-CONFIG_CDCACM_CONSOLE=n
-#CONFIG_CDCACM_EP0MAXPACKET
-CONFIG_CDCACM_EPINTIN=1
-#CONFIG_CDCACM_EPINTIN_FSSIZE
-#CONFIG_CDCACM_EPINTIN_HSSIZE
-CONFIG_CDCACM_EPBULKOUT=3
-#CONFIG_CDCACM_EPBULKOUT_FSSIZE
-#CONFIG_CDCACM_EPBULKOUT_HSSIZE
-CONFIG_CDCACM_EPBULKIN=2
-#CONFIG_CDCACM_EPBULKIN_FSSIZE
-#CONFIG_CDCACM_EPBULKIN_HSSIZE
-#CONFIG_CDCACM_NWRREQS
-#CONFIG_CDCACM_NRDREQS
-#CONFIG_CDCACM_VENDORID
-#CONFIG_CDCACM_VENDORSTR
-#CONFIG_CDCACM_PRODUCTID
-#CONFIG_CDCACM_PRODUCTSTR
-#CONFIG_CDCACM_RXBUFSIZE
-#CONFIG_CDCACM_TXBUFSIZE
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
 
 #
-# USB Storage Device Configuration
+# Application Configuration
+#
+
 #
-CONFIG_USBMSC=n
-CONFIG_USBMSC_EP0MAXPACKET=64
-CONFIG_USBMSC_EPBULKOUT=1
-CONFIG_USBMSC_EPBULKIN=2
-CONFIG_USBMSC_NRDREQS=8
-CONFIG_USBMSC_NWRREQS=2
-CONFIG_USBMSC_BULKINREQLEN=256
-CONFIG_USBMSC_BULKOUTREQLEN=64
-CONFIG_USBMSC_VENDORID=0x584e
-CONFIG_USBMSC_VENDORSTR="NuttX"
-CONFIG_USBMSC_PRODUCTID=0x5342
-CONFIG_USBMSC_PRODUCTSTR="USBdev Storage"
-CONFIG_USBMSC_VERSIONNO=0x0399
-CONFIG_USBMSC_REMOVABLE=y
-
-#
-# Settings for examples/uip
-#
-CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002
-CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00
-CONFIG_EXAMPLES_UIP_DHCPC=n
-
-#
-# Settings for examples/nettest
-#
-CONFIG_EXAMPLES_NETTEST_SERVER=n
-CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n
-CONFIG_EXAMPLES_NETTEST_NOMAC=y
-CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
-CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
-CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
-
-#
-# Settings for examples/ostest
+# Built-In Applications
 #
+# CONFIG_BUILTIN is not set
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CDCACM is not set
+# CONFIG_EXAMPLES_COMPOSITE is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_LCDRW is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_NETTEST is not set
+# CONFIG_EXAMPLES_NSH is not set
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXCONSOLE is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXFLAT is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+CONFIG_EXAMPLES_OSTEST=y
+# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set
 CONFIG_EXAMPLES_OSTEST_LOOPS=1
 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048
 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3
+CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000
+CONFIG_EXAMPLES_OSTEST_RR_RUNS=10
+# CONFIG_EXAMPLES_PASHELLO is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_QENCODER is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UDP is not set
+# CONFIG_EXAMPLES_UIP is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBMSC is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
 
 #
-# Settings for apps/nshlib
+# Interpreters
 #
-CONFIG_NSH_BUILTIN_APPS=n
-CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_STRERROR=n
-CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NESTDEPTH=3
-CONFIG_NSH_DISABLESCRIPT=n
-CONFIG_NSH_DISABLEBG=n
-CONFIG_NSH_ROMFSETC=n
-CONFIG_NSH_CONSOLE=y
-CONFIG_NSH_TELNET=n
-CONFIG_NSH_ARCHINIT=n
-CONFIG_NSH_IOBUFFER_SIZE=512
-CONFIG_NSH_DHCPC=n
-CONFIG_NSH_NOMAC=n
-CONFIG_NSH_IPADDR=0x0a000002
-CONFIG_NSH_DRIPADDR=0x0a000001
-CONFIG_NSH_NETMASK=0xffffff00
-CONFIG_NSH_ROMFSMOUNTPT="/etc"
-CONFIG_NSH_INITSCRIPT="init.d/rcS"
-CONFIG_NSH_ROMFSDEVNO=0
-CONFIG_NSH_ROMFSSECTSIZE=64
-CONFIG_NSH_FATDEVNO=1
-CONFIG_NSH_FATSECTSIZE=512
-CONFIG_NSH_FATNSECTORS=1024
-CONFIG_NSH_FATMOUNTPT="/tmp"
 
 #
-# Architecture-specific NSH options
+# Interpreters
 #
-CONFIG_NSH_MMCSDSPIPORTNO=1
-CONFIG_NSH_MMCSDSLOTNO=0
-CONFIG_NSH_MMCSDMINOR=0
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
 
 #
-# Settings for examples/usbserial
+# Network Utilities
 #
-CONFIG_EXAMPLES_USBSERIAL_INONLY=n
-CONFIG_EXAMPLES_USBSERIAL_OUTONLY=n
-CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL=n
-CONFIG_EXAMPLES_USBSERIAL_ONLYBIG=n
 
-CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n
-CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n
-CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n
-CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n
-CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
+#
+# Networking Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_DHCPC is not set
+# CONFIG_NETUTILS_DHCPD is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_FTPD is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_RESOLV is not set
+# CONFIG_NETUTILS_SMTP is not set
+# CONFIG_NETUTILS_TELNETD is not set
+# CONFIG_NETUTILS_TFTPC is not set
+# CONFIG_NETUTILS_THTTPD is not set
+# CONFIG_NETUTILS_UIPLIB is not set
+# CONFIG_NETUTILS_WEBCLIENT is not set
 
 #
-# Settings for examples/usbstorage
+# ModBus
 #
-CONFIG_EXAMPLES_USBMSC_NLUNS=1
-CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0
-CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0"
-CONFIG_EXAMPLES_USBMSC_TRACEINIT=n
-CONFIG_EXAMPLES_USBMSC_TRACECLASS=n
-CONFIG_EXAMPLES_USBMSC_TRACETRANSFERS=n
-CONFIG_EXAMPLES_USBMSC_TRACECONTROLLER=n
-CONFIG_EXAMPLES_USBMSC_TRACEINTERRUPTS=n
 
 #
-# Settings for examples/cdcacm
+# FreeModbus
 #
-# Configuration prequisites:
+# CONFIG_MODBUS is not set
+
+#
+# NSH Library
 #
-CONFIG_EXAMPLES_CDCACM_DEVMINOR=0
-CONFIG_EXAMPLES_CDCACM_TRACEINIT=n
-CONFIG_EXAMPLES_CDCACM_TRACECLASS=n
-CONFIG_EXAMPLES_CDCACM_TRACETRANSFERS=n
-CONFIG_EXAMPLES_CDCACM_TRACECONTROLLER=n
-CONFIG_EXAMPLES_CDCACM_TRACEINTERRUPTS=n
+# CONFIG_NSH_LIBRARY is not set
 
 #
-# Stack and heap information
+# NxWidgets/NxWM
 #
-CONFIG_BOOT_RUNFROMFLASH=n
-CONFIG_BOOT_COPYTORAM=n
-CONFIG_CUSTOM_STACK=n
-CONFIG_IDLETHREAD_STACKSIZE=2048
-CONFIG_USERMAIN_STACKSIZE=2048
-CONFIG_PTHREAD_STACK_MIN=256
-CONFIG_PTHREAD_STACK_DEFAULT=2048
-CONFIG_HEAP_BASE=
-CONFIG_HEAP_SIZE=
+
+#
+# System NSH Add-Ons
+#
+
+#
+# Custom Free Memory Command
+#
+# CONFIG_SYSTEM_FREE is not set
+
+#
+# I2C tool
+#
+
+#
+# FLASH Program Installation
+#
+# CONFIG_SYSTEM_INSTALL is not set
+
+#
+# readline()
+#
+# CONFIG_SYSTEM_READLINE is not set
+
+#
+# Power Off
+#
+# CONFIG_SYSTEM_POWEROFF is not set
+
+#
+# RAMTRON
+#
+# CONFIG_SYSTEM_RAMTRON is not set
+
+#
+# SD Card
+#
+# CONFIG_SYSTEM_SDCARD is not set
+
+#
+# Sysinfo
+#
+# CONFIG_SYSTEM_SYSINFO is not set
diff --git a/nuttx/configs/ubw32/ostest/ld.script b/nuttx/configs/ubw32/ostest/ld.script
deleted file mode 100644
index 3a64fff23..000000000
--- a/nuttx/configs/ubw32/ostest/ld.script
+++ /dev/null
@@ -1,317 +0,0 @@
-/****************************************************************************
- * configs/ubw32/ostest/ld.script
- *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *	notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *	notice, this list of conditions and the following disclaimer in
- *	the documentation and/or other materials provided with the
- *	distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *	used to endorse or promote products derived from this software
- *	without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-/* Memory Regions ***********************************************************/
-
-MEMORY
-{
-	/* The PIC32MX460F512L has 512Kb of program FLASH at physical address
-	 * 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000
-	 */
-
-	kseg0_progmem  (rx) : ORIGIN = 0x9d000000, LENGTH = 512K
-
-	/* The PIC32MX460F512L has 12Kb of boot FLASH at physical address
-	 * 0x1fc00000.  The initial reset vector is in KSEG1, but all other
-	 * accesses are in KSEG0.
-	 *
-	 *   REGION        PHYSICAL   KSEG   SIZE
-	 *   DESCRIPTION   START ADDR        (BYTES)
-	 *   ------------- ---------- ------ ----------------------
-	 *   Exceptions:*
-	 *     Reset       0x1fc00000 KSEG1  512         512
-	 *     TLB Refill  0x1fc00200 KSEG1  256         768
-	 *     Cache Error 0x1fc00300 KSEG1  128         896
-	 *     Others      0x1fc00380 KSEG1  128        1024 (1Kb)
-	 *     Interrupt   0x1fc00400 KSEG1  128        1152
-	 *     JTAG        0x1fc00480 KSEG1  16         1168
-	 *   Exceptions    0x1fc00490 KSEG0  8192-1168  8192 (4Kb)
-	 *   Debug code    0x1fc02000 KSEG1  4096-16   12272
-	 *   DEVCFG3-0     0x1fc02ff0 KSEG1  16        12288 (12Kb)
-	 *
-	 * Exceptions assume:
-	 *
-	 *   STATUS: BEV=0/1 and EXL=0
-	 *   CAUSE:  IV=1
-	 *   JTAG:   ProbEn=0
-	 *   And multi-vector support disabled
-	 */
-
-	kseg1_reset    (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
-	kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
-	kseg1_ebexcpt  (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
-	kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
-	kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
-	kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
-	kseg0_bootmem  (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
-	kseg1_dbgcode  (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
-	kseg1_devcfg    (r) : ORIGIN = 0xbfc02ff0, LENGTH = 16
-
-	/* The PIC32MX460F512L has 32Kb of data memory at physical address
-	 * 0x00000000.  Since the PIC32MX has no data cache, this memory is
-	 * always accessed through KSEG1.
-	 *
-	 * When used with MPLAB, we need to set aside 512 bytes of memory
-	 * for use by MPLAB.
-	 */
-
-	kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512
-}
-
-OUTPUT_FORMAT("elf32-tradlittlemips")
-OUTPUT_ARCH(pic32mx)
-ENTRY(__start)
-
-SECTIONS
-{
-	/* Boot FLASH sections */
-
-	.reset :
-	{
-		KEEP (*(.reset))
-	} > kseg1_reset
-
-	/* Exception handlers.  The following is assumed:
-	 *
-	 *   STATUS: BEV=1 and EXL=0
-	 *   CAUSE:  IV=1
-	 *   JTAG:   ProbEn=0
-	 *   And multi-vector support disabled
-	 *
-	 * In that configuration, the vector locations become:
-	 *
-	 *   Reset, Soft Reset  bfc0:0000
-	 *   TLB Refill         bfc0:0200
-	 *   Cache Error        bfc0:0300
-	 *   All others         bfc0:0380
-	 *   Interrupt          bfc0:0400
-	 *   EJTAG Debug        bfc0:0480
-	 */
-
-	 /* KSEG1 exception handler "trampolines" */
-
-	.gen_excpt :
-	{
-		KEEP (*(.gen_excpt))
-	} > kseg1_genexcpt
-
-	.ebase_excpt :
-	{
-		KEEP (*(.ebase_excpt))
-	} > kseg1_ebexcpt
-
-	.bev_excpt :
-	{
-		KEEP (*(.bev_excpt))
-	} > kseg1_bevexcpt
-
-	.int_excpt :
-	{
-		KEEP (*(.int_excpt))
-	} > kseg1_intexcpt
-
-	.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
-
-	.start :
-	{
-		/* KSEG0 Reset startup logic */
-
-		*(.start)
-
-		/* KSEG0 exception handlers */
-
-		*(.nmi_handler)
-		*(.bev_handler)
-		*(.int_handler)
-	} > kseg0_bootmem
-
-	.dbg_code = ORIGIN(kseg1_dbgcode);
-
-	.devcfg :
-	{
-		KEEP (*(.devcfg))
-	} > kseg1_devcfg
-
-	/* Program FLASH sections */
-
-	.text :
-	{
-		_stext = ABSOLUTE(.);
-		*(.text .text.*)
-		*(.stub)
-		KEEP (*(.text.*personality*))
-		*(.gnu.linkonce.t.*)
-		*(.gnu.warning)
-		*(.mips16.fn.*)
-		*(.mips16.call.*)
-
-		/* Read-only data is included in the text section */
-
-		*(.rodata .rodata.*)
-		*(.rodata1)
-		*(.gnu.linkonce.r.*)
-
-		/* Small initialized constant global and static data */
-
-		*(.sdata2 .sdata2.*)
-		*(.gnu.linkonce.s2.*)
-
-		/* Uninitialized constant global and static data */
-
-		*(.sbss2 .sbss2.*)
-		*(.gnu.linkonce.sb2.*)
-		_etext = ABSOLUTE(.);
-	} > kseg0_progmem
-
-	/* Initialization data begins here in progmem */
-
-	_data_loaddr = LOADADDR(.data);
-
-	.eh_frame_hdr : { *(.eh_frame_hdr) }
-	.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
-
-	/* RAM functions are positioned at the beginning of RAM so that
-	 * they can be guaranteed to satisfy the 2Kb alignment requirement.
-	 */
-
-/* This causes failures if there are no RAM functions
-	.ramfunc ALIGN(2K) :
-	{
-		_sramfunc =  ABSOLUTE(.);
-		*(.ramfunc	.ramfunc.*)
-		_eramfunc =  ABSOLUTE(.);
-	} > kseg1_datamem AT > kseg0_progmem
-
-	_ramfunc_loadaddr = LOADADDR(.ramfunc);
-	_ramfunc_sizeof   = SIZEOF(.ramfunc);
-	_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
-	_bmxdudba_address = LENGTH(kseg1_datamem) ;
-	_bmxdupba_address = LENGTH(kseg1_datamem) ;
-*/
-
-	.data :
-	{
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		KEEP (*(.gnu.linkonce.d.*personality*))
-		*(.data1)
-	} > kseg1_datamem AT > kseg0_progmem
-
-	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
-	_gp = ALIGN(16) + 0x7FF0 ;
-
-	.got :
-	{
-		*(.got.plt) *(.got)
-	} > kseg1_datamem AT > kseg0_progmem
-
-	.sdata :
-	{
-		*(.sdata .sdata.* .gnu.linkonce.s.*)
-	} > kseg1_datamem AT > kseg0_progmem
-
-	.lit8 :
-	{
-		*(.lit8)
-	} > kseg1_datamem AT > kseg0_progmem
-
-	.lit4 :
-	{
-		*(.lit4)
-		_edata = ABSOLUTE(.);
-	} >kseg1_datamem AT>kseg0_progmem
-
-	.sbss :
-	{
-		_sbss = ABSOLUTE(.);
-		*(.dynsbss)
-		*(.sbss .sbss.* .gnu.linkonce.sb.*)
-		*(.scommon)
-	} >kseg1_datamem
-
-	.bss :
-	{
-		*(.dynbss)
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > kseg1_datamem
-
-	/* Stabs debugging sections */
-
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-
-	/* DWARF debug sections */
-	/* DWARF 1 */
-
-	.debug 0 : { *(.debug) }
-	.line 0 : { *(.line) }
-
-	/* GNU DWARF 1 extensions */
-
-	.debug_srcinfo 0 : { *(.debug_srcinfo) }
-	.debug_sfnames 0 : { *(.debug_sfnames) }
-
-	/* DWARF 1.1 and DWARF 2 */
-
-	.debug_aranges 0 : { *(.debug_aranges) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-
-	/* DWARF 2 */
-
-	.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_frame 0 : { *(.debug_frame) }
-	.debug_str 0 : { *(.debug_str) }
-	.debug_loc 0 : { *(.debug_loc) }
-	.debug_macinfo 0 : { *(.debug_macinfo) }
-
-	/* SGI/MIPS DWARF 2 extensions */
-
-	.debug_weaknames 0 : { *(.debug_weaknames) }
-	.debug_funcnames 0 : { *(.debug_funcnames) }
-	.debug_typenames 0 : { *(.debug_typenames) }
-	.debug_varnames 0 : { *(.debug_varnames) }
-
-	/DISCARD/ : { *(.note.GNU-stack) }
-}
diff --git a/nuttx/configs/ubw32/scripts/ld.script b/nuttx/configs/ubw32/scripts/ld.script
new file mode 100644
index 000000000..c25820b11
--- /dev/null
+++ b/nuttx/configs/ubw32/scripts/ld.script
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * configs/ubw32/scripts/ld.script
+ *
+ *   Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *	notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *	notice, this list of conditions and the following disclaimer in
+ *	the documentation and/or other materials provided with the
+ *	distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *	used to endorse or promote products derived from this software
+ *	without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/* Memory Regions ***********************************************************/
+
+MEMORY
+{
+	/* The PIC32MX460F512L has 512Kb of program FLASH at physical address
+	 * 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000
+	 */
+
+	kseg0_progmem  (rx) : ORIGIN = 0x9d000000, LENGTH = 512K
+
+	/* The PIC32MX460F512L has 12Kb of boot FLASH at physical address
+	 * 0x1fc00000.  The initial reset vector is in KSEG1, but all other
+	 * accesses are in KSEG0.
+	 *
+	 *   REGION        PHYSICAL   KSEG   SIZE
+	 *   DESCRIPTION   START ADDR        (BYTES)
+	 *   ------------- ---------- ------ ----------------------
+	 *   Exceptions:*
+	 *     Reset       0x1fc00000 KSEG1  512         512
+	 *     TLB Refill  0x1fc00200 KSEG1  256         768
+	 *     Cache Error 0x1fc00300 KSEG1  128         896
+	 *     Others      0x1fc00380 KSEG1  128        1024 (1Kb)
+	 *     Interrupt   0x1fc00400 KSEG1  128        1152
+	 *     JTAG        0x1fc00480 KSEG1  16         1168
+	 *   Exceptions    0x1fc00490 KSEG0  8192-1168  8192 (4Kb)
+	 *   Debug code    0x1fc02000 KSEG1  4096-16   12272
+	 *   DEVCFG3-0     0x1fc02ff0 KSEG1  16        12288 (12Kb)
+	 *
+	 * Exceptions assume:
+	 *
+	 *   STATUS: BEV=0/1 and EXL=0
+	 *   CAUSE:  IV=1
+	 *   JTAG:   ProbEn=0
+	 *   And multi-vector support disabled
+	 */
+
+	kseg1_reset    (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
+	kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
+	kseg1_ebexcpt  (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
+	kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
+	kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
+	kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
+	kseg0_bootmem  (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
+	kseg1_dbgcode  (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
+	kseg1_devcfg    (r) : ORIGIN = 0xbfc02ff0, LENGTH = 16
+
+	/* The PIC32MX460F512L has 32Kb of data memory at physical address
+	 * 0x00000000.  Since the PIC32MX has no data cache, this memory is
+	 * always accessed through KSEG1.
+	 *
+	 * When used with MPLAB, we need to set aside 512 bytes of memory
+	 * for use by MPLAB.
+	 */
+
+	kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512
+}
+
+OUTPUT_FORMAT("elf32-tradlittlemips")
+OUTPUT_ARCH(pic32mx)
+ENTRY(__start)
+
+SECTIONS
+{
+	/* Boot FLASH sections */
+
+	.reset :
+	{
+		KEEP (*(.reset))
+	} > kseg1_reset
+
+	/* Exception handlers.  The following is assumed:
+	 *
+	 *   STATUS: BEV=1 and EXL=0
+	 *   CAUSE:  IV=1
+	 *   JTAG:   ProbEn=0
+	 *   And multi-vector support disabled
+	 *
+	 * In that configuration, the vector locations become:
+	 *
+	 *   Reset, Soft Reset  bfc0:0000
+	 *   TLB Refill         bfc0:0200
+	 *   Cache Error        bfc0:0300
+	 *   All others         bfc0:0380
+	 *   Interrupt          bfc0:0400
+	 *   EJTAG Debug        bfc0:0480
+	 */
+
+	 /* KSEG1 exception handler "trampolines" */
+
+	.gen_excpt :
+	{
+		KEEP (*(.gen_excpt))
+	} > kseg1_genexcpt
+
+	.ebase_excpt :
+	{
+		KEEP (*(.ebase_excpt))
+	} > kseg1_ebexcpt
+
+	.bev_excpt :
+	{
+		KEEP (*(.bev_excpt))
+	} > kseg1_bevexcpt
+
+	.int_excpt :
+	{
+		KEEP (*(.int_excpt))
+	} > kseg1_intexcpt
+
+	.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
+
+	.start :
+	{
+		/* KSEG0 Reset startup logic */
+
+		*(.start)
+
+		/* KSEG0 exception handlers */
+
+		*(.nmi_handler)
+		*(.bev_handler)
+		*(.int_handler)
+	} > kseg0_bootmem
+
+	.dbg_code = ORIGIN(kseg1_dbgcode);
+
+	.devcfg :
+	{
+		KEEP (*(.devcfg))
+	} > kseg1_devcfg
+
+	/* Program FLASH sections */
+
+	.text :
+	{
+		_stext = ABSOLUTE(.);
+		*(.text .text.*)
+		*(.stub)
+		KEEP (*(.text.*personality*))
+		*(.gnu.linkonce.t.*)
+		*(.gnu.warning)
+		*(.mips16.fn.*)
+		*(.mips16.call.*)
+
+		/* Read-only data is included in the text section */
+
+		*(.rodata .rodata.*)
+		*(.rodata1)
+		*(.gnu.linkonce.r.*)
+
+		/* Small initialized constant global and static data */
+
+		*(.sdata2 .sdata2.*)
+		*(.gnu.linkonce.s2.*)
+
+		/* Uninitialized constant global and static data */
+
+		*(.sbss2 .sbss2.*)
+		*(.gnu.linkonce.sb2.*)
+		_etext = ABSOLUTE(.);
+	} > kseg0_progmem
+
+	/* Initialization data begins here in progmem */
+
+	_data_loaddr = LOADADDR(.data);
+
+	.eh_frame_hdr : { *(.eh_frame_hdr) }
+	.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+	/* RAM functions are positioned at the beginning of RAM so that
+	 * they can be guaranteed to satisfy the 2Kb alignment requirement.
+	 */
+
+/* This causes failures if there are no RAM functions
+	.ramfunc ALIGN(2K) :
+	{
+		_sramfunc =  ABSOLUTE(.);
+		*(.ramfunc	.ramfunc.*)
+		_eramfunc =  ABSOLUTE(.);
+	} > kseg1_datamem AT > kseg0_progmem
+
+	_ramfunc_loadaddr = LOADADDR(.ramfunc);
+	_ramfunc_sizeof   = SIZEOF(.ramfunc);
+	_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
+	_bmxdudba_address = LENGTH(kseg1_datamem) ;
+	_bmxdupba_address = LENGTH(kseg1_datamem) ;
+*/
+
+	.data :
+	{
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		KEEP (*(.gnu.linkonce.d.*personality*))
+		*(.data1)
+	} > kseg1_datamem AT > kseg0_progmem
+
+	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+	_gp = ALIGN(16) + 0x7FF0 ;
+
+	.got :
+	{
+		*(.got.plt) *(.got)
+	} > kseg1_datamem AT > kseg0_progmem
+
+	.sdata :
+	{
+		*(.sdata .sdata.* .gnu.linkonce.s.*)
+	} > kseg1_datamem AT > kseg0_progmem
+
+	.lit8 :
+	{
+		*(.lit8)
+	} > kseg1_datamem AT > kseg0_progmem
+
+	.lit4 :
+	{
+		*(.lit4)
+		_edata = ABSOLUTE(.);
+	} >kseg1_datamem AT>kseg0_progmem
+
+	.sbss :
+	{
+		_sbss = ABSOLUTE(.);
+		*(.dynsbss)
+		*(.sbss .sbss.* .gnu.linkonce.sb.*)
+		*(.scommon)
+	} >kseg1_datamem
+
+	.bss :
+	{
+		*(.dynbss)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > kseg1_datamem
+
+	/* Stabs debugging sections */
+
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+
+	/* DWARF debug sections */
+	/* DWARF 1 */
+
+	.debug 0 : { *(.debug) }
+	.line 0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+
+	.debug_srcinfo 0 : { *(.debug_srcinfo) }
+	.debug_sfnames 0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+
+	.debug_aranges 0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+
+	.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_frame 0 : { *(.debug_frame) }
+	.debug_str 0 : { *(.debug_str) }
+	.debug_loc 0 : { *(.debug_loc) }
+	.debug_macinfo 0 : { *(.debug_macinfo) }
+
+	/* SGI/MIPS DWARF 2 extensions */
+
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames 0 : { *(.debug_varnames) }
+
+	/DISCARD/ : { *(.note.GNU-stack) }
+}
-- 
cgit v1.2.3


From 90a72e97d3f18a5e230578c63113da119622a73a Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Tue, 15 Jan 2013 15:40:18 +0000
Subject: Implement vfork() for the MIPS32 architecture

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5520 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                       |   3 +
 nuttx/Documentation/NuttX.html        |   4 +-
 nuttx/TODO                            |  21 ++-
 nuttx/arch/arm/src/arm/vfork.S        |   3 +
 nuttx/arch/arm/src/armv7-m/vfork.S    |   3 +
 nuttx/arch/arm/src/common/up_vfork.c  |   2 +-
 nuttx/arch/arm/src/common/up_vfork.h  |   8 +-
 nuttx/arch/mips/Kconfig               |   1 +
 nuttx/arch/mips/src/mips32/Kconfig    |   8 ++
 nuttx/arch/mips/src/mips32/up_vfork.c | 254 ++++++++++++++++++++++++++++++++++
 nuttx/arch/mips/src/mips32/up_vfork.h | 132 ++++++++++++++++++
 nuttx/arch/mips/src/mips32/vfork.S    | 154 +++++++++++++++++++++
 nuttx/arch/mips/src/pic32mx/Make.defs |   4 +-
 nuttx/configs/ubw32/ostest/defconfig  |   9 +-
 nuttx/sched/task_vfork.c              |   8 +-
 15 files changed, 599 insertions(+), 15 deletions(-)
 create mode 100644 nuttx/arch/mips/src/mips32/up_vfork.c
 create mode 100644 nuttx/arch/mips/src/mips32/up_vfork.h
 create mode 100644 nuttx/arch/mips/src/mips32/vfork.S

(limited to 'nuttx/arch')

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 41ac95db0..2d2cd8259 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3952,4 +3952,7 @@
 	  scripts sub-directory
 	* configs/ubw32/ostest:  Configuration configured to use the
 	  kconfig-frontends tools.
+	* arch/mips/src/mips32/up_vfork.c, up_vfork.h, and vfork.S:
+	  Implement vfork() for MIPS32 (no floating point support)
+	* configs/ubw32/ostest: Enable the vfork() test.
 
diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html
index 22651de79..c5f1ebc9c 100644
--- a/nuttx/Documentation/NuttX.html
+++ b/nuttx/Documentation/NuttX.html
@@ -381,7 +381,7 @@
   <td><br></td>
   <td>
     <p>
-      <li>Well documented in the NuttX <a href="NuttXUserGuide.html">User Guide</a>.</li>
+      <li>Well documented in the NuttX <a href="NuttxUserGuide.html">User Guide</a>.</li>
     </p>
 </tr>
 
@@ -3833,7 +3833,7 @@ pascal-3.0 2011-05-15 Gregory Nutt &lt;gnutt@nuttx.org&gt;
 </tr>
 <tr>
   <td valign="top" width="22"><img height="20" width="20" src="favicon.ico"></td>
-  <td><a href="NuttXUserGuide.html">User Guide</a></td>
+  <td><a href="NuttxUserGuide.html">User Guide</a></td>
 </tr>
 <tr>
   <td valign="top" width="22"><img height="20" width="20" src="favicon.ico"></td>
diff --git a/nuttx/TODO b/nuttx/TODO
index 0d02e10e6..58ca4cc8e 100644
--- a/nuttx/TODO
+++ b/nuttx/TODO
@@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements.
 
 nuttx/
 
- (10)  Task/Scheduler (sched/)
+ (11)  Task/Scheduler (sched/)
   (1)  Memory Managment (mm/)
   (3)  Signals (sched/, arch/)
   (2)  pthreads (sched/)
@@ -195,6 +195,25 @@ o Task/Scheduler (sched/)
   Status:      Open
   Priority:    Low
 
+  Title:       IMPROVED TASK CONTROL BLOCK STRUCTURE
+               All task resources that are shared amongst threads have
+               their own "break-away", reference-counted structure. The
+               Task Control Block (TCB) of each thread holds a reference
+               to each breakaway structure (see include/nuttx/sched.h).
+               It would be more efficent to have one reference counted
+               structure that holds all of the shared resources.
+
+               These are the current shared structures:
+               - Environment varaibles (struct environ_s)
+               - PIC data space and address environments (struct dspace_s)
+               - File descriptors (struct filelist)
+               - FILE streams (struct streamlist)
+               - Sockets (struct socketlist)
+   Status:     Open
+   Priority:   Low.  This is an enhancement.  It would slight reduce
+               memory usage but would also increase coupling.  These
+               resources are nicely modular now.
+
 o Memory Managment (mm/)
   ^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S
index 226d9f7de..7c3c8b727 100644
--- a/nuttx/arch/arm/src/arm/vfork.S
+++ b/nuttx/arch/arm/src/arm/vfork.S
@@ -105,6 +105,7 @@ vfork:
 	mov		r0, sp					/* Save the value of the stack on entry */
 	sub		sp, sp, #VFORK_SIZEOF	/* Allocate the structure on the stack */
 
+	/* CPU registers */
 	/* Save the volatile registers */
 
 	str		r4, [sp, #VFORK_R4_OFFSET]
@@ -121,6 +122,8 @@ vfork:
 	str		r0, [sp, #VFORK_SP_OFFSET]
 	str		lr, [sp, #VFORK_LR_OFFSET]
 
+	/* Floating point registers (not yet) */
+
 	/* Then, call up_vfork(), passing it a pointer to the stack structure */
 
 	mov		r0, sp
diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S
index 386fca33c..f36ff23aa 100644
--- a/nuttx/arch/arm/src/armv7-m/vfork.S
+++ b/nuttx/arch/arm/src/armv7-m/vfork.S
@@ -108,6 +108,7 @@ vfork:
 	mov		r0, sp					/* Save the value of the stack on entry */
 	sub		sp, sp, #VFORK_SIZEOF	/* Allocate the structure on the stack */
 
+	/* CPU registers */
 	/* Save the volatile registers */
 
 	str		r4, [sp, #VFORK_R4_OFFSET]
@@ -124,6 +125,8 @@ vfork:
 	str		r0, [sp, #VFORK_SP_OFFSET]
 	str		lr, [sp, #VFORK_LR_OFFSET]
 
+	/* Floating point registers (not yet) */
+
 	/* Then, call up_vfork(), passing it a pointer to the stack structure */
 
 	mov		r0, sp
diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c
index 5349378bc..3b653e317 100644
--- a/nuttx/arch/arm/src/common/up_vfork.c
+++ b/nuttx/arch/arm/src/common/up_vfork.c
@@ -208,7 +208,7 @@ pid_t up_vfork(const struct vfork_s *context)
   svdbg("New stack base:%08x SP:%08x FP:%08x\n",
         child->adj_stack_ptr, newsp, newfp);
 
- /* Update the stack pointer, frame pointer, and voltile registers.  When
+ /* Update the stack pointer, frame pointer, and volatile registers.  When
   * the child TCB was initialized, all of the values were set to zero.
   * up_initial_state() altered a few values, but the return value in R0
   * should be cleared to zero, providing the indication to the newly started
diff --git a/nuttx/arch/arm/src/common/up_vfork.h b/nuttx/arch/arm/src/common/up_vfork.h
index a4505474a..97edf9aaa 100644
--- a/nuttx/arch/arm/src/common/up_vfork.h
+++ b/nuttx/arch/arm/src/common/up_vfork.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/common/arm-vfork.h
+ * arch/arm/src/common/up_vfork.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -53,6 +53,7 @@
 #define VFORK_R8_OFFSET  (4*4)   /* Volatile register r8 */
 #define VFORK_R9_OFFSET  (5*4)   /* Volatile register r9 */
 #define VFORK_R10_OFFSET (6*4)   /* Volatile register r10 */
+
 #define VFORK_FP_OFFSET  (7*4)   /* Frame pointer */
 #define VFORK_SP_OFFSET  (8*4)   /* Stack pointer*/
 #define VFORK_LR_OFFSET  (9*4)   /* Return address*/
@@ -66,6 +67,8 @@
 #ifndef __ASSEMBLY__
 struct vfork_s
 {
+  /* CPU registers */
+
   uint32_t r4;   /* Volatile register r4 */
   uint32_t r5;   /* Volatile register r5 */
   uint32_t r6;   /* Volatile register r6 */
@@ -73,9 +76,12 @@ struct vfork_s
   uint32_t r8;   /* Volatile register r8 */
   uint32_t r9;   /* Volatile register r9 */
   uint32_t r10;  /* Volatile register r10 */
+
   uint32_t fp;   /* Frame pointer */
   uint32_t sp;   /* Stack pointer*/
   uint32_t lr;   /* Return address*/
+
+  /* Floating point registers (not yet) */
 };
 #endif
 
diff --git a/nuttx/arch/mips/Kconfig b/nuttx/arch/mips/Kconfig
index 1b10e26ae..86482ef7a 100644
--- a/nuttx/arch/mips/Kconfig
+++ b/nuttx/arch/mips/Kconfig
@@ -22,6 +22,7 @@ endchoice
 config ARCH_MIPS32
 	bool
 	default n
+	select ARCH_HAVE_VFORK
 
 config ARCH_FAMILY
 	string
diff --git a/nuttx/arch/mips/src/mips32/Kconfig b/nuttx/arch/mips/src/mips32/Kconfig
index b8b5d9b92..c7a4499c2 100644
--- a/nuttx/arch/mips/src/mips32/Kconfig
+++ b/nuttx/arch/mips/src/mips32/Kconfig
@@ -47,4 +47,12 @@ config MIPS32_TOOLCHAIN_PINGUINOL
 
 endchoice
 
+config MIPS32_FRAMEPOINTER
+	bool "ABI Uses Frame Pointer"
+	default n
+	depends on ARCH_HAVE_VFORK
+	---help---
+		Register r30 may be a frame pointer in some ABIs.  Or may just be
+		saved register s8.  It makes a difference for vfork handling.
+
 endif
diff --git a/nuttx/arch/mips/src/mips32/up_vfork.c b/nuttx/arch/mips/src/mips32/up_vfork.c
new file mode 100644
index 000000000..6b7e27f31
--- /dev/null
+++ b/nuttx/arch/mips/src/mips32/up_vfork.c
@@ -0,0 +1,254 @@
+/****************************************************************************
+ * arch/mips/src/mips32/up_vfork.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "up_vfork.h"
+#include "os_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_STACK_ALIGNMENT
+#  define CONFIG_STACK_ALIGNMENT 4
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_vfork
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the
+ *   behavior is undefined if the process created by vfork() either modifies
+ *   any data other than a variable of type pid_t used to store the return
+ *   value from vfork(), or returns from the function in which vfork() was
+ *   called, or calls any other function before successfully calling _exit()
+ *   or one of the exec family of functions. 
+ *
+ *   The overall sequence is:
+ *
+ *   1) User code calls vfork().  vfork() collects context information and
+ *      transfers control up up_vfork().
+ *   2) up_vfork()and calls task_vforksetup().
+ *   3) task_vforksetup() allocates and configures the child task's TCB.  This
+ *      consists of:
+ *      - Allocation of the child task's TCB.
+ *      - Initialization of file descriptors and streams
+ *      - Configuration of environment variables
+ *      - Setup the intput parameters for the task.
+ *      - Initialization of the TCB (including call to up_initial_state()
+ *   4) up_vfork() provides any additional operating context. up_vfork must:
+ *      - Allocate and initialize the stack
+ *      - Initialize special values in any CPU registers that were not
+ *        already configured by up_initial_state()
+ *   5) up_vfork() then calls task_vforkstart()
+ *   6) task_vforkstart() then executes the child thread.
+ *
+ * task_vforkabort() may be called if an error occurs between steps 3 and 6.
+ *
+ * Input Paremeters:
+ *   context - Caller context information saved by vfork()
+ *
+ * Return:
+ *   Upon successful completion, vfork() returns 0 to the child process and
+ *   returns the process ID of the child process to the parent process.
+ *   Otherwise, -1 is returned to the parent, no child process is created,
+ *   and errno is set to indicate the error. 
+ *
+ ****************************************************************************/
+
+pid_t up_vfork(const struct vfork_s *context)
+{
+  _TCB *parent = (FAR _TCB *)g_readytorun.head;
+  _TCB *child;
+  size_t stacksize;
+  uint32_t newsp;
+#if CONFIG_MIPS32_FRAMEPOINTER
+  uint32_t newfp;
+#endif
+  uint32_t stackutil;
+  int ret;
+
+  svdbg("s0:%08x s1:%08x s2:%08x s3:%08x s4:%08x\n",
+        context->s0, context->s1, context->s2, context->s3, context->s4);
+#if CONFIG_MIPS32_FRAMEPOINTER
+  svdbg("s5:%08x s6:%08x s7:%08x\n",
+        context->s5, context->s6, context->s7);
+#ifdef MIPS32_SAVE_GP
+  svdbg("fp:%08x sp:%08x ra:%08x gp:%08x\n",
+        context->fp, context->sp, context->ra, context->gp);
+#else
+  svdbg("fp:%08x sp:%08x ra:%08x\n",
+        context->fp context->sp, context->ra);
+#endif
+#else
+  svdbg("s5:%08x s6:%08x s7:%08x s8:%08x\n",
+        context->s5, context->s6, context->s7, context->s8);
+#ifdef MIPS32_SAVE_GP
+  svdbg("sp:%08x ra:%08x gp:%08x\n",
+        context->sp, context->ra, context->gp);
+#else
+  svdbg("sp:%08x ra:%08x\n",
+        context->sp, context->ra);
+#endif
+#endif
+
+  /* Allocate and initialize a TCB for the child task. */
+
+  child = task_vforksetup((start_t)context->ra);
+  if (!child)
+    {
+      sdbg("task_vforksetup failed\n");
+      return (pid_t)ERROR;
+    }
+
+  svdbg("Parent=%p Child=%p\n", parent, child);
+
+  /* Get the size of the parent task's stack.  Due to alignment operations,
+   * the adjusted stack size may be smaller than the stack size originally
+   * requrested.
+   */
+
+  stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1;
+
+  /* Allocate the stack for the TCB */
+
+  ret = up_create_stack(child, stacksize);
+  if (ret != OK)
+    {
+      sdbg("up_create_stack failed: %d\n", ret);
+      task_vforkabort(child, -ret);
+      return (pid_t)ERROR;
+    }
+
+  /* How much of the parent's stack was utilized?  The MIPS uses
+   * a push-down stack so that the current stack pointer should
+   * be lower than the initial, adjusted stack pointer.  The
+   * stack usage should be the difference between those two.
+   */
+
+  DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp);
+  stackutil = (uint32_t)parent->adj_stack_ptr - context->sp;
+
+  svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); 
+
+  /* Make some feeble effort to perserve the stack contents.  This is
+   * feeble because the stack surely contains invalid pointers and other
+   * content that will not work in the child context.  However, if the
+   * user follows all of the caveats of vfor() usage, even this feeble
+   * effort is overkill.
+   */
+
+  newsp = (uint32_t)child->adj_stack_ptr - stackutil;
+  memcpy((void *)newsp, (const void *)context->sp, stackutil);
+
+  /* Was there a frame pointer in place before? */
+
+#if CONFIG_MIPS32_FRAMEPOINTER
+  if (context->fp <= (uint32_t)parent->adj_stack_ptr &&
+      context->fp >= (uint32_t)parent->adj_stack_ptr - stacksize)
+    {
+      uint32_t frameutil = (uint32_t)parent->adj_stack_ptr - context->fp;
+      newfp = (uint32_t)child->adj_stack_ptr - frameutil;
+    }
+  else
+    {
+      newfp = context->fp;
+    }
+
+  svdbg("Old stack base:%08x SP:%08x FP:%08x\n",
+        parent->adj_stack_ptr, context->sp, context->fp);
+  svdbg("New stack base:%08x SP:%08x FP:%08x\n",
+        child->adj_stack_ptr, newsp, newfp);
+#else
+  svdbg("Old stack base:%08x SP:%08x\n",
+        parent->adj_stack_ptr, context->sp);
+  svdbg("New stack base:%08x SP:%08x\n",
+        child->adj_stack_ptr, newsp);
+#endif
+
+ /* Update the stack pointer, frame pointer, global pointer and saved
+  * registers.  When the child TCB was initialized, all of the values
+  * were set to zero. up_initial_state() altered a few values, but the
+  * return value in v0 should be cleared to zero, providing the
+  * indication to the newly started child thread.
+  */
+
+  child->xcp.regs[REG_S0]  = context->s0;  /* Saved register s0 */
+  child->xcp.regs[REG_S1]  = context->s1;  /* Saved register s1 */
+  child->xcp.regs[REG_S2]  = context->s2;  /* Saved register s2 */
+  child->xcp.regs[REG_S3]  = context->s3;  /* Volatile register s3 */
+  child->xcp.regs[REG_S4]  = context->s4;  /* Volatile register s4 */
+  child->xcp.regs[REG_S5]  = context->s5;  /* Volatile register s5 */
+  child->xcp.regs[REG_S6]  = context->s6;  /* Volatile register s6 */
+  child->xcp.regs[REG_S7]  = context->s7;  /* Volatile register s7 */
+#if CONFIG_MIPS32_FRAMEPOINTER
+  child->xcp.regs[REG_FP]  = newfp;        /* Frame pointer */
+#else
+  child->xcp.regs[REG_S8]  = context->s8;  /* Volatile register s8 */
+#endif
+  child->xcp.regs[REG_SP]  = newsp;        /* Stack pointer */
+#if MIPS32_SAVE_GP
+  child->xcp.regs[REG_GP]  = newsp;        /* Global pointer */
+#endif
+
+  /* And, finally, start the child task.  On a failure, task_vforkstart()
+   * will discard the TCB by calling task_vforkabort().
+   */
+
+  return task_vforkstart(child);
+}
diff --git a/nuttx/arch/mips/src/mips32/up_vfork.h b/nuttx/arch/mips/src/mips32/up_vfork.h
new file mode 100644
index 000000000..556633072
--- /dev/null
+++ b/nuttx/arch/mips/src/mips32/up_vfork.h
@@ -0,0 +1,132 @@
+/****************************************************************************
+ * arch/mips/src/mips/up_vfork.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_MIPS32_VFORK_H
+#define __ARCH_MIPS_SRC_MIPS32_VFORK_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/mips32/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Register r30 may be a frame pointer in some ABIs.  Or may just be saved
+ * register s8.  It makes a difference for vfork handling.
+ */
+
+#undef VFORK_HAVE_FP
+
+/* r0      zero   Always has the value 0.
+ * r1      at     Temporary generally used by assembler.
+ * r2-r3   v0-v1  Used for expression evaluations and to hold the integer and
+ *                pointer type function return values.
+ * r4-r7   a0-a3  Used for passing arguments to functions; values are not
+ *                preserved across function calls.
+ * r8-r15  t0-t7  Temporary registers used for expression evaluation; values
+ *                are not preserved across function calls.
+ * r16-r23 s0-s7  Saved registers; values are preserved across function calls.
+ * r24-r25 t8-t9  Temporary registers used for expression evaluations; values
+ *                are not preserved across function calls. When calling
+ *                position independent functions r25 must contain the address
+ *                of the called function.
+ * r26-r27 k0-k1  Used only by the operating system.
+ * r28     gp     Global pointer and context pointer.
+ * r29     sp     Stack pointer.
+ * r30     s8     Saved register (like s0-s7).  If a frame pointer is used,
+ *                then this is the frame pointer.
+ * r31     ra     Return address.
+ */
+ 
+#define VFORK_S0_OFFSET   (0*4)   /* Saved register s0 */
+#define VFORK_S1_OFFSET   (1*4)   /* Saved register s1 */
+#define VFORK_S2_OFFSET   (2*4)   /* Saved register s2 */
+#define VFORK_S3_OFFSET   (3*4)   /* Saved register s3 */
+#define VFORK_S4_OFFSET   (4*4)   /* Saved register s4 */
+#define VFORK_S5_OFFSET   (5*4)   /* Saved register s5 */
+#define VFORK_S6_OFFSET   (6*4)   /* Saved register s6 */
+#define VFORK_S7_OFFSET   (7*4)   /* Saved register s7 */
+
+#ifdef CONFIG_MIPS32_FRAMEPOINTER
+#  define VFORK_FP_OFFSET (8*4)   /* Frame pointer */
+#else
+#  define VFORK_S8_OFFSET (8*4)   /* Saved register s8 */
+#endif
+
+#define VFORK_SP_OFFSET   (9*4)   /* Stack pointer*/
+#define VFORK_RA_OFFSET   (10*4)  /* Return address*/
+#ifdef MIPS32_SAVE_GP
+#  define VFORK_GP_OFFSET (11*4)   /* Global pointer */
+#  define VFORK_SIZEOF    (12*4)
+#else
+#  define VFORK_SIZEOF    (11*4)
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+struct vfork_s
+{
+  /* CPU registers */
+
+  uint32_t s0;   /* Saved register s0 */
+  uint32_t s1;   /* Saved register s1 */
+  uint32_t s2;   /* Saved register s2 */
+  uint32_t s3;   /* Saved register s3 */
+  uint32_t s4;   /* Saved register s4 */
+  uint32_t s5;   /* Saved register s5 */
+  uint32_t s6;   /* Saved register s6 */
+  uint32_t s7;   /* Saved register s7 */
+#ifdef CONFIG_MIPS32_FRAMEPOINTER
+  uint32_t fp;   /* Frame pointer */
+#else
+  uint32_t s8;   /* Saved register s8 */
+#endif
+  uint32_t sp;   /* Stack pointer*/
+  uint32_t ra;   /* Return address*/
+#ifdef MIPS32_SAVE_GP
+  uint32_t gp;   /* Global pointer */
+#endif
+
+  /* Floating point registers (not yet) */
+};
+#endif
+
+#endif /* __ARCH_MIPS_SRC_MIPS32_VFORK_H */
diff --git a/nuttx/arch/mips/src/mips32/vfork.S b/nuttx/arch/mips/src/mips32/vfork.S
new file mode 100644
index 000000000..2b7d180d3
--- /dev/null
+++ b/nuttx/arch/mips/src/mips32/vfork.S
@@ -0,0 +1,154 @@
+/************************************************************************************
+ * arch/mips/src/mips32/vfork.S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "up_vfork.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.file	"vfork.S"
+	.globl	up_vfork
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: vfork
+ *
+ * Description:
+ *   The vfork() function has the same effect as fork(), except that the behavior is
+ *   undefined if the process created by vfork() either modifies any data other than
+ *   a variable of type pid_t used to store the return value from vfork(), or returns
+ *   from the function in which vfork() was called, or calls any other function before
+ *   successfully calling _exit() or one of the exec family of functions. 
+ *
+ *   This thin layer implements vfork by simply calling up_vfork() with the vfork()
+ *   context as an argument.  The overall sequence is:
+ *
+ *   1) User code calls vfork().  vfork() collects context information and
+ *      transfers control up up_vfork().
+ *   2) up_vfork()and calls task_vforksetup().
+ *   3) task_vforksetup() allocates and configures the child task's TCB.  This
+ *      consists of:
+ *      - Allocation of the child task's TCB.
+ *      - Initialization of file descriptors and streams
+ *      - Configuration of environment variables
+ *      - Setup the intput parameters for the task.
+ *      - Initialization of the TCB (including call to up_initial_state()
+ *   4) up_vfork() provides any additional operating context. up_vfork must:
+ *      - Allocate and initialize the stack
+ *      - Initialize special values in any CPU registers that were not
+ *        already configured by up_initial_state()
+ *   5) up_vfork() then calls task_vforkstart()
+ *   6) task_vforkstart() then executes the child thread.
+ *
+ * Input Paremeters:
+ *   None
+ *
+ * Return:
+ *   Upon successful completion, vfork() returns 0 to the child process and returns
+ *   the process ID of the child process to the parent process. Otherwise, -1 is
+ *   returned to the parent, no child process is created, and errno is set to
+ *   indicate the error. 
+ *
+ ************************************************************************************/
+
+	.text
+	.align  2
+	.globl	vfork
+	.type	vfork, function
+	.set	nomips16
+	.ent	vfork
+
+vfork:
+	/* Create a stack frame */
+
+	move	$t0, $sp					/* Save the value of the stack on entry */
+	addiu	$sp, $sp, -VFORK_SIZEOF		/* Allocate the structure on the stack */
+
+	/* CPU registers */
+	/* Save the saved registers */
+
+	sw		$s0, VFORK_S0_OFFSET($sp)
+	sw		$s1, VFORK_S1_OFFSET($sp)
+	sw		$s2, VFORK_S2_OFFSET($sp)
+	sw		$s3, VFORK_S3_OFFSET($sp)
+	sw		$s4, VFORK_S4_OFFSET($sp)
+	sw		$s5, VFORK_S5_OFFSET($sp)
+	sw		$s6, VFORK_S6_OFFSET($sp)
+	sw		$s7, VFORK_S7_OFFSET($sp)
+
+#ifdef CONFIG_MIPS32_FRAMEPOINTER
+	sw		$fp, VFORK_FP_OFFSET($sp)
+#else
+	sw		$s8, VFORK_S8_OFFSET($sp)
+#endif
+
+	/* Save the global pointer, stack pointer, and return address */
+
+	sw		$t0, VFORK_SP_OFFSET($sp)
+	sw		$ra, VFORK_RA_OFFSET($sp)
+#ifdef MIPS32_SAVE_GP
+	sw		$gp, VFORK_GP_OFFSET($sp)
+#endif
+
+	/* Floating point registers (not yet) */
+
+	/* Then, call up_vfork(), passing it a pointer to the stack structure */
+
+	move	$a0, $sp
+	jal		up_vfork
+	nop
+
+	/* Release the stack data and return the value returned by up_vfork */
+
+	lw		$ra, VFORK_RA_OFFSET($sp)
+	addiu	$sp, $sp, VFORK_SIZEOF
+	j		$ra
+
+	.end	vfork
+	.size	vfork, .-vfork
diff --git a/nuttx/arch/mips/src/pic32mx/Make.defs b/nuttx/arch/mips/src/pic32mx/Make.defs
index 46fef84dc..861e1c301 100644
--- a/nuttx/arch/mips/src/pic32mx/Make.defs
+++ b/nuttx/arch/mips/src/pic32mx/Make.defs
@@ -39,14 +39,14 @@ HEAD_ASRC = pic32mx-head.S
 
 # Common MIPS files
 
-CMN_ASRCS = up_syscall0.S
+CMN_ASRCS = up_syscall0.S vfork.S
 CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 			up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c \
 			up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c \
 			up_mdelay.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
 			up_puts.c up_releasepending.c up_releasestack.c up_reprioritizertr.c \
 			up_schedulesigaction.c up_sigdeliver.c up_swint0.c up_udelay.c \
-			up_unblocktask.c up_usestack.c
+			up_unblocktask.c up_usestack.c up_vfork.c
 
 # Configuration dependent common files
 
diff --git a/nuttx/configs/ubw32/ostest/defconfig b/nuttx/configs/ubw32/ostest/defconfig
index 3a387ab99..a722e25e7 100644
--- a/nuttx/configs/ubw32/ostest/defconfig
+++ b/nuttx/configs/ubw32/ostest/defconfig
@@ -72,13 +72,10 @@ CONFIG_ARCH_MIPS32=y
 # MIPS32 Configuration Options
 #
 # CONFIG_MIPS32_TOOLCHAIN_GNU_ELF is not set
-# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL is not set
-# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_LITE is not set
 # CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW is not set
 CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_LITE=y
-# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPOPENL is not set
 # CONFIG_MIPS32_TOOLCHAIN_PINGUINOW is not set
-# CONFIG_MIPS32_TOOLCHAIN_PINGUINOL is not set
+# CONFIG_MIPS32_FRAMEPOINTER is not set
 
 #
 # PIC32MX Configuration Options
@@ -245,7 +242,7 @@ CONFIG_ARCH_VECNOTIRQ=y
 CONFIG_ARCH_IRQPRIO=y
 # CONFIG_CUSTOM_STACK is not set
 # CONFIG_ADDRENV is not set
-# CONFIG_ARCH_HAVE_VFORK is not set
+CONFIG_ARCH_HAVE_VFORK=y
 CONFIG_ARCH_STACKDUMP=y
 # CONFIG_ENDIAN_BIG is not set
 CONFIG_ARCH_HAVE_RAMFUNCS=y
@@ -308,7 +305,7 @@ CONFIG_DEV_CONSOLE=y
 # CONFIG_FDCLONE_STDIO is not set
 CONFIG_SDCLONE_DISABLE=y
 # CONFIG_SCHED_WORKQUEUE is not set
-# CONFIG_SCHED_WAITPID is not set
+CONFIG_SCHED_WAITPID=y
 # CONFIG_SCHED_ATEXIT is not set
 # CONFIG_SCHED_ONEXIT is not set
 CONFIG_USER_ENTRYPOINT="ostest_main"
diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c
index 4b42c7b36..46b2d8e9f 100644
--- a/nuttx/sched/task_vfork.c
+++ b/nuttx/sched/task_vfork.c
@@ -287,7 +287,11 @@ pid_t task_vforkstart(FAR _TCB *child)
 #endif
 
 #else
-  /* Again exploiting that execv() bug: Check if the child thread is
+  /* The following logic does not appear to work... It gets stuff in an
+   * infinite kill() loop and hogs the processor.  Therefore, it looks
+   * as though CONFIG_SCHED_WAITPID may be a requirement to used vfork().
+   *
+   * Again exploiting that execv() bug: Check if the child thread is
    * still running.
    */
 
@@ -331,4 +335,4 @@ void task_vforkabort(FAR _TCB *child, int errcode)
 
   sched_releasetcb(child);
   set_errno(errcode);
-}
\ No newline at end of file
+}
-- 
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