From 3ff155d04803d8b19f0f56602e95b4034bc33820 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 18 Jan 2013 16:37:37 +0000 Subject: Beginnings of definitions for the LPC1788; convert olimex-lpc1766stk to use kconfig-frontends git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5533 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/lpc17xx/chip.h | 377 +++++++++++++++++++++++++++ nuttx/arch/arm/include/lpc17xx/irq.h | 203 ++------------- nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h | 245 +++++++++++++++++ nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h | 294 +++++++++++++++++++++ nuttx/arch/arm/src/lpc17xx/Kconfig | 56 +++- nuttx/arch/arm/src/lpc17xx/chip.h | 158 +---------- nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c | 3 +- 7 files changed, 995 insertions(+), 341 deletions(-) create mode 100644 nuttx/arch/arm/include/lpc17xx/chip.h create mode 100644 nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h create mode 100644 nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h (limited to 'nuttx/arch') diff --git a/nuttx/arch/arm/include/lpc17xx/chip.h b/nuttx/arch/arm/include/lpc17xx/chip.h new file mode 100644 index 000000000..d2c436d35 --- /dev/null +++ b/nuttx/arch/arm/include/lpc17xx/chip.h @@ -0,0 +1,377 @@ +/************************************************************************************ + * arch/arm/include/lpc17xx/chip.h + * + * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * with LPC178x support from Rommel Marcelo + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H +#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_LPC1751) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */ +# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */ +# define LPC17_CPUSRAM_SIZE (8*1024) +# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 0 /* No USB host controller */ +# define LPC17_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 1 /* One CAN controller */ +# define LPC17_NI2S 0 /* No I2S modules */ +# define LPC17_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1752) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */ +# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 0 /* No USB host controller */ +# define LPC17_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 1 /* One CAN controller */ +# define LPC17_NI2S 0 /* No I2S modules */ +# define LPC17_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1754) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 1 /* One CAN controller */ +# define LPC17_NI2S 0 /* No I2S modules */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1756) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1758) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1759) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1764) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 0 /* No USB host controller */ +# define LPC17_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 0 /* No I2S modules */ +# define LPC17_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1765) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1766) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1767) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 0 /* No USB host controller */ +# define LPC17_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_NUSBDEV 0 /* No USB device controller */ +# define LPC17_NCAN 0 /* No CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1773) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (8*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LPC17_NUSBHOST /* No USB host controller */ +# undef LPC17_NUSBOTG /* No USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_HAVE_SPIFI 1 /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* No LCD controller */ +# undef LPC17_HAVE_QEI /* No QEI interface */ +# undef LPC17_HAVE_SD /* No SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1774) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (8*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/ +# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LPC17_NUSBHOST /* One USB host controller */ +# undef LPC17_NUSBOTG /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1776) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1777) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1778) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1785) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_HAVE_LCD 1 /* One LCD controller */ +# undef LPC17_HAVE_QEI /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1786) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1787) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1788) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#else +# error "Unsupported LPC17xx chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */ diff --git a/nuttx/arch/arm/include/lpc17xx/irq.h b/nuttx/arch/arm/include/lpc17xx/irq.h index a7eebb32c..c058f6367 100644 --- a/nuttx/arch/arm/include/lpc17xx/irq.h +++ b/nuttx/arch/arm/include/lpc17xx/irq.h @@ -1,7 +1,7 @@ /**************************************************************************** - * arch/lpc17xxx/irq.h + * arch/arm/include/lpc17xxx/irq.h * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,12 +33,12 @@ * ****************************************************************************/ -/* This file should never be included directed but, rather, - * only indirectly through nuttx/irq.h +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h */ -#ifndef __ARCH_LPC17XX_IRQ_H -#define __ARCH_LPC17XX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H /**************************************************************************** * Included Files @@ -47,17 +47,17 @@ #ifndef __ASSEMBLY__ # include #endif +#include /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ - /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. */ -/* Processor Exceptions (vectors 0-15) */ +/* Common Processor Exceptions (vectors 0-15) */ #define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ /* Vector 0: Reset stack pointer value */ @@ -75,185 +75,24 @@ /* External interrupts (vectors >= 16) */ -#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ -#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ -#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) - * Capture 0 - 1 (CR0, CR1) */ -#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) - * Capture 0 - 1 (CR0, CR1) */ -#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3 - * Capture 0-1 */ -#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3 - * Capture 0-1 */ -#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * Modem Control Change - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 - * Capture 0-1 of PWM1 */ -#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ -#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ -#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ -#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF) - * Mode Fault (MODF) */ -#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 - * Rx FIFO half full of SSP0 - * Rx Timeout of SSP0 - * Rx Overrun of SSP0 */ -#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty - * Rx FIFO half full - * Rx Timeout - * Rx Overrun */ -#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ -#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) - * Alarm (RTCALF) */ -#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ -#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ -#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ -#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) - * Note: EINT3 channel is shared with GPIO interrupts */ -#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ -#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */ -#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, - * USB_INT_REQ_DMA */ -#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, - * CAN 1 Tx, CAN 1 Rx */ -#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, - * IntStatus of DMA channel 1 */ -#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ -#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, - * TxFinishedInt, TxErrorInt,* TxUnderrunInt, - * RxDoneInt, RxFinishedInt, RxErrorInt, - * RxOverrunInt */ -#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */ -#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], - * ICAP[2:0], FES */ -#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, - * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int - * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, - * POS2REV_Int */ -#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ -#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ -#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ -#define LPC17_IRQ_NEXTINT (35) -#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) +#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ -/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and - * 2 (only). We go through some special efforts to keep the number of IRQs - * to a minimum in this sparse interrupt case. - * - * 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30 - * 14 interrupts on Port 2: p2.0 - p2.13 - * -- - * 42 - */ - -#ifdef CONFIG_GPIO_IRQ -# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */ -# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */ - - /* Set 1: 12 interrupts p0.0-p0.11 */ - -# define LPC17_VALID_GPIOINT0L (0x00000ffful) -# define LPC17_VALID_SHIFT0L (0) -# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) - -# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0) -# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1) -# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2) -# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3) -# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4) -# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5) -# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6) -# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7) -# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8) -# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9) -# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10) -# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11) -# define LPC17_VALID_NIRQS0L (12) - - /* Set 2: 16 interrupts p0.15-p0.30 */ - -# define LPC17_VALID_GPIOINT0H (0x7fff8000ull) -# define LPC17_VALID_SHIFT0H (15) -# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L) - -# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0) -# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1) -# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2) -# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3) -# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4) -# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5) -# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6) -# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7) -# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8) -# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9) -# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10) -# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11) -# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12) -# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13) -# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14) -# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15) -# define LPC17_VALID_NIRQS0H (16) +/* Family Specfic Interrupts */ - /* Set 3: 14 interrupts p2.0-p2.13 */ - -# define LPC17_VALID_GPIOINT2 (0x00003ffful) -# define LPC17_VALID_SHIFT2 (0) -# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H) - -# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0) -# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1) -# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2) -# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3) -# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4) -# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5) -# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6) -# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7) -# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8) -# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9) -# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10) -# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11) -# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12) -# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13) -# define LPC17_VALID_NIRQS2 (14) -# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2) +#if defined(LPC176x) /* LPC175/6 family */ +# include +#elif defined(LPC178x) /* LPC177/8 family */ +# include #else -# define LPC17_NGPIOAIRQS (0) +# error "Unknown LPC17xx family" #endif -/* Total number of IRQ numbers */ - -#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS) - /**************************************************************************** * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ typedef void (*vic_vector_t)(uint32_t *regs); -#endif /**************************************************************************** * Inline functions @@ -267,19 +106,15 @@ typedef void (*vic_vector_t)(uint32_t *regs); * Public Function Prototypes ****************************************************************************/ -#ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif -#undef EXTERN #ifdef __cplusplus } #endif -#endif +#endif __ASSEMBLY__ -#endif /* __ARCH_LPC17XX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */ diff --git a/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h b/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h new file mode 100644 index 000000000..ac97195e6 --- /dev/null +++ b/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/lpc17xx/lpc176x_irq.h + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* External interrupts (vectors >= 16) */ + +#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ +#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3 + * Capture 0-1 */ +#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3 + * Capture 0-1 */ +#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * Modem Control Change + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 + * Capture 0-1 of PWM1 */ +#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ +#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ +#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ +#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF) + * Mode Fault (MODF) */ +#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 + * Rx FIFO half full of SSP0 + * Rx Timeout of SSP0 + * Rx Overrun of SSP0 */ +#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty + * Rx FIFO half full + * Rx Timeout + * Rx Overrun */ +#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ +#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) + * Alarm (RTCALF) */ +#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ +#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ +#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ +#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) + * Note: EINT3 channel is shared with GPIO interrupts */ +#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ +#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */ +#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, + * USB_INT_REQ_DMA */ +#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, + * CAN 1 Tx, CAN 1 Rx */ +#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, + * IntStatus of DMA channel 1 */ +#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ +#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, + * TxFinishedInt, TxErrorInt,* TxUnderrunInt, + * RxDoneInt, RxFinishedInt, RxErrorInt, + * RxOverrunInt */ +#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */ +#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], + * ICAP[2:0], FES */ +#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, + * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int + * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, + * POS2REV_Int */ +#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ +#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ +#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ +#define LPC17_IRQ_NEXTINT (35) +#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) + +/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and + * 2 (only). We go through some special efforts to keep the number of IRQs + * to a minimum in this sparse interrupt case. + * + * 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30 + * 14 interrupts on Port 2: p2.0 - p2.13 + * -- + * 42 + */ + +#ifdef CONFIG_GPIO_IRQ +# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */ +# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */ + + /* Set 1: 12 interrupts p0.0-p0.11 */ + +# define LPC17_VALID_GPIOINT0L (0x00000ffful) +# define LPC17_VALID_SHIFT0L (0) +# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) + +# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0) +# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1) +# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2) +# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3) +# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4) +# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5) +# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6) +# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7) +# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8) +# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9) +# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10) +# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11) +# define LPC17_VALID_NIRQS0L (12) + + /* Set 2: 16 interrupts p0.15-p0.30 */ + +# define LPC17_VALID_GPIOINT0H (0x7fff8000ull) +# define LPC17_VALID_SHIFT0H (15) +# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L) + +# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0) +# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1) +# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2) +# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3) +# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4) +# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5) +# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6) +# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7) +# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8) +# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9) +# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10) +# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11) +# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12) +# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13) +# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14) +# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15) +# define LPC17_VALID_NIRQS0H (16) + + /* Set 3: 14 interrupts p2.0-p2.13 */ + +# define LPC17_VALID_GPIOINT2 (0x00003ffful) +# define LPC17_VALID_SHIFT2 (0) +# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H) + +# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0) +# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1) +# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2) +# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3) +# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4) +# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5) +# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6) +# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7) +# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8) +# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9) +# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10) +# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11) +# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12) +# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13) +# define LPC17_VALID_NIRQS2 (14) +# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2) +#else +# define LPC17_NGPIOAIRQS (0) +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */ + diff --git a/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h b/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h new file mode 100644 index 000000000..9f7cbf9a7 --- /dev/null +++ b/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h @@ -0,0 +1,294 @@ +/**************************************************************************** + * arch/arm/include/lpc17xxx/lpc178x_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* External interrupts (vectors >= 16) */ + +#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ +#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3 + * Capture 0-1 */ +#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3 + * Capture 0-1 */ +#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * Modem Control Change + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 + * Capture 0-1 of PWM1 */ +#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ +#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ +#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ +/* (LPC17_IRQ_EXTINT+13) Unused */ +#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 + * Rx FIFO half full of SSP0 + * Rx Timeout of SSP0 + * Rx Overrun of SSP0 */ +#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty + * Rx FIFO half full + * Rx Timeout + * Rx Overrun */ +#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ +#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) + * Alarm (RTCALF) */ +#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ +#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ +#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ +#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) + * Note: EINT3 channel is shared with GPIO interrupts */ +#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ +#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */ +#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, + * USB_INT_REQ_DMA */ +#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, + * CAN 1 Tx, CAN 1 Rx */ +#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, + * IntStatus of DMA channel 1 */ +#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ +#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, + * TxFinishedInt, TxErrorInt,* TxUnderrunInt, + * RxDoneInt, RxFinishedInt, RxErrorInt, + * RxOverrunInt */ +#define LPC17_IRQ_MCI (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */ +#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], + * ICAP[2:0], FES */ +#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, + * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int + * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, + * POS2REV_Int */ +#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ +#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ +#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ +#define LPC17_IRQ_UART4 (LPC17_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_SSP2 (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2 + * Rx FIFO half full of SSP2 + * Rx Timeout of SSP2 + * Rx Overrun of SSP2 */ +#define LPC17_IRQ_LCD (LPC17_IRQ_EXTINT+37) /* LCD interrupt + * BER, VCompI, LNBUI, FUFI, CrsrI */ +#define LPC17_IRQ_GPIO (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt + * P0xREI, P2xREI, P0xFEI, P2xFEI */ +#define LPC17_IRQ_PWM0 (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0 + * Capture 0-1 of PWM0 */ +#define LPC17_IRQ_EEPROM (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt + * EE_PROG_DONE, EE_RW_DONE */ +#define LPC17_IRQ_NEXTINT (40) +#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) + +/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and + * 2 (only). We go through some special efforts to keep the number of IRQs + * to a minimum in this sparse interrupt case. + * + * 31 interrupts on Port 0: p0.0 - p0.30 + * 31 interrupts on Port 2: p2.0 - p2.30 + * -- + * 42 + */ + +#ifdef CONFIG_GPIO_IRQ +//~ # define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */ +//~ # define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */ + + /* Set 1: 16 interrupts p0.0-p0.15 */ + +//~ # define LPC17_VALID_GPIOINT0L (0x00000ffful) +# define LPC17_VALID_SHIFT0L (0) +# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) + +# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0) +# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1) +# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2) +# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3) +# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4) +# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5) +# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6) +# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7) +# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8) +# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9) +# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10) +# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11) +# define LPC17_IRQ_P0p12 (LPC17_VALID_FIRST0L+12) +# define LPC17_IRQ_P0p13 (LPC17_VALID_FIRST0L+13) +# define LPC17_IRQ_P0p14 (LPC17_VALID_FIRST0L+14) +# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0L+15) +# define LPC17_VALID_NIRQS0L (16) + + /* Set 2: 16 interrupts p0.16-p0.31 */ + +//~ # define LPC17_VALID_GPIOINT0H (0x7fff8000ull) +# define LPC17_VALID_SHIFT0H (15) +# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L) + +# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+0) +# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+1) +# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+2) +# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+3) +# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+4) +# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+5) +# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+6) +# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+7) +# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+8) +# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+9) +# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+10) +# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+11) +# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+12) +# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+13) +# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+14) +# define LPC17_IRQ_P0p31 (LPC17_VALID_FIRST0H+15) +# define LPC17_VALID_NIRQS0H (16) + + /* Set 3: 16 interrupts p2.0-p2.15 */ + +//~ # define LPC17_VALID_GPIOINT2 (0x00003ffful) +# define LPC17_VALID_SHIFT2L (0) +# define LPC17_VALID_FIRST2L (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H) + +# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2L+0) +# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2L+1) +# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2L+2) +# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2L+3) +# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2L+4) +# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2L+5) +# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2L+6) +# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2L+7) +# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2L+8) +# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2L+9) +# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2L+10) +# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2L+11) +# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2L+12) +# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2L+13) +# define LPC17_IRQ_P2p14 (LPC17_VALID_FIRST2L+14) +# define LPC17_IRQ_P2p15 (LPC17_VALID_FIRST2L+15) +# define LPC17_VALID_NIRQS2L (16) + + /* Set 3: 16 interrupts p2.16 - p2.31 */ + +# define LPC17_VALID_SHIFT2H (15) +# define LPC17_VALID_FIRST2H (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L) + +# define LPC17_IRQ_P2p16 (LPC17_VALID_FIRST2H+0) +# define LPC17_IRQ_P2p17 (LPC17_VALID_FIRST2H+1) +# define LPC17_IRQ_P2p18 (LPC17_VALID_FIRST2H+2) +# define LPC17_IRQ_P2p19 (LPC17_VALID_FIRST2H+3) +# define LPC17_IRQ_P2p20 (LPC17_VALID_FIRST2H+4) +# define LPC17_IRQ_P2p21 (LPC17_VALID_FIRST2H+5) +# define LPC17_IRQ_P2p22 (LPC17_VALID_FIRST2H+6) +# define LPC17_IRQ_P2p23 (LPC17_VALID_FIRST2H+7) +# define LPC17_IRQ_P2p24 (LPC17_VALID_FIRST2H+8) +# define LPC17_IRQ_P2p25 (LPC17_VALID_FIRST2H+9) +# define LPC17_IRQ_P2p26 (LPC17_VALID_FIRST2H+10) +# define LPC17_IRQ_P2p27 (LPC17_VALID_FIRST2H+11) +# define LPC17_IRQ_P2p28 (LPC17_VALID_FIRST2H+12) +# define LPC17_IRQ_P2p29 (LPC17_VALID_FIRST2H+13) +# define LPC17_IRQ_P2p30 (LPC17_VALID_FIRST2H+14) +# define LPC17_IRQ_P2p31 (LPC17_VALID_FIRST2H+15) +# define LPC17_VALID_NIRQS2H (16) + +# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H) +#else +# define LPC17_NGPIOAIRQS (0) +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */ + diff --git a/nuttx/arch/arm/src/lpc17xx/Kconfig b/nuttx/arch/arm/src/lpc17xx/Kconfig index 8acd67595..b7dd7ac34 100644 --- a/nuttx/arch/arm/src/lpc17xx/Kconfig +++ b/nuttx/arch/arm/src/lpc17xx/Kconfig @@ -12,49 +12,101 @@ choice config ARCH_CHIP_LPC1751 bool "LPC1751" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1752 bool "LPC1752" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1754 bool "LPC1754" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1756 bool "LPC1756" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1758 bool "LPC1758" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1759 bool "LPC1759" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1764 bool "LPC1764" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1765 bool "LPC1765" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1766 bool "LPC1766" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1767 bool "LPC1767" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1768 bool "LPC1768" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1769 bool "LPC1769" + select ARCH_FAMILY_LPC176X + +config ARCH_CHIP_LPC1773 + bool "LPC1773" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1774 + bool "LPC1774" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1776 + bool "LPC1776" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1777 + bool "LPC1777" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1778 + bool "LPC1778" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1785 + bool "LPC1785" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1786 + bool "LPC1786" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1787 + bool "LPC1787" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1788 + bool "LPC1788" + select ARCH_FAMILY_LPC178X endchoice config ARCH_FAMILY_LPC175X bool - default y if ARCH_CHIP_LPC1751 || ARCH_CHIP_LPC1752 || ARCH_CHIP_LPC1754 || ARCH_CHIP_LPC1756 || ARCH_CHIP_LPC1758 || ARCH_CHIP_LPC1759 config ARCH_FAMILY_LPC176X bool - default y if ARCH_CHIP_LPC1764 || ARCH_CHIP_LPC1765 || ARCH_CHIP_LPC1766 || ARCH_CHIP_LPC1767 || ARCH_CHIP_LPC1768 || ARCH_CHIP_LPC1769 + +config ARCH_FAMILY_LPC177X + bool + +config ARCH_FAMILY_LPC178X + bool menu "LPC17xx Peripheral Support" diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index 982482017..60dda773d 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -41,159 +41,7 @@ ************************************************************************************/ #include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1767) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 0 /* No USB device controller */ -# define LPC17_NCAN 0 /* No CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1766) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1765) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1764) -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1759) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1758) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1756) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1754) -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1752) -# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */ -# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1751) -# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */ -# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */ -# define LPC17_CPUSRAM_SIZE (8*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#else -# error "Unsupported LPC17xx chip" -#endif +#include /* Include only the memory map. Other chip hardware files should then include this * file for the proper setup @@ -201,6 +49,10 @@ #include "lpc17_memorymap.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + /* NVIC priority levels *************************************************************/ /* Each priority field holds a priority value, 0-31. The lower the value, the greater * the priority of the corresponding interrupt. The processor implements only diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c index 76c446c7d..db6fbe1f8 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc17xx/lpc17_ssp.c * - * Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -926,4 +926,3 @@ void ssp_flush(FAR struct spi_dev_s *dev) } #endif /* CONFIG_LPC17_SSP0/1 */ - -- cgit v1.2.3