Add support for the MikroElektronika Mikromedia for STM32F4 development board. From Ken Petit

1 files changed, 151 insertions, 0 deletions

diff --git a/nuttx/configs/mikroe-stm32f4/src/up_clockconfig.c b/nuttx/configs/mikroe-stm32f4/src/up_clockconfig.c
new file mode 100644
index 000000000..8b4af3181
--- /dev/null
+++ b/nuttx/configs/mikroe-stm32f4/src/up_clockconfig.c
@@ -0,0 +1,151 @@
+/************************************************************************************
+ * configs/mikroe_stm32f4/src/up_clockconfig.c
+ *
+ *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "mikroe-stm32f4-internal.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_board_clockconfig
+ *
+ * Description:
+ *   The Mikroe-STM32F4 board does not have an external crystal, so it must rely
+ *   on the internal 16Mhz RC oscillator.  The default clock configuration in the
+ *   OS for the STM32 architecture assumes an external crystal, so we must provide
+ *   a board specific clock configuration routine.
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
+void stm32_board_clockconfig(void)
+{
+  uint32_t regval;
+
+  /* Configure chip clocking to use the internal 16Mhz RC oscillator.  
+
+    NOTE: We will assume the HSIRDY (High Speed Internal RC Ready) bit is 
+     set, otherwise we wouldn't be here executing code.  
+   */
+
+  regval  = getreg32(STM32_RCC_APB1ENR);
+  regval |= RCC_APB1ENR_PWREN;
+  putreg32(regval, STM32_RCC_APB1ENR);
+
+  regval  = getreg32(STM32_PWR_CR);
+  regval |= PWR_CR_VOS;
+  putreg32(regval, STM32_PWR_CR);
+
+  /* Set the HCLK source/divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_HPRE_MASK;
+  regval |= STM32_RCC_CFGR_HPRE;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PCLK2 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE2_MASK;
+  regval |= STM32_RCC_CFGR_PPRE2;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PCLK1 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE1_MASK;
+  regval |= STM32_RCC_CFGR_PPRE1;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PLL dividers and multiplers to configure the main PLL */
+
+  regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
+            RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
+  putreg32(regval, STM32_RCC_PLLCFG);
+
+  /* Enable the main PLL */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLLON;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the PLL is ready */
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
+      ;
+
+  /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
+
+#ifdef STM32_FLASH_PREFETCH
+  regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
+#else
+  regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
+#endif
+  putreg32(regval, STM32_FLASH_ACR);
+
+  /* Select the main PLL as system clock source */
+
+  regval  = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_SW_MASK;
+  regval |= RCC_CFGR_SW_PLL;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Wait until the PLL source is used as the system clock source */
+
+  while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
+      ;
+
+#endif
+}