From 780a3d631301f258f71cb1bd7035a33d527d046f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Jul 2014 13:25:59 -0600 Subject: SAMA5: Update slow clock logic. Things work a little differently on the SAMA5D3 --- nuttx/ChangeLog | 2 ++ nuttx/arch/arm/src/sama5/chip/sam_sckc.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 0a584acc4..e934c1175 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -7746,4 +7746,6 @@ (2014-7-18). * configs/sama5d4-ek/src/sam_wm8904.c: Add logic to configure and initialize the WM8904 audio CODEC (2014-7-17). + * arch/arm/src/sama5/sam_sckc.c/.h and chip/sam_sckc.h: Add SAMA5 + slow clock support. diff --git a/nuttx/arch/arm/src/sama5/chip/sam_sckc.h b/nuttx/arch/arm/src/sama5/chip/sam_sckc.h index 4cb70f9b8..e9071585a 100644 --- a/nuttx/arch/arm/src/sama5/chip/sam_sckc.h +++ b/nuttx/arch/arm/src/sama5/chip/sam_sckc.h @@ -58,6 +58,12 @@ /* Slow Clock Controller Configuration Register */ +#ifdef ATSAMA5D3 +# define SCKC_CR_RCEN (1 << 0) /* Bit 0: Internal 32 kHz RC Oscillator */ +# define SCKC_CR_OSC32EN (1 << 1) /* Bit 1: 32768 Hz Oscillator */ +# define SCKC_CR_OSC32BYP (1 << 2) /* Bit 2: 2768Hz Oscillator Bypass */ +#endif + #define SCKC_CR_OSCSEL (1 << 3) /* Bit 3: Slow Clock Selector */ #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SCKC_H */ -- cgit v1.2.3