From 8bd428e3c88f0f756ee639d9a1004084e70a1c53 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 6 Jun 2010 15:10:19 +0000 Subject: Add GPIO library functions git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2730 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/Make.defs | 4 +- nuttx/arch/arm/src/lpc17xx/lpc17_adc.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_can.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_dac.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c | 652 ++++++++++++++++++++++++++++ nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h | 44 +- nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_internal.h | 89 ++-- nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h | 24 +- nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_qei.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_rit.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_spi.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_timer.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_uart.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_usb.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h | 2 +- 24 files changed, 764 insertions(+), 87 deletions(-) create mode 100755 nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c diff --git a/nuttx/arch/arm/src/lpc17xx/Make.defs b/nuttx/arch/arm/src/lpc17xx/Make.defs index b6b1276e2..55ad5662c 100755 --- a/nuttx/arch/arm/src/lpc17xx/Make.defs +++ b/nuttx/arch/arm/src/lpc17xx/Make.defs @@ -51,9 +51,9 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ # Required SAM3U files CHIP_ASRCS = -CHIP_CSRCS = lpc17_start.c +CHIP_CSRCS = lpc17_gpio.c lpc17_start.c #CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpioirq.c \ -# lpc17_irq.c lpc17_lowputc.c lpc17_pio.c lpc17_serial.c \ +# lpc17_irq.c lpc17_lowputc.c lpc17_gpio.c lpc17_serial.c \ # lpc17_start.c lpc17_timerisr.c # Configuration-dependent SAM3U files diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h index 99ca45d18..93a3daad7 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_can.h b/nuttx/arch/arm/src/lpc17xx/lpc17_can.h index 270b64271..7bfaadf6e 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_can.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_can.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h index 4afa98b7b..18d008c63 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h index 29f7192b7..fe417346b 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h index b29163ec4..d4803eba5 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c new file mode 100755 index 000000000..2ee38de63 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c @@ -0,0 +1,652 @@ +/**************************************************************************** + * arch/arm/src/lpc17xx/lpc17_gpio.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip.h" +#include "lpc17_gpio.h" +#include "lpc17_pinconn.h" +#include "lpc17_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Default input pin configuration */ + +#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* We have to remember the configured interrupt setting.. PINs are not + * actually set up to interrupt until the interrupt is enabled. + */ + +#ifdef CONFIG_GPIO_IRQ +static uint32_t g_intedge0[2]; +static uint32_t g_intedge2[2]; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ +/* These tables have global scope because they are also used in + * lpc17_gpiodbg.c + */ + +const uint32_t g_fiobase[GPIO_NPORTS] = +{ + LPC17_FIO0_BASE, + LPC17_FIO1_BASE, + LPC17_FIO2_BASE, + LPC17_FIO3_BASE, + LPC17_FIO4_BASE +}; + +/* Port 0 and Port 2 can provide a single interrupt for any combination of + * port pins + */ + +const uint32_t g_intbase[GPIO_NPORTS] = +{ + LPC17_GPIOINT0_OFFSET, + 0, + LPC17_GPIOINT2_OFFSET, + 0, + 0 +}; + +const uint32_t g_lopinsel[GPIO_NPORTS] = +{ + LPC17_PINCONN_PINSEL0, + LPC17_PINCONN_PINSEL2, + LPC17_PINCONN_PINSEL4, + 0, + 0 +}; + +const uint32_t g_hipinsel[GPIO_NPORTS] = +{ + LPC17_PINCONN_PINSEL1, + LPC17_PINCONN_PINSEL3, + 0, + LPC17_PINCONN_PINSEL7, + LPC17_PINCONN_PINSEL9 +}; + +const uint32_t g_lopinmode[GPIO_NPORTS] = +{ + LPC17_PINCONN_PINMODE0, + LPC17_PINCONN_PINMODE2, + LPC17_PINCONN_PINMODE4, + 0, + 0 +}; + +const uint32_t g_hipinmode[GPIO_NPORTS] = +{ + LPC17_PINCONN_PINMODE1, + LPC17_PINCONN_PINMODE3, + 0, + LPC17_PINCONN_PINMODE7, + LPC17_PINCONN_PINMODE9 +}; + +const uint32_t g_odmode[GPIO_NPORTS] = +{ + LPC17_PINCONN_ODMODE0, + LPC17_PINCONN_ODMODE1, + LPC17_PINCONN_ODMODE2, + LPC17_PINCONN_ODMODE3, + LPC17_PINCONN_ODMODE4 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc17_pinsel + * + * Description: + * Get the address of the PINSEL register corresponding to this port and + * pin number. + * + ****************************************************************************/ + +static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value) +{ + const uint32_t *table; + uint32_t regaddr; + uint32_t regval; + unsigned int shift; + + /* Which table do we use */ + + if (pin < 16) + { + table = g_lopinsel; + shift = PINCONN_PINSELL_SHIFT(pin); + } + else + { + table = g_hipinsel; + shift = PINCONN_PINSELH_SHIFT(pin); + } + + /* Fetch the PINSEL register address for this port/pin combination */ + + regaddr = table[port]; + if (regaddr != 0) + { + /* Set the requested value in the PINSEL register */ + + regval = getreg32(regaddr); + regval &= ~(PINCONN_PINSEL_MASK << shift); + regval |= (value << shift); + putreg32(regval, regaddr); + return OK; + } + return -EINVAL; +} + +/**************************************************************************** + * Name: lpc17_pullup + * + * Description: + * Get the address of the PINMODE register corresponding to this port and + * pin number. + * + ****************************************************************************/ + +static int lpc17_pullup(uint16_t cfgset, unsigned int port, unsigned int pin) +{ + const uint32_t *table; + uint32_t regaddr; + uint32_t regval; + uint32_t value; + unsigned int shift; + + switch (cfgset & GPIO_PUMODE_MASK) + { + default: + case GPIO_PULLUP: /* Pull-up resistor enabled */ + value = PINCONN_PINMODE_PU; + break; + + case GPIO_REPEATER: /* Repeater mode enabled */ + value = PINCONN_PINMODE_RM; + break; + + case GPIO_PUNONE: /* Neither pull-up nor -down */ + value = PINCONN_PINMODE_PD; + break; + + case GPIO_PULLDN: /* Pull-down resistor enabled */ + value = PINCONN_PINMODE_MASK; + break; + } + + /* Which table do we use */ + + if (pin < 16) + { + table = g_lopinmode; + shift = PINCONN_PINMODEL_SHIFT(pin); + } + else + { + table = g_hipinmode; + shift = PINCONN_PINMODEH_SHIFT(pin); + } + + /* Fetch the PINSEL register address for this port/pin combination */ + + regaddr = table[port]; + if (regaddr != 0) + { + /* Set the requested value in the PINSEL register */ + + regval = getreg32(regaddr); + regval &= ~(PINCONN_PINMODE_MASK << shift); + regval |= (value << shift); + putreg32(regval, regaddr); + return OK; + } + return -EINVAL; +} + +/**************************************************************************** + * Name: lpc17_setintedge + * + * Description: + * Remember the configured interrupt edge. We can't actually enable the + * the edge interrupts until the called calls IRQ enabled function. + * + ****************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +static int lpc17_setintedge(unsigned int port, unsigned int pin, unsigned int value) +{ + const uint32_t *table; + uint32_t tabval; + unsigned int shift; + + /* Which word to we use? */ + + if (port == 0) + { + table = g_intedge0; + } + else if (port == 2) + { + table = g_intedge2; + } + else + { + return; + } + + if (pin >= 16) + { + table++; + pin -= 16; + } + + /* Set the requested value in the PINSEL register */ + + *table &= ~(3 << shift); + *table |= (value << shift); +} +#endif + +/**************************************************************************** + * Name: lpc17_setopendrain + * + * Description: + * Set the ODMODE register for open drain mode + * + ****************************************************************************/ + +static void lpc17_setopendrain(unsigned int port, unsigned int pin) +{ + uint32_t regaddr; + uint32_t regval; + + regaddr = g_odmode[port]; + regval = getreg32(regaddr); + regval |= (1 << pin); + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: lpc17_clropendrain + * + * Description: + * Reset the ODMODE register to disable open drain mode + * + ****************************************************************************/ + +static void lpc17_clropendrain(unsigned int port, unsigned int pin) +{ + uint32_t regaddr; + uint32_t regval; + + regaddr = g_odmode[port]; + regval = getreg32(regaddr); + regval &= ~(1 << pin); + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: lpc17_configinput + * + * Description: + * Configure a GPIO inpue pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline int lpc17_configinput(uint16_t cfgset, unsigned int port, unsigned int pin) +{ + uint32_t regval; + uint32_t fiobase; + uint32_t intbase; + uint32_t pinmask = (1 << pin); + + /* Set up FIO registers */ + + fiobase = g_fiobase[port]; + + /* Set as input */ + + regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET); + regval &= ~pinmask; + putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET); + + /* Set up interrupt registers */ + + intbase = g_intbase[port]; + if (intbase != 0) + { + /* Disable any rising edge interrupts */ + + regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET); + regval &= ~pinmask; + putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET); + + /* Disable any falling edge interrupts */ + + regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET); + regval &= ~pinmask; + putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET); + + /* Forget about any falling/rising edge interrupt enabled */ + +#ifdef CONFIG_GPIO_IRQ + lpc17_setintedge(port, pin, 0); +#endif + } + + /* Set up PINSEL registers */ + /* Configure as GPIO */ + + lpc17_pinsel(port, pin, PINCONN_PINSEL_GPIO); + + /* Set pull-up mode */ + + lpc17_pullup(cfgset, port, pin); + + /* Open drain only applies to outputs */ + + lpc17_clropendrain(port, pin); + return OK; +} + +/**************************************************************************** + * Name: lpc17_configinterrupt + * + * Description: + * Configure a GPIO interrupt pin based on bit-encoded description of the pin. + * + ****************************************************************************/ +static inline int lpc17_configinterrupt(uint16_t cfgset, unsigned int port, unsigned int pin) +{ + /* First, configure the port as a generic input so that we have a known + * starting point and consistent behavior during the re-configuration. + */ + + (void)lpc17_configinput(cfgset, port, pin); + + /* Then just remember the rising/falling edge interrupt enabled */ + + DEBUGASSERT(port == 0 || port == 2); +#ifdef CONFIG_GPIO_IRQ + lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT); +#endif + return OK; +} + +/**************************************************************************** + * Name: lpc17_configoutput + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + ****************************************************************************/ +static inline int lpc17_configoutput(uint16_t cfgset, unsigned int port, unsigned int pin) +{ + uint32_t fiobase; + uint32_t regval; + + /* First, configure the port as a generic input so that we have a known + * starting point and consistent behavior during the re-configuration. + */ + + (void)lpc17_configinput(DEFAULT_INPUT, port, pin); + + /* Now, reconfigure the pin as an output */ + + fiobase = g_fiobase[port]; + regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET); + regval |= (1 << pin); + putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET); + + /* Check for open drain output */ + + if ((cfgset & GPIO_OPEN_DRAIN) != 0) + { + /* Set pull-up mode. This normally only applies to input pins, but does have + * meaning if the port is an open drain output. + */ + + lpc17_pullup(cfgset, port, pin); + + /* Select open drain output */ + + lpc17_setopendrain(port, pin); + } + + /* Set the initial value of the output */ + + lpc17_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); + return OK; +} + +/**************************************************************************** + * Name: lpc17_configalternate + * + * Description: + * Configure a GPIO alternate function pin based on bit-encoded description + * of the pin. + * + ****************************************************************************/ +static int lpc17_configalternate(uint16_t cfgset, unsigned int port, unsigned int pin, uint32_t alt) +{ + /* First, configure the port as an input so that we have a known + * starting point and consistent behavior during the re-configuration. + */ + + (void)lpc17_configinput(DEFAULT_INPUT, port, pin); + + /* Set up PINSEL registers */ + /* Configure as GPIO */ + + lpc17_pinsel(port, pin, alt); + + /* Set pull-up mode */ + + lpc17_pullup(cfgset, port, pin); + + /* Check for open drain output */ + + if ((cfgset & GPIO_OPEN_DRAIN) != 0) + { + /* Select open drain output */ + + lpc17_setopendrain(port, pin); + } + return OK; +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc17_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lpc17_configgpio(uint16_t cfgset) +{ + unsigned int port; + unsigned int pin; + int ret = -EINVAL; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < GPIO_NPORTS) + { + /* Get the pin number and select the port configuration register for that pin */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Handle according to pin function */ + + switch (cfgset & GPIO_FUNC_MASK) + { + case GPIO_INPUT: /* GPIO input pin */ + ret = lpc17_configinput(cfgset, port, pin); + break; + + case GPIO_INTFE: /* GPIO interrupt falling edge */ + case GPIO_INTRE: /* GPIO interrupt rising edge */ + case GPIO_INTBOTH: /* GPIO interrupt both edges */ + ret = lpc17_configinterrupt(cfgset, port, pin); + break; + + case GPIO_OUTPUT: /* GPIO outpout pin */ + ret = lpc17_configoutput(cfgset, port, pin); + break; + + case GPIO_ALT1: /* Alternate function 1 */ + ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT1); + break; + + case GPIO_ALT2: /* Alternate function 2 */ + ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT2); + break; + + case GPIO_ALT3: /* Alternate function 3 */ + ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT3); + break; + + default: + break; + } + } + return ret; +} + +/**************************************************************************** + * Name: lpc17_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void lpc17_gpiowrite(uint16_t pinset, bool value) +{ + uint32_t fiobase; + uint32_t offset; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < GPIO_NPORTS) + { + /* Get the port base address */ + + fiobase = g_fiobase[port]; + + /* Get the pin number */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set or clear the output on the pin */ + + if (value) + { + offset = LPC17_FIO_SET_OFFSET; + } + else + offset = LPC17_FIO_CLR_OFFSET; + { + } + putreg32((1 << pin), fiobase + offset); + } +} + +/**************************************************************************** + * Name: lpc17_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lpc17_gpioread(uint16_t pinset) +{ + uint32_t fiobase; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < GPIO_NPORTS) + { + /* Get the port base address */ + + fiobase = g_fiobase[port]; + + /* Get the pin number and return the input state of that pin */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + return ((getreg32(fiobase + LPC17_FIO_PIN_OFFSET) & (1 << pin)) != 0); + } + return 0; +} diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h index 002954bfe..39fa161fc 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions @@ -66,7 +66,7 @@ /* GPIO interrupt block register offsets ********************************************/ -#define LPC17_GPIOINT(n) (0x10*(n) + 0x80) +#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80) #define LPC17_GPIOINT0_OFFSET 0x0080 #define LPC17_GPIOINT2_OFFSET 0x00a0 @@ -80,7 +80,7 @@ /* Register addresses ***************************************************************/ /* GPIO block register addresses ****************************************************/ -#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT(n)) +#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n)) #define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET) #define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET) #define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET) @@ -125,33 +125,33 @@ /* GPIO interrupt block register addresses ******************************************/ -#define LPC17_GPIOINT(n) (0x10*(n) + 0x80) -#define LPC17_GPIOINT0_OFFSET 0x0080 -#define LPC17_GPIOINT2_OFFSET 0x00a0 +#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n)) +#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET) +#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET) -#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_IOINTSTATUS_OFFSET) +#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET) -#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTENF_OFFSET) +#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET) /* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */ -#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTENF_OFFSET) +#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET) /* Pins P2.0-13 (P0.14-31 are reserved) */ -#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTENF_OFFSET) +#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET) /* Register bit definitions *********************************************************/ /* GPIO block register bit definitions **********************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h index 7859e68f6..f8e098959 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h b/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h index 563212c45..61651fa95 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h index afe6cca12..1dcc13849 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h @@ -58,30 +58,51 @@ /* Bit-encoded input to lpc17_configgpio() ******************************************/ -/* Encoding: FFMM OGGG PPPN NNNN +/* Encoding: FFFx MMOV PPPN NNNN * - * Pin Function: FF - * Pin Mode: MM (input pins) + * Pin Function: FFF + * Pin Mode bits: MM * Open drain: O (output pins) - * GPIO Mode bits: GGG + * Initial value: V (output pins) * Port number: PPP (0-4) * Pin number: NNNNN (0-31) */ - /* Pin Function: FF */ - -#define GPIO_FUNC_SHIFT (14) /* Bits 14-15: Pin function select */ -#define GPIO_FUNC_MASK (3 << GPIO_FUNC_SHIFT) -# define GPIO_PIN 0 (0 << GPIO_FUNC_SHIFT) -# define GPIO_ALT1 1 (1 << GPIO_FUNC_SHIFT) -# define GPIO_ALT2 2 (2 << GPIO_FUNC_SHIFT) -# define GPIO_ALT3 3 (3 << GPIO_FUNC_SHIFT) +/* Pin Function bits: FFF + * Only meaningful when the GPIO function is GPIO_PIN + */ + +#define GPIO_FUNC_SHIFT (13) /* Bits 13-15: GPIO mode */ +#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 000 GPIO input pin */ +# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 001 GPIO interrupt falling edge */ +# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 010 GPIO interrupt rising edge */ +# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 011 GPIO interrupt both edges */ +# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 100 GPIO outpout pin */ +# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 101 Alternate function 1 */ +# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 110 Alternate function 2 */ +# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 111 Alternate function 3 */ + +#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */ +#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) + +#define GPIO_INOUT_MASK GPIO_OUTPUT +#define GPIO_FE_MASK GPIO_INTFE +#define GPIO_RE_MASK GPIO_INTRE -#define GPIO_ISGPIO(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_PIN) +#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT) +#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT) +#define GPIO_ISINPUT(ps) ((ps) & GPIO_FUNC_MASK) == GPIO_INPUT) +#define GPIO_ISOUTPUT(ps) ((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT) +#define GPIO_ISINORINT(ps) ((ps) & GPIO_INOUT_MASK) == 0) +#define GPIO_ISOUTORALT(ps) ((ps) & GPIO_INOUT_MASK) != 0) +#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps)) +#define GPIO_ISFE(ps) ((ps) & GPIO_FE_MASK) != 0) +#define GPIO_ISRE(ps) ((ps) & GPIO_RE_MASK) != 0) /* Pin Mode: MM */ -#define GPIO_PUMODE_SHIFT (12) /* Bits 12-13: Pin pull-up mode */ +#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */ #define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT) # define GPIO_PULLUP (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */ # define GPIO_REPEATER (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */ @@ -90,29 +111,13 @@ /* Open drain: O */ -#define GPIO_OPEN_DRAIN (1 << 11) /* Bit 11: Open drain mode */ - -/* GPIO Mode bits: GGG - * Only meaningful when the GPIO function is GPIO_PIN - */ - -#define GPIO_GMODE_SHIFT (8) /* Bits 8-10: GPIO mode */ -#define GPIO_GMODE_MASK (7 << GPIO_GMODE_SHIFT) -# define GPIO_INPUT (0 << GPIO_GMODE_SHIFT) /* 000 GPIO input pin */ -# define GPIO_INTFE (1 << GPIO_GMODE_SHIFT) /* 001 GPIO interrupt falling edge */ -# define GPIO_INTRE (2 << GPIO_GMODE_SHIFT) /* 010 GPIO interrupt rising edge */ -# define GPIO_INTBOTH (3 << GPIO_GMODE_SHIFT) /* 011 GPIO interrupt both edges */ -# define GPIO_OUTPUT (4 << GPIO_GMODE_SHIFT) /* 100 GPIO outpout pin */ +#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */ -#define GPIO_OUTPUT_MASK GPIO_OUTPUT -#define GPIO_FE_MASK GPIO_INTFE -#define GPIO_RE_MASK GPIO_INTRE +/* Initial value: V */ -#define GPIO_ISINPUT(ps) ((ps) & GPIO_GMODE_MASK) == GPIO_INPUT) -#define GPIO_ISOUTPUT(ps) ((ps) & GPIO_OUTPUT_MASK) != 0) -#define GPIO_ISINTERRUPT(ps) (!GPIO_ISINPUT(ps) && !GPIO_ISOUTPUT(ps)) -#define GPIO_ISFE(ps) ((ps) & GPIO_FE_MASK) != 0) -#define GPIO_ISRE(ps) ((ps) & GPIO_RE_MASK) != 0) +#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */ +#define GPIO_VALUE_ONE GPIO_VALUE +#define GPIO_VALUE_ZERO (0) /* Port number: PPP (0-4) */ @@ -124,6 +129,8 @@ # define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) # define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) +#define GPIO_NPORTS 5 + /* Pin number: NNNNN (0-31) */ #define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ @@ -348,6 +355,18 @@ extern "C" { #define EXTERN extern #endif +/* These tables have global scope only because they are shared between lpc_gpio.c + * and lpc17_gpiodbg.c + */ + +extern const uint32_t g_fiobase[GPIO_NPORTS]; +extern const uint32_t g_intbase[GPIO_NPORTS]; +extern const uint32_t g_lopinsel[GPIO_NPORTS]; +extern const uint32_t g_hipinsel[GPIO_NPORTS]; +extern const uint32_t g_lopinmode[GPIO_NPORTS]; +extern const uint32_t g_hipinmode[GPIO_NPORTS]; +extern const uint32_t g_odmode[GPIO_NPORTS]; + /************************************************************************************ * Public Function Prototypes ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h b/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h index 2f01d356e..0d562854f 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h b/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h index 2673ab99b..3b3dbb837 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions @@ -106,6 +106,12 @@ /* Register bit definitions *********************************************************/ /* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ +#define PINCONN_PINSEL_GPIO (0) +#define PINCONN_PINSEL_ALT1 (1) +#define PINCONN_PINSEL_ALT2 (2) +#define PINCONN_PINSEL_ALT3 (3) +#define PINCONN_PINSEL_MASK (3) + #define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ #define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) #define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ @@ -457,21 +463,21 @@ #define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ #define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) #define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ -#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) +#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) #define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ -#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) +#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) #define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ -#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) +#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) #define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ -#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) +#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) #define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ -#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) +#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) #define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ -#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) +#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) #define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ -#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) +#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) #define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ -#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) +#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) #define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ #define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) /* Bits 28-31: Reserved */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h b/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h index 58a29910c..b689a0779 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h index 087e0b8ac..2c37051b1 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h b/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h index 32c54f519..57d89de95 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h index 70e56de87..e92ada029 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h index b970ca2a2..4f38517a0 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h index c421e1c2f..72f94b910 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h index b844f9c85..6f13726cc 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h b/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h index ec8a25570..03a85e32d 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h b/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h index 944f72e3b..5dfbfe160 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h b/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h index 4026c7a02..f50acbe00 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h @@ -44,7 +44,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h b/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h index c29f47bda..dc02b2e1d 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lp17_memorymap.h" +#include "lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions -- cgit v1.2.3