From 8c15b6f4e858b9c10e4fa7c933d0a129a4f63f20 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 2 Jul 2012 22:15:20 +0000 Subject: Add LPC43 Event Monitor, EEPROM, FLASH header files git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4898 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/lpc43xx/chip.h | 17 ++ nuttx/arch/arm/src/lpc43xx/chip.h | 34 ++-- .../arm/src/lpc43xx/chip/lpc4310203050_memorymap.h | 196 ++++++++++++++++++++ .../arm/src/lpc43xx/chip/lpc435357_memorymap.h | 200 +++++++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h | 6 +- nuttx/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h | 158 ++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h | 24 +-- nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h | 150 ++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_flash.h | 187 +++++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h | 195 -------------------- nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h | 141 +++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_timer.h | 3 - nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h | 1 - 13 files changed, 1081 insertions(+), 231 deletions(-) create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_flash.h delete mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h diff --git a/nuttx/arch/arm/include/lpc43xx/chip.h b/nuttx/arch/arm/include/lpc43xx/chip.h index 3e333571b..560420e28 100644 --- a/nuttx/arch/arm/include/lpc43xx/chip.h +++ b/nuttx/arch/arm/include/lpc43xx/chip.h @@ -119,6 +119,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (16*1024) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # undef LPC43_ETHERNET /* No Ethernet controller */ # undef LPC43_USB0 /* No USB0 (Host, Device, OTG) */ @@ -143,6 +144,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (16*1024) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # undef LPC43_ETHERNET /* No Ethernet controller */ # undef LPC43_USB0 /* No USB0 (Host, Device, OTG) */ @@ -168,6 +170,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (16*1024) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # undef LPC43_ETHERNET /* No Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -193,6 +196,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (16*1024) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # undef LPC43_ETHERNET /* No Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -217,6 +221,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -241,6 +246,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -265,6 +271,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -289,6 +296,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -313,6 +321,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # define LPC43_NLCD (1) /* One LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -337,6 +346,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # define LPC43_NLCD (1) /* One LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -361,6 +371,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # define LPC43_NLCD (1) /* One LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -385,6 +396,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -409,6 +421,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -433,6 +446,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -457,6 +471,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -481,6 +496,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ @@ -505,6 +521,7 @@ # define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) # define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ # define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip.h b/nuttx/arch/arm/src/lpc43xx/chip.h index 0733979ec..5b0918582 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip.h +++ b/nuttx/arch/arm/src/lpc43xx/chip.h @@ -52,71 +52,71 @@ */ #if defined(CONFIG_ARCH_CHIP_LPC4310FBD144) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4310fbd144_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4310FET100) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4310fet100_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4320FBD144) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4320fbd144_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4320FET100) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4320fet100_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4330fbd144_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4330FET100) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4330fet100_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4330FET180) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4330fet180_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4330FET256) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4330fet256_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4350fbd208_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4350FET180) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4350fet180_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4350FET256) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" # include "chip/lpc4350fet256_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc435357_memorymap.h" # include "chip/lpc4353fbd208_pinconfig.h" # include "chip/lpc4353fbd208_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4353FET180) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc435357_memorymap.h" # include "chip/lpc4353fet180_pinconfig.h" # include "chip/lpc4353fet180_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4353FET256) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc435357_memorymap.h" # include "chip/lpc4353fet256_pinconfig.h" # include "chip/lpc4353fet256_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4357FET180) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc435357_memorymap.h" # include "chip/lpc4357fet180_pinconfig.h" # include "chip/lpc4357fet180_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc435357_memorymap.h" # include "chip/lpc4357fbd208_pinconfig.h" # include "chip/lpc4357fbd208_vectors.h" #elif defined(CONFIG_ARCH_CHIP_LPC4357FET256) -# include "chip/lpc43_memorymap.h" +# include "chip/lpc435357_memorymap.h" # include "chip/lpc4357fet256_pinconfig.h" # include "chip/lpc4357fet256_vectors.h" #else diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h new file mode 100644 index 000000000..1cf9f5bad --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h @@ -0,0 +1,196 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ +/* See arch/arm/include/lpc43xx/chip.h for the actual sizes of FLASH and SRAM + * regions + */ + +#define LPC43_SHADOW_BASE 0x00000000 /* -0x0fffffff: 256Mb shadow area */ +#define LPC43_LOCSRAM_BASE 0x10000000 /* -0x1fffffff: Local SRAM and external memory */ +#define LPC43_AHBSRAM_BASE 0x20000000 /* -0x27ffffff: AHB SRAM */ +#define LPC43_DYCS0_BASE 0x28000000 /* -0x2fffffff: 128Mb dynamic external memory */ +#define LPC43_DYCS1_BASE 0x30000000 /* -0x2fffffff: 256Mb dynamic external memory */ +#define LPC43_PERIPH_BASE 0x40000000 /* -0x5fffffff: Peripherals */ +#define LPC43_DYCS2_BASE 0x60000000 /* -0x6fffffff: 256Mb dynamic external memory */ +#define LPC43_DYCS3_BASE 0x70000000 /* -0x7fffffff: 256Mb dynamic external memory */ +#define LPC43_SPIFI_DATA_BASE 0x80000000 /* -0x87ffffff: 256Mb dynamic external memory */ +#define LPC43_ARM_BASE 0xe0000000 /* -0xe00fffff: ARM private */ + +/* Local SRAM Banks and external memory */ + +#define LPC43_LOCSRAM_BANK0_BASE (LPC43_LOCSRAM_BASE + 0x00000000) +#define LPC43_LOCSRAM_BANK1_BASE (LPC43_LOCSRAM_BASE + 0x00080000) +#define LPC43_ROM_BASE (LPC43_LOCSRAM_BASE + 0x00400000) +#define LPC43_LOCSRAM_SPIFI_BASE (LPC43_LOCSRAM_BASE + 0x04000000) +#define LPC43_EXTMEM_CS0_BASE (LPC43_LOCSRAM_BASE + 0x0c000000) +#define LPC43_EXTMEM_CS1_BASE (LPC43_LOCSRAM_BASE + 0x0d000000) +#define LPC43_EXTMEM_CS2_BASE (LPC43_LOCSRAM_BASE + 0x0e000000) +#define LPC43_EXTMEM_CS3_BASE (LPC43_LOCSRAM_BASE + 0x0f000000) + +/* ROM Driver Table */ + +#define LPC43_ROM_DRIVER_TABLE (LPC43_ROM_BASE+0x00000100) +#define LPC43_ROM_DRIVER_TABLE0 (LPC43_ROM_DRIVER_TABLE+0x0000) +#define LPC43_ROM_DRIVER_TABLE1 (LPC43_ROM_DRIVER_TABLE+0x0004) +#define LPC43_ROM_DRIVER_TABLE2 (LPC43_ROM_DRIVER_TABLE+0x0008) +#define LPC43_ROM_DRIVER_TABLE3 (LPC43_ROM_DRIVER_TABLE+0x000c) +#define LPC43_ROM_DRIVER_TABLE4 (LPC43_ROM_DRIVER_TABLE+0x0010) +#define LPC43_ROM_DRIVER_TABLE5 (LPC43_ROM_DRIVER_TABLE+0x0014) +#define LPC43_ROM_DRIVER_TABLE6 (LPC43_ROM_DRIVER_TABLE+0x0018) +#define LPC43_ROM_DRIVER_TABLE7 (LPC43_ROM_DRIVER_TABLE+0x001c) + +/* AHB SRAM */ + +#define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE) +#define LPC43_AHBSRAM_BANK1_BASE (LPC43_AHBSRAM_BASE + 0x00008000) +#define LPC43_AHBSRAM_BANK2_BASE (LPC43_AHBSRAM_BASE + 0x0000c000) +#define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x0000c000) + +/* Peripherals */ + +#define LPC43_AHBPERIPH_BASE (LPC43_PERIPH_BASE + 0x00000000) +#define LPC43_RTCPERIPH_BASE (LPC43_PERIPH_BASE + 0x00040000) +#define LPC43_CLKPERIPH_BASE (LPC43_PERIPH_BASE + 0x00050000) +#define LPC43_APB0PERIPH_BASE (LPC43_PERIPH_BASE + 0x00080000) +#define LPC43_APB1PERIPH_BASE (LPC43_PERIPH_BASE + 0x000a0000) +#define LPC43_APB2PERIPH_BASE (LPC43_PERIPH_BASE + 0x000c0000) +#define LPC43_APB3PERIPH_BASE (LPC43_PERIPH_BASE + 0x000e0000) +#define LPC43_GPIO_BASE (LPC43_PERIPH_BASE + 0x000f4000) +#define LPC43_SPI_BASE (LPC43_PERIPH_BASE + 0x00100000) +#define LPC43_SGPIO_BASE (LPC43_PERIPH_BASE + 0x00101000) +#define LPC43_PERIPH_BITBAND_BASE (LPC43_PERIPH_BASE + 0x02000000) + +/* AHB Peripherals */ + +#define LPC43_SCT_BASE (LPC43_AHBPERIPH_BASE + 0x00000000) +#define LPC43_DMA_BASE (LPC43_AHBPERIPH_BASE + 0x00002000) +#define LPC43_SPIFI_PERIPH_BASE (LPC43_AHBPERIPH_BASE + 0x00003000) +#define LPC43_SDMMC_BASE (LPC43_AHBPERIPH_BASE + 0x00004000) +#define LPC43_EMC_BASE (LPC43_AHBPERIPH_BASE + 0x00005000) +#define LPC43_USB0_BASE (LPC43_AHBPERIPH_BASE + 0x00006000) +#define LPC43_USB1_BASE (LPC43_AHBPERIPH_BASE + 0x00007000) +#define LPC43_LCD_BASE (LPC43_AHBPERIPH_BASE + 0x00008000) +#define LPC43_ETHERNET_BASE (LPC43_AHBPERIPH_BASE + 0x00010000) + +/* RTC Domain Peripherals */ + +#define LPC43_ATIMER_BASE (LPC43_RTCPERIPH_BASE + 0x00000000) +#define LPC43_BACKUP_BASE (LPC43_RTCPERIPH_BASE + 0x00001000) +#define LPC43_PMC_BASE (LPC43_RTCPERIPH_BASE + 0x00002000) +#define LPC43_CREG_BASE (LPC43_RTCPERIPH_BASE + 0x00003000) +#define LPC43_EVNTRTR_BASE (LPC43_RTCPERIPH_BASE + 0x00004000) +#define LPC43_OTPC_BASE (LPC43_RTCPERIPH_BASE + 0x00005000) +#define LPC43_RTC_BASE (LPC43_RTCPERIPH_BASE + 0x00006000) +#define LPC43_EVNTMNTR_BASE (LPC43_RTC_BASE + 0x00000080) + +/* Clocking and Reset Peripherals */ + +#define LPC43_CGU_BASE (LPC43_CLKPERIPH_BASE + 0x00000000) +#define LPC43_CCU1_BASE (LPC43_CLKPERIPH_BASE + 0x00001000) +#define LPC43_CCU2_BASE (LPC43_CLKPERIPH_BASE + 0x00002000) +#define LPC43_RGU_BASE (LPC43_CLKPERIPH_BASE + 0x00003000) + +/* APB0 Peripherals */ + +#define LPC43_WWDT_BASE (LPC43_APB0PERIPH_BASE + 0x00000000) +#define LPC43_USART0_BASE (LPC43_APB0PERIPH_BASE + 0x00001000) +#define LPC43_UART1_BASE (LPC43_APB0PERIPH_BASE + 0x00002000) +#define LPC43_SSP0_BASE (LPC43_APB0PERIPH_BASE + 0x00003000) +#define LPC43_TIMER0_BASE (LPC43_APB0PERIPH_BASE + 0x00004000) +#define LPC43_TIMER1_BASE (LPC43_APB0PERIPH_BASE + 0x00005000) +#define LPC43_SCU_BASE (LPC43_APB0PERIPH_BASE + 0x00006000) +#define LPC43_GPIOINT_BASE (LPC43_APB0PERIPH_BASE + 0x00007000) +#define LPC43_GRP0INT_BASE (LPC43_APB0PERIPH_BASE + 0x00008000) +#define LPC43_GRP1INT_BASE (LPC43_APB0PERIPH_BASE + 0x00009000) + +/* APB1 Peripherals */ + +#define LPC43_MCPWM_BASE (LPC43_APB1PERIPH_BASE + 0x00000000) +#define LPC43_I2C0_BASE (LPC43_APB1PERIPH_BASE + 0x00001000) +#define LPC43_I2S0_BASE (LPC43_APB1PERIPH_BASE + 0x00002000) +#define LPC43_I2S1_BASE (LPC43_APB1PERIPH_BASE + 0x00003000) +#define LPC43_CAN1_BASE (LPC43_APB1PERIPH_BASE + 0x00004000) + +/* APB2 Peripherals */ + +#define LPC43_RIT_BASE (LPC43_APB2PERIPH_BASE + 0x00000000) +#define LPC43_USART2_BASE (LPC43_APB2PERIPH_BASE + 0x00001000) +#define LPC43_USART3_BASE (LPC43_APB2PERIPH_BASE + 0x00002000) +#define LPC43_TIMER2_BASE (LPC43_APB2PERIPH_BASE + 0x00003000) +#define LPC43_TIMER3_BASE (LPC43_APB2PERIPH_BASE + 0x00004000) +#define LPC43_SSP1_BASE (LPC43_APB2PERIPH_BASE + 0x00005000) +#define LPC43_QEI_BASE (LPC43_APB2PERIPH_BASE + 0x00006000) +#define LPC43_GIMA_BASE (LPC43_APB2PERIPH_BASE + 0x00007000) + +/* APB3 Peripherals */ + +#define LPC43_I2C1_BASE (LPC43_APB3PERIPH_BASE + 0x00000000) +#define LPC43_DAC_BASE (LPC43_APB3PERIPH_BASE + 0x00001000) +#define LPC43_CAN0_BASE (LPC43_APB3PERIPH_BASE + 0x00002000) +#define LPC43_ADC0_BASE (LPC43_APB3PERIPH_BASE + 0x00003000) +#define LPC43_ADC1_BASE (LPC43_APB3PERIPH_BASE + 0x00004000) + +/* ARM Private */ + +#define LPC43_SCS_BASE (LPC43_ARM_BASE + 0x0000e000) +#define LPC43_DEBUGMCU_BASE (LPC43_ARM_BASE + 0x00042000) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h new file mode 100644 index 000000000..10e563d3a --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h @@ -0,0 +1,200 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ +/* See arch/arm/include/lpc43xx/chip.h for the actual sizes of FLASH and SRAM + * regions + */ + +#define LPC43_SHADOW_BASE 0x00000000 /* -0x0fffffff: 256Mb shadow area */ +#define LPC43_LOCSRAM_BASE 0x10000000 /* -0x1fffffff: Local SRAM and external memory */ +#define LPC43_AHBSRAM_BASE 0x20000000 /* -0x27ffffff: AHB SRAM */ +#define LPC43_DYCS0_BASE 0x28000000 /* -0x2fffffff: 128Mb dynamic external memory */ +#define LPC43_DYCS1_BASE 0x30000000 /* -0x2fffffff: 256Mb dynamic external memory */ +#define LPC43_PERIPH_BASE 0x40000000 /* -0x5fffffff: Peripherals */ +#define LPC43_DYCS2_BASE 0x60000000 /* -0x6fffffff: 256Mb dynamic external memory */ +#define LPC43_DYCS3_BASE 0x70000000 /* -0x7fffffff: 256Mb dynamic external memory */ +#define LPC43_SPIFI_DATA_BASE 0x80000000 /* -0x87ffffff: 256Mb dynamic external memory */ +#define LPC43_ARM_BASE 0xe0000000 /* -0xe00fffff: ARM private */ + +/* Local SRAM Banks and external memory */ + +#define LPC43_LOCSRAM_BANK0_BASE (LPC43_LOCSRAM_BASE + 0x00000000) +#define LPC43_LOCSRAM_BANK1_BASE (LPC43_LOCSRAM_BASE + 0x00080000) +#define LPC43_ROM_BASE (LPC43_LOCSRAM_BASE + 0x00400000) +#define LPC43_LOCSRAM_SPIFI_BASE (LPC43_LOCSRAM_BASE + 0x04000000) +#define LPC43_LOCSRAM_FLASHA_BASE (LPC43_LOCSRAM_BASE + 0x0a000000) +#define LPC43_LOCSRAM_FLASHB_BASE (LPC43_LOCSRAM_BASE + 0x0b000000) +#define LPC43_EXTMEM_CS0_BASE (LPC43_LOCSRAM_BASE + 0x0c000000) +#define LPC43_EXTMEM_CS1_BASE (LPC43_LOCSRAM_BASE + 0x0d000000) +#define LPC43_EXTMEM_CS2_BASE (LPC43_LOCSRAM_BASE + 0x0e000000) +#define LPC43_EXTMEM_CS3_BASE (LPC43_LOCSRAM_BASE + 0x0f000000) + +/* ROM Driver Table */ + +#define LPC43_ROM_DRIVER_TABLE (LPC43_ROM_BASE+0x00000100) +#define LPC43_ROM_DRIVER_TABLE0 (LPC43_ROM_DRIVER_TABLE+0x0000) +#define LPC43_ROM_DRIVER_TABLE1 (LPC43_ROM_DRIVER_TABLE+0x0004) +#define LPC43_ROM_DRIVER_TABLE2 (LPC43_ROM_DRIVER_TABLE+0x0008) +#define LPC43_ROM_DRIVER_TABLE3 (LPC43_ROM_DRIVER_TABLE+0x000c) +#define LPC43_ROM_DRIVER_TABLE4 (LPC43_ROM_DRIVER_TABLE+0x0010) +#define LPC43_ROM_DRIVER_TABLE5 (LPC43_ROM_DRIVER_TABLE+0x0014) +#define LPC43_ROM_DRIVER_TABLE6 (LPC43_ROM_DRIVER_TABLE+0x0018) +#define LPC43_ROM_DRIVER_TABLE7 (LPC43_ROM_DRIVER_TABLE+0x001c) + +/* AHB SRAM */ + +#define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE) +#define LPC43_EEPROM_BASE (LPC43_AHBSRAM_BASE + 0x00004000) +#define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x02000000) + +/* Peripherals */ + +#define LPC43_AHBPERIPH_BASE (LPC43_PERIPH_BASE + 0x00000000) +#define LPC43_RTCPERIPH_BASE (LPC43_PERIPH_BASE + 0x00040000) +#define LPC43_CLKPERIPH_BASE (LPC43_PERIPH_BASE + 0x00050000) +#define LPC43_APB0PERIPH_BASE (LPC43_PERIPH_BASE + 0x00080000) +#define LPC43_APB1PERIPH_BASE (LPC43_PERIPH_BASE + 0x000a0000) +#define LPC43_APB2PERIPH_BASE (LPC43_PERIPH_BASE + 0x000c0000) +#define LPC43_APB3PERIPH_BASE (LPC43_PERIPH_BASE + 0x000e0000) +#define LPC43_GPIO_BASE (LPC43_PERIPH_BASE + 0x000f4000) +#define LPC43_SPI_BASE (LPC43_PERIPH_BASE + 0x00100000) +#define LPC43_SGPIO_BASE (LPC43_PERIPH_BASE + 0x00101000) +#define LPC43_PERIPH_BITBAND_BASE (LPC43_PERIPH_BASE + 0x02000000) + +/* AHB Peripherals */ + +#define LPC43_SCT_BASE (LPC43_AHBPERIPH_BASE + 0x00000000) +#define LPC43_DMA_BASE (LPC43_AHBPERIPH_BASE + 0x00002000) +#define LPC43_SPIFI_PERIPH_BASE (LPC43_AHBPERIPH_BASE + 0x00003000) +#define LPC43_SDMMC_BASE (LPC43_AHBPERIPH_BASE + 0x00004000) +#define LPC43_EMC_BASE (LPC43_AHBPERIPH_BASE + 0x00005000) +#define LPC43_USB0_BASE (LPC43_AHBPERIPH_BASE + 0x00006000) +#define LPC43_USB1_BASE (LPC43_AHBPERIPH_BASE + 0x00007000) +#define LPC43_LCD_BASE (LPC43_AHBPERIPH_BASE + 0x00008000) +#define LPC43_FLASHA_BASE (LPC43_AHBPERIPH_BASE + 0x0000c000) +#define LPC43_FLASHB_BASE (LPC43_AHBPERIPH_BASE + 0x0000d000) +#define LPC43_EEPROMC_BASE (LPC43_AHBPERIPH_BASE + 0x0000e000) +#define LPC43_ETHERNET_BASE (LPC43_AHBPERIPH_BASE + 0x00010000) + +/* RTC Domain Peripherals */ + +#define LPC43_ATIMER_BASE (LPC43_RTCPERIPH_BASE + 0x00000000) +#define LPC43_BACKUP_BASE (LPC43_RTCPERIPH_BASE + 0x00001000) +#define LPC43_PMC_BASE (LPC43_RTCPERIPH_BASE + 0x00002000) +#define LPC43_CREG_BASE (LPC43_RTCPERIPH_BASE + 0x00003000) +#define LPC43_EVNTRTR_BASE (LPC43_RTCPERIPH_BASE + 0x00004000) +#define LPC43_OTPC_BASE (LPC43_RTCPERIPH_BASE + 0x00005000) +#define LPC43_RTC_BASE (LPC43_RTCPERIPH_BASE + 0x00006000) +#define LPC43_EVNTMNTR_BASE (LPC43_RTC_BASE + 0x00000080) + +/* Clocking and Reset Peripherals */ + +#define LPC43_CGU_BASE (LPC43_CLKPERIPH_BASE + 0x00000000) +#define LPC43_CCU1_BASE (LPC43_CLKPERIPH_BASE + 0x00001000) +#define LPC43_CCU2_BASE (LPC43_CLKPERIPH_BASE + 0x00002000) +#define LPC43_RGU_BASE (LPC43_CLKPERIPH_BASE + 0x00003000) + +/* APB0 Peripherals */ + +#define LPC43_WWDT_BASE (LPC43_APB0PERIPH_BASE + 0x00000000) +#define LPC43_USART0_BASE (LPC43_APB0PERIPH_BASE + 0x00001000) +#define LPC43_UART1_BASE (LPC43_APB0PERIPH_BASE + 0x00002000) +#define LPC43_SSP0_BASE (LPC43_APB0PERIPH_BASE + 0x00003000) +#define LPC43_TIMER0_BASE (LPC43_APB0PERIPH_BASE + 0x00004000) +#define LPC43_TIMER1_BASE (LPC43_APB0PERIPH_BASE + 0x00005000) +#define LPC43_SCU_BASE (LPC43_APB0PERIPH_BASE + 0x00006000) +#define LPC43_GPIOINT_BASE (LPC43_APB0PERIPH_BASE + 0x00007000) +#define LPC43_GRP0INT_BASE (LPC43_APB0PERIPH_BASE + 0x00008000) +#define LPC43_GRP1INT_BASE (LPC43_APB0PERIPH_BASE + 0x00009000) + +/* APB1 Peripherals */ + +#define LPC43_MCPWM_BASE (LPC43_APB1PERIPH_BASE + 0x00000000) +#define LPC43_I2C0_BASE (LPC43_APB1PERIPH_BASE + 0x00001000) +#define LPC43_I2S0_BASE (LPC43_APB1PERIPH_BASE + 0x00002000) +#define LPC43_I2S1_BASE (LPC43_APB1PERIPH_BASE + 0x00003000) +#define LPC43_CAN1_BASE (LPC43_APB1PERIPH_BASE + 0x00004000) + +/* APB2 Peripherals */ + +#define LPC43_RIT_BASE (LPC43_APB2PERIPH_BASE + 0x00000000) +#define LPC43_USART2_BASE (LPC43_APB2PERIPH_BASE + 0x00001000) +#define LPC43_USART3_BASE (LPC43_APB2PERIPH_BASE + 0x00002000) +#define LPC43_TIMER2_BASE (LPC43_APB2PERIPH_BASE + 0x00003000) +#define LPC43_TIMER3_BASE (LPC43_APB2PERIPH_BASE + 0x00004000) +#define LPC43_SSP1_BASE (LPC43_APB2PERIPH_BASE + 0x00005000) +#define LPC43_QEI_BASE (LPC43_APB2PERIPH_BASE + 0x00006000) +#define LPC43_GIMA_BASE (LPC43_APB2PERIPH_BASE + 0x00007000) + +/* APB3 Peripherals */ + +#define LPC43_I2C1_BASE (LPC43_APB3PERIPH_BASE + 0x00000000) +#define LPC43_DAC_BASE (LPC43_APB3PERIPH_BASE + 0x00001000) +#define LPC43_CAN0_BASE (LPC43_APB3PERIPH_BASE + 0x00002000) +#define LPC43_ADC0_BASE (LPC43_APB3PERIPH_BASE + 0x00003000) +#define LPC43_ADC1_BASE (LPC43_APB3PERIPH_BASE + 0x00004000) + +/* ARM Private */ + +#define LPC43_SCS_BASE (LPC43_ARM_BASE + 0x0000e000) +#define LPC43_DEBUGMCU_BASE (LPC43_ARM_BASE + 0x00042000) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h index 43b623c87..74e53d616 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H -#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H /************************************************************************************ * Included Files @@ -107,4 +107,4 @@ struct lpc43_aes_s * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H */ +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h new file mode 100644 index 000000000..19391d479 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h @@ -0,0 +1,158 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/chip/lpc43_eeprom.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +/* EEPROM registers */ + +#define LPC43_EEPROM_CMD_OFFSET 0x000 /* EEPROM command register */ +#define LPC43_EEPROM_RWSTATE_OFFSET 0x008 /* EEPROM read wait state register */ +#define LPC43_EEPROM_AUTOPROG_OFFSET 0x00c /* EEPROM auto programming register */ +#define LPC43_EEPROM_WSTATE_OFFSET 0x010 /* EEPROM wait state register */ +#define LPC43_EEPROM_CLKDIV_OFFSET 0x014 /* EEPROM clock divider register */ +#define LPC43_EEPROM_PWRDWN_OFFSET 0x018 /* EEPROM power-down register */ + +/* EEPROM interrupt registers */ + +#define LPC43_EEPROM_INTENCLR_OFFSET 0xfd8 /* EEPROM interrupt enable clear */ +#define LPC43_EEPROM_INTENSET_OFFSET 0xfdc /* EEPROM interrupt enable set */ +#define LPC43_EEPROM_INTSTAT_OFFSET 0xfe0 /* EEPROM interrupt status */ +#define LPC43_EEPROM_INTEN_OFFSET 0xfe4 /* EEPROM interrupt enable */ +#define LPC43_EEPROM_INTSTATCLR_OFFSET 0xfe8 /* EEPROM interrupt status clear */ +#define LPC43_EEPROM_INTSTATSET_OFFSET 0xfec /* EEPROM interrupt status set */ + +/* Register Addresses ***************************************************************/ + +/* EEPROM registers */ + +#define LPC43_EEPROM_CMD (LPC43_EEPROMC_BASE+LPC43_EEPROM_CMD_OFFSET) +#define LPC43_EEPROM_RWSTATE (LPC43_EEPROMC_BASE+LPC43_EEPROM_RWSTATE_OFFSET) +#define LPC43_EEPROM_AUTOPROG (LPC43_EEPROMC_BASE+LPC43_EEPROM_AUTOPROG_OFFSET) +#define LPC43_EEPROM_WSTATE (LPC43_EEPROMC_BASE+LPC43_EEPROM_WSTATE_OFFSET) +# LPC43_EEPROM_CLKDIV (LPC43_EEPROMC_BASE+LPC43_EEPROM_CLKDIV_OFFSET) +#define LPC43_EEPROM_PWRDWN (LPC43_EEPROMC_BASE+LPC43_EEPROM_PWRDWN_OFFSET) + +/* EEPROM interrupt registers */ + +#define LPC43_EEPROM_INTENCLR (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTENCLR_OFFSET) +#define LPC43_EEPROM_INTENSET (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTENSET_OFFSET) +#define LPC43_EEPROM_INTSTAT (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTSTAT_OFFSET) +#define LPC43_EEPROM_INTEN (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTEN_OFFSET) +#define LPC43_EEPROM_INTSTATCLR (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTSTATCLR_OFFSET) +#define LPC43_EEPROM_INTSTATSET (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTSTATSET_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* EEPROM registers */ + +/* EEPROM command register */ + +#define EEPROM_CMD_SHIFT (0) /* Bits 0-2: Command */ +#define EEPROM_CMD_MASK (7 << EEPROM_CMD_SHIFT) +# define EEPROM_CMD_PROGRAM 6 /* 110=erase/program page */ + /* Bits 3-31: Reserved */ +/* EEPROM read wait state register */ + +#define EEPROM_RWSTATE_RPHASE2_SHIFT (0) /* Bits 0-7: Wait states 2 (minus 1) */ +#define EEPROM_RWSTATE_RPHASE2_MASK (0xff << EEPROM_RWSTATE_RPHASE2_SHIFT) +# define EEPROM_RWSTATE_RPHASE2(n) (((n)-1) << EEPROM_RWSTATE_RPHASE2_SHIFT) +#define EEPROM_RWSTATE_RPHASE1_SHIFT (8) /* Bits 8-15: Wait states 1 (minus 1) */ +#define EEPROM_RWSTATE_RPHASE1_MASK (0xff << EEPROM_RWSTATE_RPHASE1_SHIFT) +# define EEPROM_RWSTATE_RPHASE1(n) (((n)-1) << EEPROM_RWSTATE_RPHASE1_SHIFT) + /* Bits 16-31: Reserved */ +/* EEPROM auto programming register */ + +#define EEPROM_AUTOPROG_SHIFT (0) /* Bits 0-1: Auto programming mode */ +#define EEPROM_AUTOPROG_MASK (3 << EEPROM_AUTOPROG_SHIFT) +# define EEPROM_AUTOPROG_OFF (0 << EEPROM_AUTOPROG_SHIFT) /* auto programming off */ +# define EEPROM_AUTOPROG_FIRST (1 << EEPROM_AUTOPROG_SHIFT) /* erase/program cycle triggered by first word */ +# define EEPROM_AUTOPROG_LAST (2 << EEPROM_AUTOPROG_SHIFT) /* erase/program cycle triggered by last word */ + /* Bits 2-31: Reserved */ +/* EEPROM wait state register */ + +#define EEPROM_WSTATE_PHASE3_SHIFT (0) /* Bits 0-7: Wait states for phase 3 (minus 1) */ +#define EEPROM_WSTATE_PHASE3_MASK (0xff << EEPROM_WSTATE_PHASE3_SHIFT) +#define EEPROM_WSTATE_PHASE2_SHIFT (8) /* Bits 8-15: Wait states for phase 2 (minus 1) */ +#define EEPROM_WSTATE_PHASE2_MASK (0xff << EEPROM_WSTATE_PHASE2_SHIFT) +#define EEPROM_WSTATE_PHASE1_SHIFT (16) /* Bits 16-23: Wait states for phase 1 (minus 1) */ +#define EEPROM_WSTATE_PHASE1_MASK (0xff << EEPROM_WSTATE_PHASE1_SHIFT) + /* Bits 24-30: Reserved */ +#define EEPROM_WSTATE_LCK_PARWEP (1 << 31) /* Bit 31: Lock for write, erase and program */ + +/* EEPROM clock divider register */ + +#define EEPROM_CLKDIV_MASK (0xffff) /* Bits 0-15: Division factor (minus 1) */ +#define EEPROM_CLKDIV(n) ((n)-1) /* Bits 0-15: Division factor (minus 1) */ + /* Bits 16-31: Reserved */ +/* EEPROM power-down register */ + +#define EEPROM_PWRDWN (1 << 0) /* Bit 0: Power down mode bit */ + /* Bits 1-31: Reserved */ +/* EEPROM interrupt registers */ +/* EEPROM interrupt enable clear */ +/* EEPROM interrupt enable set */ +/* EEPROM interrupt status */ +/* EEPROM interrupt enable */ +/* EEPROM interrupt status clear */ +/* EEPROM interrupt status set */ + /* Bits 0-1: Reserved */ +#define EEPROM_INT_ENDOFPROG (1 << 2) /* Bit 2: Program operation finished interrupt */ + /* Bits 3-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h index 95f6da871..e7d16fe26 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h @@ -575,19 +575,19 @@ #define ETH_RDES4_IPV6 (1 << 7) /* Bit 7: IPv6 packet received */ #define ETH_RDES4_MT_SHIFT (8) /* Bits 8-11: Message type */ #define ETH_RDES4_MT_MASK (15 << ETH_RDES4_MT_SHIFT) -# define ETH_RDES4_MT_NONE (0 << ETH_RDES4_MT_SHIFT) /* No PTP message received */ -# define ETH_RDES4_MT_SYNC (1 << ETH_RDES4_MT_SHIFT) /* SYNC (all clock types) */ -# define ETH_RDES4_MT_FOLLOWUP (2 << ETH_RDES4_MT_SHIFT) /* Follow_Up (all clock types) */ -# define ETH_RDES4_MT_DELAYREQ (3 << ETH_RDES4_MT_SHIFT) /* Delay_Req (all clock types) */ -# define ETH_RDES4_MT_DELAYRESP (4 << ETH_RDES4_MT_SHIFT) /* Delay_Resp (all clock types) */ -# define ETH_RDES4_MT_PDELREQAM (5 << ETH_RDES4_MT_SHIFT) /* Pdelay_Req (in peer-to-peer - * transparent clock) */ -# define ETH_RDES4_MT_PDELREQMM (6 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp (in peer-to-peer - * transparent clock) */ -# define ETH_RDES4_MT_PDELREQFUS (7 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp_Follow_Up (in +# define ETH_RDES4_MT_NONE (0 << ETH_RDES4_MT_SHIFT) /* No PTP message received */ +# define ETH_RDES4_MT_SYNC (1 << ETH_RDES4_MT_SHIFT) /* SYNC (all clock types) */ +# define ETH_RDES4_MT_FOLLOWUP (2 << ETH_RDES4_MT_SHIFT) /* Follow_Up (all clock types) */ +# define ETH_RDES4_MT_DELAYREQ (3 << ETH_RDES4_MT_SHIFT) /* Delay_Req (all clock types) */ +# define ETH_RDES4_MT_DELAYRESP (4 << ETH_RDES4_MT_SHIFT) /* Delay_Resp (all clock types) */ +# define ETH_RDES4_MT_PDELREQAM (5 << ETH_RDES4_MT_SHIFT) /* Pdelay_Req (in peer-to-peer + * transparent clock) */ +# define ETH_RDES4_MT_PDELREQMM (6 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp (in peer-to-peer + * transparent clock) */ +# define ETH_RDES4_MT_PDELREQFUS (7 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp_Follow_Up (in * peer-to-peer transparent clock) */ -# define ETH_RDES4_MT_PDELREQFUS (8 << ETH_RDES4_MT_SHIFT) /* Announce */ -# define ETH_RDES4_MT_PDELREQFUS (9 << ETH_RDES4_MT_SHIFT) /* Management */ +# define ETH_RDES4_MT_PDELREQFUS (8 << ETH_RDES4_MT_SHIFT) /* Announce */ +# define ETH_RDES4_MT_PDELREQFUS (9 << ETH_RDES4_MT_SHIFT) /* Management */ # define ETH_RDES4_MT_PDELREQFUS (10 << ETH_RDES4_MT_SHIFT) /* Signaling */ # define ETH_RDES4_MT_PDELREQFUS (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */ #define ETH_RDES4_PTPTYPE (1 << 12) /* Bit 12: PTP frame type */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h new file mode 100644 index 000000000..a12112ece --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h @@ -0,0 +1,150 @@ +/**************************************************************************************************** + * arch/arm/src/lpc43xx/chip/lpc43_eventmntr.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ +/* Register Offsets *********************************************************************************/ + +#define LPC43_EMR_CONTROL_OFFSET 0x0004 /* Event Monitor/Recorder Control register */ +#define LPC43_EMR_STATUS_OFFSET 0x0000 /* Event Monitor/Recorder Status register */ +#define LPC43_EMR_COUNTERS_OFFSET 0x0008 /* Event Monitor/Recorder Counters register */ + +#define LPC43_EMR_FIRSTSTAMP_OFFSET(n) (0x0010 + ((n) << 2)) +#define LPC43_EMR_FIRSTSTAMP0_OFFSET 0x0010 /* Event Monitor/Recorder First Stamp register Ch0 */ +#define LPC43_EMR_FIRSTSTAMP1_OFFSET 0x0014 /* Event Monitor/Recorder First Stamp register Ch1 */ +#define LPC43_EMR_FIRSTSTAMP2_OFFSET 0x0018 /* Event Monitor/Recorder First Stamp register Ch2 */ + +#define LPC43_EMR_LASTSTAMP_OFFSET(n) (0x0020 + ((n) << 2)) +#define LPC43_EMR_LASTSTAMP0_OFFSET 0x0020 /* Event Monitor/Recorder Last Stamp register Ch0 */ +#define LPC43_EMR_LASTSTAMP1_OFFSET 0x0024 /* Event Monitor/Recorder Last Stamp register Ch1 */ +#define LPC43_EMR_LASTSTAMP2_OFFSET 0x0028 /* Event Monitor/Recorder Last Stamp register Ch2 */ + +/* Register Addresses *******************************************************************************/ + +#define LPC43_EMR_CONTROL (LPC43_EVNTMNTR_BASE+LPC43_EMR_CONTROL_OFFSET) +#define LPC43_EMR_STATUS (LPC43_EVNTMNTR_BASE+LPC43_EMR_STATUS_OFFSET) +#define LPC43_EMR_COUNTERS (LPC43_EVNTMNTR_BASE+LPC43_EMR_COUNTERS_OFFSET) + +#define LPC43_EMR_FIRSTSTAMP(n) (LPC43_EVNTMNTR_BASE+LPC43_EMR_FIRSTSTAMP_OFFSET(n)) +#define LPC43_EMR_FIRSTSTAMP0 (LPC43_EVNTMNTR_BASE+LPC43_EMR_FIRSTSTAMP0_OFFSET) +#define LPC43_EMR_FIRSTSTAMP1 (LPC43_EVNTMNTR_BASE+LPC43_EMR_FIRSTSTAMP1_OFFSET) +#define LPC43_EMR_FIRSTSTAMP2 (LPC43_EVNTMNTR_BASE+LPC43_EMR_FIRSTSTAMP2_OFFSET) + +#define LPC43_EMR_LASTSTAMP(n) (LPC43_EVNTMNTR_BASE+LPC43_EMR_LASTSTAMP_OFFSET(n)) +#define LPC43_EMR_LASTSTAMP0 (LPC43_EVNTMNTR_BASE+LPC43_EMR_LASTSTAMP0_OFFSET) +#define LPC43_EMR_LASTSTAMP1 (LPC43_EVNTMNTR_BASE+LPC43_EMR_LASTSTAMP1_OFFSET) +#define LPC43_EMR_LASTSTAMP2 (LPC43_EVNTMNTR_BASE+LPC43_EMR_LASTSTAMP2_OFFSET) + +/* Register Bit Definitions *************************************************************************/ + +/* Event Monitor/Recorder Control register */ + +#define EMR_CONTROL_INTWAKE_EN0 (1 << 0) /* Bit 0: Interrupt and wakeup enable Ch0 */ +#define EMR_CONTROL_GPCLEAR_EN0 (1 << 1) /* Bit 1: Enables auto clearing of RTC GP regs Ch0 */ +#define EMR_CONTROL_POL0 (1 << 2) /* Bit 2: Selects polarity of input pin WAKEUP0 */ +#define EMR_CONTROL_EV0_INPUT_EN (1 << 3) /* Bit 3: Event enable control Ch0 */ + /* Bits 4-9: Reserved */ +#define EMR_CONTROL_INTWAKE_EN1 (1 << 10) /* Bit 10: Interrupt and wakeup enable Ch1 */ +#define EMR_CONTROL_GPCLEAR_EN1 (1 << 11) /* Bit 11: Enables auto clearing the RTC GP regs Ch1 */ +#define EMR_CONTROL_POL1 (1 << 12) /* Bit 12: Selects polarity of input pin WAKEUP1 */ +#define EMR_CONTROL_EV1_INPUT_EN (1 << 13) /* Bit 13: Event enable control Ch1 */ + /* Bits 14-19: Reserved */ +#define EMR_CONTROL_INTWAKE_EN2 (1 << 20) /* Bit 20: Interrupt and wakeup enable Ch2 */ +#define EMR_CONTROL_GPCLEAR_EN2 (1 << 21) /* Bit 21: Enables auto clearing of RTC GP regs Ch2 */ +#define EMR_CONTROL_POL2 (1 << 22) /* Bit 22: Selects polarity of input pin WAKEUP2 */ +#define EMR_CONTROL_EV2_INPUT_EN (1 << 23) /* Bit 23: Event enable control Ch2 */ + /* Bits 24-29: Reserved */ +#define EMR_CONTROL_ERMODE_SHIFT (30) /* Bits 30-31: Enable Event Monitor/Recorder */ +#define EMR_CONTROL_ERMODE_MASK (3 << EMR_CONTROL_ERMODE_SHIFT) +# define EMR_CONTROL_ERMODE_DISABLE (0 << EMR_CONTROL_ERMODE_SHIFT) /* Disable Event Monitor/Recorder clocks */ +# define EMR_CONTROL_ERMODE_16Hz (1 << EMR_CONTROL_ERMODE_SHIFT) /* 16 Hz sample clock */ +# define EMR_CONTROL_ERMODE_64Hz (2 << EMR_CONTROL_ERMODE_SHIFT) /* 64 Hz sample clock */ +# define EMR_CONTROL_ERMODE_1KHz (3 << EMR_CONTROL_ERMODE_SHIFT) /* 1 kHz sample clock */ + +/* Event Monitor/Recorder Status register */ + +#define EMR_STATUS_EV0 (1 << 0) /* Bit 0: Channel0 event flag (WAKEUP0 pin) */ +#define EMR_STATUS_EV1 (1 << 1) /* Bit 1: Channel1 Event flag (WAKEUP1 pin) */ +#define EMR_STATUS_EV2 (1 << 2) /* Bit 2: Channel2 Event flag (WAKEUP2 pin) */ +#define EMR_STATUS_GPCLR (1 << 3) /* Bit 3: General purpose register asynchronous clear flag */ + /* Bits 4-30: Reserved */ +#define EMR_STATUS_WAKEUP (1 << 31) /* Bit 31: WAKEUP Interrupt/wakeup request flag */ + +/* Event Monitor/Recorder Counters register */ + +#define EMR_COUNTERS_COUNTER0_SHIFT (0) /* Bits 0-2: Value of the counter for Event 0 */ +#define EMR_COUNTERS_COUNTER0_MASK (7 << EMR_COUNTERS_COUNTER0_SHIFT) + /* Bits 3-7: Reserved */ +#define EMR_COUNTERS_COUNTER1_SHIFT (8) /* Bits 8-10: Value of the counter for event 1 */ +#define EMR_COUNTERS_COUNTER1_MASK (8 << EMR_COUNTERS_COUNTER1_SHIFT) + /* Bits 11-15: Reserved */ +#define EMR_COUNTERS_COUNTER2_SHIFT (16) /* Bits 16-18: Value of the counter for event 2 */ +#define EMR_COUNTERS_COUNTER2_MASK (7 << EMR_COUNTERS_COUNTER2_SHIFT) + /* Bits 19-31: Reserved */ +/* Event Monitor/Recorder First/Last Stamp registers */ + +#define EMR_STAMP_SEC_SHIFT (0) /* Bits 0-5: Seconds value 0-59 */ +#define EMR_STAMP_SEC_MASK (63 << EMR_STAMP_SEC_SHIFT) +#define EMR_STAMP_MIN_SHIFT (6) /* Bits 6-11: Minutes value 0-59 */ +#define EMR_STAMP_MIN_MASK (63 << EMR_STAMP_MIN_SHIFT) +#define EMR_STAMP_HOUR_SHIFT (12) /* Bits 12-16: Hours value 0-23 */ +#define EMR_STAMP_HOUR_MASK (31 << EMR_STAMP_HOUR_SHIFT) +#define EMR_STAMP_DOY_SHIFT (17) /* Bits 17-25: Day of Year value1-366 */ +#define EMR_STAMP_DOY_MASK (511 << EMR_STAMP_DOY_SHIFT) + /* Bits 26-31: Reserved */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_flash.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_flash.h new file mode 100644 index 000000000..4f99484da --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_flash.h @@ -0,0 +1,187 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/chip/lpc43_flash.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* The AES is controlled through a set of simple API calls located in the LPC43xx + * ROM. This value holds the pointer to the AES driver table. + */ + +#define LPC43_ROM_IAP_DRIVER_TABLE LPC43_ROM_DRIVER_TABLE0 + +#define IAP_LOCATION *(volatile unsigned int *)LPC43_ROM_IAP_DRIVER_TABLE; + +/* General usage: + * + * Declare a function pointer in your code like: + * + * iap_t iap = (iap_t)IAP_LOCATION; + * + * Then call the IAP using the function pointe like: + * + * unsigned long command[6]; + * unsigned long result[5]; + * ... + * iap(command, result); + */ + +/* IAP Commands + * + * See tables 1042-1053 in the "LPC43xx User Manual" (UM10503), Rev. 1.2, 8 June + * 2012, NXP for definitions descriptions of each IAP command. + */ + +#define IAP_INIT 49 /* Initialization */ +#define IAP_WRITE_PREPARE 50 /* Prepare sectors for write operation */ +#define IAP_WRITE 51 /* Copy RAM to Flash */ +#define IAP_ERASE_SECTOR 52 /* Erase sectors */ +#define IAP_BLANK_CHECK 53 /* Blank check sectors */ +#define IAP_PART_ID 54 /* Read part ID */ +#define IAP_BOOT_VERSION 55 /* Read Boot Code version */ +#define IAP_SERIAL_NUMBER 58 /* Read device serial number */ +#define IAP_COMPARE 56 /* Compare */ +#define IAP_REINVOKE 57 /* Reinvoke ISP */ +#define IAP_ERASE_PAGE 59 /* Erase page */ +#define IAP_SET_BANK 60 /* Set active boot flash bank */ + +/* ISP/IAP return codes */ + +/* Command is executed successfully. Sent by ISP handler only when command given by + * the host has been completely and successfully executed. + */ + +#define CMD_SUCCESS 0 + +/* Invalid command */ + +#define INVALID_COMMAND + +/* Source address is not on word boundary. */ + +#define SRC_ADDR_ERROR 2 + +/* Destination address not on word or 256 byte boundary. */ + +#define DST_ADDR_ERROR 3 + +/* Source address is not mapped in the memory map. Count value is taken into + * consideration where applicable. + */ + +#define SRC_ADDR_NOT_MAPPED 4 + +/* Destination address is not mapped in the memory map. Count value is taken into + * consideration where applicable. + */ + +#define DST_ADDR_NOT_MAPPED 5 + +/* Byte count is not multiple of 4 or is not a permitted value. */ + +#define COUNT_ERROR 6 + +/* Sector number is invalid or end sector number is greater than start sector number. */ + +#define INVALID_SECTOR 7 + +/* Sector is not blank. */ + +#define SECTOR_NOT_BLANK 8 + +/* Command to prepare sector for write operation was not executed. */ + +#define SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION 9 + +/* Source and destination data not equal. */ + +#define COMPARE_ERROR 10 + +/* Flash programming hardware interface is busy. */ + +#define BUSY 11 + +/* Insufficient number of parameters or invalid parameter. */ + +#define PARAM_ERROR 12 + +/* Address is not on word boundary. */ + +#define ADDR_ERROR 13 + +/* Address is not mapped in the memory map. Count value is taken in to consideration + * where applicable. + */ + +#define ADDR_NOT_MAPPED 14 + +/* Command is locked. */ + +#define CMD_LOCKED 15 + +/* Unlock code is invalid. */ + +#define INVALID_CODE 16 + +/* Invalid baud rate setting. */ + +#define INVALID_BAUD_RATE 17 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* IAP function pointer */ + +typedef void (*iap_t)(unsigned int *cmd, unsigned int *result); + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h deleted file mode 100644 index 120d87223..000000000 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_memorymap.h +++ /dev/null @@ -1,195 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc43xx/chip/lpc43_memorymap.h - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H -#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory Map ***********************************************************************/ -/* See arch/arm/include/lpc43xx/chip.h for the actual sizes of FLASH and SRAM - * regions - */ - -#define LPC43_SHADOW_BASE 0x00000000 /* -0x0fffffff: 256Mb shadow area */ -#define LPC43_LOCSRAM_BASE 0x10000000 /* -0x1fffffff: Local SRAM and external memory */ -#define LPC43_AHBSRAM_BASE 0x20000000 /* -0x27ffffff: AHB SRAM */ -#define LPC43_DYCS0_BASE 0x28000000 /* -0x2fffffff: 128Mb dynamic external memory */ -#define LPC43_DYCS1_BASE 0x30000000 /* -0x2fffffff: 256Mb dynamic external memory */ -#define LPC43_PERIPH_BASE 0x40000000 /* -0x5fffffff: Peripherals */ -#define LPC43_DYCS2_BASE 0x60000000 /* -0x6fffffff: 256Mb dynamic external memory */ -#define LPC43_DYCS3_BASE 0x70000000 /* -0x7fffffff: 256Mb dynamic external memory */ -#define LPC43_SPIFI_DATA_BASE 0x80000000 /* -0x87ffffff: 256Mb dynamic external memory */ -#define LPC43_ARM_BASE 0xe0000000 /* -0xe00fffff: ARM private */ - -/* Local SRAM Banks and external memory */ - -#define LPC43_LOCSRAM_BANK0_BASE (LPC43_LOCSRAM_BASE + 0x00000000) -#define LPC43_LOCSRAM_BANK1_BASE (LPC43_LOCSRAM_BASE + 0x00080000) -#define LPC43_ROM_BASE (LPC43_LOCSRAM_BASE + 0x00400000) -#define LPC43_LOCSRAM_SPIFI_BASE (LPC43_LOCSRAM_BASE + 0x04000000) -#define LPC43_EXTMEM_CS0_BASE (LPC43_LOCSRAM_BASE + 0x0c000000) -#define LPC43_EXTMEM_CS1_BASE (LPC43_LOCSRAM_BASE + 0x0d000000) -#define LPC43_EXTMEM_CS2_BASE (LPC43_LOCSRAM_BASE + 0x0e000000) -#define LPC43_EXTMEM_CS3_BASE (LPC43_LOCSRAM_BASE + 0x0f000000) - -/* ROM Driver Table */ - -#define LPC43_ROM_DRIVER_TABLE (LPC43_ROM_BASE+0x00000100) -#define LPC43_ROM_DRIVER_TABLE0 (LPC43_ROM_DRIVER_TABLE+0x0000) -#define LPC43_ROM_DRIVER_TABLE1 (LPC43_ROM_DRIVER_TABLE+0x0004) -#define LPC43_ROM_DRIVER_TABLE2 (LPC43_ROM_DRIVER_TABLE+0x0008) -#define LPC43_ROM_DRIVER_TABLE3 (LPC43_ROM_DRIVER_TABLE+0x000c) -#define LPC43_ROM_DRIVER_TABLE4 (LPC43_ROM_DRIVER_TABLE+0x0010) -#define LPC43_ROM_DRIVER_TABLE5 (LPC43_ROM_DRIVER_TABLE+0x0014) -#define LPC43_ROM_DRIVER_TABLE6 (LPC43_ROM_DRIVER_TABLE+0x0018) -#define LPC43_ROM_DRIVER_TABLE7 (LPC43_ROM_DRIVER_TABLE+0x001c) - -/* AHB SRAM */ - -#define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE) -#define LPC43_AHBSRAM_BANK1_BASE (LPC43_AHBSRAM_BASE + 0x00008000) -#define LPC43_AHBSRAM_BANK2_BASE (LPC43_AHBSRAM_BASE + 0x0000c000) -#define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x0000c000) - -/* Peripherals */ - -#define LPC43_AHBPERIPH_BASE (LPC43_PERIPH_BASE + 0x00000000) -#define LPC43_RTCPERIPH_BASE (LPC43_PERIPH_BASE + 0x00040000) -#define LPC43_CLKPERIPH_BASE (LPC43_PERIPH_BASE + 0x00050000) -#define LPC43_APB0PERIPH_BASE (LPC43_PERIPH_BASE + 0x00080000) -#define LPC43_APB1PERIPH_BASE (LPC43_PERIPH_BASE + 0x000a0000) -#define LPC43_APB2PERIPH_BASE (LPC43_PERIPH_BASE + 0x000c0000) -#define LPC43_APB3PERIPH_BASE (LPC43_PERIPH_BASE + 0x000e0000) -#define LPC43_GPIO_BASE (LPC43_PERIPH_BASE + 0x000f4000) -#define LPC43_SPI_BASE (LPC43_PERIPH_BASE + 0x00100000) -#define LPC43_SGPIO_BASE (LPC43_PERIPH_BASE + 0x00101000) -#define LPC43_PERIPH_BITBAND_BASE (LPC43_PERIPH_BASE + 0x02000000) - -/* AHB Peripherals */ - -#define LPC43_SCT_BASE (LPC43_AHBPERIPH_BASE + 0x00000000) -#define LPC43_DMA_BASE (LPC43_AHBPERIPH_BASE + 0x00002000) -#define LPC43_SPIFI_PERIPH_BASE (LPC43_AHBPERIPH_BASE + 0x00003000) -#define LPC43_SDMMC_BASE (LPC43_AHBPERIPH_BASE + 0x00004000) -#define LPC43_EMC_BASE (LPC43_AHBPERIPH_BASE + 0x00005000) -#define LPC43_USB0_BASE (LPC43_AHBPERIPH_BASE + 0x00006000) -#define LPC43_USB1_BASE (LPC43_AHBPERIPH_BASE + 0x00007000) -#define LPC43_LCD_BASE (LPC43_AHBPERIPH_BASE + 0x00008000) -#define LPC43_ETHERNET_BASE (LPC43_AHBPERIPH_BASE + 0x00010000) - -/* RTC Domain Peripherals */ - -#define LPC43_ATIMER_BASE (LPC43_RTCPERIPH_BASE + 0x00000000) -#define LPC43_BACKUP_BASE (LPC43_RTCPERIPH_BASE + 0x00001000) -#define LPC43_PMC_BASE (LPC43_RTCPERIPH_BASE + 0x00002000) -#define LPC43_CREG_BASE (LPC43_RTCPERIPH_BASE + 0x00003000) -#define LPC43_EVNTRTR_BASE (LPC43_RTCPERIPH_BASE + 0x00004000) -#define LPC43_OTPC_BASE (LPC43_RTCPERIPH_BASE + 0x00005000) -#define LPC43_RTC_BASE (LPC43_RTCPERIPH_BASE + 0x00006000) - -/* Clocking and Reset Peripherals */ - -#define LPC43_CGU_BASE (LPC43_CLKPERIPH_BASE + 0x00000000) -#define LPC43_CCU1_BASE (LPC43_CLKPERIPH_BASE + 0x00001000) -#define LPC43_CCU2_BASE (LPC43_CLKPERIPH_BASE + 0x00002000) -#define LPC43_RGU_BASE (LPC43_CLKPERIPH_BASE + 0x00003000) - -/* APB0 Peripherals */ - -#define LPC43_WWDT_BASE (LPC43_APB0PERIPH_BASE + 0x00000000) -#define LPC43_USART0_BASE (LPC43_APB0PERIPH_BASE + 0x00001000) -#define LPC43_UART1_BASE (LPC43_APB0PERIPH_BASE + 0x00002000) -#define LPC43_SSP0_BASE (LPC43_APB0PERIPH_BASE + 0x00003000) -#define LPC43_TIMER0_BASE (LPC43_APB0PERIPH_BASE + 0x00004000) -#define LPC43_TIMER1_BASE (LPC43_APB0PERIPH_BASE + 0x00005000) -#define LPC43_SCU_BASE (LPC43_APB0PERIPH_BASE + 0x00006000) -#define LPC43_GPIOINT_BASE (LPC43_APB0PERIPH_BASE + 0x00007000) -#define LPC43_GRP0INT_BASE (LPC43_APB0PERIPH_BASE + 0x00008000) -#define LPC43_GRP1INT_BASE (LPC43_APB0PERIPH_BASE + 0x00009000) - -/* APB1 Peripherals */ - -#define LPC43_MCPWM_BASE (LPC43_APB1PERIPH_BASE + 0x00000000) -#define LPC43_I2C0_BASE (LPC43_APB1PERIPH_BASE + 0x00001000) -#define LPC43_I2S0_BASE (LPC43_APB1PERIPH_BASE + 0x00002000) -#define LPC43_I2S1_BASE (LPC43_APB1PERIPH_BASE + 0x00003000) -#define LPC43_CAN1_BASE (LPC43_APB1PERIPH_BASE + 0x00004000) - -/* APB2 Peripherals */ - -#define LPC43_RIT_BASE (LPC43_APB2PERIPH_BASE + 0x00000000) -#define LPC43_USART2_BASE (LPC43_APB2PERIPH_BASE + 0x00001000) -#define LPC43_USART3_BASE (LPC43_APB2PERIPH_BASE + 0x00002000) -#define LPC43_TIMER2_BASE (LPC43_APB2PERIPH_BASE + 0x00003000) -#define LPC43_TIMER3_BASE (LPC43_APB2PERIPH_BASE + 0x00004000) -#define LPC43_SSP1_BASE (LPC43_APB2PERIPH_BASE + 0x00005000) -#define LPC43_QEI_BASE (LPC43_APB2PERIPH_BASE + 0x00006000) -#define LPC43_GIMA_BASE (LPC43_APB2PERIPH_BASE + 0x00007000) - -/* APB3 Peripherals */ - -#define LPC43_I2C1_BASE (LPC43_APB3PERIPH_BASE + 0x00000000) -#define LPC43_DAC_BASE (LPC43_APB3PERIPH_BASE + 0x00001000) -#define LPC43_CAN0_BASE (LPC43_APB3PERIPH_BASE + 0x00002000) -#define LPC43_ADC0_BASE (LPC43_APB3PERIPH_BASE + 0x00003000) -#define LPC43_ADC1_BASE (LPC43_APB3PERIPH_BASE + 0x00004000) - -/* ARM Private */ - -#define LPC43_SCS_BASE (LPC43_ARM_BASE + 0x0000e000) -#define LPC43_DEBUGMCU_BASE (LPC43_ARM_BASE + 0x00042000) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h index ea9640a10..971349354 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h @@ -83,6 +83,79 @@ #define LPC43_RTC_AMON_OFFSET 0x0078 /* Alarm value for Months */ #define LPC43_RTC_AYEAR_OFFSET 0x007c /* Alarm value for Year */ +/* General Purpose Registers. + * + * In addition to the RTC registers, 64 general purpose registers are available + * to store data when the main power supply is switched off. The general purpose + * registers reside in the RTC power domain and can be battery powered. + */ + +#define LPC43_REGFILE_OFFSET(n) (0x0000 + ((n) << 2)) +#define LPC43_REGFILE0_OFFSET 0x0000 +#define LPC43_REGFILE1_OFFSET 0x0004 +#define LPC43_REGFILE2_OFFSET 0x0008 +#define LPC43_REGFILE3_OFFSET 0x000c +#define LPC43_REGFILE4_OFFSET 0x0010 +#define LPC43_REGFILE5_OFFSET 0x0014 +#define LPC43_REGFILE6_OFFSET 0x0018 +#define LPC43_REGFILE7_OFFSET 0x001c +#define LPC43_REGFILE8_OFFSET 0x0020 +#define LPC43_REGFILE9_OFFSET 0x0024 +#define LPC43_REGFILE10_OFFSET 0x0028 +#define LPC43_REGFILE11_OFFSET 0x002c +#define LPC43_REGFILE12_OFFSET 0x0030 +#define LPC43_REGFILE13_OFFSET 0x0034 +#define LPC43_REGFILE14_OFFSET 0x0038 +#define LPC43_REGFILE15_OFFSET 0x003c +#define LPC43_REGFILE16_OFFSET 0x0040 +#define LPC43_REGFILE17_OFFSET 0x0044 +#define LPC43_REGFILE18_OFFSET 0x0048 +#define LPC43_REGFILE19_OFFSET 0x004c +#define LPC43_REGFILE20_OFFSET 0x0050 +#define LPC43_REGFILE21_OFFSET 0x0054 +#define LPC43_REGFILE22_OFFSET 0x0058 +#define LPC43_REGFILE23_OFFSET 0x005c +#define LPC43_REGFILE24_OFFSET 0x0060 +#define LPC43_REGFILE25_OFFSET 0x0064 +#define LPC43_REGFILE26_OFFSET 0x0068 +#define LPC43_REGFILE27_OFFSET 0x006c +#define LPC43_REGFILE28_OFFSET 0x0070 +#define LPC43_REGFILE29_OFFSET 0x0074 +#define LPC43_REGFILE30_OFFSET 0x0078 +#define LPC43_REGFILE31_OFFSET 0x007c +#define LPC43_REGFILE32_OFFSET 0x0080 +#define LPC43_REGFILE33_OFFSET 0x0084 +#define LPC43_REGFILE34_OFFSET 0x0088 +#define LPC43_REGFILE35_OFFSET 0x008c +#define LPC43_REGFILE36_OFFSET 0x0090 +#define LPC43_REGFILE37_OFFSET 0x0094 +#define LPC43_REGFILE38_OFFSET 0x0098 +#define LPC43_REGFILE39_OFFSET 0x009c +#define LPC43_REGFILE40_OFFSET 0x00a0 +#define LPC43_REGFILE41_OFFSET 0x00a4 +#define LPC43_REGFILE42_OFFSET 0x00a8 +#define LPC43_REGFILE43_OFFSET 0x00ac +#define LPC43_REGFILE44_OFFSET 0x00b0 +#define LPC43_REGFILE45_OFFSET 0x00b4 +#define LPC43_REGFILE46_OFFSET 0x00b8 +#define LPC43_REGFILE47_OFFSET 0x00bc +#define LPC43_REGFILE48_OFFSET 0x00c0 +#define LPC43_REGFILE49_OFFSET 0x00c4 +#define LPC43_REGFILE50_OFFSET 0x00c8 +#define LPC43_REGFILE51_OFFSET 0x00cc +#define LPC43_REGFILE52_OFFSET 0x00d0 +#define LPC43_REGFILE53_OFFSET 0x00d4 +#define LPC43_REGFILE54_OFFSET 0x00d8 +#define LPC43_REGFILE55_OFFSET 0x00dc +#define LPC43_REGFILE56_OFFSET 0x00e0 +#define LPC43_REGFILE57_OFFSET 0x00e4 +#define LPC43_REGFILE58_OFFSET 0x00e8 +#define LPC43_REGFILE59_OFFSET 0x00ec +#define LPC43_REGFILE60_OFFSET 0x00f0 +#define LPC43_REGFILE61_OFFSET 0x00f4 +#define LPC43_REGFILE62_OFFSET 0x00f8 +#define LPC43_REGFILE63_OFFSET 0x00fc + /* Register addresses ***************************************************************/ /* Miscellaneous registers */ @@ -120,6 +193,74 @@ #define LPC43_RTC_AMON (LPC43_RTC_BASE+LPC43_RTC_AMON_OFFSET) #define LPC43_RTC_AYEAR (LPC43_RTC_BASE+LPC43_RTC_AYEAR_OFFSET) +/* General Purpose Registers */ + +#define LPC43_REGFILE(n) (LPC43_BACKUP_BASE+LPC43_REGFILE_OFFSET(n)) +#define LPC43_REGFILE0 (LPC43_BACKUP_BASE+LPC43_REGFILE0_OFFSET) +#define LPC43_REGFILE1 (LPC43_BACKUP_BASE+LPC43_REGFILE1_OFFSET) +#define LPC43_REGFILE2 (LPC43_BACKUP_BASE+LPC43_REGFILE2_OFFSET) +#define LPC43_REGFILE3 (LPC43_BACKUP_BASE+LPC43_REGFILE3_OFFSET) +#define LPC43_REGFILE4 (LPC43_BACKUP_BASE+LPC43_REGFILE4_OFFSET) +#define LPC43_REGFILE5 (LPC43_BACKUP_BASE+LPC43_REGFILE5_OFFSET) +#define LPC43_REGFILE6 (LPC43_BACKUP_BASE+LPC43_REGFILE6_OFFSET) +#define LPC43_REGFILE7 (LPC43_BACKUP_BASE+LPC43_REGFILE7_OFFSET) +#define LPC43_REGFILE8 (LPC43_BACKUP_BASE+LPC43_REGFILE8_OFFSET) +#define LPC43_REGFILE9 (LPC43_BACKUP_BASE+LPC43_REGFILE9_OFFSET) +#define LPC43_REGFILE10 (LPC43_BACKUP_BASE+LPC43_REGFILE10_OFFSET) +#define LPC43_REGFILE11 (LPC43_BACKUP_BASE+LPC43_REGFILE11_OFFSET) +#define LPC43_REGFILE12 (LPC43_BACKUP_BASE+LPC43_REGFILE12_OFFSET) +#define LPC43_REGFILE13 (LPC43_BACKUP_BASE+LPC43_REGFILE13_OFFSET) +#define LPC43_REGFILE14 (LPC43_BACKUP_BASE+LPC43_REGFILE14_OFFSET) +#define LPC43_REGFILE15 (LPC43_BACKUP_BASE+LPC43_REGFILE15_OFFSET) +#define LPC43_REGFILE16 (LPC43_BACKUP_BASE+LPC43_REGFILE16_OFFSET) +#define LPC43_REGFILE17 (LPC43_BACKUP_BASE+LPC43_REGFILE17_OFFSET) +#define LPC43_REGFILE18 (LPC43_BACKUP_BASE+LPC43_REGFILE18_OFFSET) +#define LPC43_REGFILE19 (LPC43_BACKUP_BASE+LPC43_REGFILE19_OFFSET) +#define LPC43_REGFILE20 (LPC43_BACKUP_BASE+LPC43_REGFILE20_OFFSET) +#define LPC43_REGFILE21 (LPC43_BACKUP_BASE+LPC43_REGFILE21_OFFSET) +#define LPC43_REGFILE22 (LPC43_BACKUP_BASE+LPC43_REGFILE22_OFFSET) +#define LPC43_REGFILE23 (LPC43_BACKUP_BASE+LPC43_REGFILE23_OFFSET) +#define LPC43_REGFILE24 (LPC43_BACKUP_BASE+LPC43_REGFILE24_OFFSET) +#define LPC43_REGFILE25 (LPC43_BACKUP_BASE+LPC43_REGFILE25_OFFSET) +#define LPC43_REGFILE26 (LPC43_BACKUP_BASE+LPC43_REGFILE26_OFFSET) +#define LPC43_REGFILE27 (LPC43_BACKUP_BASE+LPC43_REGFILE27_OFFSET) +#define LPC43_REGFILE28 (LPC43_BACKUP_BASE+LPC43_REGFILE28_OFFSET) +#define LPC43_REGFILE29 (LPC43_BACKUP_BASE+LPC43_REGFILE29_OFFSET) +#define LPC43_REGFILE30 (LPC43_BACKUP_BASE+LPC43_REGFILE30_OFFSET) +#define LPC43_REGFILE31 (LPC43_BACKUP_BASE+LPC43_REGFILE31_OFFSET) +#define LPC43_REGFILE32 (LPC43_BACKUP_BASE+LPC43_REGFILE32_OFFSET) +#define LPC43_REGFILE33 (LPC43_BACKUP_BASE+LPC43_REGFILE33_OFFSET) +#define LPC43_REGFILE34 (LPC43_BACKUP_BASE+LPC43_REGFILE34_OFFSET) +#define LPC43_REGFILE35 (LPC43_BACKUP_BASE+LPC43_REGFILE35_OFFSET) +#define LPC43_REGFILE36 (LPC43_BACKUP_BASE+LPC43_REGFILE36_OFFSET) +#define LPC43_REGFILE37 (LPC43_BACKUP_BASE+LPC43_REGFILE37_OFFSET) +#define LPC43_REGFILE38 (LPC43_BACKUP_BASE+LPC43_REGFILE38_OFFSET) +#define LPC43_REGFILE39 (LPC43_BACKUP_BASE+LPC43_REGFILE39_OFFSET) +#define LPC43_REGFILE40 (LPC43_BACKUP_BASE+LPC43_REGFILE40_OFFSET) +#define LPC43_REGFILE41 (LPC43_BACKUP_BASE+LPC43_REGFILE41_OFFSET) +#define LPC43_REGFILE42 (LPC43_BACKUP_BASE+LPC43_REGFILE42_OFFSET) +#define LPC43_REGFILE43 (LPC43_BACKUP_BASE+LPC43_REGFILE43_OFFSET) +#define LPC43_REGFILE44 (LPC43_BACKUP_BASE+LPC43_REGFILE44_OFFSET) +#define LPC43_REGFILE45 (LPC43_BACKUP_BASE+LPC43_REGFILE45_OFFSET) +#define LPC43_REGFILE46 (LPC43_BACKUP_BASE+LPC43_REGFILE46_OFFSET) +#define LPC43_REGFILE47 (LPC43_BACKUP_BASE+LPC43_REGFILE47_OFFSET) +#define LPC43_REGFILE48 (LPC43_BACKUP_BASE+LPC43_REGFILE48_OFFSET) +#define LPC43_REGFILE49 (LPC43_BACKUP_BASE+LPC43_REGFILE49_OFFSET) +#define LPC43_REGFILE50 (LPC43_BACKUP_BASE+LPC43_REGFILE50_OFFSET) +#define LPC43_REGFILE51 (LPC43_BACKUP_BASE+LPC43_REGFILE51_OFFSET) +#define LPC43_REGFILE52 (LPC43_BACKUP_BASE+LPC43_REGFILE52_OFFSET) +#define LPC43_REGFILE53 (LPC43_BACKUP_BASE+LPC43_REGFILE53_OFFSET) +#define LPC43_REGFILE54 (LPC43_BACKUP_BASE+LPC43_REGFILE54_OFFSET) +#define LPC43_REGFILE55 (LPC43_BACKUP_BASE+LPC43_REGFILE55_OFFSET) +#define LPC43_REGFILE56 (LPC43_BACKUP_BASE+LPC43_REGFILE56_OFFSET) +#define LPC43_REGFILE57 (LPC43_BACKUP_BASE+LPC43_REGFILE57_OFFSET) +#define LPC43_REGFILE58 (LPC43_BACKUP_BASE+LPC43_REGFILE58_OFFSET) +#define LPC43_REGFILE59 (LPC43_BACKUP_BASE+LPC43_REGFILE59_OFFSET) +#define LPC43_REGFILE60 (LPC43_BACKUP_BASE+LPC43_REGFILE60_OFFSET) +#define LPC43_REGFILE61 (LPC43_BACKUP_BASE+LPC43_REGFILE61_OFFSET) +#define LPC43_REGFILE62 (LPC43_BACKUP_BASE+LPC43_REGFILE62_OFFSET) +#define LPC43_REGFILE63 (LPC43_BACKUP_BASE+LPC43_REGFILE63_OFFSET) + /* Register bit definitions *********************************************************/ /* Miscellaneous registers */ /* Interrupt Location Register */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_timer.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_timer.h index b6196bb5a..7627b135d 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_timer.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_timer.h @@ -42,9 +42,6 @@ #include -#include "chip.h" -#include "lpc43_memorymap.h" - /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h index 7e8d06b01..6d18dd41c 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h @@ -41,7 +41,6 @@ ************************************************************************************************/ #include -#include "lpc43_memorymap.h" /************************************************************************************************ * Pre-processor Definitions -- cgit v1.2.3