From 9ecbcf45e00a366d02da0d82066763627dd0d589 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 1 Jul 2012 16:47:50 +0000 Subject: Add LPC43 ADC, DAC, RTC, SPI, I2S, I2C, and QEI header files from LPC17 git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4894 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/lpc17_adc.h | 10 +- nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h | 13 +- nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h | 8 +- nuttx/arch/arm/src/lpc43xx/chip/lpc43_adc.h | 198 ++++++++++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_dac.h | 94 ++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2c.h | 205 +++++++++++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2s.h | 202 ++++++++++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h | 211 +++++++++++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h | 230 ++++++++++++++++++++++++++++ nuttx/arch/arm/src/lpc43xx/chip/lpc43_spi.h | 3 - 10 files changed, 1154 insertions(+), 20 deletions(-) create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_adc.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_dac.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2c.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2s.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h create mode 100644 nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h index 93a3daad7..6b9a58345 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_adc.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -51,7 +51,6 @@ /* Register offsets *****************************************************************/ - #define LPC17_ADC_CR_OFFSET 0x0000 /* A/D Control Register */ #define LPC17_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */ #define LPC17_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */ @@ -71,7 +70,6 @@ /* Register addresses ***************************************************************/ - #define LPC17_ADC_CR (LPC17_ADC_BASE+LPC17_ADC_CR_OFFSET) #define LPC17_ADC_GDR (LPC17_ADC_BASE+LPC17_ADC_GDR_OFFSET) #define LPC17_ADC_INTEN (LPC17_ADC_BASE+LPC17_ADC_INTEN_OFFSET) @@ -115,10 +113,10 @@ /* Bits 28-31: Reserved */ /* A/D Global Data Register AND Channel 0-7 Data Register */ /* Bits 0-3: Reserved */ -#define ADC_DR_RESULT_SHIFT (4) /* Bits 4-15: Result of conversion (DONE==1)*/ +#define ADC_DR_RESULT_SHIFT (4) /* Bits 4-15: Result of conversion (DONE==1) */ #define ADC_DR_RESULT_MASK (0x0fff << ADC_DR_RESULT_SHIFT) /* Bits 16-23: Reserved */ -#define ADC_DR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted*/ +#define ADC_DR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */ #define ADC_DR_CHAN_MASK (3 << ADC_DR_CHN_SHIFT) /* Bits 27-29: Reserved */ #define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h b/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h index 61651fa95..638d40178 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_i2s * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -91,7 +91,7 @@ #define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT) # define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT) # define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT) -# define I2S_DAO_WDWID_32BITS (2 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT) #define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */ #define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ #define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ @@ -106,7 +106,7 @@ #define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT) # define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT) # define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT) -# define I2S_DAI_WDWID_32BITS (2 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT) #define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */ #define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ #define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ @@ -133,7 +133,7 @@ #define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */ #define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */ - /* Bits 3-7: Reserved */ + /* Bits 2-7: Reserved */ #define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */ #define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT) /* Bits 12-15: Reserved */ @@ -142,10 +142,9 @@ /* Bits 20-31: Reserved */ /* Interrupt Request Control Register */ -#define I2S_IRQ_ #define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */ #define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */ - /* Bits 3-7: Reserved */ + /* Bits 2-7: Reserved */ #define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */ #define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT) /* Bits 12-15: Reserved */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h index e92ada029..195e403c1 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_rtc.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -222,7 +222,7 @@ #define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */ #define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT) /* Bits 28-31: Reserved */ -/* Consolidated Time Register 2 (Shouldn't DOY width be 9 bits?) */ +/* Consolidated Time Register 2 */ #define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */ #define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT) @@ -243,7 +243,7 @@ #define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */ #define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT) #define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */ - /* Bits 12-31: Reserved */ + /* Bits 18-31: Reserved */ /* Alarm register group */ #define RTC_ALSEC_MASK (0x003f) diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_adc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_adc.h new file mode 100644 index 000000000..8652f2f67 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_adc.h @@ -0,0 +1,198 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_adc.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC43_ADC_CR_OFFSET 0x0000 /* A/D Control Register */ +#define LPC43_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */ +#define LPC43_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */ + +#define LPC43_ADC_DR_OFFSET(n) (0x0010+((n) << 2)) +#define LPC43_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */ +#define LPC43_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */ +#define LPC43_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */ +#define LPC43_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */ +#define LPC43_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */ +#define LPC43_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */ +#define LPC43_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */ +#define LPC43_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */ + +#define LPC43_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */ + +/* Register addresses ***************************************************************/ + +#define LPC43_ADC0_CR (LPC43_ADC0_BASE+LPC43_ADC_CR_OFFSET) +#define LPC43_ADC0_GDR (LPC43_ADC0_BASE+LPC43_ADC_GDR_OFFSET) +#define LPC43_ADC0_INTEN (LPC43_ADC0_BASE+LPC43_ADC_INTEN_OFFSET) +#define LPC43_ADC0_DR(n) (LPC43_ADC0_BASE+LPC43_ADC_DR_OFFSET(n)) +#define LPC43_ADC0_DR0 (LPC43_ADC0_BASE+LPC43_ADC_DR0_OFFSET) +#define LPC43_ADC0_DR1 (LPC43_ADC0_BASE+LPC43_ADC_DR1_OFFSET) +#define LPC43_ADC0_DR2 (LPC43_ADC0_BASE+LPC43_ADC_DR2_OFFSET) +#define LPC43_ADC0_DR3 (LPC43_ADC0_BASE+LPC43_ADC_DR3_OFFSET) +#define LPC43_ADC0_DR4 (LPC43_ADC0_BASE+LPC43_ADC_DR4_OFFSET) +#define LPC43_ADC0_DR5 (LPC43_ADC0_BASE+LPC43_ADC_DR5_OFFSET) +#define LPC43_ADC0_DR6 (LPC43_ADC0_BASE+LPC43_ADC_DR6_OFFSET) +#define LPC43_ADC0_DR7 (LPC43_ADC0_BASE+LPC43_ADC_DR7_OFFSET) +#define LPC43_ADC0_STAT (LPC43_ADC0_BASE+LPC43_ADC_STAT_OFFSET) + +#define LPC43_ADC1_CR (LPC43_ADC1_BASE+LPC43_ADC_CR_OFFSET) +#define LPC43_ADC1_GDR (LPC43_ADC1_BASE+LPC43_ADC_GDR_OFFSET) +#define LPC43_ADC1_INTEN (LPC43_ADC1_BASE+LPC43_ADC_INTEN_OFFSET) +#define LPC43_ADC1_DR(n) (LPC43_ADC1_BASE+LPC43_ADC_DR_OFFSET(n)) +#define LPC43_ADC1_DR0 (LPC43_ADC1_BASE+LPC43_ADC_DR0_OFFSET) +#define LPC43_ADC1_DR1 (LPC43_ADC1_BASE+LPC43_ADC_DR1_OFFSET) +#define LPC43_ADC1_DR2 (LPC43_ADC1_BASE+LPC43_ADC_DR2_OFFSET) +#define LPC43_ADC1_DR3 (LPC43_ADC1_BASE+LPC43_ADC_DR3_OFFSET) +#define LPC43_ADC1_DR4 (LPC43_ADC1_BASE+LPC43_ADC_DR4_OFFSET) +#define LPC43_ADC1_DR5 (LPC43_ADC1_BASE+LPC43_ADC_DR5_OFFSET) +#define LPC43_ADC1_DR6 (LPC43_ADC1_BASE+LPC43_ADC_DR6_OFFSET) +#define LPC43_ADC1_DR7 (LPC43_ADC1_BASE+LPC43_ADC_DR7_OFFSET) +#define LPC43_ADC1_STAT (LPC43_ADC1_BASE+LPC43_ADC_STAT_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* A/D Control Register */ + +#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */ +#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK) +#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */ +#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT) +#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */ + +#define ADC_CR_CLKS_SHIFT (17) /* Bits 17-19: Number of clocks in conversion */ +#define ADC_CR_CLKS_MASK (7 << ADC_CR_CLKS_SHIFT) +# define ADC_CR_CLKS_11 (0 << ADC_CR_CLKS_SHIFT) /* 11 clocks / 10 bits */ +# define ADC_CR_CLKS_10 (1 << ADC_CR_CLKS_SHIFT) /* 10 clocks / 9 bits */ +# define ADC_CR_CLKS_9 (2 << ADC_CR_CLKS_SHIFT) /* 9 clocks / 8 bits */ +# define ADC_CR_CLKS_8 (3 << ADC_CR_CLKS_SHIFT) /* 8 clocks / 7 bits */ +# define ADC_CR_CLKS_7 (4 << ADC_CR_CLKS_SHIFT) /* 7 clocks / 6 bits */ +# define ADC_CR_CLKS_6 (5 << ADC_CR_CLKS_SHIFT) /* 6 clocks / 5 bits */ +# define ADC_CR_CLKS_5 (6 << ADC_CR_CLKS_SHIFT) /* 5 clocks / 4 bits */ +# define ADC_CR_CLKS_4 (7 << ADC_CR_CLKS_SHIFT) /* 4 clocks / 3 bits */ + /* Bit 20: Reserved */ +#define ADC_CR_PDN (1 << 21) /* Bit 21: A/D converter power-down mode */ + /* Bits 22-23: Reserved */ +#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */ +#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT) +# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */ +# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */ +# define ADC_CR_START_CTOUT15 (2 << ADC_CR_START_SHIFT) /* Start when edge on CTOUT_15 */ +# define ADC_CR_START_CTOUT8 (3 << ADC_CR_START_SHIFT) /* Start when edge on CTOUT_8 */ +# define ADC_CR_START_ADCTRIG0 (4 << ADC_CR_START_SHIFT) /* Start when edge on ADCTRIG0 */ +# define ADC_CR_START_ADCTRIG1 (5 << ADC_CR_START_SHIFT) /* Start when edge on ADCTRIG1 */ +# define ADC_CR_START_MCPWM (6 << ADC_CR_START_SHIFT) /* Start when edge on MCPWM */ +#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */ + /* Bits 28-31: Reserved */ +/* A/D Global Data Register */ + /* Bits 0-3: Reserved */ +#define ADC_GDR_VVREF_SHIFT (6) /* Bits 6-15: Result of conversion (DONE==1) */ +#define ADC_GDR_VVREF_MASK (0x03ff << ADC_GDR_VVREF_SHIFT) + /* Bits 16-23: Reserved */ +#define ADC_GDR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */ +#define ADC_GDR_CHAN_MASK (3 << ADC_GDR_CHN_SHIFT) + /* Bits 27-29: Reserved */ +#define ADC_GDR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/ +#define ADC_GDR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/ + +/* A/D Interrupt Enable Register */ + +#define ADC_INTEN_CHAN(n) (1 << (n)) +#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */ +#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */ +#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */ +#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */ +#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */ +#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */ +#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */ +#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */ +#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */ + /* Bits 9-31: Reserved */ +/* Channel 0-7 A/D Data Register */ + /* Bits 0-3: Reserved */ +#define ADC_DR_VVREF_SHIFT (6) /* Bits 6-15: Result of conversion (DONE==1) */ +#define ADC_DR_VVREF_MASK (0x03ff << ADC_DR_VVREF_SHIFT) + /* Bits 16-29: Reserved */ +#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/ +#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/ + +/* A/D Status Register */ + +#define ADC_STAT_DONE(n) (1 << (n)) +#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */ +#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */ +#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */ +#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */ +#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */ +#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */ +#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */ +#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */ +#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8) +#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */ +#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */ +#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */ +#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */ +#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */ +#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */ +#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */ +#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */ +#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */ + /* Bits 17-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_dac.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_dac.h new file mode 100644 index 000000000..e06ecf442 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_dac.h @@ -0,0 +1,94 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_dac.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC43_DAC_CR_OFFSET 0x0000 /* D/A Converter Register */ +#define LPC43_DAC_CTRL_OFFSET 0x0004 /* DAC Control register */ +#define LPC43_DAC_CNTVAL_OFFSET 0x0008 /* DAC Counter Value register */ + +/* Register addresses ***************************************************************/ + +#define LPC43_DAC_CR (LPC43_DAC_BASE+LPC43_DAC_CR_OFFSET) +#define LPC43_DAC_CTRL (LPC43_DAC_BASE+LPC43_DAC_CTRL_OFFSET) +#define LPC43_DAC_CNTVAL (LPC43_DAC_BASE+LPC43_DAC_CNTVAL_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* D/A Converter Register */ + /* Bits 0-5: Reserved */ +#define DAC_CR_VALUE_SHIFT (6) /* Bits 6-15: Controls voltage on the AOUT pin */ +#define DAC_CR_VALUE_MASK (0x3ff << DAC_CR_VALUE_SHIFT) +#define DAC_CR_BIAS (1 << 16) /* Bit 16: Controls DAC settling time */ + /* Bits 17-31: Reserved */ +/* DAC Control register */ + +#define DAC_CTRL_INTDMAREQ (1 << 0) /* Bit 0: Timer timed out */ +#define DAC_CTRL_DBLBUFEN (1 << 1) /* Bit 1: Enable DACR double-buffering */ +#define DAC_CTRL_CNTEN (1 << 2) /* Bit 2: Enable timeout counter */ +#define DAC_CTRL_DMAEN (1 << 3) /* Bit 3: Enable DMA access */ + /* Bits 4-31: Reserved */ +/* DAC Counter Value register */ + +#define DAC_CNTVAL_SHIFT (0) /* Bits 0-15: Reload value for DAC interrupt/DMA timer */ +#define DAC_CNTVAL_MASK (0xffff << DAC_CNTVAL_SHIFT) + /* Bits 8-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2c.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2c.h new file mode 100644 index 000000000..84854d5ec --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2c.h @@ -0,0 +1,205 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_i2c.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC43_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ +#define LPC43_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ +#define LPC43_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ +#define LPC43_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ +#define LPC43_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ +#define LPC43_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ +#define LPC43_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ +#define LPC43_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ +#define LPC43_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ +#define LPC43_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ +#define LPC43_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ +#define LPC43_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ +#define LPC43_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ +#define LPC43_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ +#define LPC43_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ +#define LPC43_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ + +/* Register addresses ***************************************************************/ + +#define LPC43_I2C0_CONSET (LPC43_I2C0_BASE+LPC43_I2C_CONSET_OFFSET) +#define LPC43_I2C0_STAT (LPC43_I2C0_BASE+LPC43_I2C_STAT_OFFSET) +#define LPC43_I2C0_DAT (LPC43_I2C0_BASE+LPC43_I2C_DAT_OFFSET) +#define LPC43_I2C0_ADR0 (LPC43_I2C0_BASE+LPC43_I2C_ADR0_OFFSET) +#define LPC43_I2C0_SCLH (LPC43_I2C0_BASE+LPC43_I2C_SCLH_OFFSET) +#define LPC43_I2C0_SCLL (LPC43_I2C0_BASE+LPC43_I2C_SCLL_OFFSET) +#define LPC43_I2C0_CONCLR (LPC43_I2C0_BASE+LPC43_I2C_CONCLR_OFFSET) +#define LPC43_I2C0_MMCTRL (LPC43_I2C0_BASE+LPC43_I2C_MMCTRL_OFFSET) +#define LPC43_I2C0_ADR1 (LPC43_I2C0_BASE+LPC43_I2C_ADR1_OFFSET) +#define LPC43_I2C0_ADR2 (LPC43_I2C0_BASE+LPC43_I2C_ADR2_OFFSET) +#define LPC43_I2C0_ADR3 (LPC43_I2C0_BASE+LPC43_I2C_ADR3_OFFSET) +#define LPC43_I2C0_BUFR (LPC43_I2C0_BASE+LPC43_I2C_BUFR_OFFSET) +#define LPC43_I2C0_MASK0 (LPC43_I2C0_BASE+LPC43_I2C_MASK0_OFFSET) +#define LPC43_I2C0_MASK1 (LPC43_I2C0_BASE+LPC43_I2C_MASK1_OFFSET) +#define LPC43_I2C0_MASK2 (LPC43_I2C0_BASE+LPC43_I2C_MASK2_OFFSET) +#define LPC43_I2C0_MASK3 (LPC43_I2C0_BASE+LPC43_I2C_MASK3_OFFSET) + +#define LPC43_I2C1_CONSET (LPC43_I2C1_BASE+LPC43_I2C_CONSET_OFFSET) +#define LPC43_I2C1_STAT (LPC43_I2C1_BASE+LPC43_I2C_STAT_OFFSET) +#define LPC43_I2C1_DAT (LPC43_I2C1_BASE+LPC43_I2C_DAT_OFFSET) +#define LPC43_I2C1_ADR0 (LPC43_I2C1_BASE+LPC43_I2C_ADR0_OFFSET) +#define LPC43_I2C1_SCLH (LPC43_I2C1_BASE+LPC43_I2C_SCLH_OFFSET) +#define LPC43_I2C1_SCLL (LPC43_I2C1_BASE+LPC43_I2C_SCLL_OFFSET) +#define LPC43_I2C1_CONCLR (LPC43_I2C1_BASE+LPC43_I2C_CONCLR_OFFSET) +#define LPC43_I2C1_MMCTRL (LPC43_I2C1_BASE+LPC43_I2C_MMCTRL_OFFSET) +#define LPC43_I2C1_ADR1 (LPC43_I2C1_BASE+LPC43_I2C_ADR1_OFFSET) +#define LPC43_I2C1_ADR2 (LPC43_I2C1_BASE+LPC43_I2C_ADR2_OFFSET) +#define LPC43_I2C1_ADR3 (LPC43_I2C1_BASE+LPC43_I2C_ADR3_OFFSET) +#define LPC43_I2C1_BUFR (LPC43_I2C1_BASE+LPC43_I2C_BUFR_OFFSET) +#define LPC43_I2C1_MASK0 (LPC43_I2C1_BASE+LPC43_I2C_MASK0_OFFSET) +#define LPC43_I2C1_MASK1 (LPC43_I2C1_BASE+LPC43_I2C_MASK1_OFFSET) +#define LPC43_I2C1_MASK2 (LPC43_I2C1_BASE+LPC43_I2C_MASK2_OFFSET) +#define LPC43_I2C1_MASK3 (LPC43_I2C1_BASE+LPC43_I2C_MASK3_OFFSET) + +#define LPC43_I2C2_CONSET (LPC43_I2C2_BASE+LPC43_I2C_CONSET_OFFSET) +#define LPC43_I2C2_STAT (LPC43_I2C2_BASE+LPC43_I2C_STAT_OFFSET) +#define LPC43_I2C2_DAT (LPC43_I2C2_BASE+LPC43_I2C_DAT_OFFSET) +#define LPC43_I2C2_ADR0 (LPC43_I2C2_BASE+LPC43_I2C_ADR0_OFFSET) +#define LPC43_I2C2_SCLH (LPC43_I2C2_BASE+LPC43_I2C_SCLH_OFFSET) +#define LPC43_I2C2_SCLL (LPC43_I2C2_BASE+LPC43_I2C_SCLL_OFFSET) +#define LPC43_I2C2_CONCLR (LPC43_I2C2_BASE+LPC43_I2C_CONCLR_OFFSET) +#define LPC43_I2C2_MMCTRL (LPC43_I2C2_BASE+LPC43_I2C_MMCTRL_OFFSET) +#define LPC43_I2C2_ADR1 (LPC43_I2C2_BASE+LPC43_I2C_ADR1_OFFSET) +#define LPC43_I2C2_ADR2 (LPC43_I2C2_BASE+LPC43_I2C_ADR2_OFFSET) +#define LPC43_I2C2_ADR3 (LPC43_I2C2_BASE+LPC43_I2C_ADR3_OFFSET) +#define LPC43_I2C2_BUFR (LPC43_I2C2_BASE+LPC43_I2C_BUFR_OFFSET) +#define LPC43_I2C2_MASK0 (LPC43_I2C2_BASE+LPC43_I2C_MASK0_OFFSET) +#define LPC43_I2C2_MASK1 (LPC43_I2C2_BASE+LPC43_I2C_MASK1_OFFSET) +#define LPC43_I2C2_MASK2 (LPC43_I2C2_BASE+LPC43_I2C_MASK2_OFFSET) +#define LPC43_I2C2_MASK3 (LPC43_I2C2_BASE+LPC43_I2C_MASK3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* I2C Control Set Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ + /* Bits 7-31: Reserved */ +/* I2C Control Clear Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ +#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ + /* Bit 4: Reserved */ +#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ +#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ + /* Bits 7-31: Reserved */ +/* I2C Status Register + * + * See tables 997-1002 in the "LPC43xx User Manual" (UM10503), Rev. 1.2, 8 June + * 2012, NXP for definitions of status codes. + */ + +#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status + * Bits 0-2 always zero */ + /* Bits 8-31: Reserved */ +/* I2C Data Register */ + +#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ + /* Bits 8-31: Reserved */ +/* Monitor mode control register */ + +#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ +#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ +#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ + /* Bits 3-31: Reserved */ +/* Data buffer register */ + +#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ + /* Bits 8-31: Reserved */ +/* I2C Slave address registers: + * + * I2C Slave Address Register 0 + * I2C Slave Address Register 1 + * I2C Slave Address Register 2 + * I2C Slave Address Register 3 + */ + +#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ +#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ +#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Slave address mask registers: + * + * I2C Slave address mask register 0 + * I2C Slave address mask register 1 + * I2C Slave address mask register 2 + * I2C Slave address mask register 3 + */ + /* Bit 0: Reserved */ +#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ +#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* SCH Duty Cycle Register High Half Word */ + +#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ + /* Bits 16-31: Reserved */ +/* SCL Duty Cycle Register Low Half Word */ + +#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ + /* Bits 16-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2s.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2s.h new file mode 100644 index 000000000..15a7023a9 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2s.h @@ -0,0 +1,202 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_i2s + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC43_I2S_DAO_OFFSET 0x0000 /* Digital Audio Output Register */ +#define LPC43_I2S_DAI_OFFSET 0x0004 /* Digital Audio Input Register */ +#define LPC43_I2S_TXFIFO_OFFSET 0x0008 /* Transmit FIFO */ +#define LPC43_I2S_RXFIFO_OFFSET 0x000c /* Receive FIFO */ +#define LPC43_I2S_STATE_OFFSET 0x0010 /* Status Feedback Register */ +#define LPC43_I2S_DMA1_OFFSET 0x0014 /* DMA Configuration Register 1 */ +#define LPC43_I2S_DMA2_OFFSET 0x0018 /* DMA Configuration Register 2 */ +#define LPC43_I2S_IRQ_OFFSET 0x001c /* Interrupt Request Control Register */ +#define LPC43_I2S_TXRATE_OFFSET 0x0020 /* Transmit MCLK divider */ +#define LPC43_I2S_RXRATE_OFFSET 0x0024 /* Receive MCLK divider */ +#define LPC43_I2S_TXBITRATE_OFFSET 0x0028 /* Transmit bit rate divider */ +#define LPC43_I2S_RXBITRATE_OFFSET 0x002c /* Receive bit rate divider */ +#define LPC43_I2S_TXMODE_OFFSET 0x0030 /* Transmit mode control */ +#define LPC43_I2S_RXMODE_OFFSET 0x0034 /* Receive mode control */ + +/* Register addresses ***************************************************************/ + +#define LPC43_I2S0_DAO (LPC43_I2S0_BASE+LPC43_I2S_DAO_OFFSET) +#define LPC43_I2S0_DAI (LPC43_I2S0_BASE+LPC43_I2S_DAI_OFFSET) +#define LPC43_I2S0_TXFIFO (LPC43_I2S0_BASE+LPC43_I2S_TXFIFO_OFFSET) +#define LPC43_I2S0_RXFIFO (LPC43_I2S0_BASE+LPC43_I2S_RXFIFO_OFFSET) +#define LPC43_I2S0_STATE (LPC43_I2S0_BASE+LPC43_I2S_STATE_OFFSET) +#define LPC43_I2S0_DMA1 (LPC43_I2S0_BASE+LPC43_I2S_DMA1_OFFSET) +#define LPC43_I2S0_DMA2 (LPC43_I2S0_BASE+LPC43_I2S_DMA2_OFFSET) +#define LPC43_I2S0_IRQ (LPC43_I2S0_BASE+LPC43_I2S_IRQ_OFFSET) +#define LPC43_I2S0_TXRATE (LPC43_I2S0_BASE+LPC43_I2S_TXRATE_OFFSET) +#define LPC43_I2S0_RXRATE (LPC43_I2S0_BASE+LPC43_I2S_RXRATE_OFFSET) +#define LPC43_I2S0_TXBITRATE (LPC43_I2S0_BASE+LPC43_I2S_TXBITRATE_OFFSET) +#define LPC43_I2S0_RXBITRATE (LPC43_I2S0_BASE+LPC43_I2S_RXBITRATE_OFFSET) +#define LPC43_I2S0_TXMODE (LPC43_I2S0_BASE+LPC43_I2S_TXMODE_OFFSET) +#define LPC43_I2S0_RXMODE (LPC43_I2S0_BASE+LPC43_I2S_RXMODE_OFFSET) + +#define LPC43_I2S1_DAO (LPC43_I2S1_BASE+LPC43_I2S_DAO_OFFSET) +#define LPC43_I2S1_DAI (LPC43_I2S1_BASE+LPC43_I2S_DAI_OFFSET) +#define LPC43_I2S1_TXFIFO (LPC43_I2S1_BASE+LPC43_I2S_TXFIFO_OFFSET) +#define LPC43_I2S1_RXFIFO (LPC43_I2S1_BASE+LPC43_I2S_RXFIFO_OFFSET) +#define LPC43_I2S1_STATE (LPC43_I2S1_BASE+LPC43_I2S_STATE_OFFSET) +#define LPC43_I2S1_DMA1 (LPC43_I2S1_BASE+LPC43_I2S_DMA1_OFFSET) +#define LPC43_I2S1_DMA2 (LPC43_I2S1_BASE+LPC43_I2S_DMA2_OFFSET) +#define LPC43_I2S1_IRQ (LPC43_I2S1_BASE+LPC43_I2S_IRQ_OFFSET) +#define LPC43_I2S1_TXRATE (LPC43_I2S1_BASE+LPC43_I2S_TXRATE_OFFSET) +#define LPC43_I2S1_RXRATE (LPC43_I2S1_BASE+LPC43_I2S_RXRATE_OFFSET) +#define LPC43_I2S1_TXBITRATE (LPC43_I2S1_BASE+LPC43_I2S_TXBITRATE_OFFSET) +#define LPC43_I2S1_RXBITRATE (LPC43_I2S1_BASE+LPC43_I2S_RXBITRATE_OFFSET) +#define LPC43_I2S1_TXMODE (LPC43_I2S1_BASE+LPC43_I2S_TXMODE_OFFSET) +#define LPC43_I2S1_RXMODE (LPC43_I2S1_BASE+LPC43_I2S_RXMODE_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Digital Audio Output Register */ + +#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ +#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT) +#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */ +#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ +#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ +#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */ +#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ +#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT) +#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */ + /* Bits 16-31: Reserved */ +/* Digital Audio Input Register */ + +#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ +#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT) +#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */ +#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ +#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ +#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */ +#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ +#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT) + /* Bits 15-31: Reserved */ +/* Transmit FIFO: 8 × 32-bit transmit FIFO */ +/* Receive FIFO: 8 × 32-bit receive FIFO */ + +/* Status Feedback Register */ + +#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */ +#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */ +#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */ + /* Bits 3-7: Reserved */ +#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */ +#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */ +#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT) + /* Bits 20-31: Reserved */ +/* DMA Configuration Register 1 and 2 */ + +#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */ +#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */ + /* Bits 2-7: Reserved */ +#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */ +#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */ +#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT) + /* Bits 20-31: Reserved */ +/* Interrupt Request Control Register */ + +#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */ +#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */ + /* Bits 2-7: Reserved */ +#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */ +#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */ +#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT) + /* Bits 20-31: Reserved */ +/* Transmit and Receive MCLK divider */ + +#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */ +#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT) +#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */ +#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT) + /* Bits 16-31: Reserved */ + +/* Transmit and received bit rate divider */ + +#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */ +#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT) + /* Bits 6-31: Reserved */ +/* Transmit and Receive mode control */ + +#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */ +#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT) +# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */ +# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */ +# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */ +#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */ +#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h new file mode 100644 index 000000000..05dd3c613 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h @@ -0,0 +1,211 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_qei.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Control registers */ + +#define LPC43_QEI_CON_OFFSET 0x0000 /* Control register */ +#define LPC43_QEI_STAT_OFFSET 0x0004 /* Encoder status register */ +#define LPC43_QEI_CONF_OFFSET 0x0008 /* Configuration register */ + +/* Position, index, and timer registers */ + +#define LPC43_QEI_POS_OFFSET 0x000c /* Position register */ +#define LPC43_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */ +#define LPC43_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */ +#define LPC43_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */ +#define LPC43_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */ +#define LPC43_QEI_INXCNT_OFFSET 0x0020 /* Index count register */ +#define LPC43_QEI_INXCMP0_OFFSET 0x0024 /* Index compare register 0 */ +#define LPC43_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */ +#define LPC43_QEI_TIME_OFFSET 0x002c /* Velocity timer register */ +#define LPC43_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */ +#define LPC43_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */ +#define LPC43_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */ +#define LPC43_QEI_FLTRPHA_OFFSET 0x003c /* Input digital filter register phase A */ +#define LPC43_QEI_FLTRPHB_OFFSET 0x0040 /* Input digital filter register phase B */ +#define LPC43_QEI_FLTRINX_OFFSET 0x0044 /* Input digital filter register index */ +#define LPC43_QEI_WINDOW_OFFSET 0x0048 /* Index acceptance window register */ +#define LPC43_QEI_INXCMP1_OFFSET 0x004c /* Index compare register 1 */ +#define LPC43_QEI_INXCMP2_OFFSET 0x0050 /* Index compare register 2 */ + +/* Interrupt registers */ + +#define LPC43_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */ +#define LPC43_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */ +#define LPC43_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */ +#define LPC43_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */ +#define LPC43_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */ +#define LPC43_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */ + +/* Register addresses ***************************************************************/ +/* Control registers */ + +#define LPC43_QEI_CON (LPC43_QEI_BASE+LPC43_QEI_CON_OFFSET) +#define LPC43_QEI_STAT (LPC43_QEI_BASE+LPC43_QEI_STAT_OFFSET) +#define LPC43_QEI_CONF (LPC43_QEI_BASE+LPC43_QEI_CONF_OFFSET) + +/* Position, index, and timer registers */ + +#define LPC43_QEI_POS (LPC43_QEI_BASE+LPC43_QEI_POS_OFFSET) +#define LPC43_QEI_MAXPOS (LPC43_QEI_BASE+LPC43_QEI_MAXPOS_OFFSET) +#define LPC43_QEI_CMPOS0 (LPC43_QEI_BASE+LPC43_QEI_CMPOS0_OFFSET) +#define LPC43_QEI_CMPOS1 (LPC43_QEI_BASE+LPC43_QEI_CMPOS1_OFFSET) +#define LPC43_QEI_CMPOS2 (LPC43_QEI_BASE+LPC43_QEI_CMPOS2_OFFSET) +#define LPC43_QEI_INXCNT (LPC43_QEI_BASE+LPC43_QEI_INXCNT_OFFSET) +#define LPC43_QEI_INXCMP0 (LPC43_QEI_BASE+LPC43_QEI_INXCMP0_OFFSET) +#define LPC43_QEI_LOAD (LPC43_QEI_BASE+LPC43_QEI_LOAD_OFFSET) +#define LPC43_QEI_TIME (LPC43_QEI_BASE+LPC43_QEI_TIME_OFFSET) +#define LPC43_QEI_VEL (LPC43_QEI_BASE+LPC43_QEI_VEL_OFFSET) +#define LPC43_QEI_CAP (LPC43_QEI_BASE+LPC43_QEI_CAP_OFFSET) +#define LPC43_QEI_VELCOMP (LPC43_QEI_BASE+LPC43_QEI_VELCOMP_OFFSET) +#define LPC43_QEI_FLTRPHA (LPC43_QEI_BASE+LPC43_QEI_FLTRPHA_OFFSET) +#define LPC43_QEI_FLTRPHB (LPC43_QEI_BASE+LPC43_QEI_FLTRPHB_OFFSET) +#define LPC43_QEI_FLTRINX (LPC43_QEI_BASE+LPC43_QEI_FLTRINX_OFFSET) +#define LPC43_QEI_WINDOW (LPC43_QEI_BASE+LPC43_QEI_WINDOW_OFFSET) +#define LPC43_QEI_INXCMP1 (LPC43_QEI_BASE+LPC43_QEI_INXCMP1_OFFSET) +#define LPC43_QEI_INXCMP2 (LPC43_QEI_BASE+LPC43_QEI_INXCMP2_OFFSET) + +/* Interrupt registers */ + +#define LPC43_QEI_IEC (LPC43_QEI_BASE+LPC43_QEI_IEC_OFFSET) +#define LPC43_QEI_IES (LPC43_QEI_BASE+LPC43_QEI_IES_OFFSET) +#define LPC43_QEI_INTSTAT (LPC43_QEI_BASE+LPC43_QEI_INTSTAT_OFFSET) +#define LPC43_QEI_IE (LPC43_QEI_BASE+LPC43_QEI_IE_OFFSET) +#define LPC43_QEI_CLR (LPC43_QEI_BASE+LPC43_QEI_CLR_OFFSET) +#define LPC43_QEI_SET (LPC43_QEI_BASE+LPC43_QEI_SET_OFFSET) + +/* Register bit definitions *********************************************************/ +/* The following registers hold 32-bit integer values and have no bit fields defined + * in this section: + * + * Position register (POS) + * Maximum position register (MAXPOS) + * Position compare register 0 (CMPOS0) + * Position compare register 1 (CMPOS1) + * Position compare register 2 (CMPOS2) + * Index count register (INXCNT) + * Index compare register 0 (INXCMP0) + * Index compare register 1 (INXCMP1) + * Index compare register 2 (INXCMP2) + * Velocity timer reload register (LOAD) + * Velocity timer register (TIME) + * Velocity counter register (VEL) + * Velocity capture register (CAP) + * Velocity compare register (VELCOMP) + * Digital filter registers (FLTRPHA, FLTRPHB) + * Digital filter index register (FLTINX) + * Index acceptance window register (WINDOW) + */ + +/* Control registers */ +/* Control register */ + +#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */ +#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */ +#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */ +#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */ + /* Bits 4-31: reserved */ +/* Encoder status register */ + +#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */ + /* Bits 1-31: reserved */ +/* Configuration register */ + +#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */ +#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */ +#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */ +#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */ +#define QEI_CONF_CRESPI (1 << 4) /* Bit 4: Reset position counter on index */ + /* Bits 1-15: reserved */ +#define QEI_CONF_INXGATE_SHIFT (16) /* Bits 16-19: Index gating configuration */ +#define QEI_CONF_INXGATE_MASK (15 << QEI_CONF_INXGATE_SHIFT) +# define QEI_CONF_INXGATE_A1B0 (1 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=1 Phb=0 */ +# define QEI_CONF_INXGATE_A1B1 (2 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=1 Phb=1 */ +# define QEI_CONF_INXGATE_A0B1 (4 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=0 Phb=1 */ +# define QEI_CONF_INXGATE_A0B0 (8 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=0 Phb=0 */ + /* Bits 4-31: reserved */ + +/* Interrupt registers */ +/* Interrupt enable clear register (IEC), Interrupt enable set register (IES), + * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt + * status clear register (CLR), and Interrupt status set register (SET) common + * bit definitions. + */ + +#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */ +#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */ +#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */ +#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */ +#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */ +#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */ +#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */ +#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */ +#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */ +#define QEI_INT_REV0 (1 << 9) /* Bit 9: Index 0 compare equal to current index count */ +#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Position 0 and revolution count interrupt */ +#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */ +#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */ +#define QEI_INT_REV1 (1 << 13) /* Bit 13: Index 1 compare equal to current index count */ +#define QEI_INT_REV2 (1 << 14) /* Bit 14: Index 2 compare equal to current index count */ +#define QEI_INT_MAXPOS (1 << 15) /* Bit 15: Current position count goes through MAXPOS */ + /* Bits 16-31: reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h new file mode 100644 index 000000000..129ddebba --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h @@ -0,0 +1,230 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_rtc.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Miscellaneous registers */ + +#define LPC43_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */ +#define LPC43_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */ +#define LPC43_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */ +#define LPC43_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */ + +/* Consolidated time registers */ + +#define LPC43_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */ +#define LPC43_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */ +#define LPC43_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */ + +/* Time counter registers */ + +#define LPC43_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */ +#define LPC43_RTC_MIN_OFFSET 0x0024 /* Minutes Register */ +#define LPC43_RTC_HOUR_OFFSET 0x0028 /* Hours Register */ +#define LPC43_RTC_DOM_OFFSET 0x002c /* Day of Month Register */ +#define LPC43_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */ +#define LPC43_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */ +#define LPC43_RTC_MONTH_OFFSET 0x0038 /* Months Register */ +#define LPC43_RTC_YEAR_OFFSET 0x003c /* Years Register */ +#define LPC43_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */ + +/* Alarm register group */ + +#define LPC43_RTC_ASEC_OFFSET 0x0060 /* Alarm value for Seconds */ +#define LPC43_RTC_AMIN_OFFSET 0x0064 /* Alarm value for Minutes */ +#define LPC43_RTC_AHOUR_OFFSET 0x0068 /* Alarm value for Hours */ +#define LPC43_RTC_ADOM_OFFSET 0x006c /* Alarm value for Day of Month */ +#define LPC43_RTC_ADOW_OFFSET 0x0070 /* Alarm value for Day of Week */ +#define LPC43_RTC_ADOY_OFFSET 0x0074 /* Alarm value for Day of Year */ +#define LPC43_RTC_AMON_OFFSET 0x0078 /* Alarm value for Months */ +#define LPC43_RTC_AYEAR_OFFSET 0x007c /* Alarm value for Year */ + +/* Register addresses ***************************************************************/ +/* Miscellaneous registers */ + +#define LPC43_RTC_ILR (LPC43_RTC_BASE+LPC43_RTC_ILR_OFFSET) +#define LPC43_RTC_CCR (LPC43_RTC_BASE+LPC43_RTC_CCR_OFFSET) +#define LPC43_RTC_CIIR (LPC43_RTC_BASE+LPC43_RTC_CIIR_OFFSET) +#define LPC43_RTC_AMR (LPC43_RTC_BASE+LPC43_RTC_AMR_OFFSET) + +/* Consolidated time registers */ + +#define LPC43_RTC_CTIME0 (LPC43_RTC_BASE+LPC43_RTC_CTIME0_OFFSET) +#define LPC43_RTC_CTIME1 (LPC43_RTC_BASE+LPC43_RTC_CTIME1_OFFSET) +#define LPC43_RTC_CTIME2 (LPC43_RTC_BASE+LPC43_RTC_CTIME2_OFFSET) + +/* Time counter registers */ + +#define LPC43_RTC_SEC (LPC43_RTC_BASE+LPC43_RTC_SEC_OFFSET) +#define LPC43_RTC_MIN (LPC43_RTC_BASE+LPC43_RTC_MIN_OFFSET) +#define LPC43_RTC_HOUR (LPC43_RTC_BASE+LPC43_RTC_HOUR_OFFSET) +#define LPC43_RTC_DOM (LPC43_RTC_BASE+LPC43_RTC_DOM_OFFSET) +#define LPC43_RTC_DOW (LPC43_RTC_BASE+LPC43_RTC_DOW_OFFSET) +#define LPC43_RTC_DOY (LPC43_RTC_BASE+LPC43_RTC_DOY_OFFSET) +#define LPC43_RTC_MONTH (LPC43_RTC_BASE+LPC43_RTC_MONTH_OFFSET) +#define LPC43_RTC_YEAR (LPC43_RTC_BASE+LPC43_RTC_YEAR_OFFSET) +#define LPC43_RTC_CALIB (LPC43_RTC_BASE+LPC43_RTC_CALIB_OFFSET) + +/* Alarm register group */ + +#define LPC43_RTC_ASEC (LPC43_RTC_BASE+LPC43_RTC_ASEC_OFFSET) +#define LPC43_RTC_AMIN (LPC43_RTC_BASE+LPC43_RTC_AMIN_OFFSET) +#define LPC43_RTC_AHOUR (LPC43_RTC_BASE+LPC43_RTC_AHOUR_OFFSET) +#define LPC43_RTC_ADOM (LPC43_RTC_BASE+LPC43_RTC_ADOM_OFFSET) +#define LPC43_RTC_ADOW (LPC43_RTC_BASE+LPC43_RTC_ADOW_OFFSET) +#define LPC43_RTC_ADOY (LPC43_RTC_BASE+LPC43_RTC_ADOY_OFFSET) +#define LPC43_RTC_AMON (LPC43_RTC_BASE+LPC43_RTC_AMON_OFFSET) +#define LPC43_RTC_AYEAR (LPC43_RTC_BASE+LPC43_RTC_AYEAR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Miscellaneous registers */ +/* Interrupt Location Register */ + +#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */ +#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */ + /* Bits 2-31: Reserved */ +/* Clock Control Register */ + +#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */ +#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */ + /* Bits 2-3: Internal test mode controls */ +#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */ + /* Bits 5-31: Reserved */ +/* Counter Increment Interrupt Register */ + +#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */ +#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */ +#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */ +#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */ +#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */ +#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */ +#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */ +#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */ + /* Bits 8-31: Reserved */ +/* Alarm Mask Register */ + +#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */ +#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */ +#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */ +#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */ +#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */ +#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */ +#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */ +#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */ + /* Bits 8-31: Reserved */ +/* Consolidated time registers */ +/* Consolidated Time Register 0 */ + +#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */ +#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT) + /* Bits 6-7: Reserved */ +#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */ +#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT) + /* Bits 14-15: Reserved */ +#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */ +#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT) + /* Bits 21-23: Reserved */ +#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */ +#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT) + /* Bits 27-31: Reserved */ +/* Consolidated Time Register 1 */ + +#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */ +#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT) + /* Bits 5-7: Reserved */ +#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */ +#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT) + /* Bits 12-15: Reserved */ +#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */ +#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT) + /* Bits 28-31: Reserved */ +/* Consolidated Time Register 2 */ + +#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */ +#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT) + /* Bits 12-31: Reserved */ +/* Time counter registers */ + +#define RTC_SEC_MASK (0x003f) +#define RTC_MIN_MASK (0x003f) +#define RTC_HOUR_MASK (0x001f) +#define RTC_DOM_MASK (0x001f) +#define RTC_DOW_MASK (0x0007) +#define RTC_DOY_MASK (0x01ff) +#define RTC_MONTH_MASK (0x000f) +#define RTC_YEAR_MASK (0x0fff) + +/* Calibration Value Register */ + +#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */ +#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT) +#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */ + /* Bits 18-31: Reserved */ +/* Alarm register group */ + +#define RTC_ASEC_MASK (0x003f) +#define RTC_AMIN_MASK (0x003f) +#define RTC_AHOUR_MASK (0x001f) +#define RTC_ADOM_MASK (0x001f) +#define RTC_ADOW_MASK (0x0007) +#define RTC_ADOY_MASK (0x01ff) +#define RTC_AMON_MASK (0x000f) +#define RTC_AYEAR_MASK (0x0fff) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spi.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spi.h index b00ddb2e9..8756deff7 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spi.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spi.h @@ -42,9 +42,6 @@ #include -#include "chip.h" -#include "lpc43_memorymap.h" - /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -- cgit v1.2.3