From bd80f60429b690058fe41c721bc95862975ed42e Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 5 Apr 2009 18:53:33 +0000 Subject: Add GPIO definitions git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1685 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/imx/chip.h | 1 + nuttx/arch/arm/src/imx/imx_gpio.h | 182 +++++++++++++++++++++++++++++++++ nuttx/arch/arm/src/imx/imx_memorymap.h | 8 -- 3 files changed, 183 insertions(+), 8 deletions(-) create mode 100755 nuttx/arch/arm/src/imx/imx_gpio.h diff --git a/nuttx/arch/arm/src/imx/chip.h b/nuttx/arch/arm/src/imx/chip.h index 192100f6c..2267a827c 100644 --- a/nuttx/arch/arm/src/imx/chip.h +++ b/nuttx/arch/arm/src/imx/chip.h @@ -49,6 +49,7 @@ #include "imx_usbd.h" #include "imx_i2c.h" #include "imx_cspi.h" +#include "imx_gpio.h" #include "imx_aitc.h" /************************************************************************************ diff --git a/nuttx/arch/arm/src/imx/imx_gpio.h b/nuttx/arch/arm/src/imx/imx_gpio.h new file mode 100755 index 000000000..1265f2658 --- /dev/null +++ b/nuttx/arch/arm/src/imx/imx_gpio.h @@ -0,0 +1,182 @@ +/************************************************************************************ + * arch/arm/src/imx/imx_gpio.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_GPIO_H +#define __ARCH_ARM_IMX_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* GPIO Register Offsets ************************************************************/ + +#define GPIO_DDIR_OFFSET 0x0000 /* Data Direction Register */ +#define GPIO_OCR1_OFFSET 0x0004 /* Output Configuration Register 1 */ +#define GPIO_OCR2_OFFSET 0x0008 /* Output Configuration Register 2 */ +#define GPIO_ICONFA1_OFFSET 0x000c /* Input Configuration Register A1 */ +#define GPIO_ICONFA2_OFFSET 0x0010 /* Input Configuration Register A2 */ +#define GPIO_ICONFB1_OFFSET 0x0014 /* Input Configuration Register B1 */ +#define GPIO_ICONFB2_OFFSET 0x0018 /* Input Configuration Register B2 */ +#define GPIO_DR_OFFSET 0x001c /* Data Register */ +#define GPIO_GIUS_OFFSET 0x0020 /* GPIO In Use Register */ +#define GPIO_SSR_OFFSET 0x0024 /* Sample Status Register */ +#define GPIO_ICR1_OFFSET 0x0028 /* Interrupt Configuration Register 1 */ +#define GPIO_ICR2_OFFSET 0x002c /* Interrupt Configuration Register 2 */ +#define GPIO_IMR_OFFSET 0x0030 /* Interrupt Mask Register */ +#define GPIO_ISR_OFFSET 0x0034 /* Interrupt Status Register */ +#define GPIO_GPR_OFFSET 0x0038 /* General Purpose Register */ +#define GPIO_SWR_OFFSET 0x003c /* Software Reset Register */ +#define GPIO_PUEN_OFFSET 0x0040 /* Pull_Up Enable Register */ + +#define GPIO_PTA_OFFSET 0x0000 /* Port A offset */ +#define GPIO_PTB_OFFSET 0x0100 /* Port B offset */ +#define GPIO_PTC_OFFSET 0x0200 /* Port C offset */ +#define GPIO_PTD_OFFSET 0x0300 /* Port D offset */ + +#define GPIOA 0 /* Port A index */ +#define GPIOB 1 /* Port B index */ +#define GPIOC 2 /* Port C index */ +#define GPIOD 3 /* Port D index */ +#define GPIO_PT_OFFSET(n) (GPIO_PTA_OFFSET + (n)*0x0100) + +/* GPIO Register Addresses **********************************************************/ + +#define IMX_PTA_VBASE (IMX_GPIO_VBASE + GPIO_PTA_OFFSET) +#define IMX_PTB_VBASE (IMX_GPIO_VBASE + GPIO_PTB_OFFSET) +#define IMX_PTC_VBASE (IMX_GPIO_VBASE + GPIO_PTC_OFFSET) +#define IMX_PTD_VBASE (IMX_GPIO_VBASE + GPIO_PTD_OFFSET) +#define IMX_PT_VBASE(n) (IMX_GPIO_VBASE + GPIO_PT_OFFSET(n)) + +#define IMX_GPIOA_DDIR (IMX_PTA_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOA_OCR1 (IMX_PTA_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOA_OCR2 (IMX_PTA_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOA_ICONFA1 (IMX_PTA_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOA_ICONFA2 (IMX_PTA_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOA_ICONFB1 (IMX_PTA_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOA_ICONFB2 (IMX_PTA_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOA_DR (IMX_PTA_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOA_GIUS (IMX_PTA_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOA_SSR (IMX_PTA_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOA_ICR1 (IMX_PTA_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOA_ICR2 (IMX_PTA_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOA_IMR (IMX_PTA_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOA_ISR (IMX_PTA_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOA_GPR (IMX_PTA_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOA_SWR (IMX_PTA_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOA_PUEN (IMX_PTA_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOB_DDIR (IMX_PTB_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOB_OCR1 (IMX_PTB_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOB_OCR2 (IMX_PTB_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOB_ICONFA1 (IMX_PTB_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOB_ICONFA2 (IMX_PTB_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOB_ICONFB1 (IMX_PTB_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOB_ICONFB2 (IMX_PTB_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOB_DR (IMX_PTB_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOB_GIUS (IMX_PTB_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOB_SSR (IMX_PTB_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOB_ICR1 (IMX_PTB_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOB_ICR2 (IMX_PTB_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOB_IMR (IMX_PTB_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOB_ISR (IMX_PTB_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOB_GPR (IMX_PTB_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOB_SWR (IMX_PTB_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOB_PUEN (IMX_PTB_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOC_DDIR (IMX_PTC_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOC_OCR1 (IMX_PTC_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOC_OCR2 (IMX_PTC_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOC_ICONFA1 (IMX_PTC_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOC_ICONFA2 (IMX_PTC_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOC_ICONFB1 (IMX_PTC_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOC_ICONFB2 (IMX_PTC_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOC_DR (IMX_PTC_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOC_GIUS (IMX_PTC_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOC_SSR (IMX_PTC_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOC_ICR1 (IMX_PTC_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOC_ICR2 (IMX_PTC_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOC_IMR (IMX_PTC_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOC_ISR (IMX_PTC_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOC_GPR (IMX_PTC_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOC_SWR (IMX_PTC_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOC_PUEN (IMX_PTC_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOD_DDIR (IMX_PTD_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOD_OCR1 (IMX_PTD_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOD_OCR2 (IMX_PTD_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOD_ICONFA1 (IMX_PTD_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOD_ICONFA2 (IMX_PTD_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOD_ICONFB1 (IMX_PTD_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOD_ICONFB2 (IMX_PTD_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOD_DR (IMX_PTD_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOD_GIUS (IMX_PTD_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOD_SSR (IMX_PTD_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOD_ICR1 (IMX_PTD_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOD_ICR2 (IMX_PTD_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOD_IMR (IMX_PTD_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOD_ISR (IMX_PTD_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOD_GPR (IMX_PTD_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOD_SWR (IMX_PTD_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOD_PUEN (IMX_PTD_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIO_DDIR(n) (IMX_PT_VBASE(n) + GPIO_DDIR_OFFSET) +#define IMX_GPIO_OCR1(n) (IMX_PT_VBASE(n) + GPIO_OCR1_OFFSET) +#define IMX_GPIO_OCR2(n) (IMX_PT_VBASE(n) + GPIO_OCR2_OFFSET) +#define IMX_GPIO_ICONFA1(n) (IMX_PT_VBASE(n) + GPIO_ICONFA1_OFFSET) +#define IMX_GPIO_ICONFA2(n) (IMX_PT_VBASE(n) + GPIO_ICONFA2_OFFSET) +#define IMX_GPIO_ICONFB1(n) (IMX_PT_VBASE(n) + GPIO_ICONFB1_OFFSET) +#define IMX_GPIO_ICONFB2(n) (IMX_PT_VBASE(n) + GPIO_ICONFB2_OFFSET) +#define IMX_GPIO_DR(n) (IMX_PT_VBASE(n) + GPIO_DR_OFFSET) +#define IMX_GPIO_GIUS(n) (IMX_PT_VBASE(n) + GPIO_GIUS_OFFSET) +#define IMX_GPIO_SSR(n) (IMX_PT_VBASE(n) + GPIO_SSR_OFFSET) +#define IMX_GPIO_ICR1(n) (IMX_PT_VBASE(n) + GPIO_ICR1_OFFSET) +#define IMX_GPIO_ICR2(n) (IMX_PT_VBASE(n) + GPIO_ICR2_OFFSET) +#define IMX_GPIO_IMR(n) (IMX_PT_VBASE(n) + GPIO_IMR_OFFSET) +#define IMX_GPIO_ISR(n) (IMX_PT_VBASE(n) + GPIO_ISR_OFFSET) +#define IMX_GPIO_GPR(n) (IMX_PT_VBASE(n) + GPIO_GPR_OFFSET) +#define IMX_GPIO_SWR(n) (IMX_PT_VBASE(n) + GPIO_SWR_OFFSET) +#define IMX_GPIO_PUEN(n) (IMX_PT_VBASE(n) + GPIO_PUEN_OFFSET) + +/* GPIO Register Bit Definitions ****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_GPIO_H */ diff --git a/nuttx/arch/arm/src/imx/imx_memorymap.h b/nuttx/arch/arm/src/imx/imx_memorymap.h index 44cfc7092..4ce805900 100644 --- a/nuttx/arch/arm/src/imx/imx_memorymap.h +++ b/nuttx/arch/arm/src/imx/imx_memorymap.h @@ -107,10 +107,6 @@ #define IMX_PLL_OFFSET 0x0001b000 #define IMX_SC_OFFSET 0x0001b800 #define IMX_GPIO_OFFSET 0x0001c000 /* -0x0001cfff GPIO 4Kb */ -#define IMX_PTA_OFFSET 0x0001c000 -#define IMX_PTB_OFFSET 0x0001c100 -#define IMX_PTC_OFFSET 0x0001c200 -#define IMX_PTD_OFFSET 0x0001c300 /* -0x0001ffff Reserved 12Kb */ #define IMX_EIM_OFFSET 0x00020000 /* -0x00020fff WEIM 4Kb */ #define IMX_SDRAMC_OFFSET 0x00021000 /* -0x00021fff SDRAMC 4Kb */ @@ -148,10 +144,6 @@ #define IMX_PLL_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PLL_OFFSET) #define IMX_SC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SC_OFFSET) #define IMX_GPIO_VBASE (IMX_PERIPHERALS_VSECTION + IMX_GPIO_OFFSET) -#define IMX_PTA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PTA_OFFSET) -#define IMX_PTB_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PTB_OFFSET) -#define IMX_PTC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PTC_OFFSET) -#define IMX_PTD_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PTD_OFFSET) #define IMX_EIM_VBASE (IMX_PERIPHERALS_VSECTION + IMX_EIM_OFFSET) #define IMX_SDRAMC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SDRAMC_OFFSET) #define IMX_DSPA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_DSPA_OFFSET) -- cgit v1.2.3