From 5fd4464082c064fc73e0b160c7779cf1564056c5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 3 Sep 2010 15:14:28 +0000 Subject: Add LM3S8962 support git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2914 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lm3s/chip.h | 11 ++++ nuttx/arch/arm/src/lm3s/lm3s_gpio.c | 7 +-- nuttx/arch/arm/src/lm3s/lm3s_internal.h | 43 +++++++++++++++ nuttx/arch/arm/src/lm3s/lm3s_ssi.c | 2 +- nuttx/arch/arm/src/lm3s/lm3s_vectors.S | 95 +++++++++++++++++++++++++++++++++ 5 files changed, 154 insertions(+), 4 deletions(-) (limited to 'nuttx/arch/arm/src/lm3s') diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h index 511b2e378..94bc6ef1a 100644 --- a/nuttx/arch/arm/src/lm3s/chip.h +++ b/nuttx/arch/arm/src/lm3s/chip.h @@ -82,6 +82,17 @@ # define LM3S_NPWM 4 /* Four PWM generator modules */ # define LM3S_NQEI 2 /* Two quadrature encoders */ # define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LM3S_NSSI 1 /* One SSI module */ +# define LM3S_NUARTS 3 /* Two UART modules */ +# define LM3S_NI2C 2 /* One I2C module */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 3 /* Three PWM generator modules */ +# define LM3S_NQEI 2 /* Two quadrature encoders */ +# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */ +# define LC3S_CANCONTROLLER 1 /* One CAN controller */ #else # error "Capabilities not specified for this LM3S chip" #endif diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c index db88343ee..a57b792ab 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c @@ -147,13 +147,13 @@ static const uint32_t g_gpiobase[LM3S_NPORTS] = LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, - /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 */ + /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/ #if LM3S_NPORTS > 7 LM3S_GPIOH_BASE, #endif - /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 */ + /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/ #if LM3S_NPORTS > 8 LM3S_GPIOJ_BASE, @@ -850,4 +850,5 @@ bool lm3s_gpioread(uint32_t pinset, bool value) */ return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0); -} \ No newline at end of file +} + diff --git a/nuttx/arch/arm/src/lm3s/lm3s_internal.h b/nuttx/arch/arm/src/lm3s/lm3s_internal.h index 759a667fd..38a079743 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_internal.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_internal.h @@ -294,6 +294,49 @@ # define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ # define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ # define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ + + +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM0 (CCP1) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 0 output (C0o) ( differs) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 6) /* PC6: QEI module 0 phase B. */ +# define GPIO_CAN0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 0) /* PD0: CAN module RX */ +# define GPIO_CAN0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: CAN module TX */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PD4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC7: /* PD0: QEI module 0 index. ) */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PF0: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ #else # error "Unknown LM3S chip" #endif diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c index ac3924451..8c3929ad7 100755 --- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c @@ -77,7 +77,7 @@ #endif /* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI - * modules, the LM3S6965 supports 1 module (others may support more than 2-- in + * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in * such case, the following must be expanded). */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S index e1f2919a4..fe839bc48 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S +++ b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S @@ -296,6 +296,62 @@ lm3s_vectors: .word lm3s_epi /* Vector 69: Reserved */ .word lm3s_gpioj /* Vector 70: GPIO J */ .word lm3s_reserved /* Vector 71: Reserved */ + #elif defined(CONFIG_ARCH_CHIP_LM3S8962) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_pwmfault /* Vector 25: PWM Fault */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm3s_qei0 /* Vector 29: QEI0 */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_reserved /* Vector 42: Reserved */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_reserved /* Vector 48: Reserved */ + .word lm3s_reserved /* Vector 49: Reserved */ + .word lm3s_reserved /* Vector 50: Reserved */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_reserved /* Vector 53: Reserved*/ + .word lm3s_qei1 /* Vector 54: QEI1 */ + .word lm3s_can0 /* Vector 55: Can Controller */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_hib /* Vector 59: Hibernation Module */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ #else # error "Vectors not specified for this LM3S chip" #endif @@ -393,6 +449,45 @@ handlers: HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ + #elif defined(CONFIG_ARCH_CHIP_LM3S8962) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ -- cgit v1.2.3