From 18f9d0eaa3b20a4c3a11c9a3f4e60a150e11d69f Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 19 Mar 2013 13:33:00 +0000 Subject: More LPC1788 updates from Rommel Marcelo git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5759 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/chip.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'nuttx/arch/arm/src/lpc17xx/chip.h') diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index 4138ef934..6691ab8b0 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -61,17 +61,15 @@ # endif #endif -/* Vector Table Offset Register (VECTAB). Redefine some bits defined in +/* Vector Table Offset Register (VECTAB). Redefine the mask defined in * arch/arm/src/armv7-m/nvic.h; The LPC178x/7x User manual definitions - * do not match the ARMv7M field definitions. + * do not match the ARMv7M field definitions. Any bits set above bit + * 29 would be an error and apparently the register wants 8- not 6-bit + * alignment. */ #undef NVIC_VECTAB_TBLOFF_MASK #define NVIC_VECTAB_TBLOFF_MASK (0x3fffff00) -#undef NVIC_VECTAB_TBLBASE -#define NVIC_VECTAB_TBLBASE (1 << 29) -#undef NVIC_VECTAB_ALIGN_MASK -#define NVIC_VECTAB_ALIGN_MASK (0x000000ff) /* Include the memory map file. Other chip hardware files should then include * this file for the proper setup. -- cgit v1.2.3