From ecddebad71bd2eb04d208be607cfe3419209c2a6 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 20 Jun 2010 17:07:13 +0000 Subject: Correct conditional compilation git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2756 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c') diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c index 83a3e7a67..ad542534a 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c @@ -104,7 +104,7 @@ void lpc17_clockconfig(void) /* PLL0 is used to generate the CPU clock divider input (PLLCLK). */ -#if CONFIG_LPC17_PLL0 +#ifdef CONFIG_LPC17_PLL0 /* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that * a special "feed" sequence must be written to the PLL0FEED register in order * for changes to the PLL0CFG register to take effect. -- cgit v1.2.3