From 28d607865c3224b7398f9715039bb8d31537ee1c Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 1 May 2007 00:28:53 +0000 Subject: Low level UART support git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@196 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc214x/chip.h | 53 +++++++++++++++++++++++++++++++-------- 1 file changed, 42 insertions(+), 11 deletions(-) (limited to 'nuttx/arch/arm/src/lpc214x/chip.h') diff --git a/nuttx/arch/arm/src/lpc214x/chip.h b/nuttx/arch/arm/src/lpc214x/chip.h index 09f0ba342..f1e863c7d 100644 --- a/nuttx/arch/arm/src/lpc214x/chip.h +++ b/nuttx/arch/arm/src/lpc214x/chip.h @@ -40,6 +40,10 @@ * Included Files ************************************************************************************/ +/************************************************************************************ + * Definitions + ************************************************************************************/ + /* Memory Map ***********************************************************************/ #define LPC214X_FLASH_BASE 0x00000000 @@ -52,19 +56,50 @@ /* Register block base addresses */ +#define LPC214X_UART0_BASE 0xe000c000 /* UART0 Base Address */ +#define LPC214X_UART1_BASE 0xe0010000 /* UART1 Base Address */ +#define LPC214X_PINSEL_BASE 0xc002c000 /* Pin funtion select registers */ #define LPC214X_MAM_BASE 0xe01fc000 /* Memory Accelerator Module (MAM) Base Address */ #define LPC214X_MEMMAP 0xe01fc040 /* Memory Mapping Control */ #define LPC214X_PLL_BASE 0xe01fc080 /* Phase Locked Loop (PLL) Base Address */ #define LPC214X_VPBDIV 0xe01fc100 /* VPBDIV Address */ -#define LPC214X_PINSEL2 0xe002c014 /* PINSEL2 Address */ #define LPC214X_EMC_BASE 0xffe00000 /* External Memory Controller (EMC) Base Address */ +/* UART0/1 Register Offsets */ +#define LPC214X_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */ +#define LPC214X_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */ +#define LPC214X_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB) */ +#define LPC214X_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */ +#define LPC214X_DLM_OFFSET 0x04 /* R/W: Divisor Latch Register (MSB, DLAB=1) */ +#define LPC214X_IIR_OFFSET 0x08 /* R: Interrupt ID Register (DLAB=) */ +#define LPC214X_FCR_OFFSET 0x08 /* W: FIFO Control Register */ +#define LPC214X_LCR_OFFSET 0x0c /* R/W: Line Control Register */ +#define LPC214X_MCR_OFFSET 0x10 /* R/W: Modem Control REgister (2146/6/8 UART1 Only) */ +#define LPC214X_LSR_OFFSET 0x14 /* R: Scratch Pad Register */ +#define LPC214X_MSR_OFFSET 0x18 /* R/W: MODEM Status Register (2146/6/8 UART1 Only) */ +#define LPC214X_SCR_OFFSET 0x1c /* R/W: Line Status Register */ +#define LPC214X_ACR_OFFSET 0x20 /* R/W: Autobaud Control Register */ +#define LPC214X_FDR_OFFSET 0x28 /* R/W: Fractional Divider Register */ +#define LPC214X_TER_OFFSET 0x30 /* R/W: Transmit Enable Register */ + +/* Pin function select register offsets */ + +#define LPC214X_PINSEL0_OFFSET 0x00 /* Pin function select register 0 */ +#define LPC214X_PINSEL1_OFFSET 0x04 /* Pin function select register 1 */ +#define LPC214X_PINSEL2_OFFSET 0x14 /* Pin function select register 2 */ + +/* Pin function select registers (these are normally referenced as offsets) */ + +#define LPC214X_PINSEL0 (LPC214X_PINSEL_BASE + LPC214X_PINSEL0_OFFSET) +#define LPC214X_PINSEL1 (LPC214X_PINSEL_BASE + LPC214X_PINSEL1_OFFSET) +#define LPC214X_PINSEL2 (LPC214X_PINSEL_BASE + LPC214X_PINSEL2_OFFSET) + /* Memory Accelerator Module (MAM) Regiser Offsets */ #define LPC214X_MAMCR_OFFSET 0x00 /* MAM Control Offset*/ #define LPC214x_MAMTIM_OFFSET 0x04 /* MAM Timing Offset */ -/* Phase Locked Loop (PLL) register offsets */ +/* Phase Locked Loop (PLL) Register Offsets */ #define LPC214X_PLLCON_OFFSET 0x00 /* PLL Control Offset*/ #define LPC214X_PLLCFG_OFFSET 0x04 /* PLL Configuration Offset */ @@ -73,14 +108,14 @@ /* PLL Control Register Bit Settings */ -#define LPC214X_PLLCON_PLLE (1<<0) /* PLL Enable */ -#define LPC214X_PLLCON_PLLC (1<<1) /* PLL Connect */ +#define LPC214X_PLLCON_PLLE (1 <<0) /* PLL Enable */ +#define LPC214X_PLLCON_PLLC (1 <<1) /* PLL Connect */ /* PLL Configuration Register Bit Settings */ -#define LPC214X_PLLCFG_MSEL (0x1f<<0) /* PLL Multiplier */ -#define LPC214X_PLLCFG_PSEL (0x03<<5) /* PLL Divider */ -#define LPC214X_PLLSTAT_PLOCK (1<<10) /* PLL Lock Status */ +#define LPC214X_PLLCFG_MSEL (0x1f << 0) /* PLL Multiplier */ +#define LPC214X_PLLCFG_PSEL (0x03 << 5) /* PLL Divider */ +#define LPC214X_PLLSTAT_PLOCK (1 << 10) /* PLL Lock Status */ /* External Memory Controller (EMC) definitions */ @@ -89,10 +124,6 @@ #define LPC214X_BCFG2_OFFSET 0x08 /* BCFG2 Offset */ #define LPC214X_BCFG3_OFFSET 0x0c /* BCFG3 Offset */ -/************************************************************************************ - * Definitions - ************************************************************************************/ - /************************************************************************************ * Inline Functions ************************************************************************************/ -- cgit v1.2.3