From 07ba2fa8d09cba4b1745b5c4fd2c58bd7ca551ec Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 5 May 2007 22:35:07 +0000 Subject: Add logic for system timer git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@204 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc214x/chip.h | 60 +++++----- nuttx/arch/arm/src/lpc214x/lpc214x_timer.h | 152 ++++++++++++++++++++++++++ nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c | 72 +++++++++++- nuttx/arch/arm/src/lpc214x/lpc214x_vic.h | 140 ++++++++++++------------ 4 files changed, 322 insertions(+), 102 deletions(-) create mode 100644 nuttx/arch/arm/src/lpc214x/lpc214x_timer.h (limited to 'nuttx/arch/arm/src/lpc214x') diff --git a/nuttx/arch/arm/src/lpc214x/chip.h b/nuttx/arch/arm/src/lpc214x/chip.h index 51ae83708..56089cf1d 100644 --- a/nuttx/arch/arm/src/lpc214x/chip.h +++ b/nuttx/arch/arm/src/lpc214x/chip.h @@ -92,44 +92,44 @@ #define LPC214X_WD_FEED_OFFSET 0x08 /* Watchdog Feed Register */ #define LPC214X_WD_TV_OFFSET 0x0C /* Watchdog Time Value Register */ -/* Timer 0 register offsets */ - -#define LPC214X_TMR_IR_OFFSET 0x00 /* Interrupt Register */ -#define LPC214X_TMR_TCR_OFFSET 0x04 /* Timer Control Register */ -#define LPC214X_TMR_TC_OFFSET 0x08 /* Timer Counter */ -#define LPC214X_TMR_PR_OFFSET 0x0c /* Prescale Register */ -#define LPC214X_TMR_PC_OFFSET 0x10 /* Prescale Counter Register */ -#define LPC214X_TMR_MCR_OFFSET 0x14 /* Match Control Register */ -#define LPC214X_TMR_MR0_OFFSET 0x18 /* Match Register 0 */ -#define LPC214X_TMR_MR1_OFFSET 0x1c /* Match Register 1 */ -#define LPC214X_TMR_MR2_OFFSET 0x20 /* Match Register 2 */ -#define LPC214X_TMR_MR3_OFFSET 0x24 /* Match Register 3 */ -#define LPC214X_TMR_CCR_OFFSET 0x28 /* Capture Control Register */ -#define LPC214X_TMR_CR0_OFFSET 0x2c /* Capture Register 0 */ -#define LPC214X_TMR_CR1_OFFSET 0x30 /* Capture Register 1 */ -#define LPC214X_TMR_CR2_OFFSET 0x34 /* Capture Register 2 */ -#define LPC214X_TMR_CR3_OFFSET 0x38 /* Capture Register 3 */ -#define LPC214X_TMR_EMR_OFFSET 0x3c /* External Match Register */ - -#define LPC214X_TMR_CTCR_OFFSET 0x70 /* Count Control Register */ +/* Timer 0/1 register offsets */ + +#define LPC214X_TMR_IR_OFFSET 0x00 /* RW:Interrupt Register */ +#define LPC214X_TMR_TCR_OFFSET 0x04 /* RW: Timer Control Register */ +#define LPC214X_TMR_TC_OFFSET 0x08 /* RW: Timer Counter */ +#define LPC214X_TMR_PR_OFFSET 0x0c /* RW: Prescale Register */ +#define LPC214X_TMR_PC_OFFSET 0x10 /* RW: Prescale Counter Register */ +#define LPC214X_TMR_MCR_OFFSET 0x14 /* RW: Match Control Register */ +#define LPC214X_TMR_MR0_OFFSET 0x18 /* RW: Match Register 0 */ +#define LPC214X_TMR_MR1_OFFSET 0x1c /* RW: Match Register 1 */ +#define LPC214X_TMR_MR2_OFFSET 0x20 /* RW: Match Register 2 */ +#define LPC214X_TMR_MR3_OFFSET 0x24 /* RW: Match Register 3 */ +#define LPC214X_TMR_CCR_OFFSET 0x28 /* RW: Capture Control Register */ +#define LPC214X_TMR_CR0_OFFSET 0x2c /* R: Capture Register 0 */ +#define LPC214X_TMR_CR1_OFFSET 0x30 /* R: Capture Register 1 */ +#define LPC214X_TMR_CR2_OFFSET 0x34 /* R: Capture Register 2 */ +#define LPC214X_TMR_CR3_OFFSET 0x38 /* RW: Capture Register 3 */ +#define LPC214X_TMR_EMR_OFFSET 0x3c /* RW: External Match Register */ + +#define LPC214X_TMR_CTCR_OFFSET 0x70 /* RW: Count Control Register */ /* UART0/1 Register Offsets */ #define LPC214X_UART_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */ #define LPC214X_UART_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */ -#define LPC214X_UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB) */ +#define LPC214X_UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB, DLAB=1) */ #define LPC214X_UART_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */ -#define LPC214X_UART_DLM_OFFSET 0x04 /* R/W: Divisor Latch Register (MSB, DLAB=1) */ -#define LPC214X_UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register (DLAB=) */ +#define LPC214X_UART_DLM_OFFSET 0x04 /* RW: Divisor Latch Register (MSB, DLAB=1) */ +#define LPC214X_UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register */ #define LPC214X_UART_FCR_OFFSET 0x08 /* W: FIFO Control Register */ -#define LPC214X_UART_LCR_OFFSET 0x0c /* R/W: Line Control Register */ -#define LPC214X_UART_MCR_OFFSET 0x10 /* R/W: Modem Control REgister (2146/6/8 UART1 Only) */ +#define LPC214X_UART_LCR_OFFSET 0x0c /* RW: Line Control Register */ +#define LPC214X_UART_MCR_OFFSET 0x10 /* RW: Modem Control REgister (2146/6/8 UART1 Only) */ #define LPC214X_UART_LSR_OFFSET 0x14 /* R: Scratch Pad Register */ -#define LPC214X_UART_MSR_OFFSET 0x18 /* R/W: MODEM Status Register (2146/6/8 UART1 Only) */ -#define LPC214X_UART_SCR_OFFSET 0x1c /* R/W: Line Status Register */ -#define LPC214X_UART_ACR_OFFSET 0x20 /* R/W: Autobaud Control Register */ -#define LPC214X_UART_FDR_OFFSET 0x28 /* R/W: Fractional Divider Register */ -#define LPC214X_UART_TER_OFFSET 0x30 /* R/W: Transmit Enable Register */ +#define LPC214X_UART_MSR_OFFSET 0x18 /* RW: MODEM Status Register (2146/6/8 UART1 Only) */ +#define LPC214X_UART_SCR_OFFSET 0x1c /* RW: Line Status Register */ +#define LPC214X_UART_ACR_OFFSET 0x20 /* RW: Autobaud Control Register */ +#define LPC214X_UART_FDR_OFFSET 0x28 /* RW: Fractional Divider Register */ +#define LPC214X_UART_TER_OFFSET 0x30 /* RW: Transmit Enable Register */ /* PWM register offsets */ diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_timer.h b/nuttx/arch/arm/src/lpc214x/lpc214x_timer.h new file mode 100644 index 000000000..f9cb91c5f --- /dev/null +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_timer.h @@ -0,0 +1,152 @@ +/************************************************************************************ + * lpc214x/lpc214x_timer.h + * + * Copyright (C) 2007 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name Gregory Nutt nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __LPC214X_TIMER_H +#define __LPC214X_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Timer registers are 8-, 16-bit and 32-bits wide */ + +/* Timer Interrupt Register Bit Definitions (8-bit) */ + +#define LPC214X_TMR_IR_MR0I (1 << 0) /* Interrupt flag for match channel 0 */ +#define LPC214X_TMR_IR_MR1I (1 << 1) /* Interrupt flag for match channel 1 */ +#define LPC214X_TMR_IR_MR2I (1 << 2) /* Interrupt flag for match channel 2 */ +#define LPC214X_TMR_IR_MR3I (1 << 3) /* Interrupt flag for match channel 3 */ +#define LPC214X_TMR_IR_CR0I (1 << 4) /* Interrupt flag for capture channel 0 event */ +#define LPC214X_TMR_IR_CR1I (1 << 5) /* Interrupt flag for capture channel 1 event */ +#define LPC214X_TMR_IR_CR2I (1 << 6) /* Interrupt flag for capture channel 2 event */ +#define LPC214X_TMR_IR_CR3I (1 << 7) /* Interrupt flag for capture channel 3 event */ +#define LPC214X_TMR_IR_ALLI (0xff) /* All timer interrupts */ + +/* Timer Control Register Bit Definitions (8-bits) */ + +#define LPC214X_TMR_CR_ENABLE (1 << 0) /* Counter Enable */ +#define LPC214X_TMR_CR_RESET (1 << 1) /* Countger Reset */ + +/* Timer Counter (32-bits, no bit fields) */ + +/* Timer Prescale Register Bit Definitions (32-bits, no bit fields) */ + +/* Timer Prescale Counter Register Bit Definitions */ + +/* Timer Match Control Register Bit Definitions (16-bit) */ + +#define LPC214X_TMR_MCR_MR0I (1 << 0) /* Enable Interrupt when MR0 matches TC */ +#define LPC214X_TMR_MCR_MR0R (1 << 1) /* Enable Reset of TC upon MR0 match */ +#define LPC214X_TMR_MCR_MR0S (1 << 2) /* Enable Stop of TC upon MR0 match */ +#define LPC214X_TMR_MCR_MR1I (1 << 3) /* Enable Interrupt when MR1 matches TC */ +#define LPC214X_TMR_MCR_MR1R (1 << 4) /* Enable Reset of TC upon MR1 match */ +#define LPC214X_TMR_MCR_MR1S (1 << 5) /* Enable Stop of TC upon MR1 match */ +#define LPC214X_TMR_MCR_MR2I (1 << 6) /* Enable Interrupt when MR2 matches TC */ +#define LPC214X_TMR_MCR_MR2R (1 << 7) /* Enable Reset of TC upon MR2 match */ +#define LPC214X_TMR_MCR_MR2S (1 << 8) /* Enable Stop of TC upon MR2 match */ +#define LPC214X_TMR_MCR_MR3I (1 << 9) /* Enable Interrupt when MR3 matches TC */ +#define LPC214X_TMR_MCR_MR3R (1 << 10) /* Enable Reset of TC upon MR3 match */ +#define LPC214X_TMR_MCR_MR3S (1 << 11) /* Enable Stop of TC upon MR3 match */ + +/* Timer Match Register 0/1/2/3 (32-bits, no bit fields) */ + +/* Timer Capture Control Register Bit Definitions */ + +#define LPC214X_TMR_CCR_CAP0RE (1 << 0) /* Enable Rising edge on CAPn.0 will load TC to CR0 */ +#define LPC214X_TMR_CCR_CAP0FE (1 << 1) /* Enable Falling edge on CAPn.0 will load TC to CR0 */ +#define LPC214X_TMR_CCR_CAP0I (1 << 2) /* Enable Interrupt on load of CR0 */ +#define LPC214X_TMR_CCR_CAP1RE (1 << 3) /* Enable Rising edge on CAPn.1 will load TC to CR1 */ +#define LPC214X_TMR_CCR_CAP1FE (1 << 4) /* Enable Falling edge on CAPn.1 will load TC to CR1 */ +#define LPC214X_TMR_CCR_CAP1I (1 << 5) /* Enable Interrupt on load of CR1 */ +#define LPC214X_TMR_CCR_CAP2RE (1 << 6) /* Enable Rising edge on CAPn.2 will load TC to CR2 */ +#define LPC214X_TMR_CCR_CAP2FE (1 << 7) /* Enable Falling edge on CAPn.2 will load TC to CR2 */ +#define LPC214X_TMR_CCR_CAP2I (1 << 8) /* Enable Interrupt on load of CR2 */ +#define LPC214X_TMR_CCR_CAP3RE (1 << 9) /* Enable Rising edge on CAPn.3 will load TC to CR3 */ +#define LPC214X_TMR_CCR_CAP3FE (1 << 10) /* Enable Falling edge on CAPn.3 will load TC to CR3 */ +#define LPC214X_TMR_CCR_CAP3I (1 << 11) /* Enable Interrupt on load of CR3 */ + +/* Timer Capture Register 0/1/2/3 (32-bits, no bit fields) */ + +/* Timer External Match Register Bit Definitions */ + +#define LPC214X_TMR_EMR_EM0 (1 << 0) /* External Match 0 */ +#define LPC214X_TMR_EMR_EM1 (1 << 1) /* External Match 1 */ +#define LPC214X_TMR_EMR_EM2 (1 << 2) /* External Match 2 */ +#define LPC214X_TMR_EMR_EM3 (1 << 3) /* External Match 3 */ + +#define LPC214X_TMR_EMR_EMC0(b) ((b) << 4) /* External match control 0 (see below) */ +#define LPC214X_TMR_EMR_EMC1(b) ((b) << 6) /* External match control 1 (see below) */ +#define LPC214X_TMR_EMR_EMC2(b) ((b) << 8) /* External match control 2 (see below) */ +#define LPC214X_TMR_EMR_EMC3(b) ((b) << 10) /* External match control 3 (see below) */ + +/* EMR External Match Control (EMCn) Field Falues */ + +#define LPC214X_TMR_EMR_MASK (3) /* Mask for all bits */ +#define LPC214X_TMR_EMR_NOOP (0) /* Do nothing */ +#define LPC214X_TMR_EMR_CLEAR (1) /* Clear corresponding EMn bit/output to 0 */ +#define LPC214X_TMR_EMR_SET (2) /* Set corresponding EMn bit/output to 1 */ +#define LPC214X_TMR_EMR_TOGGLE (3) /* Toggle corresponding EMn bit/output */ + +/* Timer Count Control Register Bit Definitions (8-bit) */ + +#define LPC214X_TMR_ +#define LPC214X_TMR_CTCR_MODE_MASK (3 << 0) /* Counter/Timer Mode */ +#define LPC214X_TMR_CTCR_PCLK (0 << 0) /* Rising edge of PCLK */ +#define LPC214X_TMR_CTCR_RISING (1 << 0) /* Rising edge of CAP input */ +#define LPC214X_TMR_CTDR_FALLING (2 << 0) /* Failing edge of CAP input */ +#define LPC214X_TMR_CTCR_BOTH (3 << 0) /* Both edges of CAP input */ +#define LPC214X_TMR_CTCR_INPUT_MASK (3 << 2) /* Counter Input Select */ +#define LPC214X_TMR_CTCR_CR0 (0 << 2) /* CAPn.0 */ +#define LPC214X_TMR_CTCR_CR1 (1 << 2) /* CAPn.1 */ +#define LPC214X_TMR_CTCR_CR2 (2 << 2) /* CAPn.2 */ +#define LPC214X_TMR_CTCR_CR3 (3 << 2) /* CAPn.3 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __LPC214X_TIMER_H */ diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c b/nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c index 16de968b2..8308200ba 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c @@ -41,14 +41,29 @@ #include #include #include +#include + #include "clock_internal.h" #include "up_internal.h" #include "up_arch.h" +#include "lpc214x_timer.h" +#include "lpc214x_vic.h" + /************************************************************ * Definitions ************************************************************/ +#define PCLKFREQ (LPC214X_FOSC/4) /* PCLK must be FOSC/4 */ + +#define tmr_getreg8(o) getreg8(LPC214X_TMR0_BASE+(o)) +#define tmr_getreg16(o) getreg16(LPC214X_TMR0_BASE+(o)) +#define tmr_getreg32(o) getreg32(LPC214X_TMR0_BASE+(o)) + +#define tmr_putreg8(o,v) putreg8((v), LPC214X_TMR0_BASE+(o)) +#define tmr_putreg16(o,v) putreg16((v), LPC214X_TMR0_BASE+(o)) +#define tmr_putreg32(o,v) putreg32((v), LPC214X_TMR0_BASE+(o)) + /************************************************************ * Private Types ************************************************************/ @@ -70,11 +85,25 @@ * ************************************************************/ +#ifdef CONFIG_VECTORED_INTERRUPTS +int up_timerisr(uint32 *regs) +#else int up_timerisr(int irq, uint32 *regs) +#endif { /* Process timer interrupt */ sched_process_timer(); + + /* Clear the MR0 match interrupt */ + + tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET); + + /* Reset the VIC as well */ + +#ifdef CONFIG_VECTORED_INTERRUPTS + vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET); +#endif return 0; } @@ -89,6 +118,45 @@ int up_timerisr(int irq, uint32 *regs) void up_timerinit(void) { -#warning "Not implemented" -} + uint16 mcr; + + /* Clear all match and capture event interrupts */ + + tmr_putreg8(LPC214X_TMR_IR_ALLI, LPC214X_TMR_IR_OFFSET); + + /* Clear the timer counter */ + tmr_putreg32(0, LPC214X_TMR_TC_OFFSET); + + /* No pre-scaler */ + + tmr_putreg32(0, LPC214X_TMR_PR_OFFSET); + + /* Set timer match registger to get a TICK_PER_SEC rate + * See arch/board.h and sched/os_internal.h + */ + + tmr_putreg32(LPC214X_PCLKFREQ/TICK_PER_SEC, LPC214X_TMR_MR0_OFFSET); + + /* Reset timer counter regiser and interrupt on match */ + mcr = tmr_getreg16(LPC214X_TMR_MCR_OFFSET); + mcr &= ~LPC214X_TMR_MCR_MR1I; + mcr |= (LPC214X_TMR_MCR_MR0I | LPC214X_TMR_MCR_MR0R); + tmr_putreg16(mcr, LPC214X_TMR_MCR_OFFSET); + + /* Enable counting */ + + tmr_putreg8(LPC214X_TMR_CR_ENABLE, LPC214X_TMR_TCR_OFFSET); + + /* Attach the timer interrupt vector */ + +#ifdef CONFIG_VECTORED_INTERRUPTS + up_attach_vector(LPC214X_IRQ_SYSTIMER, LPC214X_SYSTEMER_VEC, (vic_vector_t)up_timerisr); +#else + (void)irq_attach(LPC214X_IRQ_SYSTIMER, (xcpt_t)up_timerisr); +#endif + + /* And enable the timer interrupt */ + + up_enable_irq(LPC214X_IRQ_SYSTIMER); +} diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_vic.h b/nuttx/arch/arm/src/lpc214x/lpc214x_vic.h index dcc297030..7fecd9a31 100755 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_vic.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_vic.h @@ -1,70 +1,70 @@ -/************************************************************************************ - * lpc214x/vic.h - * - * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name Gregory Nutt nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __LPC214X_VIC_H -#define __LPC214X_VIC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* All VIC registers are 32-bits wide */ - -#define vic_getreg(o) getreg32(LPC214X_VIC_BASE+(o)) -#define vic_putreg(v,o) putreg32((v),LPC214X_VIC_BASE+(o)) - -// Vector Control Register bit definitions - -#define LPC214X_VECTCNTL_IRQMASK (0x0000001f) -#define LPC214X_VECTCNTL_IRQSHIFT (0) -#define LPC214X_VECTCNTL_ENABLE (1 << 5) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __LPC214X_VIC_H */ +/************************************************************************************ + * lpc214x/lpc214x_vic.h + * + * Copyright (C) 2007 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name Gregory Nutt nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __LPC214X_VIC_H +#define __LPC214X_VIC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* All VIC registers are 32-bits wide */ + +#define vic_getreg(o) getreg32(LPC214X_VIC_BASE+(o)) +#define vic_putreg(v,o) putreg32((v),LPC214X_VIC_BASE+(o)) + +/* Vector Control Register bit definitions */ + +#define LPC214X_VECTCNTL_IRQMASK (0x0000001f) +#define LPC214X_VECTCNTL_IRQSHIFT (0) +#define LPC214X_VECTCNTL_ENABLE (1 << 5) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __LPC214X_VIC_H */ -- cgit v1.2.3