From 418843fa16f1b23b44175dfc2eddfacc20a7eff5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 29 Sep 2009 18:56:20 +0000 Subject: Fix PU/PD config; improve MODE/CNF setting git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2106 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/stm32/stm32_gpio.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'nuttx/arch/arm/src/stm32/stm32_gpio.h') diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.h b/nuttx/arch/arm/src/stm32/stm32_gpio.h index 4e2c9f8ac..dc555b9ed 100644 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.h +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.h @@ -148,10 +148,13 @@ /* Port configuration register low */ -#define GPIO_CR_MODE_SHIFT(n) ((n) << 1) +#define GPIO_CR_MODE_SHIFT(n) ((n) << 2) #define GPIO_CR_MODE_MASK(n) (3 << GPIO_CR_MODE_SHIFT(n)) -#define GPIO_CRL_CNF_SHIFT(n) (2+((n) << 1)) -#define GPIO_CRL_CNF_MASK(n) (3 << GPIO_CRL_CNF_SHIFT(n)) +#define GPIO_CR_CNF_SHIFT(n) (2 + ((n) << 2)) +#define GPIO_CR_CNF_MASK(n) (3 << GPIO_CRL_CNF_SHIFT(n)) + +#define GPIO_CR_MODECNF_SHIFT(n) ((n) << 2) +#define GPIO_CR_MODECNF_MASK(n) (0x0f << GPIO_CR_MODECNF_SHIFT(n)) #define GPIO_CRL_MODE0_SHIFT (0) /* Bits 1:0: Port mode bits */ #define GPIO_CRL_MODE0_MASK (3 << GPIO_CRL_MODE0_SHIFT) -- cgit v1.2.3