From d15145a14005d75622dd44be1be0821975293366 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 14 Aug 2012 14:42:50 +0000 Subject: Revise recent changes to serial driver error handling: Errors other than EINTR may be returned when the driver is used very early in initialization. STM32 SPI driver will now survive repeated initializations git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5026 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/stm32/stm32_spi.c | 51 +++++++++++++++++++++++------------- 1 file changed, 33 insertions(+), 18 deletions(-) (limited to 'nuttx/arch/arm/src/stm32/stm32_spi.c') diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.c b/nuttx/arch/arm/src/stm32/stm32_spi.c index 06a994524..40b1a29a0 100644 --- a/nuttx/arch/arm/src/stm32/stm32_spi.c +++ b/nuttx/arch/arm/src/stm32/stm32_spi.c @@ -1368,15 +1368,20 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv = &g_spi1dev; - /* Configure SPI1 pins: SCK, MISO, and MOSI */ + /* Only configure if the port is not already configured */ - stm32_configgpio(GPIO_SPI1_SCK); - stm32_configgpio(GPIO_SPI1_MISO); - stm32_configgpio(GPIO_SPI1_MOSI); + if ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0) + { + /* Configure SPI1 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); - /* Set up default configuration: Master, 8-bit, etc. */ + /* Set up default configuration: Master, 8-bit, etc. */ - spi_portinitialize(priv); + spi_portinitialize(priv); + } } else #endif @@ -1387,15 +1392,20 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv = &g_spi2dev; - /* Configure SPI2 pins: SCK, MISO, and MOSI */ + /* Only configure if the port is not already configured */ + + if ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0) + { + /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32_configgpio(GPIO_SPI2_SCK); - stm32_configgpio(GPIO_SPI2_MISO); - stm32_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); - /* Set up default configuration: Master, 8-bit, etc. */ + /* Set up default configuration: Master, 8-bit, etc. */ - spi_portinitialize(priv); + spi_portinitialize(priv); + } } else #endif @@ -1406,15 +1416,20 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv = &g_spi3dev; - /* Configure SPI3 pins: SCK, MISO, and MOSI */ + /* Only configure if the port is not already configured */ + + if ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0) + { + /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32_configgpio(GPIO_SPI3_SCK); - stm32_configgpio(GPIO_SPI3_MISO); - stm32_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); - /* Set up default configuration: Master, 8-bit, etc. */ + /* Set up default configuration: Master, 8-bit, etc. */ - spi_portinitialize(priv); + spi_portinitialize(priv); + } } #endif -- cgit v1.2.3