From 31e52c3a07a07a880d1c327ab25b99dca57e8dba Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 5 Apr 2009 13:08:33 +0000 Subject: Add timer and aitc headers git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1682 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/imx/imx_aitc.h | 111 +++++++++++++++++++++++++++++++++ nuttx/arch/arm/src/imx/imx_memorymap.h | 91 +++++++++++++++------------ nuttx/arch/arm/src/imx/imx_timer.h | 99 +++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+), 40 deletions(-) create mode 100644 nuttx/arch/arm/src/imx/imx_aitc.h create mode 100644 nuttx/arch/arm/src/imx/imx_timer.h (limited to 'nuttx/arch/arm/src') diff --git a/nuttx/arch/arm/src/imx/imx_aitc.h b/nuttx/arch/arm/src/imx/imx_aitc.h new file mode 100644 index 000000000..b0822d97b --- /dev/null +++ b/nuttx/arch/arm/src/imx/imx_aitc.h @@ -0,0 +1,111 @@ +/************************************************************************************ + * arch/arm/src/imx/imx_aitc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_AITC_H +#define __ARCH_ARM_IMX_AITC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* AITC Register Offsets ************************************************************/ + +#define AITC_INTCNTL_OFFSET 0x0000 /* Interrupt Control Register */ +#define AITC_NIMASK_OFFSET 0x0004 /* Normal Interrupt Mask Register */ +#define AITC_INTENNUM_OFFSET 0x0008 /* Interrupt Enable Number Register */ +#define AITC_INTDISNUM_OFFSET 0x000c /* Interrupt Disable Number Register */ +#define AITC_INTENABLEH_OFFSET 0x0010 /* Interrupt Enable Register High */ +#define AITC_INTENABLEL_OFFSET 0x0014 /* Interrupt Enable Register Low */ +#define AITC_INTTYPEH_OFFSET 0x0018 +#define AITC_INTTYPEL_OFFSET 0x001c +#define AITC_NIPRIORITY7_OFFSET 0x0020 +#define AITC_NIPRIORITY6_OFFSET 0x0024 +#define AITC_NIPRIORITY5_OFFSET 0x0028 +#define AITC_NIPRIORITY4_OFFSET 0x002c +#define AITC_NIPRIORITY3_OFFSET 0x0030 +#define AITC_NIPRIORITY2_OFFSET 0x0034 +#define AITC_NIPRIORITY1_OFFSET 0x0038 +#define AITC_NIPRIORITY0_OFFSET 0x003c +#define AITC_NIVECSR_OFFSET 0x0040 +#define AITC_FIVECSR_OFFSET 0x0044 +#define AITC_INTSRCH_OFFSET 0x0048 +#define AITC_INTSRCL_OFFSET 0x004c +#define AITC_INTFRCH_OFFSET 0x0050 +#define AITC_INTFRCL_OFFSET 0x0054 +#define AITC_NIPNDH_OFFSET 0x0058 +#define AITC_NIPNDL_OFFSET 0x005c +#define AITC_FIPNDH_OFFSET 0x0060 +#define AITC_FIPNDL_OFFSET 0x0064 + +/* AITC Register Addresses **********************************************************/ +) +#define IMX_AITC_INTCNTL (IMX_AITC_VBASE + AITC_INTCNTL_OFFSET) +#define IMX_AITC_NIMASK (IMX_AITC_VBASE + AITC_NIMASK_OFFSET) +#define IMX_AITC_INTENNUM (IMX_AITC_VBASE + AITC_INTENNUM_OFFSET) +#define IMX_AITC_INTDISNUM (IMX_AITC_VBASE + AITC_INTDISNUM_OFFSET) +#define IMX_AITC_INTENABLEH (IMX_AITC_VBASE + AITC_INTENABLEH_OFFSET) +#define IMX_AITC_INTENABLEL (IMX_AITC_VBASE + AITC_INTENABLEL_OFFSET) +#define IMX_AITC_INTTYPEH (IMX_AITC_VBASE + AITC_INTTYPEH_OFFSET) +#define IMX_AITC_INTTYPEL (IMX_AITC_VBASE + AITC_INTTYPEL_OFFSET) +#define IMX_AITC_NIPRIORITY7 (IMX_AITC_VBASE + AITC_NIPRIORITY7_OFFSET) +#define IMX_AITC_NIPRIORITY6 (IMX_AITC_VBASE + AITC_NIPRIORITY6_OFFSET) +#define IMX_AITC_NIPRIORITY5 (IMX_AITC_VBASE + AITC_NIPRIORITY5_OFFSET) +#define IMX_AITC_NIPRIORITY4 (IMX_AITC_VBASE + AITC_NIPRIORITY4_OFFSET) +#define IMX_AITC_NIPRIORITY3 (IMX_AITC_VBASE + AITC_NIPRIORITY3_OFFSET) +#define IMX_AITC_NIPRIORITY2 (IMX_AITC_VBASE + AITC_NIPRIORITY2_OFFSET) +#define IMX_AITC_NIPRIORITY1 (IMX_AITC_VBASE + AITC_NIPRIORITY1_OFFSET) +#define IMX_AITC_NIPRIORITY0 (IMX_AITC_VBASE + AITC_NIPRIORITY0_OFFSET) +#define IMX_AITC_NIVECSR (IMX_AITC_VBASE + AITC_NIVECSR_OFFSET) +#define IMX_AITC_FIVECSR (IMX_AITC_VBASE + AITC_FIVECSR_OFFSET) +#define IMX_AITC_INTSRCH (IMX_AITC_VBASE + AITC_INTSRCH_OFFSET) +#define IMX_AITC_INTSRCL (IMX_AITC_VBASE + AITC_INTSRCL_OFFSET) +#define IMX_AITC_INTFRCH (IMX_AITC_VBASE + AITC_INTFRCH_OFFSET) +#define IMX_AITC_INTFRCL (IMX_AITC_VBASE + AITC_INTFRCL_OFFSET) +#define IMX_AITC_NIPNDH (IMX_AITC_VBASE + AITC_NIPNDH_OFFSET) +#define IMX_AITC_NIPNDL (IMX_AITC_VBASE + AITC_NIPNDL_OFFSET) +#define IMX_AITC_FIPNDH (IMX_AITC_VBASE + AITC_FIPNDH_OFFSET) +#define IMX_AITC_FIPNDL (IMX_AITC_VBASE + AITC_FIPNDL_OFFSET) + +/* AITC Register Bit Definitions ****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_AITC_H */ diff --git a/nuttx/arch/arm/src/imx/imx_memorymap.h b/nuttx/arch/arm/src/imx/imx_memorymap.h index 403906eda..44cfc7092 100644 --- a/nuttx/arch/arm/src/imx/imx_memorymap.h +++ b/nuttx/arch/arm/src/imx/imx_memorymap.h @@ -49,64 +49,75 @@ /* -0x000fffff Double Map Image 1Mb */ /* -0x001fffff Bootstrap ROM 1Mb */ #define IMX_PERIPHERALS_PSECTION 0x00200000 /* -0x002fffff Peripherals 1Mb */ -#define IMX_SDRAM0_PSECTION 0x08000000 /* -0x08ffff00 SDRAM0 16Mb */ -#define IMX_SDRAM1_PSECTION 0x0c000000 /* -0x0cffff00 SDRAM1 16Mb */ -#define IMX_FLASH_PSECTION 0x10000000 /* -0x12000000 FLASH 32Mb */ +#define IMX_SDRAM0_PSECTION 0x08000000 /* -0x0bffffff SDRAM0 (CSD0) 64Mb */ +#define IMX_SDRAM1_PSECTION 0x0c000000 /* -0x0fffffff SDRAM1 (CSD1) 64Mb */ +#define IMX_FLASH_PSECTION 0x10000000 /* -0x11ffffff FLASH (CS0) 32Mb */ +#define IMX_CS1_PSECTION 0x12000000 /* -0x12ffffff CS1 32Mb */ +#define IMX_CS2_PSECTION 0x13000000 /* -0x13ffffff CS2 32Mb */ +#define IMX_CS3_PSECTION 0x14000000 /* -0x14ffffff CS3 32Mb */ +#define IMX_CS4_PSECTION 0x15000000 /* -0x15ffffff CS4 32Mb */ +#define IMX_CS5_PSECTION 0x16000000 /* -0x16ffffff CS5 32Mb */ /* Sizes of Address Sections ********************************************************/ +/* Mapped sections */ #define IMX_PERIPHERALS_NSECTIONS 1 /* 1Mb 1 section */ -#define IMX_SDRAM0_NSECTIONS 16 /* 16Mb 16 sections */ -#define IMX_SDRAM1_NSECTIONS 16 /* 16Mb 16 sections */ -#define IMX_FLASH_NSECTIONS 32 /* 32Mb 32 sections */ +#define IMX_SDRAM0_NSECTIONS 16 /* 16Mb Based on CONFIG_DRAM_SIZE */ +#define IMX_SDRAM1_NSECTIONS 0 /* 64Mb (Not mapped) */ +#define IMX_FLASH_NSECTIONS 32 /* 64Mb Based on CONFIG_FLASH_SIZE */ +#define IMX_CS1_NSECTIONS 0 /* 32Mb (Not mapped) */ +#define IMX_CS2_NSECTIONS 0 /* 32Mb (Not mapped) */ +#define IMX_CS3_NSECTIONS 0 /* 32Mb (Not mapped) */ +#define IMX_CS4_NSECTIONS 0 /* 32Mb (Not mapped) */ +#define IMX_CS5_NSECTIONS 0 /* 32Mb (Not mapped) */ /* Virtual Memory Map ***************************************************************/ -#define IMX_SDRAM_VSECTION 0x00000000 /* -0x01ffff00 32Mb */ -#define IMX_FLASH_VSECTION 0x80000000 /* -0x81ffffff 32Mb */ +#define IMX_SDRAM_VSECTION 0x00000000 /* -(+CONFIG_DRAM_SIZE) */ +#define IMX_FLASH_VSECTION 0x80000000 /* -(+CONFIG_FLASH_SIZE) */ #define IMX_PERIPHERALS_VSECTION 0xe0000000 /* -0xe00fffff 1Mb */ /* Peripheral Register Offsets ******************************************************/ -#define IMX_AIPI1_OFFSET 0x00000000 /* -0x00000fff AIPI1 4Kb */ -#define IMX_WDOG_OFFSET 0x00001000 /* -0x00001fff WatchDog 4Kb */ -#define IMX_TIMER1_OFFSET 0x00002000 /* -0x00002fff Timer1 4Kb */ -#define IMX_TIMER2_OFFSET 0x00003000 /* -0x00003fff Timer2 4Kb */ -#define IMX_RTC_OFFSET 0x00004000 /* -0x00004fff RTC 4Kb */ -#define IMX_LCDC_OFFSET 0x00005000 /* -0x00005fff LCD 4Kb */ +#define IMX_AIPI1_OFFSET 0x00000000 /* -0x00000fff AIPI1 4Kb */ +#define IMX_WDOG_OFFSET 0x00001000 /* -0x00001fff WatchDog 4Kb */ +#define IMX_TIMER1_OFFSET 0x00002000 /* -0x00002fff Timer1 4Kb */ +#define IMX_TIMER2_OFFSET 0x00003000 /* -0x00003fff Timer2 4Kb */ +#define IMX_RTC_OFFSET 0x00004000 /* -0x00004fff RTC 4Kb */ +#define IMX_LCDC_OFFSET 0x00005000 /* -0x00005fff LCD 4Kb */ #define IMX_LCDC_COLORMAP 0x00005800 -#define IMX_UART1_OFFSET 0x00006000 /* -0x00006fff UART1 4Kb */ -#define IMX_UART2_OFFSET 0x00007000 /* -0x00007fff UART2 4Kb */ -#define IMX_PWM1_OFFSET 0x00008000 /* -0x00008fff PWM 4Kb */ -#define IMX_DMA_OFFSET 0x00009000 /* -0x00009fff DMA 4Kb */ -#define IMX_UART3_OFFSET 0x0000a000 /* -0x0000afff UART3 4Kb */ - /* -0x0000ffff Reserved 20Kb */ -#define IMX_AIPI2_OFFSET 0x00010000 /* -0x00010fff AIPI2 4Kb */ -#define IMX_SIM_OFFSET 0x00011000 /* -0x00011fff SIM 4Kb */ -#define IMX_USBD_OFFSET 0x00012000 /* -0x00012fff USBD 4Kb */ -#define IMX_CSPI1_OFFSET 0x00013000 /* -0x00013fff CSPI1 4Kb */ -#define IMX_MMC_OFFSET 0x00014000 /* -0x00014fff MMC 4Kb */ -#define IMX_ASP_OFFSET 0x00015000 /* -0x00015fff ASP 4Kb */ -#define IMX_BTA_OFFSET 0x00016000 /* -0x00016fff BTA 4Kb */ -#define IMX_I2C_OFFSET 0x00017000 /* -0x00017fff I2C 4Kb */ -#define IMX_SSI_OFFSET 0x00018000 /* -0x00018fff SSI 4Kb */ -#define IMX_CSPI2_OFFSET 0x00019000 /* -0x00019fff CSPI2 4Kb */ -#define IMX_MSHC_OFFSET 0x0001a000 /* -0x0001afff Memory Stick 4Kb */ -#define IMX_CRM_OFFSET 0x0001b000 /* -0x0001bfff CRM 4Kb */ +#define IMX_UART1_OFFSET 0x00006000 /* -0x00006fff UART1 4Kb */ +#define IMX_UART2_OFFSET 0x00007000 /* -0x00007fff UART2 4Kb */ +#define IMX_PWM1_OFFSET 0x00008000 /* -0x00008fff PWM 4Kb */ +#define IMX_DMA_OFFSET 0x00009000 /* -0x00009fff DMA 4Kb */ +#define IMX_UART3_OFFSET 0x0000a000 /* -0x0000afff UART3 4Kb */ + /* -0x0000ffff Reserved 20Kb */ +#define IMX_AIPI2_OFFSET 0x00010000 /* -0x00010fff AIPI2 4Kb */ +#define IMX_SIM_OFFSET 0x00011000 /* -0x00011fff SIM 4Kb */ +#define IMX_USBD_OFFSET 0x00012000 /* -0x00012fff USBD 4Kb */ +#define IMX_CSPI1_OFFSET 0x00013000 /* -0x00013fff CSPI1 4Kb */ +#define IMX_MMC_OFFSET 0x00014000 /* -0x00014fff MMC 4Kb */ +#define IMX_ASP_OFFSET 0x00015000 /* -0x00015fff ASP 4Kb */ +#define IMX_BTA_OFFSET 0x00016000 /* -0x00016fff BTA 4Kb */ +#define IMX_I2C_OFFSET 0x00017000 /* -0x00017fff I2C 4Kb */ +#define IMX_SSI_OFFSET 0x00018000 /* -0x00018fff SSI 4Kb */ +#define IMX_CSPI2_OFFSET 0x00019000 /* -0x00019fff CSPI2 4Kb */ +#define IMX_MSHC_OFFSET 0x0001a000 /* -0x0001afff Memory Stick 4Kb */ +#define IMX_CRM_OFFSET 0x0001b000 /* -0x0001bfff CRM 4Kb */ #define IMX_PLL_OFFSET 0x0001b000 #define IMX_SC_OFFSET 0x0001b800 -#define IMX_GPIO_OFFSET 0x0001c000 /* -0x0001cfff GPIO 4Kb */ +#define IMX_GPIO_OFFSET 0x0001c000 /* -0x0001cfff GPIO 4Kb */ #define IMX_PTA_OFFSET 0x0001c000 #define IMX_PTB_OFFSET 0x0001c100 #define IMX_PTC_OFFSET 0x0001c200 #define IMX_PTD_OFFSET 0x0001c300 - /* -0x0001ffff Reserved 12Kb */ -#define IMX_EIM_OFFSET 0x00020000 /* -0x00020fff WEIM 4Kb */ -#define IMX_SDRAMC_OFFSET 0x00021000 /* -0x00021fff SDRAMC 4Kb */ -#define IMX_DSPA_OFFSET 0x00022000 /* -0x00022fff DSPA 4Kb */ -#define IMX_AITC_OFFSET 0x00023000 /* -0x00023fff AITC 4Kb */ -#define IMX_CSI_OFFSET 0x00024000 /* -0x00024fff CSI 4Kb */ - /* -0x000fffff Reserved 876Kb */ + /* -0x0001ffff Reserved 12Kb */ +#define IMX_EIM_OFFSET 0x00020000 /* -0x00020fff WEIM 4Kb */ +#define IMX_SDRAMC_OFFSET 0x00021000 /* -0x00021fff SDRAMC 4Kb */ +#define IMX_DSPA_OFFSET 0x00022000 /* -0x00022fff DSPA 4Kb */ +#define IMX_AITC_OFFSET 0x00023000 /* -0x00023fff AITC 4Kb */ +#define IMX_CSI_OFFSET 0x00024000 /* -0x00024fff CSI 4Kb */ + /* -0x000fffff Reserved 876Kb */ /* Peripheral Register Offsets ******************************************************/ diff --git a/nuttx/arch/arm/src/imx/imx_timer.h b/nuttx/arch/arm/src/imx/imx_timer.h new file mode 100644 index 000000000..eca7e123e --- /dev/null +++ b/nuttx/arch/arm/src/imx/imx_timer.h @@ -0,0 +1,99 @@ +/************************************************************************************ + * arch/arm/src/imx/imx_timer.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_TIMER_H +#define __ARCH_ARM_IMX_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Timer Register Offsets ***********************************************************/ + +#define TIMER_TCTL_OFFSET 0x0000 /* Timer control register */ +#define TIMER_TPRER_OFFSET 0x0004 /* Timer prescaler register */ +#define TIMER_TCMP_OFFSET 0x0008 /* Timer compare register */ +#define TIMER_TCR_OFFSET 0x000c /* Timer capture register */ +#define TIMER_TCN_OFFSET 0x0010 /* Timer counter regiser */ +#define TIMER_TSTAT_OFFSET 0x0014 /* Timer status register */ + +/* Timer Register Addresses *********************************************************/ + +#define IMX_TIMER1_TCTL (IMX_TIMER1_VBASE + TIMER_TCTL_OFFSET) +#define IMX_TIMER1_TPRER (IMX_TIMER1_VBASE + TIMER_TPRER_OFFSET) +#define IMX_TIMER1_TCMP (IMX_TIMER1_VBASE + TIMER_TCMP_OFFSET) +#define IMX_TIMER1_TCR (IMX_TIMER1_VBASE + TIMER_TCR_OFFSET) +#define IMX_TIMER1_TCN (IMX_TIMER1_VBASE + TIMER_TCN_OFFSET) +#define IMX_TIMER1_TSTAT (IMX_TIMER1_VBASE + TIMER_TSTAT_OFFSET) + +#define IMX_TIMER2_TCTL (IMX_TIMER2_VBASE + TIMER_TCTL_OFFSET) +#define IMX_TIMER2_TPRER (IMX_TIMER2_VBASE + TIMER_TPRER_OFFSET) +#define IMX_TIMER2_TCMP (IMX_TIMER2_VBASE + TIMER_TCMP_OFFSET) +#define IMX_TIMER2_TCR (IMX_TIMER2_VBASE + TIMER_TCR_OFFSET) +#define IMX_TIMER2_TCN (IMX_TIMER2_VBASE + TIMER_TCN_OFFSET) +#define IMX_TIMER2_TSTAT (IMX_TIMER2_VBASE + TIMER_TSTAT_OFFSET) + +/* Timer Register Bit Definitions ***************************************************/ + +/* Timer Control Register */ + +#define TIMER_TCTL_TEN (1 << 0) /* Bit 0: Timer Enable */ +#define TIMER_TCTL_CLKSOURCE_SHIFT 1 /* Bit 1-4: Clock Source */ +#define TIMER_TCTL_CLKSOURCE_MASK (0x07 << TIMER_TCTL_CLKSOURCE_SHIFT) +#define TIMER_TCTL_IRQEN (1 << 5) /* Bit 5: Interrupt Request Enable */ +#define TIMER_TCTL_OM (1 << 6) /* Bit 6: Output Mode */ +#define TIMER_TCTL_CAP (1 << 7) /* Bit 7: Capture Edge */ +#define TIMER_TCTL_FRR (1 << 8) /* Bit 8: Free-Run/Reset */ +#define TIMER_TCTL_SWR (1 << 15) /* Bit 15: Software Reset */ + +/* Timer Prescaler Register */ + +#define TIMER_TPRER_PRESCALER_SHIFT 0 /* Bits 0-7: Prescaler */ +#define TIMER_TPRER_PRESCALER_MASK (0xff << TIMER_TPRER_PRESCALER_SHIFT) + +/* Timer Status Register */ + +#define TIMER_TSTAT_COMP (1 << 0) /* Bit 0: Compare Event */ +#define TIMER_TSTAT_CAPT (1 << 1) /* Bit 1: Capture Event */ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_TIMER_H */ -- cgit v1.2.3