From 7f27c5ae6a4c1f9519e6b0ca7a4db7a094a6987b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 8 Jun 2013 09:21:20 -0600 Subject: SM4L: USB clock configuration and WDT register definition file --- nuttx/arch/arm/src/sam34/Kconfig | 35 +++++-- nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h | 96 +++++++++++++++++++ nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h | 6 +- nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h | 2 +- nuttx/arch/arm/src/sam34/chip/sam4l_scif.h | 9 +- nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h | 137 +++++++++++++++++++++++++++ nuttx/arch/arm/src/sam34/chip/sam_pinmap.h | 2 + nuttx/arch/arm/src/sam34/chip/sam_pio.h | 71 -------------- nuttx/arch/arm/src/sam34/chip/sam_wdt.h | 96 ------------------- nuttx/arch/arm/src/sam34/sam3u_clockconfig.c | 2 +- nuttx/arch/arm/src/sam34/sam3u_gpio.c | 2 +- nuttx/arch/arm/src/sam34/sam4l_clockconfig.c | 38 +++++--- nuttx/arch/arm/src/sam34/sam4l_periphclks.c | 108 ++++++++++++++++++++- nuttx/arch/arm/src/sam34/sam4l_periphclks.h | 50 +++++++--- nuttx/arch/arm/src/sam34/sam_gpioirq.c | 2 +- nuttx/arch/arm/src/sam34/sam_start.c | 10 +- 16 files changed, 452 insertions(+), 214 deletions(-) create mode 100644 nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h delete mode 100644 nuttx/arch/arm/src/sam34/chip/sam_pio.h delete mode 100644 nuttx/arch/arm/src/sam34/chip/sam_wdt.h (limited to 'nuttx/arch/arm/src') diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index d2da85624..26e8bb017 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -285,7 +285,7 @@ config SAM34_CATB depends on ARCH_CHIP_SAM4L config SAM34_LCDCA - bool " LCD Controller A" + bool "LCD Controller A" default n depends on ARCH_CHIP_SAM4L @@ -349,7 +349,6 @@ config SAM34_AST config SAM34_WDT bool "Watchdog Timer" default n - depends on ARCH_CHIP_SAM4L config SAM34_EIC bool "External Interrupt Controller" @@ -363,7 +362,7 @@ config SAM34_HSMCI endmenu -menu "AT91SAM3/4 USART Configuration" +comment "AT91SAM3/4 USART Configuration" config USART0_ISUART bool "USART0 is a UART" @@ -389,9 +388,7 @@ config USART3_ISUART depends on SAM34_USART3 select ARCH_HAVE_USART2 -endmenu - -menu "AT91SAM3/4 GPIO Interrupt Configuration" +comment "AT91SAM3/4 GPIO Interrupt Configuration" config GPIOA_IRQ bool "GPIOA interrupts" @@ -405,4 +402,28 @@ config GPIOC_IRQ bool "GPIOC interrupts" default n -endmenu +if SAM34_WDT +comment "AT91SAM3/4 Watchdog Configuration"| + +config WDT_ENABLED_ON_RESET + bool "Enabled on reset" + default n + ---help--- + The WDT can be enabled at reset. This is controlled by the WDTAUTO + fuse. The WDT will be set in basic mode, RCSYS is set as source for + CLK_CNT, and PSEL will be set to a value giving Tpsel above 100 ms + (SAM4L) + + This setting informs that start-up logic that the watchdog is + enabled. + +config WDT_DISABLE_ON_RESET + bool "Disable on reset" + default n + depends on WDT_ENABLED_ON_RESET + ---help--- + If the WDT can be enabled at reset then this setting may be used to + configure and disable the watchdog timer very early in the boot + sequence. + +endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h new file mode 100644 index 000000000..b4d28c71a --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h @@ -0,0 +1,96 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam3u_wdt.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* WDT register offsets ****************************************************************/ + +#define SAM_WDT_CR_OFFSET 0x00 /* Control Register */ +#define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */ +#define SAM_WDT_SR_OFFSET 0x08 /* Status Register */ + +/* WDT register adresses ***************************************************************/ + +#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET) +#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET) +#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) + +/* WDT register bit definitions ********************************************************/ + +#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ +#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) + +#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ +#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) +#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ +#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ +#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) +#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ + +#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ +#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h b/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h index 16a0bf028..05ba546c9 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h @@ -116,9 +116,9 @@ #define BPM_PMCON_SLEEP_SHIFT (12) /* Bits 12-13: SLEEP mode Configuration */ #define BPM_PMCON_SLEEP_MASK (3 << BPM_PMCON_SLEEP_SHIFT) # define BPM_PMCON_SLEEP_SLEEP0 (0 << BPM_PMCON_SLEEP_SHIFT) /* CPU clock stopped */ -# define BPM_PMCON_SLEEP_SLEEP0 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */ -# define BPM_PMCON_SLEEP_SLEEP0 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */ -# define BPM_PMCON_SLEEP_SLEEP0 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */ +# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */ +# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */ +# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */ #define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */ #define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h index c4babee65..68f4b2074 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_pinmap.h @@ -48,7 +48,7 @@ /************************************************************************************ * Definitions ************************************************************************************/ -/* Alternate Pin Functions. +/* Alternate Pin Functions. * * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. * Drivers, however, will use the pin selection without the numeric suffix. diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h b/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h index b1e23a2b7..d6f6661e6 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_scif.h @@ -288,7 +288,7 @@ # define SCIF_DFLL0STEP_FSTEP(n) ((n) << SCIF_DFLL0STEP_FSTEP_SHIFT) #define SCIF_DFLL0STEP_CSTEP_SHIFT (16) /* Bits 16-20: Coarse Maximum Step */ #define SCIF_DFLL0STEP_CSTEP_MASK (31 << SCIF_DFLL0STEP_CSTEP_SHIFT) -# define SCIF_DFLL0STEP_CSTEP(4) ((v) << SCIF_DFLL0STEP_CSTEP_SHIFT) +# define SCIF_DFLL0STEP_CSTEP(n) ((n) << SCIF_DFLL0STEP_CSTEP_SHIFT) /* DFLL0 Spread Spectrum Generator Control Register */ @@ -391,6 +391,13 @@ # define SCIF_GCCTRL_OSCSEL_PBCCLK (11 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus C clock */ # define SCIF_GCCTRL_OSCSEL_PBDCLK (12 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus D clock */ # define SCIF_GCCTRL_OSCSEL_RC32K (13 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 32kHz RCOSC */ +# define SCIF_GCCTRL_OSCSEL_1K (15 << SCIF_GCCTRL_OSCSEL_SHIFT) /* 1 kHz output from OSC32K */ +# define SCIF_GCCTRL_OSCSEL_PLL0 (16 << SCIF_GCCTRL_OSCSEL_SHIFT) /* PLL0 */ +# define SCIF_GCCTRL_OSCSEL_HRPCLK (17 << SCIF_GCCTRL_OSCSEL_SHIFT) /* High resolution prescaler */ +# define SCIF_GCCTRL_OSCSEL_FPCLK (18 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Fractional prescaler */ +# define SCIF_GCCTRL_OSCSEL_GCLKIN0 (19 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN0 */ +# define SCIF_GCCTRL_OSCSEL_GCLKIN1 (20 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN1 */ +# define SCIF_GCCTRL_OSCSEL_GCLK11 (21 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLK11 */ #define SCIF_GCCTRL_DIV_SHIFT (16) /* Bits 16-31: Division Factor */ #define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT) # define SCIF_GCCTRL_DIV(n) ((n) << SCIF_GCCTRL_DIV_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h new file mode 100644 index 000000000..638370614 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_wdt.h @@ -0,0 +1,137 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam4l_wdt.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* WDT register offsets ****************************************************************/ + +#define SAM_WDT_CTRL_OFFSET 0x0000 /* Control Register */ +#define SAM_WDT_CLR_OFFSET 0x0004 /* Clear Register */ +#define SAM_WDT_SR_OFFSET 0x0008 /* Status Register */ +#define SAM_WDT_IER_OFFSET 0x000c /* Interrupt Enable Register */ +#define SAM_WDT_IDR_OFFSET 0x0010 /* Interrupt Disable Register */ +#define SAM_WDT_IMR_OFFSET 0x0014 /* Interrupt Mask Register */ +#define SAM_WDT_ISR_OFFSET 0x0018 /* Interrupt Status Register */ +#define SAM_WDT_ICR_OFFSET 0x001c /* Interrupt Clear Register */ +#define SAM_WDT_VERSION_OFFSET 0x03fc /* Version Register */ + +/* WDT register adresses ***************************************************************/ + +#define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET) +#define SAM_WDT_CLR (SAM_WDT_BASE+SAM_WDT_CLR_OFFSET) +#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) +#define SAM_WDT_IER (SAM_WDT_BASE+SAM_WDT_IER_OFFSET) +#define SAM_WDT_IDR (SAM_WDT_BASE+SAM_WDT_IDR_OFFSET) +#define SAM_WDT_IMR (SAM_WDT_BASE+SAM_WDT_IMR_OFFSET) +#define SAM_WDT_ISR (SAM_WDT_BASE+SAM_WDT_ISR_OFFSET) +#define SAM_WDT_ICR (SAM_WDT_BASE+SAM_WDT_ICR_OFFSET) +#define SAM_WDT_VERSION (SAM_WDT_BASE+SAM_WDT_VERSION_OFFSET) + +/* WDT register bit definitions ********************************************************/ + +/* Control Register */ + +#define WDT_CTRL_EN (1 << 0) /* Bit 0: WDT Enable */ +#define WDT_CTRL_DAR (1 << 1) /* Bit 1: WDT Disable After Reset */ +#define WDT_CTRL_MODE (1 << 2) /* Bit 2: WDT Mode */ +#define WDT_CTRL_SFV (1 << 3) /* Bit 3: WDT Control Register Store Final Value */ +#define WDT_CTRL_IM (1 << 4) /* Bit 4: Interrupt Mode */ +#define WDT_CTRL_FCD (1 << 7) /* Bit 7: Flash Calibration Done */ +#define WDT_CTRL_PSEL_SHIFT (8) /* Bits 8-12: Time Out Prescale Select */ +#define WDT_CTRL_PSEL_MASK (31 << WDT_CTRL_PSEL_SHIFT) +#define WDT_CTRL_CEN (1 << 16) /* Bit 16: Clock Enable */ +#define WDT_CTRL_CSSEL (1 << 17) /* Bit 17: Clock Source Select */ +#define WDT_CTRL_TBAN_SHIFT (18) /* Bits 18-22: Time Ban Prescale Select */ +#define WDT_CTRL_TBAN_MASK (31 << WDT_CTRL_TBAN_SHIFT) +#define WDT_CTRL_KEY_SHIFT (24) /* Bits 24-31: Key */ +#define WDT_CTRL_KEY_MASK (0xff << WDT_CTRL_KEY_SHIFT) +# define WDT_CTRL_KEY_FIRST (0x55 << WDT_CTRL_KEY_SHIFT) +# define WDT_CTRL_KEY_SECOND (0xaa << WDT_CTRL_KEY_SHIFT) + +/* Clear Register */ + +#define WDT_CLR_WDTCLR (1 << 0) /* Bit 0: Watchdog Clear */ +#define WDT_CLR_KEY_SHIFT (24) /* Bits 24-31: Key */ +#define WDT_CLR_KEY_MASK (0xff << WDT_CLR_KEY_SHIFT) +# define WDT_CLR_KEY_FIRST (0x55 << WDT_CLR_KEY_SHIFT) +# define WDT_CLR_KEY_SECOND (0xaa << WDT_CLR_KEY_SHIFT) + +/* Status Register */ + +#define WDT_SR_WINDOW (1 << 0) /* Bit 0: Within Window */ +#define WDT_SR_CLEARED (1 << 1) /* Bit 1: WDT Counter Cleared */ + +/* Interrupt Enable Register */ +/* Interrupt Disable Register */ +/* Interrupt Mask Register */ +/* Interrupt Status Register */ +/* Interrupt Clear Register */ + +#define WDT_WINT (1 << 2) /* Bit 2: WINT */ + +/* Version Register */ + +#define WDT_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ +#define WDT_VERSION_MASK (0xfff << WDT_VERSION_VERSION_SHIFT) +#define WDT_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ +#define WDT_VARIANT_MASK (15 << WDT_VARIANT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h index 6adb547bf..0028cb6ba 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h @@ -45,6 +45,8 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_pinmap.h" #else # error Unrecognized SAM architecture #endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pio.h b/nuttx/arch/arm/src/sam34/chip/sam_pio.h deleted file mode 100644 index e2596475d..000000000 --- a/nuttx/arch/arm/src/sam34/chip/sam_pio.h +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************************** - * arch/arm/src/sam34/chip/sam_pio.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_SAM3U) -# include "chip/sam3u_vectors.h" -#elif defined(CONFIG_ARCH_CHIP_SAM4S) -# include "chip/sam4s_vectors.h" -#else -# error Unrecognized SAM architecture -#endif - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam_wdt.h deleted file mode 100644 index ffe0cb96d..000000000 --- a/nuttx/arch/arm/src/sam34/chip/sam_wdt.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************************** - * arch/arm/src/sam34/chip/sam_wdt.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "chip/sam_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* WDT register offsets ****************************************************************/ - -#define SAM_WDT_CR_OFFSET 0x00 /* Control Register */ -#define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */ -#define SAM_WDT_SR_OFFSET 0x08 /* Status Register */ - -/* WDT register adresses ***************************************************************/ - -#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET) -#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET) -#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) - -/* WDT register bit definitions ********************************************************/ - -#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ -#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ -#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) - -#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ -#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) -#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ -#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ -#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ -#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) -#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ - -#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ -#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H */ diff --git a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c index 374e4868a..4f8ff273d 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c @@ -51,7 +51,7 @@ #include "sam_clockconfig.h" #include "chip/sam_pmc.h" #include "chip/sam3u_eefc.h" -#include "chip/sam_wdt.h" +#include "chip/sam3u_wdt.h" #include "chip/sam3u_supc.h" #include "chip/sam_matrix.h" diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.c b/nuttx/arch/arm/src/sam34/sam3u_gpio.c index 271bb2f9b..499108169 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.c @@ -52,7 +52,7 @@ #include "chip.h" #include "sam_gpio.h" -#include "chip/sam_pio.h" +#include "chip/sam3u_pio.h" /**************************************************************************** * Definitions diff --git a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c index e32f985e1..0a3c4915b 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam4l_clockconfig.c @@ -41,6 +41,9 @@ #include +#include +#include + #include #include @@ -53,7 +56,7 @@ #include "chip/sam4l_bscif.h" #include "chip/sam4l_flashcalw.h" -#include "sam_periphclks.h" +#include "sam4l_periphclks.h" #include "sam_clockconfig.h" /**************************************************************************** @@ -284,6 +287,7 @@ #ifdef BOARD_PLL0_SOURCE_GCLK9 # define NEED_GLCK9 1 +#endif #ifdef NEED_GLCK9 # if defined(BOARD_GLCK9_SOURCE_RCSYS) @@ -410,8 +414,12 @@ # define SAM_PLL0_OPTIONS 0 # endif # endif +#endif -/* DPLL0 reference clock */ +/* DFLL0 */ + +#ifdef BOARD_SYSCLK_SOURCE_DFLL0 +/* DFLL0 reference clock */ # if defined(BOARD_DFLL0_SOURCE_RCSYS) # define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RCSYS @@ -529,7 +537,7 @@ static inline void sam_enableosc32(void) /* Wait for OSC32 to be ready */ - while (getreg32(SAM_BSCIF_PCLKSR) & BSCIF_INT_OSC32RDY) == 0); + while ((getreg32(SAM_BSCIF_PCLKSR) & BSCIF_INT_OSC32RDY) == 0); } #endif @@ -752,7 +760,7 @@ static inline void sam_enabledfll0(void) * and divider. */ - putreg(0, SAM_SCIF_GCCTRL0); + putreg32(0, SAM_SCIF_GCCTRL0); /* Set the generic clock 0 source */ @@ -776,11 +784,11 @@ static inline void sam_enabledfll0(void) /* Sync before reading a dfll conf register */ putreg32(SCIF_DFLL0SYNC_SYNC, SAM_SCIF_DFLL0SYNC); - while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0); + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0); /* Select Closed Loop Mode */ - conf = getreg(SAM_SCIF_DFLL0CONF); + conf = getreg32(SAM_SCIF_DFLL0CONF); conf &= ~SCIF_DFLL0CONF_RANGE_MASK; conf |= SCIF_DFLL0CONF_MODE; @@ -794,7 +802,7 @@ static inline void sam_enabledfll0(void) conf |= SCIF_DFLL0CONF_RANGE1; #else conf |= SCIF_DFLL0CONF_RANGE0; -#ednif +#endif /* Enable the reference generic clock 0 */ @@ -817,7 +825,7 @@ static inline void sam_enabledfll0(void) * too high, DFLL0 may fail to lock. */ - sam_dfll0_putreg32((SCIF_DFLL0STEP_CSTEP(4) | SCIF_DFLL0STEP_FSTEP(4), + sam_dfll0_putreg32(SCIF_DFLL0STEP_CSTEP(4) | SCIF_DFLL0STEP_FSTEP(4), SAM_SCIF_DFLL0STEP, SAM_SCIF_DFLL0STEP_OFFSET); @@ -1056,7 +1064,7 @@ static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwk { /* Set one wait state */ - waistate = true; + waitstate = true; } } } @@ -1073,7 +1081,7 @@ static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwk { /* Set one wait state */ - waistate = true; + waitstate = true; } } @@ -1117,7 +1125,7 @@ static inline void sam_mainclk(uint32_t mcsel) * ****************************************************************************/ -static __ramfunc__ void sam_instantiatepsm(Bpm *bpm, uint32_t regval) +static __ramfunc__ void sam_instantiatepsm(uint32_t regval) { /* Set the BMP PCOM register (containing the new power scaling mode) */ @@ -1144,7 +1152,7 @@ static inline void sam_setpsm(uint32_t psm) /* Then call the RAMFUNC sam_setpsm() to set the new power scaling mode */ - sam_instantiatepsm(bpm, regval); + sam_instantiatepsm(regval); } /**************************************************************************** @@ -1286,7 +1294,7 @@ void sam_clockconfig(void) sam_enableosc32(); #endif -#ifdef NEED_OSC32K +#ifdef NEED_RC80M /* Enable the 32KHz oscillator using the settings in board.h */ sam_enablerc80m(); @@ -1407,7 +1415,9 @@ void sam_clockconfig(void) sam_init_periphclks(); + /* Configure clocking to the USB controller */ + #ifdef CONFIG_USBDEV - void sam_usbclock(); + sam_usbc_enableclk(); #endif } diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c index ea11d2b0c..a346a233d 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c +++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c @@ -54,6 +54,21 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* USBC source clock selection */ + +#ifdef CONFIG_SAM34_USBC +# if defined(BOARD_USBC_SRC_OSC0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_OSC0 +# elif defined(BOARD_USBC_SRC_PLL0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_PLL0 +# elif defined(BOARD_USBC_SRC_DFLL) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_DFLL0 +# elif defined(BOARD_USBC_SRC_GCLKIN0) +# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_GCLKIN0 +# else +# error No USBC GCLK7 source clock defined +# endif +#endif /**************************************************************************** * Private Types @@ -115,7 +130,7 @@ static inline void sam_init_hsbmask(void) /* Select the non-optional peripherals */ uint32_t mask = (PM_HSBMASK_FLASHCALW | PM_HSBMASK_APBB | - PM_HSBMASK_APBC | PM_HSBMASK_APBD) + PM_HSBMASK_APBC | PM_HSBMASK_APBD); /* OR in the user selected peripherals */ @@ -191,19 +206,19 @@ static inline void sam_init_pbamask(void) #endif #ifdef CONFIG_SAM34_USART0 mask |= PM_PBAMASK_USART0; /* USART0 */ - divmask |= PBA_DIVMASK_CLK_USART; + divmask |= PM_PBADIVMASK_CLK_USART; #endif #ifdef CONFIG_SAM34_USART1 mask |= PM_PBAMASK_USART1; /* USART1 */ - divmask |= PBA_DIVMASK_CLK_USART; + divmask |= PM_PBADIVMASK_CLK_USART; #endif #ifdef CONFIG_SAM34_USART2 mask |= PM_PBAMASK_USART2; /* USART2 */ - divmask |= PBA_DIVMASK_CLK_USART; + divmask |= PM_PBADIVMASK_CLK_USART; #endif #ifdef CONFIG_SAM34_USART3 mask |= PM_PBAMASK_USART3; /* USART3 */ - divmask |= PBA_DIVMASK_CLK_USART; + divmask |= PM_PBADIVMASK_CLK_USART; #endif #ifdef CONFIG_SAM34_ADCIFE mask |= PM_PBAMASK_ADCIFE; /* ADCIFE */ @@ -579,3 +594,86 @@ void sam_pbb_disableperipheral(uint32_t bitset) irqrestore(flags); } + +/**************************************************************************** + * Name: sam_usbc_enableclk + * + * Description: + * Enable clocking for the USBC using settings from the board.h header files. + * + * "The USBC has two bus clocks connected: One High Speed Bus clock + * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks + * are generated by the Power Manager. Both clocks are enabled at reset + * and can be disabled by the Power Manager. It is recommended to disable + * the USBC before disabling the clocks, to avoid freezing the USBC in + * an undefined state. + * + * "To follow the usb data rate at 12Mbit/s in full-speed mode, the + * CLK_USBC_AHB clock should be at minimum 12MHz. + * + * "The 48MHz USB clock is generated by a dedicated generic clock from + * the SCIF module. Before using the USB, the user must ensure that the + * USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module." + * + ****************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_enableclk(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Enable USBC clocking (possibly along with the PBB peripheral bridge) */ + + flags = irqsave(); + sam_hsb_enableperipheral(PM_HSBMASK_USBC); + sam_pbb_enableperipheral(PM_PBBMASK_USBC); + + /* Reset generic clock 7 */ + + putreg32(0, SAM_SCIF_GCCTRL7); + + /* Set the generic clock source */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval &= ~SCIF_GCCTRL_OSCSEL_MASK; + regval |= SAM_USBC_GCLK_SOURCE; + putreg32(regval, SAM_SCIF_GCCTRL7); + + /* Set the generic clock divider */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK); + +#if BOARD_USBC_GCLK_DIV > 1 + regval |= SCIF_GCCTRL_DIVEN; + regval |= SCIF_GCCTRL_DIV(((divider + 1) / 2) - 1); +#endif + + putreg32(regval, SAM_SCIF_GCCTRL7); + + /* Enable the generic clock */ + + regval = getreg32(SAM_SCIF_GCCTRL7); + regval |= SCIF_GCCTRL_CEN; + putreg32(regval, SAM_SCIF_GCCTRL7); + irqrestore(flags); +} +#endif /* CONFIG_SAM34_USBC */ + +/**************************************************************************** + * Name: sam_usbc_disableclk + * + * Description: + * Disable clocking to the USBC. + * + ****************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_disableclk(void) +{ + putreg32(0, SAM_SCIF_GCCTRL7); + sam_pbb_enableperipheral(PM_PBBMASK_USBC); + sam_hsb_enableperipheral(PM_HSBMASK_USBC); +} +#endif /* CONFIG_SAM34_USBC */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h index 171e0dd8b..620942940 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h +++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h @@ -151,12 +151,6 @@ sam_pbb_enableperipheral(PM_PBBMASK_CRCCU); \ } while (0) -#define sam_usbc_enableclk() \ - do { \ - sam_hsb_enableperipheral(PM_HSBMASK_USBC); \ - sam_pbb_enableperipheral(PM_PBBMASK_USBC); \ - } while (0) - #define sam_pevc_enableclk() sam_pbb_enableperipheral(PM_PBBMASK_PEVC) #define sam_pm_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_PM) #define sam_chipid_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_CHIPID) @@ -218,12 +212,6 @@ sam_pbb_disableperipheral(PM_PBBMASK_CRCCU); \ } while (0) -#define sam_usbc_disableclk() \ - do { \ - sam_hsb_disableperipheral(PM_HSBMASK_USBC); \ - sam_pbb_disableperipheral(PM_PBBMASK_USBC); \ - } while (0) - #define sam_pevc_disableclk() sam_pbb_disableperipheral(PM_PBBMASK_PEVC) #define sam_pm_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_PM) #define sam_chipid_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_CHIPID) @@ -336,6 +324,44 @@ void sam_pbb_enableperipheral(uint32_t bitset); void sam_pbb_disableperipheral(uint32_t bitset); +/************************************************************************************ + * Name: sam_usbc_enableclk + * + * Description: + * Enable clocking for the USBC using settings from the board.h header files. + * + * "The USBC has two bus clocks connected: One High Speed Bus clock + * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks + * are generated by the Power Manager. Both clocks are enabled at reset + * and can be disabled by the Power Manager. It is recommended to disable + * the USBC before disabling the clocks, to avoid freezing the USBC in + * an undefined state. + * + * "To follow the usb data rate at 12Mbit/s in full-speed mode, the + * CLK_USBC_AHB clock should be at minimum 12MHz. + * + * "The 48MHz USB clock is generated by a dedicated generic clock from + * the SCIF module. Before using the USB, the user must ensure that the + * USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module." + * + ************************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_enableclk(void); +#endif + +/************************************************************************************ + * Name: sam_usbc_disableclk + * + * Description: + * Disable clocking to the USBC. + * + ************************************************************************************/ + +#ifdef CONFIG_SAM34_USBC +void sam_usbc_disableclk(void); +#endif + #undef EXTERN #if defined(__cplusplus) } diff --git a/nuttx/arch/arm/src/sam34/sam_gpioirq.c b/nuttx/arch/arm/src/sam34/sam_gpioirq.c index e5f0364cd..c9fcc0ca8 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpioirq.c +++ b/nuttx/arch/arm/src/sam34/sam_gpioirq.c @@ -54,7 +54,7 @@ #include "up_internal.h" #include "sam_gpio.h" -#include "chip/sam_pio.h" +#include "chip/sam3u_pio.h" #include "chip/sam_pmc.h" #ifdef CONFIG_GPIO_IRQ diff --git a/nuttx/arch/arm/src/sam34/sam_start.c b/nuttx/arch/arm/src/sam34/sam_start.c index e48da5645..6324617f3 100644 --- a/nuttx/arch/arm/src/sam34/sam_start.c +++ b/nuttx/arch/arm/src/sam34/sam_start.c @@ -54,8 +54,11 @@ #include "sam_userspace.h" /**************************************************************************** - * Private Definitions + * Pre-processor Definitions ****************************************************************************/ +#if defined(CONFIG_WDT_ENABLED_ON_RESET) && defined(CONFIG_WDT_DISABLE_ON_RESET) +# define NEED_WDT_DISABLE +#endif /**************************************************************************** * Private Data @@ -120,6 +123,11 @@ void __start(void) *dest++ = *src++; } +#ifdef NEED_WDT_DISABLE + /* Disable the watchdog timer */ +# warning Missing logic +#endif + /* Copy any necessary code sections from FLASH to RAM. The correct * destination in SRAM is geive by _sramfuncs and _eramfuncs. The * temporary location is in flash after the data initalization code -- cgit v1.2.3