From ceef9e3bece69f86e585b3bf00e5009551350e2b Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 6 Feb 2013 22:30:57 +0000 Subject: Beginnings of support for the STM32F3Discovery board git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5616 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/stm32/Kconfig | 80 ++++++++++- nuttx/arch/arm/src/stm32/chip.h | 10 ++ nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h | 2 + .../arm/src/stm32/chip/stm32f30xxx_memorymap.h | 155 +++++++++++++++++++++ .../arch/arm/src/stm32/chip/stm32f30xxx_vectors.h | 149 ++++++++++++++++++++ nuttx/arch/arm/src/stm32/stm32_vectors.S | 4 + 6 files changed, 396 insertions(+), 4 deletions(-) create mode 100644 nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h create mode 100644 nuttx/arch/arm/src/stm32/chip/stm32f30xxx_vectors.h (limited to 'nuttx/arch/arm/src') diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 41724be2d..2e29af14f 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -128,6 +128,66 @@ config ARCH_CHIP_STM32F207IG select ARCH_CORTEXM3 select STM32_STM32F20XX +config ARCH_CHIP_STM32F302CB + bool "STM32F302CB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302CC + bool "STM32F302CC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302RB + bool "STM32F302RB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302RC + bool "STM32F302RC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302VB + bool "STM32F302VB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302VC + bool "STM32F302VC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303CB + bool "STM32F303CB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303CC + bool "STM32F303CC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303RB + bool "STM32F303RB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303RC + bool "STM32F303RC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303VB + bool "STM32F303VB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303VC + bool "STM32F303VC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + config ARCH_CHIP_STM32F405RG bool "STM32F405RG" select ARCH_CORTEXM4 @@ -190,6 +250,9 @@ config STM32_CONNECTIVITYLINE config STM32_STM32F20XX bool +config STM32_STM32F30XX + bool + config STM32_STM32F40XX bool @@ -220,6 +283,12 @@ config STM32_ADC3 select STM32_ADC depends on !STM32_VALUELINE +config STM32_ADC4 + bool "ADC4" + default n + select STM32_ADC + depends on STM32_STM32F30XX + config STM32_BKP bool "BKP" default n @@ -441,17 +510,17 @@ config STM32_TIM14 config STM32_TIM15 bool "TIM15" default n - depends on STM32_VALUELINE + depends on STM32_VALUELINE || STM32_STM32F30XX config STM32_TIM16 bool "TIM16" default n - depends on STM32_VALUELINE + depends on STM32_VALUELINE || STM32_STM32F30XX config STM32_TIM17 bool "TIM17" default n - depends on STM32_VALUELINE + depends on STM32_VALUELINE || STM32_STM32F30XX config STM32_USART1 bool "USART1" @@ -468,18 +537,21 @@ config STM32_USART2 config STM32_USART3 bool "USART3" default n + depends on !STM32_STM32F30XX select ARCH_HAVE_USART3 select STM32_USART config STM32_UART4 bool "UART4" default n + depends on !STM32_STM32F30XX select ARCH_HAVE_UART4 select STM32_USART config STM32_UART5 bool "UART5" default n + depends on !STM32_STM32F30XX select ARCH_HAVE_UART5 select STM32_USART @@ -493,7 +565,7 @@ config STM32_USART6 config STM32_USB bool "USB Device" default n - depends on STM32_STM32F10XX && !STM32_VALUELINE + depends on (STM32_STM32F10XX && !STM32_VALUELINE) || STM32_STM32F30XX select USBDEV config STM32_WWDG diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h index 41a87feae..6fc56f9af 100644 --- a/nuttx/arch/arm/src/stm32/chip.h +++ b/nuttx/arch/arm/src/stm32/chip.h @@ -49,6 +49,7 @@ /* Include the chip pin configuration file */ /* STM32 F1 Family ******************************************************************/ + #if defined(CONFIG_STM32_STM32F10XX) /* STM32F100 Value Line */ @@ -89,10 +90,17 @@ # endif /* STM32 F2 Family ******************************************************************/ + #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_pinmap.h" +/* STM32 F3 Family ******************************************************************/ + +#elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/stm32f30xxx_pinmap.h" + /* STM32 F4 Family ******************************************************************/ + #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_pinmap.h" #else @@ -108,6 +116,8 @@ # include "chip/stm32f10xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_vectors.h" +# elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/stm32f30xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_vectors.h" # else diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h index 36813b565..d87cb0247 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h @@ -47,6 +47,8 @@ # include "chip/stm32f10xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/stm32f30xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_memorymap.h" #else diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h new file mode 100644 index 000000000..88fe693f1 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h @@ -0,0 +1,155 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* STM32F40XXX Address Blocks *******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ + /* 0x60000000-0xdfffffff: Reserved */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */ + /* 0x10010000-0x1ffeffff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */ + /* 0x1fff7a10-0x1fff7fff: Reserved */ +#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ + /* 0x1fffc008-0x1fffffff: Reserved */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ + /* 0x4000a000-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */ + /* 0x40016c00-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x4007ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */ + /* 0x48001800-0x4fffFfff: Reserved */ +#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */ + +/* APB1 Base Addresses **************************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ +#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff TIM4 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ +#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */ +#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */ +#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff SPI3, or */ +#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff I2S3 */ +#define STM32_I2S3EXT_BASE 0x40004000 /* 0x40004000-0x400043ff I2S3ext */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */ +#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff UART4 */ +#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff UART5 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ +#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */ +#define STM32_USBSRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */ +#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ +#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC (dual) */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */ +#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */ +#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ +#define STM32_TIM8_BASE 0x40013400 /* 0x40013400-0x400137ff TIM8 */ +#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ +#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ +#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */ +#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ +#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ +#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ +#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ +#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ +#define STM32_GPIOD_BASE 0X40000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ +#define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */ +#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ + +/* AHB3 Base Addresses **************************************************************/ + +#define STM32_ADC1_BASE 0x50000000 /* 0x5000004c-0x5000004c: Master ADC1 */ +#define STM32_ADC2_BASE 0x50000100 /* 0x5000014c-0x500001ff: Slave ADC2 */ +#define STM32_ADC12_BASE 0x50000300 /* 0x50000300-0x50000308: ADC12 Common */ +#define STM32_ADC3_BASE 0x50000400 /* 0x5000044c-0x5000044c: Master ADC3 */ +#define STM32_ADC4_BASE 0x50000500 /* 0x5000054c-0x500005ff: Slave ADC4 */ +#define STM32_ADC34_BASE 0x50000700 /* 0x50000700-0x50000708: ADC34 Common */ + +/* Cortex-M4 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this + * address range + */ + +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H */ + diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_vectors.h new file mode 100644 index 000000000..e28ecb591 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_vectors.h @@ -0,0 +1,149 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f30xxx_vectors.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by stm32_vectors.S. It provides the macro VECTOR that + * supplies each STM32F30xxx vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f30xxx_irq.h. + * stm32_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 82 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 82 + +#else + +VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */ +VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */ +VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper or Time stamp interrupt */ +VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC global interrupt */ +VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */ +VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */ +VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */ +VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */ +VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 or TSC interrupt */ +VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */ + +VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */ +VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */ +VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */ +VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */ +VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */ +VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */ +VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */ +VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */ +VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* 18: ADC1/ADC2 global interrupt */ +VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* 19: USB High Priority or CAN1 TX interrupts */ + +VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* 20: USB Low Priority or CAN1 RX0 interrupts*/ +VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* 21: CAN1 RX1 interrupt */ +VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* 22: CAN1 SCE interrupt */ +VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */ +VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* 24: TIM1 Break or TIM15 global interrupt */ +VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* 25: TIM1 Update or TIM16 global interrupt */ +VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* 26: TIM1 Trigger or TIM17 global interrupt */ +VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* 27: TIM1 Capture Compare interrupt */ +VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */ +VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */ + +VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */ +VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event or EXTI Line23 interrupt */ +VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */ +VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event or EXTI Line24 interrupt */ +VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */ +VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */ +VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */ +VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global or EXTI Line 25 interrupt */ +VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global or EXTI Line 26 interrupt */ +VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global or EXTI Line 28 interrupt */ + +VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */ +VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */ +VECTOR(stm32_ext18, STM32_IRQ_EXT18) /* 42: USB wakeup or EXTI Line 18 interrupt */ +VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* 43: TIM8 Break interrupt */ +VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* 44: TIM8 Update interrupt */ +VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* 45: TIM8 Trigger and Commutation interrupts */ +VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* 46: TIM8 Capture Compare interrupt */ +VECTOR(stm32_adc3, STM32_IRQ_ADC3) /* 47: ADC3 global interrupt */ +UNUSED(STM32_IRQ_RESERVED48) /* 48: Reserved */ +UNUSED(STM32_IRQ_RESERVED49) /* 49: Reserved */ + +UNUSED(STM32_IRQ_RESERVED50) /* 50: Reserved */ +VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 51: SPI3 global interrupt */ +VECTOR(stm32_uart4, STM32_IRQ_UART4) /* 52: UART4 global or EXTI Line 34 interrupt */ +VECTOR(stm32_uart5, STM32_IRQ_UART5) /* 53: UART5 global or EXTI Line 35 interrupt */ +VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 54: TIM6 global or DAC1/2 underrun interrupts */ +VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* 55: TIM7 global interrupt */ +VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 56: DMA2 channel 1 global interrupt */ +VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 57: DMA2 channel 2 global interrupt */ +VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 58: DMA2 channel 3 global interrupt */ +VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* 59: DMA2 channel 4 global interrupt */ + +VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* 60: DMA2 channel 5 global interrupt */ +VECTOR(stm32_adc4, STM32_IRQ_ADC4) /* 61: ADC4 global interrupt */ +UNUSED(STM32_IRQ_RESERVED62) /* 62: Reserved */ +UNUSED(STM32_IRQ_RESERVED63) /* 63: Reserved */ +VECTOR(stm32_comp123, STM32_IRQ_COMP123) /* 64: COMP1-3 or EXTI Lines 21-2 and 29 interrupts */ +VECTOR(stm32_comp456, STM32_IRQ_COMP456) /* 65: COMP4-6 or EXTI Lines 30-2 interrupts */ +VECTOR(stm32_comp7, STM32_IRQ_COMP7) /* 66: COMP7 or EXTI Line 33 interrupt */ +UNUSED(STM32_IRQ_RESERVED67) /* 67: Reserved */ +UNUSED(STM32_IRQ_RESERVED68) /* 68: Reserved */ +UNUSED(STM32_IRQ_RESERVED69) /* 69: Reserved */ + +UNUSED(STM32_IRQ_RESERVED70) /* 70: Reserved */ +UNUSED(STM32_IRQ_RESERVED71) /* 71: Reserved */ +UNUSED(STM32_IRQ_RESERVED72) /* 72: Reserved */ +UNUSED(STM32_IRQ_RESERVED73) /* 73: Reserved */ +VECTOR(stm32_usbhp, STM32_IRQ_USBHP_2) /* 74: USB High priority interrupt */ +VECTOR(stm32_usblp, STM32_IRQ_USBLP_2) /* 75: USB Low priority interrupt */ +VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP_2) /* 76: USB wakeup from suspend through EXTI line interrupt*/ +UNUSED(STM32_IRQ_RESERVED77) /* 77: Reserved */ +UNUSED(STM32_IRQ_RESERVED78) /* 78: Reserved */ +UNUSED(STM32_IRQ_RESERVED79) /* 79: Reserved */ + +UNUSED(STM32_IRQ_RESERVED80) /* 80: Reserved */ +VECTOR(stm32_fpu, STM32_IRQ_FPU) /* 81: FPU global interrupt */ + +#endif /* CONFIG_ARMV7M_CMNVECTOR */ diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S index c9b62d762..68a3e498b 100644 --- a/nuttx/arch/arm/src/stm32/stm32_vectors.S +++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S @@ -150,6 +150,8 @@ stm32_vectors: # include "chip/chip/stm32f10xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/chip/stm32f20xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/chip/stm32f30xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/chip/stm32f40xxx_vectors.h" #else @@ -186,6 +188,8 @@ handlers: # include "chip/chip/stm32f10xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/chip/stm32f20xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/chip/stm32f30xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/chip/stm32f40xxx_vectors.h" #else -- cgit v1.2.3