From 0368c4fac2539f3a8812f9471e9be74fb7aeb303 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 15 May 2009 23:26:54 +0000 Subject: Basic clocking and UART works git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1786 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lm3s/lm3s_internal.h | 2 +- nuttx/arch/arm/src/lm3s/lm3s_lowputc.c | 50 +++++++++++++++++++++------------ 2 files changed, 33 insertions(+), 19 deletions(-) (limited to 'nuttx/arch/arm') diff --git a/nuttx/arch/arm/src/lm3s/lm3s_internal.h b/nuttx/arch/arm/src/lm3s/lm3s_internal.h index 22a69a24c..4d99cb492 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_internal.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_internal.h @@ -183,7 +183,7 @@ #define GPIO_PWM4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */ #define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ #define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -#define GPIO_SSI1_CLK (GPIO_FUNC_PFIO1 | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +#define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ #define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ #define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ #define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c index f6d5272ef..8ab1d1a47 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c @@ -220,47 +220,61 @@ void up_lowputc(char ch) void up_lowsetup(void) { + uint32 regval; #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) uint32 ctl; +#endif + + /* Enable the selected UARTs and configure GPIO pins to need by the + * the selected UARTs. NOTE: The serial driver later depends on + * this pin configuration -- whether or not a serial console is selected. + */ + +#ifndef CONFIG_UART0_DISABLE + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_UART0; + putreg32(regval, LM3S_SYSCON_RCGC1); + + lm3s_configgpio(GPIO_UART0_RX); + lm3s_configgpio(GPIO_UART0_TX); +#endif + +#ifndef CONFIG_UART1_DISABLE + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_UART1; + putreg32(regval, LM3S_SYSCON_RCGC1); + + lm3s_configgpio(GPIO_UART1_RX); + lm3s_configgpio(GPIO_UART1_TX); +#endif /* Enable the selected console device */ - /* 1. Disable the UART by clearing the UARTEN bit in the UART CTL register */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); ctl &= ~UART_CTL_UARTEN; putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); - /* 2. Write the integer portion of the BRD to the UART IBRD register */ + /* Write the integer portion of the BRD to the UART IBRD register */ putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET); - /* 3. Write the fractional portion of the BRD to the UART FBRD register */ + /* Write the fractional portion of the BRD to the UART FBRD register */ putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET); - /* 4. Write the desired serial parameters to the UART LCRH register */ + /* Write the desired serial parameters to the UART LCRH register */ putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET); - /* 5. Enable the UART by setting the UARTEN bit in the UART CTL register */ + /* Enable the UART by setting the UARTEN bit in the UART CTL register */ ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); #endif - /* Then configure GPIO pins to enable the selected UARTs. NOTE: The - * serial driver later depends on this pin configuration. - */ - -#ifndef CONFIG_UART0_DISABLE - lm3s_configgpio(GPIO_UART0_RX); - lm3s_configgpio(GPIO_UART0_TX); -#endif - -#ifndef CONFIG_UART1_DISABLE - lm3s_configgpio(GPIO_UART1_RX); - lm3s_configgpio(GPIO_UART1_TX); -#endif } -- cgit v1.2.3