From 5c775298fca577723a497605f0f4dec4df9fa05a Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 21 Feb 2012 22:00:28 +0000 Subject: STM32 SDIO DMA: Ignore DMA FIFO errors; these seem to be bogus. SD multiple block transfers result in CRC errors; avoid them by using smaller FTP buffer sizes git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4410 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/stm32/stm32_dma.h | 6 +++--- nuttx/arch/arm/src/stm32/stm32_sdio.c | 21 +-------------------- nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c | 7 +++++-- 3 files changed, 9 insertions(+), 25 deletions(-) (limited to 'nuttx/arch/arm') diff --git a/nuttx/arch/arm/src/stm32/stm32_dma.h b/nuttx/arch/arm/src/stm32/stm32_dma.h index 84b861e89..2ebd691d9 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dma.h +++ b/nuttx/arch/arm/src/stm32/stm32_dma.h @@ -60,13 +60,13 @@ */ #if defined(CONFIG_STM32_STM32F10XX) -# define DMA_STATUS_FEIF 0 -# define DMA_STATUS_DMEIF 0 +# define DMA_STATUS_FEIF 0 /* (Not available in F1) */ +# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */ # define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ # define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */ # define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */ #elif defined(CONFIG_STM32_STM32F40XX) -# define DMA_STATUS_FEIF DMA_STREAM_FEIF_BIT /* Stream FIFO error */ +# define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */ # define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */ # define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */ # define DMA_STATUS_HTIF DMA_STREAM_HTIF_BIT /* Stream Half Transfer */ diff --git a/nuttx/arch/arm/src/stm32/stm32_sdio.c b/nuttx/arch/arm/src/stm32/stm32_sdio.c index 60db7373b..9672aaf0c 100644 --- a/nuttx/arch/arm/src/stm32/stm32_sdio.c +++ b/nuttx/arch/arm/src/stm32/stm32_sdio.c @@ -188,26 +188,7 @@ # define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\ DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR) -/* STM32 F4 stream configuration register (SCR) settings. - * - * Hmmm... I see conflicting statements in the Reference Manual. In the DMA - * section it says: - - * "Note: The Burst mode is allowed only when incremetation is enabled: - * – When the PINC bit is at ‘0’, the PBURST bits should also be cleared to ‘00’ - * – When the MINC bit is at ‘0’, the MBURST bits should also be cleared to ‘00’." - * - * But in the SDIO section it says: - * - * "4. Configure the DMA2 as follows: - * ... - * c) Program DMA2_Stream3 or DMA2_Stream6 Channel4 control register - * (memory increment, not peripheral increment, peripheral and source - * width is word size). - * ... - * e) Configure the incremental burst transfer to 4 beats (at least from - * peripheral side)..." - */ +/* STM32 F4 stream configuration register (SCR) settings. */ #elif defined(CONFIG_STM32_STM32F40XX) # define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_P2M|DMA_SCR_MINC|\ diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c index 02d996631..db09cfd2e 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c @@ -676,11 +676,14 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * case, a FIFO error (flag FEIFx of the DMA_HISR or DMA_LISR register) will be * generated when the stream is enabled, then the stream will be automatically * disabled." + * + * NOTE: The FEIFx error interrupt is not enabled because the FEIFx seems to + * be reported spuriously causing good transfers to be marked as failures. */ regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET); - regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK); - regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS | DMA_SFCR_FEIE); + regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK | DMA_SFCR_FEIE); + regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS); dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval); /* "Configure data transfer direction, circular mode, peripheral & memory -- cgit v1.2.3