From 5e03aead9c9e4b44148a651952dfc09851927106 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 26 Mar 2013 18:18:50 +0000 Subject: More lpc17xx LCD logic (still incomplete) git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5787 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h | 292 ++++++++++++---------------- nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c | 205 ++++++++++++++++--- nuttx/arch/arm/src/lpc17xx/lpc17_lcd.h | 35 ++++ 3 files changed, 334 insertions(+), 198 deletions(-) (limited to 'nuttx/arch/arm') diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h index 0485db388..0cea0ab1b 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_lcd.h @@ -117,166 +117,130 @@ /* Register Bitfield Definitions ****************************************************************/ /* LCD_TIMH - Horizontal Timing Register */ - /* Bits 0-1: Reserved */ -#define LCD_TIMH_PPL_SHIFT (2) /* Bits 2-7: Pixels Per Line - 16-1024ppl */ + /* Bits 0-1: Reserved */ +#define LCD_TIMH_PPL_SHIFT (2) /* Bits 2-7: Pixels Per Line - 16-1024ppl */ #define LCD_TIMH_PPL_MASK (0x3f << LCD_TIMH_PPL_SHIFT) -#define LCD_TIMH_HSW_SHIFT (8) /* Bits 8-15: Horizontal Sync Pulse Width */ +#define LCD_TIMH_HSW_SHIFT (8) /* Bits 8-15: Horizontal Sync Pulse Width */ #define LCD_TIMH_HWS_MASK (0xff << LCD_TIMH_HSW_SHIFT) -#define LCD_TIMH_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch */ +#define LCD_TIMH_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch */ #define LCD_TIMH_HFP_MASK (0xff << LCD_TIMH_HFP_SHIFT) -#define LCD_TIMH_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch */ +#define LCD_TIMH_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch */ #define LCD_TIMH_HBP_MASK (0xff << LCD_TIMH_HBP_SHIFT) /* LCD_TIMV - Vertical Timing Register */ -#define LCD_TIMV_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel 1-1024 lpp*/ +#define LCD_TIMV_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel 1-1024 lpp*/ #define LCD_TIMV_LPP_MASK (0x3ff << LCD_TIMV_LPP_SHIFT) -#define LCD_TIMV_VSW_SHIFT (10) /* Bits 10-15: Vertical Synch Pulse Width */ +#define LCD_TIMV_VSW_SHIFT (10) /* Bits 10-15: Vertical Synch Pulse Width */ #define LCD_TIMV_VSW_MASK (0x3f << LCD_TIMV_VSW_SHIFT) -#define LCD_TIMV_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */ +#define LCD_TIMV_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */ #define LCD_TIMV_VFP_MASK (0xff << LCD_TIMV_VFP_SHIFT) -#define LCD_TIMV_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */ +#define LCD_TIMV_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */ #define LCD_TIMV_VBP_MASK (0xff << LCD_TIMV_VBP_SHIFT) /* LCD_POL - Clock and Signal Polarity Register */ -#define LCD_POL_PCDLO_SHIFT (0) /* Bits 0-4: Lower 5 bits of panel clock divisor */ +#define LCD_POL_PCDLO_SHIFT (0) /* Bits 0-4: Lower 5 bits of panel clock divisor */ #define LCD_POL_PCDLO_MASK (0x1f << LCD_POL_PCDLO_SHIFT) -#define LCD_POL_CLKSEL_SHIFT (5) /* Bit 5: Clock select- 0=CCLK, 1=LCD_CLKIN */ -#define LCD_POL_CLKSEL_MASK (1 << LCD_POL_CLKSEL_SHIFT) -#define LCD_POL_ACB_SHIFT (6) /* Bits 6-10: AC bias pin frequency */ +#define LCD_POL_CLKSEL (1 << 5) /* Bit 5: Clock select- 0=CCLK, 1=LCD_CLKIN */ +#define LCD_POL_ACB_SHIFT (6) /* Bits 6-10: AC bias pin frequency */ #define LCD_POL_ACB_MASK (0x1f << LCD_POL_ACB_SHIFT) -#define LCD_POL_IVS_SHIFT (11) /* Bit 11: Invert vertical sync */ -#define LCD_POL_IVS_MASK (1 << LCD_POL_IVS_SHIFT) -#define LCD_POL_IHS_SHIFT (12) /* Bit 12: Invert horizontal sync */ -#define LCD_POL_IHS_MASK (1 << LCD_POL_IHS_SHIFT) -#define LCD_POL_IPC_SHIFT (13) /* Bit 13: Invert panel clock */ -#define LCD_POL_IPC_MASK (1 << LCD_POL_IPC_SHIFT) -#define LCD_POL_IOE_SHIFT (14) /* Bit 14: Invert output enable */ -#define LCD_POL_IOE_MASK (1 << LCD_POL_IOE_SHIFT) - /* Bit 15: Reserved */ -#define LCD_POL_CPL_SHIFT (16) /* Bit 16-25: Clocks per line */ +#define LCD_POL_IVS (1 << 11) /* Bit 11: Invert vertical sync */ +#define LCD_POL_IHS (1 << 12) /* Bit 12: Invert horizontal sync */ +#define LCD_POL_IPC (1 << 13) /* Bit 13: Invert panel clock */ +#define LCD_POL_IOE (1 << 14) /* Bit 14: Invert output enable */ + /* Bit 15: Reserved */ +#define LCD_POL_CPL_SHIFT (16) /* Bit 16-25: Clocks per line */ #define LCD_POL_CPL_MASK (0x3ff << LCD_POL_CPL_SHIFT) -#define LCD_POL_BCD_SHIFT (26) /* Bit 26: Bypass pixel clock divider */ -#define LCD_POL_BCD_MASK (1 << LCD_POL_BCD_SHIFT) -#define LCD_POL_PCDHI_SHIFT (27) /* Bits 27-31: Upper 5 bits of panel clock divisor */ +#define LCD_POL_BCD (1 << 26) /* Bit 26: Bypass pixel clock divider */ +#define LCD_POL_PCDHI_SHIFT (27) /* Bits 27-31: Upper 5 bits of panel clock divisor */ #define LCD_POL_PCDHI_MASK (0x1f << LCD_POL_PCDHI_SHIFT) /* LCD_LE - Line End Control Register */ -#define LCD_LE_LED_SHIFT (0) /* Bits 0-6: Line End delay */ +#define LCD_LE_LED_SHIFT (0) /* Bits 0-6: Line End delay */ #define LCD_LE_LED_MASK (0x7f << LCD_LE_LED_SHIFT) - /* Bits 7-15: Reserved */ -#define LCD_LE_LEE_SHIFT (16) /* Bit16: LCD line end enable */ -#define LCD_LE_LEE_MASK (1 << LCD_LE_LEE_SHIFT) - /* Bit 17-31: Reserved */ + /* Bits 7-15: Reserved */ +#define LCD_LE_LEE (1 << 16) /* Bit 16: LCD line end enable */ + /* Bit 17-31: Reserved */ /* LCD_UPBASE - Upper Panel Frame Base Address Register */ - /* Bits 0-2: Reserved */ -#define LCD_UPBASE_LCDUPBASE_SHIFT (3) /* Bits 3-31: LCD upper panel base address */ + /* Bits 0-2: Reserved */ +#define LCD_UPBASE_LCDUPBASE_SHIFT (3) /* Bits 3-31: LCD upper panel base address */ #define LCD_UPBASE_LCDUPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) /* LCD_UPBASE - Lower Panel Frame Base Address Register */ - /* Bits 0-2: Reserved */ -#define LCD_UPBASE_LCDLPBASE_SHIFT (3) /* Bits 3-31: LCD lower panel base address */ + /* Bits 0-2: Reserved */ +#define LCD_UPBASE_LCDLPBASE_SHIFT (3) /* Bits 3-31: LCD lower panel base address */ #define LCD_UPBASE_LCDLPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) /* LCD_CTRL - Controle Register */ -#define LCD_CTRL_LCDEN_SHIFT (0) /* Bit 0: LCD enable control bit */ -#define LCD_CTRL_LCDEN_MASK (1 << LCD_CTRL_LCDEN_SHIFT) -#define LCD_CTRL_LCDBPP_SHIFT (1) /* Bits 1-3: LCD bits per pixel */ +#define LCD_CTRL_LCDEN (1 << 0) /* Bit 0: LCD enable control bit */ +#define LCD_CTRL_LCDBPP_SHIFT (1) /* Bits 1-3: LCD bits per pixel */ #define LCD_CTRL_LCDBPP_MASK (7 << LCD_CTRL_LCDBPP_SHIFT) -#define LCD_CTRL_LCDBW_SHIFT (4) /* Bit 4: STN LCD monochrome/color selection */ -#define LCD_CTRL_LCDBW_MASK (1 << LCD_CTRL_LCDBW_SHIFT) -#define LCD_CTRL_LCDTFT_SHIFT (5) /* Bit 5: LCD TFT type selection */ -#define LCD_CTRL_LCDTFT_MASK (1 << LCD_CTRL_LCDTFT_SHIFT) -#define LCD_CTRL_LCDMONO8_SHIFT (6) /* Bit 6: Monochrome LCD interface bit */ -#define LCD_CTRL_LCDMONO8_MASK (1 << LCD_CTRL_LCDMONO8_SHIFT) -#define LCD_CTRL_LCDDUAL_SHIFT (7) /* Bit 7: Single or Dual LCD panel selection */ -#define LCD_CTRL_LCDDUAL_MASK (1 << LCD_CTRL_LCDDUAL_SHIFT) -#define LCD_CTRL_BGR_SHIFT (8) /* Bit 8: Color format */ -#define LCD_CTRL_BGR_MASK (1 << LCD_CTRL_BGR_SHIFT) -#define LCD_CTRL_BEBO_SHIFT (9) /* Bit 9: Big-Endian Byte Order */ -#define LCD_CTRL_BEBO_MASK (1 << LCD_CTRL_BEBO_SHIFT) -#define LCD_CTRL_BEPO_SHIFT (10) /* Bit 10: Big-Endian Pixel Ordering */ -#define LCD_CTRL_BEPO_MASK (1 << LCD_CTRL_BEPO_SHIFT) -#define LCD_CTRL_LCDPWR_SHIFT (11) /* Bit 11: LCD Power enable */ -#define LCD_CTRL_LCDPWR_MASK (1 << LCD_CTRL_LCDPWR_SHIFT) -#define LCD_CTRL_LCDVCOMP_SHIFT (12) /* Bits 12-13: LCD Vertical compare interrupt */ +#define LCD_CTRL_LCDBW (1 << 4) /* Bit 4: STN LCD monochrome/color selection */ +#define LCD_CTRL_LCDTFT (1 << 5) /* Bit 5: LCD TFT type selection */ +#define LCD_CTRL_LCDMONO8 (1 << 6) /* Bit 6: Monochrome LCD interface bit */ +#define LCD_CTRL_LCDDUAL (1 << 7) /* Bit 7: Single or Dual LCD panel selection */ +#define LCD_CTRL_BGR (1 << 8) /* Bit 8: Color format */ +#define LCD_CTRL_BEBO (1 << 9) /* Bit 9: Big-Endian Byte Order */ +#define LCD_CTRL_BEPO (1 << 10) /* Bit 10: Big-Endian Pixel Ordering */ +#define LCD_CTRL_LCDPWR (1 << 11) /* Bit 11: LCD Power enable */ +#define LCD_CTRL_LCDVCOMP_SHIFT (12) /* Bits 12-13: LCD Vertical compare interrupt */ #define LCD_CTRL_LCDVCOMP_MASK (3 << LCD_CTRL_LCDVCOMP_SHIFT) - /* Bits 14-15: Reserved */ -#define LCD_CTRL_WATERMARK_SHIFT (16) /* Bit 16: LCD DMA FIFO watermark level */ -#define LCD_CTRL_WATERMARK_MASK (1 << LCD_CTRL_WATERMARK_SHIFT) - /* Bits 17-31: Reserved */ + /* Bits 14-15: Reserved */ +#define LCD_CTRL_WATERMARK (1 << 16) /* Bit 16: LCD DMA FIFO watermark level */ + /* Bits 17-31: Reserved */ /* LCD_INTMSK - Interrupt Mask Register */ - /* Bits 0: Reserved */ -#define LCD_INTMSK_FUFIM_SHIFT (1) /* Bit 1: FIFO underflow interrupt enable */ -#define LCD_INTMSK_FUFIM_MASK (1 << LCD_INTMSK_FUFIM_SHIFT) -#define LCD_INTMSK_LNBUIM_SHIFT (2) /* Bit 2: LCD next base address interrupt enable */ -#define LCD_INTMSK_LNBUIM_MASK (1 << LCD_INTMSK_LNBUIM_SHIFT) -#define LCD_INTMSK_VCOMPIM_SHIFT (3) /* Bit 3: Vertical compare interrupt enable */ -#define LCD_INTMSK_VCOMPIM_MASK (1 << LCD_INTMSK_VCOMPIM_SHIFT) -#define LCD_INTMSK_BERIM_SHIFT (4) /* Bit 4: AHB Master error interrupt enable */ -#define LCD_INTMSK_BERIM_MASK (1 << LCD_INTMSK_BERIM_SHIFT) - /* Bits 5-31: Reserved */ + /* Bits 0: Reserved */ +#define LCD_INTMSK_FUFIM (1 << 1) /* Bit 1: FIFO underflow interrupt enable */ +#define LCD_INTMSK_LNBUIM (1 << 2) /* Bit 2: LCD next base address interrupt enable */ +#define LCD_INTMSK_VCOMPIM (1 << 3) /* Bit 3: Vertical compare interrupt enable */ +#define LCD_INTMSK_BERIM (1 << 4) /* Bit 4: AHB Master error interrupt enable */ + /* Bits 5-31: Reserved */ /* LCD_INTRAW - Raw Interrupt Status Register */ - /* Bits 0: Reserved */ -#define LCD_INTRAW_FUFRIS_SHIFT (1) /* Bit 1: FIFO Undeflow raw interrupt status */ -#define LCD_INTRAW_FUFRIS_MASK (1 << LCD_INTRAW_FUFRIS_SHIFT) -#define LCD_INTRAW_LNBURIS_SHIFT (2) /* Bit 2: LCD Next address base update intterupt */ -#define LCD_INTRAW_LNBURIS_MASK (1 << LCD_INTRAW_LNBURIS_SHIFT) -#define LCD_INTRAW_VCOMPRIS_SHIFT (3) /* Bit 3: Vertical compare interrupt status */ -#define LCD_INTRAW_VCOMPRIS_MASK (1 << LCD_INTRAW_VCOMPRIS_SHIFT) -#define LCD_INTRAW_BERRAW_SHIFT (4) /* Bit 4: AHB Master bus error interrupt status */ -#define LCD_INTRAW_BERRAW_MASK (1 << LCD_INTRAW_BERRAW_SHIFT) - /* Bits 5-31: Reserved */ + /* Bits 0: Reserved */ +#define LCD_INTRAW_FUFRIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ +#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTRAW_VCOMPRIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ +#define LCD_INTRAW_BERRAW (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ + /* Bits 5-31: Reserved */ /* LCD_INTSTAT - Masked Interrupt Status Register */ - /* Bits 0: Reserved */ -#define LCD_INTSTAT_FUFMIS_SHIFT (1) /* Bit 1: FIFO Undeflow raw interrupt status */ -#define LCD_INTSTAT_FUFMIS_MASK (1 << LCD_INTSTAT_FUFMIS_SHIFT) -#define LCD_INTSTAT_LNBUMIS_SHIFT (2) /* Bit 2: LCD Next address base update intterupt */ -#define LCD_INTSTAT_LNBUMIS_MASK (1 << LCD_INTSTAT_LNBUMIS_SHIFT) -#define LCD_INTSTAT_VCOMPMIS_SHIFT (3) /* Bit 3: Vertical compare interrupt status */ -#define LCD_INTSTAT_VCOMPMIS_MASK (1 << LCD_INTSTAT_VCOMPMIS_SHIFT) -#define LCD_INTSTAT_BERMIS_SHIFT (4) /* Bit 4: AHB Master bus error interrupt status */ -#define LCD_INTSTAT_BERMIS_MASK (1 << LCD_INTSTAT_BERMIS_SHIFT) - /* Bits 15-31: Reserved */ + /* Bits 0: Reserved */ +#define LCD_INTSTAT_FUFMIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ +#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTSTAT_VCOMPMIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ +#define LCD_INTSTAT_BERMIS (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ + /* Bits 15-31: Reserved */ /* LCD_INTCLR - Interrupt Clear Register */ - /* Bits 0: Reserved */ -#define LCD_INTCLR_FUFIC_SHIFT (1) /* Bit 1: FIFO Undeflow raw interrupt clear */ -#define LCD_INTCLR_FUFIC_MASK (1 << LCD_INTCLR_FUFIC_SHIFT) -#define LCD_INTCLR_LNBUIC_SHIFT (2) /* Bit 2: LCD Next address base update intterupt */ -#define LCD_INTCLR_LNBUIC_MASK (1 << LCD_INTCLR_LNBUIC_SHIFT) -#define LCD_INTCLR_VCOMPIC_SHIFT (3) /* Bit 3: Vertical compare interrupt clear */ -#define LCD_INTCLR_VCOMPIC_MASK (1 << LCD_INTCLR_VCOMPIC_SHIFT) -#define LCD_INTCLR_BERIC_SHIFT (4) /* Bit 4: AHB Master bus error interrupt clear */ -#define LCD_INTCLR_BERIC_MASK (1 << LCD_INTCLR_BERIC_SHIFT) - /* Bits 15-31: Reserved */ - + /* Bits 0: Reserved */ +#define LCD_INTCLR_FUFIC (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt clear */ +#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTCLR_VCOMPIC (1 << 3) /* Bit 3: Vertical compare interrupt clear */ +#define LCD_INTCLR_BERIC (1 << 4) /* Bit 4: AHB Master bus error interrupt clear */ + /* Bits 15-31: Reserved */ /* Upper and Lower Panel Address register has no bitfields */ /* * Upper Panel Current Address register (LCDUPCURR) * Lower Panel Current Address register (LCDLPCURR) */ -/* LCD_PAL - Color Palette Register */ - -#define LCD_PAL_R04_0_SHIFT (0) /* Bits 0-4: Red palette data */ -#define LCD_PAL_R04_0_MASK (0x1f << LCD_PAL_R04_0_SHIFT) -#define LCD_PAL_G04_0_SHIFT (5) /* Bits 5-9: Green palette data */ -#define LCD_PAL_G04_0_MASK (0x1f << LCD_PAL_G04_0_SHIFT) -#define LCD_PAL_B04_0_SHIFT (10) /* Bits 10-14: Blue paletted data */ -#define LCD_PAL_B04_0_MASK (0x1f << LCD_PAL_B04_0_SHIFT) -#define LCD_PAL_I0_SHIFT (15) /* Bit 15: Intensity/Unused bit */ -#define LCD_PAL_I0_MASK (1 << LCD_PAL_I0_SHIFT) -#define LCD_PAL_R14_0_SHIFT (16) /* Bit 16-20: Reda palette data */ -#define LCD_PAL_R14_0_MASK (0x1f << LCD_PAL_R14_0_SHIFT) -#define LCD_PAL_G14_0_SHIFT (21) /* Bit 21-25: Green palette data */ -#define LCD_PAL_G14_0_MASK (0x1f << LCD_PAL_G14_0_SHIFT) -#define LCD_PAL_B14_0_SHIFT (26) /* Bit 26-30: Blue palette data */ -#define LCD_PAL_B14_0_MASK (0x1f << LCD_PAL_B14_0_SHIFT) -#define LCD_PAL_I1_SHIFT (31) /* Bit 31: Intensity/Unused bit */ -#define LCD_PAL_I1_MASK (1 << LCD_PAL_I1_SHIFT) +/* LCD_PAL - Color Palette Registers */ + +#define LCD_PAL_R0_SHIFT (0) /* Bits 0-4: Red palette data */ +#define LCD_PAL_R0_MASK (0x1f << LCD_PAL_R0_SHIFT) +#define LCD_PAL_G0_SHIFT (5) /* Bits 5-9: Green palette data */ +#define LCD_PAL_G0_MASK (0x1f << LCD_PAL_G0_SHIFT) +#define LCD_PAL_B0_SHIFT (10) /* Bits 10-14: Blue paletted data */ +#define LCD_PAL_B0_MASK (0x1f << LCD_PAL_B0_SHIFT) +#define LCD_PAL_I0 (1 << 15) /* Bit 15: Intensity/Unused bit */ +#define LCD_PAL_R1_SHIFT (16) /* Bits 16-20: Red palette data */ +#define LCD_PAL_R1_MASK (0x1f << LCD_PAL_R1_SHIFT) +#define LCD_PAL_G1_SHIFT (21) /* Bits 21-25: Green palette data */ +#define LCD_PAL_G1_MASK (0x1f << LCD_PAL_G1_SHIFT) +#define LCD_PAL_B1_SHIFT (26) /* Bits 26-30: Blue palette data */ +#define LCD_PAL_B1_MASK (0x1f << LCD_PAL_B1_SHIFT) +#define LCD_PAL_I1 (1 << 31) /* Bit 31: Intensity/Unused bit */ /* LCD_CRSR_IMG - Cursor Image Register - has no bitfields */ /* The 256 words of the cursor image register defines the appearance @@ -285,12 +249,12 @@ /* LCD CRSR_CTRL - Cursor Control Register */ -#define LCD_CRSR_CTRL_CRSON_SHIFT (0) /* Bit 0: Cursor enable */ +#define LCD_CRSR_CTRL_CRSON (1 << 0) /* Bit 0: Cursor enable */ #define LCD_CRSR_CTRL_CRSON_MASK (1 << LCD_CRSR_CTRL_CRSON_SHIFT) - /* Bit 1-3: Reserved */ -#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4) /* Bit 4-5: Cursor image number */ -#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (3 << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT) - /* Bit 6-31: Reserved */ + /* Bits 1-3: Reserved */ +#define LCD_CRSR_CTRL_CRSRNUM_SHIFT (4) /* Bits 4-5: Cursor image number */ +#define LCD_CRSR_CTRL_CRSRNUM_MASK (3 << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT) + /* Bits 6-31: Reserved */ /* If the selected cursor is 32x32 */ #define LCD_CURSOR0 (0) @@ -300,71 +264,57 @@ /* LCD CRSR_CFG - Cursor Configuration Register */ -#define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0) /* Bit 0: Cursor size selection */ -#define LCD_CRSR_CFG_CRSRSIZE_MASK (1 << LCD_CRSR_CFG_CRSRSIZE_SHIFT) -#define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1) /* Bit 1: Cursor frame sync type */ -#define LCD_CRSR_CFG_FRAMESYNC_MASK (1 << LCD_CRSR_CFG_FRAMESYNC_SHIFT) - /* Bit 2-31: Reserved */ -#define LCD_CURSOR_SIZE32 (0) /* 32x32 */ -#define LCD_CURSOR_SIZE64 (1) /* 64x64 */ -#define LCD_CURSOR_FRAMEASYNC (0) /* Cursor coordinates are asynchronous */ -#define LCD_CURSOR_FRAMESYNC (1) /* coordinates are synchronize to framesync pulse */ - -/* LCD CRSR_PAL0 - Cursor Palette Register 0 */ - -#define LCD_CRSR_PAL0_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ -#define LCD_CRSR_PAL0_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT) -#define LCD_CRSR_PAL0_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ -#define LCD_CRSR_PAL0_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT) -#define LCD_CRSR_PAL0_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */ -#define LCD_CRSR_PAL0_BLUE_MASK (0xff << LCD_CRSR_PAL0_BLUE_SHIFT) - /* Bit 24-31: Reserved */ -/* LCD CRSR_PAL1 - Cursor Palette Register 1 */ - -#define LCD_CRSR_PAL1_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ -#define LCD_CRSR_PAL1_RED_MASK (0xff << LCD_CRSR_PAL1_RED_SHIFT) -#define LCD_CRSR_PAL1_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ -#define LCD_CRSR_PAL1_GREEN_MASK (0xff << LCD_CRSR_PAL1_GREEN_SHIFT) -#define LCD_CRSR_PAL1_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */ -#define LCD_CRSR_PAL1_BLUE_MASK (0xff << LCD_CRSR_PAL1_BLUE_SHIFT) - /* Bit 24-31: Reserved */ +#define LCD_CRSR_CFG_CRSRSIZE (1 << 0) /* Bit 0: Cursor size selection */ +#define LCD_CRSR_CFG_FRAMESYNC (1 << 1) /* Bit 1: Cursor frame sync type */ + /* Bits 2-31: Reserved */ + +#define LCD_CURSOR_SIZE32 (0) /* 32x32 */ +#define LCD_CURSOR_SIZE64 (1) /* 64x64 */ +#define LCD_CURSOR_FRAMEASYNC (0) /* Cursor coordinates are asynchronous */ +#define LCD_CURSOR_FRAMESYNC (1) /* coordinates are synchronize to framesync pulse */ + +/* LCD CRSR_PAL0/1 - Cursor Palette Registers */ + +#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ +#define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT) +#define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ +#define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT) +#define LCD_CRSR_PAL_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */ +#define LCD_CRSR_PAL_BLUE_MASK (0xff << LCD_CRSR_PAL0_BLUE_SHIFT) + /* Bits 24-31: Reserved */ /* LCD CRSR_XY - Cursor XY Position Register */ -#define LCD_CRSR_CRSRX_SHIFT (0) /* Bits 0-9: X ordinate */ +#define LCD_CRSR_CRSRX_SHIFT (0) /* Bits 0-9: X ordinate */ #define LCD_CRSR_CRSRX_MASK (0x3ff << LCD_CRSR_CRSRX_SHIFT) - /* Bit 10-15: Reserved */ -#define LCD_CRSR_CRSRY_SHIFT (16) /* Bits 16-25: Y ordinate */ + /* Bits 10-15: Reserved */ +#define LCD_CRSR_CRSRY_SHIFT (16) /* Bits 16-25: Y ordinate */ #define LCD_CRSR_CRSRY_MASK (0x3ff << LCD_CRSR_CRSRY_SHIFT) - /* Bit 26-31: Reserved */ + /* Bits 26-31: Reserved */ /* LCD CRSR_CLIP - Cursor Clip Position Register */ -#define LCD_CRSR_CRSRCLIPX_SHIFT (0) /* Bits 0-5: X clip position */ +#define LCD_CRSR_CRSRCLIPX_SHIFT (0) /* Bits 0-5: X clip position */ #define LCD_CRSR_CRSRCLIPX_MASK (0x3f << LCD_CRSR_CRSRCLIPX_SHIFT) - /* Bit 6-7: Reserved */ -#define LCD_CRSR_CRSRCLIPY_SHIFT (8) /* Bits 8-13: Reserved */ + /* Bits 6-7: Reserved */ +#define LCD_CRSR_CRSRCLIPY_SHIFT (8) /* Bits 8-13: Reserved */ #define LCD_CRSR_CRSRCLIPY_MASK (0x3f << LCD_CRSR_CRSRCLIPY_SHIFT) - /* Bit 14-31: Reserved */ + /* Bits 14-31: Reserved */ /* LCD CRSR_INTMSK - Cursor Interrrupt Mask Register */ -#define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0) /* Bit 0: Cursor interrupt mask */ -#define LCD_CRSR_INTMSK_CRSRIM_MASK (1 << LCD_CRSR_INTMSK_CRSRIM_SHIFT) - /* Bit 1-31: Reserved */ +#define LCD_CRSR_INTMSK_CRSRIM (1 << 0) /* Bit 0: Cursor interrupt mask */ + /* Bits 1-31: Reserved */ /* LCD CRSR_INTCLR - Cursor Interrrupt Clear Register */ -#define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0) /* Bit 0: Cursor interrupt clear */ -#define LCD_CRSR_INTCLR_CRSRIC_MASK (1 << LCD_CRSR_INTCLR_CRSRIC_SHIFT) - /* Bit 1-31: Reserved */ +#define LCD_CRSR_INTCLR_CRSRIC (1 << 0) /* Bit 0: Cursor interrupt clear */ + /* Bits 1-31: Reserved */ /* LCD CRSR_INTRAW - Cursor Raw Interrrupt Status Register */ -#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0) /* Bit 0: Cursor raw interrupt status */ -#define LCD_CRSR_INTRAW_CRSRRIS_MASK (1 << LCD_CRSR_INTRAW_CRSRRIS_SHIFT) - /* Bit 1-31: Reserved */ +#define LCD_CRSR_INTRAW_CRSRRIS (1 << 0) /* Bit 0: Cursor raw interrupt status */ + /* Bits 1-31: Reserved */ /* LCD CRSR_INTSTAT - Mask Interrrupt Status Register */ -#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0) /* Bit 0: Cursor mask interrupt status */ -#define LCD_CRSR_INTSTAT_CRSRMIS_MASK (1 << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT) - /* Bit 1-31: Reserved */ +#define LCD_CRSR_INTSTAT_CRSRMIS (1 << 0) /* Bit 0: Cursor mask interrupt status */ + /* Bits 1-31: Reserved */ /************************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c b/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c index 0fdae36e7..270250d83 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c @@ -56,6 +56,11 @@ #define FB_WIDTH ((CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_BPP + 7) / 8) #define FB_SIZE (FB_WIDTH * CONFIG_LPC17_LCD_VHEIGHT) +/* Delays */ + +#define LPC17_LCD_PWRDIS_DELAY 10000 +#define LPC17_LCD_PWREN_DELAY 10000 + /**************************************************************************** * Private Types ****************************************************************************/ @@ -113,7 +118,7 @@ static const struct fb_videoinfo_s g_videoinfo = static const struct fb_planeinfo_s g_planeinfo = { - .fbmem = (FAR void *)LCD_VRAM_BASE, + .fbmem = (FAR void *)CONFIG_LPC17_LCD_VRAMBASE, .fblen = FB_SIZE, .stride = FB_WIDTH, .bpp = CONFIG_LPC17_LCD_BPP, @@ -198,30 +203,72 @@ static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, ****************************************************************************/ #ifdef CONFIG_FB_CMAP -static int lpc17_getcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *cmap) +static int lpc17_getcmap(FAR struct fb_vtable_s *vtable, + FAR struct fb_cmap_s *cmap) { - int len; + uint32_t *pal; + uint32_t rgb; + int last; int i; - dbg("vtable=%p cmap=%p len=%d\n", vtable, cmap, cmap->len); - if (vtable && cmap) + dbg("vtable=%p cmap=%p first=%d len=%d\n", + vtable, cmap, cmap->first, cmap->len); + + DEBUGASSERT(vtable && cmap && + cmap->first < 256 && (cmap->first + cmap->len) < 256); + + pal = (uint32_t *)LPC17_LCD_PAL(cmap->first >> 1); + last = cmap->first + cmap->len; + + /* Handle the case where the first color starts on an odd boundary */ + + i = cmap->first; + if ((i & 1) != 0) { - for (i = cmap->first, len = 0; i < 256 && len < cmap->len; i++, len++) + rgb = *pal++; + i++; + + /* Save the odd palette value */ + + cmap->red[i] = (rgb & LCD_PAL_R1_MASK) >> LCD_PAL_R1_SHIFT; + cmap->green[i] = (rgb & LCD_PAL_G1_MASK) >> LCD_PAL_G1_SHIFT; + cmap->blue[i] = (rgb & LCD_PAL_B1_MASK) >> LCD_PAL_B1_SHIFT; +#ifdef CONFIG_FB_TRANSPARENCY + cmap->transp[i] = 0; +#endif + } + + /* Handle even colors */ + + for (; i < last; i += 2) + { + rgb = *pal++; + + /* Save the even palette value */ + + cmap->red[i] = (rgb & LCD_PAL_R0_MASK) >> LCD_PAL_R0_SHIFT; + cmap->green[i] = (rgb & LCD_PAL_G0_MASK) >> LCD_PAL_G0_SHIFT; + cmap->blue[i] = (rgb & LCD_PAL_B0_MASK) >> LCD_PAL_B0_SHIFT; +#ifdef CONFIG_FB_TRANSPARENCY + cmap->transp[i] = 0; +#endif + + /* Handle the case where the len ends on an odd boudary */ + + if ((i + 1) < last) { - cmap->red[i] = i; - cmap->green[i] = i; - cmap->blue[i] = i; + /* Save the even palette value */ + + cmap->red[i+1] = (rgb & LCD_PAL_R1_MASK) >> LCD_PAL_R1_SHIFT; + cmap->green[i+1] = (rgb & LCD_PAL_G1_MASK) >> LCD_PAL_G1_SHIFT; + cmap->blue[i+1] = (rgb & LCD_PAL_B1_MASK) >> LCD_PAL_B1_SHIFT; #ifdef CONFIG_FB_TRANSPARENCY - cmap->transp[i] = i; + cmap->transp[i+1] = 0; #endif } - - cmap->len = len; - return OK; } - dbg("Returning EINVAL\n"); - return -EINVAL; + return OK; } #endif @@ -230,16 +277,68 @@ static int lpc17_getcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *c ****************************************************************************/ #ifdef CONFIG_FB_CMAP -static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, FAR const struct fb_cmap_s *cmap) +static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, + FAR const struct fb_cmap_s *cmap) { - dbg("vtable=%p cmap=%p len=%d\n", vtable, cmap, cmap->len); - if (vtable && cmap) + uint32_t *pal; + uint32_t rgb0; + uint32_t rgb1; + int last; + int i; + + dbg("vtable=%p cmap=%p first=%d len=%d\n", + vtable, cmap, cmap->first, cmap->len); + + DEBUGASSERT(vtable && cmap); + + pal = (uint32_t *)LPC17_LCD_PAL(cmap->first >> 1); + last = cmap->first + cmap->len; + + /* Handle the case where the first color starts on an odd boundary */ + + i = cmap->first; + if ((i & 1) != 0) { - return OK; + rgb0 = *pal; + rgb0 &= (LCD_PAL_R0_MASK | LCD_PAL_G0_MASK | LCD_PAL_B0_MASK | LCD_PAL_I0); + rgb1 |= ((uint32_t)cmap->red[i] << LCD_PAL_R0_SHIFT | + (uint32_t)cmap->green[i] << LCD_PAL_G0_SHIFT | + (uint32_t)cmap->blue[i] << LCD_PAL_B0_SHIFT); + + /* Save the new palette value */ + + *pal++ = (rgb0 | rgb1); + i++; } - dbg("Returning EINVAL\n"); - return -EINVAL; + /* Handle even colors */ + + for (; i < last; i += 2) + { + uint32_t rgb0 = ((uint32_t)cmap->red[i] << LCD_PAL_R0_SHIFT | + (uint32_t)cmap->green[i] << LCD_PAL_G0_SHIFT | + (uint32_t)cmap->blue[i] << LCD_PAL_B0_SHIFT); + + /* Handle the case where the len ends on an odd boudary */ + + if ((i + 1) >= last) + { + rgb1 = *pal; + rgb1 &= (LCD_PAL_R1_MASK | LCD_PAL_G1_MASK | LCD_PAL_B1_MASK | LCD_PAL_I1); + } + else + { + rgb1 = ((uint32_t)cmap->red[i+1] << LCD_PAL_R1_SHIFT | + (uint32_t)cmap->green[i+1] << LCD_PAL_G1_SHIFT | + (uint32_t)cmap->blue[i+1] << LCD_PAL_B1_SHIFT); + } + + /* Save the new pallete value */ + + *pal++ = (rgb0 | rgb1); + } + + return OK; } #endif @@ -326,11 +425,21 @@ static int lpc17_setcursor(FAR struct fb_vtable_s *vtable, int up_fbinitialize(void) { + int i; + /* Disable LCD controller */ -#warning "Missing logioc" + + regval = getreg32(LPC17_LCD_CTRL); + regval &= ~LCD_CTRL_LCDPWR; + putreg32(regval, LPC17_LCD_CTRL); + + for (i = LPC17_LCD_PWRDIS_DELAY; i; i--); + + regval &= ~LCD_CTRL_LCDEN; + putreg32(regval, LPC17_LCD_CTRL); /* Configure pins */ - /* R */ + /* Video data */ lpc17_configgpio(GPIO_LCD_VD0); lpc17_configgpio(GPIO_LCD_VD1); @@ -341,8 +450,6 @@ int up_fbinitialize(void) lpc17_configgpio(GPIO_LCD_VD6); lpc17_configgpio(GPIO_LCD_VD7); - /* G */ - lpc17_configgpio(GPIO_LCD_VD8); lpc17_configgpio(GPIO_LCD_VD9); lpc17_configgpio(GPIO_LCD_VD10); @@ -352,8 +459,7 @@ int up_fbinitialize(void) lpc17_configgpio(GPIO_LCD_VD14); lpc17_configgpio(GPIO_LCD_VD15); - /* B */ - +#if CONFIG_LPC17_LCD_BPP == 24 lpc17_configgpio(GPIO_LCD_VD16); lpc17_configgpio(GPIO_LCD_VD17); lpc17_configgpio(GPIO_LCD_VD18); @@ -362,6 +468,7 @@ int up_fbinitialize(void) lpc17_configgpio(GPIO_LCD_VD21); lpc17_configgpio(GPIO_LCD_VD22); lpc17_configgpio(GPIO_LCD_VD23); +#endif /* Other pins */ @@ -371,6 +478,24 @@ int up_fbinitialize(void) lpc17_configgpio(GPIO_LCD_ENABM); lpc17_configgpio(GPIO_LCD_PWR); +#warning "Missing logic" + + /* Clear the display */ + + lpc17_lcdclear(CONFIG_LPC17_LCD_BACKCOLOR); + for (i = LPC17_LCD_PWREN_DELAY; i; i--); + + /* Enable LCD */ + + regval = getreg32(LPC17_LCD_CTRL); + regval |= LCD_CTRL_LCDEN; + putreg32(regval, LPC17_LCD_CTRL); + + for (i = LPC17_LCD_PWREN_DELAY; i; i--); + + regval |= LCD_CTRL_LCDPWR; + putreg32(regval, LPC17_LCD_CTRL); + return OK; } @@ -414,3 +539,29 @@ void fb_uninitialize(void) return OK; } +/************************************************************************************ + * Name: lpc17_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the LPC17xx. Clearing the display + * in the normal way by writing a sequences of runs that covers the entire display + * can be slow. Here the dispaly is cleared by simply setting all VRAM memory to + * the specified color. + * + ************************************************************************************/ + +void lpc17_lcdclear(nxgl_pixel_t color) +{ +#if CONFIG_LPC17_LCD_BPP == 16 + uint16_t *dest; +#else + uint32_t *dest; +#endif + int i; + + dest = (uint32_t *) CONFIG_LPC17_LCD_VRAMBASE; + for (i = 0; (CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT) > i; i++) + { + *dest++ = color; + } +} diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.h b/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.h index e86e83dfa..e17a8cc53 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.h @@ -41,6 +41,8 @@ ************************************************************************************/ #include +#include + #include "chip/lpc17_lcd.h" /************************************************************************************ @@ -48,14 +50,26 @@ ************************************************************************************/ /* Configuration */ +/* Base address of the video RAM frame buffer */ + +#ifndef CONFIG_LPC17_LCD_VRAMBASE +# define CONFIG_LPC17_LCD_VRAMBASE ((uint32_t)LPC17_EXTDRAM_CS0 + 0x00010000) +#endif + +/* LCD refresh rate */ + #ifndef CONFIG_LPC17_LCD_REFRESH_FREQ # define CONFIG_LPC17_LCD_REFRESH_FREQ (50) /* Hz */ #endif +/* Bits per pixel */ + #ifndef CONFIG_LPC17_LCD_BPP # define CONFIG_LPC17_LCD_BPP 16 /* Bytes per pixel */ #endif +/* Color format */ + #undef FB_FMT #if CONFIG_LPC17_LCD_BPP == 16 # define FB_FMT FB_FMT_RGB16_565 @@ -65,6 +79,12 @@ # error "Unsupported BPP" #endif +#ifndef CONFIG_LPC17_LCD_BACKCOLOR +# define CONFIG_LPC17_LCD_BACKCOLOR 0 /* Initial background color */ +#endif + +/* Horizontal video characteristics */ + #ifndef CONFIG_LPC17_LCD_HWIDTH # define CONFIG_LPC17_LCD_HWIDTH 480 /* Width in pixels */ #endif @@ -81,6 +101,8 @@ # define CONFIG_LPC17_LCD_HBACKPORCH 40 #endif +/* Vertical video characteristics */ + #ifndef CONFIG_LPC17_LCD_VHEIGHT # define CONFIG_LPC17_LCD_VHEIGHT 272 /* Height in rows */ #endif @@ -112,4 +134,17 @@ * include/nuttx/fb.h. */ +/************************************************************************************ + * Name: lpc17_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the LPC17xx. Clearing the display + * in the normal way by writing a sequences of runs that covers the entire display + * can be slow. Here the dispaly is cleared by simply setting all VRAM memory to + * the specified color. + * + ************************************************************************************/ + +void lpc17_lcdclear(nxgl_mxpixel_t color); + #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_LCD_H */ -- cgit v1.2.3