From 9b9627f7223c6f2e20afaf57a340d8e4d3370aec Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Sat, 9 May 2009 15:18:14 +0000
Subject: Add support for fast GPIO on lpc214x

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1766 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/arch/arm/src/lpc214x/chip.h         | 20 +++++++++++++++++++-
 nuttx/arch/arm/src/lpc214x/lpc214x_head.S | 12 ++++++++++++
 2 files changed, 31 insertions(+), 1 deletion(-)

(limited to 'nuttx/arch/arm')

diff --git a/nuttx/arch/arm/src/lpc214x/chip.h b/nuttx/arch/arm/src/lpc214x/chip.h
index 336889f4d..eba3fa52b 100644
--- a/nuttx/arch/arm/src/lpc214x/chip.h
+++ b/nuttx/arch/arm/src/lpc214x/chip.h
@@ -47,6 +47,7 @@
 /* Memory Map ***************************************************************************************/
 
 #define LPC214X_FLASH_BASE              0x00000000
+#define LPC214X_FIO_BASE                0x3fffc000
 #define LPC214X_ONCHIP_RAM_BASE         0x40000000
 #define LPC214X_USBDMA_RAM_BASE         0x7fd00000
 #define LPC214X_BOOT_BLOCK              0x7fffd000
@@ -56,7 +57,12 @@
 
 /* Peripheral Registers ****************************************************************************/
 
-/* Register block base addresses */
+/* FIO Register block base addresses */
+
+#define LPC214X_FIO0_BASE               0x3fffc000  /* Fast I/O 0 base address */
+#define LPC214X_FIO1_BASE               0x3fffc020  /* Fast I/O 1 base address */
+
+/* APB Register block base addresses */
 
 #define LPC214X_WD_BASE                 0xe0000000  /* Watchdog base address */
 #define LPC214X_TMR0_BASE               0xe0004000  /* Timer 0 base address*/
@@ -79,12 +85,15 @@
 
 #define LPC214X_SCB_BASE                0xe01fc000  /* System Control Block (SBC) base address */
 #define   LPC214X_MAM_BASE              0xe01fc000  /* Memory Accelerator Module (MAM) base address */
+#define   LPC214X_SCS                   0xe01fc1a0  /* System Control and Status flags (SCS) */
 #define   LPC214X_MEMMAP                0xe01fc040  /* Memory Mapping Control */
 #define   LPC214X_PLL_BASE              0xe01fc080  /* Phase Locked Loop (PLL) base address */
 #define   LPC214X_PCON_BASE             0xe01fc0c0  /* Power Control (PCON) base address */
 #define   LPC214X_APBDIV                0xe01fc100  /* APBDIV Address */
 #define   LPC214X_EXT_BASE              0xe01fc140  /* External Interrupt base address */       
 
+/* AHB Register block base addresses */
+
 #define LPC214X_EMC_BASE                0xffe00000  /* External Memory Controller (EMC) base address */
 #define LPC214X_VIC_BASE                0xfffff000  /* Vectored Interrupt Controller (VIC) Base */
 
@@ -169,6 +178,7 @@
 #define LPC214X_PINSEL2_OFFSET          0x14   /* Pin function select register 2 */
 
 /* Analog to Digital (AD) Converter registger offsets */
+
 #define LPC214X_AD_ADCR_OFFSET          0x00   /* A/D Control Register */
 #define LPC214X_AD_ADGDR_OFFSET         0x04   /* A/D Global Data Register (only one common register!) */
 #define LPC214X_AD_ADGSR_OFFSET         0x08   /* A/D Global Start Register */
@@ -240,6 +250,14 @@
 #define LPC214X_GPIO_DIR_OFFSET         0x08   /* Pin Direction Register */
 #define LPC214X_GPIO_CLR_OFFSET         0x0c   /* Pin Output Clear Register */
 
+/* FIO register offsets */
+
+#define LPC214X_FIO_DIR_OFFSET          0x00   /* Fast GPIO Port Direction Register */
+#define LPC214X_FIO_MASK_OFFSET         0x10   /* Fast GPIO Mask Register */
+#define LPC214X_FIO_PIN_OFFSET          0x14   /* Fast GPIO Pin Value Register */
+#define LPC214X_FIO_SET_OFFSET          0x18   /* Fast GPIO Port Output Set Register */
+#define LPC214X_FIO_CLR_OFFSET          0x1c   /* Fast GPIO Port Output Clear Register */
+
 /* Memory Accelerator Module (MAM) Regiser Offsets */
 
 #define LPC214X_MAM_CR_OFFSET           0x00   /* MAM Control Offset*/
diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_head.S b/nuttx/arch/arm/src/lpc214x/lpc214x_head.S
index b1fd603f7..58b852e60 100644
--- a/nuttx/arch/arm/src/lpc214x/lpc214x_head.S
+++ b/nuttx/arch/arm/src/lpc214x/lpc214x_head.S
@@ -433,6 +433,14 @@
 #endif
 	.endm
 
+	.macro configfastport, base, tmp
+#ifdef CONFIG_LPC214x_FIO
+	ldr	\base, =LPC214X_SCS
+	mov	\tmp, #0x03
+	str	\tmp,[\base]
+#endif
+	.endm
+
 /*****************************************************************************
  * Text
  *****************************************************************************/
@@ -534,6 +542,10 @@ __start:
 	
 	configdac	r0, r1
 
+	/* Configure Fast GPIO Port */
+
+	configfastport  r0, r1
+
 	/* Configure the uart so that we can get debug output as soon
 	 * as possible.  Modifies r0, r1, r2, and r14.
 	 */
-- 
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