From a113aa53d96d039d28e3e54ba79b2aae6a524ca5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 7 Nov 2008 16:28:17 +0000 Subject: Basic SCI support git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1152 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/sh/include/sh1/irq.h | 210 +++++++++++++++++++++------------------- 1 file changed, 108 insertions(+), 102 deletions(-) (limited to 'nuttx/arch/sh/include/sh1/irq.h') diff --git a/nuttx/arch/sh/include/sh1/irq.h b/nuttx/arch/sh/include/sh1/irq.h index dd3aa3435..fd738c8f0 100644 --- a/nuttx/arch/sh/include/sh1/irq.h +++ b/nuttx/arch/sh/include/sh1/irq.h @@ -55,68 +55,68 @@ /* Illegal instructions / Address errors */ -#define SH1_INVINSTR_IRQ (0) /* General invalid instruction */ -#define SH1_INVSLOT_IRQ (1) /* Invalid slot instruction */ -#define SH1_BUSERR_IRQ (2) /* CPU bus error */ -#define SH1_DMAERR_IRQ (3) /* DMA bus error */ -#define SH1_NMI_IRQ (4) /* NMI */ -#define SH1_USRBRK_IRQ (6) /* User break */ +#define SH1_INVINSTR_IRQ (0) /* General invalid instruction */ +#define SH1_INVSLOT_IRQ (1) /* Invalid slot instruction */ +#define SH1_BUSERR_IRQ (2) /* CPU bus error */ +#define SH1_DMAERR_IRQ (3) /* DMA bus error */ +#define SH1_NMI_IRQ (4) /* NMI */ +#define SH1_USRBRK_IRQ (6) /* User break */ /* Support for traps can be provided by simply enabling the following and * implementing the stubs to catch the interrupts */ #if 0 -# define SH1_TRAP_IRQ (7) /* TRAPA instruction (user break) */ -# define SH1_TRAP0_IRQ (SH1_TRAP_IRQ+0) /* TRAPA instruction (user break) */ -# define SH1_TRAP1_IRQ (SH1_TRAP_IRQ+1) /* " " " " " " " " */ -# define SH1_TRAP2_IRQ (SH1_TRAP_IRQ+2) /* " " " " " " " " */ -# define SH1_TRAP3_IRQ (SH1_TRAP_IRQ+3) /* " " " " " " " " */ -# define SH1_TRAP4_IRQ (SH1_TRAP_IRQ+4) /* " " " " " " " " */ -# define SH1_TRAP5_IRQ (SH1_TRAP_IRQ+5) /* " " " " " " " " */ -# define SH1_TRAP6_IRQ (SH1_TRAP_IRQ+6) /* " " " " " " " " */ -# define SH1_TRAP7_IRQ (SH1_TRAP_IRQ+7) /* " " " " " " " " */ -# define SH1_TRAP8_IRQ (SH1_TRAP_IRQ+8) /* " " " " " " " " */ -# define SH1_TRAP9_IRQ (SH1_TRAP_IRQ+9) /* " " " " " " " " */ -# define SH1_TRAP10_IRQ (SH1_TRAP_IRQ+10) /* " " " " " " " " */ -# define SH1_TRAP11_IRQ (SH1_TRAP_IRQ+11) /* " " " " " " " " */ -# define SH1_TRAP12_IRQ (SH1_TRAP_IRQ+12) /* " " " " " " " " */ -# define SH1_TRAP13_IRQ (SH1_TRAP_IRQ+13) /* " " " " " " " " */ -# define SH1_TRAP14_IRQ (SH1_TRAP_IRQ+14) /* " " " " " " " " */ -# define SH1_TRAP15_IRQ (SH1_TRAP_IRQ+15) /* " " " " " " " " */ -# define SH1_TRAP16_IRQ (SH1_TRAP_IRQ+16) /* " " " " " " " " */ -# define SH1_TRAP17_IRQ (SH1_TRAP_IRQ+17) /* " " " " " " " " */ -# define SH1_TRAP18_IRQ (SH1_TRAP_IRQ+18) /* " " " " " " " " */ -# define SH1_TRAP19_IRQ (SH1_TRAP_IRQ+19) /* " " " " " " " " */ -# define SH1_TRAP20_IRQ (SH1_TRAP_IRQ+20) /* " " " " " " " " */ -# define SH1_TRAP21_IRQ (SH1_TRAP_IRQ+21) /* " " " " " " " " */ -# define SH1_TRAP22_IRQ (SH1_TRAP_IRQ+22) /* " " " " " " " " */ -# define SH1_TRAP23_IRQ (SH1_TRAP_IRQ+23) /* " " " " " " " " */ -# define SH1_TRAP24_IRQ (SH1_TRAP_IRQ+24) /* " " " " " " " " */ -# define SH1_TRAP25_IRQ (SH1_TRAP_IRQ+25) /* " " " " " " " " */ -# define SH1_TRAP26_IRQ (SH1_TRAP_IRQ+26) /* " " " " " " " " */ -# define SH1_TRAP27_IRQ (SH1_TRAP_IRQ+27) /* " " " " " " " " */ -# define SH1_TRAP28_IRQ (SH1_TRAP_IRQ+28) /* " " " " " " " " */ -# define SH1_TRAP29_IRQ (SH1_TRAP_IRQ+29) /* " " " " " " " " */ -# define SH1_TRAP30_IRQ (SH1_TRAP_IRQ+30) /* " " " " " " " " */ -# define SH1_TRAP31_IRQ (SH1_TRAP_IRQ+31) /* " " " " " " " " */ -# define SH1_LASTTRAP_IRQ SH1_TRAP31_IRQ +# define SH1_TRAP_IRQ (7) /* TRAPA instruction (user break) */ +# define SH1_TRAP0_IRQ (SH1_TRAP_IRQ+0) /* TRAPA instruction (user break) */ +# define SH1_TRAP1_IRQ (SH1_TRAP_IRQ+1) /* " " " " " " " " */ +# define SH1_TRAP2_IRQ (SH1_TRAP_IRQ+2) /* " " " " " " " " */ +# define SH1_TRAP3_IRQ (SH1_TRAP_IRQ+3) /* " " " " " " " " */ +# define SH1_TRAP4_IRQ (SH1_TRAP_IRQ+4) /* " " " " " " " " */ +# define SH1_TRAP5_IRQ (SH1_TRAP_IRQ+5) /* " " " " " " " " */ +# define SH1_TRAP6_IRQ (SH1_TRAP_IRQ+6) /* " " " " " " " " */ +# define SH1_TRAP7_IRQ (SH1_TRAP_IRQ+7) /* " " " " " " " " */ +# define SH1_TRAP8_IRQ (SH1_TRAP_IRQ+8) /* " " " " " " " " */ +# define SH1_TRAP9_IRQ (SH1_TRAP_IRQ+9) /* " " " " " " " " */ +# define SH1_TRAP10_IRQ (SH1_TRAP_IRQ+10) /* " " " " " " " " */ +# define SH1_TRAP11_IRQ (SH1_TRAP_IRQ+11) /* " " " " " " " " */ +# define SH1_TRAP12_IRQ (SH1_TRAP_IRQ+12) /* " " " " " " " " */ +# define SH1_TRAP13_IRQ (SH1_TRAP_IRQ+13) /* " " " " " " " " */ +# define SH1_TRAP14_IRQ (SH1_TRAP_IRQ+14) /* " " " " " " " " */ +# define SH1_TRAP15_IRQ (SH1_TRAP_IRQ+15) /* " " " " " " " " */ +# define SH1_TRAP16_IRQ (SH1_TRAP_IRQ+16) /* " " " " " " " " */ +# define SH1_TRAP17_IRQ (SH1_TRAP_IRQ+17) /* " " " " " " " " */ +# define SH1_TRAP18_IRQ (SH1_TRAP_IRQ+18) /* " " " " " " " " */ +# define SH1_TRAP19_IRQ (SH1_TRAP_IRQ+19) /* " " " " " " " " */ +# define SH1_TRAP20_IRQ (SH1_TRAP_IRQ+20) /* " " " " " " " " */ +# define SH1_TRAP21_IRQ (SH1_TRAP_IRQ+21) /* " " " " " " " " */ +# define SH1_TRAP22_IRQ (SH1_TRAP_IRQ+22) /* " " " " " " " " */ +# define SH1_TRAP23_IRQ (SH1_TRAP_IRQ+23) /* " " " " " " " " */ +# define SH1_TRAP24_IRQ (SH1_TRAP_IRQ+24) /* " " " " " " " " */ +# define SH1_TRAP25_IRQ (SH1_TRAP_IRQ+25) /* " " " " " " " " */ +# define SH1_TRAP26_IRQ (SH1_TRAP_IRQ+26) /* " " " " " " " " */ +# define SH1_TRAP27_IRQ (SH1_TRAP_IRQ+27) /* " " " " " " " " */ +# define SH1_TRAP28_IRQ (SH1_TRAP_IRQ+28) /* " " " " " " " " */ +# define SH1_TRAP29_IRQ (SH1_TRAP_IRQ+29) /* " " " " " " " " */ +# define SH1_TRAP30_IRQ (SH1_TRAP_IRQ+30) /* " " " " " " " " */ +# define SH1_TRAP31_IRQ (SH1_TRAP_IRQ+31) /* " " " " " " " " */ +# define SH1_LASTTRAP_IRQ SH1_TRAP31_IRQ #else -# define SH1_LASTTRAP_IRQ (6) +# define SH1_LASTTRAP_IRQ (6) #endif /* Interrupts */ -#define SH1_IRQ_IRQ (SH1_LASTTRAP_IRQ+1) /* IRQ0-7 */ -#define SH1_IRQ0_IRQ (SH1_IRQ_IRQ+0) /* IRQ0 */ -#define SH1_IRQ1_IRQ (SH1_IRQ_IRQ+1) /* IRQ1 */ -#define SH1_IRQ2_IRQ (SH1_IRQ_IRQ+2) /* IRQ2 */ -#define SH1_IRQ3_IRQ (SH1_IRQ_IRQ+3) /* IRQ3 */ -#define SH1_IRQ4_IRQ (SH1_IRQ_IRQ+4) /* IRQ4 */ -#define SH1_IRQ5_IRQ (SH1_IRQ_IRQ+5) /* IRQ5 */ -#define SH1_IRQ6_IRQ (SH1_IRQ_IRQ+6) /* IRQ6 */ -#define SH1_IRQ7_IRQ (SH1_IRQ_IRQ+7) /* IRQ7 */ -#define SH1_LASTIRQ_IRQ SH1_IRQ7_IRQ +#define SH1_IRQ_IRQ (SH1_LASTTRAP_IRQ+1) /* IRQ0-7 */ +#define SH1_IRQ0_IRQ (SH1_IRQ_IRQ+0) /* IRQ0 */ +#define SH1_IRQ1_IRQ (SH1_IRQ_IRQ+1) /* IRQ1 */ +#define SH1_IRQ2_IRQ (SH1_IRQ_IRQ+2) /* IRQ2 */ +#define SH1_IRQ3_IRQ (SH1_IRQ_IRQ+3) /* IRQ3 */ +#define SH1_IRQ4_IRQ (SH1_IRQ_IRQ+4) /* IRQ4 */ +#define SH1_IRQ5_IRQ (SH1_IRQ_IRQ+5) /* IRQ5 */ +#define SH1_IRQ6_IRQ (SH1_IRQ_IRQ+6) /* IRQ6 */ +#define SH1_IRQ7_IRQ (SH1_IRQ_IRQ+7) /* IRQ7 */ +#define SH1_LASTIRQ_IRQ SH1_IRQ7_IRQ /* On-chip modules -- The following may be unique to the 7032 */ @@ -124,68 +124,74 @@ /* DMAC */ -#define SH1_DMAC0_IRQ (SH1_LASTIRQ_IRQ+1) /* DMAC0 */ -#define SH1_DEI0_IRQ SH1_DMAC0_IRQ /* DEI0 */ -#define SH1_DMAC1_IRQ (SH1_LASTIRQ_IRQ+2) /* DMAC1 */ -#define SH1_DEI1_IRQ SH1_DMAC1_IRQ /* DEI1 */ -#define SH1_DMAC2_IRQ (SH1_LASTIRQ_IRQ+3) /* DMAC2 */ -#define SH1_DEI2_IRQ SH1_DMAC2_IRQ /* DEI2 */ -#define SH1_DMAC3_IRQ (SH1_LASTIRQ_IRQ+4) /* DMAC3 */ -#define SH1_DEI3_IRQ SH1_DMAC3_IRQ /* DEI3 */ -#define SH1_LASTDMAC_IRQ SH1_DEI3_IRQ +#define SH1_DMAC0_IRQ (SH1_LASTIRQ_IRQ+1) /* DMAC0 */ +#define SH1_DEI0_IRQ SH1_DMAC0_IRQ /* DEI0 */ +#define SH1_DMAC1_IRQ (SH1_LASTIRQ_IRQ+2) /* DMAC1 */ +#define SH1_DEI1_IRQ SH1_DMAC1_IRQ /* DEI1 */ +#define SH1_DMAC2_IRQ (SH1_LASTIRQ_IRQ+3) /* DMAC2 */ +#define SH1_DEI2_IRQ SH1_DMAC2_IRQ /* DEI2 */ +#define SH1_DMAC3_IRQ (SH1_LASTIRQ_IRQ+4) /* DMAC3 */ +#define SH1_DEI3_IRQ SH1_DMAC3_IRQ /* DEI3 */ +#define SH1_LASTDMAC_IRQ SH1_DEI3_IRQ /* ITU */ -#define SH1_ITU0_IRQ (SH1_LASTDMAC_IRQ+1) /* ITU0 */ -#define SH1_IMIA0_IRQ (SH1_ITU0_IRQ+0) /* IMIA0 */ -#define SH1_IMIBO_IRQ (SH1_ITU0_IRQ+1) /* IMIB0 */ -#define SH1_OVI0_IRQ (SH1_ITU0_IRQ+2) /* OVI0 */ +#define SH1_ITU0_IRQ (SH1_LASTDMAC_IRQ+1) /* ITU0 */ +#define SH1_IMIA0_IRQ (SH1_ITU0_IRQ+0) /* IMIA0 */ +#define SH1_IMIBO_IRQ (SH1_ITU0_IRQ+1) /* IMIB0 */ +#define SH1_OVI0_IRQ (SH1_ITU0_IRQ+2) /* OVI0 */ -#define SH1_ITU1_IRQ (SH1_LASTDMAC_IRQ+4) /* ITU1 */ -#define SH1_IMIA1_IRQ (SH1_ITU1_IRQ+0) /* IMIA1 */ -#define SH1_IMIB1_IRQ (SH1_ITU1_IRQ+1) /* IMIB1 */ -#define SH1_OVI1_IRQ (SH1_ITU1_IRQ+2) /* OVI1 */ +#define SH1_ITU1_IRQ (SH1_LASTDMAC_IRQ+4) /* ITU1 */ +#define SH1_IMIA1_IRQ (SH1_ITU1_IRQ+0) /* IMIA1 */ +#define SH1_IMIB1_IRQ (SH1_ITU1_IRQ+1) /* IMIB1 */ +#define SH1_OVI1_IRQ (SH1_ITU1_IRQ+2) /* OVI1 */ -#define SH1_ITU2_IRQ (SH1_LASTDMAC_IRQ+7) /* ITU2 */ -#define SH1_IMIA2_IRQ (SH1_ITU2_IRQ+0) /* IMIA2 */ -#define SH1_IMIB2_IRQ (SH1_ITU2_IRQ+1) /* IMIB2 */ -#define SH1_OVI2_IRQ (SH1_ITU2_IRQ+2) /* OVI2 */ +#define SH1_ITU2_IRQ (SH1_LASTDMAC_IRQ+7) /* ITU2 */ +#define SH1_IMIA2_IRQ (SH1_ITU2_IRQ+0) /* IMIA2 */ +#define SH1_IMIB2_IRQ (SH1_ITU2_IRQ+1) /* IMIB2 */ +#define SH1_OVI2_IRQ (SH1_ITU2_IRQ+2) /* OVI2 */ -#define SH1_ITU3_IRQ (SH1_LASTDMAC_IRQ+10) /* ITU3 */ -#define SH1_IMIA3_IRQ (SH1_ITU3_IRQ+0) /* IMIA3 */ -#define SH1_IMIB3_IRQ (SH1_ITU3_IRQ+1) /* IMIB3 */ -#define SH1_OVI3_IRQ (SH1_ITU3_IRQ+2) /* OVI3 */ +#define SH1_ITU3_IRQ (SH1_LASTDMAC_IRQ+10) /* ITU3 */ +#define SH1_IMIA3_IRQ (SH1_ITU3_IRQ+0) /* IMIA3 */ +#define SH1_IMIB3_IRQ (SH1_ITU3_IRQ+1) /* IMIB3 */ +#define SH1_OVI3_IRQ (SH1_ITU3_IRQ+2) /* OVI3 */ -#define SH1_ITU4_IRQ (SH1_LASTDMAC_IRQ+13) /* ITU4 */ -#define SH1_IMIA4_IRQ (SH1_ITU4_IRQ+0) /* IMIA4 */ -#define SH1_IMIB4_IRQ (SH1_ITU4_IRQ+1) /* IMIB4 */ -#define SH1_OVI4_IRQ (SH1_ITU4_IRQ+2) /* OVI4 */ +#define SH1_ITU4_IRQ (SH1_LASTDMAC_IRQ+13) /* ITU4 */ +#define SH1_IMIA4_IRQ (SH1_ITU4_IRQ+0) /* IMIA4 */ +#define SH1_IMIB4_IRQ (SH1_ITU4_IRQ+1) /* IMIB4 */ +#define SH1_OVI4_IRQ (SH1_ITU4_IRQ+2) /* OVI4 */ -#define SH1_LASTITU_IRQ (SH1_LASTDMAC_IRQ+15) +#define SH1_LASTITU_IRQ (SH1_LASTDMAC_IRQ+15) /* SCI */ -#define SH1_SCI0_IRQ (SH1_LASTITU_IRQ+1) /* SCI0 */ -#define SH1_ERI0_IRQ (SH1_SCI0_IRQ+0) /* ERI0 */ -#define SH1_RXI0_IRQ (SH1_SCI0_IRQ+1) /* RxI0 */ -#define SH1_TXI0_IRQ (SH1_SCI0_IRQ+2) /* TxI0 */ -#define SH1_TEI0_IRQ (SH1_SCI0_IRQ+3) /* TEI0 */ - -#define SH1_SCI1_IRQ (SH1_LASTITU_IRQ+5) /* SCI1 */ -#define SH1_ERI1_IRQ (SH1_SCI1_IRQ+0) /* ERI1 */ -#define SH1_RXI1_IRQ (SH1_SCI1_IRQ+1) /* RxI1 */ -#define SH1_TXI1_IRQ (SH1_SCI1_IRQ+2) /* TxI1 */ -#define SH1_TEI1_IRQ (SH1_SCI1_IRQ+3) /* TEI1 */ - -#define SH1_LASTSCI_IRQ (SH1_LASTITU_IRQ+9) - -#define SH1_PEI_IRQ (SH1_LASTSCI_IRQ+1) /* Parity control unit PEI */ -#define SH1_ADITI_IRQ (SH1_LASTSCI_IRQ+2) /* A/D ITI */ -#define SH1_WDTITI_IRQ (SH1_LASTSCI_IRQ+3) /* WDT ITI */ -#define SH1_CMI_IRQ (SH1_LASTSCI_IRQ+4) /* REF CMI */ - -#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI -#define NR_IRQS (SH1_CMI_IRQ+1) +#define SH1_ERI_IRQ_OFFSET (0) /* ERI0 */ +#define SH1_RXI_IRQ_OFFSET (1) /* RxI0 */ +#define SH1_TXI_IRQ_OFFSET (2) /* TxI0 */ +#define SH1_TEI_IRQ_OFFSET (3) /* TEI0 */ +#define SH1_SCI_NIRQS (4) + +#define SH1_SCI0_IRQ (SH1_LASTITU_IRQ+1) /* SCI0 */ +#define SH1_ERI0_IRQ (SH1_SCI0_IRQ+SH1_ERI_IRQ_OFFSET) /* ERI0 */ +#define SH1_RXI0_IRQ (SH1_SCI0_IRQ+SH1_RXI_IRQ_OFFSET) /* RxI0 */ +#define SH1_TXI0_IRQ (SH1_SCI0_IRQ+SH1_TXI_IRQ_OFFSET) /* TxI0 */ +#define SH1_TEI0_IRQ (SH1_SCI0_IRQ+SH1_TEI_IRQ_OFFSET) /* TEI0 */ + +#define SH1_SCI1_IRQ (SH1_SCI0_IRQ+SH1_SCI_NIRQS) /* SCI1 */ +#define SH1_ERI1_IRQ (SH1_SCI1_IRQ+SH1_ERI_IRQ_OFFSET) /* ERI1 */ +#define SH1_RXI1_IRQ (SH1_SCI1_IRQ+SH1_RXI_IRQ_OFFSET) /* RxI1 */ +#define SH1_TXI1_IRQ (SH1_SCI1_IRQ+SH1_TXI_IRQ_OFFSET) /* TxI1 */ +#define SH1_TEI1_IRQ (SH1_SCI1_IRQ+SH1_TEI_IRQ_OFFSET) /* TEI1 */ + +#define SH1_LASTSCI_IRQ (SH1_SCI1_IRQ+SH1_SCI_NIRQS) + +#define SH1_PEI_IRQ (SH1_LASTSCI_IRQ+1) /* Parity control unit PEI */ +#define SH1_ADITI_IRQ (SH1_LASTSCI_IRQ+2) /* A/D ITI */ +#define SH1_WDTITI_IRQ (SH1_LASTSCI_IRQ+3) /* WDT ITI */ +#define SH1_CMI_IRQ (SH1_LASTSCI_IRQ+4) /* REF CMI */ + +#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI +#define NR_IRQS (SH1_CMI_IRQ+1) #endif -- cgit v1.2.3