From 45474d6e667a62ce96979008613e3b2fd5c713e0 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 8 Apr 2011 01:33:21 +0000 Subject: Modify interrupt handling for privileged/unprivileged mode git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3480 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/cortexm3/irq.h | 59 +++++++++-------- nuttx/arch/arm/src/arm/up_initialstate.c | 2 +- nuttx/arch/arm/src/cortexm3/exc_return.h | 90 ++++++++++++++++++++++++++ nuttx/arch/arm/src/cortexm3/up_initialstate.c | 24 +++++++ nuttx/arch/arm/src/lm3s/lm3s_vectors.S | 61 +++++++++++++++--- nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S | 93 ++++++++++++++++++++------- nuttx/arch/arm/src/sam3u/sam3u_vectors.S | 63 +++++++++++++++--- nuttx/arch/arm/src/stm32/stm32_vectors.S | 61 +++++++++++++++--- 8 files changed, 373 insertions(+), 80 deletions(-) create mode 100644 nuttx/arch/arm/src/cortexm3/exc_return.h (limited to 'nuttx/arch') diff --git a/nuttx/arch/arm/include/cortexm3/irq.h b/nuttx/arch/arm/include/cortexm3/irq.h index 063568655..ff7134e5b 100644 --- a/nuttx/arch/arm/include/cortexm3/irq.h +++ b/nuttx/arch/arm/include/cortexm3/irq.h @@ -55,43 +55,50 @@ /* IRQ Stack Frame Format: */ +/* The following additional registers are stored by the interrupt handling + * logic. + */ + +#define REG_R13 (0) /* R13 = SP at time of interrupt */ +#define REG_PRIMASK (1) /* PRIMASK */ +#define REG_R4 (2) /* R4 */ +#define REG_R5 (3) /* R5 */ +#define REG_R6 (4) /* R6 */ +#define REG_R7 (5) /* R7 */ +#define REG_R8 (6) /* R8 */ +#define REG_R9 (7) /* R9 */ +#define REG_R10 (8) /* R10 */ +#define REG_R11 (9) /* R11 */ + +#ifdef CONFIG_NUTTX_KERNEL +# define REG_EXC_RETURN (10) /* EXC_RETURN */ +# define SW_XCPT_REGS (11) +#else +# define SW_XCPT_REGS (10) +#endif +#define SW_XCPT_SIZE (4 * SW_XCPT_REGS) + /* On entry into an IRQ, the hardware automatically saves the following * registers on the stack in this (address) order: */ -#define REG_XPSR (17) /* xPSR */ -#define REG_R15 (16) /* R15 = PC */ -#define REG_R14 (15) /* R14 = LR */ -#define REG_R12 (14) /* R12 */ -#define REG_R3 (13) /* R3 */ -#define REG_R2 (12) /* R2 */ -#define REG_R1 (11) /* R1 */ -#define REG_R0 (10) /* R0 */ +#define REG_R0 (SW_XCPT_REGS+0) /* R0 */ +#define REG_R1 (SW_XCPT_REGS+1) /* R1 */ +#define REG_R2 (SW_XCPT_REGS+2) /* R2 */ +#define REG_R3 (SW_XCPT_REGS+3) /* R3 */ +#define REG_R12 (SW_XCPT_REGS+4) /* R12 */ +#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */ +#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */ +#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */ #define HW_XCPT_REGS (8) #define HW_XCPT_SIZE (4 * HW_XCPT_REGS) -/* The following additional registers are stored by the interrupt handling - * logic. - */ - -#define REG_R11 (9) /* R11 */ -#define REG_R10 (8) /* R10 */ -#define REG_R9 (7) /* R9 */ -#define REG_R8 (6) /* R8 */ -#define REG_R7 (5) /* R7 */ -#define REG_R6 (4) /* R6 */ -#define REG_R5 (3) /* R5 */ -#define REG_R4 (2) /* R4 */ -#define REG_PRIMASK (1) /* PRIMASK */ -#define REG_R13 (0) /* R13 = SP at time of interrupt */ - -#define SW_XCPT_REGS (10) -#define SW_XCPT_SIZE (4 * SW_XCPT_REGS) - #define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS) #define XCPTCONTEXT_SIZE (HW_XCPT_SIZE + SW_XCPT_SIZE) +/* Alternate register names */ + #define REG_A1 REG_R0 #define REG_A2 REG_R1 #define REG_A3 REG_R2 diff --git a/nuttx/arch/arm/src/arm/up_initialstate.c b/nuttx/arch/arm/src/arm/up_initialstate.c index 570a11459..4711c9f44 100644 --- a/nuttx/arch/arm/src/arm/up_initialstate.c +++ b/nuttx/arch/arm/src/arm/up_initialstate.c @@ -110,7 +110,7 @@ void up_initial_state(_TCB *tcb) } #endif - /* Set supervisor- or user-mode, depending on how NuttX is configured nd + /* Set supervisor- or user-mode, depending on how NuttX is configured and * what kind of thread is being started. Disable FIQs in any event */ diff --git a/nuttx/arch/arm/src/cortexm3/exc_return.h b/nuttx/arch/arm/src/cortexm3/exc_return.h new file mode 100644 index 000000000..06c0e723f --- /dev/null +++ b/nuttx/arch/arm/src/cortexm3/exc_return.h @@ -0,0 +1,90 @@ +/************************************************************************************ + * arch/arm/src/cortexm3/exc_return.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM_EXC_RETURN_H +#define __ARCH_ARM_SRC_COMMON_CORTEXM_EXC_RETURN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* The processor saves an EXC_RETURN value to the LR on exception entry. The + * exception mechanism relies on this value to detect when the processor has + * completed an exception handler. Bits[31:4] of an EXC_RETURN value are + * 0xfffffffX. When the processor loads a value matching this pattern to the + * PC it detects that the operation is a not a normal branch operation and, + * instead, that the exception is complete. Therefore, it starts the exception + * return sequence. Bits[3:0] of the EXC_RETURN value indicate the required + * return stack and processor mode: + */ + +/* EXC_RETURN_HANDLER: Return to handler mode. Exception return gets state from + * the main stack. Execution uses MSP after return. + */ + +#define EXC_RETURN_HANDLER 0xfffffff1 + +/* EXC_RETURN_PRIVTHR: Return to privileged thread mode. Exception return gets + * state from the main stack. Execution uses MSP after return. + */ + +#define EXC_RETURN_PRIVTHR 0xfffffff9 + +/* EXC_RETURN_UNPRIVTHR: Return to unprivileged thread mode. Exception return gets + * state from the process stack. Execution uses PSP after return. + */ + +#define EXC_RETURN_UNPRIVTHR 0xfffffffd + +/* In the kernel build is not selected, then all threads run in privileged thread + * mode. + */ + +#ifdef CONFIG_NUTTX_KERNEL +# define EXC_RETURN 0xfffffff9 +#endif + +/************************Th************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM_EXC_RETURN_H */ + diff --git a/nuttx/arch/arm/src/cortexm3/up_initialstate.c b/nuttx/arch/arm/src/cortexm3/up_initialstate.c index 40f98bf8c..094a3adba 100644 --- a/nuttx/arch/arm/src/cortexm3/up_initialstate.c +++ b/nuttx/arch/arm/src/cortexm3/up_initialstate.c @@ -47,7 +47,9 @@ #include "up_internal.h" #include "up_arch.h" + #include "psr.h" +#include "exc_return.h" /**************************************************************************** * Pre-processor Definitions @@ -124,6 +126,28 @@ void up_initial_state(_TCB *tcb) #endif #endif + /* Set privileged- or unprivileged-mode, depending on how NuttX is + * configured and what kind of thread is being started. + * + * If the kernel build is not selected, then all threads run in + * privileged thread mode. + */ + +#ifdef CONFIG_NUTTX_KERNEL + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL) + { + /* It is a kernel thread.. set privileged thread mode */ + + xcp->regs[REG_EXC_RETURN] = EXC_RETURN_PRIVTHR; + } + else + { + /* It is a normal task or a pthread. Set user mode */ + + xcp->regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; + } +#endif + /* Enable or disable interrupts, based on user configuration */ # ifdef CONFIG_SUPPRESS_INTERRUPTS diff --git a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S index 6fece8d3b..90f2850af 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S +++ b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S @@ -546,7 +546,8 @@ handlers: # error "Vectors not specified for this LM3S chip" #endif -/* Common IRQ handling logic. On entry here, the stack is like the following: +/* Common IRQ handling logic. On entry here, the return stack is on either + * the PSP or the MSP and looks like the following: * * REG_XPSR * REG_R15 @@ -557,18 +558,38 @@ handlers: * REG_R1 * MSP->REG_R0 * - * and R0 contains the IRQ number + * And + * R0 contains the IRQ number + * R14 Contains the EXC_RETURN value + * We are in handler mode and the current SP is the MSP */ lm3s_irqcommon: /* Complete the context save */ +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ + ite ne /* Next two instructions are condition */ + mrsne r1, msp /* R1=The main stack pointer */ + mrseq r1, psp /* R1=The process stack pointer */ +#else mrs r1, msp /* R1=The main stack pointer */ - mov r2, r1 /* R2=Copy of the main stack pointer */ - add r2, #HW_XCPT_SIZE /* R2=MSP before the interrupt was taken */ +#endif + + mov r2, r1 /* R2=Copy of the main/process stack pointer */ + add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ mrs r3, primask /* R3=Current PRIMASK setting */ +#ifdef CONFIG_NUTTX_KERNEL + stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ +#else stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ +#endif /* Disable interrupts, select the stack to use for interrupt handling * and call up_doirq to handle the interrupt @@ -581,7 +602,7 @@ lm3s_irqcommon: * Otherwise, we will re-use the main stack for interrupt level processing. */ -#ifdef CONFIG_ARCH_INTERRUPTSTACK +#if CONFIG_ARCH_INTERRUPTSTACK > 3 ldr sp, =g_intstackbase str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ bl up_doirq /* R0=IRQ, R1=register save (msp) */ @@ -610,23 +631,45 @@ lm3s_irqcommon: ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif b 2f /* Re-join common logic */ /* We are returning with no context switch. We simply need to "unwind" * the same stack frame that we created */ 1: - ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif 2: +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ + ite ne /* Next two instructions are condition */ + msrne msp, r1 /* R1=The main stack pointer */ + msreq psp, r1 /* R1=The process stack pointer */ +#else msr msp, r1 /* Recover the return MSP value */ - /* Restore the interrupt state. Preload r14 with the special return - * value first (so that the return actually occurs with interrupts - * still disabled). + /* Preload r14 with the special return value first (so that the return + * actually occurs with interrupts still disabled). */ ldr r14, =EXC_RETURN /* Load the special value */ +#endif + + /* Restore the interrupt state */ + msr primask, r3 /* Restore interrupts */ /* Always return with R14 containing the special value that will: (1) diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S index 7a25c5610..4cfa9a3ce 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S @@ -220,7 +220,8 @@ handlers: HANDLER lpc17_usbact, LPC17_IRQ_USBACT /* Vector 16+33: USB Activity Interrupt */ HANDLER lpc17_canact, LPC17_IRQ_CANACT /* Vector 16+34: CAN Activity Interrupt */ -/* Common IRQ handling logic. On entry here, the stack is like the following: +/* Common IRQ handling logic. On entry here, the return stack is on either + * the PSP or the MSP and looks like the following: * * REG_XPSR * REG_R15 @@ -231,18 +232,38 @@ handlers: * REG_R1 * MSP->REG_R0 * - * and R0 contains the IRQ number + * And + * R0 contains the IRQ number + * R14 Contains the EXC_RETURN value + * We are in handler mode and the current SP is the MSP */ lpc17_common: /* Complete the context save */ +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ + ite ne /* Next two instructions are condition */ + mrsne r1, msp /* R1=The main stack pointer */ + mrseq r1, psp /* R1=The process stack pointer */ +#else mrs r1, msp /* R1=The main stack pointer */ - mov r2, r1 /* R2=Copy of the main stack pointer */ - add r2, #HW_XCPT_SIZE /* R2=MSP before the interrupt was taken */ +#endif + + mov r2, r1 /* R2=Copy of the main/process stack pointer */ + add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ mrs r3, primask /* R3=Current PRIMASK setting */ +#ifdef CONFIG_NUTTX_KERNEL + stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ +#else stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ +#endif /* Disable interrupts, select the stack to use for interrupt handling * and call up_doirq to handle the interrupt @@ -257,13 +278,13 @@ lpc17_common: #if CONFIG_ARCH_INTERRUPTSTACK > 3 ldr sp, =g_intstackbase - str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ - bl up_doirq /* R0=IRQ, R1=register save (msp) */ - ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */ + str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ + bl up_doirq /* R0=IRQ, R1=register save (msp) */ + ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */ #else - mov sp, r1 /* We are using the main stack pointer */ - bl up_doirq /* R0=IRQ, R1=register save (msp) */ - mov r1, sp /* Recover R1=main stack pointer */ + mov sp, r1 /* We are using the main stack pointer */ + bl up_doirq /* R0=IRQ, R1=register save (msp) */ + mov r1, sp /* Recover R1=main stack pointer */ #endif /* On return from up_doirq, R0 will hold a pointer to register context @@ -271,8 +292,8 @@ lpc17_common: * as current stack pointer, then things are relatively easy. */ - cmp r0, r1 /* Context switch? */ - beq 1f /* Branch if no context switch */ + cmp r0, r1 /* Context switch? */ + beq 1f /* Branch if no context switch */ /* We are returning with a pending context switch. This case is different * because in this case, the register save structure does not lie on the @@ -280,34 +301,56 @@ lpc17_common: * values to the stack. */ - add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */ - ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ + add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */ + ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ - stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ - ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ - b 2f /* Re-join common logic */ + stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif + b 2f /* Re-join common logic */ /* We are returning with no context switch. We simply need to "unwind" * the same stack frame that we created */ 1: - ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif 2: - msr msp, r1 /* Recover the return MSP value */ +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ + ite ne /* Next two instructions are condition */ + msrne msp, r1 /* R1=The main stack pointer */ + msreq psp, r1 /* R1=The process stack pointer */ +#else + msr msp, r1 /* Recover the return MSP value */ - /* Restore the interrupt state. Preload r14 with the special return - * value first (so that the return actually occurs with interrupts - * still disabled). + /* Preload r14 with the special return value first (so that the return + * actually occurs with interrupts still disabled). */ - ldr r14, =EXC_RETURN /* Load the special value */ - msr primask, r3 /* Restore interrupts */ + ldr r14, =EXC_RETURN /* Load the special value */ +#endif + + /* Restore the interrupt state */ + + msr primask, r3 /* Restore interrupts */ /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) continue to use the MSP */ - bx r14 /* And return */ + bx r14 /* And return */ .size handlers, .-handlers /************************************************************************************************ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S b/nuttx/arch/arm/src/sam3u/sam3u_vectors.S index d03593297..c4ab12ba0 100755 --- a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S +++ b/nuttx/arch/arm/src/sam3u/sam3u_vectors.S @@ -211,7 +211,8 @@ handlers: HANDLER sam3u_dmac, SAM3U_IRQ_DMAC /* Vector 16+28: DMA Controller */ HANDLER sam3u_udphs, SAM3U_IRQ_UDPHS /* Vector 16+29: USB Device High Speed */ -/* Common IRQ handling logic. On entry here, the stack is like the following: +/* Common IRQ handling logic. On entry here, the return stack is on either + * the PSP or the MSP and looks like the following: * * REG_XPSR * REG_R15 @@ -222,18 +223,38 @@ handlers: * REG_R1 * MSP->REG_R0 * - * and R0 contains the IRQ number + * And + * R0 contains the IRQ number + * R14 Contains the EXC_RETURN value + * We are in handler mode and the current SP is the MSP */ sam3u_common: /* Complete the context save */ +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ + ite ne /* Next two instructions are condition */ + mrsne r1, msp /* R1=The main stack pointer */ + mrseq r1, psp /* R1=The process stack pointer */ +#else mrs r1, msp /* R1=The main stack pointer */ - mov r2, r1 /* R2=Copy of the main stack pointer */ - add r2, #HW_XCPT_SIZE /* R2=MSP before the interrupt was taken */ +#endif + + mov r2, r1 /* R2=Copy of the main/process stack pointer */ + add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ mrs r3, primask /* R3=Current PRIMASK setting */ +#ifdef CONFIG_NUTTX_KERNEL + stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ +#else stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ +#endif /* Disable interrupts, select the stack to use for interrupt handling * and call up_doirq to handle the interrupt @@ -246,7 +267,7 @@ sam3u_common: * Otherwise, we will re-use the main stack for interrupt level processing. */ -#ifdef CONFIG_ARCH_INTERRUPTSTACK +#if CONFIG_ARCH_INTERRUPTSTACK > 3 ldr sp, =g_intstackbase str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ bl up_doirq /* R0=IRQ, R1=register save (msp) */ @@ -275,23 +296,45 @@ sam3u_common: ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif b 2f /* Re-join common logic */ /* We are returning with no context switch. We simply need to "unwind" * the same stack frame that we created */ 1: - ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif 2: - msr msp, r1 /* Recover the return MSP value */ +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ - /* Restore the interrupt state. Preload r14 with the special return - * value first (so that the return actually occurs with interrupts - * still disabled). + adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ + ite ne /* Next two instructions are condition */ + msrne msp, r1 /* R1=The main stack pointer */ + msreq psp, r1 /* R1=The process stack pointer */ +#else + msr msp, r1 /* Recover the return MSP value */ + + /* Preload r14 with the special return value first (so that the return + * actually occurs with interrupts still disabled). */ ldr r14, =EXC_RETURN /* Load the special value */ +#endif + + /* Restore the interrupt state */ + msr primask, r3 /* Restore interrupts */ /* Always return with R14 containing the special value that will: (1) diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S index 987982dec..908dc5b44 100644 --- a/nuttx/arch/arm/src/stm32/stm32_vectors.S +++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S @@ -403,7 +403,8 @@ handlers: HANDLER stm32_dma2ch45, STM32_IRQ_DMA2CH45 /* Vector 16+59: DMA2 Channel 4&5 global interrupt */ #endif -/* Common IRQ handling logic. On entry here, the stack is like the following: +/* Common IRQ handling logic. On entry here, the return stack is on either + * the PSP or the MSP and looks like the following: * * REG_XPSR * REG_R15 @@ -414,18 +415,38 @@ handlers: * REG_R1 * MSP->REG_R0 * - * and R0 contains the IRQ number + * And + * R0 contains the IRQ number + * R14 Contains the EXC_RETURN value + * We are in handler mode and the current SP is the MSP */ stm32_common: /* Complete the context save */ +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ + ite ne /* Next two instructions are condition */ + mrsne r1, msp /* R1=The main stack pointer */ + mrseq r1, psp /* R1=The process stack pointer */ +#else mrs r1, msp /* R1=The main stack pointer */ - mov r2, r1 /* R2=Copy of the main stack pointer */ - add r2, #HW_XCPT_SIZE /* R2=MSP before the interrupt was taken */ +#endif + + mov r2, r1 /* R2=Copy of the main/process stack pointer */ + add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ mrs r3, primask /* R3=Current PRIMASK setting */ +#ifdef CONFIG_NUTTX_KERNEL + stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ +#else stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ +#endif /* Disable interrupts, select the stack to use for interrupt handling * and call up_doirq to handle the interrupt @@ -438,7 +459,7 @@ stm32_common: * Otherwise, we will re-use the main stack for interrupt level processing. */ -#ifdef CONFIG_ARCH_INTERRUPTSTACK +#if CONFIG_ARCH_INTERRUPTSTACK > 3 ldr sp, =g_intstackbase str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ bl up_doirq /* R0=IRQ, R1=register save (msp) */ @@ -467,23 +488,45 @@ stm32_common: ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif b 2f /* Re-join common logic */ /* We are returning with no context switch. We simply need to "unwind" * the same stack frame that we created */ 1: - ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif 2: +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ + ite ne /* Next two instructions are condition */ + msrne msp, r1 /* R1=The main stack pointer */ + msreq psp, r1 /* R1=The process stack pointer */ +#else msr msp, r1 /* Recover the return MSP value */ - /* Restore the interrupt state. Preload r14 with the special return - * value first (so that the return actually occurs with interrupts - * still disabled). + /* Preload r14 with the special return value first (so that the return + * actually occurs with interrupts still disabled). */ ldr r14, =EXC_RETURN /* Load the special value */ +#endif + + /* Restore the interrupt state */ + msr primask, r3 /* Restore interrupts */ /* Always return with R14 containing the special value that will: (1) -- cgit v1.2.3