From 4701309f2cc828598885175e7d61ffc8d4edf043 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 16 Mar 2010 00:53:32 +0000 Subject: Bugfixes submitted by David Hewson git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2543 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/lpc313x/irq.h | 4 ++-- nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h | 12 +++++++----- nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h | 4 ++-- nuttx/arch/arm/src/lpc313x/lpc313x_clkfreq.c | 8 ++++---- nuttx/arch/arm/src/lpc313x/lpc313x_fdcndx.c | 4 ++-- nuttx/arch/arm/src/lpc313x/lpc313x_intc.h | 8 ++++---- nuttx/arch/arm/src/lpc313x/lpc313x_irq.c | 12 ++++++------ nuttx/arch/arm/src/lpc313x/lpc313x_pllconfig.c | 4 ++-- nuttx/arch/arm/src/lpc313x/lpc313x_setfdiv.c | 4 ++-- nuttx/arch/arm/src/lpc313x/lpc313x_setfreqin.c | 4 ++-- 10 files changed, 33 insertions(+), 31 deletions(-) (limited to 'nuttx/arch') diff --git a/nuttx/arch/arm/include/lpc313x/irq.h b/nuttx/arch/arm/include/lpc313x/irq.h index c2945ba25..d3879e1d2 100755 --- a/nuttx/arch/arm/include/lpc313x/irq.h +++ b/nuttx/arch/arm/include/lpc313x/irq.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/include/lpc313x/irq.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -59,7 +59,7 @@ #define LPC313X_IRQ_TMR1 5 /* IRQ6: Timer 1 Interrupt */ #define LPC313X_IRQ_TMR2 6 /* IRQ7: Timer 2 Interrupt */ #define LPC313X_IRQ_TMR3 7 /* IRQ8: Timer 3 Interrupt */ -#define LPC313X_IRQ_TMR3 8 /* IRQ9: ADC 10-bit */ +#define LPC313X_IRQ_ADC 8 /* IRQ9: ADC 10-bit */ #define LPC313X_IRQ_UART 9 /* IRQ10: UART */ #define LPC313X_IRQ_I2C0 10 /* IRQ11: I2C0 */ #define LPC313X_IRQ_I2C1 11 /* IRQ12: I2C1 */ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h b/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h index 3e6b7ffa8..18f756572 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h @@ -1,7 +1,7 @@ /************************************************************************************************ * arch/arm/src/lpc313x/lpc313x_cgu.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -1223,17 +1223,19 @@ /* Fractional divider register 0 to 23 FDC0 to FDC23 (except FDC17) addresses 0x13004518 to 0x13004574 */ #define CGU_FDC_MSUB_SHIFT (11) /* Bits 11-18: Modulo subtraction value */ -#define CGU_FDC_MSUB_MASK (255 << CGU_FDC_MSUB_SHIFT) +#define CGU_FDC_MSUB_MASK (0x000000ff << CGU_FDC_MSUB_SHIFT) +#define CGU_FDC_MSUB_EXTEND (0xffffff00) #define CGU_FDC_MADD_SHIFT (3) /* Bits 3-10: Modulo addition value */ -#define CGU_FDC_MADD_MASK (255 << CGU_FDC_MADD_SHIFT) +#define CGU_FDC_MADD_MASK (0x000000ff << CGU_FDC_MADD_SHIFT) #define CGU_FDC_STRETCH (1 << 2) /* Bit 2: Enables the stretching option */ #define CGU_FDC_RESET (1 << 1) /* Bit 1: Reset fractional divider */ #define CGU_FDC_RUN (1 << 0) /* Bit 0: Enable fractional divider */ #define CGU_FDC17_MSUB_SHIFT (16) /* Bits 16-28: Modulo subtraction value */ -#define CGU_FDC17_MSUB_MASK (0x1fff << CGU_FDC17_MSUB_SHIFT) +#define CGU_FDC17_MSUB_MASK (0x00001fff << CGU_FDC17_MSUB_SHIFT) +#define CGU_FDC17_MSUB_EXTEND (0xffffe000) #define CGU_FDC17_MADD_SHIFT (3) /* Bits 3-15: Modulo addition value */ -#define CGU_FDC17_MADD_MASK (0x1fff << CGU_FDC17_MADD_SHIFT) +#define CGU_FDC17_MADD_MASK (0x00001fff << CGU_FDC17_MADD_SHIFT) #define CGU_FDC17_STRETCH (1 << 2) /* Bit 2: Enables the stretching option */ #define CGU_FDC17_RESET (1 << 1) /* Bit 1: Reset fractional divider */ #define CGU_FDC17_RUN (1 << 0) /* Bit 0: Enable fractional divider */ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h b/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h index 7cdceb0b2..8addcc67f 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h @@ -1,7 +1,7 @@ /************************************************************************ * arch/arm/src/lpc313x/lpc313x_cgudrvr.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -561,7 +561,7 @@ static inline uint32_t lpc313x_getbasefreq(enum lpc313x_domainid_e dmnid) /* Fetch the SSR register associated with this clock domain */ - regval = getreg32(LPC313X_CGU_SSR_OFFSET((int)dmnid)); + regval = getreg32(LPC313X_CGU_SSR((int)dmnid)); /* Extract the last frequency input selection */ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_clkfreq.c b/nuttx/arch/arm/src/lpc313x/lpc313x_clkfreq.c index 17252c9ca..b2cb0361f 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_clkfreq.c +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_clkfreq.c @@ -1,7 +1,7 @@ /************************************************************************ * arch/arm/src/lpc313x/lpc313x_clkfreq.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -100,7 +100,7 @@ uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid, * it is enabled (not necessary since lpc313x_fdcndx() also does this check */ - regval = getreg32(LPC313X_CGU_FDC_OFFSET(fdcndx)); + regval = getreg32(LPC313X_CGU_FDC(fdcndx)); if ((regval & CGU_ESR_ESREN) != 0) { int32_t msub; @@ -117,14 +117,14 @@ uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid, { /* Range is 0-0x1fff for both */ - msub = (regval & CGU_FDC17_MSUB_MASK) >> CGU_FDC17_MSUB_SHIFT; + msub = ((regval & CGU_FDC17_MSUB_MASK) >> CGU_FDC17_MSUB_SHIFT) | CGU_FDC17_MSUB_EXTEND; madd = (regval & CGU_FDC17_MADD_MASK) >> CGU_FDC17_MADD_SHIFT; } else { /* Range is 0-255 for both */ - msub = (regval & CGU_FDC_MSUB_MASK) >> CGU_FDC_MSUB_SHIFT; + msub = ((regval & CGU_FDC_MSUB_MASK) >> CGU_FDC_MSUB_SHIFT) | CGU_FDC_MSUB_EXTEND; madd = (regval & CGU_FDC_MADD_MASK) >> CGU_FDC_MADD_SHIFT; } diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_fdcndx.c b/nuttx/arch/arm/src/lpc313x/lpc313x_fdcndx.c index 128f321db..dc66405d5 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_fdcndx.c +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_fdcndx.c @@ -1,7 +1,7 @@ /************************************************************************ * arch/arm/src/lpc313x/lpc313x_fdcndx.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -109,7 +109,7 @@ int lpc313x_fdcndx(enum lpc313x_clockid_e clkid, enum lpc313x_domainid_e dmnid) { /* Read the clock's ESR to get the fractional divider */ - uint32_t regval = getreg32(LPC313X_CGU_ESR_OFFSET(esrndx)); + uint32_t regval = getreg32(LPC313X_CGU_ESR(esrndx)); /* Check if any fractional divider is enabled for this clock. */ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_intc.h b/nuttx/arch/arm/src/lpc313x/lpc313x_intc.h index 434d61356..301272945 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_intc.h +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_intc.h @@ -1,7 +1,7 @@ /************************************************************************************************ * arch/arm/src/lpc313x/lpc313x_intc.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -177,11 +177,11 @@ #define INTC_REQUEST_ENABLE (1 << 16) /* Bit 16: Enable interrupt request */ #define INTC_REQUEST_TARGET_SHIFT (8) /* Bits 8-13: Interrupt target */ #define INTC_REQUEST_TARGET_MASK (63 << INTC_REQUEST_TARGET_SHIFT) -# define INTC_REQUEST_TARGET_IRQ (0 << INTC_REQUEST_TARGET_SHIFT) /* Proc interrupt request 0: IRQ */ -# define INTC_REQUEST_TARGET_FIQ (1 << INTC_REQUEST_TARGET_SHIFT) /* Proc interrupt request 1: FIQ */ +# define INTC_REQUEST_TARGET_IRQ (INTC_REQUEST_WETARGET | (0 << INTC_REQUEST_TARGET_SHIFT)) /* Proc interrupt request 0: IRQ */ +# define INTC_REQUEST_TARGET_FIQ (INTC_REQUEST_WETARGET | (1 << INTC_REQUEST_TARGET_SHIFT)) /* Proc interrupt request 1: FIQ */ #define INTC_REQUEST_PRIOLEVEL_SHIFT (0) /* Bits 0-7: Priority level */ #define INTC_REQUEST_PRIOLEVEL_MASK (255 << INTC_REQUEST_PRIOLEVEL_SHIFT) -# define INTC_REQUEST_PRIOLEVEL(n) (((n) << INTC_REQUEST_TARGET_SHIFT) & INTC_REQUEST_PRIOLEVEL_MASK) +# define INTC_REQUEST_PRIOLEVEL(n) (((n) << INTC_REQUEST_PRIOLEVEL_SHIFT) & INTC_REQUEST_PRIOLEVEL_MASK) /************************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_irq.c b/nuttx/arch/arm/src/lpc313x/lpc313x_irq.c index 6f6b23b56..35ef3e89e 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_irq.c +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc313x/lpc313x_irq.c * arch/arm/src/chip/lpc313x_irq.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -105,13 +105,13 @@ void up_irqinitialize(void) /* Disable all interrupts. Start from index 1 since 0 is unused.*/ - for (irq = 1; irq <= NR_IRQS; irq++) + for (irq = 0; irq < NR_IRQS; irq++) { /* Initialize as high-active, disable the interrupt, set target to IRQ, * Set priority level to 1 (= lowest) for all the interrupt lines */ - uint32_t address = LPC313X_INTC_REQUEST(irq); + uint32_t address = LPC313X_INTC_REQUEST(irq+1); putreg32(INTC_REQUEST_WEACTLOW|INTC_REQUEST_WEENABLE|INTC_REQUEST_TARGET_IRQ| INTC_REQUEST_PRIOLEVEL(1)|INTC_REQUEST_WEPRIO, address); @@ -142,7 +142,7 @@ void up_disable_irq(int irq) * interrupt source */ - uint32_t address = LPC313X_INTC_REQUEST(irq); + uint32_t address = LPC313X_INTC_REQUEST(irq+1); /* Clear the ENABLE bit with WE_ENABLE=1. Configuration settings will be * preserved because WE_TARGET is zero. @@ -165,7 +165,7 @@ void up_enable_irq(int irq) * interrupt source */ - uint32_t address = LPC313X_INTC_REQUEST(irq); + uint32_t address = LPC313X_INTC_REQUEST(irq+1); /* Set the ENABLE bit with WE_ENABLE=1. Configuration settings will be * preserved because WE_TARGET is zero. @@ -188,7 +188,7 @@ void up_maskack_irq(int irq) * interrupt source */ - uint32_t address = LPC313X_INTC_REQUEST(irq); + uint32_t address = LPC313X_INTC_REQUEST(irq+1); /* Clear the pending interrupt (INTC_REQUEST_CLRSWINT=1) AND disable interrupts * (ENABLE=0 && WE_ENABLE=1). Configuration settings will be preserved because diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_pllconfig.c b/nuttx/arch/arm/src/lpc313x/lpc313x_pllconfig.c index e7d589feb..8ecbc4a5c 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_pllconfig.c +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_pllconfig.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc313x/lpc313x_pllconfig.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -89,7 +89,7 @@ lpc313x_switchdomains(const struct lpc313x_pllconfig_s * const cfg) { /* Get the switch status registers (SSR) for this frequency input domain */ - address = LPC313X_CGU_SSR_OFFSET(i); + address = LPC313X_CGU_SSR(i); regval = getreg32(address); /* Check if the current frequency selection is the PLL-to-be-configured */ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_setfdiv.c b/nuttx/arch/arm/src/lpc313x/lpc313x_setfdiv.c index 7bb2f1d9c..87ab5e377 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_setfdiv.c +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_setfdiv.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc313x/lpc313x_setfdiv.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -95,7 +95,7 @@ void lpc313x_setfdiv(enum lpc313x_domainid_e dmnid, { /* Yes.. Save the current reference frequency selection */ - regaddr = LPC313X_CGU_SSR_OFFSET((int)dmnid); + regaddr = LPC313X_CGU_SSR((int)dmnid); basefreq = (getreg32(regaddr) & CGU_SSR_FS_MASK) >> CGU_SSR_FS_SHIFT; /* Switch domain to FFAST input */ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_setfreqin.c b/nuttx/arch/arm/src/lpc313x/lpc313x_setfreqin.c index 20411f320..dc6ef2b3a 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_setfreqin.c +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_setfreqin.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc313x/lpc313x_setfreqin.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -92,7 +92,7 @@ void lpc313x_selectfreqin(enum lpc313x_domainid_e dmnid, uint32_t finsel) /* If FS1 is currently enabled set the reference clock to FS2 and enable FS2 */ - if (getreg32(LPC313X_CGU_SSR(dmnid) & CGU_SSR_FS1STAT) != 0) + if ((getreg32(LPC313X_CGU_SSR(dmnid)) & CGU_SSR_FS1STAT) != 0) { /* Check if the selected frequency, FS1, is same as requested */ -- cgit v1.2.3