From 61381bfda1b6bd7d614cd22cac7137d4ef73e3bc Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 1 Jun 2012 13:22:27 +0000 Subject: Interrupt priority fix + new LM3S header files git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4792 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/armv7-m/nvic.h | 2 + nuttx/arch/arm/src/lm3s/lm3s_epi.h | 113 +++++++++++++++++++++++++++++++ nuttx/arch/arm/src/lm3s/lm3s_timer.h | 125 +++++++++++++++++++++++++++++++++++ nuttx/arch/arm/src/stm32/stm32_irq.c | 43 ++++++------ 4 files changed, 264 insertions(+), 19 deletions(-) create mode 100755 nuttx/arch/arm/src/lm3s/lm3s_epi.h create mode 100755 nuttx/arch/arm/src/lm3s/lm3s_timer.h (limited to 'nuttx/arch') diff --git a/nuttx/arch/arm/src/armv7-m/nvic.h b/nuttx/arch/arm/src/armv7-m/nvic.h index de34cc7b9..27fbf9a71 100644 --- a/nuttx/arch/arm/src/armv7-m/nvic.h +++ b/nuttx/arch/arm/src/armv7-m/nvic.h @@ -203,6 +203,7 @@ #define NVIC_ISAR3_OFFSET 0x0d6c /* ISA feature register 3 */ #define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */ #define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */ +#define NVIC_ICTR_OFFSET 0x0004 /* Interrupt controller type register */ #define NVIC_STIR_OFFSET 0x0f00 /* Software trigger interrupt register */ #define NVIC_FPCCR_OFFSET 0x0f34 /* Floating-point Context Control Register */ #define NVIC_FPCAR_OFFSET 0x0f38 /* Floating-point Context Address Register */ @@ -372,6 +373,7 @@ #define NVIC_ISAR3 (ARMV7M_NVIC_BASE + NVIC_ISAR3_OFFSET) #define NVIC_ISAR4 (ARMV7M_NVIC_BASE + NVIC_ISAR4_OFFSET) #define NVIC_CPACR (ARMV7M_NVIC_BASE + NVIC_CPACR_OFFSET) +#define NVIC_ICTR (ARMV7M_NVIC_BASE + NVIC_ICTR_OFFSET) #define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET) #define NVIC_FPCCR (ARMV7M_NVIC_BASE + NVIC_FPCCR_OFFSET) #define NVIC_PID4 (ARMV7M_NVIC_BASE + NVIC_PID4_OFFSET) diff --git a/nuttx/arch/arm/src/lm3s/lm3s_epi.h b/nuttx/arch/arm/src/lm3s/lm3s_epi.h new file mode 100755 index 000000000..90c9bfb7f --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/lm3s_epi.h @@ -0,0 +1,113 @@ +/************************************************************************************ + * arch/arm/src/lm3s/lm3s_epi.h + * + * Copyright (C) 2009-2012 Max Neklyudov. All rights reserved. + * Author: Max Neklyudov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_LM3S_EPI_H +#define __ARCH_ARM_SRC_LM3S_LM3S_EPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* External Peripheral Interface Register Offsets ***********************************/ + +#define LM3S_EPI_CFG_OFFSET 0x000 +#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 +#define LM3S_EPI_ADDRMAP_OFFSET 0x01C +#define LM3S_EPI_STAT_OFFSET 0x060 +#define LM3S_EPI_BAUD_OFFSET 0x004 + +/* External Peripheral Interface Register Addresses *********************************/ + +#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) +#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) +#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) +#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) +#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) + +/* External Peripheral Interface Register Bit Definitions ***************************/ + +/* EPI Configuration (EPICFG), offset 0x000 */ + +#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ +#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) +# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ + +/* EPI Address Map (EPIADDRMAP), offset 0x01C */ + +#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ +#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) +#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ +#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) + +/* EPI Status (EPISTAT), offset 0x060 */ + +#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ +#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) + +/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ + +#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ +#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) +#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ +#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) +# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) +#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ +#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) + +/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ + +#define EPI_BAUD_COUNT0_SHIFT 0 +#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) +# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM3S_LM3S_EPI_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timer.h b/nuttx/arch/arm/src/lm3s/lm3s_timer.h new file mode 100755 index 000000000..7c4166293 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/lm3s_timer.h @@ -0,0 +1,125 @@ +/************************************************************************************ + * arch/arm/src/lm3s/lm3s_timer.h + * + * Copyright (C) 2012 Max Nekludov. All rights reserved. + * Author: Max Nekludov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H +#define __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Timer register offsets ***********************************************************/ + +#define TIMER_GPTMCFG_OFFSET 0x000 +#define TIMER_GPTMTAMR_OFFSET 0x004 +#define TIMER_GPTMCTL_OFFSET 0x00C +#define TIMER_GPTMIMR_OFFSET 0x018 +#define TIMER_GPTMRIS_OFFSET 0x01C +#define TIMER_GPTMICR_OFFSET 0x024 +#define TIMER_GPTMTAILR_OFFSET 0x028 +#define TIMER_GPTMTAR_OFFSET 0x048 + +/* SSI register addresses ***********************************************************/ + +#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) + +#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) +#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) +#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) +#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) +#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) +#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) +#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) +#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) + +/* SSI register bit defitiions ******************************************************/ + +/* GPTM Configuration (GPTMCFG), offset 0x000 */ + +#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ +#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) +#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ +#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ +#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ + +/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ + +#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ +#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) +#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ +#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ +#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ +#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ +#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) +#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ +#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ +#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ +#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) +#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ +#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ +#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ +#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) +#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ +#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ +#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ +#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) + +/* GPTM Control (GPTMCTL), offset 0x00C */ + +#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ +#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) +#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ +#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) + +/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ + +#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ +#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) + +/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ + +#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ +#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) + +/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ + +#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ +#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H */ diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index 40c0c5bc3..c5fab1514 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -2,8 +2,8 @@ * arch/arm/src/stm32/stm32_irq.c * arch/arm/src/chip/stm32_irq.c * - * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -273,6 +273,9 @@ static int stm32_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) void up_irqinitialize(void) { + uint32_t regaddr; + int num_priority_registers; + /* Disable all interrupts */ putreg32(0, NVIC_IRQ0_31_ENABLE); @@ -294,23 +297,25 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ64_67_PRIORITY); + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } /* currents_regs is non-NULL only while processing an interrupt */ -- cgit v1.2.3