From c93bc6dc271027672de7e0e33fd3cb1ceb9da569 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Fri, 20 Jun 2014 10:33:33 -0600
Subject: SAMA5D4-EK:  Make sure that the H32MX divider is set; correct sense
 of bit driver red LED

---
 nuttx/arch/arm/src/sama5/sam_clockconfig.c | 40 ++++++++++++++++++++++++++++++
 nuttx/arch/arm/src/sama5/sam_irq.c         |  5 ++--
 2 files changed, 42 insertions(+), 3 deletions(-)

(limited to 'nuttx/arch')

diff --git a/nuttx/arch/arm/src/sama5/sam_clockconfig.c b/nuttx/arch/arm/src/sama5/sam_clockconfig.c
index 2c5fa7d0e..cfcb965ea 100644
--- a/nuttx/arch/arm/src/sama5/sam_clockconfig.c
+++ b/nuttx/arch/arm/src/sama5/sam_clockconfig.c
@@ -350,6 +350,42 @@ static inline void __ramfunc__ sam_mckdivider(void)
 }
 #endif
 
+/****************************************************************************
+ * Name: sam_h32mxdivider
+ *
+ * Description:
+ *   Set the H32MX divider.
+ *
+ *   0: The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix
+ *      frequency. It is possible only if the AHB 64-bit Matrix frequency
+ *      does not exceed 90 MHz.
+ *   1: H32MXDIV2 The AHB 32-bit Matrix frequency is equal to the AHB 64-bit
+ *      Matrix frequency divided by 2.
+ *
+ ****************************************************************************/
+
+#ifdef PMC_MCKR_H32MXDIV
+static inline void __ramfunc__ sam_h32mxdivider(void)
+{
+  uint32_t regval;
+
+  regval = getreg32(SAM_PMC_MCKR);
+
+  /* Check the 64-bit Matrix frequency (MCK, right?) */
+
+  if (BOARD_MCK_FREQUENCY <= 90000000)
+    {
+      regval &= ~PMC_MCKR_H32MXDIV;
+    }
+  else
+    {
+      regval |= PMC_MCKR_H32MXDIV;
+    }
+
+  putreg32(regval, SAM_PMC_MCKR);
+}
+#endif
+
 /****************************************************************************
  * Name: sam_selectplla
  *
@@ -654,6 +690,10 @@ void __ramfunc__ sam_clockconfig(void)
 
       sam_mckdivider();
 
+      /* Configure the H32MX Divider */
+
+      sam_h32mxdivider();
+
       /* Finally, elect the PLLA output as the input clock for PCK and MCK. */
 
       sam_selectplla();
diff --git a/nuttx/arch/arm/src/sama5/sam_irq.c b/nuttx/arch/arm/src/sama5/sam_irq.c
index ad4e1e5c9..ca7d63987 100644
--- a/nuttx/arch/arm/src/sama5/sam_irq.c
+++ b/nuttx/arch/arm/src/sama5/sam_irq.c
@@ -91,7 +91,7 @@ extern uint32_t _vector_end;   /* End+1 of vector block */
 
 static const uint8_t g_srctype[SCRTYPE_NTYPES] =
 {
- 0, 0, 1, 1, 2, 3
+  0, 0, 1, 1, 2, 3
 };
 
 /****************************************************************************
@@ -494,7 +494,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
   ivr = getreg32(SAM_AIC_IVR);
   putreg32(ivr, SAM_AIC_IVR);
 
-  /* Get the IRQ number from the interrrupt status register.  NOTE that the
+  /* Get the IRQ number from the interrupt status register.  NOTE that the
    * IRQ number is the same is the peripheral ID (PID).
    */
 
@@ -691,4 +691,3 @@ void sam_irq_srctype(int irq, enum sam_srctype_e srctype)
   sam_dumpaic("srctype", irq);
   irqrestore(flags);
 }
-
-- 
cgit v1.2.3