From fe19b6983e874ab10a1e3ad510829ad34a8612cd Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 20 Jun 2012 19:29:20 +0000 Subject: Updates to support the Mirtoo internal clocking git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4855 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/configs/mirtoo/include/board.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'nuttx/configs/mirtoo/include') diff --git a/nuttx/configs/mirtoo/include/board.h b/nuttx/configs/mirtoo/include/board.h index 98aa904a3..ffea646d1 100644 --- a/nuttx/configs/mirtoo/include/board.h +++ b/nuttx/configs/mirtoo/include/board.h @@ -52,16 +52,22 @@ /* Configuration ************************************************************/ /* Clocking *****************************************************************/ -/* Crystal frequencies */ +/* The Mirtoo does not use an external crystal but relies instead on the + * internal +/- 0.9% FRC clock. That clock has a nomninal frequency of 8MHz. + */ + +#define BOARD_FRC_FREQ 8000000 /* FRC nomimal frequency(8MHz) */ + +/* Oscillator modes */ -#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */ -#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ -#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ +#define BOARD_FNOSC_FRCPLL 1 /* Use FRC w/PLL module */ +#define BOARD_POSC_DISABLED 1 /* Disable primary oscillator */ /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV */ +#define BOARD_PLL_INPUT BOARD_FRC_FREQ #define BOARD_PLL_IDIV 2 /* PLL input divider */ #define BOARD_PLL_MULT 20 /* PLL multiplier */ #define BOARD_PLL_ODIV 1 /* PLL output divider */ -- cgit v1.2.3