From 89bf1ad3436abe815fa7441e157ba59078189993 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Sat, 6 Nov 2010 15:55:07 +0000
Subject: Add support for the Olimex LPC1766-STK board

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3079 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/configs/olimex-lpc1766stk/tools/olimex.cfg | 61 ++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100755 nuttx/configs/olimex-lpc1766stk/tools/olimex.cfg

(limited to 'nuttx/configs/olimex-lpc1766stk/tools/olimex.cfg')

diff --git a/nuttx/configs/olimex-lpc1766stk/tools/olimex.cfg b/nuttx/configs/olimex-lpc1766stk/tools/olimex.cfg
new file mode 100755
index 000000000..6b98458e6
--- /dev/null
+++ b/nuttx/configs/olimex-lpc1766stk/tools/olimex.cfg
@@ -0,0 +1,61 @@
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG A"
+ft2232_layout "olimex-jtag"
+ft2232_vid_pid 0x15BA 0x0003
+
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc1768
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+#delays on reset lines
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# LPC2000 & LPC1700 -> SRST causes TRST
+reset_config trst_and_srst srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
+
+# REVISIT is there any good reason to have this reset-init event handler??
+# Normally they should set up (board-specific) clocking then probe the flash...
+$_TARGETNAME configure -event reset-init {
+	# Force NVIC.VTOR to point to flash at 0 ...
+	# WHY?  This is it's reset value; we run right after reset!!
+	mwb 0xE000ED08 0x00
+}
+
+# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
+# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 80000 calc_checksum
+
+# 4MHz / 6 = 666kHz, so use 500
+jtag_khz 100
-- 
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