From 2c18afa0c32762c68c078b7879ff98fed73d32b0 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Wed, 15 May 2013 23:59:13 -0600
Subject: Fix Pirelli DP-L10 linker script

---
 nuttx/configs/pirelli_dpl10/README.txt         | 15 ++++++------
 nuttx/configs/pirelli_dpl10/scripts/highram.ld | 34 ++++++++++++++------------
 2 files changed, 27 insertions(+), 22 deletions(-)

(limited to 'nuttx/configs')

diff --git a/nuttx/configs/pirelli_dpl10/README.txt b/nuttx/configs/pirelli_dpl10/README.txt
index d81ead702..3b89005ed 100644
--- a/nuttx/configs/pirelli_dpl10/README.txt
+++ b/nuttx/configs/pirelli_dpl10/README.txt
@@ -78,17 +78,18 @@ Loading NuttX
 Memory Map
 =========
 
-  Calypso has 256KB of internal SRAM (0x800000-0x83ffff).  Only this internal SRAM
-  is used by these configurations.  The internal SRAM is broken up into three
-  logic banks.
+  Calypso has 256KB of internal SRAM (0x800000-0x83ffff, although some of
+  this is, I believe, actually ROM).  Only this internal SRAM is used by
+  these configurations.  The internal SRAM is broken up into two logical
+  banks.
 
     LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000
-    TRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00010000
+    HRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00020000
     IRAM (rw) : ORIGIN = 0x00830000, LENGTH = 0x00010000
 
-  Code can be loaded by the bootloader only into TRAM and, hence, is restricted
-  to 64KB.  The additional 64KB if IRAM may be used for uninitialized data and
-  for the NuttX heap only.
+  Code can be loaded by the CalypsoBootloader only into HRAM beginning at
+  address 0x00820000 and, hence, is restricted to 128KB (including then
+  non-loaded sections:  uninitialized data and for the NuttX heap).
 
 JTAG and Alternative Serial Console
 ===================================
diff --git a/nuttx/configs/pirelli_dpl10/scripts/highram.ld b/nuttx/configs/pirelli_dpl10/scripts/highram.ld
index 35fa84728..f20a5f89c 100644
--- a/nuttx/configs/pirelli_dpl10/scripts/highram.ld
+++ b/nuttx/configs/pirelli_dpl10/scripts/highram.ld
@@ -1,23 +1,27 @@
 /*
- * Linker script for running from internal SRAM on Compal phones
+ * Linker script for running from internal SRAM on Pirelli DP-L10 phones
  *
  * This script is tailored specifically to the requirements imposed
- * on us by the Compal bootloader.
+ * on us by the CalypsoRomloader in the Pirelli rom.
  *
  */
 
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 ENTRY(__start)
+
 MEMORY
 {
-    /* 0x800000-0x83ffff */
-    /* compal-loaded binary: our text, initialized data */
+    /* 0x00800000-0x0082000:  Low RAM.  Used only for exception vectors */
+
     LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000
-    TRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00010000
-    /* compal-loaded binary: our unitialized data, stacks, heap */
-    IRAM (rw) : ORIGIN = 0x00830000, LENGTH = 0x00010000
+
+    /* 0x00820000-0x0084000: High RAM.  The CalypsoRomloader loads binary to
+	 * address 0x00820000 */
+
+    HRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00020000
 }
+
 SECTIONS
 {
     . = 0x800000;
@@ -34,7 +38,7 @@ SECTIONS
         PROVIDE(__start = .);
         KEEP(*(.text.start))
         *(.text.start)
-    } > TRAM
+    } > HRAM
 
     /* exception vectors from 0x80001c to 0x800034 */
     .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) {
@@ -55,7 +59,7 @@ SECTIONS
         /* gcc voodoo */
         *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
         . = ALIGN(4);
-    } > TRAM
+    } > HRAM
     PROVIDE(_text_start = LOADADDR(.text));
     PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text));
 
@@ -67,7 +71,7 @@ SECTIONS
         KEEP(*(SORT(.ctors)))
         /* end of list */
         LONG(0)
-    } > TRAM
+    } > HRAM
     PROVIDE(_ctor_start = LOADADDR(.ctors));
     PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors));
 
@@ -79,7 +83,7 @@ SECTIONS
         KEEP(*(SORT(.dtors)))
         /* end of list */
         LONG(0)
-    } > TRAM
+    } > HRAM
     PROVIDE(_dtor_start = LOADADDR(.dtors));
     PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors));
 
@@ -87,7 +91,7 @@ SECTIONS
     . = ALIGN(4);
     .rodata : {
         *(.rodata*)
-    } > TRAM
+    } > HRAM
     PROVIDE(_rodata_start = LOADADDR(.rodata));
     PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata));
 
@@ -95,7 +99,7 @@ SECTIONS
     . = ALIGN(4);
     .data : {
         *(.data)
-    } > TRAM
+    } > HRAM
     PROVIDE(_data_start = LOADADDR(.data));
     PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data));
 
@@ -104,7 +108,7 @@ SECTIONS
     .got : {
         *(.got)
         *(.got.plt) *(.igot.plt) *(.got) *(.igot)
-    } > TRAM
+    } > HRAM
     PROVIDE(_got_start = LOADADDR(.got));
     PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got));
 
@@ -115,7 +119,7 @@ SECTIONS
         _sbss = ABSOLUTE(.);
         *(.bss)
         _ebss = ABSOLUTE(.);
-    } > IRAM
+    } > HRAM
     . = ALIGN(4);
     __bss_end = .;
     PROVIDE(_bss_start = __bss_start);
-- 
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