From 256f0e1d7c705832b7cefe68dca56056b1855301 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 4 Apr 2009 20:27:37 +0000 Subject: Add eZ80 I2C driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1679 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/z80/src/ez80/Make.defs | 5 +- nuttx/arch/z80/src/ez80/ez80_i2c.c | 931 ++++++++++++++++++++++++++++++++++ nuttx/arch/z80/src/ez80/ez80f91_i2c.h | 33 +- nuttx/include/nuttx/i2c.h | 29 +- 4 files changed, 990 insertions(+), 8 deletions(-) create mode 100644 nuttx/arch/z80/src/ez80/ez80_i2c.c (limited to 'nuttx') diff --git a/nuttx/arch/z80/src/ez80/Make.defs b/nuttx/arch/z80/src/ez80/Make.defs index 2cbf5559c..8999b6a66 100644 --- a/nuttx/arch/z80/src/ez80/Make.defs +++ b/nuttx/arch/z80/src/ez80/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/z80/src/ez80/Make.defs # -# Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. +# Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -52,7 +52,8 @@ endif CHIP_SSRCS = CHIP_CSRCS = ez80_clock.c ez80_initialstate.c ez80_irq.c ez80_copystate.c \ ez80_schedulesigaction.c ez80_sigdeliver.c ez80_timerisr.c \ - ez80_lowuart.c ez80_serial.c ez80_spi.c ez80_registerdump.c + ez80_lowuart.c ez80_serial.c ez80_spi.c ez80_i2c.c \ + ez80_registerdump.c ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y) ifeq ($(CONFIG_EZ80_EMAC),y) CHIP_CSRCS += ez80_emac.c diff --git a/nuttx/arch/z80/src/ez80/ez80_i2c.c b/nuttx/arch/z80/src/ez80/ez80_i2c.c new file mode 100644 index 000000000..a1ca6c297 --- /dev/null +++ b/nuttx/arch/z80/src/ez80/ez80_i2c.c @@ -0,0 +1,931 @@ +/**************************************************************************** + * arch/z80/src/ez80/ez80_i2c.c + * + * Copyright(C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "ez80f91.h" +#include "ez80f91_i2c.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct ez80_i2cdev_s +{ + const struct i2c_ops_s *ops; /* I2C vtable */ + uint16 ccr; /* Clock control register value */ + uint16 addr; /* 7- or 10-bit address */ + ubyte addr10 : 1; /* 1=Address is 10-bit */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Misc. Helpers */ + +static void i2c_setccr(uint16 ccr); +static uint16 i2c_getccr(uint32 frequency); +static ubyte i2c_waitiflg(void); +static void i2c_clriflg(void); +static void i2c_start(void); +static void i2c_stop(void); +static int i2c_sendaddr(struct ez80_i2cdev_s *priv, ubyte readbit); + +/* I2C methods */ + +static uint32 i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32 frequency); +static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits); +static int i2c_write(FAR struct i2c_dev_s *dev, const ubyte *buffer, int buflen); +static int i2c_read(FAR struct i2c_dev_s *dev, ubyte *buffer, int buflen); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* This function is normally prototyped int the ZiLOG header file sio.h */ + +extern uint32 get_freq(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static ubyte g_currccr; /* Current setting of I2C CCR register */ +static boolean g_initialized; /* TRUE:I2C has been initialized */ +static sem_t g_i2csem; /* Serialize I2C transfers */ + +const struct i2c_ops_s g_ops = +{ + i2c_setfrequency, + i2c_setaddress, + i2c_write, + i2c_read, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ +/**************************************************************************** + * Name: i2c_semtake/i2c_semgive + * + * Description: + * Take/Give the I2C semaphore. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void i2c_semtake(void) +{ + /* Take the I2C semaphore (perhaps waiting) */ + + while (sem_wait(&g_i2csem) != 0) + { + /* The only case that an error should occr here is if + * the wait was awakened by a signal. + */ + + ASSERT(errno == EINTR); + } +} + +#define i2c_semgive() sem_post(&g_i2csem) + +/**************************************************************************** + * Name: i2c_setccr + * + * Description: + * Set the current BRG value for this transaction + * + * Input Parameters: + * ccr - BRG to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void i2c_setccr(uint16 ccr) +{ + if (g_currccr != ccr) + { + outp(EZ80_I2C_CCR, ccr); + g_currccr = ccr; + } +} + +/**************************************************************************** + * Name: i2c_getccr + * + * Description: + * Calculate the BRG value + * + * Input Parameters: + * fscl - The I2C frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint16 i2c_getccr(uint32 fscl) +{ + uint32 fsamp; + uint32 ftmp; + ubyte n; + ubyte m; + + /* The sampling frequency is given by: + * + * fsamp = sysclock / 2**N + * + * And the I2C clock is determined by: + * + * fscl = sysclock / 10 / (M + 1) / 2**N + * = fsamp / 10 / (M + 1) + * + * The fsmp must be >= 10 * fscl. The best solution is the smallest value of + * N so that the sampling rate is the highest subject to: + * + * The minimum value of the fsamp is given by: + */ + + fsamp = 10 * fscl; + + /* Now, serarch for the smallest value of N that results in the actual + * fsamp >= the ideal fsamp. Fortunately, we only have to check at most + * eight values. + */ + + if (fsamp >= EZ80_SYS_CLK_FREQ) + { + ftmp = EZ80_SYS_CLK_FREQ / 10; + n = 0; + } + else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 1)) + { + ftmp = (EZ80_SYS_CLK_FREQ >> 1) / 10; + n = 1; + } + else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 2)) + { + ftmp = (EZ80_SYS_CLK_FREQ >> 2) / 10; + n = 2; + } + else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 3)) + { + ftmp = (EZ80_SYS_CLK_FREQ >> 3) / 10; + n = 3; + } + else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 4)) + { + ftmp = (EZ80_SYS_CLK_FREQ >> 4) / 10; + n = 4; + } + else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 5)) + { + ftmp = (EZ80_SYS_CLK_FREQ >> 5) / 10; + n = 5; + } + else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 6)) + { + ftmp = (EZ80_SYS_CLK_FREQ >> 6) / 10; + n = 6; + } + else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 7)) + { + ftmp = (EZ80_SYS_CLK_FREQ >> 7) / 10; + n = 7; + } + else + { + ftmp = (EZ80_SYS_CLK_FREQ >> 7) / 10; + fscl = ftmp; + n = 7; + } + + /* Finally, get M: + * + * M = (fsamp / 10) / fscl - 1 = ftmp / fscl - 1 + */ + + m = ftmp / fscl; + if (m > 0) + { + if (--m > 15) + { + m = 15; + } + } + + /* Return the value for CCR */ + + return (n << I2C_CCR_NSHIFT) | (m << I2C_CCR_MSHIFT); +} + +/**************************************************************************** + * Name: i2c_waitiflg + * + * Description: + * In polled mode, we have to spin until the IFLG bit in the xxx register + * goes to 1, signalling that the last send or receive is complete. This + * could be used to generate an interrupt for a non-polled driver. + * + * Input Parameters: + * priv - Device-specific state data + * readbit - 0 or I2C_READBIT + * + * Returned Value: + * The contents of the I2C_SR register at the time that IFLG became 1. + * + ****************************************************************************/ + +static ubyte i2c_waitiflg(void) +{ + while ((inp(EZ80_I2C_CTL) & I2C_CTL_IFLG) != 0); + return inp(EZ80_I2C_SR); +} + +/**************************************************************************** + * Name: i2c_clriflg + * + * Description: + * Clear the IFLAG bit in the I2C_CTL register, acknowledging the event. + * If interrupts are enabled, this would clear the interrupt status. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void i2c_clriflg(void) +{ + ubyte regval = inp(EZ80_I2C_CTL); + regval &= ~I2C_CTL_IFLG; + outp(EZ80_I2C_CTL, regval); +} + +/**************************************************************************** + * Name: i2c_start + * + * Description: + * Send the START bit. IFLAG must be zero; it will go to 1 when it is + * time to send the address. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void i2c_start(void) +{ + ubyte regval = inp(EZ80_I2C_CTL); + regval |= I2C_CTL_STA; + outp(EZ80_I2C_CTL, regval); +} + +/**************************************************************************** + * Name: i2c_stop + * + * Description: + * Send the STOP bit. This terminates the I2C transfer and reverts back + * to IDLE mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void i2c_stop(void) +{ + ubyte regval = inp(EZ80_I2C_CTL); + regval |= I2C_CTL_STP; + outp(EZ80_I2C_CTL, regval); +} + +/**************************************************************************** + * Name: i2c_sendaddr + * + * Description: + * Send the 8- or 11-bit address for either a read or a write transaction. + * + * Input Parameters: + * priv - Device-specific state data + * readbit - 0 or I2C_READBIT + * + * Returned Value: + * 0: Success, IFLG is set and DATA can be sent or received. + + * Or <0: Negated error value. IFLG is cleared. + * + * -EIO: Irrecoverable (or unexpected) error occured + * -EAGAIN: And + * + ****************************************************************************/ + +static int i2c_sendaddr(struct ez80_i2cdev_s *priv, ubyte readbit) +{ + ubyte sr; + int ret = OK; + + /* Wait for the IFLG bit to transition to 1. At this point, we should + * have status == 8 meaning that the start bit was sent successfully. + */ + + sr = i2c_waitiflg(); +#ifdef CONFIG_DEBUG + if (sr != I2C_SR_MSTART) + { + /* This error should never occur */ + + dbg("Bad START status: %02x\n", sr); + i2c_clriflg(); + return -EIO; + } +#endif + + /* Now send the address */ + + if (!priv->addr10) + { + /* Load the I2C_DR with the 8-bit I2C slave address and clear the + * IFLG. Clearing the IFLAG will cause the address to be transferred. + */ + + outp(EZ80_I2C_DR, (ubyte)I2C_ADDR8(priv->addr) | readbit); + i2c_clriflg(); + + /* And wait for the address transfer to complete */ + + sr = i2c_waitiflg(); + if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR) + { + dbg("Bad ADDR8 status: %02x\n", sr); + goto failure; + } + } + else + { + /* Load the I2C_DR with upper part of the 10->16-bit I2C slave address + * and clear the IFLG. Clearing the IFLAG will cause the address to + * be transferred. + */ + + outp(EZ80_I2C_DR, (ubyte)I2C_ADDR10H(priv->addr) | readbit); + i2c_clriflg(); + + /* And wait for the address transfer to complete */ + + sr = i2c_waitiflg(); + if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR) + { + dbg("Bad ADDR10H status: %02x\n", sr); + goto failure; + } + + /* Now send the lower 8 bits of the 10-bit address */ + + outp(EZ80_I2C_DR, (ubyte)I2C_ADDR10L(priv->addr)); + i2c_clriflg(); + + /* And wait for the address transfer to complete */ + + sr = i2c_waitiflg(); + if (sr != I2C_SR_MADDR2WRACK && sr != I2C_SR_MADDR2WR) + { + dbg("Bad ADDR10L status: %02x\n", sr); + goto failure; + } + } + + return OK; + + /* We don't attempt any fancy status-based error recovery */ + +failure: +#ifdef CONFIG_DEBUG + switch (sr) + { + case I2C_SR_ARBLOST1: /* Arbitration lost in address or data byte */ + case I2C_SR_ARBLOST2: /* Arbitration lost in address as master, slave address and Write bit received, ACK transmitted */ + case I2C_SR_ARBLOST3: /* Arbitration lost in address as master, General Call address received, ACK transmitted */ + case I2C_SR_ARBLOST4: /* Arbitration lost in address as master, slave address and Read bit received, ACK transmitted */ + dbg("Arbitration lost: %02x\n", sr); + i2c_clriflg(); + return -EAGAIN; + + default: + dbg("Unexpected status: %02x\n", sr); + i2c_clriflg(); + return -EIO; + } +#else + i2c_clriflg(); + return -EAGAIN; +#endif +} + +/**************************************************************************** + * Name: i2c_setfrequency + * + * Description: + * Set the I2C frequency. This frequency will be retained in the struct + * i2c_dev_s instance and will be used with all transfers. Required. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The I2C frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32 i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32 frequency) +{ + FAR struct ez80_i2cdev_s *priv = (FAR struct ez80_i2cdev_s *)dev; + + /* Sanity Check */ + +#ifdef CONFIG_DEBUG + if (!dev) + { + dbg("Invalid inputs\n"); + return -EINVAL; + } +#endif + + /* Calculate and save the BRG (we won't apply it until the first transfer) */ + + priv->ccr = i2c_getccr(frequency); + return OK; +} + +/**************************************************************************** + * Name: i2c_setaddress + * + * Description: + * Set the I2C slave address. This frequency will be retained in the struct + * i2c_dev_s instance and will be used with all transfers. Required. + * + * Input Parameters: + * dev - Device-specific state data + * address - The I2C slave address + * nbits - The number of address bits provided (7 or 10) + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) +{ + FAR struct ez80_i2cdev_s *priv = (FAR struct ez80_i2cdev_s *)dev; + + /* Sanity Check */ + +#ifdef CONFIG_DEBUG + if (!dev || (unsigned)addr > 0x7f || (nbits != 7 && nbits != 10)) + { + dbg("Invalid inputs\n"); + return -EINVAL; + } +#endif + + /* Save the 7- or 10-bit address */ + + priv->addr = addr; + priv->addr10 = (nbits == 10); + return OK; +} + +/**************************************************************************** + * Name: i2c_write + * + * Description: + * Send a block of data on I2C using the previously selected I2C + * frequency and slave address. Each write operational will be an 'atomic' + * operation in the sense that any other I2C actions will be serialized + * and pend until this write completes. Required. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the read-only buffer of data to be written to device + * buflen - The number of bytes to send from the buffer + * + * Returned Value: + * 0: success, <0: A negated errno + * + ****************************************************************************/ + +static int i2c_write(FAR struct i2c_dev_s *dev, const ubyte *buffer, int buflen) +{ + FAR struct ez80_i2cdev_s *priv = (FAR struct ez80_i2cdev_s *)dev; + const ubyte *ptr; + ubyte sr; + int retry; + int count; + int ret; + +#ifdef CONFIG_DEBUG + if (!priv || !buffer || buflen < 1) + { + dbg("Invalid inputs\n"); + return -EINVAL; + } +#endif + + /* Get exclusive access */ + + i2c_semtake(); + + /* Set the frequency */ + + i2c_setccr(priv->ccr); + + /* Retry as necessary to send this whole message */ + + for (retry = 0; retry < 100; retry++) + { + /* Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL + * register to 1. The I2C then tests the I2C bus and transmits a START + * condition when the bus is free. + */ + + i2c_start(); + + /* When a START condition is transmitted, the IFLG bit is 1. Then we may + * send the I2C slave address. + */ + + ret = i2c_sendaddr(priv, 0); + if (ret < 0) + { + if (ret == -EAGAIN) + { + continue; + } + else + { + goto failure; + } + } + + /* Then send all of the bytes in the buffer */ + + ptr = buffer; + for (count = buflen; count; count--) + { + /* Load the I2C_DR with next data byte and clear the IFLG. Clearing + * the IFLAG will cause the data to be transferred. + */ + + outp(EZ80_I2C_DR, *ptr++); + i2c_clriflg(); + + /* And wait for the data transfer to complete */ + + sr = i2c_waitiflg(); + if (sr != I2C_SR_MDATAWRACK && sr != I2C_SR_MDATAWR) + { + dbg("Bad DATA status: %02x\n", sr); + i2c_clriflg(); + if (sr == I2C_SR_ARBLOST1) + { + /* Arbitration lost, break out of the inner loop and + * try sending the message again + */ + + break; + } + + /* Otherwise, it is fatal (shouldn't happen) */ + + ret = -EIO; + goto failure; + } + + /* Data byte was sent successfully. Was that the last byte? */ + + else if (count <= 1) + { + /* When all bytes are transmitted, the microcontroller must + * write a 1 to the STP bit in the I2C_CTL register. The + * I2C then transmits a STOP condition, clears the STP bit + * and returns to an idle state. + */ + + i2c_stop(); + + ret = OK; + goto success; + } + } + } + + /* If we get here, we timed out without successfully sending the message */ + + ret = -ETIMEDOUT; + +success: +failure: + i2c_semgive(); + return ret; +} + +/**************************************************************************** + * Name: i2c_read + * + * Description: + * Receive a block of data from I2C using the previously selected I2C + * frequency and slave address. Each read operational will be an 'atomic' + * operation in the sense that any other I2C actions will be serialized + * and pend until this read completes. Required. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to a buffer of data to receive the data from the device + * buflen - The requested number of bytes to be read + * + * Returned Value: + * 0: success, <0: A negated errno + * + ****************************************************************************/ + +static int i2c_read(FAR struct i2c_dev_s *dev, ubyte *buffer, int buflen) +{ + FAR struct ez80_i2cdev_s *priv = (FAR struct ez80_i2cdev_s *)dev; + ubyte *ptr; + ubyte regval; + int retry; + int count; + int ret; + +#ifdef CONFIG_DEBUG + if (!priv || !buffer || buflen < 1) + { + dbg("Invalid inputs\n"); + return -EINVAL; + } +#endif + + /* Get exclusive access */ + + i2c_semtake(); + + /* Set the frequency */ + + i2c_setccr(priv->ccr); + + /* Retry as necessary to receive the whole message */ + + for (retry = 0; retry < 100; retry++) + { + /* Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL + * register to 1. The I2C then tests the I2C bus and transmits a START + * condition when the bus is free. + */ + + i2c_start(); + + /* When a START condition is transmitted, the IFLG bit is 1. Then we may + * send the I2C slave address. + */ + + ret = i2c_sendaddr(priv, 0); + if (ret < 0) + { + if (ret == -EAGAIN) + { + continue; + } + else + { + goto failure; + } + } + + /* Now loop to receive each data byte */ + + ptr = buffer; + for (count = buflen; count; count--) + { + /* Is this the last byte? If so, we must NACK it */ + + regval = inp(EZ80_I2C_CTL); + if (count <= 1) + { + /* If the AAK bit is cleared to 0 during a transfer, the I2C + * transmits a NACK bit after the next byte is received. + */ + + regval &= ~I2C_CTL_AAK; + } + else + { + /* If the AAK bit in the I2C_CTL register is set to 1 then an + * ACK bit is transmitted and the IFLG bit is set after each + * byte is received. + */ + + regval |= I2C_CTL_AAK; + } + outp(EZ80_I2C_CTL, regval); + + /* Wait for IFLG to be set meaning that incoming data is + * available in the I2C_DR registers. + */ + + regval = i2c_waitiflg(); + + /* Data byte received in MASTER mode, ACK transmitted */ + + if (regval == I2C_SR_MDATARDACK) + { + /* Since we just ACKed the incoming byte, it must NOT be the last */ + + DEBUGASSERT(count > 1); + + /* Receive the data and clear the IFLGS */ + + *ptr++ = inp(EZ80_I2C_DR); + i2c_clriflg(); + } + + /* Data byte received in MASTER mode, NACK transmitted */ + + else if (regval == I2C_SR_MDATARDNAK) + { + /* Since we just NACKed the incoming byte, it must be the last */ + + DEBUGASSERT(count <= 1); + + /* When all bytes are received and the NACK has been sent, then the + * microcontroller must write 1 to the STP bit in the I2C_CTL + * register. The I2C then transmits a STOP condition, clears + * the STP bit and returns to an idle state. + */ + + i2c_stop(); + i2c_clriflg(); + + ret = OK; + goto success; + } + + /* Arbitration lost in address or data byte */ + + else if (regval == I2C_SR_ARBLOST1) + { + /* Clear the IFLG and break out of the inner loop. + * this will cause the whole transfer to start over + */ + + dbg("Arbitration lost: %02x\n", regval); + i2c_clriflg(); + break; + } + + /* Unexpected status response */ + + else + { + dbg("Unexpected status: %02x\n", regval); + i2c_clriflg(); + ret = -EIO; + goto failure; + } + } + } + ret = -ETIMEDOUT; + +success: +failure: + i2c_semgive(); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_i2cinitialize + * + * Description: + * Initialize the selected I2C port. And return a unique instance of struct + * struct i2c_dev_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameter: + * Port number (for hardware that has mutiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structre reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct i2c_dev_s *up_i2cinitialize(int port) +{ + FAR struct ez80_i2cdev_s *i2c; + uint16 ccr; + ubyte regval; + + if (!g_initialized) + { + /* Set up some initial BRG value */ + + ccr = i2c_getccr(100*1000); + i2c_setccr(ccr); + + /* No GPIO setup is required -- I2C pints, SCL/SDA are not multiplexed */ + + /* This semaphore enforces serialized access for I2C transfers */ + + sem_init(&g_i2csem, 0, 1); + + /* Enable I2C -- but not interrupts */ + + regval = inp(EZ80_I2C_CTL); + regval |= I2C_CTL_ENAB; + outp(EZ80_I2C_CTL, regval); + } + + /* Now, allocate an I2C instance for this caller */ + + i2c = (FAR struct ez80_i2cdev_s *)malloc(sizeof(FAR struct ez80_i2cdev_s)); + if (i2c) + { + /* Initialize the allocated instance */ + + i2c->ops = &g_ops; + i2c->ccr = g_currccr; + } + return (FAR struct i2c_dev_s *)i2c; +} diff --git a/nuttx/arch/z80/src/ez80/ez80f91_i2c.h b/nuttx/arch/z80/src/ez80/ez80f91_i2c.h index 4420db350..b77e56ae4 100644 --- a/nuttx/arch/z80/src/ez80/ez80f91_i2c.h +++ b/nuttx/arch/z80/src/ez80/ez80f91_i2c.h @@ -80,12 +80,43 @@ #define I2C_SR_SHIFT 3 /* Bits 3-7: 5-bit status code */ #define I2C_SR_MASK (0x1c << I2C_SR_SHIFT) + +#define I2C_SR_BUSERR 0x00 /* Bus error */ +#define I2C_SR_MSTART 0x08 /* START condition transmitted */ +#define I2C_SR_MREPSTART 0x10 /* Repeated START condition transmitted */ +#define I2C_SR_MADDRWRACK 0x18 /* Address and Write bit transmitted, ACK received */ +#define I2C_SR_MADDRWR 0x20 /* Address and Write bit transmitted, ACK not received */ +#define I2C_SR_MDATAWRACK 0x28 /* Data byte transmitted in MASTER mode, ACK received */ +#define I2C_SR_MDATAWR 0x30 /* Data byte transmitted in MASTER mode, ACK not received */ +#define I2C_SR_ARBLOST1 0x38 /* Arbitration lost in address or data byte */ +#define I2C_SR_MADDRRDACK 0x40 /* Address and Read bit transmitted, ACK received */ +#define I2C_SR_MADDRRD 0x48 /* Address and Read bit transmitted, ACK not received */ +#define I2C_SR_MDATARDACK 0x50 /* Data byte received in MASTER mode, ACK transmitted */ +#define I2C_SR_MDATARDNAK 0x58 /* Data byte received in MASTER mode, NACK transmitted */ +#define I2C_SR_SADDRWRACK 0x60 /* Slave address and Write bit received, ACK transmitted */ +#define I2C_SR_ARBLOST2 0x68 /* Arbitration lost in address as master, slave address and Write bit received, ACK transmitted */ +#define I2C_SR_SGCARDACK 0x70 /* General Call address received, ACK transmitted */ +#define I2C_SR_ARBLOST3 0x78 /* Arbitration lost in address as master, General Call address received, ACK transmitted */ +#define I2C_SR_SDATARDACK 0x80 /* Data byte received after slave address received, ACK transmitted */ +#define I2C_SR_SDATARDNAK 0x88 /* Data byte received after slave address received, NACK transmitted */ +#define I2C_SR_SDATAGCAACK 0x90 /* Data byte received after General Call received, ACK transmitted */ +#define I2C_SR_SDATAGCANAK 0x98 /* Data byte received after General Call received, NACK transmitted */ +#define I2C_SR_SSTOP 0xa0 /* STOP or repeated START condition received in SLAVE mode */ +#define I2C_SR_SSADDRRDACK 0xa8 /* Slave address and Read bit received, ACK transmitted */ +#define I2C_SR_ARBLOST4 0xb0 /* Arbitration lost in address as master, slave address and Read bit received, ACK transmitted */ +#define I2C_SR_SDATAWRACK 0xb8 /* Data byte transmitted in SLAVE mode, ACK received */ +#define I2C_SR_SDATAWR 0xc0 /* Data byte transmitted in SLAVE mode, ACK not received */ +#define I2C_SR_SLDATAWR 0xc8 /* Last byte transmitted in SLAVE mode, ACK received */ +#define I2C_SR_MADDR2WRACK 0xd0 /* Second Address byte and Write bit transmitted, ACK received */ +#define I2C_SR_MADDR2WR 0xd8 /* Second Address byte and Write bit transmitted, ACK not received */ +#define I2C_SR_NONE 0xf8 /* No relevant status information, IFLG = 0 */ + /* Clock Control Register (CCR) Bit Definitions */ #define I2C_CCR_NSHIFT 0 /* Bits 0-2: I2C clock divider exponent */ #define I2C_CCR_NMASK (0x07 << I2C_CCR_NSHIFT) #define I2C_CCR_MSHIFT 3 /* Bits 3-6: I2C clock divider scalar value */ -#define I2C_CCR_NMASK (0x0f << I2C_CCR_MSHIFT) +#define I2C_CCR_MMASK (0x0f << I2C_CCR_MSHIFT) /* Software Reset Register (SRR) Bit Definitions */ /* Writing any value to this register performs a software reset of the I2C module */ diff --git a/nuttx/include/nuttx/i2c.h b/nuttx/include/nuttx/i2c.h index 96c3bf735..e44684cbd 100644 --- a/nuttx/include/nuttx/i2c.h +++ b/nuttx/include/nuttx/i2c.h @@ -47,10 +47,28 @@ * Definitions ****************************************************************************/ -/* I2C address calculation. Convert 7-bit address to 8-bit read/write address */ +/* I2C address calculation. Convert 7- and 10-bit address to 8-bit and + * 16-bit read/write address + */ + +#define I2C_READBIT 0x01 + +/* Conver 7- to 8-bit address */ + +#define I2C_ADDR8(a) ((a) << 1) +#define I2C_WRITEADDR8(a) I2C_ADDR8(a) +#define I2C_READADDR8(a) (I2C_ADDR8(a) | I2C_READBIT) + +/* Convert 10- to 16-bit address */ + +#define I2C_ADDR10H(a) (0xf0 | (((a) >> 7) & 0x06)) +#define I2C_ADDR10L(a) ((a) & 0xff) + +#define I2C_WRITEADDR10H(a) I2C_ADDR10H(a) +#define I2C_WRITEADDR10L(a) I2C_ADDR10L(a) -#define I2C_READADDR(a) (((a) << 1) | 1) -#define I2C_WRITEADDR(a) ((a) << 1) +#define I2C_READADDR10H(a) (I2C_ADDR10H(a) | I2C_READBIT) +#define I2C_READADDR10L(a) I2C_ADDR10L(a) /* Access macros */ @@ -82,13 +100,14 @@ * Input Parameters: * dev - Device-specific state data * address - The I2C slave address + * nbits - The number of address bits provided (7 or 10) * * Returned Value: * Returns the actual frequency selected * ****************************************************************************/ -#define I2C_SETADDRESS(d,f) ((d)->ops->setaddress(d,f)) +#define I2C_SETADDRESS(d,f,b) ((d)->ops->setaddress(d,f,b)) /**************************************************************************** * Name: I2C_WRITE @@ -142,7 +161,7 @@ struct i2c_dev_s; struct i2c_ops_s { uint32 (*setfrequency)(FAR struct i2c_dev_s *dev, uint32 frequency); - int (*setaddress)(FAR struct i2c_dev_s *dev, int addr); + int (*setaddress)(FAR struct i2c_dev_s *dev, int addr, int nbits); int (*write)(FAR struct i2c_dev_s *dev, const ubyte *buffer, int buflen); int (*read)(FAR struct i2c_dev_s *dev, ubyte *buffer, int buflen); }; -- cgit v1.2.3