From f59a457ba7da70e76fdba829f1b17764dbc1d486 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 15 Apr 2011 22:42:47 +0000 Subject: Add support for SMSC LAN8720 PHY git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3510 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c | 107 +++++++++++++++++++-- nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig | 6 +- nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig | 6 +- .../lpcxpresso-lpc1768/usbstorage/defconfig | 6 +- nuttx/include/nuttx/mii.h | 39 ++++++++ 5 files changed, 154 insertions(+), 10 deletions(-) (limited to 'nuttx') diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c index 5662ec7c7..3efa3df03 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -159,11 +159,21 @@ /* PHYs *********************************************************************/ /* Select PHY-specific values. Add more PHYs as needed. */ -#ifdef CONFIG_PHY_KS8721 +#if defined(CONFIG_PHY_KS8721) # define LPC17_PHYNAME "KS8721" # define LPC17_PHYID1 MII_PHYID1_KS8721 # define LPC17_PHYID2 MII_PHYID2_KS8721 # define LPC17_HAVE_PHY 1 +#elif defined(CONFIG_PHY_DP83848C) +# define LPC17_PHYNAME "DP83848C" +# define LPC17_PHYID1 MII_PHYID1_DP83848C +# define LPC17_PHYID2 MII_PHYID2_DP83848C +# define LPC17_HAVE_PHY 1 +#elif defined(CONFIG_PHY_LAN8720) +# define LPC17_PHYNAME "LAN8720" +# define LPC17_PHYID1 MII_PHYID1_LAN8720 +# define LPC17_PHYID2 MII_PHYID2_LAN8720 +# define LPC17_HAVE_PHY 1 #else # warning "No PHY specified!" # undef LPC17_HAVE_PHY @@ -1763,8 +1773,7 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr) /* Check if auto-negotiation has completed */ phyreg = lpc17_phyread(phyaddr, MII_MSR); - if ((phyreg & (MII_MSR_LINKSTATUS | MII_MSR_ANEGCOMPLETE)) == - (MII_MSR_LINKSTATUS | MII_MSR_ANEGCOMPLETE)) + if ((phyreg & MII_MSR_ANEGCOMPLETE) != 0) { /* Yes.. return success */ @@ -1832,13 +1841,23 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode) for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--) { +#ifdef CONFIG_PHY_DP83848C + phyreg = lpc17_phyread(phyaddr, MII_DP83848C_STS); + if ((phyreg & 0x0001) != 0) + { + /* Yes.. return success */ + + return OK; + } +#else phyreg = lpc17_phyread(phyaddr, MII_MSR); - if (phyreg & MII_MSR_LINKSTATUS) + if ((phyreg & MII_MSR_LINKSTATUS) != 0) { /* Yes.. return success */ return OK; } +#endif } ndbg("Link failed. MSR: %04x\n", phyreg); @@ -1895,16 +1914,19 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) */ phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1); + nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg); + if (phyreg == LPC17_PHYID1) { phyreg = lpc17_phyread(phyaddr, MII_PHYID2); + nvdbg("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg); + if (phyreg == LPC17_PHYID2) { break; } } } - nvdbg("phyaddr: %d\n", phyaddr); /* Check if the PHY device address was found */ @@ -1912,8 +1934,10 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) { /* Failed to find PHY at any location */ + ndbg("No PHY detected\n"); return -ENODEV; } + nvdbg("phyaddr: %d\n", phyaddr); /* Save the discovered PHY device address */ @@ -1973,7 +1997,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) /* Check configuration */ -#ifdef CONFIG_PHY_KS8721 +#if defined(CONFIG_PHY_KS8721) phyreg = lpc17_phyread(phyaddr, MII_KS8721_10BTCR); switch (phyreg & KS8721_10BTCR_MODE_MASK) @@ -1993,9 +2017,78 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) priv->lp_mode = LPC17_100BASET_FD; break; default: - dbg("Unrecognized mode: %04x\n", phyreg); + ndbg("Unrecognized mode: %04x\n", phyreg); return -ENODEV; } +#elif defined(CONFIG_PHY_DP83848C) + phyreg = lpc17_phyread(phyaddr, MII_DP83848C_STS); + + /* Configure for full/half duplex mode and speed */ + + switch (phyreg & 0x0006) + { + case 0x0000: + priv->lp_mode = LPC17_100BASET_HD; + break; + case 0x0002: + priv->lp_mode = LPC17_10BASET_HD; + break; + case 0x0004: + priv->lp_mode = LPC17_100BASET_FD; + break; + case 0x0006: + priv->lp_mode = LPC17_10BASET_FD; + break; + default: + ndbg("Unrecognized mode: %04x\n", phyreg); + return -ENODEV; + } +#elif defined(CONFIG_PHY_LAN8720) + { + uint16_t advertise; + uint16_t lpa; + + up_udelay(500); + advertise = lpc17_phyread(phyaddr, MII_ADVERTISE); + lpa = lpc17_phyread(phyaddr, MII_LPA); + + /* Check for 100BASETX full duplex */ + + if ((advertise & MII_ADVERTISE_100BASETXFULL) != 0 && + (lpa & MII_LPA_100BASETXFULL) != 0) + { + priv->lp_mode = LPC17_100BASET_FD; + } + + /* Check for 100BASETX half duplex */ + + else if ((advertise & MII_ADVERTISE_100BASETXHALF) != 0 && + (lpa & MII_LPA_100BASETXHALF) != 0) + { + priv->lp_mode = LPC17_100BASET_HD; + } + + /* Check for 10BASETX full duplex */ + + else if ((advertise & MII_ADVERTISE_10BASETXFULL) != 0 && + (lpa & MII_LPA_10BASETXFULL) != 0) + { + priv->lp_mode = LPC17_10BASET_FD; + } + + /* Check for 10BASETX half duplex */ + + else if ((advertise & MII_ADVERTISE_10BASETXHALF) != 0 && + (lpa & MII_LPA_10BASETXHALF) != 0) + { + priv->lp_mode = LPC17_10BASET_HD; + } + else + { + ndbg("Unrecognized mode: %04x\n", phyreg); + return -ENODEV; + } + } #else # warning "PHY Unknown: speed and duplex are bogus" #endif diff --git a/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig b/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig index 10aa9e5f2..3b71b7172 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -188,6 +188,8 @@ CONFIG_UART3_2STOP=0 # LPC17xx specific PHY/Ethernet device driver settings # # CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY +# CONFIG_PHY_DP83848C - Selects National Semiconductor DP83848C PHY +# CONFIG_PHY_LAN8720 - Selects SMSC LAN8720 PHY # CONFIG_PHY_AUTONEG - Enable auto-negotion # CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. # CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex @@ -205,7 +207,9 @@ CONFIG_UART3_2STOP=0 # CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames. # Automatically set if CONFIG_NET_IGMP is selected. # -CONFIG_PHY_KS8721=y +CONFIG_PHY_KS8721=n +CONFIG_PHY_DP83848C=n +CONFIG_PHY_LAN8720=y CONFIG_PHY_AUTONEG=y CONFIG_PHY_SPEED100=n CONFIG_PHY_FDUPLEX=y diff --git a/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig b/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig index 0e32576eb..770252766 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig @@ -188,6 +188,8 @@ CONFIG_UART3_2STOP=0 # LPC17xx specific PHY/Ethernet device driver settings # # CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY +# CONFIG_PHY_DP83848C - Selects National Semiconductor DP83848C PHY +# CONFIG_PHY_LAN8720 - Selects SMSC LAN8720 PHY # CONFIG_PHY_AUTONEG - Enable auto-negotion # CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. # CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex @@ -203,7 +205,9 @@ CONFIG_UART3_2STOP=0 # CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames. # Automatically set if CONFIG_NET_IGMP is selected. # -CONFIG_PHY_KS8721=y +CONFIG_PHY_KS8721=n +CONFIG_PHY_DP83848C=n +CONFIG_PHY_LAN8720=y CONFIG_PHY_AUTONEG=y CONFIG_PHY_SPEED100=n CONFIG_PHY_FDUPLEX=y diff --git a/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig b/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig index abb4f6761..79f59228f 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig @@ -188,6 +188,8 @@ CONFIG_UART3_2STOP=0 # LPC17xx specific PHY/Ethernet device driver settings # # CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY +# CONFIG_PHY_DP83848C - Selects National Semiconductor DP83848C PHY +# CONFIG_PHY_LAN8720 - Selects SMSC LAN8720 PHY # CONFIG_PHY_AUTONEG - Enable auto-negotion # CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. # CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex @@ -203,7 +205,9 @@ CONFIG_UART3_2STOP=0 # CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames. # Automatically set if CONFIG_NET_IGMP is selected. # -CONFIG_PHY_KS8721=y +CONFIG_PHY_KS8721=n +CONFIG_PHY_DP83848C=n +CONFIG_PHY_LAN8720=y CONFIG_PHY_AUTONEG=y CONFIG_PHY_SPEED100=n CONFIG_PHY_FDUPLEX=y diff --git a/nuttx/include/nuttx/mii.h b/nuttx/include/nuttx/mii.h index 5b82ac600..ea63b154b 100644 --- a/nuttx/include/nuttx/mii.h +++ b/nuttx/include/nuttx/mii.h @@ -110,6 +110,33 @@ #define MII_KS8721_INTCS 0x1b /* Interrupt control/status register */ #define MII_KS8721_10BTCR 0x1f /* 10BASE-TX PHY control register */ +/* National Semiconductor DP83848C PHY Extended Registers */ + +#define MII_DP83848C_STS 0x10 /* Status Register */ +#define MII_DP83848C_MICR 0x11 /* MII Interrupt Control Register */ +#define MII_DP83848C_MISR 0x12 /* MII Interrupt Status Register */ +#define MII_DP83848C_FCSCR 0x14 /* False Carrier Sense Counter */ +#define MII_DP83848C_RECR 0x15 /* Receive Error Counter */ +#define MII_DP83848C_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define MII_DP83848C_RBR 0x17 /* RMII and Bypass Register */ +#define MII_DP83848C_LEDCR 0x18 /* LED Direct Control Register */ +#define MII_DP83848C_PHYCR 0x19 /* PHY Control Register */ +#define MII_DP83848C_10BTSCR 0x1a /* 10Base-T Status/Control Register */ +#define MII_DP83848C_CDCTRL1 0x1b /* CD Test Control and BIST Extens */ +#define MII_DP83848C_EDCR 0x1d /* Energy Detect Control Register */ + +/* SMSC LAN8720 PHY Extended Registers */ + +#define MII_LAN8720_REV 0x10 /* Silicon Revision Register */ +#define MII_LAN8720_MCSR 0x11 /* Mode Control/Status Register */ +#define MII_LAN8720_MODES 0x12 /* Special modes */ +#define MII_LAN8720_SECR 0x1a /* Symbol Error Counter Register */ +#define MII_LAN8720_CSIR 0x1b /* Control / Status Indicator Register */ +#define MII_LAN8720_SITC 0x1c /* Special Internal Testability Controls */ +#define MII_LAN8720_ISR 0x1d /* Interrupt Source Register */ +#define MII_LAN8720_IMR 0x1e /* Interrupt Mask Register */ +#define MII_LAN8720_SCSR 0x1f /* PHY Special Control/Status Register */ + /* GMII */ #define GMII_MCR MII_MCR /* GMII management control */ @@ -241,6 +268,18 @@ #define DP83840_PHYADDR_DUPLEX (1 << 7) #define DP83840_PHYADDR_SPEED (1 << 6) +/* National Semiconductor DP83848C ******************************************/ +/* DP83848C MII ID1/2 register bits */ + +#define MII_PHYID1_DP83848C 0x2000 /* ID1 value for DP83848C */ +#define MII_PHYID2_DP83848C 0x5c90 /* ID2 value for DP83848C */ + +/* SMSC LAN8720 *************************************************************/ +/* SMSC LAN8720 MII ID1/2 register bits */ + +#define MII_PHYID1_LAN8720 0x0007 /* ID1 value for LAN8720 */ +#define MII_PHYID2_LAN8720 0xc0f1 /* ID2 value for LAN8720 */ + /* Am79c874-specific register bit settings **********************************/ /* Am79c874 MII ID1/2 register bits */ -- cgit v1.2.3