############################################################################
# arch/arm/src/sam34/Make.defs
#
#   Copyright (C) 2009-2011, 2013-2015 Gregory Nutt. All rights reserved.
#   Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in
#    the documentation and/or other materials provided with the
#    distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
#    used to endorse or promote products derived from this software
#    without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################

# The start-up, "head", file

ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
HEAD_ASRC =
else
HEAD_ASRC = sam_vectors.S
endif

# Common ARM and Cortex-M3 files

CMN_UASRCS =
CMN_UCSRCS =

CMN_ASRCS  = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_ASRCS += vfork.S
CMN_CSRCS  = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c
CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c
CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c
CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c

# Configuration-dependent common files

ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S
else
CMN_ASRCS += up_exception.S
endif
CMN_CSRCS += up_vectors.c
endif

ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif

ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif

ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y)
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
endif

ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
endif

ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif

ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif

# Required SAM3/4 files

CHIP_ASRCS  =
CHIP_CSRCS  = sam_allocateheap.c sam_gpioirq.c sam_irq.c sam_lowputc.c
CHIP_CSRCS += sam_serial.c sam_start.c

# Configuration-dependent SAM3/4 files

ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CHIP_ASRCS += sam_vectors.S
endif

ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif

ifeq ($(CONFIG_CRYPTO_AES),y)
CHIP_CSRCS += sam_aes.c
endif

ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y)
CHIP_CSRCS += sam4cm_supc.c
endif

ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
CHIP_CSRCS += sam4l_clockconfig.c sam4l_periphclks.c sam4l_gpio.c
else
CHIP_CSRCS += sam_clockconfig.c sam_gpio.c
endif

ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += sam_userspace.c sam_mpuinit.c
endif

ifeq ($(CONFIG_SAM34_CMCC),y)
CHIP_CSRCS += sam_cmcc.c
endif

ifeq ($(CONFIG_SAM34_DMAC0),y)
CHIP_CSRCS += sam_dmac.c
endif

ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
ifeq ($(CONFIG_SAM34_PDCA),y)
CHIP_CSRCS += sam4l_pdca.c
endif
endif

ifeq ($(CONFIG_SAM34_EMAC),y)
CHIP_CSRCS += sam_emac.c
endif

ifeq ($(CONFIG_SAM34_UDP),y)
CHIP_CSRCS += sam_udp.c
endif

ifeq ($(CONFIG_SAM34_HSMCI),y)
CHIP_CSRCS += sam_hsmci.c
endif

ifeq ($(CONFIG_SAM34_SPI0),y)
CHIP_CSRCS += sam_spi.c
else
ifeq ($(CONFIG_SAM34_SPI1),y)
CHIP_CSRCS += sam_spi.c
endif
endif

ifeq ($(CONFIG_SAM34_AES),y)
CHIP_CSRCS += sam_aes.c
endif

ifeq ($(CONFIG_SAM34_RTC),y)
CHIP_CSRCS += sam_rtc.c
endif

ifeq ($(CONFIG_SAM34_RTT),y)
CHIP_CSRCS += sam_rtt.c
endif

ifeq ($(CONFIG_SAM34_WDT),y)
CHIP_CSRCS += sam_wdt.c
endif

ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += sam_tc.c
endif

ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y)
ifeq ($(CONFIG_SAM34_TC),y)
CHIP_CSRCS += sam4cm_tc.c
ifeq ($(CONFIG_SAM34_ONESHOT),y)
CHIP_CSRCS += sam4cm_oneshot.c
endif
ifeq ($(CONFIG_SAM34_FREERUN),y)
CHIP_CSRCS += sam4cm_freerun.c
endif
ifeq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam4cm_tickless.c
endif
endif
endif