############################################################################
# arch/arm/sama5/Make.defs
#
#   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
#   Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in
#    the documentation and/or other materials provided with the
#    distribution.
# 3. Neither the name Gregory Nutt nor the names of its contributors may be
#    used to endorse or promote products derived from this software
#    without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################

# The vector table is the "head" object, i.e., the one that must forced into
# the link in order to draw in all of the other components

HEAD_ASRC  = arm_vectortab.S

ifeq ($(CONFIG_BUILD_KERNEL),y)
STARTUP_OBJS = crt0$(OBJEXT)
endif

# Force the start-up logic to be at the beginning of the .text to simplify
# debug.

ifeq ($(CONFIG_PAGING),y)
CMN_ASRCS  = arm_pghead.S
else
CMN_ASRCS  = arm_head.S
endif

# Common assembly language files

CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S
CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S

# Configuration dependent assembly language files

ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += arm_memcpy.S
endif

# Common C source files

CMN_CSRCS  = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
CMN_CSRCS += up_createstack.c up_releasestack.c up_usestack.c up_vfork.c
CMN_CSRCS += up_puts.c up_mdelay.c up_stackframe.c up_udelay.c
CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c

CMN_CSRCS += arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_dataabort.c
CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c
CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c

# Configuration dependent C files

ifeq ($(CONFIG_ARMV7A_L2CC_PL310),y)
CMN_CSRCS += arm_l2cc_pl310.c
endif

ifeq ($(CONFIG_PAGING),y)
CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c
CMN_CSRCS += arm_va2pte.c
endif

ifeq ($(CONFIG_BUILD_KERNEL),y)
CMN_CSRCS += up_task_start.c up_pthread_start.c arm_signal_dispatch.c
endif

ifeq ($(CONFIG_ARCH_ADDRENV),y)
CMN_CSRCS += arm_addrenv.c arm_addrenv_utils.c arm_pgalloc.c
ifeq ($(CONFIG_ARCH_STACK_DYNAMIC),y)
CMN_CSRCS += arm_addrenv_ustack.c
endif
ifeq ($(CONFIG_ARCH_KERNEL_STACK),y)
CMN_CSRCS += arm_addrenv_kstack.c
endif
ifeq ($(CONFIG_MM_SHM),y)
CMN_CSRCS += arm_addrenv_shm.c
endif
endif

ifeq ($(CONFIG_MM_PGALLOC),y)
CMN_CSRCS += arm_physpgaddr.c
ifeq ($(CONFIG_ARCH_PGPOOL_MAPPING),y)
CMN_CSRCS += arm_virtpgaddr.c
endif
endif

ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c
endif

ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S
CMN_CSRCS += arm_copyarmstate.c
endif

ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif

# SAMA5-specific assembly language files

CHIP_ASRCS  =

# SAMA5-specific C source files

CHIP_CSRCS  = sam_allocateheap.c sam_boot.c sam_clockconfig.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_memories.c sam_pck.c sam_pio.c sam_pmc.c
CHIP_CSRCS += sam_sckc.c sam_serial.c

# Configuration dependent C and assembly language files

ifeq ($(CONFIG_MM_PGALLOC),y)
CHIP_CSRCS += sam_pgalloc.c
endif

ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif

ifeq ($(CONFIG_SAMA5_DMAC0),y)
CHIP_CSRCS += sam_dmac.c
else
ifeq ($(CONFIG_SAMA5_DMAC1),y)
CHIP_CSRCS += sam_dmac.c
endif
endif

ifeq ($(CONFIG_SAMA5_XDMAC0),y)
CHIP_CSRCS += sam_xdmac.c
else
ifeq ($(CONFIG_SAMA5_XDMAC1),y)
CHIP_CSRCS += sam_xdmac.c
endif
endif

ifeq ($(CONFIG_SAMA5_PIO_IRQ),y)
CHIP_CSRCS += sam_pioirq.c
endif

ifeq ($(CONFIG_SAMA5_RTC),y)
CHIP_CSRCS += sam_rtc.c
endif

ifeq ($(CONFIG_SAMA5_WDT),y)
CHIP_CSRCS += sam_wdt.c
endif

ifeq ($(CONFIG_SAMA5_DBGU),y)
CHIP_CSRCS += sam_dbgu.c
endif

ifeq ($(CONFIG_SAMA5_TRNG),y)
CHIP_CSRCS += sam_trng.c
endif

ifeq ($(CONFIG_SAMA5_SPI0),y)
CHIP_CSRCS += sam_spi.c
else
ifeq ($(CONFIG_SAMA5_SPI1),y)
CHIP_CSRCS += sam_spi.c
else
endif
endif

ifeq ($(CONFIG_SAMA5_SSC0),y)
CHIP_CSRCS += sam_ssc.c
else
ifeq ($(CONFIG_SAMA5_SSC1),y)
CHIP_CSRCS += sam_ssc.c
else
endif
endif

ifeq ($(CONFIG_SAMA5_LCDC),y)
CHIP_CSRCS += sam_lcd.c
endif

ifeq ($(CONFIG_SAMA5_UHPHS),y)
ifeq ($(CONFIG_SAMA5_OHCI),y)
CHIP_CSRCS += sam_ohci.c
endif
ifeq ($(CONFIG_SAMA5_EHCI),y)
CHIP_CSRCS += sam_ehci.c
endif
endif

ifeq ($(CONFIG_SAMA5_UDPHS),y)
CHIP_CSRCS += sam_udphs.c
endif

ifeq ($(CONFIG_USBHOST),y)
ifeq ($(CONFIG_USBHOST_TRACE),y)
CHIP_CSRCS += sam_usbhost.c
else
ifeq ($(CONFIG_DEBUG_USB),y)
CHIP_CSRCS += sam_usbhost.c
endif
endif
endif

ifeq ($(CONFIG_SAMA5_HSMCI0),y)
CHIP_CSRCS += sam_hsmci.c sam_hsmci_clkdiv.c
else
ifeq ($(CONFIG_SAMA5_HSMCI1),y)
CHIP_CSRCS += sam_hsmci.c sam_hsmci_clkdiv.c
else
ifeq ($(CONFIG_SAMA5_HSMCI2),y)
CHIP_CSRCS += sam_hsmci.c sam_hsmci_clkdiv.c
endif
endif
endif

ifeq ($(CONFIG_NET),y)
CHIP_CSRCS += sam_ethernet.c
ifeq ($(CONFIG_SAMA5_EMACA),y)
CHIP_CSRCS += sam_emaca.c
endif
ifeq ($(CONFIG_SAMA5_EMACB),y)
CHIP_CSRCS += sam_emacb.c
endif
ifeq ($(CONFIG_SAMA5_GMAC),y)
CHIP_CSRCS += sam_gmac.c
endif
endif

ifeq ($(CONFIG_SAMA5_CAN0),y)
CHIP_CSRCS += sam_can.c
else
ifeq ($(CONFIG_SAMA5_CAN1),y)
CHIP_CSRCS += sam_can.c
endif
endif

ifeq ($(CONFIG_SAMA5_TWI0),y)
CHIP_CSRCS += sam_twi.c
else
ifeq ($(CONFIG_SAMA5_TWI1),y)
CHIP_CSRCS += sam_twi.c
else
ifeq ($(CONFIG_SAMA5_TWI2),y)
CHIP_CSRCS += sam_twi.c
endif
endif
endif

ifeq ($(CONFIG_SAMA5_ADC),y)
CHIP_CSRCS += sam_adc.c
ifeq ($(CONFIG_SAMA5_TSD),y)
CHIP_CSRCS += sam_tsd.c
endif
endif

ifeq ($(CONFIG_SAMA5_PWM),y)
CHIP_CSRCS += sam_pwm.c
endif

ifeq ($(CONFIG_SAMA5_HAVE_TC),y)
CHIP_CSRCS += sam_tc.c
ifeq ($(CONFIG_SAMA5_ONESHOT),y)
CHIP_CSRCS += sam_oneshot.c
endif
ifeq ($(CONFIG_SAMA5_FREERUN),y)
CHIP_CSRCS += sam_freerun.c
endif
ifeq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_tickless.c
endif
endif

ifeq ($(CONFIG_SAMA5_EBICS0_NAND),y)
CHIP_CSRCS += sam_nand.c sam_pmecc.c sam_gf512.c sam_gf1024.c
else
ifeq ($(CONFIG_SAMA5_EBICS1_NAND),y)
CHIP_CSRCS += sam_nand.c sam_pmecc.c sam_gf512.c sam_gf1024.c
else
ifeq ($(CONFIG_SAMA5_EBICS2_NAND),y)
CHIP_CSRCS += sam_nand.c sam_pmecc.c sam_gf512.c sam_gf1024.c
else
ifeq ($(CONFIG_SAMA5_EBICS3_NAND),y)
CHIP_CSRCS += sam_nand.c sam_pmecc.c sam_gf512.c sam_gf1024.c
endif
endif
endif
endif