1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
|
/************************************************************************************
* arch/arm/src/tiva/chip/tiva_timer.h
*
* Originally:
*
* Copyright (C) 2012, 2014 Max Nekludov. All rights reserved.
* Author: Max Nekludov <macscomp@gmail.com>
*
* Ongoing support and major revision to support the TM4C129 family
* (essentially a full file replacement):
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some bitfield definitions taken from a header file provided by:
*
* Copyright (C) 2014 TRD2 Inc. All rights reserved.
* Author: Calvin Maguranis <calvin.maguranis@trd2inc.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CHIP_TIVA_TIMER_H
#define __ARCH_ARM_SRC_TIVA_CHIP_TIVA_TIMER_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/tiva/chip.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* GPTM register offsets ************************************************************/
#define TIVA_TIMER_CFG_OFFSET 0x0000 /* GPTM Configuration */
#define TIVA_TIMER_TAMR_OFFSET 0x0004 /* GPTM Timer A Mode */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_TBMR_OFFSET 0x0008 /* GPTM Timer B Mode */
#endif
#define TIVA_TIMER_CTL_OFFSET 0x000c /* GPTM Control */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_SYNC_OFFSET 0x0010 /* GPTM Synchronize */
#endif
#define TIVA_TIMER_IMR_OFFSET 0x0018 /* GPTM Interrupt Mask */
#define TIVA_TIMER_RIS_OFFSET 0x001c /* GPTM Raw Interrupt Status */
#define TIVA_TIMER_ICR_OFFSET 0x0024 /* GPTM Interrupt Clear */
#define TIVA_TIMER_TAILR_OFFSET 0x0028 /* GPTM Timer A Interval Load */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_TBILR_OFFSET 0x002c /* GPTM Timer B Interval Load */
# define TIVA_TIMER_TAMATCHR_OFFSET 0x0030 /* GPTM Timer A Match */
# define TIVA_TIMER_TBMATCHR_OFFSET 0x0034 /* GPTM Timer B Match */
# define TIVA_TIMER_TAPR_OFFSET 0x0038 /* GPTM Timer A Prescale */
# define TIVA_TIMER_TBPR_OFFSET 0x003c /* GPTM Timer B Prescale */
# define TIVA_TIMER_TAPMR_OFFSET 0x0040 /* GPTM TimerA Prescale Match */
# define TIVA_TIMER_TBPMR_OFFSET 0x0044 /* GPTM TimerB Prescale Match */
#endif
#define TIVA_TIMER_TAR_OFFSET 0x0048 /* GPTM Timer A */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_TBR_OFFSET 0x004c /* GPTM Timer B */
# define TIVA_TIMER_TAV_OFFSET 0x0050 /* GPTM Timer A Value */
# define TIVA_TIMER_TBV_OFFSET 0x0054 /* GPTM Timer B Value */
# define TIVA_TIMER_RTCPD_OFFSET 0x0058 /* GPTM RTC Predivide */
# define TIVA_TIMER_TAPS_OFFSET 0x005c /* GPTM Timer A Prescale Snapshot */
# define TIVA_TIMER_TBPS_OFFSET 0x0060 /* GPTM Timer B Prescale Snapshot */
# define TIVA_TIMER_DMAEV_OFFSET 0x006c /* GPTM DMA Event */
# define TIVA_TIMER_ADCEV_OFFSET 0x0070 /* GPTM ADC Event */
# define TIVA_TIMER_PP_OFFSET 0x0fc0 /* GPTM Peripheral Properties */
# define TIVA_TIMER_CC_OFFSET 0x0fc8 /* GPTM Clock Configuration */
#endif
/* GPTM register addresses **********************************************************/
#if TIVA_NTIMERS > 0
#define TIVA_TIMER0_CFG (TIVA_TIMER0_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER0_TAMR (TIVA_TIMER0_BASE + TIVA_TIMER_TAMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER0_TBMR (TIVA_TIMER0_BASE + TIVA_TIMER_TBMR_OFFSET)
#endif
#define TIVA_TIMER0_CTL (TIVA_TIMER0_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER0_SYNC (TIVA_TIMER0_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER0_IMR (TIVA_TIMER0_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER0_RIS (TIVA_TIMER0_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER0_ICR (TIVA_TIMER0_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER0_TAILR (TIVA_TIMER0_BASE + TIVA_TIMER_TAILR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER0_TBILR (TIVA_TIMER0_BASE + TIVA_TIMER_TBILR_OFFSET)
# define TIVA_TIMER0_TAMATCHR (TIVA_TIMER0_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
# define TIVA_TIMER0_TBMATCHR (TIVA_TIMER0_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
# define TIVA_TIMER0_TAPR (TIVA_TIMER0_BASE + TIVA_TIMER_TAPR_OFFSET)
# define TIVA_TIMER0_TBPR (TIVA_TIMER0_BASE + TIVA_TIMER_TBPR_OFFSET)
# define TIVA_TIMER0_TAPMR (TIVA_TIMER0_BASE + TIVA_TIMER_TAPMR_OFFSET)
# define TIVA_TIMER0_TBPMR (TIVA_TIMER0_BASE + TIVA_TIMER_TBPMR_OFFSET)
#endif
#define TIVA_TIMER0_TAR (TIVA_TIMER0_BASE + TIVA_TIMER_TAR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER0_TBR (TIVA_TIMER0_BASE + TIVA_TIMER_TBR_OFFSET)
# define TIVA_TIMER0_TAV (TIVA_TIMER0_BASE + TIVA_TIMER_TAV_OFFSET)
# define TIVA_TIMER0_TBV (TIVA_TIMER0_BASE + TIVA_TIMER_TBV_OFFSET)
# define TIVA_TIMER0_RTCPD (TIVA_TIMER0_BASE + TIVA_TIMER_RTCPD_OFFSET)
# define TIVA_TIMER0_TAPS (TIVA_TIMER0_BASE + TIVA_TIMER_TAPS_OFFSET)
# define TIVA_TIMER0_TBPS (TIVA_TIMER0_BASE + TIVA_TIMER_TBPS_OFFSET)
# define TIVA_TIMER0_DMAEV (TIVA_TIMER0_BASE + TIVA_TIMER_DMAEV_OFFSET)
# define TIVA_TIMER0_ADCEV (TIVA_TIMER0_BASE + TIVA_TIMER_ADCEV_OFFSET)
# define TIVA_TIMER0_PP (TIVA_TIMER0_BASE + TIVA_TIMER_PP_OFFSET)
# define TIVA_TIMER0_CC (TIVA_TIMER0_BASE + TIVA_TIMER_CC_OFFSET)
#endif
#endif /* TIVA_NTIMERS > 0 */
#if TIVA_NTIMERS > 1
#define TIVA_TIMER1_CFG (TIVA_TIMER1_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER1_TAMR (TIVA_TIMER1_BASE + TIVA_TIMER_TAMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER1_TBMR (TIVA_TIMER1_BASE + TIVA_TIMER_TBMR_OFFSET)
#endif
#define TIVA_TIMER1_CTL (TIVA_TIMER1_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER1_SYNC (TIVA_TIMER1_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER1_IMR (TIVA_TIMER1_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER1_RIS (TIVA_TIMER1_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER1_ICR (TIVA_TIMER1_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER1_TAILR (TIVA_TIMER1_BASE + TIVA_TIMER_TAILR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER1_TBILR (TIVA_TIMER1_BASE + TIVA_TIMER_TBILR_OFFSET)
# define TIVA_TIMER1_TAMATCHR (TIVA_TIMER1_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
# define TIVA_TIMER1_TBMATCHR (TIVA_TIMER1_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
# define TIVA_TIMER1_TAPR (TIVA_TIMER1_BASE + TIVA_TIMER_TAPR_OFFSET)
# define TIVA_TIMER1_TBPR (TIVA_TIMER1_BASE + TIVA_TIMER_TBPR_OFFSET)
# define TIVA_TIMER1_TAPMR (TIVA_TIMER1_BASE + TIVA_TIMER_TAPMR_OFFSET)
# define TIVA_TIMER1_TBPMR (TIVA_TIMER1_BASE + TIVA_TIMER_TBPMR_OFFSET)
#endif
#define TIVA_TIMER1_TAR (TIVA_TIMER1_BASE + TIVA_TIMER_TAR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER1_TBR (TIVA_TIMER1_BASE + TIVA_TIMER_TBR_OFFSET)
# define TIVA_TIMER1_TAV (TIVA_TIMER1_BASE + TIVA_TIMER_TAV_OFFSET)
# define TIVA_TIMER1_TBV (TIVA_TIMER1_BASE + TIVA_TIMER_TBV_OFFSET)
# define TIVA_TIMER1_RTCPD (TIVA_TIMER1_BASE + TIVA_TIMER_RTCPD_OFFSET)
# define TIVA_TIMER1_TAPS (TIVA_TIMER1_BASE + TIVA_TIMER_TAPS_OFFSET)
# define TIVA_TIMER1_TBPS (TIVA_TIMER1_BASE + TIVA_TIMER_TBPS_OFFSET)
# define TIVA_TIMER1_DMAEV (TIVA_TIMER1_BASE + TIVA_TIMER_DMAEV_OFFSET)
# define TIVA_TIMER1_ADCEV (TIVA_TIMER1_BASE + TIVA_TIMER_ADCEV_OFFSET)
# define TIVA_TIMER1_PP (TIVA_TIMER1_BASE + TIVA_TIMER_PP_OFFSET)
# define TIVA_TIMER1_CC (TIVA_TIMER1_BASE + TIVA_TIMER_CC_OFFSET)
#endif
#endif /* TIVA_NTIMERS > 1 */
#if TIVA_NTIMERS > 2
#define TIVA_TIMER2_CFG (TIVA_TIMER2_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER2_TAMR (TIVA_TIMER2_BASE + TIVA_TIMER_TAMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER2_TBMR (TIVA_TIMER2_BASE + TIVA_TIMER_TBMR_OFFSET)
#endif
#define TIVA_TIMER2_CTL (TIVA_TIMER2_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER2_SYNC (TIVA_TIMER2_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER2_IMR (TIVA_TIMER2_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER2_RIS (TIVA_TIMER2_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER2_ICR (TIVA_TIMER2_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER2_TAILR (TIVA_TIMER2_BASE + TIVA_TIMER_TAILR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER2_TBILR (TIVA_TIMER2_BASE + TIVA_TIMER_TBILR_OFFSET)
# define TIVA_TIMER2_TAMATCHR (TIVA_TIMER2_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
# define TIVA_TIMER2_TBMATCHR (TIVA_TIMER2_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
# define TIVA_TIMER2_TAPR (TIVA_TIMER2_BASE + TIVA_TIMER_TAPR_OFFSET)
# define TIVA_TIMER2_TBPR (TIVA_TIMER2_BASE + TIVA_TIMER_TBPR_OFFSET)
# define TIVA_TIMER2_TAPMR (TIVA_TIMER2_BASE + TIVA_TIMER_TAPMR_OFFSET)
# define TIVA_TIMER2_TBPMR (TIVA_TIMER2_BASE + TIVA_TIMER_TBPMR_OFFSET)
#endif
#define TIVA_TIMER2_TAR (TIVA_TIMER2_BASE + TIVA_TIMER_TAR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER2_TBR (TIVA_TIMER2_BASE + TIVA_TIMER_TBR_OFFSET)
# define TIVA_TIMER2_TAV (TIVA_TIMER2_BASE + TIVA_TIMER_TAV_OFFSET)
# define TIVA_TIMER2_TBV (TIVA_TIMER2_BASE + TIVA_TIMER_TBV_OFFSET)
# define TIVA_TIMER2_RTCPD (TIVA_TIMER2_BASE + TIVA_TIMER_RTCPD_OFFSET)
# define TIVA_TIMER2_TAPS (TIVA_TIMER2_BASE + TIVA_TIMER_TAPS_OFFSET)
# define TIVA_TIMER2_TBPS (TIVA_TIMER2_BASE + TIVA_TIMER_TBPS_OFFSET)
# define TIVA_TIMER2_DMAEV (TIVA_TIMER2_BASE + TIVA_TIMER_DMAEV_OFFSET)
# define TIVA_TIMER2_ADCEV (TIVA_TIMER2_BASE + TIVA_TIMER_ADCEV_OFFSET)
# define TIVA_TIMER2_PP (TIVA_TIMER2_BASE + TIVA_TIMER_PP_OFFSET)
# define TIVA_TIMER2_CC (TIVA_TIMER2_BASE + TIVA_TIMER_CC_OFFSET)
#endif
#endif /* TIVA_NTIMERS > 2 */
#if TIVA_NTIMERS > 3
#define TIVA_TIMER3_CFG (TIVA_TIMER3_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER3_TAMR (TIVA_TIMER3_BASE + TIVA_TIMER_TAMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER3_TBMR (TIVA_TIMER3_BASE + TIVA_TIMER_TBMR_OFFSET)
#endif
#define TIVA_TIMER3_CTL (TIVA_TIMER3_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER3_SYNC (TIVA_TIMER3_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER3_IMR (TIVA_TIMER3_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER3_RIS (TIVA_TIMER3_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER3_ICR (TIVA_TIMER3_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER3_TAILR (TIVA_TIMER3_BASE + TIVA_TIMER_TAILR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER3_TBILR (TIVA_TIMER3_BASE + TIVA_TIMER_TBILR_OFFSET)
# define TIVA_TIMER3_TAMATCHR (TIVA_TIMER3_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
# define TIVA_TIMER3_TBMATCHR (TIVA_TIMER3_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
# define TIVA_TIMER3_TAPR (TIVA_TIMER3_BASE + TIVA_TIMER_TAPR_OFFSET)
# define TIVA_TIMER3_TBPR (TIVA_TIMER3_BASE + TIVA_TIMER_TBPR_OFFSET)
# define TIVA_TIMER3_TAPMR (TIVA_TIMER3_BASE + TIVA_TIMER_TAPMR_OFFSET)
# define TIVA_TIMER3_TBPMR (TIVA_TIMER3_BASE + TIVA_TIMER_TBPMR_OFFSET)
#endif
#define TIVA_TIMER3_TAR (TIVA_TIMER3_BASE + TIVA_TIMER_TAR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER3_TBR (TIVA_TIMER3_BASE + TIVA_TIMER_TBR_OFFSET)
# define TIVA_TIMER3_TAV (TIVA_TIMER3_BASE + TIVA_TIMER_TAV_OFFSET)
# define TIVA_TIMER3_TBV (TIVA_TIMER3_BASE + TIVA_TIMER_TBV_OFFSET)
# define TIVA_TIMER3_RTCPD (TIVA_TIMER3_BASE + TIVA_TIMER_RTCPD_OFFSET)
# define TIVA_TIMER3_TAPS (TIVA_TIMER3_BASE + TIVA_TIMER_TAPS_OFFSET)
# define TIVA_TIMER3_TBPS (TIVA_TIMER3_BASE + TIVA_TIMER_TBPS_OFFSET)
# define TIVA_TIMER3_DMAEV (TIVA_TIMER3_BASE + TIVA_TIMER_DMAEV_OFFSET)
# define TIVA_TIMER3_ADCEV (TIVA_TIMER3_BASE + TIVA_TIMER_ADCEV_OFFSET)
# define TIVA_TIMER3_PP (TIVA_TIMER3_BASE + TIVA_TIMER_PP_OFFSET)
# define TIVA_TIMER3_CC (TIVA_TIMER3_BASE + TIVA_TIMER_CC_OFFSET)
#endif
#endif /* TIVA_NTIMERS > 3 */
#if TIVA_NTIMERS > 4
#define TIVA_TIMER4_CFG (TIVA_TIMER4_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER4_TAMR (TIVA_TIMER4_BASE + TIVA_TIMER_TAMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER4_TBMR (TIVA_TIMER4_BASE + TIVA_TIMER_TBMR_OFFSET)
#endif
#define TIVA_TIMER4_CTL (TIVA_TIMER4_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER4_SYNC (TIVA_TIMER4_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER4_IMR (TIVA_TIMER4_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER4_RIS (TIVA_TIMER4_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER4_ICR (TIVA_TIMER4_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER4_TAILR (TIVA_TIMER4_BASE + TIVA_TIMER_TAILR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER4_TBILR (TIVA_TIMER4_BASE + TIVA_TIMER_TBILR_OFFSET)
# define TIVA_TIMER4_TAMATCHR (TIVA_TIMER4_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
# define TIVA_TIMER4_TBMATCHR (TIVA_TIMER4_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
# define TIVA_TIMER4_TAPR (TIVA_TIMER4_BASE + TIVA_TIMER_TAPR_OFFSET)
# define TIVA_TIMER4_TBPR (TIVA_TIMER4_BASE + TIVA_TIMER_TBPR_OFFSET)
# define TIVA_TIMER4_TAPMR (TIVA_TIMER4_BASE + TIVA_TIMER_TAPMR_OFFSET)
# define TIVA_TIMER4_TBPMR (TIVA_TIMER4_BASE + TIVA_TIMER_TBPMR_OFFSET)
#endif
#define TIVA_TIMER4_TAR (TIVA_TIMER4_BASE + TIVA_TIMER_TAR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER4_TBR (TIVA_TIMER4_BASE + TIVA_TIMER_TBR_OFFSET)
# define TIVA_TIMER4_TAV (TIVA_TIMER4_BASE + TIVA_TIMER_TAV_OFFSET)
# define TIVA_TIMER4_TBV (TIVA_TIMER4_BASE + TIVA_TIMER_TBV_OFFSET)
# define TIVA_TIMER4_RTCPD (TIVA_TIMER4_BASE + TIVA_TIMER_RTCPD_OFFSET)
# define TIVA_TIMER4_TAPS (TIVA_TIMER4_BASE + TIVA_TIMER_TAPS_OFFSET)
# define TIVA_TIMER4_TBPS (TIVA_TIMER4_BASE + TIVA_TIMER_TBPS_OFFSET)
# define TIVA_TIMER4_DMAEV (TIVA_TIMER4_BASE + TIVA_TIMER_DMAEV_OFFSET)
# define TIVA_TIMER4_ADCEV (TIVA_TIMER4_BASE + TIVA_TIMER_ADCEV_OFFSET)
# define TIVA_TIMER4_PP (TIVA_TIMER4_BASE + TIVA_TIMER_PP_OFFSET)
# define TIVA_TIMER4_CC (TIVA_TIMER4_BASE + TIVA_TIMER_CC_OFFSET)
#endif
#endif /* TIVA_NTIMERS > 4 */
#if TIVA_NTIMERS > 5
#define TIVA_TIMER5_CFG (TIVA_TIMER5_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER5_TAMR (TIVA_TIMER5_BASE + TIVA_TIMER_TAMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER5_TBMR (TIVA_TIMER5_BASE + TIVA_TIMER_TBMR_OFFSET)
#endif
#define TIVA_TIMER5_CTL (TIVA_TIMER5_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER5_SYNC (TIVA_TIMER5_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER5_IMR (TIVA_TIMER5_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER5_RIS (TIVA_TIMER5_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER5_ICR (TIVA_TIMER5_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER5_TAILR (TIVA_TIMER5_BASE + TIVA_TIMER_TAILR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER5_TBILR (TIVA_TIMER5_BASE + TIVA_TIMER_TBILR_OFFSET)
# define TIVA_TIMER5_TAMATCHR (TIVA_TIMER5_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
# define TIVA_TIMER5_TBMATCHR (TIVA_TIMER5_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
# define TIVA_TIMER5_TAPR (TIVA_TIMER5_BASE + TIVA_TIMER_TAPR_OFFSET)
# define TIVA_TIMER5_TBPR (TIVA_TIMER5_BASE + TIVA_TIMER_TBPR_OFFSET)
# define TIVA_TIMER5_TAPMR (TIVA_TIMER5_BASE + TIVA_TIMER_TAPMR_OFFSET)
# define TIVA_TIMER5_TBPMR (TIVA_TIMER5_BASE + TIVA_TIMER_TBPMR_OFFSET)
#endif
#define TIVA_TIMER5_TAR (TIVA_TIMER5_BASE + TIVA_TIMER_TAR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER5_TBR (TIVA_TIMER5_BASE + TIVA_TIMER_TBR_OFFSET)
# define TIVA_TIMER5_TAV (TIVA_TIMER5_BASE + TIVA_TIMER_TAV_OFFSET)
# define TIVA_TIMER5_TBV (TIVA_TIMER5_BASE + TIVA_TIMER_TBV_OFFSET)
# define TIVA_TIMER5_RTCPD (TIVA_TIMER5_BASE + TIVA_TIMER_RTCPD_OFFSET)
# define TIVA_TIMER5_TAPS (TIVA_TIMER5_BASE + TIVA_TIMER_TAPS_OFFSET)
# define TIVA_TIMER5_TBPS (TIVA_TIMER5_BASE + TIVA_TIMER_TBPS_OFFSET)
# define TIVA_TIMER5_DMAEV (TIVA_TIMER5_BASE + TIVA_TIMER_DMAEV_OFFSET)
# define TIVA_TIMER5_ADCEV (TIVA_TIMER5_BASE + TIVA_TIMER_ADCEV_OFFSET)
# define TIVA_TIMER5_PP (TIVA_TIMER5_BASE + TIVA_TIMER_PP_OFFSET)
# define TIVA_TIMER5_CC (TIVA_TIMER5_BASE + TIVA_TIMER_CC_OFFSET)
#endif
#endif /* TIVA_NTIMERS > 5 */
#if TIVA_NTIMERS > 6
#define TIVA_TIMER6_CFG (TIVA_TIMER6_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER6_TAMR (TIVA_TIMER6_BASE + TIVA_TIMER_TAMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER6_TBMR (TIVA_TIMER6_BASE + TIVA_TIMER_TBMR_OFFSET)
#endif
#define TIVA_TIMER6_CTL (TIVA_TIMER6_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER6_SYNC (TIVA_TIMER6_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER6_IMR (TIVA_TIMER6_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER6_RIS (TIVA_TIMER6_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER6_ICR (TIVA_TIMER6_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER6_TAILR (TIVA_TIMER6_BASE + TIVA_TIMER_TAILR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER6_TBILR (TIVA_TIMER6_BASE + TIVA_TIMER_TBILR_OFFSET)
# define TIVA_TIMER6_TAMATCHR (TIVA_TIMER6_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
# define TIVA_TIMER6_TBMATCHR (TIVA_TIMER6_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
# define TIVA_TIMER6_TAPR (TIVA_TIMER6_BASE + TIVA_TIMER_TAPR_OFFSET)
# define TIVA_TIMER6_TBPR (TIVA_TIMER6_BASE + TIVA_TIMER_TBPR_OFFSET)
# define TIVA_TIMER6_TAPMR (TIVA_TIMER6_BASE + TIVA_TIMER_TAPMR_OFFSET)
# define TIVA_TIMER6_TBPMR (TIVA_TIMER6_BASE + TIVA_TIMER_TBPMR_OFFSET)
#endif
#define TIVA_TIMER6_TAR (TIVA_TIMER6_BASE + TIVA_TIMER_TAR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER6_TBR (TIVA_TIMER6_BASE + TIVA_TIMER_TBR_OFFSET)
# define TIVA_TIMER6_TAV (TIVA_TIMER6_BASE + TIVA_TIMER_TAV_OFFSET)
# define TIVA_TIMER6_TBV (TIVA_TIMER6_BASE + TIVA_TIMER_TBV_OFFSET)
# define TIVA_TIMER6_RTCPD (TIVA_TIMER6_BASE + TIVA_TIMER_RTCPD_OFFSET)
# define TIVA_TIMER6_TAPS (TIVA_TIMER6_BASE + TIVA_TIMER_TAPS_OFFSET)
# define TIVA_TIMER6_TBPS (TIVA_TIMER6_BASE + TIVA_TIMER_TBPS_OFFSET)
# define TIVA_TIMER6_DMAEV (TIVA_TIMER6_BASE + TIVA_TIMER_DMAEV_OFFSET)
# define TIVA_TIMER6_ADCEV (TIVA_TIMER6_BASE + TIVA_TIMER_ADCEV_OFFSET)
# define TIVA_TIMER6_PP (TIVA_TIMER6_BASE + TIVA_TIMER_PP_OFFSET)
# define TIVA_TIMER6_CC (TIVA_TIMER6_BASE + TIVA_TIMER_CC_OFFSET)
#endif
#endif /* TIVA_NTIMERS > 6 */
#if TIVA_NTIMERS > 7
#define TIVA_TIMER7_CFG (TIVA_TIMER7_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER7_TAMR (TIVA_TIMER7_BASE + TIVA_TIMER_TAMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER7_TBMR (TIVA_TIMER7_BASE + TIVA_TIMER_TBMR_OFFSET)
#endif
#define TIVA_TIMER7_CTL (TIVA_TIMER7_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER7_SYNC (TIVA_TIMER7_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER7_IMR (TIVA_TIMER7_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER7_RIS (TIVA_TIMER7_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER7_ICR (TIVA_TIMER7_BASE + TIVA_TIMER_ICR_OFFSET)
#define TIVA_TIMER7_TAILR (TIVA_TIMER7_BASE + TIVA_TIMER_TAILR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER7_TBILR (TIVA_TIMER7_BASE + TIVA_TIMER_TBILR_OFFSET)
# define TIVA_TIMER7_TAMATCHR (TIVA_TIMER7_BASE + TIVA_TIMER_TAMATCHR_OFFSET)
# define TIVA_TIMER7_TBMATCHR (TIVA_TIMER7_BASE + TIVA_TIMER_TBMATCHR_OFFSET)
# define TIVA_TIMER7_TAPR (TIVA_TIMER7_BASE + TIVA_TIMER_TAPR_OFFSET)
# define TIVA_TIMER7_TBPR (TIVA_TIMER7_BASE + TIVA_TIMER_TBPR_OFFSET)
# define TIVA_TIMER7_TAPMR (TIVA_TIMER7_BASE + TIVA_TIMER_TAPMR_OFFSET)
# define TIVA_TIMER7_TBPMR (TIVA_TIMER7_BASE + TIVA_TIMER_TBPMR_OFFSET)
#endif
#define TIVA_TIMER7_TAR (TIVA_TIMER7_BASE + TIVA_TIMER_TAR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER7_TBR (TIVA_TIMER7_BASE + TIVA_TIMER_TBR_OFFSET)
# define TIVA_TIMER7_TAV (TIVA_TIMER7_BASE + TIVA_TIMER_TAV_OFFSET)
# define TIVA_TIMER7_TBV (TIVA_TIMER7_BASE + TIVA_TIMER_TBV_OFFSET)
# define TIVA_TIMER7_RTCPD (TIVA_TIMER7_BASE + TIVA_TIMER_RTCPD_OFFSET)
# define TIVA_TIMER7_TAPS (TIVA_TIMER7_BASE + TIVA_TIMER_TAPS_OFFSET)
# define TIVA_TIMER7_TBPS (TIVA_TIMER7_BASE + TIVA_TIMER_TBPS_OFFSET)
# define TIVA_TIMER7_DMAEV (TIVA_TIMER7_BASE + TIVA_TIMER_DMAEV_OFFSET)
# define TIVA_TIMER7_ADCEV (TIVA_TIMER7_BASE + TIVA_TIMER_ADCEV_OFFSET)
# define TIVA_TIMER7_PP (TIVA_TIMER7_BASE + TIVA_TIMER_PP_OFFSET)
# define TIVA_TIMER7_CC (TIVA_TIMER7_BASE + TIVA_TIMER_CC_OFFSET)
#endif
#endif /* TIVA_NTIMERS > 7 */
/* GPTM register bit definitions ****************************************************/
/* GPTM Configuration (CFG) */
#define TIMER_CFG_CFG_SHIFT 0 /* Bits 2-0: Configuration */
#define TIMER__CFG_MASK (7 << TIMER_CFG_CFG_SHIFT)
# define TIMER_CFG_CFG_32 (0 << TIMER_CFG_CFG_SHIFT) /* 32-bit timer configuration */
# define TIMER_CFG_CFG_RTC (1 << TIMER_CFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */
# define TIMER_CFG_CFG_16 (4 << TIMER_CFG_CFG_SHIFT) /* 16-bit timer configuration */
/* GPTM Timer A Mode (TAMR) */
#define TIMER_TAMR_TAMR_SHIFT 0 /* Bits 1-0: Timer A Mode */
#define TIMER_TAMR_TAMR_MASK (3 << TIMER_TAMR_TAMR_SHIFT)
# define TIMER_TAMR_TAMR_ONESHOT (1 << TIMER_TAMR_TAMR_SHIFT) /* One-Shot Timer mode */
# define TIMER_TAMR_TAMR_PERIODIC (2 << TIMER_TAMR_TAMR_SHIFT) /* Periodic Timer mode */
# define TIMER_TAMR_TAMR_CAPTURE (3 << TIMER_TAMR_TAMR_SHIFT) /* Capture mode */
#define TIMER_TAMR_TACMR (1 << 2) /* Bit 2: Timer A Capture Mode */
# define TIMER_TAMR_TACMR_EDGECOUNT (0 << TIMER_TAMR_TACMR_SHIFT) /* Edge-Count mode */
# define TIMER_TAMR_TACMR_EDGETIME (1 << TIMER_TAMR_TACMR_SHIFT) /* Edge-Time mode */
#define TIMER_TAMR_TAAMS (1 << 3) /* Bit 3: Timer A Alternate Mode Select */
# define TIMER_TAMR_TAAMS_CAPTURE (0 << TIMER_TAMR_TAAMS_SHIFT) /* Capture mode is enabled */
# define TIMER_TAMR_TAAMS_PWM (1 << TIMER_TAMR_TAAMS_SHIFT) /* PWM mode is enabled */
#define TIMER_TAMR_TACDIR (1 << 4) /* Bit 4: Timer A Count Direction */
# define TIMER_TAMR_TACDIR_DOWN (0 << TIMER_TAMR_TACDIR_SHIFT) /* The timer counts down */
# define TIMER_TAMR_TACDIR_UP (1 << TIMER_TAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */
#define TIMER_TAMR_TAMIE (1 << 5) /* Bit 5: Timer A Match Interrupt Enable */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TAMR_TAWOT (1 << 6) /* Bit 6: GPTM Timer A Wait-on-Trigger */
# define TIMER_TAMR_TASNAPS (1 << 7) /* Bit 7: GPTM Timer A Snap-Shot Mode */
# define TIMER_TAMR_TAILD (1 << 8) /* Bit 8: GPTM Timer A Interval Load Write */
# define TIMER_TAMR_TAPWMIE (1 << 9) /* Bit 9: GPTM Timer A PWM Interrupt Enable */
# define TIMER_TAMR_TAMRSU (1 << 10) /* Bit 10: GPTM Timer A Match Register Update */
# define TIMER_TAMR_TAPLO (1 << 11) /* Bit 11: GPTM Timer A PWM Legacy Operation */
# define TIMER_TAMR_TACINTD (1 << 12) /* Bit 12: One-shot/Periodic Interrupt Disable */
# define TIMER_TAMR_TCACT_SHIFT (13) /* Bits 13-15: Timer Compare Action Select */
# define TIMER_TAMR_TCACT_MASK (7 << TIMER_TAMR_TCACT_SHIFT)
# define TIMER_TAMR_TCACT_NONE (0 << TIMER_TAMR_TCACT_SHIFT) /* Disable compare operations */
# define TIMER_TAMR_TCACT_TOGGLE (1 << TIMER_TAMR_TCACT_SHIFT) /* Toggle state on timeout */
# define TIMER_TAMR_TCACT_CLRTO (2 << TIMER_TAMR_TCACT_SHIFT) /* Clear CCP on timeout */
# define TIMER_TAMR_TCACT_SETTO (3 << TIMER_TAMR_TCACT_SHIFT) /* Set CCP on timeout */
# define TIMER_TAMR_TCACT_SETTOGTO (4 << TIMER_TAMR_TCACT_SHIFT) /* Set CCP and toggle on TimeOut */
# define TIMER_TAMR_TCACT_CLRTOGTO (5 << TIMER_TAMR_TCACT_SHIFT) /* Clear CCP and toggle on TimeOut */
# define TIMER_TAMR_TCACT_SETCLRTO (6 << TIMER_TAMR_TCACT_SHIFT) /* Set CCP and clear on timeout */
# define TIMER_TAMR_TCACT_CLRSETTO (7 << TIMER_TAMR_TCACT_SHIFT) /* Clear CCP and set on timeout */
#endif
/* GPTM Timer B Mode (TBMR) */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TBMR_TBMR_SHIFT 0 /* Bits 1-0: Timer B Mode */
# define TIMER_TBMR_TBMR_MASK (3 << TIMER_TBMR_TBMR_SHIFT)
# define TIMER_TBMR_TBMR_ONESHOT (1 << TIMER_TBMR_TBMR_SHIFT) /* One-Shot Timer mode */
# define TIMER_TBMR_TBMR_PERIODIC (2 << TIMER_TBMR_TBMR_SHIFT) /* Periodic Timer mode */
# define TIMER_TBMR_TBMR_CAPTURE (3 << TIMER_TBMR_TBMR_SHIFT) /* Capture mode */
# define TIMER_TBMR_TBCMR (1 << 2) /* Bit 2: Timer B Capture Mode */
# define TIMER_TBMR_TBCMR_EDGECOUNT (0 << TIMER_TBMR_TBCMR_SHIFT) /* Edge-Count mode */
# define TIMER_TBMR_TBCMR_EDGETIME (1 << TIMER_TBMR_TBCMR_SHIFT) /* Edge-Time mode */
# define TIMER_TBMR_TBAMS (1 << 3) /* Bit 3: Timer B Alternate Mode Select */
# define TIMER_TBMR_TBAMS_CAPTURE (0 << TIMER_TBMR_TBAMS_SHIFT) /* Capture mode is enabled */
# define TIMER_TBMR_TBAMS_PWM (1 << TIMER_TBMR_TBAMS_SHIFT) /* PWM mode is enabled */
# define TIMER_TBMR_TBCDIR (1 << 4) /* Bit 4: Timer B Count Direction */
# define TIMER_TBMR_TBCDIR_DOWN (0 << TIMER_TBMR_TBCDIR_SHIFT) /* The timer counts down */
# define TIMER_TBMR_TBCDIR_UP (1 << TIMER_TBMR_TBCDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */
# define TIMER_TBMR_TBMIE (1 << 5) /* Bit 5: Timer B Match Interrupt Enable */
# define TIMER_TBMR_TBWOT (1 << 6) /* Bit 6: GPTM Timer B Wait-on-Trigger */
# define TIMER_TBMR_TBSNAPS (1 << 7) /* Bit 7: GPTM Timer B Snap-Shot Mode */
# define TIMER_TBMR_TBILD (1 << 8) /* Bit 8: GPTM Timer B Interval Load Write */
# define TIMER_TBMR_TBPWMIE (1 << 9) /* Bit 9: GPTM Timer B PWM Interrupt Enable */
# define TIMER_TBMR_TBMRSU (1 << 10) /* Bit 10: GPTM Timer B Match Register Update */
# define TIMER_TBMR_TBPLO (1 << 11) /* Bit 11: GPTM Timer B PWM Legacy Operation */
# define TIMER_TBMR_TBCINTD (1 << 12) /* Bit 12: One-shot/Periodic Interrupt Disable */
# define TIMER_TBMR_TCACT_SHIFT (13) /* Bits 13-15: Timer Compare Action Select */
# define TIMER_TBMR_TCACT_MASK (7 << TIMER_TBMR_TCACT_SHIFT)
# define TIMER_TBMR_TCACT_NONE (0 << TIMER_TBMR_TCACT_SHIFT) /* Disable compare operations */
# define TIMER_TBMR_TCACT_TOGGLE (1 << TIMER_TBMR_TCACT_SHIFT) /* Toggle state on timeout */
# define TIMER_TBMR_TCACT_CLRTO (2 << TIMER_TBMR_TCACT_SHIFT) /* Clear CCP on timeout */
# define TIMER_TBMR_TCACT_SETTO (3 << TIMER_TBMR_TCACT_SHIFT) /* Set CCP on timeout */
# define TIMER_TBMR_TCACT_SETTOGTO (4 << TIMER_TBMR_TCACT_SHIFT) /* Set CCP and toggle on TimeOut */
# define TIMER_TBMR_TCACT_CLRTOGTO (5 << TIMER_TBMR_TCACT_SHIFT) /* Clear CCP and toggle on TimeOut */
# define TIMER_TBMR_TCACT_SETCLRTO (6 << TIMER_TBMR_TCACT_SHIFT) /* Set CCP and clear on timeout */
# define TIMER_TBMR_TCACT_CLRSETTO (7 << TIMER_TBMR_TCACT_SHIFT) /* Clear CCP and set on timeout */
#endif
/* GPTM Control (CTL) */
#define TIMER_CTL_TAEN (1 << 0) /* Bit 0: Timer A Enable */
#define TIMER_CTL_TASTALL_SHIFT (1 << 1) /* Bit 1: Timer A Stall Enable */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_CTL_TAEVENT_SHIFT (2) /* Bits 2-3: GPTM Timer A Event Mode */
# define TIMER_CTL_TAEVENT_MASK (3 << TIMER_CTL_TAEVENT_SHIFT)
# define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */
# define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */
# define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */
# define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */
# define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */
# define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level */
# define TIMER_CTL_TBEN (1 << 8) /* Bit 8: GPTM Timer B Enable */
# define TIMER_CTL_TBSTALL (1 << 9) /* Bit 9: GPTM Timer B Stall Enable */
# define TIMER_CTL_TBEVENT_SHFIT (10) /* Bits 10-11: GPTM Timer B Event Mode */
# define TIMER_CTL_TBEVENT_MASK (3 << TIMER_CTL_TBEVENT_SHFIT)
# define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */
# define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */
# define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */
# define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */
# define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */
#endif
/* GPTM Synchronize */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_SYNC_
#endif
/* GPTM Interrupt Mask (IMR) */
#define TIMER_IMR_TATOIM_SHIFT (1 << 0) /* Bit 0: Timer A Time-Out Interrupt Mask */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
#endif
/* GPTM Raw Interrupt Status (RIS) */
#define TIMER_RIS_TATORIS_SHIFT (1 << 0) /* Bit 0: Timer A Time-Out Raw Interrupt */
/* GPTM Interrupt Clear (ICR) */
#define TIMER_ICR_TATOCINT_SHIFT (1 << 0) /* Bit 0: Timer A Time-Out Raw Interrupt Clear*/
/* GPTM Timer B Interval Load */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TBILR_
#endif
/* GPTM Timer A Match */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TAMATCHR_
#endif
/* GPTM Timer B Match */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TBMATCHR_
#endif
/* GPTM Timer A Prescale */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TAPR_
#endif
/* GPTM Timer B Prescale */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TBPR_
#endif
/* GPTM TimerA Prescale Match */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TAPMR_
#endif
/* GPTM TimerB Prescale Match */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TBPMR_
#endif
/* GPTM Timer A (TAR) */
#define TIMER_TAR_
/* GPTM Timer B (TBR) */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIMER_TBR_
#endif
/* GPTM Timer A Value */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_TAV_
#endif
/* GPTM Timer B Value */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_TBV_
#endif
/* GPTM RTC Predivide */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_RTCPD_
#endif
/* GPTM Timer A Prescale Snapshot */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_TAPS_
#endif
/* GPTM Timer B Prescale Snapshot */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_TBPS_
#endif
/* GPTM DMA Event */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_DMAEV_
#endif
/* GPTM ADC Event */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_ADCEV_
#endif
/* GPTM Peripheral Properties */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_PP_
#endif
/* GPTM Clock Configuration */
#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# define TIVA_TIMER_CC_
#endif
#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TIVA_TIMER_H */
|
