diff options
| author | Gregory Nutt <gnutt@nuttx.org> | 2014-03-28 15:20:26 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-03-28 15:20:26 -0600 |
| commit | 72db81ca76369766a84a1b094858c47c9ec183ec (patch) | |
| tree | 8ef2fed225c2c0800323d35c5751e9cc85a8d479 | |
| parent | 45369a3188583ebaef68da5b379121fc582b3287 (diff) | |
| download | nuttx-72db81ca76369766a84a1b094858c47c9ec183ec.tar.gz nuttx-72db81ca76369766a84a1b094858c47c9ec183ec.tar.bz2 nuttx-72db81ca76369766a84a1b094858c47c9ec183ec.zip | |
Add basic board support framework for the Atmel SAMA5D3 Xplained board (not finished)
46 files changed, 11718 insertions, 131 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 3c529348d..51f69084d 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -7058,4 +7058,11 @@ LCD. Reported by Toby Duckworth (2014-3-27). * arch/arm/include/sama5/chip.h and arch/arm/src/sama5/Kconfig: Add support for the SAMA5D36 (2014-3-28). - + * libc/strings/lib_strncpy.c: Change ordering of test and copy. Logic + would have failed if n=0; one byte was always copying before testing + for the end of the copy. + * nuttx/configs/sama5d3-xplained/: Add a board support configuration + for the Atmel SAMA5D3 Xplaiend board. The initial check in is not + finished. For example, it still builds to run out of NOR FLASH but + the SAMA5D Xlpained has no NOR FLASH (2013-4-28). +
\ No newline at end of file diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index d2563513d..c41fc66bc 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -1217,10 +1217,10 @@ <li>ARM <ul> <li><a href="#arm7tdmi">ARM7TDMI</b></a> (5)</li> - <li><a href="#arm920t">ARM920T</a> (1) </li> - <li><a href="#arm926ejs">ARM926EJS</a> (4) </li> - <li><a href="#armcortexa5">ARM Cortex-A5</a> (1) </li> - <li><a href="#armcortexa8">ARM Cortex-A8</a> (1) </li> + <li><a href="#arm920t">ARM920T</a> (1)</li> + <li><a href="#arm926ejs">ARM926EJS</a> (4)</li> + <li><a href="#armcortexa5">ARM Cortex-A5</a> (2)</li> + <li><a href="#armcortexa8">ARM Cortex-A8</a> (1)</li> <li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (3)</li> <li><a href="#armcortexm3">ARM Cortex-M3</a> (25)</li> <li><a href="#armcortexm4">ARM Cortex-M4</a> (11)</li> @@ -1724,141 +1724,160 @@ <td> <p> <a name="at91sama5d3"><b>Atmel SAMA5D3</b>.</a> - This is the port of NuttX to the Atmel SAMA5D3<i>x</i>-EK development boards (where <i>x</i>=1,3,4, or 5). - These boards feature the Atmel SAMA5D3<i>x</i> microprocessors. - Four different SAMA5D3<i>x</i>-EK kits are available - </p> - <ul> - <li>SAMA5D31-EK with the <a href="http://www.atmel.com/devices/sama5d31.aspx">ATSAMA5D31</a></li> - <li>SAMA5D33-EK with the <a href="http://www.atmel.com/devices/sama5d33.aspx">ATSAMA5D33</a></li> - <li>SAMA5D34-EK with the <a href="http://www.atmel.com/devices/sama5d34.aspx">ATSAMA5D34</a></li> - <li>SAMA5D35-EK with the <a href="http://www.atmel.com/devices/sama5d35.aspx">ATSAMA5D35</a></li> - </ul> + There are ports to two Atmel SAMA5D3 boards: <p> - The each kit consist of an identical base board with different plug-in modules for each CPU. - All four boards are supported by NuttX with a simple reconfiguration of the processor type. - </p> <ul> - <p> - <b>STATUS</b>. - Initial support for the SAMA5D3x-EK was released in NuttX-6.29. - That initial support was minimal: - There are simple test configurations that run out of internal SRAM and extended configurations that run out of the on-board NOR FLASH: - </p> - <ul> - <li> - A barebones NuttShell (<a href="NuttShell.html">NSH</a>) configuration that can be used as the basis for further application development. - </li> - <li> - A full-loaded NuttShell (<a href="NuttShell.html">NSH</a>) configuration that demonstrates all of the SAMA5D3x features. - </li> - </ul> - <p> - The following support was added in Nuttx 6.30: - </p> - <ul> - <li> - DMA support, and - </li> - <li> - PIO interrupts, - </li> - </ul> - <p> - And drivers for + <li><p><b>Atmel SAMA5D3<i>x</i>-EK development boards</b> + This is the port of NuttX to the Atmel SAMA5D3<i>x</i>-EK development boards (where <i>x</i>=1,3,4, or 5). + These boards feature the Atmel SAMA5D3<i>x</i> microprocessors. + Four different SAMA5D3<i>x</i>-EK kits are available </p> <ul> - <li> - SPI (with DMA support), - </li> - <li> - AT25 Serial Flash, - </li> - <li> - Two Wire Interface (TWI), and - </li> - <li> - HSMCI memory cards. - </li> + <li>SAMA5D31-EK with the <a href="http://www.atmel.com/devices/sama5d31.aspx">ATSAMA5D31</a></li> + <li>SAMA5D33-EK with the <a href="http://www.atmel.com/devices/sama5d33.aspx">ATSAMA5D33</a></li> + <li>SAMA5D34-EK with the <a href="http://www.atmel.com/devices/sama5d34.aspx">ATSAMA5D34</a></li> + <li>SAMA5D35-EK with the <a href="http://www.atmel.com/devices/sama5d35.aspx">ATSAMA5D35</a></li> </ul> <p> - NuttX-6.30 also introduces full USB support: + The each kit consist of an identical base board with different plug-in modules for each CPU. + All four boards are supported by NuttX with a simple reconfiguration of the processor type. </p> <ul> - <li> + <p> + <b>STATUS</b>. + Initial support for the SAMA5D3x-EK was released in NuttX-6.29. + That initial support was minimal: + There are simple test configurations that run out of internal SRAM and extended configurations that run out of the on-board NOR FLASH: + </p> + <ul> + <li> + A barebones NuttShell (<a href="NuttShell.html">NSH</a>) configuration that can be used as the basis for further application development. + </li> + <li> + A full-loaded NuttShell (<a href="NuttShell.html">NSH</a>) configuration that demonstrates all of the SAMA5D3x features. + </li> + </ul> + <p> + The following support was added in Nuttx 6.30: + </p> + <ul> + <li> + DMA support, and + </li> + <li> + PIO interrupts, + </li> + </ul> + <p> + And drivers for + </p> + <ul> + <li> + SPI (with DMA support), + </li> + <li> + AT25 Serial Flash, + </li> + <li> + Two Wire Interface (TWI), and + </li> + <li> + HSMCI memory cards. + </li> + </ul> + <p> + NuttX-6.30 also introduces full USB support: + </p> + <ul> + <li> High speed device controller driver, - </li> - <li> + </li> + <li> OHCI (low- and full-speed) and - </li> - <li> + </li> + <li> EHCI (high-speed) host controller driver support. - </li> - </ul> - <p> - With NuttX-6.31, these additional drivers were added: - </p> - <ul> - <li> - A 10/100Base-T Ethernet (EMAC) driver, - </li> - <li> - A 1000Base-T Ethernet (GMAC) driver, - </li> - <li> - A Real Time Clock (RTC) driver and integrated with the NuttX system time logic - </li> - <li> - <code>/dev/random</code> using the SAMA5D3x True Random Number Generator (TRNG), - </li> - <li> - A Watchdog Timer (WDT) driver, - </li> - <li> - A Timer/Counter (TC) library with interface that make be used by other drivers that need timer support, - </li> - <li> - An ADC driver that can collect multiple samples using the sequencer, can be trigger by a timer/counter, and supports DMA data transfers, - </li> - <li> - A touchscreen driver based on the special features of the SAMA5D3 ADC peripheral, - An LCD controller (LCDC) frame buffer driver, and - </li> - <li> - A CAN driver (Testing of the CAN has been delayed because of cabling issues). - </li> - </ul> - <p> - Additional board configurations were added to test and demonstrate these new drivers including new graphics and NxWM configurations. - </p> - <p> - These drivers were added in NuttX-6.32: - </p> - <ul> - <li> - A PWM driver with DMA support - </li> - <li> - An SSC-based I2S driver - </li> - <li> - Support for Programmable clock outputs - </li> - <li> - NAND support including support for the PMECC hardware ECC and for DMA transfers. - </li> + </li> + </ul> + <p> + With NuttX-6.31, these additional drivers were added: + </p> + <ul> + <li> + A 10/100Base-T Ethernet (EMAC) driver, + </li> + <li> + A 1000Base-T Ethernet (GMAC) driver, + </li> + <li> + A Real Time Clock (RTC) driver and integrated with the NuttX system time logic + </li> + <li> + <code>/dev/random</code> using the SAMA5D3x True Random Number Generator (TRNG), + </li> + <li> + A Watchdog Timer (WDT) driver, + </li> + <li> + A Timer/Counter (TC) library with interface that make be used by other drivers that need timer support, + </li> + <li> + An ADC driver that can collect multiple samples using the sequencer, can be trigger by a timer/counter, and supports DMA data transfers, + </li> + <li> + A touchscreen driver based on the special features of the SAMA5D3 ADC peripheral, + An LCD controller (LCDC) frame buffer driver, and + </li> + <li> + A CAN driver (Testing of the CAN has been delayed because of cabling issues). + </li> + </ul> + <p> + Additional board configurations were added to test and demonstrate these new drivers including new graphics and NxWM configurations. + </p> + <p> + These drivers were added in NuttX-6.32: + </p> + <ul> + <li> + A PWM driver with DMA support + </li> + <li> + An SSC-based I2S driver + </li> + <li> + Support for Programmable clock outputs + </li> + <li> + NAND support including support for the PMECC hardware ECC and for DMA transfers. + </li> + </ul> + <p> + Refer to the NuttX board <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/sama5d3x-ek/README.txt">README</a> file for further information. + </p> + </li> + <li> + <p> + <b>Atmel SAMA5D3 Xplained development board</b> + This is the port of NuttX to the Atmel SAMA5D3 Xplained development board. + The board features the Atmel SAMA5D36 microprocessors. + See the <a href="http://www.atmel.com/devices/sama5d36.aspx">Atmel Website</a> for additional information about this board. + </p> + <p> + <b>STATUS</b>. + This port is underway as of this writing and not ready for general use. + The basic port is expected to be simple because of the similarity to the SAMAD3<i>x</i>-EK boards and should be available in the NuttX 7.2 release. + </p> + <p> + Refer to the NuttX board <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/sama5d3-xplained/README.txt">README</a> file for further information. + </p> </ul> - <p> - Develop continues. - Work is underway to provide a Image Sensor Interface (ISI) camera interface. - </p> - <p> - Refer to the NuttX board <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/sama5d3x-ek/README.txt">README</a> file for further information. - </p> - <p> - <b>Development Environments:</b> - 1) Linux with native Linux GNU toolchain, 2) Cygwin/MSYS with Cygwin GNU toolchain, 3) Cygwin/MSYS with Windows native toolchain, or 4) Native Windows. - All testing has been perfomed with the CodeSourcery toolchain (GCC version 4.7.3) in the Cygwin environment under Windows. + </li> + </ul> + <p> + <b>Development Environments:</b> + 1) Linux with native Linux GNU toolchain, 2) Cygwin/MSYS with Cygwin GNU toolchain, 3) Cygwin/MSYS with Windows native toolchain, or 4) Native Windows. + All testing has been perfomed with the CodeSourcery toolchain (GCC version 4.7.3) in the Cygwin environment under Windows. </p> </td> </tr> diff --git a/nuttx/Documentation/README.html b/nuttx/Documentation/README.html index e1b0ff183..d1b9e8536 100644 --- a/nuttx/Documentation/README.html +++ b/nuttx/Documentation/README.html @@ -8,7 +8,7 @@ <tr align="center" bgcolor="#e4e4e4"> <td> <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1> - <p>Last Updated: March 10, 2014</p> + <p>Last Updated: March 28, 2014</p> </td> </tr> </table> @@ -163,6 +163,8 @@ | | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/rgmp/README.txt"><b><i>README.txt</i></b></a> | | |- sama5d3x-ek/ | | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/sama5d3x-ek/README.txt"><b><i>README.txt</i></b></a> + | | |- sama5d3-xplained/ + | | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/sama5d3-xplained/README.txt"><b><i>README.txt</i></b></a> | | |- samd20-xplained/ | | | `- <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/samd20-xplained/README.txt"><b><i>README.txt</i></b></a> | | |- sam3u-ek/ diff --git a/nuttx/README.txt b/nuttx/README.txt index e6f686fdd..21f82a141 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -1027,6 +1027,8 @@ nuttx | | `- README.txt | |- sama5d3x-ek/ | | `- README.txt + | |- sama5d3-xplained/ + | | `- README.txt | |- samd20-xplained/ | | `- README.txt | |- sam3u-ek/ diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index 121ab0f18..62b0ceafe 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -544,6 +544,15 @@ config ARCH_BOARD_SAMA5D3X_EK ---help--- The port of NuttX to the Atmel SAMA5D3x-EK development board (where x=1,3,4, or 5). +config ARCH_BOARD_SAMA5D3_XPLAINED + bool "Atmel SAMA5D3 Xplained development board" + depends on ARCH_CHIP_ATSAMA5D36 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + The port of NuttX to the Atmel SAMA5D3 Xplained development board. + config ARCH_BOARD_SAMD20_XPLAINED bool "Atmel SAMD20-Xplained Pro development board" depends on ARCH_CHIP_SAMD20J18 @@ -957,6 +966,7 @@ config ARCH_BOARD default "qemu-i486" if ARCH_BOARD_QEMU_I486 default "rgmp" if ARCH_BOARD_RGMP default "sama5d3x-ek" if ARCH_BOARD_SAMA5D3X_EK + default "sama5d3-xplained" if ARCH_BOARD_SAMA5D3_XPLAINED default "samd20-xplained" if ARCH_BOARD_SAMD20_XPLAINED default "sam3u-ek" if ARCH_BOARD_SAM3UEK default "sam4e-ek" if ARCH_BOARD_SAM4EEK @@ -1207,6 +1217,9 @@ endif if ARCH_BOARD_SAMA5D3X_EK source "configs/sama5d3x-ek/Kconfig" endif +if ARCH_BOARD_SAMA5D3_XPLAINED +source "configs/sama5d3-xplained/Kconfig" +endif if ARCH_BOARD_SAMD20_XPLAINED source "configs/samd20-xplained/Kconfig" endif diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index b0499c236..bd94d0f27 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -466,8 +466,10 @@ configs/sama5d3x-ek are supported by NuttX with a simple reconfiguration of the processor type. - There is also the SAMA5D3FAE-EK bundle includes everything: The base - board, all four CPU modules, and the LCD. +configs/sama5d3-xplained + This is the port of NuttX to the Atmel SAMA5D3x-Xplained development board. + This board features the Atmel SAMA5D36. See + http://www.atmel.com/devices/sama5d36.aspx. configs/samd20-xplained The port of NuttX to the Atmel SAMD20-Xplained Pro development board. This diff --git a/nuttx/configs/sama5d3-xplained/Kconfig b/nuttx/configs/sama5d3-xplained/Kconfig new file mode 100644 index 000000000..ce6623bd0 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/Kconfig @@ -0,0 +1,165 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_SAMA5D3_XPLAINED + +choice + prompt "SAMA5D3-Xplained DRAM Type" + default SAMA5D3XPLAINED_MT47H128M16RT + depends on SAMA5_DDRCS + +config SAMA5D3XPLAINED_MT47H128M16RT + bool "MT47H128M16RT" + ---help--- + Micron 2Gbit x16 DDR2-1066 128Mb + +config SAMA5D3XPLAINED_MT47H64M16HR + bool "MT47H64M16HR" + ---help--- + Micron 1Gbit x16 DDR2-800 64Mb + +endchoice # SAMA5D3-Xplained DRAM Type + +config SAMA5D3XPLAINED_NOR_MAIN + bool "Build nor_main" + default n + depends on SAMA5_BOOT_ISRAM + ---help--- + nor_main is a tiny program that runs in ISRAM. nor_main will enable + NOR flash then either (1) jump to the program in NOR flash or (2) + wait for you to break in with GDB to debug the NOR program. + +config SAMA5D3XPLAINED_NOR_START + bool "Start NOR program" + default n + depends on SAMA5D3XPLAINED_NOR_MAIN + ---help--- + The default behavior of the NOR boot program is to initialize the + NOR FLASH at CS0, then patiently wait for you to break into the + program with GDB. An alternative behvior is enabled with this + option: If SAMA5D3XPLAINED_NOR_START is defined, then it will not wait but + will, instead, immediately start the program in NOR FLASH. + +config SAMA5D3XPLAINED_NAND_AUTOMOUNT + bool "NAND FLASH auto-mount" + default n + depends on NSH_ARCHINIT && SAMA5_EBICS3_NAND + ---help--- + Automatically initialize the NAND FLASH driver when NSH starts. + +choice + prompt "NAND FLASH configuration" + default SAMA5D3XPLAINED_NAND_NXFFS + depends on SAMA5D3XPLAINED_NAND_AUTOMOUNT + +config SAMA5D3XPLAINED_NAND_FTL + bool "Create NAND FLASH block driver" + depends on MTD && MTD_NAND + ---help--- + Create the MTD driver for the NAND and "wrap" the NAND as a standard + block driver that could then, for example, be mounted using FAT or + any other file system. Any file system may be used, but there will + be no wear-leveling. + + NOTE: This options is not currently recommended. There is not now + NuttX file system that can handle the NAND back blocks or performs + wear-leveling other than NXFFS and NXFFS does not use a block driver + but, rather, operates directly upon the NAND MTD device. + +config SAMA5D3XPLAINED_NAND_NXFFS + bool "Create NAND FLASH NXFFS file system" + depends on MTD && MTD_NAND && FS_NXFFS && NXFFS_NAND + ---help--- + Create the MTD driver for the NAND and mount the NAND device as + a wear-leveling, NuttX FLASH file system (NXFFS). The downside of + NXFFS is that it can be very slow. + + NOTE: NXFFS is recommended because (1) it can handle the NAND back + blocks and (1) performs wear-leveling. + +endchoice # NAND FLASH configuration + +config SAMA5D3XPLAINED_AT25_AUTOMOUNT + bool "AT25 serial FLASH auto-mount" + default n + depends on NSH_ARCHINIT && SAMA5_SPI0 && MTD_AT25 + ---help--- + Automatically initialize the AT25 SPI FLASH driver when NSH starts. + +choice + prompt "AT25 serial FLASH configuration" + default SAMA5D3XPLAINED_AT25_FTL + depends on SAMA5D3XPLAINED_AT25_AUTOMOUNT + +config SAMA5D3XPLAINED_AT25_FTL + bool "Create AT25 Serial FLASH block driver" + ---help--- + Create the MTD driver for the AT25 and "wrap" the AT25 as a standard + block driver that could then, for example, be mounted using FAT or + any other file system. Any file system may be used, but there will + be no wear-leveling. + +config SAMA5D3XPLAINED_AT25_NXFFS + bool "Create AT25 serial FLASH NXFFS file system" + depends on FS_NXFFS + ---help--- + Create the MTD driver for the AT25 and mount the AT25 device as + a wear-leveling, NuttX FLASH file system (NXFFS). The downside of + NXFFS is that it can be very slow. + +endchoice # AT25 serial FLASH configuration + +config SAMA5D3XPLAINED_CHANNEL + int "PWM channel number" + default 0 if SAMA5_PWM_CHAN0 + default 1 if SAMA5_PWM_CHAN1 + default 2 if SAMA5_PWM_CHAN2 + default 3 if SAMA5_PWM_CHAN3 + range 0 3 + depends on PWM && SAMA5_PWM + ---help--- + Selects the PWM channel number that will be used to perform the PWM + test. See apps/examples/pwm. + +if AUDIO_I2SCHAR && (SAMA5_SSC0 || SAMA5_SSC1) + +if SAMA5_SSC0 && SAMA5_SSC1 + +config SAMA5D3XPLAINED_SSC_PORT + int "SSC port number" + default 0 + range 0 1 + ---help--- + Specify the I2S port to use, i.e., 0 for SSC0 or 1 for SSC1 + +endif # SAMA5_SSC0 && SAMA5_SSC1 + +if SAMA5_SSC0 && !SAMA5_SSC1 + +config SAMA5D3XPLAINED_SSC_PORT + int + default 0 + +endif # SAMA5_SSC0 && !SAMA5_SSC1 + +if !SAMA5_SSC0 && SAMA5_SSC1 + +config SAMA5D3XPLAINED_SSC_PORT + int + default 1 + +endif # SAMA5_SSC0 && !SAMA5_SSC1 + +config SAMA5D3XPLAINED_I2SCHAR_MINOR + int "I2S character driver minor number" + default 0 + ---help--- + The minor device number to use when registering the I2S character + device. The driver will be registered at /dev/is2charN where N is + the value provided by this setting. + +endif # AUDIO_I2SCHAR && (SAMA5_SSC0 || SAMA5_SSC1) + +endif # ARCH_BOARD_SAMA5D3_XPLAINED diff --git a/nuttx/configs/sama5d3-xplained/README.txt b/nuttx/configs/sama5d3-xplained/README.txt new file mode 100644 index 000000000..bc6cf6df8 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/README.txt @@ -0,0 +1,2653 @@ +README +====== + + This README file describes the port of NuttX to the SAMA5D3-Xplained + development board. This board features the Atmel SAMA5D36 microprocessor. + See http://www.atmel.com/devices/sama5d36.aspx for further information. + + PARAMTER SAMA5D36 + ------------------------- ------------- + Pin Count 324 + Max. Operating Frequency 536 MHz + CPU Cortex-A5 + Max I/O Pins 160 + Ext Interrupts 160 + USB Transceiver 3 + USB Speed Hi-Speed + USB Interface Host, Device + SPI 6 + TWI (I2C) 3 + UART 7 + CAN 2 + LIN 4 + SSC 2 + Ethernet 2 + SD / eMMC 3 + Graphic LCD Yes + Camera Interface Yes + ADC channels 12 + ADC Resolution (bits) 12 + ADC Speed (ksps) 1000 + Resistive Touch Screen Yes + Crypto Engine AES/DES/ + SHA/TRNG + SRAM (Kbytes) 128 + External Bus Interface 1 + DRAM Memory DDR2/LPDDR, + SDRAM/LPSDR + NAND Interface Yes + Temp. Range (deg C) -40 to 105 + I/O Supply Class 1.8/3.3 + Operating Voltage (Vcc) 1.08 to 1.32 + FPU Yes + MPU / MMU No/Yes + Timers 6 + Output Compare channels 6 + Input Capture Channels 6 + PWM Channels 4 + 32kHz RTC Yes + Packages LFBGA324_A + +Contents +======== + + - Development Environment + - GNU Toolchain Options + - IDEs + - NuttX EABI "buildroot" Toolchain + - NXFLAT Toolchain + - Loading Code into SRAM with J-Link + - Writing to FLASH using SAM-BA + - Creating and Using NORBOOT + - Buttons and LEDs + - Serial Console + - Networking + - AT25 Serial FLASH + - HSMCI Card Slots + - USB Ports + - USB High-Speed Device + - USB High-Speed Host + - SDRAM Support + - NAND Support + - I2C Tool + - CAN Usage + - SAMA5 ADC Support + - SAMA5 PWM Support + - RTC + - Watchdog Timer + - TRNG and /dev/random + - I2S Audio Support + - SAMA5D3-Xplained Configuration Options + - Configurations + - To-Do List + +Development Environment +======================= + + Several possible development environments may be use: + + - Linux or OSX native + - Cygwin unders Windows + - MinGW + MSYS under Windows + - Windows native (with GNUMake from GNUWin32). + + All testing has been performed using Cygwin under Windows. + + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. + +GNU Toolchain Options +===================== + + The NuttX make system will support the several different toolchain options. + + All testing has been conducted using the CodeSourcery GCC toolchain. To use + a different toolchain, you simply need to add change to one of the following + configuration options to your .config (or defconfig) file: + + CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_ARMV7A_TOOLCHAIN_ATOLLIC=y : Atollic toolchain for Windos + CONFIG_ARMV7A_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows + CONFIG_ARMV7A_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux + CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows + + The CodeSourcery GCC toolchain is selected with + CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y and setting the PATH variable + appropriately. + + NOTE about Windows native toolchains + ------------------------------------ + + There are several limitations to using a Windows based toolchain in a + Cygwin environment. The three biggest are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' + utility but you might easily find some new path problems. If so, check + out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic + links are used in Nuttx (e.g., include/arch). The make system works + around these problems for the Windows tools by copying directories + instead of linking them. But this can also cause some confusion for + you: For example, you may edit a file in a "linked" directory and find + that your changes had no effect. That is because you are building the + copy of the file in the "fake" symbolic directory. If you use a\ + Windows toolchain, you should get in the habit of making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + + 3. Dependencies are not made when using Windows versions of the GCC. This is + because the dependencies are generated using Windows paths which do not + work with the Cygwin make. + + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + +IDEs +==== + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project. + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/arm/src/sam34, + arch/arm/src/common, arch/arm/src/armv7-m, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX + one time from the Cygwin command line in order to obtain the pre-built + startup object needed by an IDE. + +NuttX EABI "buildroot" Toolchain +================================ + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the Cortex-M3 GCC toolchain (if + different from the default in your PATH variable). + + If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX + SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in <some-dir>/nuttx. + + cd tools + ./configure.sh sama5d3-xplained/<sub-dir> + + 2. Download the latest buildroot package into <some-dir> + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot. + + 4. cd <some-dir>/buildroot + + 5. Copy the configuration file from the configs/ sub-directory to the + top-level build directory: + + cp configs/cortexa8-eabi-defconfig-4.8.2 .config + + 6a. You may wish to modify the configuration before you build it. For + example, it is recommended that you build the kconfig-frontends tools, + generomfs, and the NXFLAT tools as well. You may also want to change + the selected toolchain. These reconfigurations can all be done with + + make menuconfig + + 6b. If you chose to make the configuration with no changes, then you + should still do the following to make certain that the build + configuration is up-to-date: + + make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + See the file configs/README.txt in the buildroot source tree. That has more + details PLUS some special instructions that you will need to follow if you are + building a Cortex-M3 toolchain for Cygwin under Windows. + +NXFLAT Toolchain +================ + + If you are *not* using the NuttX buildroot toolchain and you want to use + the NXFLAT tools, then you will still have to build a portion of the buildroot + tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can + be downloaded from the NuttX SourceForge download site + (https://sourceforge.net/projects/nuttx/files/). + + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in <some-dir>/nuttx. + + cd tools + ./configure.sh sama5d3-xplained/<sub-dir> + + 2. Download the latest buildroot package into <some-dir> + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot. + + 4. cd <some-dir>/buildroot + + 5. cp configs/cortexm3-defconfig-nxflat .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built NXFLAT binaries. + + NOTE: There are some known incompatibilities with 4.6.3 EABI toolchain + and the NXFLAT tools. See the top-level TODO file (under "Binary + loaders") for more information about this problem. If you plan to use + NXFLAT, please do not use the GCC 4.6.3 EABI toochain. + +Loading Code into SRAM with J-Link +================================== + + Loading code with the Segger tools and GDB + ------------------------------------------ + + 1) Change directories into the directory where you built NuttX. + 2) Start the GDB server and wait until it is ready to accept GDB + connections. + 3) Then run GDB like this: + + $ arm-none-eabi-gdb + (gdb) target remote localhost:2331 + (gdb) mon reset + (gdb) load nuttx + (gdb) ... start debugging ... + + Loading code using J-Link Commander + ---------------------------------- + + J-Link> r + J-Link> loadbin <file> <address> + J-Link> setpc <address of __start> + J-Link> ... start debugging ... + +Writing to FLASH using SAM-BA +============================= + + Assumed starting configuration: + + 1. You have installed the J-Link CDC USB driver (Windows only, there is + no need to install a driver on any regular Linux distribution), + 2. You have the USB connected to DBGU port (J23) + 3. Terminal configuration: 115200 8N1 + + Using SAM-BA to write to FLASH: + + 1. Exit the terminal emulation program and remove the USB cable from + the DBGU port (J23) + 2. Connect the USB cable to the device USB port (J6) + 3. JP9 must open (BMS == 1) to boot from on-chip Boot ROM. + 4. Press and maintain PB4 CS_BOOT button and power up the board. PB4 + CS_BOOT button prevents booting from Nand or serial Flash by + disabling Flash Chip Selects after having powered the board, you can + release the PB4 BS_BOOT button. + 5. On Windows you may need to wait for a device driver to be installed. + 6. Start the SAM-BA application, selecting (1) the correct USB serial + port, and (2) board = at91sama5d3-xplained. + 7. The SAM-BA menu should appear. + 8. Select the FLASH bank that you want to use and the address to write + to and "Execute" + 9. When you are finished writing to FLASH, remove the USB cable from J6 + and re-connect the serial link on USB CDC / DBGU connector (J23) and + re-open the terminal emulator program. + 10. Power cycle the board. + +Creating and Using NORBOOT +========================== + + In order to have more control of debugging code that runs out of NOR FLASH, + I created the sama5d3-xplained/norboot configuration. That configuration is + described below under "Configurations." + + Here are some general instructions on how to build an use norboot: + + Building: + 1. Remove any old configurations (if applicable). + + cd <nuttx> + make distclean + + 2. Install and build the norboot configuration. This steps will establish + the norboot configuration and setup the PATH variable in order to do + the build: + + cd tools + ./configure.sh sama5d3-xplained/<subdir> + cd - + . ./setenv.sh + + Before sourcing the setenv.sh file above, you should examine it and + perform edits as necessary so that TOOLCHAIN_BIN is the correct path + to the directory than holds your toolchain binaries. + + NOTE: Be aware that the default norboot also disables the watchdog. + Since you will not be able to re-enable the watchdog later, you may + need to set CONFIG_SAMA5_WDT=y in the NuttX configuration file. + + Then make norboot: + + make + + This will result in an ELF binary called 'nuttx' and also HEX and + binary versions called 'nuttx.hex' and 'nuttx.bin'. + + 3. Rename the binaries. Since you will need two versions of NuttX: this + norboot version that runs in internal SRAM and another under test in + NOR FLASH, I rename the resulting binary files so that they can be + distinguished: + + mv nuttx norboot + mv nuttx.hex norboot.hex + mv nuttx.bin norboot.bin + + 4. Build your NOR configuration and write this into NOR FLASH. Here, for + example, is how you would create the NSH NOR configuration: + + cd <nuttx> + make distclean # Remove the norboot configuration + cd tools + ./configure.sh sama5d3-xplained/nsh # Establish the NSH configuration + cd - + make # Build the NSH configuration + + Then use SAM-BA to write the nuttx.bin binary into NOR FLASH. This + will involve holding the CS_BOOT button and power cycling to start + the ROM loader. The SAM-BA serial connection will be on the device + USB port, not the debug USB port. Follow the SAM-BA instruction to + write the nuttx.bin binary to NOR FLASH. + + 5. Restart the system without holding CS_BOOT to get back to the normal + debug setup. + + 6. Then start the J-Link GDB server and GDB. In GDB, I do the following: + + (gdb) mon reset # Reset and halt the CPU + (gdb) load norboot # Load norboot into internal SRAM + (gdb) mon go # Start norboot + (gdb) mon halt # Break in + (gdb) mon reg pc = 0x10000040 # Set the PC to NOR flash entry point + (gdb) mon go # And jump into NOR flash + + The norboot program can also be configured to jump directly into + NOR FLASH without requiring the final halt and go by setting + CONFIG_SAMA5D3XPLAINED_NOR_START=y in the NuttX configuration. However, + since I have been debugging the early boot sequence, the above + sequence has been most convenient for me since it allows me to + step into the program in NOR. + + 7. An option is to use the SAM-BA tool to write the NORBOOT image into + Serial FLASH. Then, the system will boot from Serial FLASH by + copying the NORBOOT image in SRAM which will run and then start the + image in NOR FLASH automatically. This is a very convenient usage! + + NOTES: (1) There is jumper on the CM module that must be closed to + enable use of the AT25 Serial Flash. (2) If using SAM-BA, make sure + that you load the NOR boot program into the boot area via the pull- + down menu. + + STATUS: + 2014-7-30: I have been unable to execute these configurations from NOR + FLASH by closing the BMS jumper (J9). As far as I can tell, this + jumper does nothing on my board??? So I have been using the norboot + configuration exclusively to start the program-under-test in NOR FLASH. + +Buttons and LEDs +================ + + Buttons + ------- + + The following push buttons switches are available: + + 1. One board reset button (BP2). When pressed and released, this push + button causes a power-on reset of the whole board. + + 2. One wakeup pushbutton that brings the processor out of Low-power mode + (BP1) + + 3. One user pushbutton (BP3) + + Only the user push button (BP3) is controllable by software: + + - PE29. Pressing the switch connect PE29 to ground. Therefore, PE29 + must be pulled high internally. When the button is pressed the SAMA5 + will sense "0" is on PE29. + + LEDs + ---- + There are two LEDs on the SAMA5D3 series-CM board that can be controlled + by software. A blue LED is controlled via PIO pins. A red LED normally + provides an indication that power is supplied to the board but can also + be controlled via software. + + PE23. This blue LED is pulled high and is illuminated by pulling PE23 + low. + + PE24. The red LED is also pulled high but is driven by a transistor so + that it is illuminated when power is applied even if PE24 is not + configured as an output. + + These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + defined. In that case, the usage by the board port is defined in + include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + events as follows: + + SYMBOL Meaning LED state + Blue Red + ------------------- ----------------------- -------- -------- + LED_STARTED NuttX has been started OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF + LED_IRQSENABLED Interrupts enabled OFF OFF + LED_STACKCREATED Idle stack created ON OFF + LED_INIRQ In an interrupt No change + LED_SIGNAL In a signal handler No change + LED_ASSERTION An assertion failed No change + LED_PANIC The system has crashed OFF Blinking + LED_IDLE MCU is is sleep mode Not used + + Thus if the blue LED is statically on, NuttX has successfully booted and + is, apparently, running normally. If the red is flashing at + approximately 2Hz, then a fatal error has been detected and the system + has halted. + +Serial Console +============== + + UARTS/USARTS + ------------ + + CONN LABEL PIO UART/USART FUNCTION + ----- ------- ----- ----------- --------------- + J18 SCL0 PC30 UART0 UTXD0 + J18 SDA0 PC29 UART0 URXD0 + J15 1 PA31 UART1 UTXD1 + J15 0 PA30 UART1 URXD1 + J20 TXD3 14 PC26 UART1 URXD1 + J20 RXD3 15 PC27 UART1 UTXD1 + J20 TXD1 16 PD18 USART0 TXD0 + J20 RXD1 17 PD17 USART0 RXD0 + J20 TXD0 18 PB29 USART1 TXD1 + J20 RXD0 19 PB28 USART1 RXD1 + J20 SDA 20 PE19 USART3 TXD3 + J20 SCL 21 PE18 USART3 RXD3 + + By default USART1 is used as the NuttX serial console in all + configurations (unless otherwise noted). USART1 is provided at TTL + levels at pins TXD0 and TXD1 or J20. + + USART1 Connector J8 + + DBGU Interface + -------------- + + The SAMA5D3 Xplained board has a dedicated serial port for debugging, + which is accessible through the 6-pin male header J23. + + PIN PIO Usage + --- ---- ----------------------------------------- + 1 PE13 (available) + 2 PB31 DBGU DTXD + 3 PB30 DBGU DRXD + 4 N/C (may be used by debug interface tool) + 5 PE14 (available) + 6 GND + + The DBGU is not used by NuttX. + +Networking +========== + + Networking support via the can be added to NSH by selecting the following + configuration options. The SAMA5D36 supports two different Ethernet MAC + peripherals: (1) The 10/100Base-T EMAC peripheral and (2) the + 10/100/1000Base-T GMAC peripheral. + + Selecting the EMAC peripheral + ----------------------------- + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_EMAC=y : Enable the EMAC peripheral + + System Type -> EMAC device driver options + CONFIG_SAMA5_EMAC_NRXBUFFERS=16 : Set aside some RS and TX buffers + CONFIG_SAMA5_EMAC_NTXBUFFERS=4 + CONFIG_SAMA5_EMAC_PHYADDR=1 : KSZ9031 PHY is at address 1 + CONFIG_SAMA5_EMAC_AUTONEG=y : Use autonegotiation + CONFIG_SAMA5_EMAC_RMII=y : Either MII or RMII interface should work + CONFIG_SAMA5_EMAC_PHYSR=30 : Address of PHY status register on KSZ9031 + CONFIG_SAMA5_EMAC_PHYSR_ALTCONFIG=y : Needed for KSZ9031 + CONFIG_SAMA5_EMAC_PHYSR_ALTMODE=0x7 : " " " " " " + CONFIG_SAMA5_EMAC_PHYSR_10HD=0x1 : " " " " " " + CONFIG_SAMA5_EMAC_PHYSR_100HD=0x2 : " " " " " " + CONFIG_SAMA5_EMAC_PHYSR_10FD=0x5 : " " " " " " + CONFIG_SAMA5_EMAC_PHYSR_100FD=0x6 : " " " " " " + + PHY selection. Later in the configuration steps, you will need to select + the KSZ9031 PHY for EMAC (See below) + + Selecting the GMAC peripheral + ----------------------------- + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_GMAC=y : Enable the GMAC peripheral + + System Type -> GMAC device driver options + CONFIG_SAMA5_GMAC_NRXBUFFERS=16 : Set aside some RS and TX buffers + CONFIG_SAMA5_GMAC_NTXBUFFERS=4 + CONFIG_SAMA5_GMAC_PHYADDR=1 : KSZ8081 PHY is at address 1 + CONFIG_SAMA5_GMAC_AUTONEG=y : Use autonegotiation + + If both EMAC and GMAC are selected, you will also need: + + CONFIG_SAMA5_GMAC_ISETH0=y : GMAC is "eth0"; EMAC is "eth1" + + PHY selection. Later in the configuration steps, you will need to select + the KSZ9081 PHY for GMAC (See below) + + Common configuration settings + ----------------------------- + + Networking Support + CONFIG_NET=y : Enable Neworking + CONFIG_NET_SOCKOPTS=y : Enable socket operations + CONFIG_NET_BUFSIZE=562 : Maximum packet size (MTD) 1518 is more standard + CONFIG_NET_RECEIVE_WINDOW=562 : Should be the same as CONFIG_NET_BUFSIZE + CONFIG_NET_TCP=y : Enable TCP/IP networking + CONFIG_NET_TCPBACKLOG=y : Support TCP/IP backlog + CONFIG_NET_TCP_READAHEAD_BUFSIZE=562 Read-ahead buffer size + CONFIG_NET_UDP=y : Enable UDP networking + CONFIG_NET_ICMP=y : Enable ICMP networking + CONFIG_NET_ICMP_PING=y : Needed for NSH ping command + : Defaults should be okay for other options + Device drivers -> Network Device/PHY Support + CONFIG_NETDEVICES=y : Enabled PHY selection + CONFIG_ETH0_PHY_KSZ8081=y : Select the KSZ8081 PHY (for EMAC), OR + CONFIG_ETH0_PHY_KSZ90x1=y : Select the KSZ9031 PHY (for GMAC) + + Application Configuration -> Network Utilities + CONFIG_NETUTILS_RESOLV=y : Enable host address resolution + CONFIG_NETUTILS_TELNETD=y : Enable the Telnet daemon + CONFIG_NETUTILS_TFTPC=y : Enable TFTP data file transfers for get and put commands + CONFIG_NETUTILS_UIPLIB=y : Network library support is needed + CONFIG_NETUTILS_WEBCLIENT=y : Needed for wget support + : Defaults should be okay for other options + Application Configuration -> NSH Library + CONFIG_NSH_TELNET=y : Enable NSH session via Telnet + CONFIG_NSH_IPADDR=0x0a000002 : Select an IP address + CONFIG_NSH_DRIPADDR=0x0a000001 : IP address of gateway/host PC + CONFIG_NSH_NETMASK=0xffffff00 : Netmask + CONFIG_NSH_NOMAC=y : Need to make up a bogus MAC address + : Defaults should be okay for other options + + Using the network with NSH + -------------------------- + + So what can you do with this networking support? First you see that + NSH has several new network related commands: + + ifconfig, ifdown, ifup: Commands to help manage your network + get and put: TFTP file transfers + wget: HTML file transfers + ping: Check for access to peers on the network + Telnet console: You can access the NSH remotely via telnet. + + You can also enable other add on features like full FTP or a Web + Server or XML RPC and others. There are also other features that + you can enable like DHCP client (or server) or network name + resolution. + + By default, the IP address of the SAMA5D3-Xplained will be 10.0.0.2 and + it will assume that your host is the gateway and has the IP address + 10.0.0.1. + + nsh> ifconfig + eth0 HWaddr 00:e0:de:ad:be:ef at UP + IPaddr:10.0.0.2 DRaddr:10.0.0.1 Mask:255.255.255.0 + + You can use ping to test for connectivity to the host (Careful, + Window firewalls usually block ping-related ICMP traffic). On the + target side, you can: + + nsh> ping 10.0.0.1 + PING 10.0.0.1 56 bytes of data + 56 bytes from 10.0.0.1: icmp_seq=1 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=2 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=3 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=4 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=5 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=6 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=7 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=8 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=9 time=0 ms + 56 bytes from 10.0.0.1: icmp_seq=10 time=0 ms + 10 packets transmitted, 10 received, 0% packet loss, time 10100 ms + + NOTE: In this configuration is is normal to have packet loss > 0% + the first time you ping due to the default handling of the ARP + table. + + On the host side, you should also be able to ping the SAMA5D3-Xplained: + + $ ping 10.0.0.2 + + You can also log into the NSH from the host PC like this: + + $ telnet 10.0.0.2 + Trying 10.0.0.2... + Connected to 10.0.0.2. + Escape character is '^]'. + sh_telnetmain: Session [3] Started + + NuttShell (NSH) NuttX-6.31 + nsh> help + help usage: help [-v] [<cmd>] + + [ echo ifconfig mkdir mw sleep + ? exec ifdown mkfatfs ping test + cat exit ifup mkfifo ps umount + cp free kill mkrd put usleep + cmp get losetup mh rm wget + dd help ls mount rmdir xd + df hexdump mb mv sh + + Builtin Apps: + nsh> + + NOTE: If you enable this feature, you experience a delay on booting. + That is because the start-up logic waits for the network connection + to be established before starting NuttX. In a real application, you + would probably want to do the network bringup on a separate thread + so that access to the NSH prompt is not delayed. + + This delay will be especially long if the board is not connected to + a network. + +AT25 Serial FLASH +================= + + Connections + ----------- + + Both the SAMA5D3-Xplained board supports an options Serial DataFlash. The + SPI connection is as follows: + + AT25DF321A SAMA5 + --------------- ----------------------------------------------- + SI PD11 SPI0_MOSI + SO PD10 SPI0_MIS0 + SCK PD12 SPI0_SPCK + /CS PD13 if jumper JP6 is closed. + + Configuration + ------------- + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_SPI0=y : Enable SPI0 + CONFIG_SAMA5_DMAC0=y : Enable DMA controller 0 + + System Type -> SPI device driver options + CONFIG_SAMA5_SPI_DMA=y : Use DMA for SPI transfers + CONFIG_SAMA5_SPI_DMATHRESHOLD=4 : Don't DMA for small transfers + + Device Drivers -> SPI Driver Support + CONFIG_SPI=y : Enable SPI support + CONFIG_SPI_EXCHANGE=y : Support the exchange method + + Device Drivers -> Memory Technology Device (MTD) Support + CONFIG_MTD=y : Enable MTD support + CONFIG_MTD_AT25=y : Enable the AT25 driver + CONFIG_AT25_SPIMODE=0 : Use SPI mode 0 + CONFIG_AT25_SPIFREQUENCY=10000000 : Use SPI frequency 10MHz + + The AT25 is capable of higher SPI rates than this. I have not experimented + a lot, but at 20MHz, the behavior is not the same with all CM modules. This + lower rate gives more predictable performance. + + Application Configuration -> NSH Library + CONFIG_NSH_ARCHINIT=y : NSH board-initialization + + Board Selection + CONFIG_SAMA5D3XPLAINED_AT25_AUTOMOUNT=y : Mounts AT25 for NSH + CONFIG_SAMA5D3XPLAINED_AT25_FTL=y : Create block driver for FAT + + NOTE that you must close JP6 in order to enable the AT25 FLASH chip select. + + You can then format the AT25 FLASH for a FAT file system and mount the + file system at /mnt/at25 using these NSH commands: + + nsh> mkfatfs /dev/mtdblock0 + nsh> mount -t vfat /dev/mtdblock0 /mnt/at25 + + Then you an use the FLASH as a normal FAT file system: + + nsh> echo "This is a test" >/mnt/at25/atest.txt + nsh> ls -l /mnt/at25 + /mnt/at25: + -rw-rw-rw- 16 atest.txt + nsh> cat /mnt/at25/atest.txt + This is a test + + NOTE: It appears that if Linux runs out of NAND, it will destroy the + contents of the AT25. + +HSMCI Card Slots +================ + + Physical Slots + -------------- + + The SAMA5D3-Xplained provides a two SD memory card slots: (1) a full size SD + card slot (J10), and (2) a microSD memory card slot (J11). + + The full size SD card slot connects via HSMCI0. The card detect discrete + is available on PD17 (pulled high). The write protect discrete is tied to + ground and not i savailable to software. The slot supports 8-bit wide + transfer mode, but the NuttX driver currently uses only the 4-bit wide + transfer mode + + PD17 MCI0_CD + PD1 MCI0_DA0 + PD2 MCI0_DA1 + PD3 MCI0_DA2 + PD4 MCI0_DA3 + PD5 MCI0_DA4 + PD6 MCI0_DA5 + PD7 MCI0_DA6 + PD8 MCI0_DA7 + PD9 MCI0_CK + PD0 MCI0_CDA + + PE2 PWR_MCI0 + + The microSD connects vi HSMCI1. The card detect discrete is available on + PD18 (pulled high): + + PD18 MCI1_CD + PB20 MCI1_DA0 + PB21 MCI1_DA1 + PB22 MCI1_DA2 + PB23 MCI1_DA3 + PB24 MCI1_CK + PB19 MCI1_CDA + + Configuration Settings + ---------------------- + + Enabling HSMCI support. The SAMA5D3-Xplained provides a two SD memory card + slots: (1) a full size SD card slot (J10), and (2) a microSD memory card + slot (J11). The full size SD card slot connects via HSMCI0; the microSD + connects via HSMCI1. Support for both SD slots can be enabled with the + following settings: + + System Type->ATSAMA5 Peripheral Support + CONFIG_SAMA5_HSMCI0=y : Enable HSMCI0 support + CONFIG_SAMA5_HSMCI1=y : Enable HSMCI1 support + CONFIG_SAMA5_DMAC0=y : DMAC0 is needed by HSMCI0 + CONFIG_SAMA5_DMAC1=y : DMAC1 is needed by HSMCI1 + + System Type + CONFIG_SAMA5_PIO_IRQ=y : PIO interrupts needed + CONFIG_SAMA5_PIOD_IRQ=y : Card detect pins are on PIOD + + Device Drivers -> MMC/SD Driver Support + CONFIG_MMCSD=y : Enable MMC/SD support + CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance + CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards + CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support + CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support + CONFIG_SDIO_DMA=y : Use SDIO DMA + CONFIG_SDIO_BLOCKSETUP=y : Needs to know block sizes + + Library Routines + CONFIG_SCHED_WORKQUEUE=y : Driver needs work queue support + + Application Configuration -> NSH Library + CONFIG_NSH_ARCHINIT=y : NSH board-initialization + + Using the SD card + ----------------- + + 1) After booting, the HSCMI devices will appear as /dev/mmcsd0 + and /dev/mmcsd1. + + 2) If you try mounting an SD card with nothing in the slot, the + mount will fail: + + nsh> mount -t vfat /dev/mmcsd1 /mnt/sd1 + nsh: mount: mount failed: 19 + + NSH can be configured to provide errors as strings instead of + numbers. But in this case, only the error number is reported. The + error numbers can be found in nuttx/include/errno.h: + + #define ENODEV 19 + #define ENODEV_STR "No such device" + + So the mount command is saying that there is no device or, more + correctly, that there is no card in the SD card slot. + + 3) Inserted the SD card. Then the mount should succeed. + + nsh> mount -t vfat /dev/mmcsd1 /mnt/sd1 + nsh> ls /mnt/sd1 + /mnt/sd1: + atest.txt + nsh> cat /mnt/sd1/atest.txt + This is a test + + 4) Before removing the card, you must umount the file system. This is + equivalent to "ejecting" or "safely removing" the card on Windows: It + flushes any cached data to the card and makes the SD card unavailable + to the applications. + + nsh> umount -t /mnt/sd1 + + It is now safe to remove the card. NuttX provides into callbacks + that can be used by an application to automatically unmount the + volume when it is removed. But those callbacks are not used in + these configurations. + +USB Ports +========= + + The SAMA5D3-Xplained features three USB communication ports: + + * Port A Host High Speed (EHCI) and Full Speed (OHCI) multiplexed with + USB Device High Speed Micro AB connector, J6 + + * Port B Host High Speed (EHCI) and Full Speed (OHCI) standard type A + connector, J7 upper port + + * Port C Host Full Speed (OHCI) only standard type A connector, J7 + lower port + + The two USB host ports (only) are equipped with 500-mA high-side power + switch for self-powered and bus-powered applications. + + The USB device port A (J6) features a VBUS insert detection function. + + Port A + ------ + + PIO Signal Name Function + ---- ----------- ------------------------------------------------------- + PE9 VBUS_SENSE VBus detection + + Note: No VBus power switch enable on port A. I think that this limits + this port to a device port or as a host port for self-powered devices + only. + + Port B + ------ + + PIO Signal Name Function + ---- ----------- ------------------------------------------------------- + PE4 EN5V_USBB VBus power enable (via MN3 power switch). To the A1 + pin of J7 Dual USB A connector + + Port C + ------ + + PIO Signal Name Function + ---- ----------- ------------------------------------------------------- + PE3 EN5V_USBC VBus power enable (via MN3 power switch). To the B1 + pin of J7 Dual USB A connector + + Both Ports B and C + ------------------ + + PIO Signal Name Function + ---- ----------- ------------------------------------------------------- + PE5 OVCUR_USB Combined over-current indication from port A and B + +USB High-Speed Device +===================== + + Basic USB High-Speed Device Configuration + ----------------------------------------- + + Support the USB high-speed device (UDPHS) driver can be enabled with these + NuttX configuration settings. + + Device Drivers -> USB Device Driver Support + CONFIG_USBDEV=y : Enable USB device support + CONFIG_USBDEV_DUALSPEED=y : Device support High and Full Speed + CONFIG_USBDEV_DMA=y : Device uses DMA + + System Type -> ATSAMA5 Peripheral Support + CONFIG_SAMA5_UDPHS=y : Enable UDPHS High Speed USB device + + Application Configuration -> NSH Library + CONFIG_NSH_ARCHINIT=y : NSH board-initialization + + Mass Storage Class + ------------------ + + The Mass Storage Class (MSC) class driver is selected for use with + UDPHS: + + Device Drivers -> USB Device Driver Support + CONFIG_USBMSC=y : Enable the USB MSC class driver + CONFIG_USBMSC_EPBULKOUT=1 : Use EP1 for the BULK OUT endpoint + CONFIG_USBMSC_EPBULKIN=2 : Use EP2 for the BULK IN endpoint + + The following setting enables an add-on that can can be used to control + the USB MSC device. It will add two new NSH commands: + + a. msconn will connect the USB serial device and export the AT25 + to the host, and + b. msdis which will disconnect the USB serial device. + + Application Configuration -> System Add-Ons: + CONFIG_SYSTEM_USBMSC=y : Enable the USBMSC add-on + CONFIG_SYSTEM_USBMSC_NLUNS=1 : One LUN + CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 : Minor device zero + CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/mtdblock0" + : Use a single, LUN: The AT25 + : block driver. + + NOTES: + + a. To prevent file system corruption, make sure that the AT25 is un- + mounted *before* exporting the mass storage device to the host: + + nsh> umount /mnt/at25 + nsh> mscon + + The AT25 can be re-mounted after the mass storage class is disconnected: + + nsh> msdis + nsh> mount -t vfat /dev/mtdblock0 /mnt/at25 + + b. If you change the value CONFIG_SYSTEM_USBMSC_DEVPATH1, then you + can export other file systems: + + "/dev/mmcsd1" will export the HSMCI1 microSD + "/dev/mmcsd0" will export the HSMCI0 full-size SD slot + "/dev/ram0" could even be used to export a RAM disk. But you would + first have to use mkrd to create the RAM disk and mkfatfs to put + a FAT file system on it. + + CDC/ACM Serial Device Class + --------------------------- + + This will select the CDC/ACM serial device. Defaults for the other + options should be okay. + + Device Drivers -> USB Device Driver Support + CONFIG_CDCACM=y : Enable the CDC/ACM device + CONFIG_CDCACM_BULKIN_REQLEN=768 : Default too small for high-speed + + The following setting enables an example that can can be used to control + the CDC/ACM device. It will add two new NSH commands: + + a. sercon will connect the USB serial device (creating /dev/ttyACM0), and + b. serdis which will disconnect the USB serial device (destroying + /dev/ttyACM0). + + Application Configuration -> Examples: + CONFIG_SYSTEM_CDCACM=y : Enable an CDC/ACM example + + Debugging USB Device + -------------------- + + There is normal console debug output available that can be enabled with + CONFIG_DEBUG + CONFIG_DEBUG_USB. However, USB device operation is very + time critical and enabling this debug output WILL interfere with the + operation of the UDPHS. USB device tracing is a less invasive way to get + debug information: If tracing is enabled, the USB device will save + encoded trace output in in-memory buffer; if the USB monitor is also + enabled, that trace buffer will be periodically emptied and dumped to the + system logging device (the serial console in this configuration): + + Device Drivers -> "USB Device Driver Support: + CONFIG_USBDEV_TRACE=y : Enable USB trace feature + CONFIG_USBDEV_TRACE_NRECORDS=256 : Buffer 256 records in memory + CONFIG_USBDEV_TRACE_STRINGS=y : (optional) + + Application Configuration -> NSH LIbrary: + CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH + CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor + + Application Configuration -> System NSH Add-Ons: + CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y + CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y + CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y + CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + + NOTE: If USB debug output is also enabled, both outputs will appear on the + serial console. However, the debug output will be asynchronous with the + trace output and, hence, difficult to interpret. + +USB High-Speed Host +=================== + + OHCI Only + --------- + + Support the USB low/full-speed OHCI host driver can be enabled by changing + the NuttX configuration file as follows: + + System Type -> ATSAMA5 Peripheral Support + CONFIG_SAMA5_UHPHS=y : USB Host High Speed + + System Type -> USB High Speed Host driver options + CONFIG_SAMA5_OHCI=y : Low/full-speed OHCI support + : Defaults for values probably OK + Device Drivers + CONFIG_USBHOST=y : Enable USB host support + + Device Drivers -> USB Host Driver Support + CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not used + CONFIG_USBHOST_MSC=y : Enable the mass storage class driver + CONFIG_USBHOST_HIDKBD=y : Enable the HID keyboard class driver + + Library Routines + CONFIG_SCHED_WORKQUEUE=y : Worker thread support is required + + Application Configuration -> NSH Library + CONFIG_NSH_ARCHINIT=y : NSH board-initialization + + NOTE: When OHCI is selected, the SAMA5 will operate at 384MHz instead of + 396MHz. This is so that the PLL generates a frequency which is a multiple + of the 48MHz needed for OHCI. The delay loop calibration values that are + used will be off slightly because of this. + + EHCI + ---- + + Support the USB high-speed EHCI host driver can be enabled by changing the + NuttX configuration file as follows. If EHCI is enabled by itself, then + only high-speed devices can be supported. If OHCI is also enabled, then + all low-, full-, and high speed devices will work. + + System Type -> ATSAMA5 Peripheral Support + CONFIG_SAMA5_UHPHS=y : USB Host High Speed + + System Type -> USB High Speed Host driver options + CONFIG_SAMA5_EHCI=y : High-speed EHCI support + CONFIG_SAMA5_OHCI=y : Low/full-speed OHCI support + : Defaults for values probably OK for both + Device Drivers + CONFIG_USBHOST=y : Enable USB host support + CONFIG_USBHOST_INT_DISABLE=y : Interrupt endpoints not needed + CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not needed + + Device Drivers -> USB Host Driver Support + CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not used + CONFIG_USBHOST_MSC=y : Enable the mass storage class driver + CONFIG_USBHOST_HIDKBD=y : Enable the HID keyboard class driver + + Library Routines + CONFIG_SCHED_WORKQUEUE=y : Worker thread support is required + + Application Configuration -> NSH Library + CONFIG_NSH_ARCHINIT=y : NSH board-initialization + + Mass Storage Device Usage + ------------------------- + + Example Usage: + + NuttShell (NSH) NuttX-6.29 + nsh> ls /dev + /dev: + console + mtdblock0 + null + ttyS0 + + Here a USB FLASH stick is inserted. Nothing visible happens in the + shell. But a new device will appear: + + nsh> ls /dev + /dev: + console + mtdblock0 + null + sda + ttyS0 + nsh> mount -t vfat /dev/sda /mnt/sda + nsh> ls -l /mnt/sda + /mnt/sda: + -rw-rw-rw- 8788 viminfo + drw-rw-rw- 0 .Trash-1000/ + -rw-rw-rw- 3378 zmodem.patch + -rw-rw-rw- 1503 sz-1.log + -rw-rw-rw- 613 .bashrc + + HID Keyboard Usage + ------------------ + + If a (supported) USB keyboard is connected, a /dev/kbda device will appear: + + nsh> ls /dev + /dev: + console + kbda + mtdblock0 + null + ttyS0 + + /dev/kbda is a read-only serial device. Reading from /dev/kbda will get + keyboard input as ASCII data (other encodings are possible): + + nsh> cat /dev/kbda + + Debugging USB Host + ------------------ + + There is normal console debug output available that can be enabled with + CONFIG_DEBUG + CONFIG_DEBUG_USB. However, USB host operation is very time + critical and enabling this debug output might interfere with the operation + of the UDPHS. USB host tracing is a less invasive way to get debug + information: If tracing is enabled, the USB host will save encoded trace + output in in-memory buffer; if the USB monitor is also enabled, that trace + buffer will be periodically emptied and dumped to the system logging device + (the serial console in this configuration): + + Device Drivers -> "USB Host Driver Support: + CONFIG_USBHOST_TRACE=y : Enable USB host trace feature + CONFIG_USBHOST_TRACE_NRECORDS=256 : Buffer 256 records in memory + CONFIG_USBHOST_TRACE_VERBOSE=y : Buffer everything + + Application Configuration -> NSH LIbrary: + CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH + CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor + + Application Configuration -> System NSH Add-Ons: + CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second + + NOTE: If USB debug output is also enabled, both outpus will appear on the + serial console. However, the debug output will be asynchronous with the + trace output and, hence, difficult to interpret. + +NOR FLASH Support +================= + + Most of these configurations execute out of CS0 NOR flash and can only be + loaded via SAM-BA. These are the relevant configuration options the + define the NOR FLASH configuration: + + CONFIG_SAMA5_BOOT_CS0FLASH=y : Boot from FLASH on CS0 + CONFIG_BOOT_RUNFROMFLASH=y : Run in place on FLASH (vs copying to RAM) + + CONFIG_SAMA5_EBICS0=y : Enable CS0 external memory + CONFIG_SAMA5_EBICS0_SIZE=134217728 : Memory size is 128KB + CONFIG_SAMA5_EBICS0_NOR=y : Memory type is NOR FLASH + + CONFIG_FLASH_START=0x10000000 : Physical FLASH start address + CONFIG_FLASH_VSTART=0x10000000 : Virtual FLASH start address + CONFIG_FLASH_SIZE=134217728 : FLASH size (again) + + CONFIG_RAM_START=0x00300400 : Data stored after page table + CONFIG_RAM_VSTART=0x00300400 + CONFIG_RAM_SIZE=114688 : Available size of 128KB - 16KB for page table + + NOTE: In order to boot in this configuration, you need to close the BMS + jumper. + + STATUS: I have been unable to execute these configurations from NOR FLASH + by closing the BMS jumper (J9). As far as I can tell, this jumper does + nothing on my board??? So I have been using the norboot configuration + exclusively to start the program-under-test in NOR FLASH (see the section + entitled "Creating and Using NORBOOT" above.) + +SDRAM Support +============= + + SRAM Heap Configuration + ----------------------- + + In these configurations, .data and .bss are retained in ISRAM. SDRAM can + be initialized and included in the heap. Relevant configuration settings: + + System Type->ATSAMA5 Peripheral Support + CONFIG_SAMA5_MPDDRC=y : Enable the DDR controller + + System Type->External Memory Configuration + CONFIG_SAMA5_DDRCS=y : Tell the system that DRAM is at the DDR CS + CONFIG_SAMA5_DDRCS_SIZE=268435456 : 2Gb DRAM -> 256GB + CONFIG_SAMA5_DDRCS_LPDDR2=y : Its DDR2 + CONFIG_SAMA5D3XPLAINED_MT47H128M16RT=y : This is the type of DDR2 + + System Type->Heap Configuration + CONFIG_SAMA5_DDRCS_HEAP=y : Add the SDRAM to the heap + CONFIG_SAMA5_DDRCS_HEAP_OFFSET=0 + CONFIG_SAMA5_DDRCS_HEAP_SIZE=268435456 + + Memory Management + CONFIG_MM_REGIONS=2 : Two heap memory regions: ISRAM and SDRAM + + RAM Test + -------- + + Another thing you could do is to enable the RAM test built-in application. + You can enable the NuttX RAM test that may be used to verify the external + SDRAM. To do this, keep the SDRAM out of the heap so that it can be tested + without crashing programs using the memory: + + System Type->Heap Configuration + CONFIG_SAMA5_DDRCS_HEAP=n : Don't add the SDRAM to the heap + + Memory Management + CONFIG_MM_REGIONS=1 : One memory regions: ISRAM + + Then enable the RAM test built-in application: + + Application Configuration->System NSH Add-Ons->Ram Test + CONFIG_SYSTEM_RAMTEST=y + + In this configuration, the SDRAM is not added to heap and so is not + accessable to the applications. So the RAM test can be freely executed + against the SRAM memory beginning at address 0x2000:0000 (DDR CS): + + nsh> ramtest -h + Usage: <noname> [-w|h|b] <hex-address> <decimal-size> + + Where: + <hex-address> starting address of the test. + <decimal-size> number of memory locations (in bytes). + -w Sets the width of a memory location to 32-bits. + -h Sets the width of a memory location to 16-bits (default). + -b Sets the width of a memory location to 8-bits. + + To test the entire external 256MB SRAM: + + nsh> ramtest -w 20000000 268435456 + RAMTest: Marching ones: 20000000 268435456 + RAMTest: Marching zeroes: 20000000 268435456 + RAMTest: Pattern test: 20000000 268435456 55555555 aaaaaaaa + RAMTest: Pattern test: 20000000 268435456 66666666 99999999 + RAMTest: Pattern test: 20000000 268435456 33333333 cccccccc + RAMTest: Address-in-address test: 20000000 268435456 + + SDRAM Data Configuration + ------------------------ + + In these configurations, .data and .bss are retained in ISRAM by default. + .data and .bss can also be retained in SDRAM using these slightly + different configuration settings. In this configuration, ISRAM is + used only for the Cortex-A5 page table for the IDLE thread stack. + + System Type->ATSAMA5 Peripheral Support + CONFIG_SAMA5_MPDDRC=y : Enable the DDR controller + + System Type->External Memory Configuration + CONFIG_SAMA5_DDRCS=y : Tell the system that DRAM is at the DDR CS + CONFIG_SAMA5_DDRCS_SIZE=268435456 : 2Gb DRAM -> 256GB + CONFIG_SAMA5_DDRCS_LPDDR2=y : Its DDR2 + CONFIG_SAMA5D3XPLAINED_MT47H128M16RT=y : This is the type of DDR2 + + System Type->Heap Configuration + CONFIG_SAMA5_ISRAM_HEAP=n : These do not apply in this case + CONFIG_SAMA5_DCRS_HEAP=n + + System Type->Boot Memory Configuration + CONFIG_RAM_START=0x20000000 : Physical address of SDRAM + CONFIG_RAM_VSTART=0x20000000 : Virtual address of SDRAM + CONFIG_RAM_SIZE=268435456 : Size of SDRAM + CONFIG_BOOT_SDRAM_DATA=y : Data is in SDRAM + + Care must be used applied these RAM locations; graphics + configurations may use SDRAM in an incompatible way to set aside + LCD framebuffers. + + Memory Management + CONFIG_MM_REGIONS=1 : One heap memory region: ISDRAM + +NAND Support +============ + + NAND support is only partial in that there is no file system that works + with it properly. Lower-level NAND support has been developed and + verified, but there is no way to use it in the current NuttX architecture + other than through the raw MTD interface. + + NAND should still be considered a work in progress. You will not want to + use NAND unless you are interested in investing a little effort, + particularly in infrastructure. See the "STATUS SUMMARY" section below. + + NAND Support + ------------ + + NAND Support can be added to the NSH configuration by modifying the + NuttX configuration file as follows: + + Build Setup + CONFIG_EXPERIMENTAL=y : NXFFS implementation is incomplete and + : not yet fully functional. + + System Type -> SAMA5 Peripheral support + CONFIG_SAMA5_HSMC=y : Make sure that the SMC is enabled + + Drivers -> Memory Technology Device (MTD) Support + CONFIG_MTD=y : Enable MTD support + CONFIG_MTD_NAND=y : Enable NAND support + CONFIG_MTD_NAND_BLOCKCHECK=n : Interferes with NXFFS bad block checking + CONFIG_MTD_NAND_SWECC=y : Use S/W ECC calculation + + Defaults for all other NAND settings should be okay + + System Type -> External Memory Configuration + CONFIG_SAMA5_EBICS3=y : Enable External CS3 memory + CONFIG_SAMA5_EBICS3_NAND=y : Select NAND memory type + CONFIG_SAMA5_EBICS3_SIZE=8388608 : Use this size + CONFIG_SAMA5_EBICS3_SWECC=y : Use S/W ECC calculation + + Defaults for ROM page table addresses should be okay + + Application Configuration -> NSH Library + CONFIG_NSH_ARCHINIT=y : Use architecture-specific initialization + + NOTES: + + 1. WARNING: This will wipe out everything that you may have on the NAND + FLASH! I have found that using the JTAG with no valid image on NAND + or Serial FLASH is a problem: In that case, the code always ends up + in the SAM-BA bootloader. + + My understanding is that you can enable JTAG in this case by simply + entering any data on the DBG serial port. I have not tried this. + Instead, I just changed to boot from Serial Flash: + + 2. Booting from Serial Flash. The work around for this case is to put + the NORBOOT image into Serial FLASH. Then, the system will boot from + Serial FLASH by copying the NORBOOT image in SRAM which will run and + then start the image in NOR FLASH. See the discussion of the NORBOOT + configuration in the "Creating and Using NORBOOT" section above. + + NOTE that there is jumper on the CM module that must be closed to enable + use of the AT25 Serial Flash. Also, if you are using using SAM-BA, + make sure that you load the NOR boot program into the boot area via + the pull-down menu. + + 3. Unfortunately, there are no appropriate NAND file system in NuttX as + of this writing. The following sections discussion issues/problems + with using NXFFS and FAT. + + PMECC + ----- + + Hardware ECC calculation using the SAMA5D3's PMECC can be enable as + follows: + + Drivers -> Memory Technology Device (MTD) Support + CONFIG_MTD_NAND_SWECC=y : Don't use S/W ECC calculation + CONFIG_MTD_NAND_HWECC=y : Use H/W ECC instead + + System Type -> External Memory Configuration + CONFIG_SAMA5_EBICS3_SWECC=n : Don't use S/W ECC calculation + CONFIG_SAMA5_HAVE_PMECC=n : Use H/W ECC instead + + Other PMECC-related default settings should be okay. + + STATUS: As of the writing, NAND transfers using PMECC appear to + work correctly. However, the PMECC based systems do not work as + as well with FAT or NXFFS. My belief that that the FAT/NXFFS layers + are inappropriate for NAND and, as a result, happen not to work with + the PMECC ECC calculation. See also the "STATUS SUMMARY" section below. + + DMA Support + ----------- + + DMA support can be enabled as follows: + + System Type -> SAMA5 Peripheral support + CONFIG_SAMA5_DMAC0=y : Use DMAC0 for memory-to-memory DMA + + System Type -> External Memory Configuration + CONFIG_SAMA5_NAND_DMA=y : Use DMAC0 for NAND data transfers + + STATUS: DMA appears to be functional, but probably has not been + exercised enough to claim that with any certainty. See also the "STATUS + SUMMARY" section below. + + NXFFS + ----- + + The NuttX FLASH File System (NXFFS) works well with NOR-like FLASH + but does not work well with NAND (See comments below under STATUS) + + File Systems: + CONFIG_FS_NXFFS=y : Enable the NXFFS file system + + Defaults for all other NXFFS settings should be okay. + + NOTE: NXFFS will require some significant buffering because of + the large size of the NAND flash blocks. You will also need + to enable SDRAM as described above. + + Board Selection + CONFIG_SAMA5D3XPLAINED_NAND_AUTOMOUNT=y : Enable FS support on NAND + CONFIG_SAMA5D3XPLAINED_NAND_NXFFS=y : Use the NXFFS file system + + Other file systems are not recommended because only NXFFS can handle + bad blocks and only NXFFS performs wear-levelling. + + FAT + --- + + Another option is FAT. FAT, however, is not appropriate for use with + NAND: FAT will not handle bad blocks, does not perform any wear + levelling, and may not conform to writing ordering requirements of NAND. + Also, there appear to be issues with FAT when PMECC is enabled (see + "STATUS SUMMARY" below). + + File Systems: + CONFIG_FS_FAT=y : Enable the FAT FS + CONFIG_FAT_LCNAMES=y : With lower case name support + CONFIG_FAT_LFN=y : And (patented) FAT long file name support + CONFIG_FS_NXFFS=n : Don't need NXFFS + + Defaults for all other NXFFS settings should be okay. + + Board Selection + CONFIG_SAMA5D3XPLAINED_NAND_AUTOMOUNT=y : Enable FS support on NAND + CONFIG_SAMA5D3XPLAINED_NAND_FTL=y : Use an flash translation layer + + NOTE: FTL will require some significant buffering because of + the large size of the NAND flash blocks. You will also need + to enable SDRAM as described above. + + SMART FS + -------- + + Another option is Smart FS. Smart FS is another small file system + designed to work with FLASH. Properties: It does support some wear- + leveling like NXFFS, but like FAT, cannot handle bad blocks and like + NXFFS, it will try to re-write erased bits. + + Using NAND with NXFFS + --------------------- + + With the options CONFIG_SAMA5D3XPLAINED_NAND_AUTOMOUNT=y and + CONFIG_SAMA5D3XPLAINED_NAND_NXFFS=y, the NAND FLASH will be mounted in the NSH + start-up logic before the NSH prompt appears. There is no feedback as + to whether or not the mount was successful. You can, however, see the + mounted file systems using the nsh 'mount' command: + + nsh> mount + /mnt/nand type nxffs + + Then NAND can be used like any other file system: + + nsh> echo "This is a test" >/mnt/nand/atest.txt + nsh> ls -l /mnt/nand + /mnt/nand: + ---x--x--x 16 atest.txt + nsh> cat /mnt/nand/atest.txt + This is a test + + The NAND volume can be un-mounted with this comment: + + nsh> umount /mnt/nand + nsh> mount + + And re-mounted with this command: + + nsh> mount -t nxffs /mnt/mystuff + nsh> mount + /mnt/mystuff type nxffs + + NOTES: + 1. NXFFS can be very slow. The first time that you start the system, + be prepared for a wait; NXFFS will need to format the NAND volume. + I have lots of debug on so I don't yet know what the optimized wait + will be. But with debug ON, software ECC, and no DMA the wait is + in many tens of minutes (and substantially longer if many debug + options are enabled. + + [I don't yet have data for the more optimal cases. It will be + significantly less, but still not fast.] + + 2. On subsequent boots, after the NXFFS file system has been created + the delay will be less. When the new file system is empty, it will + be very fast. But the NAND-related boot time can become substantial + when there has been a lot of usage of the NAND. This is because + NXFFS needs to scan the NAND device and build the in-memory dataset + needed to access NAND and there is more that must be scanned after + the device has been used. You may want to create a separate thread at + boot time to bring up NXFFS so that you don't delay the boot-to-prompt + time excessively in these longer delay cases. + + 3. There is another NXFFS related performance issue: When the FLASH + is fully used, NXFFS will restructure the entire FLASH, the delay + to restructure the entire FLASH will probably be even larger. This + solution in this case is to implement an NXFSS clean-up daemon that + does the job a little-at-a-time so that there is no massive clean-up + when the FLASH becomes full. + + 4. Bad NXFFS behavior with NAND: If you restart NuttX, the files that + you wrote to NAND will be gone. Why? Because the multiple writes + have corrupted the NAND ECC bits. See STATUS below. NXFFS would + require a major overhaul to be usable with NAND. + + Using NAND with FAT + ------------------- + + If configured for FAT, the system will create block driver at + /dev/mtdblock0: + + NuttShell (NSH) + nsh> ls /dev + /dev: + console + mtdblock0 + null + ttyS0 + + You will not that the system comes up immediately because there is not + need to scan the volume in this case.. + + The NSH 'mkfatfs' command can be used to format a FAT file system on + NAND. + + nsh> mkfatfs /dev/mtdblock0 + + This step, on the other hand, requires quite a bit of time. + + And the FAT file system can be mounted like: + + nsh> mount -t vfat /dev/mtdblock0 /mnt/nand + nsh> ls /mnt/nand + /mnt/nand: + + nsh> echo "This is a test" > /mnt/nand/atest.txt + + NOTE: This will take a long time because it will require reading, + modifying, and re-writing the 128KB erase page! + + nsh> ls -l /mnt/nand + /mnt/nand: + -rw-rw-rw- 16 atest.txt + + nsh> cat /mnt/fat/atest.txt + This is a test + + NOTES: + + 1. Unlike NXFFS, FAT can work with NAND (at least with PMECC disabled). + But there are some significant issues. + + 2. First, each NAND write access will cause a 256KB data transfer: It + will read the entire 128KB erase block, modify it and write it back + to memory. There is some caching logic so that this cached erase + block can be re-used if possible and writes will be deferred as long + as possible. + + 3. If you hit a bad block, then FAT is finished. There is no mechanism + in place in FAT not to mark and skip over bad blocks. + + What is Needed + -------------- + + What is needed to work with FAT properly would be another MTD layer + between the FTL layer and the NAND FLASH layer. That layer would + perform bad block detection and sparing so that FAT works transparently + on top of the NAND. + + Another, less general, option would be support bad blocks within FAT. + + STATUS SUMMARY + -------------- + + 1. PMECC appears to be working in that I can write a NAND block with its + ECC and read the block back and verify that that is are no bit + failures. However, when attempting to work with FAT, it does not + work correctly: The MBR is written and read back correctly, but gets + corrupted later for unknown reasons. + + 2. DMA works (at least with software ECC), but I have seen occasional + failures. I recommend enabling DMA with caution. + + In NuttX, DMA will also cost two context switches (and, hence, four + register state transfers). With smaller NAND page sizes (say 2KiB and + below), I would expect little or no performance improvement with DMA + for this reason. + + 3. NXFFS does not work with NAND. NAND differs from other other FLASH + types several ways. For one thing, NAND requires error correction + (ECC) bytes that must be set in order to work around bit failures. + This affects NXFFS in two ways: + + a. First, write failures are not fatal. Rather, they should be tried by + bad blocks and simply ignored. This is because unrecoverable bit + failures will cause read failures when reading from NAND. Setting + the CONFIG_EXPERIMENTAL+CONFIG_NXFFS_NANDs option will enable this + behavior. + + b. Secondly, NXFFS will write a block many times. It tries to keep + bits in the erased state and assumes that it can overwrite those bits + to change them from the erased to the non-erased state. This works + will with NOR-like FLASH. NAND behaves this way too. But the + problem with NAND is that the ECC bits cannot be re-written in this + way. So once a block has been written, it cannot be modified. This + behavior has NOT been fixed in NXFFS. Currently, NXFFS will attempt + to re-write the ECC bits causing the ECC to become corrupted because + the ECC bits cannot be overwritten without erasing the entire block. + + This may prohibit NXFFS from ever being used with NAND. + + 4. As mentioned above, FAT does work but (1) has some performance issues on + writes and (2) cannot handle bad blocks. + +I2C Tool +======== + + I2C Tool. NuttX supports an I2C tool at apps/system/i2c that can be used + to peek and poke I2C devices. That tool cal be enabled by setting the + following: + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_TWI0=y : Enable TWI0 + CONFIG_SAMA5_TWI1=y : Enable TWI1 + CONFIG_SAMA5_TWI2=y : Enable TWI2 + + System Type -> TWI device driver options + SAMA5_TWI0_FREQUENCY=100000 : Select a TWI0 frequency + SAMA5_TWI1_FREQUENCY=100000 : Select a TWI1 frequency + SAMA5_TWI2_FREQUENCY=100000 : Select a TWI2 frequency + + Device Drivers -> I2C Driver Support + CONFIG_I2C=y : Enable I2C support + CONFIG_I2C_TRANSFER=y : Driver supports the transfer() method + CONFIG_I2C_WRITEREAD=y : Driver supports the writeread() method + + Application Configuration -> NSH Library + CONFIG_SYSTEM_I2CTOOL=y : Enable the I2C tool + CONFIG_I2CTOOL_MINBUS=0 : TWI0 has the minimum bus number 0 + CONFIG_I2CTOOL_MAXBUS=2 : TWI2 has the maximum bus number 2 + CONFIG_I2CTOOL_DEFFREQ=100000 : Pick a consistent frequency + + The I2C tool has extensive help that can be accessed as follows: + + nsh> i2c help + Usage: i2c <cmd> [arguments] + Where <cmd> is one of: + + Show help : ? + List busses : bus + List devices : dev [OPTIONS] <first> <last> + Read register : get [OPTIONS] [<repititions>] + Show help : help + Write register: set [OPTIONS] <value> [<repititions>] + Verify access : verf [OPTIONS] [<value>] [<repititions>] + + Where common "sticky" OPTIONS include: + [-a addr] is the I2C device address (hex). Default: 03 Current: 03 + [-b bus] is the I2C bus number (decimal). Default: 0 Current: 0 + [-r regaddr] is the I2C device register address (hex). Default: 00 Current: 00 + [-w width] is the data width (8 or 16 decimal). Default: 8 Current: 8 + [-s|n], send/don't send start between command and data. Default: -n Current: -n + [-i|j], Auto increment|don't increment regaddr on repititions. Default: NO Current: NO + [-f freq] I2C frequency. Default: 100000 Current: 100000 + + NOTES: + o Arguments are "sticky". For example, once the I2C address is + specified, that address will be re-used until it is changed. + + WARNING: + o The I2C dev command may have bad side effects on your I2C devices. + Use only at your own risk. + + As an example, the I2C dev comman can be used to list all devices + responding on TWI0 (the default) like this: + + nsh> i2c dev 0x03 0x77 + 0 1 2 3 4 5 6 7 8 9 a b c d e f + 00: -- -- -- -- -- -- -- -- -- -- -- -- -- + 10: -- -- -- -- -- -- -- -- -- -- 1a -- -- -- -- -- + 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 30: -- -- -- -- -- -- -- -- -- 39 -- -- -- 3d -- -- + 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 60: 60 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 70: -- -- -- -- -- -- -- -- + nsh> + + Address 0x1a is the WM8904. Address 0x39 is the SIL9022A. I am not sure + what is at address 0x3d and 0x60 + +CAN Usage +========= + I planned to verify CAN using the IXXAT USB-to-CAN Compact. This section + provides miscellaneous CAN-related notes, mostly to myself but perhaps of + interest to others. + + [Unfortunately, as of this writing, I still do not have a proper CAN test + bed to verify the CAN driver.] + + CAN Configuration + ----------------- + + The following steps illustrate how to enable CAN0 and/or CAN1 in the NuttX + configuration: + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_CAN0=y : Select CAN0 and/or CAN1 + CONFIG_SAMA5_CAN1=y + + Device Drivers -> CAN Driver Support + CONFIG_CAN=y : (Automatically selected) + CONFIG_CAN_EXTID=y : For extended, 29-bit CAN IDs + + System Type -> CAN Drive Support + CONFIG_SAMA5_CAN0_BAUD=250000 : Select some BAUD for CAN0 (if enabled) + CONFIG_SAMA5_CAN0_NRECVMB=1 : Select number of receive mailboxes (see below) + CONFIG_SAMA5_CAN1_BAUD=250000 : Select some BAUD for CAN1 (if enabled) + CONFIG_SAMA5_CAN1_NRECVMB=1 : Select number of receive mailboxes (see below) + + Receive Mailboxes and Address Filtering + --------------------------------------- + + The SAMA5 CAN0 peripheral supports 8 mailboxes that can be used for sending + and receiving messages. Note that the number of dedicated receive mailboxes + (CONFIG_SAMA5_CANn_NRECVMB) was set to one in the above configuration. This + could be set to any value from 1 to 3 (the upper limit of 3 is purely + arbrary and can be increased with some minor code enhancement). The + remainder can be configured dynamically to send CAN messages. + + Why would you want to use more than one receive mailbox? There are two + reasons. Multiple receive mailboxes might needed to either (1) receive + bursts of messages, or (2) to support multiple groups of messages filtered + on message ID. + + You must also specify the address filtering for each dedicated receive mailbox: + + System Type -> CAN Drive Support + CONFIG_SAMA5_CAN0_ADDR0 and CONFIG_SAMA5_CAN0_MASK0 : If CONFIG_SAMA5_CAN0_NRECVMB >= 1 + CONFIG_SAMA5_CAN0_ADDR1 and CONFIG_SAMA5_CAN0_MASK1 : If CONFIG_SAMA5_CAN0_NRECVMB >= 2 + CONFIG_SAMA5_CAN0_ADDR2 and CONFIG_SAMA5_CAN0_MASK2 : If CONFIG_SAMA5_CAN0_NRECVMB >= 3 + CONFIG_SAMA5_CAN1_ADDR0 and CONFIG_SAMA5_CAN1_MASK0 : If CONFIG_SAMA5_CAN1_NRECVMB >= 1 + CONFIG_SAMA5_CAN1_ADDR1 and CONFIG_SAMA5_CAN1_MASK1 : If CONFIG_SAMA5_CAN1_NRECVMB >= 2 + CONFIG_SAMA5_CAN1_ADDR2 and CONFIG_SAMA5_CAN1_MASK2 : If CONFIG_SAMA5_CAN1_NRECVMB >= 3 + + Only messages that have IDs that match the CONFIG_SAMA5_CANn_ADDRn when both + the received and the configured address are masked by CONFIG_SAMA5_CANn_MASKn + will be accepted. For example, if the mask is all ones, then only messasges + with exact address matches will be accepted; if the mask is all zeroes than + any address will be accepted. + + CAN connectors + -------------- + + CAN1 and CAN2 are available via RJ-11 connectors on the SAMA5D3-Xplained. Each + is wired as follows. Also shown below is the matching pins if you want connect + the CAN to a device that uses an DB-9 connector (Such as the IXXAT USB-to-CAN + Compact). Both connector types (as well as RJ-45) are common. + + +----------+ RJ-11 DB-9 + | O | ----------- -------------- + +------------+ | | Pin 1 3v3 Pin 1 N/C + | +--+ | | o5 | Pin 2 5v Pin 2 CANL + | | | | | o9 | Pin 3 N/C Pin 3 GND + | +-+ +-+ | | o4 | Pin 4 CANL Pin 4 N/C + | | | | | o8 | Pin 5 CANH Pin 5 N/C + | |654321| | | o3 | Pin 6 N/C Pin 6 N/C + | |oooooo| | | o7 | Pin 7 CANH + | +------+ | | o2 | Pin 8 N/C + +------------+ | o6 | Pin 9 CANV+ (N/C on IXXAT) RJ-11 Female | x1 | + | | + | O | + +----------+ + DB-9 Male + +SAMA5 ADC Support +================= + + Basic driver configuration + -------------------------- + ADC support can be added to the NSH configuration. However, there are no + ADC input pins available to the user for ADC testing (the touchscreen ADC + inputs are intended for other functionality). Because of this, there is + not much motivation to enable ADC support on the SAMA5D3-Xplained. This + paragraph is included here, however, for people using a custom SAMA5D3x + board that requires ADC support. + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_ADC=y : Enable ADC driver support + CONFIG_SAMA5_TC0=y : Enable the Timer/counter library need for periodic sampling + + Drivers + CONFIG_ANALOG=y : Should be automatically selected + CONFIG_ADC=y : Should be automatically selected + + System Type -> ADC Configuration + CONFIG_SAMA5_ADC_CHAN0=y : These settings enable the sequencer to collect + CONFIG_SAMA5_ADC_CHAN1=y : Samples from ADC channels 0-3 on each trigger + CONFIG_SAMA5_ADC_CHAN2=y + CONFIG_SAMA5_ADC_CHAN3=y + CONFIG_SAMA5_ADC_SEQUENCER=y + + CONFIG_SAMA5_ADC_TIOA0TRIG=y : Trigger on the TC0, channel 0 output A + CONFIG_SAMA5_ADC_TIOAFREQ=2 : At a frequency of 2Hz + CONFIG_SAMA5_ADC_TIOA_RISING=y : Trigger on the rising edge + + Default ADC settings (like gain and offset) may also be set if desired. + + System Type -> Timer/counter Configuration + CONFIG_SAMA5_TC0_TIOA0=y : Should be automatically selected + + Work queue supported is also needed: + + Library routines + CONFIG_SCHED_WORKQUEUE=y + + ADC Test Example + ---------------- + For testing purposes, there is an ADC program at apps/examples/adc that + will collect a specified number of samples. This test program can be + enabled as follows: + + Application Configuration -> Examples -> ADC example + CONFIG_EXAMPLES_ADC=y : Enables the example code + CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" + + Other default settings for the ADC example should be okay. + + ADC DMA Support + --------------- + At 2Hz, DMA is not necessary nor desire-able. The ADC driver has support + for DMA transfers of converted data (although that support has not been + tested as of this writing). DMA support can be added by include the + following in the configuration. + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_DMAC1=y : Enable DMAC1 support + + System Type -> ADC Configuration + CONFIG_SAMA5_ADC_DMA=y : Enable ADC DMA transfers + CONFIG_SAMA5_ADC_DMASAMPLES=2 : Collect two sets of samples per DMA + + Drivers -> Analog device (ADC/DAC) support + CONFIG_ADC_FIFOSIZE=16 : Driver may need a large ring buffer + + Application Configuration -> Examples -> ADC example + CONFIG_EXAMPLES_ADC_GROUPSIZE=16 : Larger buffers in the test + +SAMA5 PWM Support +================= + + Basic driver configuration + -------------------------- + PWM support can be added to the NSH configuration. However, there are no + PWM output pins available to the user for PWM testing. Because of this, + there is not much motivation to enable PWM support on the SAMA5D3-Xplained. This + paragraph is included here, however, for people using a custom SAMA5D3x + board that requires PWM support. + + Basic driver configuration: + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_PWM=y : Enable PWM driver support + + Drivers + CONFIG_PWM=y : Should be automatically selected + + PWM Channel/Output Selection + ---------------------------- + In order to use the PWM, you must enable one or more PWM Channels: + + System Type -> PWM Configuration + CONFIG_SAMA5_PWM_CHAN0=y : Enable one or more of channels 0-3 + CONFIG_SAMA5_PWM_CHAN1=y + CONFIG_SAMA5_PWM_CHAN2=y + CONFIG_SAMA5_PWM_CHAN3=y + + For each channel that is enabled, you must also specify the output pins + to be enabled and the clocking supplied to the PWM channel. + + CONFIG_SAMA5_PWM_CHANx_FAULTINPUT=n : (not used currently) + CONFIG_SAMA5_PWM_CHANx_OUTPUTH=y : Enable One of both of the H and L output pins + CONFIG_SAMA5_PWM_CHANx_OUTPUTL=y + + Where x=0..3. + + Care must be taken because all PWM output pins conflict with some other + usage of the pin by other devices. Furthermore, many of these pins have + not been brought out to an external connector: + + -----+---+---+----+------+---------------- + PWM PIN PER PIO I/O CONFLICTS + -----+---+---+----+------+---------------- + PWM0 FI B PC28 J2.30 SPI1, ISI + H B PB0 --- GMAC + B PA20 J1.14 LCDC, ISI + L B PB1 --- GMAC + B PA21 J1.16 LCDC, ISI + -----+---+---+----+------+---------------- + PWM1 FI B PC31 J2.36 HDMI + H B PB4 --- GMAC + B PA22 J1.18 LCDC, ISI + L B PB5 --- GMAC + B PE31 J3.20 ISI, HDMI + B PA23 J1.20 LCDC, ISI + -----+---+---+----+------+---------------- + PWM2 FI B PC29 J2.29 UART0, ISI, HDMI + H C PD5 --- HSMCI0 + B PB8 --- GMAC + L C PD6 --- HSMCI0 + B PB9 --- GMAC + -----+---+---+----+------+---------------- + PWM3 FI C PD16 --- SPI0, Audio + H C PD7 --- HSMCI0 + B PB12 J3.7 GMAC + L C PD8 --- HSMCI0 + B PB13 --- GMAC + -----+---+---+----+-------------------- + + See configs/sama5d3-xplained/include/board.h for all of the default PWM + pin selections. I used PWM channel 0, pins PA20 and PA21 for testing. + + Clocking is addressed in the next paragraph. + + PWM Clock Configuration + ----------------------- + PWM Channels can be clocked from either a coarsely divided divided down + MCK or from a custom frequency from PWM CLKA and/or CLKB. If you want + to use CLKA or CLKB, you must enable and configure them. + + System Type -> PWM Configuration + CONFIG_SAMA5_PWM_CLKA=y + CONFIG_SAMA5_PWM_CLKA_FREQUENCY=3300 + CONFIG_SAMA5_PWM_CLKB=y + CONFIG_SAMA5_PWM_CLKB_FREQUENCY=3300 + + Then for each of the enabled, channels you must select the input clock + for that channel: + + System Type -> PWM Configuration + CONFIG_SAMA5_PWM_CHANx_CLKA=y : Pick one of MCK, CLKA, or CLKB (only) + CONFIG_SAMA5_PWM_CHANx_CLKB=y + CONFIG_SAMA5_PWM_CHANx_MCK=y + CONFIG_SAMA5_PWM_CHANx_MCKDIV=128 : If MCK is selected, then the MCK divider must + : also be provided (1,2,4,8,16,32,64,128,256,512, or 1024). + + PWM Test Example + ---------------- + For testing purposes, there is an PWM program at apps/examples/pwm that + will collect a specified number of samples. This test program can be + enabled as follows: + + Application Configuration -> Examples -> PWM example + CONFIG_EXAMPLES_PWM=y : Enables the example code + + Other default settings for the PWM example should be okay. + + CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm0" + CONFIG_EXAMPLES_PWM_FREQUENCY=100 + + Usage of the example is straightforward: + + nsh> pwm -h + Usage: pwm [OPTIONS] + + Arguments are "sticky". For example, once the PWM frequency is + specified, that frequency will be re-used until it is changed. + + "sticky" OPTIONS include: + [-p devpath] selects the PWM device. Default: /dev/pwm0 Current: /dev/pwm0 + [-f frequency] selects the pulse frequency. Default: 100 Hz Current: 100 Hz + [-d duty] selects the pulse duty as a percentage. Default: 50 % Current: 50 % + [-t duration] is the duration of the pulse train in seconds. Default: 5 Current: 5 + [-h] shows this message and exits + +RTC +=== + + The Real Time Clock/Calendar RTC) may be enabled with these settings: + + System Type: + CONFIG_SAMA5_RTC=y : Enable the RTC driver + + Drivers (these values will be selected automatically): + CONFIG_RTC=y : Use the RTC for system time + CONFIG_RTC_DATETIME=y : RTC supports data/time + + The RTC supports an alarm that may be enable with the following settings. + However, there is nothing in the system that currently makes use of this + alarm. + + Drivers: + CONFIG_RTC_ALARM=y : Enable the RTC alarm + + Library Routines + CONFIG_SCHED_WORKQUEUE=y : Alarm needs work queue support + +Watchdog Timer +============== + + NSH can be configured to exercise the watchdog timer test + (apps/examples/watchdog). This can be selected with the following + settings in the NuttX configuration file: + + System Type: + CONFIG_SAMA5_WDT=y : Enable the WDT peripheral + : Defaults in "RTC Configuration" should be OK + + Drivers (this will automatically be selected): + CONFIG_WATCHDOG=y : Enables watchdog timer driver support + + Application Configuration -> Examples + CONFIG_EXAMPLES_WATCHDOG=y : Enable apps/examples/watchdog + + The WDT timer is driven off the slow, 32768Hz clock divided by 128. As a + result, the watchdog a maximum timeout value of 16 seconds. The SAMA5 WDT + may also only be programmed one time; the processor must be reset before + the WDT can be reprogrammed. + + The SAMA5 always boots with the watchdog timer enabled at its maximum + timeout (16 seconds). In the normal case where no watchdog timer driver + has been configured, the watchdog timer is disabled as part of the start + up logic. But, since we are permitted only one opportunity to program + the WDT, we cannot disable the watchdog time if CONFIG_SAMA5_WDT=y. So, + be forewarned: You have only 16 seconds to run your watchdog timer test! + + NOTE: If you are using the norboot program to run from FLASH as I did, + beware that the default version also disables the watchdog. You will + need a special version of norboot with CONFIG_SAMA5_WDT=y. + +TRNG and /dev/random +==================== + + NSH can be configured to enable the SAMA5 TRNG peripheral so that it + provides /dev/random. The following configuration will enable the TRNG, + /dev/random, and the simple test of /dev/random at apps/examples/ranadom: + + System Type: + CONFIG_SAMA5_TRNG=y : Enable the TRNG peripheral + + Drivers (automatically selected): + CONFIG_DEV_RANDOM=y : Enable /dev/random + + Applications -> Examples + CONFIG_EXAMPLES_RANDOM=y : Enable apps/examples/random + CONFIG_EXAMPLES_MAXSAMPLES=64 : Default settings are probably OK + CONFIG_EXAMPLES_NSAMPLES=8 + +I2S Audio Support +================= + + The SAMA5D3-Xplained has two devices on-board that can be used for verification + of I2S functionality: HDMI and a WM8904 audio CODEC. As of this writing, + the I2S driver is present, but there are not drivers for either the HDMI + or the WM8904. + + WM8904 Audio CODEC Interface + ---------------------------- + + ------------- ---------------- ----------------- + WM8904 SAMA5D3 NuttX Pin Name + ------------- ---------------- ----------------- + 3 SDA PA30 TWD0 PIO_TWI0_D + 2 SCLK PA31 TWCK0 PIO_TWI0_CK + 28 MCLK PD30 PCK0 PIO_PMC_PCK0 + 29 BCLK/GPIO4 PC16 TK PIO_SSC0_TK + "" " " PC19 RK PIO_SSC0_RK + 30 LRCLK PC17 TF PIO_SSC0_TF + "" " " PC20 RF PIO_SSC0_RF + 31 ADCDAT PC21 RD PIO_SSC0_RD + 32 DACDAT PC18 TD PIO_SSC0_TD + 1 IRQ/GPIO1 PD16 INT_AUDIO N/A + ------------- ---------------- ----------------- + + I2S Loopback Test + ----------------- + + The I2S driver was verified using a special I2C character driver (at + nuttx/drivers/audio/i2schar.c) and a test driver at apps/examples/i2schar. + The I2S driver was verified in loopback mode with no audio device. + + [NOTE: The above statement is anticipatory: As of this writing I2S driver + verification is underway and still not complete]. + + This section describes the modifications to the NSH configuration that were + used to perform the I2S testing: + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_SSCO=y : Enable SSC0 driver support + CONFIG_SAMA5_DMAC0=y : DMAC0 required by SSC0 + + Alternatively, SSC1 could have be used: + + System Type -> SAMA5 Peripheral Support + CONFIG_SAMA5_SSC1=y : Enable SSC0 driver support + CONFIG_SAMA5_DMAC1=y : DMAC0 required by SSC0 + + System Type -> SSC Configuration + CONFIG_SAMA5_SSC_MAXINFLIGHT=16 : Up to 16 pending DMA transfers + CONFIG_SAMA5_SSC0_MASTER=y : Master mode + CONFIG_SAMA5_SSC0_DATALEN=16 : 16-bit data + CONFIG_SAMA5_SSC0_RX=y : Support a receiver + CONFIG_SAMA5_SSC0_RX_RKINPUT=y : Receiver gets clock from RK input + CONFIG_SAMA5_SSC0_TX=y : Support a transmitter + CONFIG_SAMA5_SSC0_TX_MCKDIV=y : Transmitter gets clock from MCK/2 + CONFIG_SAMA5_SSC0_MCKDIV_SAMPLERATE=48000 : Sampling at 48K samples/sec + CONFIG_SAMA5_SSC0_TX_TKOUTPUT_XFR=y : Outputs clock on TK when transferring data + CONFIG_SAMA5_SSC0_LOOPBACK=y : Loopmode mode connects RD/TD and RK/TK + + Audio + CONFIG_AUDIO=y : Audio support needed + : Defaults should be okay + + Drivers -> Audio + CONFIG_I2S=y : General I2S support + CONFIG_AUDIO_DEVICES=y : Audio device support + CONFIG_AUDIO_I2SCHAR=y : Build I2S character driver + + The following describes how I have the test application at + apps/examples/i2schar configured: + + CONFIG_EXAMPLES_I2SCHAR=y + CONFIG_EXAMPLES_I2SCHAR_DEVPATH="/dev/i2schar0" + CONFIG_EXAMPLES_I2SCHAR_TX=y + CONFIG_EXAMPLES_I2SCHAR_TXBUFFERS=4 + CONFIG_EXAMPLES_I2SCHAR_TXSTACKSIZE=1536 + CONFIG_EXAMPLES_I2SCHAR_RX=y + CONFIG_EXAMPLES_I2SCHAR_RXBUFFERS=4 + CONFIG_EXAMPLES_I2SCHAR_RXSTACKSIZE=1536 + CONFIG_EXAMPLES_I2SCHAR_BUFSIZE=256 + CONFIG_EXAMPLES_I2SCHAR_DEVINIT=y + + Board Selection + CONFIG_SAMA5D3XPLAINED_I2SCHAR_MINOR=0 + CONFIG_SAMA5D3XPLAINED_SSC_PORT=0 : 0 or SSC0, 1 for SSC1 + + Library Routines + CONFIG_SCHED_WORKQUEUE=y : Driver needs work queue support + +SAMA5D3-Xplained Configuration Options +================================= + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH="arm" + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXA5=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP="sama5" + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_SAMA5=y + + and one of: + + CONFIG_ARCH_CHIP_ATSAMA5D31=y + CONFIG_ARCH_CHIP_ATSAMA5D33=y + CONFIG_ARCH_CHIP_ATSAMA5D34=y + CONFIG_ARCH_CHIP_ATSAMA5D35=y + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD="sama5d3-xplained" (for the SAMA5D3-Xplained development board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_SAMA5D3_XPLAINED=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case): + + CONFIG_RAM_SIZE=0x0002000 (128Kb) + + CONFIG_RAM_START - The physical start address of installed DRAM + + CONFIG_RAM_START=0x20000000 + + CONFIG_RAM_VSTART - The virutal start address of installed DRAM + + CONFIG_RAM_VSTART=0x20000000 + + CONFIG_ARCH_IRQPRIO - The SAM3UF103Z supports interrupt prioritization + + CONFIG_ARCH_IRQPRIO=y + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibrate + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + + CONFIG_SAMA5_DBGU - Debug Unit Interrupt + CONFIG_SAMA5_PIT - Periodic Interval Timer Interrupt + CONFIG_SAMA5_WDT - Watchdog timer Interrupt + CONFIG_SAMA5_HSMC - Multi-bit ECC Interrupt + CONFIG_SAMA5_SMD - SMD Soft Modem + CONFIG_SAMA5_USART0 - USART 0 + CONFIG_SAMA5_USART1 - USART 1 + CONFIG_SAMA5_USART2 - USART 2 + CONFIG_SAMA5_USART3 - USART 3 + CONFIG_SAMA5_UART0 - UART 0 + CONFIG_SAMA5_UART1 - UART 1 + CONFIG_SAMA5_TWI0 - Two-Wire Interface 0 + CONFIG_SAMA5_TWI1 - Two-Wire Interface 1 + CONFIG_SAMA5_TWI2 - Two-Wire Interface 2 + CONFIG_SAMA5_HSMCI0 - High Speed Multimedia Card Interface 0 + CONFIG_SAMA5_HSMCI1 - High Speed Multimedia Card Interface 1 + CONFIG_SAMA5_HSMCI2 - High Speed Multimedia Card Interface 2 + CONFIG_SAMA5_SPI0 - Serial Peripheral Interface 0 + CONFIG_SAMA5_SPI1 - Serial Peripheral Interface 1 + CONFIG_SAMA5_TC0 - Timer Counter 0 (ch. 0, 1, 2) + CONFIG_SAMA5_TC1 - Timer Counter 1 (ch. 3, 4, 5) + CONFIG_SAMA5_PWM - Pulse Width Modulation Controller + CONFIG_SAMA5_ADC - Touch Screen ADC Controller + CONFIG_SAMA5_DMAC0 - DMA Controller 0 + CONFIG_SAMA5_DMAC1 - DMA Controller 1 + CONFIG_SAMA5_UHPHS - USB Host High Speed + CONFIG_SAMA5_UDPHS - USB Device High Speed + CONFIG_SAMA5_GMAC - Gigabit Ethernet MAC + CONFIG_SAMA5_EMAC - Ethernet MAC + CONFIG_SAMA5_LCDC - LCD Controller + CONFIG_SAMA5_ISI - Image Sensor Interface + CONFIG_SAMA5_SSC0 - Synchronous Serial Controller 0 + CONFIG_SAMA5_SSC1 - Synchronous Serial Controller 1 + CONFIG_SAMA5_CAN0 - CAN controller 0 + CONFIG_SAMA5_CAN1 - CAN controller 1 + CONFIG_SAMA5_SHA - Secure Hash Algorithm + CONFIG_SAMA5_AES - Advanced Encryption Standard + CONFIG_SAMA5_TDES - Triple Data Encryption Standard + CONFIG_SAMA5_TRNG - True Random Number Generator + CONFIG_SAMA5_ARM - Performance Monitor Unit + CONFIG_SAMA5_FUSE - Fuse Controller + CONFIG_SAMA5_MPDDRC - MPDDR controller + + Some subsystems can be configured to operate in different ways. The drivers + need to know how to configure the subsystem. + + CONFIG_SAMA5_PIOA_IRQ - Support PIOA interrupts + CONFIG_SAMA5_PIOB_IRQ - Support PIOB interrupts + CONFIG_SAMA5_PIOC_IRQ - Support PIOD interrupts + CONFIG_SAMA5_PIOD_IRQ - Support PIOD interrupts + CONFIG_SAMA5_PIOE_IRQ - Support PIOE interrupts + + CONFIG_USART0_ISUART - USART0 is configured as a UART + CONFIG_USART1_ISUART - USART1 is configured as a UART + CONFIG_USART2_ISUART - USART2 is configured as a UART + CONFIG_USART3_ISUART - USART3 is configured as a UART + + ST91SAMA5 specific device driver settings + + CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=0,1,2,3) or UART + m (m=4,5) for the console and ttys0 (default is the USART1). + CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_U[S]ARTn_2STOP - Two stop bits + + AT91SAMA5 USB Host Configuration + Pre-requisites + + CONFIG_USBDEV - Enable USB device support + CONFIG_USBHOST - Enable USB host support + CONFIG_SAMA5_UHPHS - Needed + CONFIG_SAMA5_OHCI - Enable the STM32 USB OTG FS block + CONFIG_SCHED_WORKQUEUE - Worker thread support is required + + Options: + + CONFIG_SAMA5_OHCI_NEDS + Number of endpoint descriptors + CONFIG_SAMA5_OHCI_NTDS + Number of transfer descriptors + CONFIG_SAMA5_OHCI_TDBUFFERS + Number of transfer descriptor buffers + CONFIG_SAMA5_OHCI_TDBUFSIZE + Size of one transfer descriptor buffer + CONFIG_USBHOST_INT_DISABLE + Disable interrupt endpoint support + CONFIG_USBHOST_ISOC_DISABLE + Disable isochronous endpoint support + CONFIG_USBHOST_BULK_DISABLE + Disable bulk endpoint support + +config SAMA5_OHCI_REGDEBUG + +Configurations +============== + + Information Common to All Configurations + ---------------------------------------- + Each SAMA5D3-Xplained configuration is maintained in a sub-directory and + can be selected as follow: + + cd tools + ./configure.sh sama5d3-xplained/<subdir> + cd - + . ./setenv.sh + + Before sourcing the setenv.sh file above, you should examine it and perform + edits as necessary so that TOOLCHAIN_BIN is the correct path to the directory + than holds your toolchain binaries. + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + + make + + The <subdir> that is provided above as an argument to the tools/configure.sh + must be is one of the following. + + NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless stated otherwise, all configurations generate console + output on UART0 (J3). + + 3. All of these configurations use the Code Sourcery for Windows toolchain + (unless stated otherwise in the description of the configuration). That + toolchain selection can easily be reconfigured using 'make menuconfig'. + Here are the relevant current settings: + + Build Setup: + CONFIG_HOST_WINDOWS=y : Microsoft Windows + CONFIG_WINDOWS_CYGWIN=y : Using Cygwin or other POSIX environment + + System Type -> Toolchain: + CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW=y : GNU EABI toolchain for windows + + That same configuration will work with Atmel GCC toolchain. The only + change required to use the Atmel GCC toolchain is to change the PATH + variable so that those tools are selected instead of the CodeSourcery + tools. Try 'which arm-none-eabi-gcc' to make sure that you are + selecting the right tool. + + The setenv.sh file is available for you to use to set the PATH + variable. The path in the that file may not, however, be correct + for your installation. + + See also the "NOTE about Windows native toolchains" in the section call + "GNU Toolchain Options" above. + + !!!WARNING!!! The first time that you type 'make', the system will + configure itself based on the settings in the .config file. One of + these settings can cause a lot of confusion if you configure the build + in the wrong state: If you are running on Linux, make *certain* that + you have CONFIG_HOST_LINUX=y *before* the first make or you will + create a very corrupt configuration that may not be easy to recover + from. + + Configuration Sub-directories + ----------------------------- + Summary: Some of the descriptions below are long and wordy. Here is the + concise summary of the available SAMA5D3-Xplained configurations: + + norboot: + This is a little program to help debug of code in NOR flash. I wrote + it because I don't yet understand how to get the SAMA5 to boot from + NOR FLASH. See the description below and the section above entitled + "Creating and Using NORBOOT" for more information + nsh: This is another NSH configuration, not too different from the + demo configuration. The nsh configuration is, however, bare bones. + It is the simplest possible NSH configuration and is useful as a + platform for debugging and integrating new features in isolation. + + There may be issues with some of these configurations. See the details + before of the status of individual configurations. + + Now for the gory details: + + norboot: + This is a little program to help debug of code in NOR flash. It + does the following: + + - It enables and configures NOR FLASH, then + - Waits for you to break in with GDB. + + At that point, you can set the PC and begin executing from NOR FLASH + under debug control. See the section entitled "Creating and Using + NORBOOT" above. + + NOTES: + + 1. This program derives from the hello configuration. All of the + notes there apply to this configuration as well. + + 2. The default norboot program initializes the NOR memory, + displays a message and halts. The norboot program can also be + configured to jump directly into NOR FLASH without requiring the + final halt and go by setting CONFIG_SAMA5D3XPLAINED_NOR_START=y in the + NuttX configuration. + + 3. Be aware that the default norboot also disables the watchdog. + Since you will not be able to re-enable the watchdog later, you may + need to set CONFIG_SAMA5_WDT=y in the NuttX configuration file. + + 4. If you put norboot on the Serial FLASH, you can automatically + boot to NOR on reset. See the section "Creating and Using NORBOOT" + above. + + STATUS: + See the To-Do list below + + nsh: + + This configuration directory provide the NuttShell (NSH). There are + two NSH configurations: nsh and demo. The difference is that nsh is + intended to be a very simple NSH configuration upon which you can build + further functionality. The demo configuration, on the other hand, is + intended to be a rich configuration that shows many features all working + together. + + NOTES: + 1. This configuration uses the default USART1 serial console. That + is easily changed by reconfiguring to (1) enable a different + serial peripheral, and (2) selecting that serial peripheral as + the console device. + + 2. By default, this configuration is set up to build on Windows + under either a Cygwin or MSYS environment using a recent, Windows- + native, generic ARM EABI GCC toolchain (such as the CodeSourcery + toolchain). Both the build environment and the toolchain + selection can easily be changed by reconfiguring: + + CONFIG_HOST_WINDOWS=y : Windows operating system + CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows + CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows + + If you are running on Linux, make *certain* that you have + CONFIG_HOST_LINUX=y *before* the first make or you will create a + corrupt configuration that may not be easy to recover from. See + the warning in the section "Information Common to All Configurations" + for further information. + + 3. This configuration executes out of CS0 NOR flash and can only + be loaded via SAM-BA. The are the relevant configuration options + are provided above in the section entitled "NOR FLASH Support". + + 4. This configuration has support for NSH built-in applications enabled. + However, no built-in applications are selected in the base configuration. + + 5. Data resides in ISRAM, but can be moved to SDRAM as described above + under "SDRAM Data Configuration." + + 6. This configuration has support for the FAT file system built in. However, + by default, there are no block drivers initialized. The FAT file system can + still be used to create RAM disks. + + 7. SDRAM support can be enabled by modifying your NuttX configuration as + described above in the paragraph entitle "SDRAM Support" + + 8. The SAMA5D3 Xplained board includes an option serial DataFlash. Support + for that serial FLASH can be enabled by modifying the NuttX configuration + as described above in the paragraph entitled "AT25 Serial FLASH". + + 9. Enabling HSMCI support. The SAMA5D3-Xplained provides a two SD memory + card slots: (1) a full size SD card slot (J10), and (2) a microSD + memory card slot (J11). The full size SD card slot connects via HSMCI0; + the microSD connects vi HSMCI1. Support for both SD slots can be enabled + with the settings provided in the paragraph entitled "HSMCI Card Slots" + above. + + 10. Support the USB low-, high- and full-speed OHCI host driver can be enabled + by changing the NuttX configuration file as described in the section + entitled "USB High-Speed Host" above. + + 11. Support the USB high-speed USB device driver (UDPHS) can be enabled + by changing the NuttX configuration file as described above in the + section entitled "USB High-Speed Device." + + 12. I2C Tool. NuttX supports an I2C tool at apps/system/i2c that can be + used to peek and poke I2C devices. See the discussion above under + "I2C Tool" for detailed configuration settings. + + 13. Networking support via the can be added to NSH by modifying the + configuration. See the "Networking" section above for detailed + configuration settings. + + 16. The Real Time Clock/Calendar RTC) may be enabled by reconfiguring NuttX. + See the section entitled "RTC" above for detailed configuration settings. + + 17. This example can be configured to exercise the watchdog timer test + (apps/examples/watchdog). See the detailed configuration settings in + the section entitled "Watchdog Timer" above. + + 18. This example can be configured to enable the SAMA5 TRNG peripheral so + that it provides /dev/random. See the section entitled "TRNG and + /dev/random" above for detailed configuration information. + + 19. See also the sections above for additional configuration options: + "CAN Usage", "SAMA5 ADC Support", "SAMA5 PWM Support", "I2S Audio + Support" + + STATUS: + See the To-Do list below + + I2C + 2014-9-12: The I2C tool, however, seems to work well. It succesfully + enumerates the devices on the bus and successfully exchanges a few + commands. The real test of the come later when a real I2C device is + integrated. + +To-Do List +========== + +1) Currently the SAMA5Dx is running at 396MHz in these configurations. This + is because the timing for the PLLs, NOR FLASH, and SDRAM came from the + Atmel NoOS sample code which runs at that rate. The SAMA5Dx is capable + of running at 528MHz, however. The setup for that configuration exists + in the Bareboard assembly language setup and should be incorporated. + +2) Most of these configurations execute from NOR FLASH. I have been unable + to execute these configurations from NOR FLASH by closing the BMS jumper + (J9). As far as I can tell, this jumper does nothing on my board??? I + have been using the norboot configuration to start the program in NOR + FLASH (see just above). See "Creating and Using NORBOOT" above. + +3) Neither USB OHCI nor EHCI support Isochronous endpoints. Interrupt + endpoint support in the EHCI driver is untested (but works in similar + EHCI drivers). + +4) HSCMI TX DMA support is currently commented out. + +5) I believe that there is an issue when the internal AT25 FLASH is + formatted by NuttX. That format works fine with Linux, but does not + appear to work with Windows. Reformatting on Windows can resolve this. + NOTE: This is not a SAMA5Dx issue. + + UPDATE: Two important bugs were recently fixed in the NuttX FAT + formatting function (mkfatfs). It is likely that these fixes will + eliminate this issue, but that has not yet been verified. + +6) CAN testing has not yet been performed due to issues with cabling. I + just do not have a good test bed (or sufficient CAN knowledge) for + good CAN testing. + +7) The NxWM example does not work well. This example was designed to work + with much smaller displays and does not look good or work well with the + SAMA5D3-Xplained's 800x480 display. See above for details. + +8) I have a Camera, but there is still no ISI driver. I am not sure what to + do with the camera. NuttX needs something like V4L to provide the + definition for what a camera driver is supposed to do. + + I will probably develop a test harness for ISI, but it is of only + minimal value with no OS infrastructure to deal with images and video. + +9) GMAC has only been tested on a 10/100Base-T network. I don't have a + 1000Base-T network to support additional testing. diff --git a/nuttx/configs/sama5d3-xplained/include/board.h b/nuttx/configs/sama5d3-xplained/include/board.h new file mode 100644 index 000000000..59292dfdf --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/include/board.h @@ -0,0 +1,341 @@ +/************************************************************************************ + * configs/sama5d3-xplained/include/board.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_H +#define __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. These + * definitions will configure operational clocking. + */ + +#if 1 /* #if !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */ +/* This is the configuration provided in the Atmel example code. This setup results + * in a CPU clock of 396MHz. + * + * In this configuration, UPLL is the source of the UHPHS clock (if enabled). + */ + +# include <arch/board/board_396mhz.h> + +#else +/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz + * USB clock with the required accuracy using only PLLA. When PPLA is used to clock + * OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup + * results in a CPU clock of 384MHz. + */ + +# include <arch/board/board_384mhz.h> + +#endif + +/* LED definitions ******************************************************************/ +/* There are two LEDs on the SAMA5D3 series-CM board that can be controlled + * by software. A blue LED is controlled via PIO pins. A red LED normally + * provides an indication that power is supplied to the board but can also + * be controlled via software. + * + * PE23. This blue LED is pulled high and is illuminated by pulling PE23 + * low. + * + * PE24. The red LED is also pulled high but is driven by a transistor so + * that it is illuminated when power is applied even if PE24 is not + * configured as an output. If PE24 is configured as an output, then the + * LCD is illuminated by a high output. + */ + +/* LED index values for use with sam_setled() */ + +#define BOARD_BLUE 0 +#define BOARD_RED 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with sam_setleds() */ + +#define BOARD_BLUE_BIT (1 << BOARD_BLUE) +#define BOARD_RED_BIT (1 << BOARD_RED) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows: + * + * SYMBOL Val Meaning LED state + * Blue Red + * ----------------- --- ----------------------- -------- -------- */ +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON OFF */ +#define LED_INIRQ 2 /* In an interrupt No change */ +#define LED_SIGNAL 2 /* In a signal handler No change */ +#define LED_ASSERTION 2 /* An assertion failed No change */ +#define LED_PANIC 3 /* The system has crashed OFF Blinking */ +#undef LED_IDLE /* MCU is is sleep mode Not used */ + +/* Thus if the blue LED is statically on, NuttX has successfully booted and + * is, apparently, running normmally. If the red is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* Button definitions ***************************************************************/ +/* The following push buttons switches are available: + * + * 1. One board reset button (BP2). When pressed and released, this push + * button causes a power-on reset of the whole board. + * + * 2. One wakeup pushbutton that brings the processor out of Low-power mode + * (BP1) + * + * 3. One user pushbutton (BP3) + * + * Only the user push button (BP3) is controllable by software: + * + * - PE29. Pressing the switch connect PE29 to ground. Therefore, PE29 + * must be pulled high internally. When the button is pressed the SAMA5 + * will sense "0" is on PE29. + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* NAND *****************************************************************************/ + +/* Address for transferring command bytes to the nandflash, CLE A22*/ + +#define BOARD_EBICS3_NAND_CMDADDR 0x60400000 + +/* Address for transferring address bytes to the nandflash, ALE A21*/ + +#define BOARD_EBICS3_NAND_ADDRADDR 0x60200000 + +/* Address for transferring data bytes to the nandflash.*/ + +#define BOARD_EBICS3_NAND_DATAADDR 0x60000000 + +/* PIO configuration ****************************************************************/ +/* PWM. There are no dedicated PWM output pins available to the user for PWM + * testing. Care must be taken because all PWM output pins conflict with some other + * usage of the pin by other devices. Furthermore, many of these pins have not been + * brought out to an external connector: + * + * -----+---+---+----+------+---------------- + * PWM PIN PER PIO I/O CONFLICTS + * -----+---+---+----+------+---------------- + * PWM0 FI B PC28 J2.30 SPI1, ISI + * H B PB0 --- GMAC + * B PA20 J1.14 LCDC, ISI + * L B PB1 --- GMAC + * B PA21 J1.16 LCDC, ISI + * -----+---+---+----+------+---------------- + * PWM1 FI B PC31 J2.36 HDMI + * H B PB4 --- GMAC + * B PA22 J1.18 LCDC, ISI + * L B PB5 --- GMAC + * B PE31 J3.20 ISI, HDMI + * B PA23 J1.20 LCDC, ISI + * -----+---+---+----+------+---------------- + * PWM2 FI B PC29 J2.29 UART0, ISI, HDMI + * H C PD5 --- HSMCI0 + * B PB8 --- GMAC + * L C PD6 --- HSMCI0 + * B PB9 --- GMAC + * -----+---+---+----+------+---------------- + * PWM3 FI C PD16 --- SPI0, Audio + * H C PD7 --- HSMCI0 + * B PB12 J3.7 GMAC + * L C PD8 --- HSMCI0 + * B PB13 --- GMAC + * -----+---+---+----+------+---------------- + */ + +/* PWM channel 0: + * + * PA20 and PA21 can be used if the LCDC or ISI are not selected. These outputs are + * available on J1, pins 14 and 16, respectively. + * + * If the GMAC is not selected, then PB0 and PB1 could also be used. However, + * these pins are not available at the I/O expansion connectors. + */ + +#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI) +# define PIO_PWM0_H PIO_PWM0_H_2 +# define PIO_PWM0_L PIO_PWM0_L_2 +#elif !defined(CONFIG_SAMA5_GMAC) +# define PIO_PWM0_H PIO_PWM0_H_1 +# define PIO_PWM0_L PIO_PWM0_L_1 +#endif + +/* PWM channel 1: + * + * PA22 and PA23 can be used if the LCDC or ISI are not selected. These outputs are + * available on J1, pins 18 and 20, respectively. + * + * PE31 can be used if the ISI is not selected (and the HDMI is not being used). + * That signal is available at J3 pin 20. + * + * If the GMAC is not selected, then PB4 and PB5 could also be used. However, + * these pins are not available at the I/O expansion connectors. + */ + +#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI) +# define PIO_PWM1_H PIO_PWM1_H_2 +#elif !defined(CONFIG_SAMA5_GMAC) +# define PIO_PWM1_H PIO_PWM1_H_1 +#endif + +#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI) +# define PIO_PWM1_L PIO_PWM1_L_3 +#elif !defined(CONFIG_SAMA5_ISI) +# define PIO_PWM1_L PIO_PWM1_L_2 +#elif !defined(CONFIG_SAMA5_GMAC) +# define PIO_PWM1_L PIO_PWM1_L_1 +#endif + +/* PWM channel 2: + * + * None of the output pin options are available at any of the I/O expansion + * connectors for PWM channel 2 + */ + +#if !defined(CONFIG_SAMA5_HSMCI0) +# define PIO_PWM2_H PIO_PWM2_H_1 +# define PIO_PWM2_L PIO_PWM2_L_1 +#elif !defined(CONFIG_SAMA5_GMAC) +# define PIO_PWM2_H PIO_PWM2_H_2 +# define PIO_PWM2_L PIO_PWM2_L_2 +#endif + +/* PWM channel 3: + * + * If the GMAC is not selected, then PB12 can used and is available at J3 pin 7. + * None of the other output pins are accessible at the I/O expansion connectors. + */ + +#if !defined(CONFIG_SAMA5_GMAC) +# define PIO_PWM3_H PIO_PWM3_H_2 +# define PIO_PWM3_L PIO_PWM3_L_2 +#elif !defined(CONFIG_SAMA5_HSMCI0) +# define PIO_PWM3_H PIO_PWM3_H_1 +# define PIO_PWM3_L PIO_PWM3_L_1 +#endif + +/************************************************************************************ + * Assembly Language Macros + ************************************************************************************/ + +#ifdef __ASSEMBLY__ + .macro config_sdram + .endm +#endif /* __ASSEMBLY__ */ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAMA5 architectures must provide the following entry point. This entry point + * is called early in the initialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void); + +/************************************************************************************ + * Name: sam_phyirq + * + * Description: + * This function may be called to register an interrupt handler that will be + * called when an interrupt is received from a PHY. + * + ************************************************************************************/ + +#if defined(CONFIG_NET) && (defined(CONFIG_SAMA5_EMAC) || defined(CONFIG_SAMA5_GMAC)) && \ + defined(CONFIG_SAMA5_PIOE_IRQ) +xcpt_t sam_phyirq(int intf, xcpt_t irqhandler); +#endif + +/************************************************************************************ + * Name: sam_ledinit, sam_setled, and sam_setleds + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If + * CONFIG_ARCH_LEDS is not defined, then the following interfaces are available to + * control the LEDs from user applications. + * + ************************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void sam_ledinit(void); +void sam_setled(int led, bool ledon); +void sam_setleds(uint8_t ledset); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_H */ diff --git a/nuttx/configs/sama5d3-xplained/include/board_384mhz.h b/nuttx/configs/sama5d3-xplained/include/board_384mhz.h new file mode 100644 index 000000000..d2fea9be7 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/include/board_384mhz.h @@ -0,0 +1,230 @@ +/************************************************************************************ + * configs/sama5d3-xplained/include/board_384mhz.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_384MHZ_H +#define __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_384MHZ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. These + * definitions will configure operational clocking. + * + * This is an alternative slower configuration that will produce a 48MHz USB clock + * with the required accuracy. When used with OHCI, an additional requirement is + * the PLLACK be a multiple of 48MHz. This setup results in a CPU clock of 384MHz. + * + * MAINOSC: Frequency = 12MHz (crystal) + * PLLA: PLL Divider = 1, Multiplier = 64 to generate PLLACK = 768MHz + * Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate + * MCK = 128MHz + * CPU clock = 384MHz + */ + +/* Main oscillator register settings. + * + * The start up time should be should be: + * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles. + */ + +#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration. + * + * Divider = 1 + * Multipler = 64 + */ + +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_CKGR_PLLAR_OUT (0) +#define BOARD_CKGR_PLLAR_MUL (63 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS + +/* PMC master clock register settings. + * + * Master/Processor Clock Source Selection = PLLA + * Master/Processor Clock Prescaler = 1 + * PLLA Divider = 2 + * Master Clock Division (MDIV) = 3 + * + * NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3. + * + * Prescaler input = 768MHz / 2 = 384MHz + * Prescaler output = 384MHz / 1 = 384MHz + * Processor Clock (PCK) = 384MHz + * Master clock (MCK) = 396MHz / 3 = 128MHz + */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 +#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2 +#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3 + +#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \ + defined(CONFIG_SAMA5_UDPHS) + +/* For OHCI Full-speed operations, the user has to perform the following: + * + * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER + * register. + * 2) Select PLLACK as Input clock of OHCI part, USBS bit in PMC_USB + * register. + * 3) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in + * PMC_USB register. USBDIV value is calculated regarding the PLLACK + * value and USB Full-speed accuracy. + * 4) Enable the OHCI clocks, UHP bit in PMC_SCER register. + * + * "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI + * full-speed operations. These clocks must be generated by a PLL with a + * correct accuracy of ± 0.25% thanks to USBDIV field. + * + * "Thus the USB Host peripheral receives three clocks from the Power + * Management Controller (PMC): the Peripheral Clock (MCK domain), the + * UHP48M and the UHP12M (built-in UHP48M divided by four) used by the + * OHCI to interface with the bus USB signals (Recovered 12 MHz domain) + * in Full-speed operations" + * + * USB Clock = PLLACK / (USBDIV + 1) = 48MHz + * USBDIV = PLLACK / 48MHz - 1 + * = 15 + * + * The maximum value of USBDIV is 15 corresponding to a divisor of 16. + * REVISIT: However, using the divisor of (15+1) yields a frame rate + * of 500 frames per second. A divisor of (7+1) gives the correct 1MS + * frame rate. I cannot explain the factor of 2 difference. + */ + +# undef BOARD_USE_UPLL /* Use PLLA as source clock */ +# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA /* Input is PLLACK */ +# if 1 /* REVISIT */ +# define BOARD_OHCI_DIVIDER (7) /* Divided by 8 */ +# else +# define BOARD_OHCI_DIVIDER (15) /* Divided by 16 */ +# endif +#endif + +/* ADC Configuration + * + * ADCClock = MCK / ((PRESCAL+1) * 2) + * + * Given: + * MCK = 128MHz + * ADCClock = 8MHz + * Then: + * PRESCAL = 7 + */ + +#define BOARD_ADC_PRESCAL (7) +#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */ +#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */ +#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */ + +/* Resulting frequencies */ + +#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ +#define BOARD_PLLA_FREQUENCY (768000000) /* PLLACK: 64 * 12Mhz / 1 */ +#define BOARD_PCK_FREQUENCY (384000000) /* CPU: PLLACK / 2 / 1 */ +#define BOARD_MCK_FREQUENCY (128000000) /* MCK: PLLACK / 2 / 1 / 3 */ +#define BOARD_ADCCLK_FREQUENCY (8000000) /* ADCCLK: MCK / ((7+1)*2) */ + +/* HSMCI clocking + * + * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV) + CLOCKODD + 2). + * + * MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2) + * + * Where CLKDIV has a range of 0-255. + */ + +/* MCK = 128MHz, CLKDIV = 159, MCI_SPEED = 128MHz / (2*159 + 0 + 2) = 400 KHz */ + +#define HSMCI_INIT_CLKDIV (159 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 128MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 128MHz /(2*2 + 1 + 2) = 18.3 MHz */ + +#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD) + +/* MCK = 128MHz, CLKDIV = 2, MCI_SPEED = 128MHz /(2*2 + 0 + 2) = 21.3 MHz */ + +#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/* FLASH wait states + * + * FWS Max frequency + * 1.62V 1.8V + * --- ----- ------ + * 0 24MHz 27MHz + * 1 40MHz 47MHz + * 2 72MHz 84MHz + * 3 84MHz 96MHz + */ + +#define BOARD_FWS 3 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_384MHZ_H */ diff --git a/nuttx/configs/sama5d3-xplained/include/board_396mhz.h b/nuttx/configs/sama5d3-xplained/include/board_396mhz.h new file mode 100644 index 000000000..9882ff1fb --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/include/board_396mhz.h @@ -0,0 +1,221 @@ +/************************************************************************************ + * configs/sama5d3-xplained/include/board_396mhz.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_396MHZ_H +#define __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_396MHZ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. These + * definitions will configure operational clocking. + * + * This is the configuration provided in the Atmel example code. This results in a + * CPU clock of 396MHz: + * + * MAINOSC: Frequency = 12MHz (crystal) + * PLLA: PLL Divider = 1, Multiplier = 66 to generate PLLACK = 792MHz + * Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate + * MCK = 132MHz + * CPU clock = 396MHz + */ + +/* Main oscillator register settings. + * + * The start up time should be should be: + * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles. + */ + +#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration. + * + * Divider = 1 + * Multipler = 66 + */ + +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_CKGR_PLLAR_OUT (0) +#define BOARD_CKGR_PLLAR_MUL (65 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS + +/* PMC master clock register settings. + * + * Master/Processor Clock Source Selection = PLLA + * Master/Processor Clock Prescaler = 1 + * PLLA Divider = 2 + * Master Clock Division (MDIV) = 3 + * + * NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3. + * + * Prescaler input = 792MHz / 2 = 396MHz + * Prescaler output = 396MHz / 1 = 396MHz + * Processor Clock (PCK) = 396MHz + * Master clock (MCK) = 396MHz / 3 = 132MHz + */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 +#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2 +#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3 + +/* ADC Configuration + * + * ADCClock = MCK / ((PRESCAL+1) * 2) + * + * Given: + * MCK = 132MHz + * ADCClock = 8MHz + * Then: + * PRESCAL = 7.25 + * + * PRESCAL=7 and MCK=132MHz yields ADC clock of 8.25MHz + */ + +#define BOARD_ADC_PRESCAL (7) +#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */ +#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */ +#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */ + +/* Resulting frequencies */ + +#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ +#define BOARD_PLLA_FREQUENCY (792000000) /* PLLACK: 66 * 12Mhz / 1 */ +#define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */ +#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */ +#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */ + +#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \ + defined(CONFIG_SAMA5_UDPHS) + +/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded + * High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL + * (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either + * the 12MHz internal RC oscillator on a an external 12MHz crystal. The + * Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier. + * + * For High-speed operations, the user has to perform the following: + * + * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in + * PMC_PCER register. + * 2) Write CKGR_PLLCOUNT field in PMC_UCKR register. + * 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register. + * 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register + * 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register. + * 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB + * register. + * 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in + * PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is + * selected. + * 8) Enable OHCI clocks, UHP bit in PMC_SCER register. + * + * Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI + * driver is initialized. + */ + +# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ +# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ +# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ +#endif + +/* HSMCI clocking + * + * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV) + CLOCKODD + 2). + * + * MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2) + * + * Where CLKDIV has a range of 0-255. + */ + +/* MCK = 132MHz, CLKDIV = 164, MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz */ + +#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz */ + +#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD) + +/* MCK = 132MHz, CLKDIV = 2, MCI_SPEED = 132MHz /(2*2 + 0 + 2) = 22 MHz */ + +#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/* FLASH wait states + * + * FWS Max frequency + * 1.62V 1.8V + * --- ----- ------ + * 0 24MHz 27MHz + * 1 40MHz 47MHz + * 2 72MHz 84MHz + * 3 84MHz 96MHz + */ + +#define BOARD_FWS 3 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_396MHZ_H */ diff --git a/nuttx/configs/sama5d3-xplained/include/board_memorymap.h b/nuttx/configs/sama5d3-xplained/include/board_memorymap.h new file mode 100644 index 000000000..bb39b72df --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/include/board_memorymap.h @@ -0,0 +1,73 @@ +/************************************************************************************ + * configs/sama5d3-xplained/include/board_memorymap.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_MEMORYMAP_H +#define __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/nuttx/configs/sama5d3-xplained/norboot/Make.defs b/nuttx/configs/sama5d3-xplained/norboot/Make.defs new file mode 100644 index 000000000..c9e67ca9f --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/norboot/Make.defs @@ -0,0 +1,146 @@ +############################################################################ +# configs/sama5d3-xplained/norboot/Make.defs +# +# Copyright (C) 2014-2014 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}$(DELIM)arch$(DELIM)arm$(DELIM)src$(DELIM)armv7-a$(DELIM)Toolchain.defs + +ifeq ($(CONFIG_SAMA5_BOOT_ISRAM),y) + LDSCRIPT = isram.ld +endif + +ifeq ($(CONFIG_SAMA5_BOOT_SDRAM),y) + LDSCRIPT = ddram.ld +endif + +ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y) +ifeq ($(CONFIG_BOOT_SDRAM_DATA),y) + LDSCRIPT = nor-ddram.ld +else + LDSCRIPT = nor-isram.ld +endif +endif + +ifeq ($(CONFIG_SAMA5_BOOT_CS1FLASH),y) +# LDSCRIPT = cs1flash.ld +endif + +ifeq ($(CONFIG_SAMA5_BOOT_CS2FLASH),y) +# LDSCRIPT = cs2flash.ld +endif + +ifeq ($(CONFIG_SAMA5_BOOT_CS3FLASH),y) +# LDSCRIPT = cs3flash.ld +endif + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include$(DELIM)cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + ARCHINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include -isystem $(TOPDIR)$(DELIM)include$(DELIM)cxx + ARCHSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCPUFLAGS = -mcpu=cortex-a5 -mfpu=vfpv4-d16 +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = +ifeq ($(CONFIG_HOST_WINDOWS),y) + HOSTEXEEXT = .exe +else + HOSTEXEEXT = +endif + +ifeq ($(WINTOOL),y) + # Windows-native host tools + DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh + DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mknulldeps.sh +else + # Linux/Cygwin-native host tools + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkdeps$(HOSTEXEEXT) +endif + diff --git a/nuttx/configs/sama5d3-xplained/norboot/defconfig b/nuttx/configs/sama5d3-xplained/norboot/defconfig new file mode 100644 index 000000000..c935b4873 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/norboot/defconfig @@ -0,0 +1,736 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +CONFIG_ARCH_CHIP_SAMA5=y +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM4 is not set +CONFIG_ARCH_CORTEXA5=y +# CONFIG_ARCH_CORTEXA8 is not set +CONFIG_ARCH_FAMILY="armv7-a" +CONFIG_ARCH_CHIP="sama5" +CONFIG_ARCH_HAVE_FPU=y +CONFIG_ARCH_FPU=y +# CONFIG_ARCH_HAVE_MPU is not set +CONFIG_ARCH_HAVE_LOWVECTORS=y +CONFIG_ARCH_LOWVECTORS=y +# CONFIG_ARCH_ROMPGTABLE is not set + +# +# ARMv7-A Configuration Options +# +# CONFIG_ARMV7A_TOOLCHAIN_BUILDROOT is not set +CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y +# CONFIG_ARMV7A_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIL is not set +# CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW is not set +# CONFIG_ARMV7A_TOOLCHAIN_GNU_OABI is not set + +# +# SAMA5 Configuration Options +# +CONFIG_SAMA5_HAVE_UART0=y +CONFIG_SAMA5_HAVE_UART1=y +CONFIG_SAMA5_HAVE_CAN0=y +CONFIG_SAMA5_HAVE_CAN1=y +CONFIG_SAMA5_HAVE_LCDC=y +CONFIG_SAMA5_HAVE_GMAC=y +CONFIG_SAMA5_HAVE_EMAC=y +CONFIG_SAMA5_HAVE_HSMCI2=y +CONFIG_SAMA5_HAVE_TC1=y +# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set +# CONFIG_ARCH_CHIP_ATSAMA5D33 is not set +# CONFIG_ARCH_CHIP_ATSAMA5D34 is not set +# CONFIG_ARCH_CHIP_ATSAMA5D35 is not set +CONFIG_ARCH_CHIP_ATSAMA5D36=y + +# +# SAMA5 Peripheral Support +# +# CONFIG_SAMA5_DBGU is not set +# CONFIG_SAMA5_PIT is not set +# CONFIG_SAMA5_WDT is not set +# CONFIG_SAMA5_RTC is not set +CONFIG_SAMA5_HSMC=y +# CONFIG_SAMA5_SMD is not set +# CONFIG_SAMA5_UART0 is not set +# CONFIG_SAMA5_UART1 is not set +# CONFIG_SAMA5_USART0 is not set +CONFIG_SAMA5_USART1=y +# CONFIG_SAMA5_USART2 is not set +# CONFIG_SAMA5_USART3 is not set +# CONFIG_SAMA5_TWI0 is not set +# CONFIG_SAMA5_TWI1 is not set +# CONFIG_SAMA5_TWI2 is not set +# CONFIG_SAMA5_HSMCI0 is not set +# CONFIG_SAMA5_HSMCI1 is not set +# CONFIG_SAMA5_HSMCI2 is not set +# CONFIG_SAMA5_SPI0 is not set +# CONFIG_SAMA5_SPI1 is not set +# CONFIG_SAMA5_TC0 is not set +# CONFIG_SAMA5_TC1 is not set +# CONFIG_SAMA5_PWM is not set +# CONFIG_SAMA5_ADC is not set +# CONFIG_SAMA5_DMAC0 is not set +# CONFIG_SAMA5_DMAC1 is not set +# CONFIG_SAMA5_UHPHS is not set +# CONFIG_SAMA5_UDPHS is not set +# CONFIG_SAMA5_GMAC is not set +# CONFIG_SAMA5_EMAC is not set +# CONFIG_SAMA5_LCDC is not set +# CONFIG_SAMA5_ISI is not set +# CONFIG_SAMA5_CAN0 is not set +# CONFIG_SAMA5_CAN1 is not set +# CONFIG_SAMA5_SHA is not set +# CONFIG_SAMA5_AES is not set +# CONFIG_SAMA5_TDES is not set +# CONFIG_SAMA5_TRNG is not set +# CONFIG_SAMA5_ARM is not set +# CONFIG_SAMA5_FUSE is not set +# CONFIG_SAMA5_MPDDRC is not set +# CONFIG_SAMA5_PIO_IRQ is not set + +# +# External Memory Configuration +# +CONFIG_SAMA5_EBICS0=y +CONFIG_SAMA5_EBICS0_SIZE=134217728 +# CONFIG_SAMA5_EBICS0_SRAM is not set +# CONFIG_SAMA5_EBICS0_PSRAM is not set +# CONFIG_SAMA5_EBICS0_PROM is not set +# CONFIG_SAMA5_EBICS0_EEPROM is not set +# CONFIG_SAMA5_EBICS0_EPROM is not set +# CONFIG_SAMA5_EBICS0_LCD is not set +CONFIG_SAMA5_EBICS0_NOR=y +# CONFIG_SAMA5_EBICS1 is not set +# CONFIG_SAMA5_EBICS2 is not set +# CONFIG_SAMA5_EBICS3 is not set +# CONFIG_SAMA5_HAVE_NAND is not set +# CONFIG_SAMA5_HAVE_PMECC is not set +CONFIG_SAMA5_BOOT_ISRAM=y +# CONFIG_SAMA5_BOOT_CS0FLASH is not set + +# +# Heap Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_HAVE_MMU=y +CONFIG_ARCH_NAND_HWECC=y +# CONFIG_PAGING is not set +CONFIG_ARCH_IRQPRIO=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=49341 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +# CONFIG_BOOT_RUNFROMFLASH is not set +CONFIG_BOOT_RUNFROMISRAM=y +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x00300000 +CONFIG_RAM_VSTART=0x00300000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_SAMA5D3_XPLAINED=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sama5d3-xplained" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +CONFIG_SAMA5D3XPLAINED_NOR_MAIN=y +# CONFIG_SAMA5D3XPLAINED_NOR_START is not set + +# +# RTOS Features +# +# CONFIG_BOARD_INITIALIZE is not set +CONFIG_MSEC_PER_TICK=10 +# CONFIG_SYSTEM_TIME64 is not set +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2014 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=29 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nor_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_ENVIRON=y + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_ARCH_HAVE_UART is not set +# CONFIG_ARCH_HAVE_UART0 is not set +# CONFIG_ARCH_HAVE_UART1 is not set +# CONFIG_ARCH_HAVE_UART2 is not set +# CONFIG_ARCH_HAVE_UART3 is not set +# CONFIG_ARCH_HAVE_UART4 is not set +# CONFIG_ARCH_HAVE_UART5 is not set +# CONFIG_ARCH_HAVE_UART6 is not set +# CONFIG_ARCH_HAVE_UART7 is not set +# CONFIG_ARCH_HAVE_UART8 is not set +# CONFIG_ARCH_HAVE_SCI0 is not set +# CONFIG_ARCH_HAVE_SCI1 is not set +# CONFIG_ARCH_HAVE_USART0 is not set +CONFIG_ARCH_HAVE_USART1=y +# CONFIG_ARCH_HAVE_USART2 is not set +# CONFIG_ARCH_HAVE_USART3 is not set +# CONFIG_ARCH_HAVE_USART4 is not set +# CONFIG_ARCH_HAVE_USART5 is not set +# CONFIG_ARCH_HAVE_USART6 is not set +# CONFIG_ARCH_HAVE_USART7 is not set +# CONFIG_ARCH_HAVE_USART8 is not set + +# +# USART Configuration +# +CONFIG_USART1_ISUART=y +CONFIG_MCU_SERIAL=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +CONFIG_DISABLE_MOUNTPOINT=y +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_PROCFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG_ENABLE is not set +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_MULTIHEAP is not set +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Library Support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +CONFIG_EXAMPLES_HELLO=y +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# EMACS-like Command Line Editor +# +# CONFIG_SYSTEM_CLE is not set + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# FLASH Erase-all Command +# + +# +# I2C tool +# + +# +# INI File Parser +# +# CONFIG_SYSTEM_INIFILE is not set + +# +# NxPlayer media player library / command Line +# +# CONFIG_SYSTEM_NXPLAYER is not set + +# +# RAM test +# +# CONFIG_SYSTEM_RAMTEST is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set + +# +# VI Work-Alike Editor +# +# CONFIG_SYSTEM_VI is not set + +# +# Stack Monitor +# + +# +# USB CDC/ACM Device Commands +# + +# +# USB Composite Device Commands +# + +# +# USB Mass Storage Device Commands +# + +# +# USB Monitor +# + +# +# Zmodem Commands +# +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/nuttx/configs/sama5d3-xplained/norboot/setenv.sh b/nuttx/configs/sama5d3-xplained/norboot/setenv.sh new file mode 100755 index 000000000..51f65864f --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/norboot/setenv.sh @@ -0,0 +1,76 @@ +#!/bin/bash +# configs/sama5d3-xplained/norboot/setenv.sh +# +# Copyright (C) 2014 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/sama5d3-xplained/nsh/Make.defs b/nuttx/configs/sama5d3-xplained/nsh/Make.defs new file mode 100644 index 000000000..59f0fd0b6 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/nsh/Make.defs @@ -0,0 +1,146 @@ +############################################################################ +# configs/sama5d3-xplained/nsh/Make.defs +# +# Copyright (C) 2014-2014 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}$(DELIM)arch$(DELIM)arm$(DELIM)src$(DELIM)armv7-a$(DELIM)Toolchain.defs + +ifeq ($(CONFIG_SAMA5_BOOT_ISRAM),y) + LDSCRIPT = isram.ld +endif + +ifeq ($(CONFIG_SAMA5_BOOT_SDRAM),y) + LDSCRIPT = ddram.ld +endif + +ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y) +ifeq ($(CONFIG_BOOT_SDRAM_DATA),y) + LDSCRIPT = nor-ddram.ld +else + LDSCRIPT = nor-isram.ld +endif +endif + +ifeq ($(CONFIG_SAMA5_BOOT_CS1FLASH),y) +# LDSCRIPT = cs1flash.ld +endif + +ifeq ($(CONFIG_SAMA5_BOOT_CS2FLASH),y) +# LDSCRIPT = cs2flash.ld +endif + +ifeq ($(CONFIG_SAMA5_BOOT_CS3FLASH),y) +# LDSCRIPT = cs3flash.ld +endif + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include$(DELIM)cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + ARCHINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include -isystem $(TOPDIR)$(DELIM)include$(DELIM)cxx + ARCHSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCPUFLAGS = -mcpu=cortex-a5 -mfpu=vfpv4-d16 +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = +ifeq ($(CONFIG_HOST_WINDOWS),y) + HOSTEXEEXT = .exe +else + HOSTEXEEXT = +endif + +ifeq ($(WINTOOL),y) + # Windows-native host tools + DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh + DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mknulldeps.sh +else + # Linux/Cygwin-native host tools + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkdeps$(HOSTEXEEXT) +endif + diff --git a/nuttx/configs/sama5d3-xplained/nsh/defconfig b/nuttx/configs/sama5d3-xplained/nsh/defconfig new file mode 100644 index 000000000..71f1f3d89 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/nsh/defconfig @@ -0,0 +1,834 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +CONFIG_ARCH_CHIP_SAMA5=y +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM4 is not set +CONFIG_ARCH_CORTEXA5=y +# CONFIG_ARCH_CORTEXA8 is not set +CONFIG_ARCH_FAMILY="armv7-a" +CONFIG_ARCH_CHIP="sama5" +CONFIG_ARCH_HAVE_FPU=y +CONFIG_ARCH_FPU=y +# CONFIG_ARCH_HAVE_MPU is not set +CONFIG_ARCH_HAVE_LOWVECTORS=y +CONFIG_ARCH_LOWVECTORS=y +# CONFIG_ARCH_ROMPGTABLE is not set + +# +# ARMv7-A Configuration Options +# +# CONFIG_ARMV7A_TOOLCHAIN_BUILDROOT is not set +CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y +# CONFIG_ARMV7A_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIL is not set +# CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW is not set +# CONFIG_ARMV7A_TOOLCHAIN_GNU_OABI is not set + +# +# SAMA5 Configuration Options +# +CONFIG_SAMA5_HAVE_UART0=y +CONFIG_SAMA5_HAVE_UART1=y +CONFIG_SAMA5_HAVE_CAN0=y +CONFIG_SAMA5_HAVE_CAN1=y +CONFIG_SAMA5_HAVE_LCDC=y +CONFIG_SAMA5_HAVE_GMAC=y +CONFIG_SAMA5_HAVE_EMAC=y +CONFIG_SAMA5_HAVE_HSMCI2=y +CONFIG_SAMA5_HAVE_TC1=y +# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set +# CONFIG_ARCH_CHIP_ATSAMA5D33 is not set +# CONFIG_ARCH_CHIP_ATSAMA5D34 is not set +# CONFIG_ARCH_CHIP_ATSAMA5D35 is not set +CONFIG_ARCH_CHIP_ATSAMA5D36=y + +# +# SAMA5 Peripheral Support +# +# CONFIG_SAMA5_DBGU is not set +# CONFIG_SAMA5_PIT is not set +# CONFIG_SAMA5_WDT is not set +# CONFIG_SAMA5_RTC is not set +CONFIG_SAMA5_HSMC=y +# CONFIG_SAMA5_SMD is not set +# CONFIG_SAMA5_UART0 is not set +# CONFIG_SAMA5_UART1 is not set +# CONFIG_SAMA5_USART0 is not set +CONFIG_SAMA5_USART1=y +# CONFIG_SAMA5_USART2 is not set +# CONFIG_SAMA5_USART3 is not set +# CONFIG_SAMA5_TWI0 is not set +# CONFIG_SAMA5_TWI1 is not set +# CONFIG_SAMA5_TWI2 is not set +# CONFIG_SAMA5_HSMCI0 is not set +# CONFIG_SAMA5_HSMCI1 is not set +# CONFIG_SAMA5_HSMCI2 is not set +# CONFIG_SAMA5_SPI0 is not set +# CONFIG_SAMA5_SPI1 is not set +# CONFIG_SAMA5_TC0 is not set +# CONFIG_SAMA5_TC1 is not set +# CONFIG_SAMA5_PWM is not set +# CONFIG_SAMA5_ADC is not set +# CONFIG_SAMA5_DMAC0 is not set +# CONFIG_SAMA5_DMAC1 is not set +# CONFIG_SAMA5_UHPHS is not set +# CONFIG_SAMA5_UDPHS is not set +# CONFIG_SAMA5_GMAC is not set +# CONFIG_SAMA5_EMAC is not set +# CONFIG_SAMA5_LCDC is not set +# CONFIG_SAMA5_ISI is not set +# CONFIG_SAMA5_CAN0 is not set +# CONFIG_SAMA5_CAN1 is not set +# CONFIG_SAMA5_SHA is not set +# CONFIG_SAMA5_AES is not set +# CONFIG_SAMA5_TDES is not set +# CONFIG_SAMA5_TRNG is not set +# CONFIG_SAMA5_ARM is not set +# CONFIG_SAMA5_FUSE is not set +# CONFIG_SAMA5_MPDDRC is not set +# CONFIG_SAMA5_PIO_IRQ is not set + +# +# External Memory Configuration +# +CONFIG_SAMA5_EBICS0=y +CONFIG_SAMA5_EBICS0_SIZE=134217728 +# CONFIG_SAMA5_EBICS0_SRAM is not set +# CONFIG_SAMA5_EBICS0_PSRAM is not set +# CONFIG_SAMA5_EBICS0_PROM is not set +# CONFIG_SAMA5_EBICS0_EEPROM is not set +# CONFIG_SAMA5_EBICS0_EPROM is not set +# CONFIG_SAMA5_EBICS0_LCD is not set +CONFIG_SAMA5_EBICS0_NOR=y +# CONFIG_SAMA5_EBICS1 is not set +# CONFIG_SAMA5_EBICS2 is not set +# CONFIG_SAMA5_EBICS3 is not set +# CONFIG_SAMA5_HAVE_NAND is not set +# CONFIG_SAMA5_HAVE_PMECC is not set +# CONFIG_SAMA5_BOOT_ISRAM is not set +CONFIG_SAMA5_BOOT_CS0FLASH=y + +# +# Heap Configuration +# +CONFIG_SAMA5_ISRAM_HEAP=y + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_HAVE_MMU=y +CONFIG_ARCH_NAND_HWECC=y +# CONFIG_PAGING is not set +CONFIG_ARCH_IRQPRIO=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=49341 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x00304000 +CONFIG_RAM_VSTART=0x00304000 +CONFIG_RAM_SIZE=114688 +CONFIG_FLASH_START=0x10000000 +CONFIG_FLASH_VSTART=0x10000000 +CONFIG_FLASH_SIZE=134217728 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_SAMA5D3_XPLAINED=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sama5d3-xplained" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +# CONFIG_BOARD_INITIALIZE is not set +CONFIG_MSEC_PER_TICK=10 +# CONFIG_SYSTEM_TIME64 is not set +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=32 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2014 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=31 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_ENVIRON=y + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_ARCH_HAVE_UART is not set +# CONFIG_ARCH_HAVE_UART0 is not set +# CONFIG_ARCH_HAVE_UART1 is not set +# CONFIG_ARCH_HAVE_UART2 is not set +# CONFIG_ARCH_HAVE_UART3 is not set +# CONFIG_ARCH_HAVE_UART4 is not set +# CONFIG_ARCH_HAVE_UART5 is not set +# CONFIG_ARCH_HAVE_UART6 is not set +# CONFIG_ARCH_HAVE_UART7 is not set +# CONFIG_ARCH_HAVE_UART8 is not set +# CONFIG_ARCH_HAVE_SCI0 is not set +# CONFIG_ARCH_HAVE_SCI1 is not set +# CONFIG_ARCH_HAVE_USART0 is not set +CONFIG_ARCH_HAVE_USART1=y +# CONFIG_ARCH_HAVE_USART2 is not set +# CONFIG_ARCH_HAVE_USART3 is not set +# CONFIG_ARCH_HAVE_USART4 is not set +# CONFIG_ARCH_HAVE_USART5 is not set +# CONFIG_ARCH_HAVE_USART6 is not set +# CONFIG_ARCH_HAVE_USART7 is not set +# CONFIG_ARCH_HAVE_USART8 is not set + +# +# USART Configuration +# +CONFIG_USART1_ISUART=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG_ENABLE is not set +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_MULTIHEAP is not set +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Library Support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=80 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_CONSOLE=y + +# +# USB Trace Support +# +# CONFIG_NSH_CONDEV is not set +# CONFIG_NSH_ARCHINIT is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# EMACS-like Command Line Editor +# +# CONFIG_SYSTEM_CLE is not set + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# FLASH Erase-all Command +# + +# +# I2C tool +# + +# +# INI File Parser +# +# CONFIG_SYSTEM_INIFILE is not set + +# +# NxPlayer media player library / command Line +# +# CONFIG_SYSTEM_NXPLAYER is not set + +# +# RAM test +# +# CONFIG_SYSTEM_RAMTEST is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set + +# +# VI Work-Alike Editor +# +# CONFIG_SYSTEM_VI is not set + +# +# Stack Monitor +# + +# +# USB CDC/ACM Device Commands +# + +# +# USB Composite Device Commands +# + +# +# USB Mass Storage Device Commands +# + +# +# USB Monitor +# + +# +# Zmodem Commands +# +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/nuttx/configs/sama5d3-xplained/nsh/setenv.sh b/nuttx/configs/sama5d3-xplained/nsh/setenv.sh new file mode 100755 index 000000000..c66a4e249 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/nsh/setenv.sh @@ -0,0 +1,76 @@ +#!/bin/bash +# configs/sama5d3-xplained/nsh/setenv.sh +# +# Copyright (C) 2014 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/sama5d3-xplained/scripts/ddram.ld b/nuttx/configs/sama5d3-xplained/scripts/ddram.ld new file mode 100644 index 000000000..96e343239 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/scripts/ddram.ld @@ -0,0 +1,123 @@ +/**************************************************************************** + * configs/sama5d3-xplained/scripts/ddram.ld + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The SAMA5D3 has 128 KB of ISRAM beginning at virtual address 0x0030:0000. + * This memory configuration, however, loads into the 64 MB SDRAM on board + * the SAMA5D3-Xplained which lies at 0x2000:0000 + * + * Vectors in low memory are assumed and 16KB of ISRAM is reserved at the + * high end of ISRAM for the page table. + */ + +MEMORY +{ + isram (W!RX) : ORIGIN = 0x300000, LENGTH = 128K - 16K + sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 64M +} + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + _etext = ABSOLUTE(.); + } > sdram + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > sdram + + .ARM.extab : { + *(.ARM.extab*) + } > sdram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > sdram + PROVIDE_HIDDEN (__exidx_end = .); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sdram + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sdram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/sama5d3-xplained/scripts/isram.ld b/nuttx/configs/sama5d3-xplained/scripts/isram.ld new file mode 100644 index 000000000..473cd6b21 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/scripts/isram.ld @@ -0,0 +1,120 @@ +/**************************************************************************** + * configs/sama5d3-xplained/scripts/isram.ld + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The SAMA5D3 has 128 KB of ISRAM beginning at virtual address 0x0030:0000. + * + * Vectors in low memory are assumed and 16KB of ISRAM is reserved at the + * high end of ISRAM for the page table. + */ + +MEMORY +{ + isram (W!RX) : ORIGIN = 0x300000, LENGTH = 128K - 16K +} + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + _etext = ABSOLUTE(.); + } > isram + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > isram + + .ARM.extab : { + *(.ARM.extab*) + } > isram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > isram + PROVIDE_HIDDEN (__exidx_end = .); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > isram + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > isram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/sama5d3-xplained/scripts/nor-ddram.ld b/nuttx/configs/sama5d3-xplained/scripts/nor-ddram.ld new file mode 100644 index 000000000..f74d7bcf5 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/scripts/nor-ddram.ld @@ -0,0 +1,131 @@ +/**************************************************************************** + * configs/sama5d3-xplained/scripts/nor-ddram.ld + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The SAMA5D3-Xplained has 128MB of NOR flash at CS0 (0x1000:0000). In this + * configuration, the .text and a copy of the .data section will be loaded + * into NOR flash. NuttX .data, .bss, the IDLE stack, and the primary + * heap will be allocated in SRAM. The SAMA5D3 has 128 KB of ISRAM beginning + * at virtual address 0x0030:0000. + * + * The SAMA5D3 has 128 KB of ISRAM beginning at virtual address 0x0030:0000 + * And 256Mb of SDRAm at address 0x2000:0000. This script assumes ISRAM used + * only for the page table. All variables are retained in SDRAM. + * + * Vectors in low memory are assumed to reside at the beginning of NOR flash. + */ + +MEMORY +{ + norflash (W!RX) : ORIGIN = 0x10000000, LENGTH = 128M + isram (WR) : ORIGIN = 0x00304000, LENGTH = 128K - 16K + sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 256K +} + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + _etext = ABSOLUTE(.); + } > norflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > norflash + + .ARM.extab : { + *(.ARM.extab*) + } > norflash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > norflash + PROVIDE_HIDDEN (__exidx_end = .); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sdram AT > norflash + + _eronly = LOADADDR(.data); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sdram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/sama5d3-xplained/scripts/nor-isram.ld b/nuttx/configs/sama5d3-xplained/scripts/nor-isram.ld new file mode 100644 index 000000000..486624b04 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/scripts/nor-isram.ld @@ -0,0 +1,127 @@ +/**************************************************************************** + * configs/sama5d3-xplained/scripts/nor-isram.ld + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The SAMA5D3-Xplained has 128MB of NOR flash at CS0 (0x1000:0000). In this + * configuration, the .text and a copy of the .data section will be loaded + * into NOR flash. NuttX .data, .bss, the IDLE stack, and the primary + * heap will be allocated in SRAM. The SAMA5D3 has 128 KB of ISRAM beginning + * at virtual address 0x0030:0000. + * + * Vectors in low memory are assumed to reside at the beginning of NOR flash + * 16KB of ISRAM is reserved at the beginning of ISRAM for the page table. + */ + +MEMORY +{ + norflash (W!RX) : ORIGIN = 0x10000000, LENGTH = 128M + isram (WR) : ORIGIN = 0x00304000, LENGTH = 128K - 16K +} + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + _etext = ABSOLUTE(.); + } > norflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > norflash + + .ARM.extab : { + *(.ARM.extab*) + } > norflash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > norflash + PROVIDE_HIDDEN (__exidx_end = .); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > isram AT > norflash + + _eronly = LOADADDR(.data); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > isram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/sama5d3-xplained/scripts/pg-sram.ld b/nuttx/configs/sama5d3-xplained/scripts/pg-sram.ld new file mode 100644 index 000000000..1c961b9ca --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/scripts/pg-sram.ld @@ -0,0 +1,158 @@ +/**************************************************************************** + * configs/sama5d3-xplained/scripts/pg-isram.ld + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The SAMA5D3 has 128 KB of ISRAM beginning at virtual address 0x0030:0000. + * The .text vitual address space begins at the same location as the physical + * address space: 0x0030:0000. The virtual space is broken up into three + * regions: + * + * PHYSICAL VIRTUAL + * NAME DESCRIPTION SIZE START SIZE START + * -------- -------------------------- ----- ----------- ------- ----------- + * locked Pages locked in memory. 40KB 0x0030:0000 40KB 0x0030:0000 + * paged Pages in nonvolatile store. 48KB 0x0030:a000 48KB 0x0030:a000 + * data .data/.bss/heap. 24KB 0x0031:6000 24KB 0x0031:6000 + * Reserved for page table 16KB 0x0031:c000 16KB 0x0031:c000 + * -------- -------------------------- ----- ----------- ------- ----------- + * 128KB 0x0032 0000 128KB 0x0032 0000 + * + * These region sizes must match the size in pages specified for each region + * in the NuttX configuration file: CONFIG_PAGING_NLOCKED, CONFIG_PAGING_NVPAGED, + * and CONFIG_PAGING_NDATA. + * + * NOTE 1: The locked region is should be big here so that you can enable lots of + * debug output without overflowing the locked region. 32KB would probably be + * plenty if this were a real, optimized application. + * + * NOTE 2: Different compilers will compile the code to different sizes. If you + * get a link time error saying that the locked region is full, you may have to + * re-organize this memory layout (here and in defconfig) to make the locked + * region even bigger. + * + * NOTE 3: Vectors in low memory are assumed and 16KB of ISRAM is reserved at + * the high end of ISRAM for the page table (?). + */ + +MEMORY +{ + locked (rx) : ORIGIN = 0x00300000, LENGTH = 40K + paged (rx) : ORIGIN = 0x0030a000, LENGTH = 48K + data (rw) : ORIGIN = 0x00316000, LENGTH = 24K +} + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) +ENTRY(_stext) + +SECTIONS +{ + .locked : { + _slocked = ABSOLUTE(.); + *(.vectors) + up_head.o locked.r (.text .text.*) + up_head.o locked.r (.fixup) + up_head.o locked.r (.gnu.warning) + up_head.o locked.r (.rodata .rodata.*) + up_head.o locked.r (.gnu.linkonce.t.*) + up_head.o locked.r (.glue_7) + up_head.o locked.r (.glue_7t) + up_head.o locked.r (.got) + up_head.o locked.r (.gcc_except_table) + up_head.o locked.r (.gnu.linkonce.r.*) + _elocked = ABSOLUTE(.); + } >locked + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > locked + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > isram + PROVIDE_HIDDEN (__exidx_end = .); + + .paged : { + _spaged = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + _epaged = ABSOLUTE(.); + } > paged + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > data AT > locked + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > data + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/sama5d3-xplained/src/Makefile b/nuttx/configs/sama5d3-xplained/src/Makefile new file mode 100644 index 000000000..7872db7ac --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/Makefile @@ -0,0 +1,188 @@ +############################################################################ +# configs/sama5d3-xplained/src/Makefile +# +# Copyright (C) 2014 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +CFLAGS += -I$(TOPDIR)/sched + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = sam_boot.c + +ifeq ($(CONFIG_HAVE_CXX),y) +CSRCS += sam_cxxinitialize.c +endif + +ifeq ($(CONFIG_SAMA5_SPI0),y) +CSRCS += sam_spi.c +else +ifeq ($(CONFIG_SAMA5_SPI1),y) +CSRCS += sam_spi.c +endif +endif + +ifeq ($(CONFIG_SAMA5_DDRCS),y) +CSRCS += sam_sdram.c +endif + +ifeq ($(CONFIG_SAMA5_EBICS0_NOR),y) +CSRCS += sam_norflash.c +endif + +ifeq ($(CONFIG_SAMA5_EBICS3_NAND),y) +CSRCS += sam_nandflash.c +endif + +ifeq ($(CONFIG_SAMA5D3XPLAINED_NOR_MAIN),y) +CSRCS += nor_main.c +endif + +ifeq ($(CONFIG_MTD_AT25),y) +ifeq ($(CONFIG_SAMA5_SPI0),y) +CSRCS += sam_at25.c +endif +endif + +ifeq ($(CONFIG_SAMA5_HSMCI0),y) +CSRCS += sam_hsmci.c +else +ifeq ($(CONFIG_SAMA5_HSMCI1),y) +CSRCS += sam_hsmci.c +endif +endif + +ifeq ($(CONFIG_SAMA5_UHPHS),y) +CSRCS += sam_usb.c +else +ifeq ($(CONFIG_SAMA5_UDPHS),y) +CSRCS += sam_usb.c +endif +endif + +ifeq ($(CONFIG_SAMA5_EMAC),y) +CSRCS += sam_ethernet.c +else +ifeq ($(CONFIG_SAMA5_GMAC),y) +CSRCS += sam_ethernet.c +endif +endif + +ifeq ($(CONFIG_NSH_ARCHINIT),y) +CSRCS += sam_nsh.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += sam_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += sam_pwm.c +endif + +ifeq ($(CONFIG_CAN),y) +CSRCS += sam_can.c +endif + +ifeq ($(CONFIG_AUDIO_I2SCHAR),y) +ifeq ($(CONFIG_SAMA5_SSC0),y) +CSRCS += sam_i2schar.c +else +ifeq ($(CONFIG_SAMA5_SSC1),y) +CSRCS += sam_i2schar.c +endif +endif +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += sam_usbmsc.c +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CSRCS += sam_ostest.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += sam_autoleds.c +else +CSRCS += sam_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += sam_buttons.c +endif + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-a}" +else + CFLAGS += -I$(ARCH_SRCDIR)/chip + CFLAGS += -I$(ARCH_SRCDIR)/common + CFLAGS += -I$(ARCH_SRCDIR)/armv7-a +endif + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/nuttx/configs/sama5d3-xplained/src/nor_main.c b/nuttx/configs/sama5d3-xplained/src/nor_main.c new file mode 100644 index 000000000..2c7120475 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/nor_main.c @@ -0,0 +1,195 @@ +/***************************************************************************** + * configs/sama5d3-xplained/src/nor_main.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdio.h> +#include <debug.h> + +#include <arch/irq.h> + +#include "up_arch.h" +#include "mmu.h" +#include "cache.h" + +#include "sam_periphclks.h" +#include "chip/sam_hsmc.h" +#include "chip/sam_matrix.h" +#include "chip/sam_aximx.h" + +#include "sama5d3-xplained.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NOR_ENTRY ((nor_entry_t)SAM_EBICS0_VSECTION) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef void (*nor_entry_t)(void); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nor_main + * + * Description: + * nor_main is a tiny program that runs in ISRAM. nor_main will enable + * NOR flash then jump to the program in NOR flash + * + ****************************************************************************/ + +int nor_main(int argc, char *argv) +{ + uint32_t regval; + +#ifdef CONFIG_SAMA5D3XPLAINED_NOR_START + printf("Configuring and booting from NOR FLASH on CS0\n"); +#else + printf("Configuring NOR FLASH on CS0 and halting\n"); +#endif + + /* Make sure that the SMC peripheral is enabled (But of course it is... we + * are executing from NOR FLASH now). + */ + + sam_hsmc_enableclk(); + + /* The SAMA5D3-Xplained has 118MB of 16-bit NOR FLASH at CS0. The NOR FLASH + * has already been configured by the first level ROM bootloader... we + * simply need to modify the timing here. + */ + + regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(0) | + HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(0); + putreg32(regval, SAM_HSMC_SETUP(HSMC_CS0)); + + regval = HSMC_PULSE_NWE_PULSE(10) | HSMC_PULSE_NCS_WRPULSE(10) | + HSMC_PULSE_NRD_PULSE(11) | HSMC_PULSE_NCS_RDPULSE(11); + putreg32(regval, SAM_HSMC_PULSE(HSMC_CS0)); + + regval = HSMC_CYCLE_NWE_CYCLE(11) | HSMC_CYCLE_NRD_CYCLE(14); + putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS0)); + + regval = HSMC_TIMINGS_TCLR(0) | HSMC_TIMINGS_TADL(0) | + HSMC_TIMINGS_TAR(0) | HSMC_TIMINGS_TRR(0) | + HSMC_TIMINGS_TWB(0) | HSMC_TIMINGS_RBNSEL(0); + putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS0)); + + regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE | + HSMC_MODE_EXNWMODE_DISABLED | HSMC_MODE_BIT_16 | + HSMC_MODE_TDFCYCLES(1); + putreg32(regval, SAM_HSMC_MODE(HSMC_CS0)); + + /* Interrupts must be disabled through the following. In this configuration, + * there should only be timer interrupts. Your NuttX configuration must use + * CONFIG_SERIAL_LOWCONSOLE=y or printf() will hang when the interrupts + * are disabled! + */ + + (void)irqsave(); + + /* Disable MATRIX write protection */ + +#if 0 /* Disabled on reset */ + putreg32(MATRIX_WPMR_WPKEY, SAM_MATRIX_WPMR); +#endif + + /* Set remap state 1. + * + * Boot state: ROM is seen at address 0x00000000 + * Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave + * interface) instead of ROM. + * Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave + * interface) instead of ROM for external boot. + * + * REVISIT: This does not work. No matter what I do, the internal + * SRAM is always visible at address zero. I am missing something. + */ + + putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR); /* Enable remap */ + putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap HEBI */ + + /* Restore MATRIX write protection */ + +#if 0 /* Disabled on reset */ + putreg32(MATRIX_WPMR_WPKEY | MATRIX_WPMR_WPEN, SAM_MATRIX_WPMR); +#endif + + /* Disable the caches and the MMU. Disabling the MMU should be safe here + * because there is a 1-to-1 identity mapping between the physical and + * virtual addressing. + */ + + /* NOTE: This generates crashes and lots of error, but does leave the + * system in the proper state to run from NOR: very ugly but usable. + * Better than the alternative. + */ + + cp15_disable_mmu(); + cp15_disable_caches(); + + /* Invalidate caches and TLBs */ + + cp15_invalidate_icache(); + cp15_invalidate_dcache_all(); + cp15_invalidate_tlbs(); + +#ifdef CONFIG_SAMA5D3XPLAINED_NOR_START + /* Then jump into NOR flash */ + + NOR_ENTRY(); + +#else + /* Or just wait patiently for the user to break in with GDB. */ + + for (;;); +#endif + + return 0; /* We should not get here in either case */ +} diff --git a/nuttx/configs/sama5d3-xplained/src/sam_adc.c b/nuttx/configs/sama5d3-xplained/src/sam_adc.c new file mode 100644 index 000000000..4b1b14674 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_adc.c @@ -0,0 +1,118 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/up_adc.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <errno.h> +#include <debug.h> + +#include <nuttx/analog/adc.h> + +#include "sam_adc.h" +#include "sama5d3-xplained.h" + +#ifdef CONFIG_ADC + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: adc_devinit + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/adc. + * + ************************************************************************************/ + +int adc_devinit(void) +{ +#ifdef CONFIG_SAMA5_ADC + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = sam_adc_initialize(); + if (adc == NULL) + { + adbg("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + adbg("adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_ADC */
\ No newline at end of file diff --git a/nuttx/configs/sama5d3-xplained/src/sam_at25.c b/nuttx/configs/sama5d3-xplained/src/sam_at25.c new file mode 100644 index 000000000..8fbe23301 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_at25.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * config/sama5d3-xplained/src/sam_at25.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/mount.h> + +#include <stdbool.h> +#include <stdio.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/spi/spi.h> +#include <nuttx/mtd/mtd.h> +#include <nuttx/fs/nxffs.h> + +#include "sam_spi.h" +#include "sama5d3-xplained.h" + +#ifdef HAVE_AT25 + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_at25_automount + * + * Description: + * Initialize and configure the AT25 serial FLASH + * + ****************************************************************************/ + +int sam_at25_automount(int minor) +{ + FAR struct spi_dev_s *spi; + FAR struct mtd_dev_s *mtd; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the SPI port driver */ + + spi = up_spiinitialize(AT25_PORT); + if (!spi) + { + fdbg("ERROR: Failed to initialize SPI port %d\n", AT25_PORT); + return -ENODEV; + } + + /* Now bind the SPI interface to the AT25 SPI FLASH driver */ + + mtd = at25_initialize(spi); + if (!mtd) + { + fdbg("ERROR: Failed to bind SPI port %d to the AT25 FLASH driver\n"); + return -ENODEV; + } + +#if defined(CONFIG_SAMA5D3XPLAINED_AT25_FTL) + /* And finally, use the FTL layer to wrap the MTD driver as a block driver */ + + ret = ftl_initialize(AT25_MINOR, mtd); + if (ret < 0) + { + fdbg("ERROR: Failed to initialize the FTL layer: %d\n", ret); + return ret; + } + +#elif defined(CONFIG_SAMA5D3XPLAINED_AT25_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + fdbg("ERROR: NXFFS initialization failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/at25 */ + + ret = mount(NULL, "/mnt/at25", "nxffs", 0, NULL); + if (ret < 0) + { + fdbg("ERROR: Failed to mount the NXFFS volume: %d\n", errno); + return ret; + } +#endif + /* Now we are initializeed */ + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_AT25 */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_autoleds.c b/nuttx/configs/sama5d3-xplained/src/sam_autoleds.c new file mode 100644 index 000000000..73429e816 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_autoleds.c @@ -0,0 +1,173 @@ +/**************************************************************************** + * configs/sama5d3-xplained/src/sam_autoleds.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* There are two LEDs on the SAMA5D3 series-CM board that can be controlled + * by software. A blue LED is controlled via PIO pins. A red LED normally + * provides an indication that power is supplied to the board but can also + * be controlled via software. + * + * PE25. This blue LED is pulled high and is illuminated by pulling PE25 + * low. + * + * PE24. The red LED is also pulled high but is driven by a transistor so + * that it is illuminated when power is applied even if PE24 is not + * configured as an output. If PE24 is configured as an output, then the + * LCD is illuminated by a low output. + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows: + * + * SYMBOL Val Meaning LED state + * Blue Red + * ----------------- --- ----------------------- -------- -------- + * LED_STARTED 0 NuttX has been started OFF OFF + * LED_HEAPALLOCATE 0 Heap has been allocated OFF OFF + * LED_IRQSENABLED 0 Interrupts enabled OFF OFF + * LED_STACKCREATED 1 Idle stack created ON OFF + * LED_INIRQ 2 In an interrupt No change + * LED_SIGNAL 2 In a signal handler No change + * LED_ASSERTION 2 An assertion failed No change + * LED_PANIC 3 The system has crashed OFF Blinking + * LED_IDLE N/A MCU is is sleep mode Not used + * + * Thus if the blue LED is statically on, NuttX has successfully booted and + * is, apparently, running normmally. If the red is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <debug.h> + +#include <arch/board/board.h> + +#include "sam_pio.h" +#include "sama5d3-xplained.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG + * with CONFIG_DEBUG_VERBOSE too) + */ + +#ifdef CONFIG_DEBUG_LEDS +# define leddbg lldbg +# define ledvdbg llvdbg +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_led_initialize + ****************************************************************************/ + +void board_led_initialize(void) +{ + /* Configure LED PIOs for output */ + + sam_configpio(PIO_BLUE); + sam_configpio(PIO_RED); +} + +/**************************************************************************** + * Name: board_led_on + ****************************************************************************/ + +void board_led_on(int led) +{ + bool blueoff = true; /* Low illuminates */ + bool redon = false; /* High illuminates */ + + switch (led) + { + case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ + break; + + case 1: /* LED_STACKCREATED */ + blueoff = false; + break; + + default: + case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ + return; + + case 3: /* LED_PANIC */ + redon = true; + break; + } + + sam_piowrite(PIO_BLUE, blueoff); + sam_piowrite(PIO_RED, redon); +} + +/**************************************************************************** + * Name: board_led_off + ****************************************************************************/ + +void board_led_off(int led) +{ + if (led != 2) + { + sam_piowrite(PIO_BLUE, true); /* Low illuminates */ + sam_piowrite(PIO_RED, false); /* High illuminates */ + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_boot.c b/nuttx/configs/sama5d3-xplained/src/sam_boot.c new file mode 100644 index 000000000..fd651bf27 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_boot.c @@ -0,0 +1,150 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/sam_boot.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> + +#include "sama5d3-xplained.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAMA5 architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is enable, and 2) the weak function + * sam_spiinitialize() has been brought into the link. + */ + +#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1) + if (sam_spiinitialize) + { + sam_spiinitialize(); + } +#endif + +#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM) + + /* Configure SDRAM if (1) SDRAM has been enalbled in the NuttX configuration and + * (2) if we are not currently running out of SDRAM. If we are now running out + * of SDRAM then we have to assume that some second level bootloader has properly + * configured SDRAM for our use. + */ + + sam_sdram_config(); + +#endif + + /* Initialize USB if the 1) the HS host or device controller is in the + * configuration and 2) the weak function sam_usbinitialize() has been brought + * into the build. Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also + * selected. + */ + +#if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS) + if (sam_usbinitialize) + { + sam_usbinitialize(); + } +#endif + + /* Configure board resources to support networkingif the 1) networking is enabled, + * 2) the EMAC or GMAC module is enabled, and 2) the weak function + * sam_netinitialize() has been brought into the build. + */ + +#ifdef HAVE_NETWORK + if (sam_netinitialize) + { + sam_netinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_led_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intiialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform NSH initialization here instead of from the NSH. This + * alternative NSH initialization is necessary when NSH is ran in user-space + * but the initialization function must run in kernel space. + */ + +#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_NSH_ARCHINIT) + (void)nsh_archinitialize(); +#endif +} +#endif /* CONFIG_BOARD_INITIALIZE */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_buttons.c b/nuttx/configs/sama5d3-xplained/src/sam_buttons.c new file mode 100644 index 000000000..15ef81938 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_buttons.c @@ -0,0 +1,172 @@ +/**************************************************************************** + * configs/sama5d3-xplained/src/sam_buttons.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* There are five push button switches on the SAMA5D3-Xplained base board: + * + * 1. One Reset, board reset (BP1) + * 2. One Wake up, push button to bring the processor out of low power mode + * (BP2) + * 3. One User momentary Push Button + * 4. One Disable CS Push Button + * + * Only the momentary push button is controllable by software (labeled + * "PB_USER1" on the board): + * + * - PE27. Pressing the switch connect PE27 to grounded. Therefore, PE27 + * must be pulled high internally. When the button is pressed the SAMA5 + * will sense "0" is on PE27. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> + +#include <nuttx/arch.h> +#include <nuttx/irq.h> + +#include <arch/irq.h> +#include <arch/board/board.h> + +#include "sam_pio.h" +#include "sama5d3-xplained.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_SAMA5_PIOE_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) +static xcpt_t g_irquser1; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_buttons() may be called to collect the current state of all + * buttons or board_button_irq() may be called to register button interrupt + * handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + (void)sam_configpio(PIO_USER1); +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be called to + * collect the state of all buttons. board_buttons() returns an 8-bit bit set + * with each bit associated with a button. See the BUTTON* definitions + * above for the meaning of each bit in the returned value. + * + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + return sam_pioread(PIO_USER1) ? 0 : BUTTON_USER1_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * This function may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is one + * of the BUTTON* definitions provided above. The previous interrupt + * handler address isreturned (so that it may restored, if so desired). + * + * Configuration Notes: + * Configuration CONFIG_SAMA5_PIO_IRQ must be selected to enable the + * overall PIO IRQ feature and CONFIG_SAMA5_PIOE_IRQ must be enabled to + * select PIOs to support interrupts on PIOE. + * + ****************************************************************************/ + +#if defined(CONFIG_SAMA5_PIOE_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) +xcpt_t board_button_irq(int id, xcpt_t irqhandler) +{ + xcpt_t oldhandler = NULL; + + if (id == BUTTON_USER1) + { + irqstate_t flags; + + /* Disable interrupts until we are done. This guarantees that the + * following operations are atomic. + */ + + flags = irqsave(); + + /* Get the old button interrupt handler and save the new one */ + + oldhandler = g_irquser1; + g_irquser1 = irqhandler; + + /* Configure the interrupt */ + + sam_pioirq(IRQ_USER1); + (void)irq_attach(IRQ_USER1, irqhandler); + sam_pioirqenable(IRQ_USER1); + irqrestore(flags); + } + + /* Return the old button handler (so that it can be restored) */ + + return oldhandler; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_can.c b/nuttx/configs/sama5d3-xplained/src/sam_can.c new file mode 100644 index 000000000..24b3e2468 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_can.c @@ -0,0 +1,140 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/up_can.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <errno.h> +#include <debug.h> + +#include <nuttx/can.h> +#include <arch/board/board.h> + +#include "chip.h" +#include "up_arch.h" + +#include "sam_can.h" +#include "sama5d3-xplained.h" + +#if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1)) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#if defined(CONFIG_SAMA5_CAN0) && defined(CONFIG_SAMA5_CAN1) +# warning "Both CAN0 and CAN1 are enabled. Assuming only CAN0." +# undef CONFIG_SAMA5_CAN1 +#endif + +#ifdef CONFIG_SAMA5_CAN0 +# define CAN_PORT 0 +#else +# define CAN_PORT 1 +#endif + +/* Debug ***************************************************************************/ +/* Non-standard debug that may be enabled just for testing CAN */ + +#ifdef CONFIG_DEBUG_CAN +# define candbg dbg +# define canvdbg vdbg +# define canlldbg lldbg +# define canllvdbg llvdbg +#else +# define candbg(x...) +# define canvdbg(x...) +# define canlldbg(x...) +# define canllvdbg(x...) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: can_devinit + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/can. + * + ************************************************************************************/ + +int can_devinit(void) +{ + static bool initialized = false; + struct can_dev_s *can; + int ret; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = sam_caninitialize(CAN_PORT); + if (can == NULL) + { + candbg("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + candbg("ERROR: can_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_CAN && (CONFIG_SAMA5_CAN0 || CONFIG_SAMA5_CAN1) */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_cxxinitialize.c b/nuttx/configs/sama5d3-xplained/src/sam_cxxinitialize.c new file mode 100644 index 000000000..b7bfc3e06 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_cxxinitialize.c @@ -0,0 +1,153 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/sam_cxxinitialize.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> + +#include <nuttx/arch.h> + +#include <arch/sama5/chip.h> +#include "chip.h" + +#if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE) + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Debug ****************************************************************************/ +/* Non-standard debug that may be enabled just for testing the static constructors */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_CXX +#endif + +#ifdef CONFIG_DEBUG_CXX +# define cxxdbg dbg +# define cxxlldbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define cxxvdbg vdbg +# define cxxllvdbg llvdbg +# else +# define cxxvdbg(x...) +# define cxxllvdbg(x...) +# endif +#else +# define cxxdbg(x...) +# define cxxlldbg(x...) +# define cxxvdbg(x...) +# define cxxllvdbg(x...) +#endif + +/************************************************************************************ + * Private Types + ************************************************************************************/ +/* This type defines one entry in initialization array */ + +typedef void (*initializer_t)(void); + +/************************************************************************************ + * External references + ************************************************************************************/ +/* _sinit and _einit are symbols exported by the linker script that mark the + * beginning and the end of the C++ initialization section. + */ + +extern initializer_t _sinit; +extern initializer_t _einit; + +/* _stext and _etext are symbols exported by the linker script that mark the + * beginning and the end of text. + */ + +extern uint32_t _stext; +extern uint32_t _etext; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: up_cxxinitialize + * + * Description: + * If C++ and C++ static constructors are supported, then this function + * must be provided by board-specific logic in order to perform + * initialization of the static C++ class instances. + * + * This function should then be called in the application-specific + * user_start logic in order to perform the C++ initialization. NOTE + * that no component of the core NuttX RTOS logic is involved; This + * function defintion only provides the 'contract' between application + * specific C++ code and platform-specific toolchain support + * + ***************************************************************************/ + +void up_cxxinitialize(void) +{ + initializer_t *initp; + + cxxdbg("_sinit: %p _einit: %p _stext: %p _etext: %p\n", + &_sinit, &_einit, &_stext, &_etext); + + /* Visit each entry in the initialzation table */ + + for (initp = &_sinit; initp != &_einit; initp++) + { + initializer_t initializer = *initp; + cxxdbg("initp: %p initializer: %p\n", initp, initializer); + + /* Make sure that the address is non-NULL and lies in the text region + * defined by the linker script. Some toolchains may put NULL values + * or counts in the initialization table + */ + + if ((void*)initializer > (void*)&_stext && (void*)initializer < (void*)&_etext) + { + cxxdbg("Calling %p\n", initializer); + initializer(); + } + } +} + +#endif /* CONFIG_HAVE_CXX && CONFIG_HAVE_CXXINITIALIZE */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_ethernet.c b/nuttx/configs/sama5d3-xplained/src/sam_ethernet.c new file mode 100644 index 000000000..2f337689e --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_ethernet.c @@ -0,0 +1,186 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/sam_ethernet.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <nuttx/irq.h> + +#include "sam_pio.h" +#include "sam_ethernet.h" + +#ifdef HAVE_NETWORK + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +#ifdef CONFIG_SAMA5_PIOE_IRQ +#ifdef CONFIG_SAMA5_EMAC +static xcpt g_emac_handler; +#endif +#ifdef CONFIG_SAMA5_GMAC +static xcpt g_gmac_handler; +#endif +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_netinitialize + * + * Description: + * Configure board resources to support networking. + * + ************************************************************************************/ + +void weak_function sam_netinitialize(void) +{ +#ifdef CONFIG_SAMA4_EMAC + /* Ethernet 10/100 (EMAC) Port + * + * The main board contains a MICREL PHY device (KSZ8051) operating at 10/100 Mbps. + * The board supports MII and RMII interface modes. + * + * The two independent PHY devices embedded on CM and MB boards are connected to + * independent RJ-45 connectors with built-in magnetic and status LEDs. + * + * At the De-Assertion of Reset: + * PHY ADD[2:0]:001 + * CONFIG[2:0]:001,Mode:RMII + * Duplex Mode:Half Duplex + * Isolate Mode:Disable + * Speed Mode:100Mbps + * Nway Auto-Negotiation:Enable + * + * The KSZ8051 PHY interrtup is available on PE30 INT_ETH1 + */ + + sam_configpio(PIO_INT_ETH1); +#endif + +#ifdef CONFIG_SAMA4_GMAC + /* Tri-Speed Ethernet PHY + * + * The SAMA5D3 series-CM board is equipped with a MICREL PHY devices (MICREL + * KSZ9021/31) operating at 10/100/1000 Mbps. The board supports RGMII interface + * mode. The Ethernet interface consists of 4 pairs of low voltage differential + * pair signals designated from GRX± and GTx± plus control signals for link + * activity indicators. These signals can be used to connect to a 10/100/1000 + * BaseT RJ45 connector integrated on the main board. + * + * The KSZ9021/31 interrupt is available on PB35 INT_GETH0 + */ + + sam_configpio(PIO_INT_ETH0); +#endif +} + +/************************************************************************************ + * Name: sam_phyirq + * + * Description: + * This function may be called to register an interrupt handler that will be + * called when an interrupt is received from a PHY. + * + ************************************************************************************/ + +#ifdef CONFIG_SAMA5_PIOE_IRQ +xcpt_t sam_phyirq(int intf, xcpt_t irqhandler) +{ + irqstate_t flags; + xcpt_t *handler; + xcpt_t oldhandler; + int irq; + +#ifdef CONFIG_SAMA5_EMAC + if (intf == EMAC_INTF) + { + handler = &g_emac_handler; + irq = IRQ_INT_ETH1; + } + else +#endif +#ifdef CONFIG_SAMA5_GMAC + if (intf == GMAC_INTF) + { + handler = &g_gmac_handler; + irq = IRQ_INT_ETH0; + } + else +#endif + { + ndbg("Unsupported interface: %d\n", intf); + return NULL; + } + + /* Disable interrupts until we are done. This guarantees that the + * following operations are atomic. + */ + + flags = irqsave(); + + /* Get the old button interrupt handler and save the new one */ + + oldhandler = *handler; + *handler = irqhandler; + + /* Configure the interrupt */ + + sam_pioirq(irq); + (void)irq_attach(irq, irqhandler); + sam_pioirqenable(irq); + + /* Return the old button handler (so that it can be restored) */ + + irqrestore(flags); + return oldhandler; +} +#endif /* CONFIG_SAMA5_PIOE_IRQ */ + +#endif /* HAVE_NETWORK */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_hsmci.c b/nuttx/configs/sama5d3-xplained/src/sam_hsmci.c new file mode 100644 index 000000000..4ce0d6da3 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_hsmci.c @@ -0,0 +1,344 @@ +/**************************************************************************** + * config/sama5d3-xplained/src/sam_hsmci.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* The SAMA5D3-Xplained provides a two SD memory card slots: (1) a full size SD card + * slot (J10), and (2) a microSD memory card slot (J11). + * + * The full size SD card slot connects via HSMCI0. The card detect discrete + * is available on PB17 (pulled high). The write protect descrete is tied to + * ground (via PP6) and not available to software. The slot supports 8-bit + * wide transfer mode, but the NuttX driver currently uses only the 4-bit + * wide transfer mode + * + * PD17 MCI0_CD + * PD1 MCI0_DA0 + * PD2 MCI0_DA1 + * PD3 MCI0_DA2 + * PD4 MCI0_DA3 + * PD5 MCI0_DA4 + * PD6 MCI0_DA5 + * PD7 MCI0_DA6 + * PD8 MCI0_DA7 + * PD9 MCI0_CK + * PD0 MCI0_CDA + * + * The microSD connects vi HSMCI1. The card detect discrete is available on + * PB18 (pulled high): + * + * PD18 MCI1_CD + * PB20 MCI1_DA0 + * PB21 MCI1_DA1 + * PB22 MCI1_DA2 + * PB23 MCI1_DA3 + * PB24 MCI1_CK + * PB19 MCI1_CDA + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdio.h> +#include <debug.h> +#include <errno.h> + +#include <nuttx/sdio.h> +#include <nuttx/mmcsd.h> + +#include "sam_pio.h" +#include "sam_hsmci.h" + +#include "sama5d3-xplained.h" + +#ifdef HAVE_HSMCI + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ +/* This structure holds static information unique to one HSMCI peripheral */ + +struct sam_hsmci_state_s +{ + struct sdio_dev_s *hsmci; /* R/W device handle */ + pio_pinset_t pincfg; /* Card detect PIO pin configuratin */ + uint8_t irq; /* Interrupt number (same as pid) */ + uint8_t slotno; /* Slot number */ + bool cd; /* TRUE: card is inserted */ + xcpt_t handler; /* Interrupt handler */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* HSCMI device state */ + +#ifdef CONFIG_SAMA5_HSMCI0 +static int sam_hsmci0_cardetect(int irq, void *regs); + +static struct sam_hsmci_state_s g_hsmci0 = +{ + .pincfg = PIO_MCI0_CD, + .irq = IRQ_MCI0_CD, + .slotno = 0, + .handler = sam_hsmci0_cardetect, +}; +#endif + +#ifdef CONFIG_SAMA5_HSMCI1 +static int sam_hsmci1_cardetect(int irq, void *regs); + +static struct sam_hsmci_state_s g_hsmci1 = +{ + .pincfg = PIO_MCI1_CD, + .irq = IRQ_MCI1_CD, + .slotno = 1, + .handler = sam_hsmci1_cardetect, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_cardinserted_internal + * + * Description: + * Check if a card is inserted into the selected HSMCI slot + * + ****************************************************************************/ + +bool sam_cardinserted_internal(struct sam_hsmci_state_s *state) +{ + bool inserted; + + /* Get the state of the PIO pin */ + + inserted = sam_pioread(state->pincfg); + fllvdbg("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES"); + return !inserted; +} + +/**************************************************************************** + * Name: sam_hsmci_cardetect, sam_hsmci0_cardetect, and sam_hsmci1_cardetect + * + * Description: + * Card detect interrupt handlers + * + ****************************************************************************/ + +static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state) +{ + /* Get the current card insertion state */ + + bool cd = sam_cardinserted_internal(state); + + /* Has the card detect state changed? */ + + if (cd != state->cd) + { + /* Yes... remember that new state and inform the HSMCI driver */ + + state->cd = cd; + + /* Report the new state to the SDIO driver */ + + sdio_mediachange(state->hsmci, cd); + } + + return OK; +} + +#ifdef CONFIG_SAMA5_HSMCI0 +static int sam_hsmci0_cardetect(int irq, void *regs) +{ + return sam_hsmci_cardetect(&g_hsmci0); +} +#endif + +#ifdef CONFIG_SAMA5_HSMCI1 +static int sam_hsmci1_cardetect(int irq, void *regs) +{ + return sam_hsmci_cardetect(&g_hsmci1); +} +#endif + +/**************************************************************************** + * Name: sam_hsmci_state + * + * Description: + * Initialize HSMCI PIOs. + * + ****************************************************************************/ + +static struct sam_hsmci_state_s *sam_hsmci_state(int slotno) +{ + struct sam_hsmci_state_s *state = NULL; + +#ifdef CONFIG_SAMA5_HSMCI0 +#ifdef CONFIG_SAMA5_HSMCI1 + if (slotno == 0) +#endif + { + state = &g_hsmci0; + } +#ifdef CONFIG_SAMA5_HSMCI1 + else +#endif +#endif + +#ifdef CONFIG_SAMA5_HSMCI1 + { + state = &g_hsmci1; + } +#endif + + return state; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_hsmci_initialize + * + * Description: + * Perform architecture specific initialization + * + ****************************************************************************/ + +int sam_hsmci_initialize(int slotno, int minor) +{ + struct sam_hsmci_state_s *state; + int ret; + + /* Get the static HSMI description */ + + state = sam_hsmci_state(slotno); + if (!state) + { + fdbg("No state for slotno %d\n", slotno); + return -EINVAL; + } + + /* Initialize card-detect and write-protect PIOs */ + + sam_configpio(state->pincfg); + + /* Mount the SDIO-based MMC/SD block driver */ + /* First, get an instance of the SDIO interface */ + + state->hsmci = sdio_initialize(slotno); + if (!state->hsmci) + { + fdbg("Failed to initialize SDIO slot %d\n", slotno); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(minor, state->hsmci); + if (ret != OK) + { + fdbg("Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + /* Configure card detect interrupts */ + + sam_pioirq(state->pincfg); + (void)irq_attach(state->irq, state->handler); + + /* Then inform the HSMCI driver if there is or is not a card in the slot. */ + + state->cd = sam_cardinserted_internal(state); + sdio_mediachange(state->hsmci, state->cd); + + /* Enable card detect interrupts */ + + sam_pioirqenable(state->irq); + return OK; +} + +/**************************************************************************** + * Name: sam_cardinserted + * + * Description: + * Check if a card is inserted into the selected HSMCI slot + * + ****************************************************************************/ + +bool sam_cardinserted(int slotno) +{ + struct sam_hsmci_state_s *state; + + /* Get the HSMI description */ + + state = sam_hsmci_state(slotno); + if (!state) + { + fdbg("No state for slotno %d\n", slotno); + return false; + } + + /* Return the state of the PIO pin */ + + return sam_cardinserted_internal(state); +} + +/**************************************************************************** + * Name: sam_writeprotected + * + * Description: + * Check if a card is inserted into the selected HSMCI slot + * + ****************************************************************************/ + +bool sam_writeprotected(int slotno) +{ + /* There are no write protect pins */ + + return false; +} + +#endif /* HAVE_HSMCI */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_i2schar.c b/nuttx/configs/sama5d3-xplained/src/sam_i2schar.c new file mode 100644 index 000000000..8842c1046 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_i2schar.c @@ -0,0 +1,124 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/sam_i2schar.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/audio/i2s.h> + +#include "sam_ssc.h" +#include "sama5d3-xplained.h" + +#if defined(CONFIG_AUDIO_I2SCHAR) && \ + (defined(CONFIG_SAMA5_SSC0) || defined(CONFIG_SAMA5_SSC1)) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef CONFIG_SAMA5D3XPLAINED_SSC_PORT +# if defined(CONFIG_SAMA5_SSC0) +# define CONFIG_SAMA5D3XPLAINED_SSC_PORT 0 +# elif defined(CONFIG_SAMA5_SSC1) +# define CONFIG_SAMA5D3XPLAINED_SSC_PORT 1 +# endif +#endif + +#ifndef CONFIG_SAMA5D3XPLAINED_I2SCHAR_MINOR +# define CONFIG_SAMA5D3XPLAINED_I2SCHAR_MINOR 0 +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: i2schar_devinit + * + * Description: + * All architectures must provide the following interface in order to work with + * apps/examples/i2schar. + * + ************************************************************************************/ + +int i2schar_devinit(void) +{ + static bool initialized = false; + struct i2s_dev_s *i2s; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call sam_ssc_initialize() to get an instance of the SSC/I2S interface */ + + i2s = sam_ssc_initialize(CONFIG_SAMA5D3XPLAINED_SSC_PORT); + if (!i2s) + { + dbg("ERROR: Failed to get the SAMA5 SSC/I2S driver for SSC%d\n", + CONFIG_SAMA5D3XPLAINED_SSC_PORT); + return -ENODEV; + } + + /* Register the I2S character driver at "/dev/i2schar0" */ + + ret = i2schar_register(i2s, CONFIG_SAMA5D3XPLAINED_I2SCHAR_MINOR); + if (ret < 0) + { + adbg("ERROR: i2schar_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_AUDIO_I2SCHAR && (CONFIG_SAMA5_SSC0 || CONFIG_SAMA5_SSC1) */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_nandflash.c b/nuttx/configs/sama5d3-xplained/src/sam_nandflash.c new file mode 100644 index 000000000..19572b075 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_nandflash.c @@ -0,0 +1,231 @@ +/**************************************************************************** + * configs/sama5d3-xplained/src/sam_norflash.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Most of this file derives from Atmel sample code for the SAMA5D3-Xplained + * board. That sample code has licensing that is compatible with the NuttX + * modified BSD license: + * + * Copyright (c) 2012, Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor Atmel nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/mount.h> +#include <stdbool.h> +#include <stdint.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/mtd/mtd.h> +#include <nuttx/fs/nxffs.h> + +#include "up_arch.h" +#include "sam_periphclks.h" +#include "sam_pio.h" +#include "sam_nand.h" +#include "chip/sam_hsmc.h" +#include "chip/sam_pinmap.h" + +#include "sama5d3-xplained.h" + +#ifdef CONFIG_SAMA5_EBICS3_NAND + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_nandflash_config + * + * Description: + * If CONFIG_SAMA5_EBICS3_NAND is defined, then NAND FLASH support is + * enabled. This function provides the board-specific implementation of + * the logic to reprogram the SMC to support NAND FLASH on the specified + * CS. + * + * Input Parameters: + * cs - Chip select number (in the event that multiple NAND devices + * are connected on-board). + * + * Returned Values: + * OK if the HSMC was successfully configured for this CS. A negated + * errno value is returned on a failure. This would fail with -ENODEV, + * for example, if the board does not support NAND FLASH on the requested + * CS. + * + ****************************************************************************/ + +int board_nandflash_config(int cs) +{ + uint32_t regval; + + /* The Embest and Ronetix CM boards and one Hynix NAND HY27UF(08/16)2G2B + * Series NAND (MT29F2G08ABAEAWP). This part has a capacity of 256Mx8bit + * () with spare 8Mx8 bit capacity. The device contains 2048 blocks, composed + * by 64 x 2112 byte pages. The effective size is approximately 256MiB. + * + * NAND is available on CS3. + */ + + if (cs == HSMC_CS3) + { + /* Make sure that the SMC peripheral is enabled. */ + + sam_hsmc_enableclk(); + + /* Configure the SMC */ + + regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(1) | + HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(1); + putreg32(regval, SAM_HSMC_SETUP(HSMC_CS3)); + + regval = HSMC_PULSE_NWE_PULSE(5) | HSMC_PULSE_NCS_WRPULSE(7) | + HSMC_PULSE_NRD_PULSE(5) | HSMC_PULSE_NCS_RDPULSE(7); + putreg32(regval, SAM_HSMC_PULSE(HSMC_CS3)); + + regval = HSMC_CYCLE_NWE_CYCLE(8) | HSMC_CYCLE_NRD_CYCLE(9); + putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS3)); + + regval = HSMC_TIMINGS_TCLR(3) | HSMC_TIMINGS_TADL(10) | + HSMC_TIMINGS_TAR(3) | HSMC_TIMINGS_TRR(4) | + HSMC_TIMINGS_TWB(5) | HSMC_TIMINGS_RBNSEL(3) | + HSMC_TIMINGS_NFSEL; + putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS3)); + + regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE | + HSMC_MODE_BIT_8 | HSMC_MODE_TDFCYCLES(1); + putreg32(regval, SAM_HSMC_MODE(HSMC_CS3)); + + /* Configure NAND PIO pins + * + * NAND Interface: + * + * NCS3/NANDCE - Dedicated pin; no configuration needed + * NANDCLE - PE21 + * NANDALE - PE22 + * NRD/NANDOE - Dedicated pin; no configuration needed + * NWE/NANDWE - Dedicated pin; no configuration needed + * NANDRDY - Dedicated pin; no configuration needed + * M_EBI_D0-7 - Dedicated pins; no configuration needed + */ + + sam_configpio(PIO_HSMC_NANDALE); + sam_configpio(PIO_HSMC_NANDCLE); + + return OK; + } + + return -ENODEV; +} + +/**************************************************************************** + * Name: sam_nand_automount + * + * Description: + * Initialize and configure the NAND on CS3 + * + ****************************************************************************/ + +#ifdef HAVE_NAND +int sam_nand_automount(int minor) +{ + FAR struct mtd_dev_s *mtd; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Create and initialize an NAND MATD device */ + + mtd = sam_nand_initialize(HSMC_CS3); + if (!mtd) + { + fdbg("ERROR: Failed to create the NAND driver on CS%d\n", HSMC_CS3); + return -ENODEV; + } + +#if defined(CONFIG_SAMA5D3XPLAINED_NAND_FTL) + /* Use the FTL layer to wrap the MTD driver as a block driver */ + + ret = ftl_initialize(NAND_MINOR, mtd); + if (ret < 0) + { + fdbg("ERROR: Failed to initialize the FTL layer: %d\n", ret); + return ret; + } + +#elif defined(CONFIG_SAMA5D3XPLAINED_NAND_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + fdbg("ERROR: NXFFS initialization failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/nand */ + + ret = mount(NULL, "/mnt/nand", "nxffs", 0, NULL); + if (ret < 0) + { + fdbg("ERROR: Failed to mount the NXFFS volume: %d\n", errno); + return ret; + } +#endif + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} +#endif + +#endif /* CONFIG_SAMA5_EBICS3_NAND */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_norflash.c b/nuttx/configs/sama5d3-xplained/src/sam_norflash.c new file mode 100644 index 000000000..871461a5a --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_norflash.c @@ -0,0 +1,145 @@ +/**************************************************************************** + * configs/sama5d3-xplained/src/sam_norflash.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Most of this file derives from Atmel sample code for the SAMA5D3-Xplained + * board. That sample code has licensing that is compatible with the NuttX + * modified BSD license: + * + * Copyright (c) 2012, Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor Atmel nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> + +#include "up_arch.h" +#include "sam_periphclks.h" +#include "chip/sam_hsmc.h" + +#include "sama5d3-xplained.h" + +#ifdef CONFIG_SAMA5_BOOT_CS0FLASH + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_norflash_config + * + * Description: + * If CONFIG_SAMA5_BOOT_CS0FLASH, then the system is boot directly off + * CS0 NOR FLASH. In this case, we assume that we get here from the + * primary boot loader under these conditions: + * + * "If BMS signal is tied to 0, BMS_BIT is read at 1. The ROM Code + * allows execution of the code contained into the memory connected to + * Chip Select 0 of the External Bus Interface. + * + * "To achieve that, the following sequence is preformed by the ROM + * Code: + * + * - The main clock is the on-chip 12 MHz RC oscillator, + * - The Static Memory Controller is configured with timing allowing + * code execution inCS0 external memory at 12 MHz + * - AXI matrix is configured to remap EBI CS0 address at 0x0 + * - 0x0 is loaded in the Program Counter register + * + * "The user software in the external memory must perform the next + * operation in order to complete the clocks and SMC timings + * configuration to run at a higher clock frequency: + * + * - Enable the 32768 Hz oscillator if best accuracy is needed + * - Reprogram the SMC setup, cycle, hold, mode timing registers + * for EBI CS0, to adapt them to the new clock + * - Program the PMC (Main Oscillator Enable or Bypass mode) + * - Program and Start the PLL + * - Switch the system clock to the new value" + * + * This function provides the board-specific implementation of the logic + * to reprogram the SMC. + * + ****************************************************************************/ + +void board_norflash_config(void) +{ + uint32_t regval; + + /* Make sure that the SMC peripheral is enabled (But of course it is... we + * are executing from NOR FLASH now). + */ + + sam_hsmc_enableclk(); + + /* The SAMA5D3-Xplained has 118MB of 16-bit NOR FLASH at CS0. The NOR FLASH + * has already been configured by the first level ROM bootloader... we + * simply need to modify the timing here. + */ + + regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(0) | + HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(0); + putreg32(regval, SAM_HSMC_SETUP(HSMC_CS0)); + + regval = HSMC_PULSE_NWE_PULSE(10) | HSMC_PULSE_NCS_WRPULSE(10) | + HSMC_PULSE_NRD_PULSE(11) | HSMC_PULSE_NCS_RDPULSE(11); + putreg32(regval, SAM_HSMC_PULSE(HSMC_CS0)); + + regval = HSMC_CYCLE_NWE_CYCLE(11) | HSMC_CYCLE_NRD_CYCLE(14); + putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS0)); + + regval = HSMC_TIMINGS_TCLR(0) | HSMC_TIMINGS_TADL(0) | + HSMC_TIMINGS_TAR(0) | HSMC_TIMINGS_TRR(0) | + HSMC_TIMINGS_TWB(0) | HSMC_TIMINGS_RBNSEL(0); + putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS0)); + + regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE | + HSMC_MODE_EXNWMODE_DISABLED | HSMC_MODE_BIT_16 | + HSMC_MODE_TDFCYCLES(1); + putreg32(regval, SAM_HSMC_MODE(HSMC_CS0)); +} + +#endif /* CONFIG_SAMA5_BOOT_CS0FLASH */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_nsh.c b/nuttx/configs/sama5d3-xplained/src/sam_nsh.c new file mode 100644 index 000000000..20cb0ae85 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_nsh.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * config/sama5d3-xplained/src/sam_nsh.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/mount.h> + +#include <stdbool.h> +#include <stdio.h> +#include <errno.h> +#include <debug.h> + +#ifdef CONFIG_SYSTEM_USBMONITOR +# include <apps/usbmonitor.h> +#endif + +#include "sama5d3-xplained.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/* Debug ********************************************************************/ + +#ifdef CONFIG_CPP_HAVE_VARARGS +# ifdef CONFIG_DEBUG +# define message(...) syslog(__VA_ARGS__) +# else +# define message(...) printf(__VA_ARGS__) +# endif +#else +# ifdef CONFIG_DEBUG +# define message syslog +# else +# define message printf +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_archinitialize + * + * Description: + * Perform architecture specific initialization + * + ****************************************************************************/ + +int nsh_archinitialize(void) +{ +#if defined(HAVE_NAND) || defined(HAVE_AT25) || defined(HAVE_HSMCI) || \ + defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR) + int ret; +#endif + +#ifdef HAVE_NAND + /* Initialize the NAND driver */ + + ret = sam_nand_automount(NAND_MINOR); + if (ret < 0) + { + message("ERROR: sam_nand_automount failed: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_AT25 + /* Initialize the AT25 driver */ + + ret = sam_at25_automount(AT25_MINOR); + if (ret < 0) + { + message("ERROR: sam_at25_automount failed: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_HSMCI +#ifdef CONFIG_SAMA5_HSMCI0 + /* Initialize the HSMCI0 driver */ + + ret = sam_hsmci_initialize(HSMCI0_SLOTNO, HSMCI0_MINOR); + if (ret < 0) + { + message("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n", + HSMCI0_SLOTNO, HSMCI0_MINOR, ret); + return ret; + } +#endif + +#ifdef CONFIG_SAMA5_HSMCI1 + /* Initialize the HSMCI1 driver */ + + ret = sam_hsmci_initialize(HSMCI1_SLOTNO, HSMCI1_MINOR); + if (ret < 0) + { + message("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n", + HSMCI1_SLOTNO, HSMCI1_MINOR, ret); + return ret; + } +#endif +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. sam_usbhost_initialize() starts a thread + * will monitor for USB connection and disconnection events. + */ + + ret = sam_usbhost_initialize(); + if (ret != OK) + { + message("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(0, NULL); + if (ret != OK) + { + message("nsh_archinitialize: Start USB monitor: %d\n", ret); + } +#endif + + return OK; +} diff --git a/nuttx/configs/sama5d3-xplained/src/sam_ostest.c b/nuttx/configs/sama5d3-xplained/src/sam_ostest.c new file mode 100644 index 000000000..c169d9da5 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_ostest.c @@ -0,0 +1,113 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/sam_ostest.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <string.h> +#include <debug.h> + +#include <arch/irq.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "up_internal.h" +#include "sama5d3-xplained.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#undef HAVE_FPU +#if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_EXAMPLES_OSTEST_FPUTESTDISABLE) && \ + defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \ + !defined(CONFIG_DISABLE_SIGNALS) +# define HAVE_FPU 1 +#endif + +#ifdef HAVE_FPU + +#if CONFIG_EXAMPLES_OSTEST_FPUSIZE != (4*FPU_CONTEXT_REGS) +# error "CONFIG_EXAMPLES_OSTEST_FPUSIZE has the wrong size" +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static uint32_t g_saveregs[XCPTCONTEXT_REGS]; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ +/* Given an array of size CONFIG_EXAMPLES_OSTEST_FPUSIZE, this function will return + * the current FPU registers. + */ + +void arch_getfpu(FAR uint32_t *fpusave) +{ + irqstate_t flags; + + /* Take a snapshot of the thread context right now */ + + flags = irqsave(); + up_saveusercontext(g_saveregs); + + /* Return only the floating register values */ + + memcpy(fpusave, &g_saveregs[REG_S0], (4*FPU_CONTEXT_REGS)); + irqrestore(flags); +} + +/* Given two arrays of size CONFIG_EXAMPLES_OSTEST_FPUSIZE this function + * will compare them and return true if they are identical. + */ + +bool arch_cmpfpu(FAR const uint32_t *fpusave1, FAR const uint32_t *fpusave2) +{ + return memcmp(fpusave1, fpusave2, (4*FPU_CONTEXT_REGS)) == 0; +} + +#endif /* HAVE_FPU */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_pwm.c b/nuttx/configs/sama5d3-xplained/src/sam_pwm.c new file mode 100644 index 000000000..5992bd0d5 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_pwm.c @@ -0,0 +1,161 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/sam_pwm.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/pwm.h> +#include <arch/board/board.h> + +#include "sam_pwm.h" +#include "sama5d3-xplained.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ +/* PWM. There are no dedicated PWM output pins available to the user for PWM + * testing. Care must be taken because all PWM output pins conflict with some other + * usage of the pin by other devices: + * + * -----+---+---+----+-------------------- + * PWM PIN PER PIO CONFLICTS + * -----+---+---+----+-------------------- + * PWM0 FI B PC28 SPI1, ISI + * H B PB0 GMAC + * B PA20 LCDC, ISI + * L B PB1 GMAC + * B PA21 LCDC, ISI + * -----+---+---+----+-------------------- + * PWM1 FI B PC31 HDMI + * H B PB4 GMAC + * B PA22 LCDC, ISI + * L B PB5 GMAC + * B PE31 ISI, HDMI + * B PA23 LCDC, ISI + * -----+---+---+----+-------------------- + * PWM2 FI B PC29 UART0, ISI, HDMI + * H C PD5 HSMCI0 + * B PB8 GMAC + * L C PD6 HSMCI0 + * B PB9 GMAC + * -----+---+---+----+-------------------- + * PWM3 FI C PD16 SPI0, Audio + * H C PD7 HSMCI0 + * B PB12 GMAC + * L C PD8 HSMCI0 + * B PB13 GMAC + * -----+---+---+----+-------------------- + */ + +#ifndef CONFIG_SAMA5D3XPLAINED_CHANNEL +# if defined(CONFIG_SAMA5_PWM_CHAN0) +# warning Assuming PWM channel 0 +# define CONFIG_SAMA5D3XPLAINED_CHANNEL 0 +# elif defined(CONFIG_SAMA5_PWM_CHAN1) +# warning Assuming PWM channel 1 +# define CONFIG_SAMA5D3XPLAINED_CHANNEL 1 +# elif defined(CONFIG_SAMA5_PWM_CHAN2) +# warning Assuming PWM channel 2 +# define CONFIG_SAMA5D3XPLAINED_CHANNEL 2 +# elif defined(CONFIG_SAMA5_PWM_CHAN3) +# warning Assuming PWM channel 3 +# define CONFIG_SAMA5D3XPLAINED_CHANNEL 3 +# endif +#endif + +#if defined(CONFIG_PWM) && defined(CONFIG_SAMA5_PWM) + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: pwm_devinit + * + * Description: + * All SAMA5 architectures must provide the following interface to work with + * examples/pwm. + * + ************************************************************************************/ + +int pwm_devinit(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call sam_pwminitialize() to get an instance of the PWM interface */ + + pwm = sam_pwminitialize(CONFIG_SAMA5D3XPLAINED_CHANNEL); + if (!pwm) + { + dbg("Failed to get the SAMA5 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + adbg("pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_sdram.c b/nuttx/configs/sama5d3-xplained/src/sam_sdram.c new file mode 100644 index 000000000..9e0bee0c8 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_sdram.c @@ -0,0 +1,578 @@ +/**************************************************************************** + * configs/sama5d3-xplained/src/sam_sdram.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Most of this file derives from Atmel sample code for the SAMA5D3x-E + * board. That sample code has licensing that is compatible with the NuttX + * modified BSD license: + * + * Copyright (c) 2012, Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor Atmel nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> + +#include "up_arch.h" + +#include "sam_periphclks.h" +#include "chip/sam_memorymap.h" +#include "chip/sam_pmc.h" +#include "chip/sam_sfr.h" +#include "chip/sam_mpddrc.h" + +#include "sama5d3-xplained.h" + +/* This file requires: + * + * CONFIG_SAMA5_DDRCS -- DRAM support is enabled, and + * !CONFIG_SAMA5_BOOT_SDRAM - We did not boot into SRAM. + */ + +#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* SDRAM differences */ + +#if defined(CONFIG_SAMA5D3XPLAINED_MT47H128M16RT) + + /* Used for SDRAM command handshaking */ + +# define DDR2_BA0 (1 << 26) +# define DDR2_BA1 (1 << 27) + +#elif defined(CONFIG_SAMA5D3XPLAINED_MT47H64M16HR) + + /* Used for SDRAM command handshaking */ + +# define DDR2_BA0 (1 << 25) +# define DDR2_BA1 (1 << 26) + +#else +# error Unknown SDRAM type +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_sdram_delay + * + * Description: + * Precision delay function for SDRAM configuration. + * + * This delay loop requires 6 core cycles per iteration. At 396MHz, that + * is equivalent to 15.1515 nanoseconds per iteration. + * + ****************************************************************************/ + +static inline void sam_sdram_delay(unsigned int loops) +{ + volatile unsigned int i; + + for (i = 0; i < loops; i++) + { + asm("nop"); + } +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_sdram_config + * + * Description: + * Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR) + * + * Configures DDR2 (MT47H128M16RT 128MB or, optionally, MT47H64M16HR) + * + * Per the SAMA5D3-Xplained User guide: "Two SDRAM/DDR2 used as main system memory. + * MT47H128M16 - 2 Gb - 16 Meg x 16 x 8 banks, the board provides up to 2 Gb on- + * board, soldered DDR2 SDRAM. The memory bus is 32 bits wide and operates with + * up to 166 MHz." + * + * From the Atmel Code Example: + * MT47H64M16HR : 8 Meg x 16 x 8 banks + * Refresh count: 8K + * Row address: A[12:0] (8K) + * Column address A[9:0] (1K) + * Bank address BA[2:0] a(24,25) (8) + * + * This logic was taken from Atmel sample code for the SAMA5D3-Xplained. + * + * Input Parameters: + * devtype - Either DDRAM_MT47H128M16RT or DDRAM_MT47H64M16HR + * + * Assumptions: + * The DDR memory regions is configured as strongly ordered memory. When + * we complete initialization of SDRAM and it is ready for use, we will + * make DRAM into normal memory. + * + ************************************************************************************/ + +void sam_sdram_config(void) +{ + volatile uint8_t *ddr = (uint8_t *)SAM_DDRCS_VSECTION; + uint32_t regval; + + /* Enable x2 clocking to the MPDDRC */ + + sam_mpddrc_enableclk(); + + /* Enable DDR clocking */ + + regval = getreg32(SAM_PMC_SCER); + regval |= PMC_DDRCK; + putreg32(regval, SAM_PMC_SCER); + + /* Clear the low power register */ + + putreg32(0, SAM_MPDDRC_LPR); + + /* Enable autofresh during calibration (undocumented) */ + + regval = getreg32(SAM_MPDDRC_HS); + regval |= MPDDRC_HS_AUTOREFRESH_CAL; + putreg32(regval, SAM_MPDDRC_HS); + + /* Force DDR_DQ and DDR_DQS input buffer always on (undocumented) */ + + regval = getreg32(SAM_SFR_DDRCFG); + regval |= SFR_DDRCFG_DRQON; + putreg32(regval, SAM_SFR_DDRCFG); + + /* Configure the slave offset register */ + + regval = MPDDRC_DLL_SOR_S0OFF(1) | /* DLL Slave 0 Delay Line Offset */ + MPDDRC_DLL_SOR_S1OFF(0) | /* DLL Slave 1 Delay Line Offset */ + MPDDRC_DLL_SOR_S2OFF(1) | /* DLL Slave 2 Delay Line Offset */ + MPDDRC_DLL_SOR_S3OFF(1); /* DLL Slave 3 Delay Line Offset */ + putreg32(regval, SAM_MPDDRC_DLL_SOR); + + /* Configure the master offset register (including upper mystery bits) */ + + regval = MPDDRC_DLL_MOR_MOFF(7) | /* DLL Master Delay Line Offset */ + MPDDRC_DLL_MOR_CLK90OFF(31) | /* DLL CLK90 Delay Line Offset */ + MPDDRC_DLL_MOR_SELOFF | /* DLL Offset Selection */ + MPDDRC_DLL_MOR_KEY; /* Undocumented key */ + putreg32(regval, SAM_MPDDRC_DLL_MOR); + + /* Configure the I/O calibration register */ + + regval = getreg32(SAM_MPDDRC_IO_CALIBR); + regval &= ~(MPDDRC_IO_CALIBR_RDIV_MASK | MPDDRC_IO_CALIBR_TZQIO_MASK); + regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3)); + putreg32(regval, SAM_MPDDRC_IO_CALIBR); + + /* Force DDR_DQ and DDR_DQS input buffer always on, clearing other bits + * (undocumented) + */ + + putreg32(SFR_DDRCFG_DRQON, SAM_SFR_DDRCFG); + + /* Step 1: Program the memory device type + * + * DBW = 0 (32-bit bus wide) + * Memory Device = DDR2-SDRAM + */ + + putreg32(MPDDRC_MD_DDR2_SDRAM, SAM_MPDDRC_MD); + + /* Step 2: Program the features of DDR2-SDRAM device into the Timing + * Register + */ + +#if defined(CONFIG_SAMA5D3XPLAINED_MT47H128M16RT) + + /* For MT47H128M16RT + * + * NC = 10 DDR column bits + * NR = 14 DDR row bits + * CAS = DDR2/LPDDR2 CAS Latency 4 + * DLL = Disable reset (0) + * DIC_DS = 0 + * DIS_DLL = Enable PLL (0) + * ZQ = Calibration command after initialization (0) + * OCD = OCD calibration mode exit, maintain setting (0) + * DQMS = Not shared (0) + * ENDRM = Disable read measure (0) + * NB = 8 banks + * NDQS = Not DQS disabled + * DECODE = Sequential decoding (0) + * UNAL = Unaliged access supported + */ + + regval = MPDDRC_CR_NC_10 | /* Number of Column Bits */ + MPDDRC_CR_NR_14 | /* Number of Row Bits */ + MPDDRC_CR_CAS_4 | /* CAS Latency */ + MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ + MPDDRC_CR_8BANKS | /* Number of Banks */ + MPDDRC_CR_NDQS | /* Not DQS */ + MPDDRC_CR_UNAL; /* upport Unaligned Access */ + +#elif defined(CONFIG_SAMA5D3XPLAINED_MT47H64M16HR) + /* For MT47H64M16HR + * + * NC = 10 DDR column bits + * NR = 13 DDR row bits + * CAS = DDR2/LPDDR2 CAS Latency 3 + * DLL = Disable reset (0) + * DIC_DS = 0 + * DIS_DLL = Enable PLL (0) + * ZQ = Calibration command after initialization (0) + * OCD = OCD calibration mode exit, maintain setting (0) + * DQMS = Not shared (0) + * ENDRM = Disable read measure (0) + * NB = 8 banks + * NDQS = Not DQS disabled + * DECODE = Sequential decoding (0) + * UNAL = Unaliged access supported + */ + + regval = MPDDRC_CR_NC_10 | /* Number of Column Bits */ + MPDDRC_CR_NR_13 | /* Number of Row Bits */ + MPDDRC_CR_CAS_3 | /* CAS Latency */ + MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ + MPDDRC_CR_8BANKS | /* Number of Banks */ + MPDDRC_CR_NDQS | /* Not DQS */ + MPDDRC_CR_UNAL; /* upport Unaligned Access */ + +#else +# error Unknwon SDRAM type +#endif + + putreg32(regval, SAM_MPDDRC_CR); + + /* Configure the Timing Parameter 0 Register */ + + regval = MPDDRC_TPR0_TRAS(6) | /* Active to Precharge Delay: 6 * 7.5 = 45 ns */ + MPDDRC_TPR0_TRCD(2) | /* Row to Column Delay: 2 * 7.5 = 15 ns */ + MPDDRC_TPR0_TWR(2) | /* Write Recovery Delay: 3 * 7.5 = 22.5 ns */ + MPDDRC_TPR0_TRC(8) | /* Row Cycle Delay: 8 * 7.5 = 60 ns */ + MPDDRC_TPR0_TRP(2) | /* Row Precharge Delay: 2 * 7.5 = 15 ns */ + MPDDRC_TPR0_TRRD(1) | /* Active BankA to Active BankB: 2 * 7.5 = 15 ns */ + MPDDRC_TPR0_TWTR(2) | /* Internal Write to Read Delay: 2 clock cycle */ + MPDDRC_TPR0_TMRD(2); /* Load Mode Register Command to + * Activate or Refresh Command: 2 clock cycles */ + putreg32(regval, SAM_MPDDRC_TPR0); + + /* Configure the Timing Parameter 1 Register */ + + regval = MPDDRC_TPR1_TRFC(14) | /* Row Cycle Delay: + * 18 * 7.5 = 135 ns (min 127.5 ns for 1Gb DDR) */ + MPDDRC_TPR1_TXSNR(16) | /* Exit Self Refresh Delay to Non Read Command: + * 20 * 7.5 > 142.5ns TXSNR: Exit self refresh + * delay to non read command */ + MPDDRC_TPR1_TXSRD(208) | /* Exit Self Refresh Delay to Read Command: + * min 200 clock cycles, TXSRD: Exit self refresh + * delay to Read command */ + MPDDRC_TPR1_TXP(2); /* Exit Power-down Delay to First Command: + * 2 * 7.5 = 15 ns */ + putreg32(regval, SAM_MPDDRC_TPR1); + + /* Configure the Timing Parameter 2 Register */ + + regval = MPDDRC_TPR2_TXARD(7) | /* Exit Active Power Down Delay to Read Command in Mode 'Fast Exit': + * min 2 clock cycles */ + MPDDRC_TPR2_TXARDS(7) | /* Exit Active Power Down Delay to Read Command in Mode 'Slow Exit': + * min 7 clock cycles */ + MPDDRC_TPR2_TRPA(2) | /* Row Precharge All Delay: + * min 18ns */ + MPDDRC_TPR2_TRTP(2) | /* Four Active Windows: + * 2 * 7.5 = 15 ns (min 7.5ns) */ + MPDDRC_TPR2_TFAW(10); + putreg32(regval, SAM_MPDDRC_TPR2); + + /* DDRSDRC Low-power Register */ + + sam_sdram_delay(13300); + + regval = MPDDRC_LPR_LPCB_DISABLED | /* Low-power Feature is inhibited */ + MPDDRC_LPR_TIMEOUT_0CLKS | /* Activates low-power mode after the end of transfer */ + MPDDRC_LPR_APDE_FAST; /* Active Power Down Exit Time */ + putreg32(regval, SAM_MPDDRC_LPR); + + /* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP + * command into the Mode Register, the application must set MODE to 1 in + * the Mode Register. + */ + + putreg32(MPDDRC_MR_MODE_NOP, SAM_MPDDRC_MR); + + /* Perform a write access to any DDR2-SDRAM address to acknowledge this + * command. + */ + + *ddr = 0; + + /* Now clocks which drive DDR2-SDRAM device are enabled. + * + * A minimum pause of 200 usec is provided to precede any signal toggle. + * (6 core cycles per iteration, core is at 396MHz: min 13200 loops) + */ + + sam_sdram_delay(13300); + + /* Step 4: An NOP command is issued to the DDR2-SDRAM */ + + putreg32(MPDDRC_MR_MODE_NOP, SAM_MPDDRC_MR); + + /* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/ + + *ddr = 0; + + /* Now CKE is driven high.*/ + /* Wait 400 ns min */ + + sam_sdram_delay(100); + + /* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */ + + putreg32(MPDDRC_MR_MODE_PRCGALL, SAM_MPDDRC_MR); + + /* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/ + + *ddr = 0; + + /* Wait 400 ns min */ + + sam_sdram_delay(100); + + /* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose + * between commercialor high temperature operations. + * + * The write address must be chosen so that BA[1] is set to 1 and BA[0] is + * set to 0. + */ + + putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR); + *((volatile uint8_t *)(ddr + DDR2_BA1)) = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set + * all registers to 0. + * + * The write address must be chosen so that BA[1] is set to 1 and BA[0] is + * set to 1. + */ + + putreg32(MPDDRC_MR_MODE_LMR, SAM_MPDDRC_MR); + *((volatile uint8_t *)(ddr + DDR2_BA1 + DDR2_BA0)) = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. + * + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. + */ + + putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR); + *((volatile uint8_t *)(ddr + DDR2_BA0)) = 0; + + /* An additional 200 cycles of clock are required for locking DLL */ + + sam_sdram_delay(10000); + + /* Step 9: Program DLL field into the Configuration Register.*/ + + regval = getreg32(SAM_MPDDRC_CR); + regval |= MPDDRC_CR_DLL; + putreg32(regval, SAM_MPDDRC_CR); + + /* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL. + * + * The write address must be chosen so that BA[1:0] bits are set to 0. + */ + + putreg32(MPDDRC_MR_MODE_LMR, SAM_MPDDRC_MR); + *ddr = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. + * + * Perform a write access to any DDR2-SDRAM address to acknowledge this + * command + */ + + putreg32(MPDDRC_MR_MODE_PRCGALL, SAM_MPDDRC_MR); + *ddr = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto + * refresh command (CBR) into the Mode Register. + * + * Perform a write access to any DDR2-SDRAM address to acknowledge this + * command. + */ + + putreg32(MPDDRC_MR_MODE_RFSH, SAM_MPDDRC_MR); + *ddr = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Configure 2nd CBR. + * + * Perform a write access to any DDR2-SDRAM address to acknowledge this command. + */ + + putreg32(MPDDRC_MR_MODE_RFSH, SAM_MPDDRC_MR); + *ddr = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Step 13: Program DLL field into the Configuration Register to low + * (Disable DLL reset). + */ + + regval = getreg32(SAM_MPDDRC_CR); + regval &= ~MPDDRC_CR_DLL; + putreg32(regval, SAM_MPDDRC_CR); + + /* Step 14: A Mode Register set (MRS) cycle is issued to program the + * parameters of the DDR2-SDRAM devices. + * + * The write address must be chosen so that BA[1:0] are set to 0. + */ + + putreg32(MPDDRC_MR_MODE_LMR, SAM_MPDDRC_MR); + *ddr = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Step 15: Program OCD field into the Configuration Register to high (OCD + * calibration default). + */ + + regval = getreg32(SAM_MPDDRC_CR); + regval |= MPDDRC_CR_OCD_DEFAULT; + putreg32(regval, SAM_MPDDRC_CR); + + /* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD + * default value. + * + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is + * set to 1. + */ + + putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR); + *((volatile uint8_t *)(ddr + DDR2_BA0)) = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Step 17: Program OCD field into the Configuration Register to low (OCD + * calibration mode exit). + */ + +#if 0 + regval = getreg32(SAM_MPDDRC_CR); + regval &= ~MPDDRC_CR_OCD_MASK; + putreg32(regval, SAM_MPDDRC_CR); +#endif + + /* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to + * enable OCD exit. + * + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is + * set to 1. + */ + + putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR); + *((volatile uint8_t *)(ddr + DDR2_BA0)) = 0; + + /* Wait 2 cycles min */ + + sam_sdram_delay(100); + + /* Step 19,20: A mode Normal command is provided. Program the Normal mode + * into Mode Register. + */ + + putreg32(MPDDRC_MR_MODE_NORMAL, SAM_MPDDRC_MR); + *ddr = 0; + + /* Step 21: Write the refresh rate into the count field in the Refresh + * Timer register. The DDR2-SDRAM device requires a refresh every 15.625 + * usec or 7.81 usec. + * + * With a 100MHz frequency, the refresh timer count register must to be + * set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 + * i.e. 0x030d. + */ + + /* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates + * to an average refresh rate of 7.8125usec (commercial), To ensure all + * rows of all banks are properly refreshed, 8192 REFRESH commands must be + * issued every 64ms (commercial) + */ + + /* ((64 x 10(^-3))/8192) x133 x (10^6) */ + /* Set Refresh timer 7.8125 us */ + + putreg32( MPDDRC_RTR_COUNT(300), SAM_MPDDRC_RTR); + + /* OK now we are ready to work on the DDRSDR */ + /* Wait for end of calibration */ + + sam_sdram_delay(500); +} + +#endif /* CONFIG_SAMA5_DDRCS && !CONFIG_SAMA5_BOOT_SDRAM */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_spi.c b/nuttx/configs/sama5d3-xplained/src/sam_spi.c new file mode 100644 index 000000000..025d6ce4d --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_spi.c @@ -0,0 +1,216 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/up_spi.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <debug.h> +#include <errno.h> + +#include <nuttx/spi/spi.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "chip.h" +#include "sam_pio.h" +#include "sam_spi.h" +#include "sama5d3-xplained.h" + +#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1) + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SPI_DEBUG /* Define to enable debug */ +#undef SPI_VERBOSE /* Define to enable verbose debug */ + +#ifdef SPI_DEBUG +# define spidbg lldbg +# ifdef SPI_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# undef SPI_VERBOSE +# define spidbg(x...) +# define spivdbg(x...) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_spiinitialize + * + * Description: + * Called to configure SPI chip select PIO pins for the SAMA5D3-Xplained board. + * + ************************************************************************************/ + +void weak_function sam_spiinitialize(void) +{ +#ifdef CONFIG_SAMA5_SPI0 +#ifdef CONFIG_MTD_AT25 + /* The AT25 serial FLASH connects using NPCS0 */ + + sam_configpio(PIO_AT25_NPCS0); +#endif +#endif + +#ifdef CONFIG_SAMA5_SPI1 +#endif +} + +/**************************************************************************** + * Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They + * include: + * + * o sam_spi[0|1]select is a functions tomanage the board-specific chip selects + * o sam_spi[0|1]status and sam_spi[0|1]cmddata: Implementations of the status + * and cmddata methods of the SPI interface defined by struct spi_ops_ + * (see include/nuttx/spi/spi.h). All other methods including + * up_spiinitialize()) are provided by common SAM3/4 logic. + * + * To use this common SPI logic on your board: + * + * 1. Provide logic in sam_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in your board- + * specific logic. These functions will perform chip selection and + * status operations using PIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * sam_spi[0|1]cmddata() functions in your board-specific logic. This + * function will perform cmd/data selection operations using PIOs in + * the way your board is configured. + * 3. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_spi[0|1]select + * + * Description: + * PIO chip select pins may be programmed by the board specific logic in + * one of two different ways. First, the pins may be programmed as SPI + * peripherals. In that case, the pins are completely controlled by the + * SPI driver. This method still needs to be provided, but it may be only + * a stub. + * + * An alternative way to program the PIO chip select pins is as a normal + * PIO output. In that case, the automatic control of the CS pins is + * bypassed and this function must provide control of the chip select. + * NOTE: In this case, the PIO output pin does *not* have to be the + * same as the NPCS pin normal associated with the chip select number. + * + * Input Parameters: + * devid - Identifies the (logical) device + * selected - TRUE:Select the device, FALSE:De-select the device + * + * Returned Values: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMA5_SPI0 +void sam_spi0select(enum spi_dev_e devid, bool selected) +{ +#ifdef CONFIG_MTD_AT25 + /* The AT25 serial FLASH connects using NPCS0 */ + + if (devid == SPIDEV_FLASH) + { + sam_piowrite(PIO_AT25_NPCS0, !selected); + } +#endif +} +#endif + +#ifdef CONFIG_SAMA5_SPI1 +void sam_spi1select(enum spi_dev_e devid, bool selected) +{ +} +#endif + +/**************************************************************************** + * Name: sam_spi[0|1]status + * + * Description: + * Return status information associated with the SPI device. + * + * Input Parameters: + * devid - Identifies the (logical) device + * + * Returned Values: + * Bit-encoded SPI status (see include/nuttx/spi/spi.h. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMA5_SPI0 +uint8_t sam_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_SAMA5_SPI0 +uint8_t sam_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_SAMA5_SPI0 || CONFIG_SAMA5_SPI1 */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_usb.c b/nuttx/configs/sama5d3-xplained/src/sam_usb.c new file mode 100644 index 000000000..089032431 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_usb.c @@ -0,0 +1,530 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/sam_usb.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <sched.h> +#include <errno.h> +#include <assert.h> +#include <debug.h> + +#include <nuttx/usb/usbdev.h> +#include <nuttx/usb/usbhost.h> +#include <nuttx/usb/usbdev_trace.h> + +#include "up_arch.h" +#include "sam_pio.h" +#include "sam_usbhost.h" +#include "chip/sam_ohci.h" +#include "sama5d3-xplained.h" + +#if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# define CONFIG_USBHOST_STACKSIZE 1024 +#endif + +#ifdef HAVE_USBDEV +# undef CONFIG_SAMA5_UHPHS_RHPORT1 +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ +/* Retained device driver handles */ + +#ifdef CONFIG_SAMA5_OHCI +static struct usbhost_connection_s *g_ohciconn; +#endif +#ifdef CONFIG_SAMA5_EHCI +static struct usbhost_connection_s *g_ehciconn; +#endif + +/* Overcurrent interrupt handler */ + +#if defined(HAVE_USBHOST) && defined(CONFIG_SAMA5_PIOD_IRQ) +static xcpt_t g_ochandler; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected to either the OHCI or EHCI hub. + * + ************************************************************************************/ + +#if HAVE_USBHOST +#ifdef CONFIG_DEBUG_USB +static int usbhost_waiter(struct usbhost_connection_s *dev, const char *hcistr) +#else +static int usbhost_waiter(struct usbhost_connection_s *dev) +#endif +{ + bool connected[SAM_OHCI_NRHPORT] = {false, false, false}; + int rhpndx; + int ret; + + uvdbg("%s Waiter Running\n", hcistr); + for (;;) + { + /* Wait for the device to change state */ + + rhpndx = CONN_WAIT(dev, connected); + DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_OHCI_NRHPORT); + + connected[rhpndx] = !connected[rhpndx]; + + uvdbg("%s RHport%d %s\n", + hcistr, rhpndx + 1, connected[rhpndx] ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (connected[rhpndx]) + { + /* Yes.. enumerate the newly connected device */ + + ret = CONN_ENUMERATE(dev, rhpndx); + if (ret < 0) + { + uvdbg("%s RHport%d CONN_ENUMERATE failed: %d\n", hcistr, rhpndx+1, ret); + connected[rhpndx] = false; + } + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/************************************************************************************ + * Name: ohci_waiter + * + * Description: + * Wait for USB devices to be connected to the OHCI hub. + * + ************************************************************************************/ + +#ifdef CONFIG_SAMA5_OHCI +static int ohci_waiter(int argc, char *argv[]) +{ +#ifdef CONFIG_DEBUG_USB + return usbhost_waiter(g_ohciconn, "OHCI"); +#else + return usbhost_waiter(g_ohciconn); +#endif +} +#endif + +/************************************************************************************ + * Name: ehci_waiter + * + * Description: + * Wait for USB devices to be connected to the EHCI hub. + * + ************************************************************************************/ + +#ifdef CONFIG_SAMA5_EHCI +static int ehci_waiter(int argc, char *argv[]) +{ +#ifdef CONFIG_DEBUG_USB + return usbhost_waiter(g_ehciconn, "EHCI"); +#else + return usbhost_waiter(g_ehciconn); +#endif +} +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_usbinitialize + * + * Description: + * Called from sam_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the SAMA5D3-Xplained board. + * + * USB Ports + * The SAMA5D3 series-MB features three USB communication ports: + * + * 1. Port A Host High Speed (EHCI) and Full Speed (OHCI) multiplexed with + * USB Device High Speed Micro AB connector, J20 + * + * 2. Port B Host High Speed (EHCI) and Full Speed (OHCI) standard type A + * connector, J19 upper port + * + * 3. Port C Host Full Speed (OHCI) only standard type A connector, J19 + * lower port + * + * The two USB host ports (only) are equipped with 500-mA high-side power + * switch for self-powered and bus-powered applications. + * + * The USB device port A (J6) features a VBUS insert detection function. + * + * Port A + * + * PIO Signal Name Function + * ---- ----------- ------------------------------------------------------- + * PE9 VBUS_SENSE VBus detection + * + * Note: No VBus power switch enable on port A. I think that this limits + * this port to a device port or as a host port for self-powered devices + * only. + * + * Port B + * + * PIO Signal Name Function + * ---- ----------- ------------------------------------------------------- + * PE4 EN5V_USBB VBus power enable (via MN3 power switch). To the A1 + * pin of J19 Dual USB A connector + * + * Port C + * + * PIO Signal Name Function + * ---- ----------- ------------------------------------------------------- + * PE3 EN5V_USBC VBus power enable (via MN3 power switch). To the B1 + * pin of J19 Dual USB A connector + * + * Both Ports B and C + * + * PIO Signal Name Function + * ---- ----------- ------------------------------------------------------- + * PE5 OVCUR_USB Combined over-current indication from port A and B + * + * That offers a lot of flexibility. However, here we enable the ports only + * as follows: + * + * Port A -- USB device + * Port B -- EHCI host + * Port C -- OHCI host + * + ************************************************************************************/ + +void weak_function sam_usbinitialize(void) +{ +#ifdef HAVE_USBDEV + /* Configure Port A to support the USB device function */ + + sam_configpio(PIO_USBA_VBUS_SENSE); /* VBUS sense */ + + /* TODO: Configure an interrupt on VBUS sense */ +#endif + +#ifdef HAVE_USBHOST +#ifdef CONFIG_SAMA5_UHPHS_RHPORT1 + /* Configure Port A to support the USB OHCI/EHCI function */ + + sam_configpio(PIO_USBA_VBUS_ENABLE); /* VBUS enable, initially OFF */ +#endif + +#ifdef CONFIG_SAMA5_UHPHS_RHPORT2 + /* Configure Port B to support the USB OHCI/EHCI function */ + + sam_configpio(PIO_USBB_VBUS_ENABLE); /* VBUS enable, initially OFF */ +#endif + +#ifdef CONFIG_SAMA5_UHPHS_RHPORT3 + /* Configure Port C to support the USB OHCI/EHCI function */ + + sam_configpio(PIO_USBC_VBUS_ENABLE); /* VBUS enable, initially OFF */ +#endif + +#if defined(CONFIG_SAMA5_UHPHS_RHPORT2) || defined(CONFIG_SAMA5_UHPHS_RHPORT3) + /* Configure Port B/C VBUS overrcurrent detection */ + + sam_configpio(PIO_USBBC_VBUS_OVERCURRENT); /* VBUS overcurrent */ +#endif +#endif /* HAVE_USBHOST */ +} + +/*********************************************************************************** + * Name: sam_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ***********************************************************************************/ + +#if HAVE_USBHOST +int sam_usbhost_initialize(void) +{ + pid_t pid; + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about + * + * Register theUSB host Mass Storage Class: + */ + + ret = usbhost_storageinit(); + if (ret != OK) + { + udbg("ERROR: Failed to register the mass storage class: %d\n", ret); + } + + /* Register the USB host HID keyboard class driver */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + udbg("ERROR: Failed to register the KBD class\n"); + } + + /* Then get an instance of the USB host interface. */ + +#ifdef CONFIG_SAMA5_OHCI + /* Get an instance of the USB OHCI interface */ + + g_ohciconn = sam_ohci_initialize(0); + if (!g_ohciconn) + { + udbg("ERROR: sam_ohci_initialize failed\n"); + return -ENODEV; + } + + /* Start a thread to handle device connection. */ + + pid = TASK_CREATE("OHCI Monitor", CONFIG_USBHOST_DEFPRIO, CONFIG_USBHOST_STACKSIZE, + (main_t)ohci_waiter, (FAR char * const *)NULL); + if (pid < 0) + { + udbg("ERROR: Failed to create ohci_waiter task: %d\n", ret); + return -ENODEV; + } +#endif + +#ifdef CONFIG_SAMA5_EHCI + /* Get an instance of the USB EHCI interface */ + + g_ehciconn = sam_ehci_initialize(0); + if (!g_ehciconn) + { + udbg("ERROR: sam_ehci_initialize failed\n"); + return -ENODEV; + } + + /* Start a thread to handle device connection. */ + + pid = TASK_CREATE("EHCI Monitor", CONFIG_USBHOST_DEFPRIO, CONFIG_USBHOST_STACKSIZE, + (main_t)ehci_waiter, (FAR char * const *)NULL); + if (pid < 0) + { + udbg("ERROR: Failed to create ehci_waiter task: %d\n", ret); + return -ENODEV; + } +#endif + + return OK; +} +#endif + +/*********************************************************************************** + * Name: sam_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be provided by + * each platform that implements the OHCI or EHCI host interface + * + * Input Parameters: + * rhport - Selects root hub port to be powered host interface. See SAM_RHPORT_* + * definitions above. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ***********************************************************************************/ + +#if HAVE_USBHOST +void sam_usbhost_vbusdrive(int rhport, bool enable) +{ + pio_pinset_t pinset = 0; + + uvdbg("RHPort%d: enable=%d\n", rhport+1, enable); + + /* Pick the PIO configuration associated with the selected root hub port */ + + switch (rhport) + { + case SAM_RHPORT1: +#ifndef CONFIG_SAMA5_UHPHS_RHPORT1 + udbg("ERROR: RHPort1 is not available in this configuration\n"); + return; +#else + pinset = PIO_USBA_VBUS_ENABLE; + break; +#endif + + case SAM_RHPORT2: +#ifndef CONFIG_SAMA5_UHPHS_RHPORT2 + udbg("ERROR: RHPort2 is not available in this configuration\n"); + return; +#else + pinset = PIO_USBB_VBUS_ENABLE; + break; +#endif + + case SAM_RHPORT3: +#ifndef CONFIG_SAMA5_UHPHS_RHPORT3 + udbg("ERROR: RHPort3 is not available in this configuration\n"); + return; +#else + pinset = PIO_USBC_VBUS_ENABLE; + break; +#endif + + default: + udbg("ERROR: RHPort%d is not supported\n", rhport+1); + return; + } + + /* Then enable or disable VBUS power */ + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + sam_piowrite(pinset, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + sam_piowrite(pinset, true); + } +} +#endif + +/************************************************************************************ + * Name: sam_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition is + * detected on port B or C. + * + * REVISIT: Since this is a common signal, we will need to come up with some way + * to inform both EHCI and OHCI drivers when this error occurs. + * + * Input paramter: + * handler - New overcurrent interrupt handler + * + * Returned value: + * Old overcurrent interrupt handler + * + ************************************************************************************/ + +#if HAVE_USBHOST +xcpt_t sam_setup_overcurrent(xcpt_t handler) +{ +#if defined(CONFIG_SAMA5_PIOD_IRQ) && (defined(CONFIG_SAMA5_UHPHS_RHPORT2) || \ + defined(CONFIG_SAMA5_UHPHS_RHPORT3)) + + xcpt_t oldhandler; + irqstate_t flags; + + /* Disable interrupts until we are done. This guarantees that the + * following operations are atomic. + */ + + flags = irqsave(); + + /* Get the old button interrupt handler and save the new one */ + + oldhandler = g_ochandler; + g_ochandler = handler; + + /* Configure the interrupt */ + + sam_pioirq(IRQ_USBBC_VBUS_OVERCURRENT); + (void)irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler); + sam_pioirqenable(IRQ_USBBC_VBUS_OVERCURRENT); + + /* Return the old button handler (so that it can be restored) */ + + irqrestore(flags); + return oldhandler; + +#else + return NULL; + +#endif +} +#endif /* CONFIG_SAMA5_PIOD_IRQ ... */ + +/************************************************************************************ + * Name: sam_usbsuspend + * + * Description: + * Board logic must provide the sam_usbsuspend logic if the USBDEV driver is + * used. This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, etc. + * while the USB is suspended. + * + ************************************************************************************/ + +#ifdef CONFIG_USBDEV +void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + ulldbg("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_SAMA5_UHPHS || CONFIG_SAMA5_UDPHS */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_usbmsc.c b/nuttx/configs/sama5d3-xplained/src/sam_usbmsc.c new file mode 100644 index 000000000..79c4d6c42 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_usbmsc.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * configs/sama5d3-xplained/src/up_usbmsc.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Configure and register the SAM3U MMC/SD SDIO block driver. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdio.h> +#include <debug.h> +#include <errno.h> + +#include "sama5d3-xplained.h" + +#ifdef CONFIG_USBMSC + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef HAVE_AT25 +# error AT25 Serial FLASH not supported +#endif + +#ifndef CONFIG_SAMA5D3XPLAINED_AT25_FTL +# error AT25 FTL support required (CONFIG_SAMA5D3XPLAINED_AT25_FTL) +# undef HAVE_AT25 +#endif + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +#if CONFIG_SYSTEM_USBMSC_DEVMINOR1 != AT25_MINOR +# error Confusion in the assignment of minor device numbers +# undef HAVE_AT25 +#endif + +/* Debug ********************************************************************/ + +#ifdef CONFIG_CPP_HAVE_VARARGS +# ifdef CONFIG_DEBUG +# define message(...) lowsyslog(__VA_ARGS__) +# define msgflush() +# else +# define message(...) printf(__VA_ARGS__) +# define msgflush() fflush(stdout) +# endif +#else +# ifdef CONFIG_DEBUG +# define message lowsyslog +# define msgflush() +# else +# define message printf +# define msgflush() fflush(stdout) +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbmsc_archinitialize + * + * Description: + * Perform architecture specific initialization + * + ****************************************************************************/ + +int usbmsc_archinitialize(void) +{ + /* Initialize the AT25 MTD driver */ + +#ifdef HAVE_AT25 + int ret = sam_at25_automount(AT25_MINOR); + if (ret < 0) + { + message("ERROR: sam_at25_automount failed: %d\n", ret); + } + + return ret; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_USBMSC */ diff --git a/nuttx/configs/sama5d3-xplained/src/sam_userleds.c b/nuttx/configs/sama5d3-xplained/src/sam_userleds.c new file mode 100644 index 000000000..e9cfabbb1 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sam_userleds.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * configs/sama5d3-xplained/src/sam_userleds.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* There are two LEDs on the SAMA5D3 series-CM board that can be controlled + * by software. A blue LED is controlled via PIO pins. A red LED normally + * provides an indication that power is supplied to the board but can also + * be controlled via software. + * + * PE25. This blue LED is pulled high and is illuminated by pulling PE25 + * low. + * + * PE24. The red LED is also pulled high but is driven by a transistor so + * that it is illuminated when power is applied even if PE24 is not + * configured as an output. If PE24 is configured as an output, then the + * LCD is illuminated by a low output. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <debug.h> + +#include <arch/board/board.h> + +#include "sam_pio.h" +#include "sama5d3-xplained.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG + * with CONFIG_DEBUG_VERBOSE too) + */ + +#ifdef CONFIG_DEBUG_LEDS +# define leddbg lldbg +# define ledvdbg llvdbg +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_ledinit + ****************************************************************************/ + +void sam_ledinit(void) +{ + /* Configure LED PIOs for output */ + + sam_configpio(PIO_BLUE); + sam_configpio(PIO_RED); +} + +/**************************************************************************** + * Name: sam_setled + ****************************************************************************/ + +void sam_setled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_BLUE) + { + /* Low illuminates */ + + ledcfg = PIO_BLUE; + ledon = !ledon; + } + else if (led == BOARD_RED) + { + /* High illuminates */ + + ledcfg = PIO_RED; + } + else + { + return; + } + + sam_piowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: sam_setleds + ****************************************************************************/ + +void sam_setleds(uint8_t ledset) +{ + bool ledon; + + /* Low illuminates */ + + ledon = ((ledset & BOARD_BLUE_BIT) == 0); + sam_piowrite(PIO_BLUE, ledon); + + /* High illuminates */ + + ledon = ((ledset & BOARD_RED_BIT) != 0); + sam_piowrite(PIO_RED, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/nuttx/configs/sama5d3-xplained/src/sama5d3-xplained.h b/nuttx/configs/sama5d3-xplained/src/sama5d3-xplained.h new file mode 100644 index 000000000..1d51ae7c0 --- /dev/null +++ b/nuttx/configs/sama5d3-xplained/src/sama5d3-xplained.h @@ -0,0 +1,676 @@ +/************************************************************************************ + * configs/sama5d3-xplained/src/sama5d3-xplained.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAMA5D3_XPLAINED_SRC_SAMA5D3_XPLAINED_H +#define __CONFIGS_SAMA5D3_XPLAINED_SRC_SAMA5D3_XPLAINED_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/compiler.h> + +#include <stdint.h> + +#include <arch/irq.h> +#include <nuttx/irq.h> + +#include "chip/sam_pinmap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ************************************************************/ + +#define HAVE_HSMCI 1 +#define HAVE_AT25 1 +#define HAVE_NAND 1 +#define HAVE_USBHOST 1 +#define HAVE_USBDEV 1 +#define HAVE_USBMONITOR 1 +#define HAVE_NETWORK 1 + +/* HSMCI */ +/* Can't support MMC/SD if the card interface(s) are not enable */ + +#if !defined(CONFIG_SAMA5_HSMCI0) && !defined(CONFIG_SAMA5_HSMCI1) +# undef HAVE_HSMCI +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#if defined(HAVE_HSMCI) && defined(CONFIG_DISABLE_MOUNTPOINT) +# warning Mountpoints disabled. No MMC/SD support +# undef HAVE_HSMCI +#endif + +/* We need PIO interrupts on PIOD to support card detect interrupts */ + +#if defined(HAVE_HSMCI) && !defined(CONFIG_SAMA5_PIOD_IRQ) +# warning PIOD interrupts not enabled. No MMC/SD support. +# undef HAVE_HSMCI +#endif + +/* NAND FLASH */ +/* Can't support the NAND device if NAND flash is not configured on EBI CS3 */ + +#ifndef CONFIG_SAMA5_EBICS3_NAND +# undef HAVE_NAND +#endif + +/* Can't support NAND features if mountpoints are disabled or if we were not + * asked to mount the NAND part + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_SAMA5D3XPLAINED_NAND_AUTOMOUNT) +# undef HAVE_NAND +#endif + +/* Can't support NAND if the MTD feature is not enabled */ + +#if !defined(CONFIG_MTD) || !defined(CONFIG_MTD_NAND) +# undef HAVE_NAND +#endif + +/* If we are going to mount the NAND, then they user must also have told + * us what to do with it by setting one of CONFIG_SAMA5D3XPLAINED_NAND_FTL or + * CONFIG_SAMA5D3XPLAINED_NAND_NXFFS. + */ + +#ifndef CONFIG_MTD +# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS +# undef CONFIG_SAMA5D3XPLAINED_NAND_FTL +#endif + +#if !defined(CONFIG_FS_NXFFS) || !defined(CONFIG_NXFFS_NAND) +# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS +#endif + +#if !defined(CONFIG_SAMA5D3XPLAINED_NAND_FTL) && !defined(CONFIG_SAMA5D3XPLAINED_NAND_NXFFS) +# undef HAVE_NAND +#endif + +#if defined(CONFIG_SAMA5D3XPLAINED_NAND_FTL) && defined(CONFIG_SAMA5D3XPLAINED_NAND_NXFFS) +# warning Both CONFIG_SAMA5D3XPLAINED_NAND_FTL and CONFIG_SAMA5D3XPLAINED_NAND_NXFFS are set +# warning Ignoring CONFIG_SAMA5D3XPLAINED_NAND_NXFFS +# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS +#endif + +/* AT25 Serial FLASH */ +/* Can't support the AT25 device if it SPI0 or AT25 support are not enabled */ + +#if !defined(CONFIG_SAMA5_SPI0) || !defined(CONFIG_MTD_AT25) +# undef HAVE_AT25 +#endif + +/* Can't support AT25 features if mountpoints are disabled or if we were not + * asked to mount the AT25 part + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_SAMA5D3XPLAINED_AT25_AUTOMOUNT) +# undef HAVE_AT25 +#endif + +/* If we are going to mount the AT25, then they user must also have told + * us what to do with it by setting one of these. + */ + +#ifndef CONFIG_FS_NXFFS +# undef CONFIG_SAMA5D3XPLAINED_AT25_NXFFS +#endif + +#if !defined(CONFIG_SAMA5D3XPLAINED_AT25_FTL) && !defined(CONFIG_SAMA5D3XPLAINED_AT25_NXFFS) +# undef HAVE_AT25 +#endif + +#if defined(CONFIG_SAMA5D3XPLAINED_AT25_FTL) && defined(CONFIG_SAMA5D3XPLAINED_AT25_NXFFS) +# warning Both CONFIG_SAMA5D3XPLAINED_AT25_FTL and CONFIG_SAMA5D3XPLAINED_AT25_NXFFS are set +# warning Ignoring CONFIG_SAMA5D3XPLAINED_AT25_NXFFS +# undef CONFIG_SAMA5D3XPLAINED_AT25_NXFFS +#endif + +/* Assign minor device numbers. For example, if we also use MINOR number 0 + * for the AT25, it should appear as /dev/mtdblock0 + */ + +#define _NAND_MINOR 0 + +#ifdef HAVE_NAND +# define NAND_MINOR _NAND_MINOR +# define _AT25_MINOR (_NAND_MINOR+1) +#else +# define _AT25_MINOR _NAND_MINOR +#endif + +#ifdef HAVE_AT25 +# define AT25_MINOR _AT25_MINOR +#endif + +/* MMC/SD minor numbers: The NSH device minor extended is extended to support + * two devices. If CONFIG_NSH_MMCSDMINOR is zero, these will be: /dev/mmcsd0 + * and /dev/mmcsd1. + */ + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +#ifdef HAVE_HSMCI + +# define HSMCI0_SLOTNO 0 +# define HSMCI1_SLOTNO 1 + +# ifdef CONFIG_SAMA5_HSMCI0 +# define HSMCI0_MINOR CONFIG_NSH_MMCSDMINOR +# define HSMCI1_MINOR (CONFIG_NSH_MMCSDMINOR+1) +# else +# define HSMCI1_MINOR CONFIG_NSH_MMCSDMINOR +# endif +#else +#endif + +/* USB Host / USB Device */ +/* Either CONFIG_SAMA5_UHPHS or CONFIG_SAMA5_UDPHS must be defined, or there is + * no USB of any kind. + */ + +#if !defined(CONFIG_SAMA5_UHPHS) +# undef CONFIG_SAMA5_OHCI +# undef CONFIG_SAMA5_EHCI +#endif + +#if !defined(CONFIG_SAMA5_UDPHS) +# undef HAVE_USBDEV +#endif + +/* CONFIG_USBDEV and CONFIG_USBHOST must also be defined */ + +#if !defined(CONFIG_USBDEV) +# undef HAVE_USBDEV +#endif + +#if defined(CONFIG_USBHOST) +# if !defined(CONFIG_SAMA5_OHCI) && !defined(CONFIG_SAMA5_EHCI) +# warning CONFIG_USBHOST is defined, but neither CONFIG_SAMA5_OHCI nor CONFIG_SAMA5_EHCI are defined +# endif +#else +# undef CONFIG_SAMA5_OHCI +# undef CONFIG_SAMA5_EHCI +#endif + +#if !defined(CONFIG_SAMA5_OHCI) && !defined(CONFIG_SAMA5_EHCI) +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_SYSTEM_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +/* Networking */ + +#if !defined(CONFIG_NET) || (!defined(CONFIG_SAMA5_EMAC) && !defined(CONFIG_SAMA5_GMAC)) +# undef HAVE_NETWORK +#endif + +/* LEDs *****************************************************************************/ +/* There are two LEDs on the SAMA5D3 series-CM board that can be controlled + * by software. A blue LED is controlled via PIO pins. A red LED normally + * provides an indication that power is supplied to the board but can also + * be controlled via software. + * + * PE23. This blue LED is pulled high and is illuminated by pulling PE23 + * low. + * + * PE24. The red LED is also pulled high but is driven by a transistor so + * that it is illuminated when power is applied even if PE24 is not + * configured as an output. If PE24 is configured as an output, then the + * LCD is illuminated by a high output. + */ + +#define PIO_BLUE (PIO_OUTPUT | PIO_CFG_PULLUP | PIO_OUTPUT_SET | \ + PIO_PORT_PIOE | PIO_PIN23) +#define PIO_RED (PIO_OUTPUT | PIO_CFG_PULLUP | PIO_OUTPUT_CLEAR | \ + PIO_PORT_PIOE | PIO_PIN24) + +/* Buttons **************************************************************************/ +/* There are five push button switches on the SAMA5D3-Xplained base board: + * + * 1. One Reset, board reset (BP1) + * 2. One Wake up, push button to bring the processor out of low power mode + * (BP2) + * 3. One User momentary Push Button + * 4. One Disable CS Push Button + * + * Only the user push button is controllable by software (labeled + * "PB_USER1" on the board): + * + * - PE29. Pressing the switch connects PE29 to ground. Therefore, PE29 + * must be pulled high internally. When the button is pressed the SAMA5 + * will sense "0" is on PE29. + */ + +#define PIO_USER (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \ + PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN29) +#define IRQ_USER SAM_IRQ_PE29 + +/* HSMCI Card Slots *****************************************************************/ +/* The SAMA5D3-Xplained provides a two SD memory card slots: (1) a full size SD card + * slot (J10), and (2) a microSD memory card slot (J11). + * + * The full size SD card slot connects via HSMCI0. The card detect discrete + * is available on PD17 (pulled high). The write protect descrete is tied to + * ground (via PP6) and not available to software. The slot supports 8-bit + * wide transfer mode, but the NuttX driver currently uses only the 4-bit + * wide transfer mode + * + * PD17 MCI0_CD + * PD1 MCI0_DA0 + * PD2 MCI0_DA1 + * PD3 MCI0_DA2 + * PD4 MCI0_DA3 + * PD5 MCI0_DA4 + * PD6 MCI0_DA5 + * PD7 MCI0_DA6 + * PD8 MCI0_DA7 + * PD9 MCI0_CK + * PD0 MCI0_CDA + */ + +#define PIO_MCI0_CD (PIO_INPUT | PIO_CFG_DEFAULT | PIO_CFG_DEGLITCH | \ + PIO_INT_BOTHEDGES | PIO_PORT_PIOD | PIO_PIN17) +#define IRQ_MCI0_CD SAM_IRQ_PD17 + +/* The microSD connects vi HSMCI1. The card detect discrete is available on + * PBD8 (pulled high): + * + * PD18 MCI1_CD + * PB20 MCI1_DA0 + * PB21 MCI1_DA1 + * PB22 MCI1_DA2 + * PB23 MCI1_DA3 + * PB24 MCI1_CK + * PB19 MCI1_CDA + */ + +#define PIO_MCI1_CD (PIO_INPUT | PIO_CFG_DEFAULT | PIO_CFG_DEGLITCH | \ + PIO_INT_BOTHEDGES | PIO_PORT_PIOD | PIO_PIN18) +#define IRQ_MCI1_CD SAM_IRQ_PD18 + +/* USB Ports ************************************************************************/ +/* The SAMA5D3 series-MB features three USB communication ports: + * + * 1. Port A Host High Speed (EHCI) and Full Speed (OHCI) multiplexed with + * USB Device High Speed Micro AB connector, J6 + * + * 2. Port B Host High Speed (EHCI) and Full Speed (OHCI) standard type A + * connector, J7 upper port + * + * 3. Port C Host Full Speed (OHCI) only standard type A connector, J7 + * lower port + * + * The two USB host ports (only) are equipped with 500-mA high-side power + * switch for self-powered and bus-powered applications. + * + * The USB device port A (J6) features a VBUS insert detection function. + * + * + * Port A + * + * PIO Signal Name Function + * ---- ----------- ------------------------------------------------------- + * PE9 VBUS_SENSE VBus detection + * + * Note: No VBus power switch enable on port A. I think that this limits + * this port to a device port or as a host port for self-powered devices + * only. + */ + +#define PIO_USBA_VBUS_SENSE \ + (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \ + PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN9) +#define IRQ_USBA_VBUS_SENSE \ + SAM_IRQ_PE9 + +/* Port B + * + * PIO Signal Name Function + * ---- ----------- ------------------------------------------------------- + * PE4 EN5V_USBB VBus power enable (via MN3 AIC1526 Dual USB High-Side + * Power Switch). To the A1 pin of J7 Dual USB A + * connector + */ + +#define PIO_USBB_VBUS_ENABLE \ + (PIO_OUTPUT | PIO_CFG_DEFAULT | PIO_OUTPUT_CLEAR | \ + PIO_PORT_PIOE | PIO_PIN4) + +/* Port C + * + * PIO Signal Name Function + * ---- ----------- ------------------------------------------------------- + * PE3 EN5V_USBC VBus power enable (via MN3 power switch). To the B1 + * pin of J7 Dual USB A connector + */ + +#define PIO_USBC_VBUS_ENABLE \ + (PIO_OUTPUT | PIO_CFG_DEFAULT | PIO_OUTPUT_CLEAR | \ + PIO_PORT_PIOE | PIO_PIN3) + +/* Both Ports B and C + * + * PIO Signal Name Function + * ---- ----------- ------------------------------------------------------- + * PE5 OVCUR_USB Combined over-current indication from port A and B + */ + +#define PIO_USBBC_VBUS_OVERCURRENT \ + (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \ + PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN5) +#define IRQ_USBBC_VBUS_OVERCURRENT \ + SAM_IRQ_PE5 + +/* Ethernet */ + +#ifdef CONFIG_SAMA4_EMAC + /* ETH1: Ethernet 10/100 (EMAC) Port + * + * The main board contains a MICREL PHY device (KSZ8051) operating at 10/100 Mbps. + * The board supports MII and RMII interface modes. + * + * The two independent PHY devices embedded on CM and MB boards are connected to + * independent RJ-45 connectors with built-in magnetic and status LEDs. + * + * At the De-Assertion of Reset: + * PHY ADD[2:0]:001 + * CONFIG[2:0]:001,Mode:RMII + * Duplex Mode:Half Duplex + * Isolate Mode:Disable + * Speed Mode:100Mbps + * Nway Auto-Negotiation:Enable + * + * The KSZ8051 PHY interrtup is available on PE30 INT_ETH1 + */ + +#define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \ + PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN30) +#define IRQ_INT_ETH1 SAM_IRQ_PE30 + +#endif + +#ifdef CONFIG_SAMA4_GMAC + /* ETH0: Tri-Speed Ethernet PHY + * + * The SAMA5D3 series-CM board is equipped with a MICREL PHY devices (MICREL + * KSZ9021/31) operating at 10/100/1000 Mbps. The board supports RGMII interface + * mode. The Ethernet interface consists of 4 pairs of low voltage differential + * pair signals designated from GRX± and GTx± plus control signals for link + * activity indicators. These signals can be used to connect to a 10/100/1000 + * BaseT RJ45 connector integrated on the main board. + * + * The KSZ9021/31 interrupt is available on PB35 INT_GETH0 + */ + +#define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \ + PIO_INT_BOTHEDGES | PIO_PORT_PIOB | PIO_PIN25) +#define IRQ_INT_ETH0 SAM_IRQ_PB25 + +#endif + +/* SPI Chip Selects *****************************************************************/ +/* Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an + * Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash. The SPI + * connection is as follows: + * + * AT25DF321A SAMA5 + * --------------- ----------------------------------------------- + * SI PD11 SPI0_MOSI + * SO PD10 SPI0_MIS0 + * SCK PD12 SPI0_SPCK + * /CS PD13 via NL17SZ126 if JP1 is closed (See below) + * + * JP1 and JP2 seem to related to /CS on the Ronetix board, but the usage is + * less clear. For the Embest module, JP1 must be closed to connect /CS to + * PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may + * not be populated?). I think closing JP1 is correct in either case. + */ + +#define PIO_AT25_NPCS0 (PIO_OUTPUT | PIO_CFG_PULLUP | PIO_OUTPUT_SET | \ + PIO_PORT_PIOD | PIO_PIN13) +#define AT25_PORT SPI0_CS0 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_spiinitialize + * + * Description: + * Called to configure SPI chip select PIO pins for the SAMA5D3-Xplained board. + * + ************************************************************************************/ + +#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1) +void weak_function sam_spiinitialize(void); +#endif + +/************************************************************************************ + * Name: board_sdram_config + * + * Description: + * Configures DDR2 (MT47H128M16RT 128MB or, optionally, MT47H64M16HR) + * + * Per the SAMA5D3-Xplained User guide: "Two SDRAM/DDR2 used as main system memory. + * MT47H128M16 - 2 Gb - 16 Meg x 16 x 8 banks, the board provides up to 2 Gb on- + * board, soldered DDR2 SDRAM. The memory bus is 32 bits wide and operates with + * up to 166 MHz." + * + * From the Atmel Code Example: + * MT47H64M16HR : 8 Meg x 16 x 8 banks + * Refresh count: 8K + * Row address: A[12:0] (8K) + * Column address A[9:0] (1K) + * Bank address BA[2:0] a(24,25) (8) + * + * This logic was taken from Atmel sample code for the SAMA5D3-Xplained. + * + * Input Parameters: + * devtype - Either DDRAM_MT47H128M16RT or DDRAM_MT47H64M16HR + * + * Assumptions: + * The DDR memory regions is configured as strongly ordered memory. When we + * complete initialization of SDRAM and it is ready for use, we will make DRAM + * into normal memory. + * + ************************************************************************************/ + +#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM) +void sam_sdram_config(void); +#else +# define board_sdram_config(t) +#endif + +/**************************************************************************** + * Name: sam_nand_automount + * + * Description: + * Initialize and configure the NAND on CS3 + * + ****************************************************************************/ + +#ifdef HAVE_NAND +int sam_nand_automount(int minor); +#endif + +/**************************************************************************** + * Name: sam_at25_automount + * + * Description: + * Initialize and configure the AT25 serial FLASH + * + ****************************************************************************/ + +#ifdef HAVE_AT25 +int sam_at25_automount(int minor); +#endif + +/**************************************************************************** + * Name: sam_hsmci_initialize + * + * Description: + * Initialize and configure one HSMCI slot + * + ****************************************************************************/ + +#ifdef HAVE_HSMCI +int sam_hsmci_initialize(int slotno, int minor); +#endif + +/************************************************************************************ + * Name: sam_cardinserted + * + * Description: + * Check if a card is inserted into the selected HSMCI slot + * + ************************************************************************************/ + +#ifdef HAVE_HSMCI +bool sam_cardinserted(int slotno); +#endif + +/************************************************************************************ + * Name: sam_writeprotected + * + * Description: + * Check if the card in the MMCSD slot is write protected + * + ************************************************************************************/ + +#ifdef HAVE_HSMCI +bool sam_writeprotected(int slotno); +#endif + +/************************************************************************************ + * Name: sam_usbinitialize + * + * Description: + * Called from sam_usbinitialize very early in inialization to setup USB-related + * PIO pins for the SAMA5D3-Xplained board. + * + ************************************************************************************/ + +#if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS) +void weak_function sam_usbinitialize(void); +#endif + +/**************************************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host functionality. This function will + * start a thread that will monitor for device connection/disconnection events. + * + ****************************************************************************************************/ + +#ifdef HAVE_USBHOST +int sam_usbhost_initialize(void); +#endif + +/************************************************************************************ + * Name: sam_netinitialize + * + * Description: + * Configure board resources to support networking. + * + ************************************************************************************/ + +#ifdef HAVE_NETWORK +void weak_function sam_netinitialize(void); +#endif + +/************************************************************************************ + * Name: board_led_initialize + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_led_initialize(void); +#endif + +/************************************************************************************ + * Name: nsh_archinitialize + * + * Description: + * Perform architecture specific initialization for NSH. + * + * CONFIG_NSH_ARCHINIT=y : + * Called from the NSH library + * + * CONFIG_BOARD_INITIALIZE=y, CONFIG_NSH_LIBRARY=y, && CONFIG_NSH_ARCHINIT=n : + * Called from board_initialize(). + * + ************************************************************************************/ + +#ifdef CONFIG_NSH_LIBRARY +int nsh_archinitialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_SAMA5D3_XPLAINED_SRC_SAMA5D3_XPLAINED_H */ + |