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| author | Gregory Nutt <gnutt@nuttx.org> | 2014-04-04 16:05:20 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-04-04 16:05:20 -0600 |
| commit | b35415bb17a73370a2052d619ce1d2c49332107f (patch) | |
| tree | a5e802d20a9d46085ffeba45e2a072cbf7097b46 | |
| parent | 0dadcfd847b9cf69eec96286320c106e59b6b47e (diff) | |
| download | nuttx-b35415bb17a73370a2052d619ce1d2c49332107f.tar.gz nuttx-b35415bb17a73370a2052d619ce1d2c49332107f.tar.bz2 nuttx-b35415bb17a73370a2052d619ce1d2c49332107f.zip | |
SAMA5: Don't use MMU PMD bufferable bit to try to control write-through vs write-back. It does not work that way
| -rw-r--r-- | nuttx/ChangeLog | 3 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/armv7-a/mmu.h | 11 |
2 files changed, 8 insertions, 6 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 7d192fb53..6b5db2577 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -7142,4 +7142,7 @@ only USB device tracing is enabled (2014-4-4). * Documentation/UsbTrace.html: Add some discussion of the USB monitor (2014-4-4). + * nuttx/arch/arm/src/armv7-a/mmu.h: Bufferable bit did not do what + I thought it was going to do. Result was the NOR FLASH accesses + were very slow (2014-4-3). diff --git a/nuttx/arch/arm/src/armv7-a/mmu.h b/nuttx/arch/arm/src/armv7-a/mmu.h index 334843286..1112ec8b1 100644 --- a/nuttx/arch/arm/src/armv7-a/mmu.h +++ b/nuttx/arch/arm/src/armv7-a/mmu.h @@ -2,7 +2,7 @@ * arch/arm/src/armv7-a/mmu.h * CP15 MMU register definitions * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * References: @@ -296,7 +296,7 @@ #define PMD_SECT_PXN (1 << 0) /* Bit 0: Privileged execute-never bit */ /* Bits 0-1: Type of mapping */ #define PMD_SECT_B (1 << 2) /* Bit 2: Bufferable bit */ -#define PMD_SECT_C (1 << 3) /* Bit 3: Cacheable bit*/ +#define PMD_SECT_C (1 << 3) /* Bit 3: Cacheable bit */ #define PMD_SECT_XN (1 << 4) /* Bit 4: Execute-never bit */ #define PMD_SECT_DOM_SHIFT (5) /* Bits 5-8: Domain */ #define PMD_SECT_DOM_MASK (15 << PMD_SECT_DOM_SHIFT) @@ -502,8 +502,7 @@ #define PMD_STRONGLY_ORDERED (0) #define PMD_DEVICE (PMD_SECT_B) -#define PMD_WRITE_THROUGH (PMD_SECT_C) -#define PMD_WRITE_BACK (PMD_SECT_B | PMD_SECT_C) +#define PM_CACHEABLE (PMD_SECT_B | PMD_SECT_C) #define PTE_STRONGLY_ORDER (0) #define PTE_DEVICE (PTE_B) @@ -515,9 +514,9 @@ * REVISIT: Here we expect all threads to be running at PL1 */ -#define MMU_ROMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_R1 | PMD_WRITE_THROUGH | \ +#define MMU_ROMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_R1 | PM_CACHEABLE | \ PMD_SECT_DOM(0)) -#define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_WRITE_BACK | \ +#define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PM_CACHEABLE | \ PMD_SECT_DOM(0)) #define MMU_IOFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_DEVICE | \ PMD_SECT_DOM(0) | PMD_SECT_XN) |