SAMD20: Add NVMCTRL register definition header file. Also empty framework for clock configuration

6 files changed, 475 insertions, 3 deletions

diff --git a/nuttx/arch/arm/src/samd/Make.defs b/nuttx/arch/arm/src/samd/Make.defs
index acb5638fc..baac8f4a2 100644
--- a/nuttx/arch/arm/src/samd/Make.defs
+++ b/nuttx/arch/arm/src/samd/Make.defs
@@ -68,7 +68,8 @@ CMN_CSRCS += up_dumpnvic.c
 endif
 
 CHIP_ASRCS  = 
-CHIP_CSRCS  = sam_idle.c sam_irq.c sam_port.c sam_start.c sam_timerisr.c
+CHIP_CSRCS  = sam_clockconfig.c sam_idle.c sam_irq.c sam_port.c sam_start.c
+CHIP_CSRCS += sam_timerisr.c
 
 ifeq ($(CONFIG_NUTTX_KERNEL),y)
 CHIP_CSRCS += sam_userspace.c
diff --git a/nuttx/arch/arm/src/samd/chip/sam_gclk.h b/nuttx/arch/arm/src/samd/chip/sam_gclk.h
index 075e00d05..ded483ca8 100644
--- a/nuttx/arch/arm/src/samd/chip/sam_gclk.h
+++ b/nuttx/arch/arm/src/samd/chip/sam_gclk.h
@@ -76,10 +76,10 @@
 /* Generic clock control register */
 
 #define GCLK_CLKCTRL_ID_SHIFT   (0)       /* Bits 0-5: Generic Clock Selection ID */
-#define GCLK_CLKCTRL_ID_SHIFT   (0x3f << GCLK_CLKCTRL_ID_SHIFT)
+#define GCLK_CLKCTRL_ID_MASK    (0x3f << GCLK_CLKCTRL_ID_SHIFT)
 #  define GCLK_CLKCTRL_ID(n)    ((n) << GCLK_CLKCTRL_ID_SHIFT)
 #define GCLK_CLKCTRL_GEN_SHIFT  (8)       /* Bits 8-11: Generic Clock Generator */
-#define GCLK_CLKCTRL_GEN_SHIFT  (15 << GCLK_CLKCTRL_GEN_SHIFT)
+#define GCLK_CLKCTRL_GEN_MASK   (15 << GCLK_CLKCTRL_GEN_SHIFT)
 #  define GCLK_CLKCTRL_GEN(n)   ((n) << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator n */
 #  define GCLK_CLKCTRL_GEN0     (0 << GCLK_CLKCTRL_GEN_SHIFT)   /* Generic clock generator 0 */
 #  define GCLK_CLKCTRL_GEN1     (1 << GCLK_CLKCTRL_GEN_SHIFT)   /* Generic clock generator 1 */
diff --git a/nuttx/arch/arm/src/samd/chip/sam_nvmctrl.h b/nuttx/arch/arm/src/samd/chip/sam_nvmctrl.h
new file mode 100644
index 000000000..cc8f75a1b
--- /dev/null
+++ b/nuttx/arch/arm/src/samd/chip/sam_nvmctrl.h
@@ -0,0 +1,165 @@
+/********************************************************************************************
+ * arch/arm/src/samd/chip/sam_nvmctrl.h
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMD_CHIP_SAM_NVMCTRL_H
+#define __ARCH_ARM_SRC_SAMD_CHIP_SAM_NVMCTRL_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* NVMCTRL register offsets ********************************************************************/
+
+#define SAM_NVMCTRL_CTRLA_OFFSET     0x0000 /* Control A register */
+#define SAM_NVMCTRL_CTRLB_OFFSET     0x0004 /* Control B register */
+#define SAM_NVMCTRL_PARAM_OFFSET     0x0008 /* NVM parameter register */
+#define SAM_NVMCTRL_INTENCLR_OFFSET  0x000c /* Interrupt clear register */
+#define SAM_NVMCTRL_INTENSET_OFFSET  0x0010 /* Interrupt set register */
+#define SAM_NVMCTRL_INTFLAG_OFFSET   0x0014 /* Interface flags status and clear register */
+#define SAM_NVMCTRL_STATUS_OFFSET    0x0018 /* Status register */
+#define SAM_NVMCTRL_ADDR_OFFSET      0x001c /* Address register */
+#define SAM_NVMCTRL_LOCK_OFFSET      0x0020 /* Lock section register */
+
+/* NVMCTRL register addresses ******************************************************************/
+
+#define SAM_NVMCTRL_CTRLA            (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLA_OFFSET)
+#define SAM_NVMCTRL_CTRLB            (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLB_OFFSET)
+#define SAM_NVMCTRL_PARAM            (SAM_NVMCTRL_BASE+SAM_NVMCTRL_PARAM_OFFSET)
+#define SAM_NVMCTRL_INTENCLR         (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTENCLR_OFFSET)
+#define SAM_NVMCTRL_INTENSET         (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTENSET_OFFSET)
+#define SAM_NVMCTRL_INTFLAG          (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTFLAG_OFFSET)
+#define SAM_NVMCTRL_STATUS           (SAM_NVMCTRL_BASE+SAM_NVMCTRL_STATUS_OFFSET)
+#define SAM_NVMCTRL_ADDR             (SAM_NVMCTRL_BASE+SAM_NVMCTRL_ADDR_OFFSET)
+#define SAM_NVMCTRL_LOCK             (SAM_NVMCTRL_BASE+SAM_NVMCTRL_LOCK_OFFSET)
+
+/* NVMCTRL register bit definitions ************************************************************/
+
+/* Control A register */
+
+#define NVMCTRL_CTRLA_CMD_SHIFT      (0)       /* Bits 0-6: Command */
+#define NVMCTRL_CTRLA_CMD_MASK       (0x7f << NVMCTRL_CTRLA_CMD_SHIFT)
+#  define NVMCTRL_CTRLA_CMD_ER       (0x02 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Row */
+#  define NVMCTRL_CTRLA_CMD_WP       (0x04 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Page */
+#  define NVMCTRL_CTRLA_CMD_EAR      (0x05 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Auxiliary Row */
+#  define NVMCTRL_CTRLA_CMD_WAP      (0x06 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Auxiliary Page */
+#  define NVMCTRL_CTRLA_CMD_LR       (0x40 << NVMCTRL_CTRLA_CMD_SHIFT) /* Lock Region */
+#  define NVMCTRL_CTRLA_CMD_UR       (0x41 << NVMCTRL_CTRLA_CMD_SHIFT) /* Unlock Region */
+#  define NVMCTRL_CTRLA_CMD_SPRM     (0x42 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set power reduction mode */
+#  define NVMCTRL_CTRLA_CMD_CPRM     (0x43 << NVMCTRL_CTRLA_CMD_SHIFT) /* Clear power reduction mode */
+#  define NVMCTRL_CTRLA_CMD_PBC      (0x44 << NVMCTRL_CTRLA_CMD_SHIFT) /* Page Buffer Clear */
+#  define NVMCTRL_CTRLA_CMD_SSB      (0x45 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set Security Bit */
+#  define NVMCTRL_CTRLA_CMD_INVALL   (0x46 << NVMCTRL_CTRLA_CMD_SHIFT) /* Invalidate all cache lines */
+#define NVMCTRL_CTRLA_CMDEX_SHIFT    (8)       /* Bits 8-15: Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_MASK     (0xff << NVMCTRL_CTRLA_CMDEX_SHIFT)
+#  define NVMCTRL_CTRLA_CMDEX        (0xa5 << NVMCTRL_CTRLA_CMDEX_SHIFT)
+
+/* Control B register */
+
+#define NVMCTRL_CTRLB_RWS_SHIFT      (1)       /* Bits 1-4: NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_MASK       (15 << NVMCTRL_CTRLB_RWS_SHIFT)
+#  define NVMCTRL_CTRLB_RWS(n)       ((n) << NVMCTRL_CTRLB_RWS_SHIFT)
+#define NVMCTRL_CTRLB_MANW           (1 << 7)  /* Bit 7: Manual Write */
+#define NVMCTRL_CTRLB_SLEEPPRM_SHIFT (8)       /* Bits 8-9: Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_MASK  (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT)
+#  define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS    (0 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power on first access */
+#  define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT   (1 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power when exit sleep */
+#  define NVMCTRL_CTRLB_SLEEPPRM_DISABLED        (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Auto power reduction disabled */
+#define NVMCTRL_CTRLB_READMODE_SHIFT (16)      /* Bits 16-17: NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_MASK  (3 << NVMCTRL_CTRLB_READMODE_SHIFT)
+#  define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (0 << NVMCTRL_CTRLB_READMODE_SHIFT) /* No extra wait states on miss */
+#  define NVMCTRL_CTRLB_READMODE_LOW_POWER       (1 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Insert wait/reduce power */
+#  define NVMCTRL_CTRLB_READMODE_DETERMINISTIC       (2 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Same wait on all access */
+#define NVMCTRL_CTRLB_CACHEDIS       (1 << 18)  /* Bit 18: Cache Disable */
+
+/* NVM parameter register */
+
+#define NVMCTRL_PARAM_NVMP_SHIFT     (0)      /* Bits 0-15: NVM Pages */
+#define NVMCTRL_PARAM_NVMP_MASK      (0xffff << NVMCTRL_PARAM_NVMP_SHIFT)
+#  define NVMCTRL_PARAM_NVMP(n)      ((n) << NVMCTRL_PARAM_NVMP_SHIFT)
+#define NVMCTRL_PARAM_PSZ_SHIFT      (16)      /* Bits 16-18: Page Size */
+#define NVMCTRL_PARAM_PSZ_MASK       (7 << NVMCTRL_PARAM_PSZ_SHIFT)
+#  define NVMCTRL_PARAM_PSZ_8B       (0 << NVMCTRL_PARAM_PSZ_SHIFT) /* 8 bytes */
+#  define NVMCTRL_PARAM_PSZ_16B      (1 << NVMCTRL_PARAM_PSZ_SHIFT) /* 16 bytes */
+#  define NVMCTRL_PARAM_PSZ_32B      (2 << NVMCTRL_PARAM_PSZ_SHIFT) /* 32 bytes */
+#  define NVMCTRL_PARAM_PSZ_64B      (3 << NVMCTRL_PARAM_PSZ_SHIFT) /* 64 bytes */
+#  define NVMCTRL_PARAM_PSZ_128B     (4 << NVMCTRL_PARAM_PSZ_SHIFT) /* 128 bytes */
+#  define NVMCTRL_PARAM_PSZ_256B     (5 << NVMCTRL_PARAM_PSZ_SHIFT) /* 256 bytes */
+#  define NVMCTRL_PARAM_PSZ_512B     (6 << NVMCTRL_PARAM_PSZ_SHIFT) /* 512 bytes */
+#  define NVMCTRL_PARAM_PSZ_1KB      (7 << NVMCTRL_PARAM_PSZ_SHIFT) /* 1024 bytes */
+
+/* Interrupt clear register */
+/* Interrupt set register */
+/* Interface flags status and clear register */
+
+#define NVMCTRL_INT_READY            (1 << 0)  /* Bit 0: NVM Ready Interrupt */
+#define NVMCTRL_INT_ERROR            (1 << 1)  /* Bit 1: Error Interrupt */
+
+/* Status register */
+
+#define NVMCTRL_STATUS_PRM           (1 << 0)  /* Bit 0: Power Reduction Mode */
+#define NVMCTRL_STATUS_LOAD          (1 << 1)  /* Bit 1: NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_PROGE         (1 << 2)  /* Bit 2: Programming Error Status */
+#define NVMCTRL_STATUS_LOCKE         (1 << 3)  /* Bit 3: Lock Error Status */
+#define NVMCTRL_STATUS_NVME          (1 << 4)  /* Bit 4: NVM Error */
+#define NVMCTRL_STATUS_SB            (1 << 8)  /* Bit 8: Security Bit Status */
+
+/* Address register */
+
+#define NVMCTRL_ADDR_MASK (0x003fffff) /* Bits 0-21: NVM Address */
+
+/* Lock section register */
+
+#define NVMCTRL_LOCK_REGION(n)       (1 << (n)) /* Region n is locked */
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAMD_CHIP_SAM_NVMCTRL_H */
diff --git a/nuttx/arch/arm/src/samd/chip/sam_sysctrl.h b/nuttx/arch/arm/src/samd/chip/sam_sysctrl.h
index ee6c32e99..41c36059e 100644
--- a/nuttx/arch/arm/src/samd/chip/sam_sysctrl.h
+++ b/nuttx/arch/arm/src/samd/chip/sam_sysctrl.h
@@ -102,6 +102,8 @@
 #define SYSCTRL_INT_BOD33DET          (1 << 10) /* Bit 10: BOD33 detection interrupt */
 #define SYSCTRL_INT_B33SRDY           (1 << 11) /* Bit 11: BOD33 synchronization ready interrupt */
 
+#define SYSCTRL_INT_ALL               (0x00000fff)
+
 /* External multi-purpose crystal oscillator control register */
 
 #define SYSCTRL_XOSC_ENABLE           (1 << 1)  /* Bit 1:  Oscillator enable */
diff --git a/nuttx/arch/arm/src/samd/sam_clockconfig.c b/nuttx/arch/arm/src/samd/sam_clockconfig.c
new file mode 100644
index 000000000..165c44097
--- /dev/null
+++ b/nuttx/arch/arm/src/samd/sam_clockconfig.c
@@ -0,0 +1,300 @@
+/****************************************************************************
+ * arch/arm/src/samd/sam_clockconfig.c
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+
+#include "up_arch.h"
+
+#include "chip/sam_pm.h"
+#include "chip/sam_sysctrl.h"
+#include "chip/sam_gclk.h"
+#include "chip/sam_nvmctrl.h"
+
+#include <arch/board/board.h>
+
+#include "sam_clockconfig.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_flash_waitstates
+ *
+ * Description:
+ *   Set the FLASH wait states based on settings in the board.h header file
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void sam_flash_waitstates(void)
+{
+  uint32_t regval;
+
+  regval = getreg32(SAM_NVMCTRL_CTRLB);
+  regval &= ~NVMCTRL_CTRLB_RWS_MASK;
+  regval |= NVMCTRL_CTRLB_RWS(BOARD_FLASH_WAITSTATES);
+  putreg32(regval, SAM_NVMCTRL_CTRLB);
+}
+
+/****************************************************************************
+ * Name: sam_xosc_config
+ *
+ * Description:
+ *   Configure XOSC based on settings in the board.h header file
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SAMD_XOSC) || defined(BOARD_XOSC_ENABLE)
+static inline void sam_xosc_config(void)
+{
+#warning Missing logic
+}
+#else
+#  define sam_xosc_config()
+#endif
+
+/****************************************************************************
+ * Name: sam_xosc32k_config
+ *
+ * Description:
+ *   Configure XOSC32K based on settings in the board.h header file
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SAMD_XOSC32K) || defined(BOARD_XOSC32_ENABLE)
+static inline void sam_xosc32k_config(void)
+{
+#warning Missing logic
+}
+#else
+#  define sam_xosc32k_config()
+#endif
+
+/****************************************************************************
+ * Name: sam_osc32k_config
+ *
+ * Description:
+ *   Configure OSC32K based on settings in the board.h header file
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SAMD_OSC32K) || defined(BOARD_OSC32_ENABLE)
+static inline void sam_osc32k_config(void)
+{
+#warning Missing logic
+}
+#else
+#  define sam_osc32k_config()
+#endif
+
+/****************************************************************************
+ * Name: sam_dfll_config
+ *
+ * Description:
+ *   Configure the DFLL based on settings in the board.h header file
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SAMD_DFLL) || defined(BOARD_DFLL_ENABLE)
+static inline void sam_dfll_config(void)
+{
+#warning Missing logic
+}
+#else
+#  define sam_dfll_config()
+#endif
+
+/****************************************************************************
+ * Name: sam_osc8m_config
+ *
+ * Description:
+ *   Configure OSC8M based on settings in the board.h header file
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void sam_osc8m_config(void)
+{
+#warning Missing logic
+}
+
+/****************************************************************************
+ * Name: sam_gclk_config
+ *
+ * Description:
+ *   Configure GCLK(s) based on settings in the board.h header file
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SAMD_GCLK) || defined(BOARD_GCLK_ENABLE)
+static inline void sam_gclk_config(void)
+{
+#warning Missing logic
+}
+#else
+#  define sam_gclk_config()
+#endif
+
+/****************************************************************************
+ * Name: sam_dividers
+ *
+ * Description:
+ *   Setup PM main clock dividers to generate CPU, AHB, and APB clocks.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void sam_dividers(void)
+{
+#warning Missing logic
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_clockconfig
+ *
+ * Description:
+ *   Called to establish the clock settings based on the values in board.h.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void sam_clockconfig(void)
+{
+  /* Clear pending interrupt status. */
+
+  putreg32(SYSCTRL_INT_ALL, SAM_SYSCTRL_INTFLAG);
+
+  /* Set FLASH wait states */
+
+  sam_flash_waitstates();
+
+  /* Configure XOSC */
+
+  sam_xosc_config();
+
+  /* Configure XOSC32K */
+
+  sam_xosc32k_config();
+
+  /* Configure OSCK32K */
+
+  sam_osc32k_config();
+
+  /* Configure DFLL */
+
+  sam_dfll_config();
+
+  /* Configure OSC8M */
+
+  sam_osc8m_config();
+
+  /* Configure GCLK(s) */
+
+  sam_gclk_config();
+
+  /* Set CPU and BUS clock dividers */
+
+  sam_dividers();
+}
diff --git a/nuttx/configs/samd20-xplained/include/board.h b/nuttx/configs/samd20-xplained/include/board.h
index 6bd10f224..6a57e7084 100644
--- a/nuttx/configs/samd20-xplained/include/board.h
+++ b/nuttx/configs/samd20-xplained/include/board.h
@@ -136,6 +136,10 @@
 #define BOARD_PBC_FREQUENCY        (BOARD_MCK_FREQUENCY >> BOARD_PBC_SHIFT)
 #define BOARD_PBD_FREQUENCY        (BOARD_MCK_FREQUENCY >> BOARD_PBD_SHIFT)
 
+/* FLASH wait states */
+
+#define BOARD_FLASH_WAITSTATES     0
+
 /* LED definitions ******************************************************************/
 /* There are three LEDs on board the SAMD20 Xplained Pro board:  The EDBG
  * controls two of the LEDs, a power LED and a status LED.  There is only