Beginnings of definitions for the LPC1788; convert olimex-lpc1766stk to use kconfig-frontends

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5533 42af7a65-404d-4744-a932-0658087f49c3

17 files changed, 1731 insertions, 943 deletions

diff --git a/apps/nshlib/nsh_netcmds.c b/apps/nshlib/nsh_netcmds.c
index 506950e14..473045c40 100644
--- a/apps/nshlib/nsh_netcmds.c
+++ b/apps/nshlib/nsh_netcmds.c
@@ -53,12 +53,13 @@
 #include <errno.h>
 #include <debug.h>
 
+#include <net/ethernet.h>
+#include <netinet/ether.h>
+
 #include <nuttx/net/net.h>
 #include <nuttx/clock.h>
-#include <net/ethernet.h>
 #include <nuttx/net/uip/uip.h>
 #include <nuttx/net/uip/uip-arch.h>
-#include <netinet/ether.h>
 
 #ifdef CONFIG_NET_STATISTICS
 #  include <nuttx/net/uip/uip.h>
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 2a1561abe..c61479cad 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3977,3 +3977,8 @@
 	  sched/task_posixspawn() now it requires internal, reparenting
 	  interfaces
 	* include/nuttx/spawn():  Move libc/spawn.h to include/nuttx/spawn.h
+	* arch/arm/include/lpc17xx/chip.h, irq178x.h:  Integrate Marcelo
+	  Rommel's LPC1788 definitions into the base LPC17xx.
+	* configs/olimex-lpc1766stk/nsh:  Convert configuration to use
+	  the kconfig-frontends tools.
+	* sched/task_reparent.c:  Simplify reparenting interface.
diff --git a/nuttx/arch/arm/include/lpc17xx/chip.h b/nuttx/arch/arm/include/lpc17xx/chip.h
new file mode 100644
index 000000000..d2c436d35
--- /dev/null
+++ b/nuttx/arch/arm/include/lpc17xx/chip.h
@@ -0,0 +1,377 @@
+/************************************************************************************
+ * arch/arm/include/lpc17xx/chip.h
+ *
+ *   Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           with LPC178x support from Rommel Marcelo
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
+#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Get customizations for each supported chip */
+
+#if defined(CONFIG_ARCH_CHIP_LPC1751)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (32*1024) /* 32Kb */
+#  define LPC17_SRAM_SIZE       (8*1024)  /*  8Kb */
+#  define LPC17_CPUSRAM_SIZE    (8*1024)
+#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
+#  define LPC17_NUSBHOST        0  /* No USB host controller */
+#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            1  /* One CAN controller */
+#  define LPC17_NI2S            0  /* No I2S modules */
+#  define LPC17_NDAC            0  /* No DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1752)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (64*1024) /* 65Kb */
+#  define LPC17_SRAM_SIZE       (16*1024) /* 16Kb */
+#  define LPC17_CPUSRAM_SIZE    (16*1024)
+#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
+#  define LPC17_NUSBHOST        0  /* No USB host controller */
+#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            1  /* One CAN controller */
+#  define LPC17_NI2S            0  /* No I2S modules */
+#  define LPC17_NDAC            0  /* No DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1754)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
+#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
+#  define LPC17_CPUSRAM_SIZE    (16*1024)
+#  define  LPC17_HAVE_BANK0     1  /* Have AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            1  /* One CAN controller */
+#  define LPC17_NI2S            0  /* No I2S modules */
+#  define LPC17_NDAC            1  /* One DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1756)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
+#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
+#  define LPC17_CPUSRAM_SIZE    (16*1024)
+#  define LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            2  /* Two CAN controllers */
+#  define LPC17_NI2S            1  /* One I2S module */
+#  define LPC17_NDAC            1  /* One DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1758)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            2  /* Two CAN controllers */
+#  define LPC17_NI2S            1  /* One I2S module */
+#  define LPC17_NDAC            1  /* One DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1759)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            2  /* Two CAN controllers */
+#  define LPC17_NI2S            1  /* One I2S module */
+#  define LPC17_NDAC            1  /* One DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1764)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
+#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
+#  define LPC17_CPUSRAM_SIZE    (16*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        0  /* No USB host controller */
+#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            2  /* Two CAN controllers */
+#  define LPC17_NI2S            0  /* No I2S modules */
+#  define LPC17_NDAC            0  /* No DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1765)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            2  /* Two CAN controllers */
+#  define LPC17_NI2S            1  /* One I2S module */
+#  define LPC17_NDAC            1  /* One DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1766)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            2  /* Two CAN controllers */
+#  define LPC17_NI2S            1  /* One I2S module */
+#  define LPC17_NDAC            1  /* One DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1767)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        0  /* No USB host controller */
+#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
+#  define LPC17_NUSBDEV         0  /* No USB device controller */
+#  define LPC17_NCAN            0  /* No CAN controllers */
+#  define LPC17_NI2S            1  /* One I2S module */
+#  define LPC17_NDAC            1  /* One DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
+#  define LPC176x               1  /* LPC175/6 family */
+#  undef  LPC178x                  /* Not LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_NCAN            2  /* Two CAN controllers */
+#  define LPC17_NI2S            1  /* One I2S module */
+#  define LPC17_NDAC            1  /* One DAC module */
+#elif defined(CONFIG_ARCH_CHIP_LPC1773)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
+#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
+#  define LPC17_CPUSRAM_SIZE    (8*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* No Peripheral SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LPC17_NUSBHOST           /* No USB host controller */
+#  undef  LPC17_NUSBOTG            /* No USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  define LPC17_HAVE_SPIFI      1  /* Have SPIFI interface */
+#  undef  LPC17_HAVE_LCD           /* No LCD controller */
+#  undef  LPC17_HAVE_QEI           /* No QEI interface */
+#  undef  LPC17_HAVE_SD            /* No SD controller */
+#elif defined(CONFIG_ARCH_CHIP_LPC1774)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
+#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
+#  define LPC17_CPUSRAM_SIZE    (8*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0*/
+#  undef  LPC17_HAVE_BANK1         /* Have Peripheral SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  undef  LPC17_NUSBHOST           /* One USB host controller */
+#  undef  LPC17_NUSBOTG            /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
+#  undef  LPC17_HAVE_LCD           /* One LCD controller */
+#  define LPC17_HAVE_QEI        1  /* One QEI interface */
+#  define LPC17_HAVE_SD         1  /* One SD controller */
+#elif defined(CONFIG_ARCH_CHIP_LPC1776)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE      (16*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0  */
+#  undef  LPC17_HAVE_BANK1         /* Have Peripheral SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
+#  undef  LPC17_HAVE_LCD           /* One LCD controller */
+#  define LPC17_HAVE_QEI        1  /* One QEI interface */
+#  define LPC17_HAVE_SD         1  /* One SD controller */
+#elif defined(CONFIG_ARCH_CHIP_LPC1777)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have Peripheral SRAM bank 1 */
+#  undef  LPC17_NETHCONTROLLERS    /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
+#  undef  LPC17_HAVE_LCD           /* One LCD controller */
+#  define LPC17_HAVE_QEI        1  /* One QEI interface */
+#  define LPC17_HAVE_SD         1  /* One SD controller */
+#elif defined(CONFIG_ARCH_CHIP_LPC1778)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have Peripheral SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
+#  undef  LPC17_HAVE_LCD           /* One LCD controller */
+#  define LPC17_HAVE_QEI        1  /* One QEI interface */
+#  define LPC17_HAVE_SD         1  /* One SD controller */
+#elif defined(CONFIG_ARCH_CHIP_LPC1785)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (16*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* Have Peripheral SRAM bank 1 */
+#  undef  LPC17_NETHCONTROLLERS    /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
+#  define LPC17_HAVE_LCD        1  /* One LCD controller */
+#  undef  LPC17_HAVE_QEI           /* One QEI interface */
+#  define LPC17_HAVE_SD         1  /* One SD controller */
+#elif defined(CONFIG_ARCH_CHIP_LPC1786)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (16*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1         /* Have Peripheral SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
+#  define LPC17_HAVE_LCD        1  /* One LCD controller */
+#  define LPC17_HAVE_QEI        1  /* One QEI interface */
+#  define LPC17_HAVE_SD         1  /* One SD controller */
+#elif defined(CONFIG_ARCH_CHIP_LPC1787)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have Peripheral SRAM bank 1 */
+#  undef  LPC17_NETHCONTROLLERS    /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
+#  define LPC17_HAVE_LCD        1  /* One LCD controller */
+#  define LPC17_HAVE_QEI        1  /* One QEI interface */
+#  define LPC17_HAVE_SD         1  /* One SD controller */
+#elif defined(CONFIG_ARCH_CHIP_LPC1788)
+#  undef  LPC176x                  /* Not LPC175/6 family */
+#  define LPC178x               1  /* LPC177/8 family */
+#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
+#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_CPUSRAM_SIZE    (32*1024)
+#  define LPC17_HAVE_BANK0      1  /* Have Peripheral SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have Peripheral SRAM bank 1 */
+#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LPC17_NUSBHOST        1  /* One USB host controller */
+#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
+#  define LPC17_NUSBDEV         1  /* One USB device controller */
+#  undef  LPC17_HAVE_SPIFI         /* Have SPIFI interface */
+#  define LPC17_HAVE_LCD        1  /* One LCD controller */
+#  define LPC17_HAVE_QEI        1  /* One QEI interface */
+#  define LPC17_HAVE_SD         1  /* One SD controller */
+#else
+#  error "Unsupported LPC17xx chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */
diff --git a/nuttx/arch/arm/include/lpc17xx/irq.h b/nuttx/arch/arm/include/lpc17xx/irq.h
index a7eebb32c..c058f6367 100644
--- a/nuttx/arch/arm/include/lpc17xx/irq.h
+++ b/nuttx/arch/arm/include/lpc17xx/irq.h
@@ -1,7 +1,7 @@
 /****************************************************************************
- * arch/lpc17xxx/irq.h
+ * arch/arm/include/lpc17xxx/irq.h
  *
- *   Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -33,12 +33,12 @@
  *
  ****************************************************************************/
 
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
  */
 
-#ifndef __ARCH_LPC17XX_IRQ_H
-#define __ARCH_LPC17XX_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
 
 /****************************************************************************
  * Included Files
@@ -47,17 +47,17 @@
 #ifndef __ASSEMBLY__
 #  include <stdint.h>
 #endif
+#include <arch/lpc17xx/chip.h>
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
- 
 /* IRQ numbers.  The IRQ number corresponds vector number and hence map
  * directly to bits in the NVIC.  This does, however, waste several words of
  * memory in the IRQ to handle mapping tables.
  */
 
-/* Processor Exceptions (vectors 0-15) */
+/* Common Processor Exceptions (vectors 0-15) */
 
 #define LPC17_IRQ_RESERVED       (0) /* Reserved vector (only used with CONFIG_DEBUG) */
                                      /* Vector  0: Reset stack pointer value */
@@ -75,185 +75,24 @@
 
 /* External interrupts (vectors >= 16) */
 
-#define LPC17_IRQ_EXTINT        (16)                  /* Vector number of the first external interrupt */
-#define LPC17_IRQ_WDT           (LPC17_IRQ_EXTINT+0)  /* WDT Watchdog Interrupt (WDINT) */
-#define LPC17_IRQ_TMR0          (LPC17_IRQ_EXTINT+1)  /* Timer 0 Match 0 - 1 (MR0, MR1)
-                                                       * Capture 0 - 1 (CR0, CR1) */
-#define LPC17_IRQ_TMR1          (LPC17_IRQ_EXTINT+2)  /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
-                                                       * Capture 0 - 1 (CR0, CR1) */
-#define LPC17_IRQ_TMR2          (LPC17_IRQ_EXTINT+3)  /* Timer 2 Match 0-3
-                                                       * Capture 0-1 */
-#define LPC17_IRQ_TMR3          (LPC17_IRQ_EXTINT+4)  /* Timer 3 Match 0-3
-                                                       * Capture 0-1 */
-#define LPC17_IRQ_UART0         (LPC17_IRQ_EXTINT+5)  /* UART 0 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART1         (LPC17_IRQ_EXTINT+6)  /* UART 1 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * Modem Control Change
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART2         (LPC17_IRQ_EXTINT+7)  /* UART 2 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_UART3         (LPC17_IRQ_EXTINT+8)  /* UART 3 Rx Line Status (RLS)
-                                                       * Transmit Holding Register Empty (THRE)
-                                                       * Rx Data Available (RDA)
-                                                       * Character Time-out Indicator (CTI)
-                                                       * End of Auto-Baud (ABEO)
-                                                       * Auto-Baud Time-Out (ABTO) */
-#define LPC17_IRQ_PWM1          (LPC17_IRQ_EXTINT+9)  /* PWM1 Match 0 - 6 of PWM1
-                                                       * Capture 0-1 of PWM1 */
-#define LPC17_IRQ_I2C0          (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
-#define LPC17_IRQ_I2C1          (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
-#define LPC17_IRQ_I2C2          (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
-#define LPC17_IRQ_SPIF          (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
-                                                       * Mode Fault (MODF) */
-#define LPC17_IRQ_SSP0          (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
-                                                       * Rx FIFO half full of SSP0
-                                                       * Rx Timeout of SSP0
-                                                       * Rx Overrun of SSP0 */
-#define LPC17_IRQ_SSP1          (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
-                                                       * Rx FIFO half full
-                                                       * Rx Timeout
-                                                       * Rx Overrun */
-#define LPC17_IRQ_PLL0          (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
-#define LPC17_IRQ_RTC           (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
-                                                       * Alarm (RTCALF) */
-#define LPC17_IRQ_EINT0         (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
-#define LPC17_IRQ_EINT1         (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
-#define LPC17_IRQ_EINT2         (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
-#define LPC17_IRQ_EINT3         (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
-                                                       * Note: EINT3 channel is shared with GPIO interrupts */
-#define LPC17_IRQ_ADC           (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
-#define LPC17_IRQ_BOD           (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
-#define LPC17_IRQ_USB           (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
-                                                       * USB_INT_REQ_DMA */
-#define LPC17_IRQ_CAN           (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
-                                                       *                 CAN 1 Tx, CAN 1 Rx */
-#define LPC17_IRQ_GPDMA         (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
-                                                       *       IntStatus of DMA channel 1 */
-#define LPC17_IRQ_I2S           (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
-#define LPC17_IRQ_ETH           (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
-                                                       * TxFinishedInt, TxErrorInt,* TxUnderrunInt,
-                                                       * RxDoneInt, RxFinishedInt, RxErrorInt,
-                                                       * RxOverrunInt */
-#define LPC17_IRQ_RITINT        (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
-#define LPC17_IRQ_MCPWM         (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
-                                                       * ICAP[2:0], FES */
-#define LPC17_IRQ_QEI           (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
-                                                       * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
-                                                       * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
-                                                       * POS2REV_Int */
-#define LPC17_IRQ_PLL1          (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
-#define LPC17_IRQ_USBACT        (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
-#define LPC17_IRQ_CANACT        (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
-#define LPC17_IRQ_NEXTINT       (35)
-#define LPC17_IRQ_NIRQS         (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
+#define LPC17_IRQ_EXTINT        (16) /* Vector number of the first external interrupt */
 
-/* GPIO interrupts.  The LPC17xx supports several interrupts on ports 0 and
- * 2 (only).  We go through some special efforts to keep the number of IRQs
- * to a minimum in this sparse interrupt case.
- *
- * 28 interrupts on Port 0:  p0.0 - p0.11, p0.15-p0.30
- * 14 interrupts on Port 2:  p2.0 - p2.13
- * --
- * 42
- */
-
-#ifdef CONFIG_GPIO_IRQ
-#  define LPC17_VALID_GPIOINT0  (0x7fff8ffful) /* GPIO port 0 interrrupt set */
-#  define LPC17_VALID_GPIOINT2  (0x00003ffful) /* GPIO port 2 interrupt set */
-
-   /* Set 1: 12 interrupts p0.0-p0.11 */
-
-#  define LPC17_VALID_GPIOINT0L (0x00000ffful)
-#  define LPC17_VALID_SHIFT0L   (0)
-#  define LPC17_VALID_FIRST0L   (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
-
-#  define LPC17_IRQ_P0p0        (LPC17_VALID_FIRST0L+0)
-#  define LPC17_IRQ_P0p1        (LPC17_VALID_FIRST0L+1)
-#  define LPC17_IRQ_P0p2        (LPC17_VALID_FIRST0L+2)
-#  define LPC17_IRQ_P0p3        (LPC17_VALID_FIRST0L+3)
-#  define LPC17_IRQ_P0p4        (LPC17_VALID_FIRST0L+4)
-#  define LPC17_IRQ_P0p5        (LPC17_VALID_FIRST0L+5)
-#  define LPC17_IRQ_P0p6        (LPC17_VALID_FIRST0L+6)
-#  define LPC17_IRQ_P0p7        (LPC17_VALID_FIRST0L+7)
-#  define LPC17_IRQ_P0p8        (LPC17_VALID_FIRST0L+8)
-#  define LPC17_IRQ_P0p9        (LPC17_VALID_FIRST0L+9)
-#  define LPC17_IRQ_P0p10       (LPC17_VALID_FIRST0L+10)
-#  define LPC17_IRQ_P0p11       (LPC17_VALID_FIRST0L+11)
-#  define LPC17_VALID_NIRQS0L   (12)
-
-   /* Set 2: 16 interrupts p0.15-p0.30 */
-
-#  define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
-#  define LPC17_VALID_SHIFT0H   (15)
-#  define LPC17_VALID_FIRST0H   (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
-
-#  define LPC17_IRQ_P0p15       (LPC17_VALID_FIRST0H+0)
-#  define LPC17_IRQ_P0p16       (LPC17_VALID_FIRST0H+1)
-#  define LPC17_IRQ_P0p17       (LPC17_VALID_FIRST0H+2)
-#  define LPC17_IRQ_P0p18       (LPC17_VALID_FIRST0H+3)
-#  define LPC17_IRQ_P0p19       (LPC17_VALID_FIRST0H+4)
-#  define LPC17_IRQ_P0p20       (LPC17_VALID_FIRST0H+5)
-#  define LPC17_IRQ_P0p21       (LPC17_VALID_FIRST0H+6)
-#  define LPC17_IRQ_P0p22       (LPC17_VALID_FIRST0H+7)
-#  define LPC17_IRQ_P0p23       (LPC17_VALID_FIRST0H+8)
-#  define LPC17_IRQ_P0p24       (LPC17_VALID_FIRST0H+9)
-#  define LPC17_IRQ_P0p25       (LPC17_VALID_FIRST0H+10)
-#  define LPC17_IRQ_P0p26       (LPC17_VALID_FIRST0H+11)
-#  define LPC17_IRQ_P0p27       (LPC17_VALID_FIRST0H+12)
-#  define LPC17_IRQ_P0p28       (LPC17_VALID_FIRST0H+13)
-#  define LPC17_IRQ_P0p29       (LPC17_VALID_FIRST0H+14)
-#  define LPC17_IRQ_P0p30       (LPC17_VALID_FIRST0H+15)
-#  define LPC17_VALID_NIRQS0H   (16)
+/* Family Specfic Interrupts */
 
-   /* Set 3: 14 interrupts p2.0-p2.13 */
-
-#  define LPC17_VALID_GPIOINT2  (0x00003ffful)
-#  define LPC17_VALID_SHIFT2    (0)
-#  define LPC17_VALID_FIRST2    (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
-
-#  define LPC17_IRQ_P2p0        (LPC17_VALID_FIRST2+0)
-#  define LPC17_IRQ_P2p1        (LPC17_VALID_FIRST2+1)
-#  define LPC17_IRQ_P2p2        (LPC17_VALID_FIRST2+2)
-#  define LPC17_IRQ_P2p3        (LPC17_VALID_FIRST2+3)
-#  define LPC17_IRQ_P2p4        (LPC17_VALID_FIRST2+4)
-#  define LPC17_IRQ_P2p5        (LPC17_VALID_FIRST2+5)
-#  define LPC17_IRQ_P2p6        (LPC17_VALID_FIRST2+6)
-#  define LPC17_IRQ_P2p7        (LPC17_VALID_FIRST2+7)
-#  define LPC17_IRQ_P2p8        (LPC17_VALID_FIRST2+8)
-#  define LPC17_IRQ_P2p9        (LPC17_VALID_FIRST2+9)
-#  define LPC17_IRQ_P2p10       (LPC17_VALID_FIRST2+10)
-#  define LPC17_IRQ_P2p11       (LPC17_VALID_FIRST2+11)
-#  define LPC17_IRQ_P2p12       (LPC17_VALID_FIRST2+12)
-#  define LPC17_IRQ_P2p13       (LPC17_VALID_FIRST2+13)
-#  define LPC17_VALID_NIRQS2    (14)
-#  define LPC17_NGPIOAIRQS      (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2)
+#if defined(LPC176x)                 /* LPC175/6 family */
+#  include <arch/lpc17xx/lpc176x_irq.h>
+#elif defined(LPC178x)               /* LPC177/8 family */
+#  include <arch/lpc17xx/lpc178x_irq.h>
 #else
-#  define LPC17_NGPIOAIRQS      (0)
+#  error "Unknown LPC17xx family"
 #endif
 
-/* Total number of IRQ numbers */
-
-#define NR_IRQS                 (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
-
 /****************************************************************************
  * Public Types
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
 typedef void (*vic_vector_t)(uint32_t *regs);
-#endif
 
 /****************************************************************************
  * Inline functions
@@ -267,19 +106,15 @@ typedef void (*vic_vector_t)(uint32_t *regs);
  * Public Function Prototypes
  ****************************************************************************/
 
-#ifndef __ASSEMBLY__
 #ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
+extern "C"
+{
 #endif
 
-#undef EXTERN
 #ifdef __cplusplus
 }
 #endif
-#endif
+#endif __ASSEMBLY__
 
-#endif /* __ARCH_LPC17XX_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */
 
diff --git a/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h b/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h
new file mode 100644
index 000000000..ac97195e6
--- /dev/null
+++ b/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/lpc17xx/lpc176x_irq.h
+ *
+ *   Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC.  This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ */
+
+/* External interrupts (vectors >= 16) */
+
+#define LPC17_IRQ_WDT           (LPC17_IRQ_EXTINT+0)  /* WDT Watchdog Interrupt (WDINT) */
+#define LPC17_IRQ_TMR0          (LPC17_IRQ_EXTINT+1)  /* Timer 0 Match 0 - 1 (MR0, MR1)
+                                                       * Capture 0 - 1 (CR0, CR1) */
+#define LPC17_IRQ_TMR1          (LPC17_IRQ_EXTINT+2)  /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
+                                                       * Capture 0 - 1 (CR0, CR1) */
+#define LPC17_IRQ_TMR2          (LPC17_IRQ_EXTINT+3)  /* Timer 2 Match 0-3
+                                                       * Capture 0-1 */
+#define LPC17_IRQ_TMR3          (LPC17_IRQ_EXTINT+4)  /* Timer 3 Match 0-3
+                                                       * Capture 0-1 */
+#define LPC17_IRQ_UART0         (LPC17_IRQ_EXTINT+5)  /* UART 0 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_UART1         (LPC17_IRQ_EXTINT+6)  /* UART 1 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * Modem Control Change
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_UART2         (LPC17_IRQ_EXTINT+7)  /* UART 2 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_UART3         (LPC17_IRQ_EXTINT+8)  /* UART 3 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_PWM1          (LPC17_IRQ_EXTINT+9)  /* PWM1 Match 0 - 6 of PWM1
+                                                       * Capture 0-1 of PWM1 */
+#define LPC17_IRQ_I2C0          (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
+#define LPC17_IRQ_I2C1          (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
+#define LPC17_IRQ_I2C2          (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
+#define LPC17_IRQ_SPIF          (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
+                                                       * Mode Fault (MODF) */
+#define LPC17_IRQ_SSP0          (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
+                                                       * Rx FIFO half full of SSP0
+                                                       * Rx Timeout of SSP0
+                                                       * Rx Overrun of SSP0 */
+#define LPC17_IRQ_SSP1          (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
+                                                       * Rx FIFO half full
+                                                       * Rx Timeout
+                                                       * Rx Overrun */
+#define LPC17_IRQ_PLL0          (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
+#define LPC17_IRQ_RTC           (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
+                                                       * Alarm (RTCALF) */
+#define LPC17_IRQ_EINT0         (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
+#define LPC17_IRQ_EINT1         (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
+#define LPC17_IRQ_EINT2         (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
+#define LPC17_IRQ_EINT3         (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
+                                                       * Note: EINT3 channel is shared with GPIO interrupts */
+#define LPC17_IRQ_ADC           (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
+#define LPC17_IRQ_BOD           (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
+#define LPC17_IRQ_USB           (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
+                                                       * USB_INT_REQ_DMA */
+#define LPC17_IRQ_CAN           (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
+                                                       *                 CAN 1 Tx, CAN 1 Rx */
+#define LPC17_IRQ_GPDMA         (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
+                                                       *       IntStatus of DMA channel 1 */
+#define LPC17_IRQ_I2S           (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
+#define LPC17_IRQ_ETH           (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
+                                                       * TxFinishedInt, TxErrorInt,* TxUnderrunInt,
+                                                       * RxDoneInt, RxFinishedInt, RxErrorInt,
+                                                       * RxOverrunInt */
+#define LPC17_IRQ_RITINT        (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
+#define LPC17_IRQ_MCPWM         (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
+                                                       * ICAP[2:0], FES */
+#define LPC17_IRQ_QEI           (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
+                                                       * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
+                                                       * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
+                                                       * POS2REV_Int */
+#define LPC17_IRQ_PLL1          (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
+#define LPC17_IRQ_USBACT        (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
+#define LPC17_IRQ_CANACT        (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
+#define LPC17_IRQ_NEXTINT       (35)
+#define LPC17_IRQ_NIRQS         (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
+
+/* GPIO interrupts.  The LPC17xx supports several interrupts on ports 0 and
+ * 2 (only).  We go through some special efforts to keep the number of IRQs
+ * to a minimum in this sparse interrupt case.
+ *
+ * 28 interrupts on Port 0:  p0.0 - p0.11, p0.15-p0.30
+ * 14 interrupts on Port 2:  p2.0 - p2.13
+ * --
+ * 42
+ */
+
+#ifdef CONFIG_GPIO_IRQ
+#  define LPC17_VALID_GPIOINT0  (0x7fff8ffful) /* GPIO port 0 interrrupt set */
+#  define LPC17_VALID_GPIOINT2  (0x00003ffful) /* GPIO port 2 interrupt set */
+
+   /* Set 1: 12 interrupts p0.0-p0.11 */
+
+#  define LPC17_VALID_GPIOINT0L (0x00000ffful)
+#  define LPC17_VALID_SHIFT0L   (0)
+#  define LPC17_VALID_FIRST0L   (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
+
+#  define LPC17_IRQ_P0p0        (LPC17_VALID_FIRST0L+0)
+#  define LPC17_IRQ_P0p1        (LPC17_VALID_FIRST0L+1)
+#  define LPC17_IRQ_P0p2        (LPC17_VALID_FIRST0L+2)
+#  define LPC17_IRQ_P0p3        (LPC17_VALID_FIRST0L+3)
+#  define LPC17_IRQ_P0p4        (LPC17_VALID_FIRST0L+4)
+#  define LPC17_IRQ_P0p5        (LPC17_VALID_FIRST0L+5)
+#  define LPC17_IRQ_P0p6        (LPC17_VALID_FIRST0L+6)
+#  define LPC17_IRQ_P0p7        (LPC17_VALID_FIRST0L+7)
+#  define LPC17_IRQ_P0p8        (LPC17_VALID_FIRST0L+8)
+#  define LPC17_IRQ_P0p9        (LPC17_VALID_FIRST0L+9)
+#  define LPC17_IRQ_P0p10       (LPC17_VALID_FIRST0L+10)
+#  define LPC17_IRQ_P0p11       (LPC17_VALID_FIRST0L+11)
+#  define LPC17_VALID_NIRQS0L   (12)
+
+   /* Set 2: 16 interrupts p0.15-p0.30 */
+
+#  define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
+#  define LPC17_VALID_SHIFT0H   (15)
+#  define LPC17_VALID_FIRST0H   (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
+
+#  define LPC17_IRQ_P0p15       (LPC17_VALID_FIRST0H+0)
+#  define LPC17_IRQ_P0p16       (LPC17_VALID_FIRST0H+1)
+#  define LPC17_IRQ_P0p17       (LPC17_VALID_FIRST0H+2)
+#  define LPC17_IRQ_P0p18       (LPC17_VALID_FIRST0H+3)
+#  define LPC17_IRQ_P0p19       (LPC17_VALID_FIRST0H+4)
+#  define LPC17_IRQ_P0p20       (LPC17_VALID_FIRST0H+5)
+#  define LPC17_IRQ_P0p21       (LPC17_VALID_FIRST0H+6)
+#  define LPC17_IRQ_P0p22       (LPC17_VALID_FIRST0H+7)
+#  define LPC17_IRQ_P0p23       (LPC17_VALID_FIRST0H+8)
+#  define LPC17_IRQ_P0p24       (LPC17_VALID_FIRST0H+9)
+#  define LPC17_IRQ_P0p25       (LPC17_VALID_FIRST0H+10)
+#  define LPC17_IRQ_P0p26       (LPC17_VALID_FIRST0H+11)
+#  define LPC17_IRQ_P0p27       (LPC17_VALID_FIRST0H+12)
+#  define LPC17_IRQ_P0p28       (LPC17_VALID_FIRST0H+13)
+#  define LPC17_IRQ_P0p29       (LPC17_VALID_FIRST0H+14)
+#  define LPC17_IRQ_P0p30       (LPC17_VALID_FIRST0H+15)
+#  define LPC17_VALID_NIRQS0H   (16)
+
+   /* Set 3: 14 interrupts p2.0-p2.13 */
+
+#  define LPC17_VALID_GPIOINT2  (0x00003ffful)
+#  define LPC17_VALID_SHIFT2    (0)
+#  define LPC17_VALID_FIRST2    (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
+
+#  define LPC17_IRQ_P2p0        (LPC17_VALID_FIRST2+0)
+#  define LPC17_IRQ_P2p1        (LPC17_VALID_FIRST2+1)
+#  define LPC17_IRQ_P2p2        (LPC17_VALID_FIRST2+2)
+#  define LPC17_IRQ_P2p3        (LPC17_VALID_FIRST2+3)
+#  define LPC17_IRQ_P2p4        (LPC17_VALID_FIRST2+4)
+#  define LPC17_IRQ_P2p5        (LPC17_VALID_FIRST2+5)
+#  define LPC17_IRQ_P2p6        (LPC17_VALID_FIRST2+6)
+#  define LPC17_IRQ_P2p7        (LPC17_VALID_FIRST2+7)
+#  define LPC17_IRQ_P2p8        (LPC17_VALID_FIRST2+8)
+#  define LPC17_IRQ_P2p9        (LPC17_VALID_FIRST2+9)
+#  define LPC17_IRQ_P2p10       (LPC17_VALID_FIRST2+10)
+#  define LPC17_IRQ_P2p11       (LPC17_VALID_FIRST2+11)
+#  define LPC17_IRQ_P2p12       (LPC17_VALID_FIRST2+12)
+#  define LPC17_IRQ_P2p13       (LPC17_VALID_FIRST2+13)
+#  define LPC17_VALID_NIRQS2    (14)
+#  define LPC17_NGPIOAIRQS      (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2)
+#else
+#  define LPC17_NGPIOAIRQS      (0)
+#endif
+
+/* Total number of IRQ numbers */
+
+#define NR_IRQS                 (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */
+
diff --git a/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h b/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h
new file mode 100644
index 000000000..9f7cbf9a7
--- /dev/null
+++ b/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h
@@ -0,0 +1,294 @@
+/****************************************************************************
+ * arch/arm/include/lpc17xxx/lpc178x_irq.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Authors: Rommel Marcelo
+ *            Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+ 
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC.  This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ */
+
+/* External interrupts (vectors >= 16) */
+
+#define LPC17_IRQ_WDT           (LPC17_IRQ_EXTINT+0)  /* WDT Watchdog Interrupt (WDINT) */
+#define LPC17_IRQ_TMR0          (LPC17_IRQ_EXTINT+1)  /* Timer 0 Match 0 - 1 (MR0, MR1)
+                                                       * Capture 0 - 1 (CR0, CR1) */
+#define LPC17_IRQ_TMR1          (LPC17_IRQ_EXTINT+2)  /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
+                                                       * Capture 0 - 1 (CR0, CR1) */
+#define LPC17_IRQ_TMR2          (LPC17_IRQ_EXTINT+3)  /* Timer 2 Match 0-3
+                                                       * Capture 0-1 */
+#define LPC17_IRQ_TMR3          (LPC17_IRQ_EXTINT+4)  /* Timer 3 Match 0-3
+                                                       * Capture 0-1 */
+#define LPC17_IRQ_UART0         (LPC17_IRQ_EXTINT+5)  /* UART 0 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_UART1         (LPC17_IRQ_EXTINT+6)  /* UART 1 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * Modem Control Change
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_UART2         (LPC17_IRQ_EXTINT+7)  /* UART 2 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_UART3         (LPC17_IRQ_EXTINT+8)  /* UART 3 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_PWM1          (LPC17_IRQ_EXTINT+9)  /* PWM1 Match 0 - 6 of PWM1
+                                                       * Capture 0-1 of PWM1 */
+#define LPC17_IRQ_I2C0          (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
+#define LPC17_IRQ_I2C1          (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
+#define LPC17_IRQ_I2C2          (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
+/*                              (LPC17_IRQ_EXTINT+13)    Unused  */
+#define LPC17_IRQ_SSP0          (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
+                                                       * Rx FIFO half full of SSP0
+                                                       * Rx Timeout of SSP0
+                                                       * Rx Overrun of SSP0 */
+#define LPC17_IRQ_SSP1          (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
+                                                       * Rx FIFO half full
+                                                       * Rx Timeout
+                                                       * Rx Overrun */
+#define LPC17_IRQ_PLL0          (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
+#define LPC17_IRQ_RTC           (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
+                                                       * Alarm (RTCALF) */
+#define LPC17_IRQ_EINT0         (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
+#define LPC17_IRQ_EINT1         (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
+#define LPC17_IRQ_EINT2         (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
+#define LPC17_IRQ_EINT3         (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
+                                                       * Note: EINT3 channel is shared with GPIO interrupts */
+#define LPC17_IRQ_ADC           (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
+#define LPC17_IRQ_BOD           (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
+#define LPC17_IRQ_USB           (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
+                                                       * USB_INT_REQ_DMA */
+#define LPC17_IRQ_CAN           (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
+                                                       *                 CAN 1 Tx, CAN 1 Rx */
+#define LPC17_IRQ_GPDMA         (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
+                                                       *       IntStatus of DMA channel 1 */
+#define LPC17_IRQ_I2S           (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
+#define LPC17_IRQ_ETH           (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
+                                                       * TxFinishedInt, TxErrorInt,* TxUnderrunInt,
+                                                       * RxDoneInt, RxFinishedInt, RxErrorInt,
+                                                       * RxOverrunInt */
+#define LPC17_IRQ_MCI           (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */
+#define LPC17_IRQ_MCPWM         (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
+                                                       * ICAP[2:0], FES */
+#define LPC17_IRQ_QEI           (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
+                                                       * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
+                                                       * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
+                                                       * POS2REV_Int */
+#define LPC17_IRQ_PLL1          (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
+#define LPC17_IRQ_USBACT        (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
+#define LPC17_IRQ_CANACT        (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
+#define LPC17_IRQ_UART4         (LPC17_IRQ_EXTINT+35)  /* UART 4 Rx Line Status (RLS)
+                                                       * Transmit Holding Register Empty (THRE)
+                                                       * Rx Data Available (RDA)
+                                                       * Character Time-out Indicator (CTI)
+                                                       * End of Auto-Baud (ABEO)
+                                                       * Auto-Baud Time-Out (ABTO) */
+#define LPC17_IRQ_SSP2          (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
+                                                       * Rx FIFO half full of SSP2
+                                                       * Rx Timeout of SSP2
+                                                       * Rx Overrun of SSP2 */
+#define LPC17_IRQ_LCD           (LPC17_IRQ_EXTINT+37) /* LCD interrupt
+                                                       * BER, VCompI, LNBUI, FUFI, CrsrI */
+#define LPC17_IRQ_GPIO          (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt
+                                                       * P0xREI, P2xREI, P0xFEI, P2xFEI */
+#define LPC17_IRQ_PWM0          (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
+                                                       * Capture 0-1 of PWM0 */
+#define LPC17_IRQ_EEPROM        (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt
+                                                       * EE_PROG_DONE, EE_RW_DONE */
+#define LPC17_IRQ_NEXTINT       (40)
+#define LPC17_IRQ_NIRQS         (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
+
+/* GPIO interrupts.  The LPC177x_8x supports several interrupts on ports 0 and
+ * 2 (only).  We go through some special efforts to keep the number of IRQs
+ * to a minimum in this sparse interrupt case.
+ *
+ * 31 interrupts on Port 0:  p0.0 - p0.30
+ * 31 interrupts on Port 2:  p2.0 - p2.30
+ * --
+ * 42
+ */
+
+#ifdef CONFIG_GPIO_IRQ
+//~ #  define LPC17_VALID_GPIOINT0  (0x7fff8ffful) /* GPIO port 0 interrrupt set */
+//~ #  define LPC17_VALID_GPIOINT2  (0x00003ffful) /* GPIO port 2 interrupt set */
+
+   /* Set 1: 16 interrupts p0.0-p0.15 */
+
+//~ #  define LPC17_VALID_GPIOINT0L (0x00000ffful)
+#  define LPC17_VALID_SHIFT0L   (0)
+#  define LPC17_VALID_FIRST0L   (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
+
+#  define LPC17_IRQ_P0p0        (LPC17_VALID_FIRST0L+0)
+#  define LPC17_IRQ_P0p1        (LPC17_VALID_FIRST0L+1)
+#  define LPC17_IRQ_P0p2        (LPC17_VALID_FIRST0L+2)
+#  define LPC17_IRQ_P0p3        (LPC17_VALID_FIRST0L+3)
+#  define LPC17_IRQ_P0p4        (LPC17_VALID_FIRST0L+4)
+#  define LPC17_IRQ_P0p5        (LPC17_VALID_FIRST0L+5)
+#  define LPC17_IRQ_P0p6        (LPC17_VALID_FIRST0L+6)
+#  define LPC17_IRQ_P0p7        (LPC17_VALID_FIRST0L+7)
+#  define LPC17_IRQ_P0p8        (LPC17_VALID_FIRST0L+8)
+#  define LPC17_IRQ_P0p9        (LPC17_VALID_FIRST0L+9)
+#  define LPC17_IRQ_P0p10       (LPC17_VALID_FIRST0L+10)
+#  define LPC17_IRQ_P0p11       (LPC17_VALID_FIRST0L+11)
+#  define LPC17_IRQ_P0p12       (LPC17_VALID_FIRST0L+12)
+#  define LPC17_IRQ_P0p13       (LPC17_VALID_FIRST0L+13)
+#  define LPC17_IRQ_P0p14       (LPC17_VALID_FIRST0L+14)
+#  define LPC17_IRQ_P0p15       (LPC17_VALID_FIRST0L+15)
+#  define LPC17_VALID_NIRQS0L   (16)
+
+   /* Set 2: 16 interrupts p0.16-p0.31 */
+
+//~ #  define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
+#  define LPC17_VALID_SHIFT0H   (15)
+#  define LPC17_VALID_FIRST0H   (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
+
+#  define LPC17_IRQ_P0p16       (LPC17_VALID_FIRST0H+0)
+#  define LPC17_IRQ_P0p17       (LPC17_VALID_FIRST0H+1)
+#  define LPC17_IRQ_P0p18       (LPC17_VALID_FIRST0H+2)
+#  define LPC17_IRQ_P0p19       (LPC17_VALID_FIRST0H+3)
+#  define LPC17_IRQ_P0p20       (LPC17_VALID_FIRST0H+4)
+#  define LPC17_IRQ_P0p21       (LPC17_VALID_FIRST0H+5)
+#  define LPC17_IRQ_P0p22       (LPC17_VALID_FIRST0H+6)
+#  define LPC17_IRQ_P0p23       (LPC17_VALID_FIRST0H+7)
+#  define LPC17_IRQ_P0p24       (LPC17_VALID_FIRST0H+8)
+#  define LPC17_IRQ_P0p25       (LPC17_VALID_FIRST0H+9)
+#  define LPC17_IRQ_P0p26       (LPC17_VALID_FIRST0H+10)
+#  define LPC17_IRQ_P0p27       (LPC17_VALID_FIRST0H+11)
+#  define LPC17_IRQ_P0p28       (LPC17_VALID_FIRST0H+12)
+#  define LPC17_IRQ_P0p29       (LPC17_VALID_FIRST0H+13)
+#  define LPC17_IRQ_P0p30       (LPC17_VALID_FIRST0H+14)
+#  define LPC17_IRQ_P0p31       (LPC17_VALID_FIRST0H+15)
+#  define LPC17_VALID_NIRQS0H   (16)
+
+   /* Set 3: 16 interrupts p2.0-p2.15 */
+
+//~ #  define LPC17_VALID_GPIOINT2  (0x00003ffful)
+#  define LPC17_VALID_SHIFT2L   (0)
+#  define LPC17_VALID_FIRST2L   (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
+
+#  define LPC17_IRQ_P2p0        (LPC17_VALID_FIRST2L+0)
+#  define LPC17_IRQ_P2p1        (LPC17_VALID_FIRST2L+1)
+#  define LPC17_IRQ_P2p2        (LPC17_VALID_FIRST2L+2)
+#  define LPC17_IRQ_P2p3        (LPC17_VALID_FIRST2L+3)
+#  define LPC17_IRQ_P2p4        (LPC17_VALID_FIRST2L+4)
+#  define LPC17_IRQ_P2p5        (LPC17_VALID_FIRST2L+5)
+#  define LPC17_IRQ_P2p6        (LPC17_VALID_FIRST2L+6)
+#  define LPC17_IRQ_P2p7        (LPC17_VALID_FIRST2L+7)
+#  define LPC17_IRQ_P2p8        (LPC17_VALID_FIRST2L+8)
+#  define LPC17_IRQ_P2p9        (LPC17_VALID_FIRST2L+9)
+#  define LPC17_IRQ_P2p10       (LPC17_VALID_FIRST2L+10)
+#  define LPC17_IRQ_P2p11       (LPC17_VALID_FIRST2L+11)
+#  define LPC17_IRQ_P2p12       (LPC17_VALID_FIRST2L+12)
+#  define LPC17_IRQ_P2p13       (LPC17_VALID_FIRST2L+13)
+#  define LPC17_IRQ_P2p14       (LPC17_VALID_FIRST2L+14)
+#  define LPC17_IRQ_P2p15       (LPC17_VALID_FIRST2L+15)
+#  define LPC17_VALID_NIRQS2L   (16)
+
+   /* Set 3: 16 interrupts p2.16 - p2.31 */
+
+#  define LPC17_VALID_SHIFT2H   (15)
+#  define LPC17_VALID_FIRST2H   (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L)
+
+#  define LPC17_IRQ_P2p16       (LPC17_VALID_FIRST2H+0)
+#  define LPC17_IRQ_P2p17       (LPC17_VALID_FIRST2H+1)
+#  define LPC17_IRQ_P2p18       (LPC17_VALID_FIRST2H+2)
+#  define LPC17_IRQ_P2p19       (LPC17_VALID_FIRST2H+3)
+#  define LPC17_IRQ_P2p20       (LPC17_VALID_FIRST2H+4)
+#  define LPC17_IRQ_P2p21       (LPC17_VALID_FIRST2H+5)
+#  define LPC17_IRQ_P2p22       (LPC17_VALID_FIRST2H+6)
+#  define LPC17_IRQ_P2p23       (LPC17_VALID_FIRST2H+7)
+#  define LPC17_IRQ_P2p24       (LPC17_VALID_FIRST2H+8)
+#  define LPC17_IRQ_P2p25       (LPC17_VALID_FIRST2H+9)
+#  define LPC17_IRQ_P2p26       (LPC17_VALID_FIRST2H+10)
+#  define LPC17_IRQ_P2p27       (LPC17_VALID_FIRST2H+11)
+#  define LPC17_IRQ_P2p28       (LPC17_VALID_FIRST2H+12)
+#  define LPC17_IRQ_P2p29       (LPC17_VALID_FIRST2H+13)
+#  define LPC17_IRQ_P2p30       (LPC17_VALID_FIRST2H+14)
+#  define LPC17_IRQ_P2p31       (LPC17_VALID_FIRST2H+15)
+#  define LPC17_VALID_NIRQS2H   (16)
+   
+#  define LPC17_NGPIOAIRQS      (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H)
+#else
+#  define LPC17_NGPIOAIRQS      (0)
+#endif
+
+/* Total number of IRQ numbers */
+
+#define NR_IRQS                 (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */
+
diff --git a/nuttx/arch/arm/src/lpc17xx/Kconfig b/nuttx/arch/arm/src/lpc17xx/Kconfig
index 8acd67595..b7dd7ac34 100644
--- a/nuttx/arch/arm/src/lpc17xx/Kconfig
+++ b/nuttx/arch/arm/src/lpc17xx/Kconfig
@@ -12,49 +12,101 @@ choice
 
 config ARCH_CHIP_LPC1751
 	bool "LPC1751"
+	select ARCH_FAMILY_LPC175X
 
 config ARCH_CHIP_LPC1752
 	bool "LPC1752"
+	select ARCH_FAMILY_LPC175X
 
 config ARCH_CHIP_LPC1754
 	bool "LPC1754"
+	select ARCH_FAMILY_LPC175X
 
 config ARCH_CHIP_LPC1756
 	bool "LPC1756"
+	select ARCH_FAMILY_LPC175X
 
 config ARCH_CHIP_LPC1758
 	bool "LPC1758"
+	select ARCH_FAMILY_LPC175X
 
 config ARCH_CHIP_LPC1759
 	bool "LPC1759"
+	select ARCH_FAMILY_LPC175X
 
 config ARCH_CHIP_LPC1764
 	bool "LPC1764"
+	select ARCH_FAMILY_LPC176X
 
 config ARCH_CHIP_LPC1765
 	bool "LPC1765"
+	select ARCH_FAMILY_LPC176X
 
 config ARCH_CHIP_LPC1766
 	bool "LPC1766"
+	select ARCH_FAMILY_LPC176X
 
 config ARCH_CHIP_LPC1767
 	bool "LPC1767"
+	select ARCH_FAMILY_LPC176X
 
 config ARCH_CHIP_LPC1768
 	bool "LPC1768"
+	select ARCH_FAMILY_LPC176X
 
 config ARCH_CHIP_LPC1769
 	bool "LPC1769"
+	select ARCH_FAMILY_LPC176X
+
+config ARCH_CHIP_LPC1773
+	bool "LPC1773"
+	select ARCH_FAMILY_LPC177X
+
+config ARCH_CHIP_LPC1774
+	bool "LPC1774"
+	select ARCH_FAMILY_LPC177X
+
+config ARCH_CHIP_LPC1776
+	bool "LPC1776"
+	select ARCH_FAMILY_LPC177X
+
+config ARCH_CHIP_LPC1777
+	bool "LPC1777"
+	select ARCH_FAMILY_LPC177X
+
+config ARCH_CHIP_LPC1778
+	bool "LPC1778"
+	select ARCH_FAMILY_LPC177X
+
+config ARCH_CHIP_LPC1785
+	bool "LPC1785"
+	select ARCH_FAMILY_LPC178X
+
+config ARCH_CHIP_LPC1786
+	bool "LPC1786"
+	select ARCH_FAMILY_LPC178X
+
+config ARCH_CHIP_LPC1787
+	bool "LPC1787"
+	select ARCH_FAMILY_LPC178X
+
+config ARCH_CHIP_LPC1788
+	bool "LPC1788"
+	select ARCH_FAMILY_LPC178X
 
 endchoice
 
 config ARCH_FAMILY_LPC175X
 	bool
-	default y if ARCH_CHIP_LPC1751 || ARCH_CHIP_LPC1752 || ARCH_CHIP_LPC1754 || ARCH_CHIP_LPC1756 || ARCH_CHIP_LPC1758 || ARCH_CHIP_LPC1759
 
 config ARCH_FAMILY_LPC176X
 	bool
-	default y if ARCH_CHIP_LPC1764 || ARCH_CHIP_LPC1765 || ARCH_CHIP_LPC1766 || ARCH_CHIP_LPC1767 || ARCH_CHIP_LPC1768 || ARCH_CHIP_LPC1769
+
+config ARCH_FAMILY_LPC177X
+	bool
+
+config ARCH_FAMILY_LPC178X
+	bool
 
 menu "LPC17xx Peripheral Support"
 
diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h
index 982482017..60dda773d 100644
--- a/nuttx/arch/arm/src/lpc17xx/chip.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip.h
@@ -41,159 +41,7 @@
  ************************************************************************************/
 
 #include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Get customizations for each supported chip */
-
-#if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1767)
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        0  /* No USB host controller */
-#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC17_NUSBDEV         0  /* No USB device controller */
-#  define LPC17_NCAN            0  /* No CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1766)
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1765)
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1764)
-#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
-#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  define LPC17_CPUSRAM_SIZE    (16*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        0  /* No USB host controller */
-#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            0  /* No I2S modules */
-#  define LPC17_NDAC            0  /* No DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1759)
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1758)
-#  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
-#  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
-#  define LPC17_CPUSRAM_SIZE    (32*1024)
-#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
-#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1756)
-#  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
-#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  define LPC17_CPUSRAM_SIZE    (16*1024)
-#  define LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            2  /* Two CAN controllers */
-#  define LPC17_NI2S            1  /* One I2S module */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1754)
-#  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
-#  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
-#  define LPC17_CPUSRAM_SIZE    (16*1024)
-#  define  LPC17_HAVE_BANK0     1  /* Have AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        1  /* One USB host controller */
-#  define LPC17_NUSBOTG         1  /* One USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            1  /* One CAN controller */
-#  define LPC17_NI2S            0  /* No I2S modules */
-#  define LPC17_NDAC            1  /* One DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1752)
-#  define LPC17_FLASH_SIZE      (64*1024) /* 65Kb */
-#  define LPC17_SRAM_SIZE       (16*1024) /* 16Kb */
-#  define LPC17_CPUSRAM_SIZE    (16*1024)
-#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        0  /* No USB host controller */
-#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            1  /* One CAN controller */
-#  define LPC17_NI2S            0  /* No I2S modules */
-#  define LPC17_NDAC            0  /* No DAC module */
-#elif defined(CONFIG_ARCH_CHIP_LPC1751)
-#  define LPC17_FLASH_SIZE      (32*1024) /* 32Kb */
-#  define LPC17_SRAM_SIZE       (8*1024)  /*  8Kb */
-#  define LPC17_CPUSRAM_SIZE    (8*1024)
-#  undef  LPC17_HAVE_BANK0         /* No AHB SRAM bank 0 */
-#  undef  LPC17_HAVE_BANK1         /* No AHB SRAM bank 1 */
-#  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
-#  define LPC17_NUSBHOST        0  /* No USB host controller */
-#  define LPC17_NUSBOTG         0  /* No USB OTG controller */
-#  define LPC17_NUSBDEV         1  /* One USB device controller */
-#  define LPC17_NCAN            1  /* One CAN controller */
-#  define LPC17_NI2S            0  /* No I2S modules */
-#  define LPC17_NDAC            0  /* No DAC module */
-#else
-#  error "Unsupported LPC17xx chip"
-#endif
+#include <arch/lpc17xx/chip.h>
 
 /* Include only the memory map.  Other chip hardware files should then include this
  * file for the proper setup
@@ -201,6 +49,10 @@
 
 #include "lpc17_memorymap.h"
 
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
 /* NVIC priority levels *************************************************************/
 /* Each priority field holds a priority value, 0-31. The lower the value, the greater
  * the priority of the corresponding interrupt. The processor implements only
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c
index 76c446c7d..db6fbe1f8 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/lpc17xx/lpc17_ssp.c
  *
- *   Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -926,4 +926,3 @@ void ssp_flush(FAR struct spi_dev_s *dev)
 }
 
 #endif /* CONFIG_LPC17_SSP0/1 */
-
diff --git a/nuttx/configs/olimex-lpc1766stk/README.txt b/nuttx/configs/olimex-lpc1766stk/README.txt
index 13c63d18b..990d1141a 100644
--- a/nuttx/configs/olimex-lpc1766stk/README.txt
+++ b/nuttx/configs/olimex-lpc1766stk/README.txt
@@ -935,44 +935,37 @@ Where <subdir> is one of the following:
 
     Configuration Notes:
 
-    1. Uses the buildroot toolchaing (CONFIG_LPC17_BUILDROOT=y).  But that is
-       easily reconfigured (see above)
-    2. Support for FAT long file names is built-in but can easily be
-       removed if you are concerned about Microsoft patent issues (see the
-       section "FAT Long File Names" in the top-level COPYING file).
-       
-        CONFIG_FS_FAT=y
-        CONFIG_FAT_LCNAMES=y <-- Long file name support
-        CONFIG_FAT_LFN=y
-        CONFIG_FAT_MAXFNAME=32
-        CONFIG_FS_NXFFS=n
-        CONFIG_FS_ROMFS=n
+    NOTES:
+ 
+    1. This configuration uses the mconf-based configuration tool.  To
+       change this configuration using that tool, you should:
 
-    3. Includes logic to support a button test (apps/examples/buttons).  To
-       enable the button test, make the following changes in the .config
-       after configuring:
+       a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+          and misc/tools/
+
+       b. Execute 'make menuconfig' in nuttx/ in order to start the
+          reconfiguration process.
 
-       -CONFIG_ARCH_BUTTONS=n
-       +CONFIG_ARCH_BUTTONS=y
+    2. Uses the older, OABI, buildroot toolchain.  But that is easily
+       reconfigured:
 
-       -CONFIG_GPIO_IRQ=n
-       -CONFIG_ARCH_IRQBUTTONS=n
-       +CONFIG_GPIO_IRQ=y
-       +CONFIG_ARCH_IRQBUTTONS=y
+       CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain
+       CONFIG_ARMV7M_OABI_TOOLCHAIN=y      : Older, OABI toolchain
 
-    4. This example supports the CAN loopback test (apps/examples/can) but this
-       must be manually enabled by selecting:
+    3. This configuration supports a network.  You may have to change
+       these settings for your network:
 
-       CONFIG_CAN=y             : Enable the generic CAN infrastructure
-       CONFIG_LPC17_CAN1=y      : Enable CAN1
-       CONFIG_CAN_LOOPBACK=y    : Enable CAN loopback mode
+       CONFIG_NSH_IPADDR=0x0a000002        : IP address: 10.0.0.2
+       CONFIG_NSH_DRIPADDR=0x0a000001      : Gateway:    10.0.0.1
+       CONFIG_NSH_NETMASK=0xffffff00       : Netmask:    255.255.255.0
 
-       See also apps/examples/README.txt
- 
-       Special CAN-only debug options:
+    4. This configuration supports the SPI-based MMC/SD card slot.
+       FAT file system support for FAT long file names is built-in but
+       can easily be removed if you are concerned about Microsoft patent
+       issues (see the section "FAT Long File Names" in the top-level
+       COPYING file).
 
-       CONFIG_DEBUG_CAN
-       CONFIG_CAN_REGDEBUG
+       CONFIG_FAT_LFN=y                    : Enables long file name support
 
   nx:
     An example using the NuttX graphics system (NX).  This example uses
diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/appconfig b/nuttx/configs/olimex-lpc1766stk/nsh/appconfig
deleted file mode 100644
index b535ca869..000000000
--- a/nuttx/configs/olimex-lpc1766stk/nsh/appconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-############################################################################
-# configs/olimex-lpc1766stk/nsh/appconfig
-#
-#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-# Path to example in apps/examples containing the user_start entry point
-
-CONFIGURED_APPS += examples/nsh
-
-# NSH library
-
-CONFIGURED_APPS += system/readline
-CONFIGURED_APPS += nshlib
-
-# Networking support
-
-ifeq ($(CONFIG_NET),y)
-CONFIGURED_APPS += netutils/uiplib
-CONFIGURED_APPS += netutils/dhcpc
-CONFIGURED_APPS += netutils/resolv
-CONFIGURED_APPS += netutils/tftpc
-CONFIGURED_APPS += netutils/webclient
-ifeq ($(CONFIG_NSH_TELNET),y)
-CONFIGURED_APPS += netutils/telnetd
-endif
-endif
-
-ifeq ($(CONFIG_ARCH_BUTTONS),y)
-CONFIGURED_APPS += examples/buttons
-endif
-
-ifeq ($(CONFIG_CAN),y)
-CONFIGURED_APPS += examples/can
-endif
-
-
diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig
index c096cdb0e..0f16933b8 100755
--- a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig
+++ b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig
@@ -1,255 +1,292 @@
-############################################################################
-# configs/olimex-lpc1766stk/nsh/defconfig
-#
-#   Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-#
-# Architecture Selection
 #
-CONFIG_ARCH="arm"
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+CONFIG_NUTTX_NEWCONFIG=y
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+# CONFIG_APPS_DIR="../apps"
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+CONFIG_INTELHEX_BINARY=y
+# CONFIG_MOTOROLA_SREC is not set
+# CONFIG_RAW_BINARY is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_SYMBOLS is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_8051 is not set
 CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_IMX is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+# CONFIG_ARCH_CHIP_LM is not set
+CONFIG_ARCH_CHIP_LPC17XX=y
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_SAM3U is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
 CONFIG_ARCH_CORTEXM3=y
+CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="lpc17xx"
-CONFIG_ARCH_CHIP_LPC17XX=y
-CONFIG_ARCH_CHIP_LPC1766=y
-CONFIG_ARCH_BOARD="olimex-lpc1766stk"
-CONFIG_ARCH_BOARD_LPC1766STK=y
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARMV7M_MPU is not set
 CONFIG_BOARD_LOOPSPERMSEC=8111
-CONFIG_DRAM_SIZE=32768
-CONFIG_DRAM_START=0x10000000
-CONFIG_ARCH_IRQPRIO=y
-CONFIG_ARCH_INTERRUPTSTACK=0
-CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARCH_BOOTLOADER=n
-CONFIG_ARCH_LEDS=y
-CONFIG_ARCH_BUTTONS=n
-CONFIG_ARCH_CALIBRATION=n
-CONFIG_ARCH_DMA=n
+# CONFIG_ARCH_CALIBRATION is not set
 
 #
-# Identify toolchain and linker options
+# ARMV7M Configuration Options
 #
-CONFIG_LPC17_CODESOURCERYW=n
-CONFIG_LPC17_CODESOURCERYL=n
-CONFIG_LPC17_DEVKITARM=n
-CONFIG_LPC17_BUILDROOT=y
+CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set
+CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 
 #
-# Individual subsystems can be enabled:
+# LPC17xx Configuration Options
 #
+# CONFIG_ARCH_CHIP_LPC1751 is not set
+# CONFIG_ARCH_CHIP_LPC1752 is not set
+# CONFIG_ARCH_CHIP_LPC1754 is not set
+# CONFIG_ARCH_CHIP_LPC1756 is not set
+# CONFIG_ARCH_CHIP_LPC1758 is not set
+# CONFIG_ARCH_CHIP_LPC1759 is not set
+# CONFIG_ARCH_CHIP_LPC1764 is not set
+# CONFIG_ARCH_CHIP_LPC1765 is not set
+CONFIG_ARCH_CHIP_LPC1766=y
+# CONFIG_ARCH_CHIP_LPC1767 is not set
+# CONFIG_ARCH_CHIP_LPC1768 is not set
+# CONFIG_ARCH_CHIP_LPC1769 is not set
+# CONFIG_ARCH_CHIP_LPC1773 is not set
+# CONFIG_ARCH_CHIP_LPC1774 is not set
+# CONFIG_ARCH_CHIP_LPC1776 is not set
+# CONFIG_ARCH_CHIP_LPC1777 is not set
+# CONFIG_ARCH_CHIP_LPC1778 is not set
+# CONFIG_ARCH_CHIP_LPC1785 is not set
+# CONFIG_ARCH_CHIP_LPC1786 is not set
+# CONFIG_ARCH_CHIP_LPC1787 is not set
+# CONFIG_ARCH_CHIP_LPC1788 is not set
+CONFIG_ARCH_FAMILY_LPC176X=y
+
+#
+# LPC17xx Peripheral Support
+#
+CONFIG_LPC17_MAINOSC=y
+CONFIG_LPC17_PLL0=y
+CONFIG_LPC17_PLL1=y
 CONFIG_LPC17_ETHERNET=y
-CONFIG_LPC17_USBHOST=n
-CONFIG_LPC17_USBOTG=n
-CONFIG_LPC17_USBDEV=n
+# CONFIG_LPC17_USBHOST is not set
+# CONFIG_LPC17_USBDEV is not set
 CONFIG_LPC17_UART0=y
-CONFIG_LPC17_UART1=n
-CONFIG_LPC17_UART2=n
-CONFIG_LPC17_UART3=n
-CONFIG_LPC17_CAN1=n
-CONFIG_LPC17_CAN2=n
-CONFIG_LPC17_SPI=n
-CONFIG_LPC17_SSP0=n
+# CONFIG_LPC17_UART1 is not set
+# CONFIG_LPC17_UART2 is not set
+# CONFIG_LPC17_UART3 is not set
+# CONFIG_LPC17_CAN1 is not set
+# CONFIG_LPC17_CAN2 is not set
+# CONFIG_LPC17_SPI is not set
+# CONFIG_LPC17_SSP0 is not set
 CONFIG_LPC17_SSP1=y
-CONFIG_LPC17_I2C0=n
-CONFIG_LPC17_I2C1=n
-CONFIG_LPC17_I2S=n
-CONFIG_LPC17_TMR0=n
-CONFIG_LPC17_TMR1=n
-CONFIG_LPC17_TMR2=n
-CONFIG_LPC17_TMR3=n
-CONFIG_LPC17_RIT=n
-CONFIG_LPC17_PWM=n
-CONFIG_LPC17_MCPWM=n
-CONFIG_LPC17_QEI=n
-CONFIG_LPC17_RTC=n
-CONFIG_LPC17_WDT=n
-CONFIG_LPC17_ADC=n
-CONFIG_LPC17_DAC=n
-CONFIG_LPC17_GPDMA=n
+# CONFIG_LPC17_I2C0 is not set
+# CONFIG_LPC17_I2C1 is not set
+# CONFIG_LPC17_I2C2 is not set
+# CONFIG_LPC17_I2S is not set
+# CONFIG_LPC17_TMR0 is not set
+# CONFIG_LPC17_TMR1 is not set
+# CONFIG_LPC17_TMR2 is not set
+# CONFIG_LPC17_TMR3 is not set
+# CONFIG_LPC17_RIT is not set
+# CONFIG_LPC17_PWM is not set
+# CONFIG_LPC17_MCPWM is not set
+# CONFIG_LPC17_QEI is not set
+# CONFIG_LPC17_RTC is not set
+# CONFIG_LPC17_WDT is not set
+# CONFIG_LPC17_ADC is not set
+# CONFIG_LPC17_DAC is not set
+# CONFIG_LPC17_GPDMA is not set
+# CONFIG_LPC17_FLASH is not set
 
 #
-# LPC17xx Button interrupt support
+# Serial driver options
 #
-CONFIG_GPIO_IRQ=n
-CONFIG_ARCH_IRQBUTTONS=n
+# CONFIG_SERIAL_TERMIOS is not set
+# CONFIG_UART0_FLOWCONTROL is not set
 
 #
-# LPC17xx specific serial device driver settings
+# ADC driver options
 #
-CONFIG_UART0_SERIAL_CONSOLE=y
-CONFIG_UART1_SERIAL_CONSOLE=n
-CONFIG_UART2_SERIAL_CONSOLE=n
-CONFIG_UART3_SERIAL_CONSOLE=n
-
-CONFIG_UART0_TXBUFSIZE=256
-CONFIG_UART1_TXBUFSIZE=256
-CONFIG_UART2_TXBUFSIZE=256
-CONFIG_UART3_TXBUFSIZE=256
-
-CONFIG_UART0_RXBUFSIZE=256
-CONFIG_UART1_RXBUFSIZE=256
-CONFIG_UART2_RXBUFSIZE=256
-CONFIG_UART3_RXBUFSIZE=256
 
-CONFIG_UART0_BAUD=57600
-CONFIG_UART2_BAUD=57600
-CONFIG_UART3_BAUD=57600
-CONFIG_UART1_BAUD=57600
-
-CONFIG_UART0_BITS=8
-CONFIG_UART1_BITS=8
-CONFIG_UART2_BITS=8
-CONFIG_UART3_BITS=8
-
-CONFIG_UART0_PARITY=0
-CONFIG_UART1_PARITY=0
-CONFIG_UART2_PARITY=0
-CONFIG_UART3_PARITY=0
+#
+# CAN driver options
+#
+# CONFIG_GPIO_IRQ is not set
 
-CONFIG_UART0_2STOP=0
-CONFIG_UART1_2STOP=0
-CONFIG_UART2_2STOP=0
-CONFIG_UART3_2STOP=0
+#
+# I2C driver options
+#
 
 #
-# LPC17xx specific PHY/Ethernet device driver settings
+# Ethernet driver options
 #
-CONFIG_PHY_KS8721=y
 CONFIG_PHY_AUTONEG=y
-CONFIG_PHY_SPEED100=n
-CONFIG_PHY_FDUPLEX=y
 CONFIG_NET_EMACRAM_SIZE=8192
 CONFIG_NET_NTXDESC=7
 CONFIG_NET_NRXDESC=7
-CONFIG_NET_REGDEBUG=n
+CONFIG_NET_PRIORITY=0
+# CONFIG_NET_WOL is not set
+# CONFIG_NET_HASH is not set
+# CONFIG_NET_MULTICAST is not set
 
 #
-# General build options
+# USB device driver options
 #
-CONFIG_RRLOAD_BINARY=n
-CONFIG_INTELHEX_BINARY=y
-CONFIG_MOTOROLA_SREC=n
-CONFIG_RAW_BINARY=n
 
 #
-# General OS setup
+# USB host driver options
 #
-CONFIG_USER_ENTRYPOINT="nsh_main"
-CONFIG_DEBUG=n
-CONFIG_DEBUG_VERBOSE=n
-CONFIG_DEBUG_SYMBOLS=n
-CONFIG_DEBUG_NET=n
-CONFIG_DEBUG_USB=n
-CONFIG_DEBUG_GPIO=n
-CONFIG_DEBUG_CAN=n
-CONFIG_MM_REGIONS=2
-CONFIG_ARCH_LOWPUTC=y
-CONFIG_RR_INTERVAL=200
-CONFIG_SCHED_INSTRUMENTATION=n
-CONFIG_TASK_NAME_SIZE=0
-CONFIG_START_YEAR=2011
-CONFIG_START_MONTH=12
-CONFIG_START_DAY=30
-CONFIG_GREGORIAN_TIME=n
-CONFIG_JULIAN_TIME=n
-CONFIG_DEV_CONSOLE=y
-CONFIG_DEV_LOWCONSOLE=n
-CONFIG_MUTEX_TYPES=n
-CONFIG_PRIORITY_INHERITANCE=n
-CONFIG_SEM_PREALLOCHOLDERS=0
-CONFIG_SEM_NNESTPRIO=0
-CONFIG_FDCLONE_DISABLE=n
-CONFIG_FDCLONE_STDIO=n
-CONFIG_SDCLONE_DISABLE=y
-CONFIG_SCHED_WORKQUEUE=n
-CONFIG_SCHED_WORKPRIORITY=192
-CONFIG_SCHED_WORKPERIOD=50000
-CONFIG_SCHED_WORKSTACKSIZE=1024
-CONFIG_SIG_SIGWORK=17
-CONFIG_SCHED_WAITPID=y
-CONFIG_SCHED_ATEXIT=n
 
 #
-# Settings for NXFLAT
+# Architecture Options
 #
-CONFIG_NXFLAT=y
-CONFIG_NXFLAT_DUMPBUFFER=n
-CONFIG_SYMTAB_ORDEREDBYNAME=y
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_VECNOTIRQ is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_IRQPRIO=y
+# CONFIG_CUSTOM_STACK is not set
+# CONFIG_ADDRENV is not set
+CONFIG_ARCH_HAVE_VFORK=y
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
+# CONFIG_ARCH_HAVE_RAMFUNCS is not set
 
 #
-# The following can be used to disable categories of
-# APIs supported by the OS.  If the compiler supports
-# weak functions, then it should not be necessary to
-# disable functions unless you want to restrict usage
-# of those APIs.
+# Board Settings
 #
-# There are certain dependency relationships in these
-# features.
+CONFIG_DRAM_START=0x10000000
+CONFIG_DRAM_SIZE=32768
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+
 #
-# o mq_notify logic depends on signals to awaken tasks
-#   waiting for queues to become full or empty.
-# o pthread_condtimedwait() depends on signals to wake
-#   up waiting tasks.
+# Boot options
 #
-CONFIG_DISABLE_CLOCK=n
-CONFIG_DISABLE_POSIX_TIMERS=n
-CONFIG_DISABLE_PTHREAD=n
-CONFIG_DISABLE_SIGNALS=n
-CONFIG_DISABLE_MQUEUE=n
-CONFIG_DISABLE_MOUNTPOINT=n
-CONFIG_DISABLE_ENVIRON=n
-CONFIG_DISABLE_POLL=y
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
 
 #
-# Misc libc settings
+# Board Selection
 #
-CONFIG_NOPRINTF_FIELDWIDTH=n
+CONFIG_ARCH_BOARD_LPC1766STK=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="olimex-lpc1766stk"
 
 #
-# Allow for architecture optimized implementations
+# Common Board Options
+#
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_HAVE_BUTTONS=y
+# CONFIG_ARCH_BUTTONS is not set
+CONFIG_ARCH_HAVE_IRQBUTTONS=y
+CONFIG_NSH_MMCSDMINOR=0
+CONFIG_NSH_MMCSDSLOTNO=0
+CONFIG_NSH_MMCSDSPIPORTNO=1
+
 #
-# The architecture can provide optimized versions of the
-# following to improve system performance
+# Board-Specific Options
 #
-CONFIG_ARCH_MEMCPY=n
-CONFIG_ARCH_MEMCMP=n
-CONFIG_ARCH_MEMMOVE=n
-CONFIG_ARCH_MEMSET=n
-CONFIG_ARCH_STRCMP=n
-CONFIG_ARCH_STRCPY=n
-CONFIG_ARCH_STRNCPY=n
-CONFIG_ARCH_STRLEN=n
-CONFIG_ARCH_STRNLEN=n
-CONFIG_ARCH_BZERO=n
+
+#
+# RTOS Features
+#
+CONFIG_MSEC_PER_TICK=10
+CONFIG_RR_INTERVAL=200
+# CONFIG_SCHED_INSTRUMENTATION is not set
+CONFIG_TASK_NAME_SIZE=0
+# CONFIG_SCHED_HAVE_PARENT is not set
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2011
+CONFIG_START_MONTH=12
+CONFIG_START_DAY=30
+CONFIG_DEV_CONSOLE=y
+# CONFIG_MUTEX_TYPES is not set
+# CONFIG_PRIORITY_INHERITANCE is not set
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+# CONFIG_SCHED_WORKQUEUE is not set
+CONFIG_SCHED_WAITPID=y
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_CLOCK is not set
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_DISABLE_ENVIRON is not set
+CONFIG_DISABLE_POLL=y
+
+#
+# Signal Numbers
+#
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGALARM=3
+CONFIG_SIG_SIGCONDTIMEDOUT=16
 
 #
 # Sizes of configurable things (0 disables)
@@ -260,9 +297,6 @@ CONFIG_NPTHREAD_KEYS=4
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NAME_MAX=32
-CONFIG_STDIO_BUFFER_SIZE=256
-CONFIG_STDIO_LINEBUFFER=y
-CONFIG_NUNGET_CHARS=2
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_MQ_MAXMSGSIZE=32
 CONFIG_MAX_WDOGPARMS=2
@@ -270,263 +304,426 @@ CONFIG_PREALLOC_WDOGS=4
 CONFIG_PREALLOC_TIMERS=4
 
 #
-# Filesystem configuration
+# Stack and heap information
 #
-CONFIG_FS_FAT=y
-CONFIG_FAT_LCNAMES=y
-CONFIG_FAT_LFN=y
-CONFIG_FAT_MAXFNAME=32
-CONFIG_FS_NXFFS=n
-CONFIG_FS_ROMFS=n
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
 
 #
-# Maintain legacy build behavior (revisit)
-#
-
+# Device Drivers
+#
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_LOOP is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_PWM is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_OWNBUS is not set
+# CONFIG_SPI_EXCHANGE is not set
+# CONFIG_SPI_CMDDATA is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_LCD is not set
 CONFIG_MMCSD=y
+CONFIG_MMCSD_NSLOTS=1
+# CONFIG_MMCSD_READONLY is not set
+# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set
+# CONFIG_MMCSD_MMCSUPPORT is not set
+# CONFIG_MMCSD_HAVECARDDETECT is not set
 CONFIG_MMCSD_SPI=y
-CONFIG_MTD=y
+CONFIG_MMCSD_SPICLOCK=12500000
+# CONFIG_MMCSD_SDIO is not set
+# CONFIG_MTD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_NET_SLIP is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+CONFIG_ARCH_HAVE_UART0=y
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_NO_SERIAL_CONSOLE is not set
 
 #
-# SPI-based MMC/SD driver
+# UART0 Configuration
 #
-CONFIG_MMCSD_NSLOTS=1
-CONFIG_MMCSD_READONLY=n
-CONFIG_MMCSD_SPICLOCK=12500000
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART0_BAUD=57600
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_WIRELESS is not set
 
 #
-# Block driver buffering
+# System Logging Device Options
 #
-CONFIG_FS_READAHEAD=n
-CONFIG_FS_WRITEBUFFER=n
 
 #
-# SDIO-based MMC/SD driver
+# System Logging
 #
-CONFIG_SDIO_DMA=n
-CONFIG_MMCSD_MMCSUPPORT=n
-CONFIG_MMCSD_HAVECARDDETECT=n
+# CONFIG_RAMLOG is not set
 
 #
-# TCP/IP and UDP support via uIP
+# Networking Support
 #
 CONFIG_NET=y
-CONFIG_NET_IPv6=n
+CONFIG_ARCH_HAVE_PHY=y
+CONFIG_PHY_KS8721=y
+# CONFIG_PHY_DP83848C is not set
+# CONFIG_PHY_LAN8720 is not set
+# CONFIG_PHY_DM9161 is not set
+# CONFIG_NET_NOINTS is not set
+# CONFIG_NET_MULTIBUFFER is not set
+# CONFIG_NET_IPv6 is not set
 CONFIG_NSOCKET_DESCRIPTORS=8
+CONFIG_NET_NACTIVESOCKETS=16
 CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_BUFSIZE=562
+# CONFIG_NET_TCPURGDATA is not set
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_CONNS=8
-CONFIG_NET_NTCP_READAHEAD_BUFFERS=16
-CONFIG_NET_TCPBACKLOG=n
 CONFIG_NET_MAX_LISTENPORTS=8
+CONFIG_NET_TCP_READAHEAD_BUFSIZE=562
+CONFIG_NET_NTCP_READAHEAD_BUFFERS=16
+CONFIG_NET_TCP_RECVDELAY=0
+# CONFIG_NET_TCPBACKLOG is not set
 CONFIG_NET_UDP=y
 CONFIG_NET_UDP_CHECKSUMS=y
-#CONFIG_NET_UDP_CONNS=8
+CONFIG_NET_UDP_CONNS=8
+# CONFIG_NET_BROADCAST is not set
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_PING=y
-#CONFIG_NET_PINGADDRCONF=0
-CONFIG_NET_STATISTICS=n
-#CONFIG_NET_RECEIVE_WINDOW=
-#CONFIG_NET_ARPTAB_SIZE=8
-CONFIG_NET_BROADCAST=n
+# CONFIG_NET_PINGADDRCONF is not set
+# CONFIG_NET_IGMP is not set
+# CONFIG_NET_STATISTICS is not set
+CONFIG_NET_RECEIVE_WINDOW=562
+CONFIG_NET_ARPTAB_SIZE=16
+# CONFIG_NET_ARP_IPIN is not set
 
 #
-# UIP Network Utilities
+# File Systems
 #
-CONFIG_NET_DHCP_LIGHT=n
-CONFIG_NET_RESOLV_ENTRIES=4
 
 #
-# CAN device driver settings
+# File system configuration
 #
-CONFIG_CAN=n
-CONFIG_CAN_EXTID=n
-#CONFIG_CAN_FIFOSIZE
-#CONFIG_CAN_NPENDINGRTR
-CONFIG_CAN_LOOPBACK=n
-CONFIG_CAN_REGDEBUG=n
-CONFIG_CAN1_BAUD=700000
-CONFIG_CAN2_BAUD=700000
+# CONFIG_FS_RAMMAP is not set
+CONFIG_FS_FAT=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FAT_LFN=y
+CONFIG_FAT_MAXFNAME=32
+# CONFIG_FS_FATTIME is not set
+# CONFIG_FAT_DMAMEMORY is not set
+# CONFIG_NFS is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+# CONFIG_FS_BINFS is not set
 
 #
-# USB Device Configuration
+# System Logging
 #
-CONFIG_USBDEV=n
-CONFIG_USBDEV_ISOCHRONOUS=n
-CONFIG_USBDEV_DUALSPEED=n
-CONFIG_USBDEV_SELFPOWERED=y
-CONFIG_USBDEV_REMOTEWAKEUP=n
-CONFIG_USBDEV_MAXPOWER=100
-CONFIG_USBDEV_TRACE=n
-CONFIG_USBDEV_TRACE_NRECORDS=128
+# CONFIG_SYSLOG is not set
 
 #
-# USB Host Configuration
+# Graphics Support
 #
-CONFIG_USBHOST=n
-CONFIG_USBHOST_NPREALLOC=0
-CONFIG_USBHOST_BULK_DISABLE=n
-CONFIG_USBHOST_INT_DISABLE=y
-CONFIG_USBHOST_ISOC_DISABLE=y
+# CONFIG_NX is not set
 
 #
-# LPC17xx USB Device Configuration
+# Memory Management
 #
-CONFIG_LPC17_USBDEV_FRAME_INTERRUPT=n
-CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT=n
-CONFIG_LPC17_USBDEV_DMA=n
-CONFIG_LPC17_USBDEV_NDMADESCRIPTORS=0
-CONFIG_LPC17_USBDEV_DMAINTMASK=0
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=2
+# CONFIG_GRAN is not set
 
 #
-# LPC17xx USB Host Configuration
+# Binary Formats
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+CONFIG_NXFLAT=y
+# CONFIG_ELF is not set
+CONFIG_BUILTIN=y
+CONFIG_PIC=y
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+
 #
-# OHCI RAM layout:
+# Library Routines
 #
-CONFIG_USBHOST_OHCIRAM_SIZE=1536
-CONFIG_USBHOST_NEDS=2
-CONFIG_USBHOST_NTDS=3
-CONFIG_USBHOST_TDBUFFERS=3
-CONFIG_USBHOST_TDBUFSIZE=128
-CONFIG_USBHOST_IOBUFSIZE=512
 
 #
-# USB Serial Device Configuration
+# Standard C Library Options
 #
-CONFIG_PL2303=n
-CONFIG_PL2303_EPINTIN=1
-CONFIG_PL2303_EPBULKOUT=2
-CONFIG_PL2303_EPBULKIN=5
-CONFIG_PL2303_NWRREQS=4
-CONFIG_PL2303_NRDREQS=4
-CONFIG_PL2303_VENDORID=0x067b
-CONFIG_PL2303_PRODUCTID=0x2303
-CONFIG_PL2303_VENDORSTR="Nuttx"
-CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
-CONFIG_PL2303_RXBUFSIZE=512
-CONFIG_PL2303_TXBUFSIZE=512
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_EXECFUNCS is not set
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
 
 #
-# USB Storage Device Configuration
+# Non-standard Helper Functions
 #
-CONFIG_USBMSC=n
-CONFIG_USBMSC_EP0MAXPACKET=64
-CONFIG_USBMSC_EPBULKOUT=2
-CONFIG_USBMSC_EPBULKIN=5
-CONFIG_USBMSC_NRDREQS=2
-CONFIG_USBMSC_NWRREQS=2
-CONFIG_USBMSC_BULKINREQLEN=256
-CONFIG_USBMSC_BULKOUTREQLEN=256
-CONFIG_USBMSC_VENDORID=0x584e
-CONFIG_USBMSC_VENDORSTR="NuttX"
-CONFIG_USBMSC_PRODUCTID=0x5342
-CONFIG_USBMSC_PRODUCTSTR="USBdev Storage"
-CONFIG_USBMSC_VERSIONNO=0x0399
-CONFIG_USBMSC_REMOVABLE=y
+# CONFIG_LIB_KBDCODEC is not set
 
 #
-# Settings for examples/uip
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
+
+#
+# Application Configuration
 #
-CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002
-CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00
-CONFIG_EXAMPLES_UIP_DHCPC=n
 
 #
-# Settings for examples/nettest
+# Built-In Applications
 #
-CONFIG_EXAMPLES_NETTEST_SERVER=n
-CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n
-CONFIG_EXAMPLES_NETTEST_NOMAC=y
-CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
-CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
-CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
-CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
+CONFIG_BUILTIN_PROXY_STACKSIZE=1024
 
 #
-# Settings for examples/ostest
+# Examples
 #
-CONFIG_EXAMPLES_OSTEST_LOOPS=1
-CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048
-CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CDCACM is not set
+# CONFIG_EXAMPLES_COMPOSITE is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_LCDRW is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_NETTEST is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXCONSOLE is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXFLAT is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PASHELLO is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_QENCODER is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UDP is not set
+# CONFIG_EXAMPLES_DISCOVER is not set
+# CONFIG_EXAMPLES_UIP is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBMSC is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
 
 #
-# Settings for examples/buttons
+# Interpreters
 #
-CONFIG_EXAMPLES_BUTTONS_MIN=0
-CONFIG_EXAMPLES_BUTTONS_MAX=7
-CONFIG_EXAMPLES_IRQBUTTONS_MIN=0
-CONFIG_EXAMPLES_IRQBUTTONS_MAX=7
-CONFIG_EXAMPLES_BUTTONS_NAME0="BUT1"
-CONFIG_EXAMPLES_BUTTONS_NAME1="BUT2"
-CONFIG_EXAMPLES_BUTTONS_NAME2="WAKE-UP"
-CONFIG_EXAMPLES_BUTTONS_NAME3="CENTER"
-CONFIG_EXAMPLES_BUTTONS_NAME4="UP"
-CONFIG_EXAMPLES_BUTTONS_NAME5="DOWN"
-CONFIG_EXAMPLES_BUTTONS_NAME6="LEFT"
-CONFIG_EXAMPLES_BUTTONS_NAME7="RIGHT"
 
 #
-# Settings for apps/nshlib
+# Interpreters
 #
-CONFIG_BUILTIN=y
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+
+#
+# Network Utilities
+#
+
+#
+# Networking Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+CONFIG_NETUTILS_DHCPC=y
+# CONFIG_NETUTILS_DHCPD is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_FTPD is not set
+# CONFIG_NETUTILS_JSON is not set
+CONFIG_NETUTILS_RESOLV=y
+CONFIG_NET_RESOLV_ENTRIES=8
+CONFIG_NET_RESOLV_MAXRESPONSE=96
+# CONFIG_NETUTILS_SMTP is not set
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NETUTILS_TFTPC=y
+# CONFIG_NETUTILS_THTTPD is not set
+CONFIG_NETUTILS_UIPLIB=y
+CONFIG_NETUTILS_WEBCLIENT=y
+CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)"
+# CONFIG_NETUTILS_WEBSERVER is not set
+# CONFIG_NETUTILS_DISCOVER is not set
+# CONFIG_NETUTILS_XMLRPC is not set
+
+#
+# ModBus
+#
+
+#
+# FreeModbus
+#
+# CONFIG_MODBUS is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_BUILTIN_APPS=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFATFS is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_NSFMOUNT is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PING is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+CONFIG_NSH_CODECS_BUFSIZE=128
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_STRERROR=n
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_NESTDEPTH=3
-CONFIG_NSH_DISABLESCRIPT=n
-CONFIG_NSH_DISABLEBG=n
-CONFIG_NSH_ROMFSETC=n
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLEBG is not set
 CONFIG_NSH_CONSOLE=y
-CONFIG_NSH_TELNET=y
+# CONFIG_NSH_CONDEV is not set
 CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_TELNET=y
+CONFIG_NSH_TELNETD_PORT=23
+CONFIG_NSH_TELNETD_DAEMONPRIO=100
+CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048
+CONFIG_NSH_TELNETD_CLIENTPRIO=100
+CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048
 CONFIG_NSH_IOBUFFER_SIZE=512
-CONFIG_NSH_DHCPC=n
-CONFIG_NSH_NOMAC=y
+# CONFIG_NSH_TELNET_LOGIN is not set
 CONFIG_NSH_IPADDR=0x0a000002
 CONFIG_NSH_DRIPADDR=0x0a000001
 CONFIG_NSH_NETMASK=0xffffff00
-CONFIG_NSH_ROMFSMOUNTPT="/etc"
-CONFIG_NSH_INITSCRIPT="init.d/rcS"
-CONFIG_NSH_ROMFSDEVNO=0
-CONFIG_NSH_ROMFSSECTSIZE=64
-CONFIG_NSH_FATDEVNO=1
-CONFIG_NSH_FATSECTSIZE=512
-CONFIG_NSH_FATNSECTORS=1024
-CONFIG_NSH_FATMOUNTPT="/tmp"
+CONFIG_NSH_NOMAC=y
+CONFIG_NSH_MAX_ROUNDTRIP=20
 
 #
-# Architecture-specific NSH options
+# NxWidgets/NxWM
+#
+
+#
+# System NSH Add-Ons
 #
-CONFIG_NSH_MMCSDSPIPORTNO=1
-CONFIG_NSH_MMCSDSLOTNO=0
-CONFIG_NSH_MMCSDMINOR=0
 
 #
-# Settings for examples/usbserial
+# Custom Free Memory Command
 #
-CONFIG_EXAMPLES_USBSERIAL_INONLY=n
-CONFIG_EXAMPLES_USBSERIAL_OUTONLY=n
-CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL=n
-CONFIG_EXAMPLES_USBSERIAL_ONLYBIG=n
+# CONFIG_SYSTEM_FREE is not set
 
-CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n
-CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n
-CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n
-CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n
-CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
+#
+# I2C tool
+#
 
 #
-# Stack and heap information
+# FLASH Program Installation
 #
-CONFIG_BOOT_RUNFROMFLASH=n
-CONFIG_BOOT_COPYTORAM=n
-CONFIG_CUSTOM_STACK=n
-CONFIG_IDLETHREAD_STACKSIZE=1024
-CONFIG_USERMAIN_STACKSIZE=2048
-CONFIG_PTHREAD_STACK_MIN=256
-CONFIG_PTHREAD_STACK_DEFAULT=2048
-CONFIG_HEAP_BASE=
-CONFIG_HEAP_SIZE=
+# CONFIG_SYSTEM_INSTALL is not set
+
+#
+# readline()
+#
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+
+#
+# Power Off
+#
+# CONFIG_SYSTEM_POWEROFF is not set
+
+#
+# RAMTRON
+#
+# CONFIG_SYSTEM_RAMTRON is not set
+
+#
+# SD Card
+#
+# CONFIG_SYSTEM_SDCARD is not set
+
+#
+# Sysinfo
+#
+# CONFIG_SYSTEM_SYSINFO is not set
diff --git a/nuttx/drivers/mmcsd/Kconfig b/nuttx/drivers/mmcsd/Kconfig
index 5cdc23bcf..2d9a04bbb 100644
--- a/nuttx/drivers/mmcsd/Kconfig
+++ b/nuttx/drivers/mmcsd/Kconfig
@@ -53,7 +53,7 @@ config MMCSD_SPICLOCK
 
 config MMCSD_SDIO
 	bool "MMC/SD sdio transfer support"
-	default y
+	default n
 
 if MMCSD_SDIO
 config SDIO_DMA
diff --git a/nuttx/sched/Makefile b/nuttx/sched/Makefile
index 73c67239e..38d3e047f 100644
--- a/nuttx/sched/Makefile
+++ b/nuttx/sched/Makefile
@@ -35,166 +35,172 @@
 
 -include $(TOPDIR)/Make.defs
 
-ASRCS		= 
-AOBJS		= $(ASRCS:.S=$(OBJEXT))
-
-MISC_SRCS	= os_start.c os_bringup.c errno_getptr.c errno_get.c errno_set.c \
-		  sched_garbage.c sched_setupstreams.c sched_getfiles.c sched_getsockets.c \
-		  sched_getstreams.c sched_setupidlefiles.c sched_setuptaskfiles.c \
-		  sched_setuppthreadfiles.c sched_releasefiles.c
-
-TSK_SRCS	= prctl.c task_create.c task_init.c task_setup.c task_activate.c \
-		  task_start.c task_delete.c task_deletecurrent.c task_exithook.c \
-		  task_restart.c task_vfork.c exit.c getpid.c sched_addreadytorun.c \
-		  sched_removereadytorun.c sched_addprioritized.c sched_mergepending.c \
-		  sched_addblocked.c sched_removeblocked.c sched_free.c sched_gettcb.c \
-		  sched_verifytcb.c sched_releasetcb.c task_posixspawn.c
-
-SCHED_SRCS	= sched_setparam.c sched_setpriority.c sched_getparam.c \
-		  sched_setscheduler.c sched_getscheduler.c \
-		  sched_yield.c sched_rrgetinterval.c sched_foreach.c \
-		  sched_lock.c sched_unlock.c sched_lockcount.c sched_self.c
+ASRCS = 
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+
+MISC_SRCS  = os_start.c os_bringup.c errno_getptr.c errno_get.c errno_set.c
+MISC_SRCS += sched_garbage.c sched_setupstreams.c sched_getfiles.c sched_getsockets.c
+MISC_SRCS += sched_getstreams.c sched_setupidlefiles.c sched_setuptaskfiles.c
+MISC_SRCS += sched_setuppthreadfiles.c sched_releasefiles.c
+
+TSK_SRCS = prctl.c task_create.c task_init.c task_setup.c task_activate.c
+TSK_SRCS += task_start.c task_delete.c task_deletecurrent.c task_exithook.c
+TSK_SRCS += task_restart.c task_vfork.c exit.c getpid.c sched_addreadytorun.c
+TSK_SRCS += sched_removereadytorun.c sched_addprioritized.c sched_mergepending.c
+TSK_SRCS += sched_addblocked.c sched_removeblocked.c sched_free.c sched_gettcb.c
+TSK_SRCS += sched_verifytcb.c sched_releasetcb.c
+
+ifneq ($(CONFIG_BINFMT_DISABLE),y)
+ifeq ($(CONFIG_LIBC_EXECFUNCS),y)
+TSK_SRCS += task_posixspawn.c
+endif
+endif
+
+SCHED_SRCS = sched_setparam.c sched_setpriority.c sched_getparam.c
+SCHED_SRCS += sched_setscheduler.c sched_getscheduler.c
+SCHED_SRCS += sched_yield.c sched_rrgetinterval.c sched_foreach.c
+SCHED_SRCS += sched_lock.c sched_unlock.c sched_lockcount.c sched_self.c
 
 ifeq ($(CONFIG_SCHED_ATEXIT),y)
-SCHED_SRCS	+= atexit.c 
+SCHED_SRCS += atexit.c 
 endif
 
 ifeq ($(CONFIG_SCHED_ONEXIT),y)
-SCHED_SRCS	+= on_exit.c 
+SCHED_SRCS += on_exit.c 
 endif
 
 ifeq ($(CONFIG_PRIORITY_INHERITANCE),y)
-SCHED_SRCS	+= sched_reprioritize.c 
+SCHED_SRCS += sched_reprioritize.c 
 endif
 
 ifeq ($(CONFIG_SCHED_HAVE_PARENT),y)
-SCHED_SRCS	+= task_reparent.c 
+SCHED_SRCS += task_reparent.c 
 endif
 
 ifeq ($(CONFIG_SCHED_WAITPID),y)
-SCHED_SRCS	+= sched_waitpid.c
+SCHED_SRCS += sched_waitpid.c
 ifeq ($(CONFIG_SCHED_HAVE_PARENT),y)
-SCHED_SRCS	+= sched_waitid.c sched_wait.c
+SCHED_SRCS += sched_waitid.c sched_wait.c
 endif
 endif
 
-ENV_SRCS	= env_getenvironptr.c env_dup.c env_share.c env_release.c \
-		  env_findvar.c env_removevar.c \
-		  env_clearenv.c env_getenv.c env_putenv.c env_setenv.c env_unsetenv.c
+ENV_SRCS  = env_getenvironptr.c env_dup.c env_share.c env_release.c
+ENV_SRCS += env_findvar.c env_removevar.c
+ENV_SRCS += env_clearenv.c env_getenv.c env_putenv.c env_setenv.c env_unsetenv.c
 
-WDOG_SRCS	= wd_initialize.c wd_create.c wd_start.c wd_cancel.c wd_delete.c \
-		  wd_gettime.c
+WDOG_SRCS = wd_initialize.c wd_create.c wd_start.c wd_cancel.c wd_delete.c
+WDOG_SRCS += wd_gettime.c
 
-TIME_SRCS	= sched_processtimer.c
+TIME_SRCS = sched_processtimer.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-TIME_SRCS	+= sleep.c usleep.c
+TIME_SRCS += sleep.c usleep.c
 endif
 
-CLOCK_SRCS	= clock_initialize.c clock_settime.c clock_gettime.c clock_getres.c \
-		  clock_time2ticks.c clock_abstime2ticks.c clock_ticks2time.c \
-		  clock_gettimeofday.c clock_systimer.c
+CLOCK_SRCS  = clock_initialize.c clock_settime.c clock_gettime.c clock_getres.c
+CLOCK_SRCS += clock_time2ticks.c clock_abstime2ticks.c clock_ticks2time.c
+CLOCK_SRCS += clock_gettimeofday.c clock_systimer.c
 
-SIGNAL_SRCS	= sig_initialize.c \
-		  sig_action.c sig_procmask.c sig_pending.c sig_suspend.c \
-		  sig_kill.c sig_queue.c sig_waitinfo.c sig_timedwait.c \
-		  sig_findaction.c sig_allocatependingsigaction.c \
-		  sig_releasependingsigaction.c sig_unmaskpendingsignal.c \
-		  sig_removependingsignal.c sig_releasependingsignal.c sig_lowest.c \
-		  sig_mqnotempty.c sig_cleanup.c sig_received.c sig_deliver.c pause.c
+SIGNAL_SRCS  = sig_initialize.c
+SIGNAL_SRCS += sig_action.c sig_procmask.c sig_pending.c sig_suspend.c
+SIGNAL_SRCS += sig_kill.c sig_queue.c sig_waitinfo.c sig_timedwait.c
+SIGNAL_SRCS += sig_findaction.c sig_allocatependingsigaction.c
+SIGNAL_SRCS += sig_releasependingsigaction.c sig_unmaskpendingsignal.c
+SIGNAL_SRCS += sig_removependingsignal.c sig_releasependingsignal.c sig_lowest.c
+SIGNAL_SRCS += sig_mqnotempty.c sig_cleanup.c sig_received.c sig_deliver.c pause.c
 
-MQUEUE_SRCS	= mq_open.c mq_close.c mq_unlink.c mq_send.c mq_timedsend.c\
-		  mq_sndinternal.c mq_receive.c mq_timedreceive.c mq_rcvinternal.c \
-		  mq_initialize.c mq_descreate.c mq_findnamed.c mq_msgfree.c mq_msgqfree.c
+MQUEUE_SRCS  = mq_open.c mq_close.c mq_unlink.c mq_send.c mq_timedsend.c
+MQUEUE_SRCS += mq_sndinternal.c mq_receive.c mq_timedreceive.c mq_rcvinternal.c
+MQUEUE_SRCS += mq_initialize.c mq_descreate.c mq_findnamed.c mq_msgfree.c mq_msgqfree.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-MQUEUE_SRCS	+= mq_waitirq.c
+MQUEUE_SRCS += mq_waitirq.c
 endif
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-MQUEUE_SRCS	+= mq_notify.c
+MQUEUE_SRCS += mq_notify.c
 endif
 
-PTHREAD_SRCS = pthread_create.c pthread_exit.c pthread_join.c pthread_detach.c \
-		  pthread_yield.c pthread_getschedparam.c pthread_setschedparam.c \
-		  pthread_mutexinit.c pthread_mutexdestroy.c \
-		  pthread_mutexlock.c pthread_mutextrylock.c pthread_mutexunlock.c \
-		  pthread_condinit.c pthread_conddestroy.c \
-		  pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c \
-		  pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c \
-		  pthread_cancel.c pthread_setcancelstate.c \
-		  pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c pthread_keydelete.c \
-		  pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c \
-		  pthread_removejoininfo.c pthread_once.c pthread_setschedprio.c
+PTHREAD_SRCS  = pthread_create.c pthread_exit.c pthread_join.c pthread_detach.c
+PTHREAD_SRCS += pthread_yield.c pthread_getschedparam.c pthread_setschedparam.c
+PTHREAD_SRCS += pthread_mutexinit.c pthread_mutexdestroy.c
+PTHREAD_SRCS += pthread_mutexlock.c pthread_mutextrylock.c pthread_mutexunlock.c
+PTHREAD_SRCS += pthread_condinit.c pthread_conddestroy.c
+PTHREAD_SRCS += pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c
+PTHREAD_SRCS += pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c
+PTHREAD_SRCS += pthread_cancel.c pthread_setcancelstate.c
+PTHREAD_SRCS += pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c pthread_keydelete.c
+PTHREAD_SRCS += pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c
+PTHREAD_SRCS += pthread_removejoininfo.c pthread_once.c pthread_setschedprio.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-PTHREAD_SRCS	+= pthread_condtimedwait.c pthread_kill.c pthread_sigmask.c
+PTHREAD_SRCS += pthread_condtimedwait.c pthread_kill.c pthread_sigmask.c
 endif
 
-SEM_SRCS	= sem_initialize.c sem_destroy.c sem_open.c sem_close.c sem_unlink.c \
-		  sem_wait.c sem_trywait.c sem_timedwait.c sem_post.c sem_findnamed.c
+SEM_SRCS  = sem_initialize.c sem_destroy.c sem_open.c sem_close.c sem_unlink.c
+SEM_SRCS += sem_wait.c sem_trywait.c sem_timedwait.c sem_post.c sem_findnamed.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-SEM_SRCS	+= sem_waitirq.c
+SEM_SRCS += sem_waitirq.c
 endif
 
 ifeq ($(CONFIG_PRIORITY_INHERITANCE),y)
-SEM_SRCS	+= sem_holder.c
+SEM_SRCS += sem_holder.c
 endif
 
 ifneq ($(CONFIG_DISABLE_POSIX_TIMERS),y)
-TIMER_SRCS	= timer_initialize.c timer_create.c timer_delete.c timer_getoverrun.c \
-		  timer_gettime.c timer_settime.c timer_release.c
+TIMER_SRCS += timer_initialize.c timer_create.c timer_delete.c timer_getoverrun.c
+TIMER_SRCS += timer_gettime.c timer_settime.c timer_release.c
 endif
 
 ifeq ($(CONFIG_SCHED_WORKQUEUE),y)
-WORK_SRCS	= work_thread.c work_queue.c work_cancel.c work_signal.c
+WORK_SRCS = work_thread.c work_queue.c work_cancel.c work_signal.c
 endif
 
 ifeq ($(CONFIG_PAGING),y)
-PGFILL_SRCS	= pg_miss.c pg_worker.c
+PGFILL_SRCS = pg_miss.c pg_worker.c
 endif
 
-IRQ_SRCS	= irq_initialize.c irq_attach.c irq_dispatch.c irq_unexpectedisr.c
+IRQ_SRCS = irq_initialize.c irq_attach.c irq_dispatch.c irq_unexpectedisr.c
 
-KMM_SRCS	= kmm_initialize.c kmm_addregion.c kmm_semaphore.c \
-		  kmm_kmalloc.c kmm_kzalloc.c kmm_krealloc.c kmm_kfree.c
+KMM_SRCS = kmm_initialize.c kmm_addregion.c kmm_semaphore.c
+KMM_SRCS = kmm_kmalloc.c kmm_kzalloc.c kmm_krealloc.c kmm_kfree.c
 
-CSRCS		= $(MISC_SRCS) $(TSK_SRCS) $(SCHED_SRCS) $(WDOG_SRCS) $(TIME_SRCS) \
-		  $(SEM_SRCS) $(TIMER_SRCS) $(WORK_SRCS) $(PGFILL_SRCS) $(IRQ_SRCS)
+CSRCS = $(MISC_SRCS) $(TSK_SRCS) $(SCHED_SRCS) $(WDOG_SRCS) $(TIME_SRCS) \
+	    $(SEM_SRCS) $(TIMER_SRCS) $(WORK_SRCS) $(PGFILL_SRCS) $(IRQ_SRCS)
 
 ifneq ($(CONFIG_DISABLE_CLOCK),y)
-CSRCS		+= $(CLOCK_SRCS)
+CSRCS += $(CLOCK_SRCS)
 endif
 
 ifneq ($(CONFIG_DISABLE_PTHREAD),y)
-CSRCS		+= $(PTHREAD_SRCS)
+CSRCS += $(PTHREAD_SRCS)
 endif
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-CSRCS		+= $(SIGNAL_SRCS)
+CSRCS += $(SIGNAL_SRCS)
 endif
 
 ifneq ($(CONFIG_DISABLE_MQUEUE),y)
-CSRCS		+= $(MQUEUE_SRCS)
+CSRCS += $(MQUEUE_SRCS)
 endif
 
 ifneq ($(CONFIG_DISABLE_ENVIRON),y)
-CSRCS		+= $(ENV_SRCS)
+CSRCS += $(ENV_SRCS)
 endif
 
 ifeq ($(CONFIG_NUTTX_KERNEL),y)
-CSRCS		+= $(KMM_SRCS)
+CSRCS += $(KMM_SRCS)
 endif
 
-COBJS		= $(CSRCS:.c=$(OBJEXT))
+COBJS = $(CSRCS:.c=$(OBJEXT))
 
-SRCS		= $(ASRCS) $(CSRCS)
-OBJS		= $(AOBJS) $(COBJS)
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)
 
-BIN		= libsched$(LIBEXT)
+BIN = libsched$(LIBEXT)
 
-all:	$(BIN)
+all: $(BIN)
 .PHONY: context depend clean distclean
 
 $(AOBJS): %$(OBJEXT): %.S
diff --git a/nuttx/sched/os_internal.h b/nuttx/sched/os_internal.h
index f21d9654f..95b42c7ae 100644
--- a/nuttx/sched/os_internal.h
+++ b/nuttx/sched/os_internal.h
@@ -269,7 +269,7 @@ int  task_argsetup(FAR _TCB *tcb, FAR const char *name, FAR const char *argv[]);
 void task_exithook(FAR _TCB *tcb, int status);
 int  task_deletecurrent(void);
 #ifdef CONFIG_SCHED_HAVE_PARENT
-int  task_reparent(pid_t oldpid, pid_t newpid, pid_t chpid);
+int  task_reparent(pid_t ppid, pid_t chpid);
 #endif
 #ifndef CONFIG_CUSTOM_STACK
 int  kernel_thread(FAR const char *name, int priority, int stack_size,
diff --git a/nuttx/sched/task_posixspawn.c b/nuttx/sched/task_posixspawn.c
index 4201e759b..7bb9c9a4d 100644
--- a/nuttx/sched/task_posixspawn.c
+++ b/nuttx/sched/task_posixspawn.c
@@ -40,6 +40,7 @@
 #include <nuttx/config.h>
 
 #include <sys/wait.h>
+#include <unistd.h>
 #include <semaphore.h>
 #include <signal.h>
 #include <sched.h>
@@ -431,7 +432,7 @@ static int spawn_proxy(int argc, char *argv[])
            * What should we do in the event of a failure?
            */
 
-          int tmp = task_reparent(0, 0, *g_ps_parms.pid);
+          int tmp = task_reparent(0, *g_ps_parms.pid);
           if (tmp < 0)
             {
               sdbg("ERROR: task_reparent() failed: %d\n", tmp);
diff --git a/nuttx/sched/task_reparent.c b/nuttx/sched/task_reparent.c
index 9daa0743b..244825f80 100644
--- a/nuttx/sched/task_reparent.c
+++ b/nuttx/sched/task_reparent.c
@@ -60,8 +60,8 @@
  *   Change the parent of a task.
  *
  * Parameters:
- *   oldpid - PID of the old parent task (0 if this task)
- *   newpid - PID ot the new parent task (0 for the parent of this task)
+ *   ppid - PID of the new parent task (0 for grandparent, i.e. the parent
+ *     of the current parent task)
  *   chpid  - PID of the child to be reparented.
  *
  * Return Value:
@@ -69,72 +69,69 @@
  *
  *****************************************************************************/
 
-int task_reparent(pid_t oldpid, pid_t newpid, pid_t chpid)
+int task_reparent(pid_t ppid, pid_t chpid)
 {
-  _TCB *oldtcb;
-  _TCB *newtcb;
+  _TCB *ptcb;
   _TCB *chtcb;
+  _TCB *otcb;
+  pid_t opid;
   irqstate_t flags;
   int ret;
 
-  /* If oldpid is zero, then we are parent task. */
+  /* Disable interrupts so that nothing can change in the relatinoship of
+   * the three task:  Child, current parent, and new parent.
+   */
 
-  if (oldpid == 0)
-    {
-      oldpid = getpid();
-    }
+  flags = irqsave();
 
-  /* Get the current parent task's TCB */
+  /* Get the child tasks TCB (chtcb) */
 
-  oldtcb = sched_gettcb(oldpid);
-  if (!oldtcb)
+  chtcb = sched_gettcb(chpid);
+  if (!chtcb)
     {
-      return -ESRCH;
+      ret = -ECHILD;
+      goto errout_with_ints;
     }
 
-  /* Disable interrupts so that nothing can change from this point */
+  /* Get the PID of the child task's parent (opid) */
 
-  flags = irqsave();
+  opid = chtcb->parent;
 
-  /* If newpid is zero, then new is the parent of oldpid. */
+  /* Get the TCB of the child task's parent (otcb) */
 
-  if (newpid == 0)
-    {
-      newpid = oldtcb->parent;
-    }
-  
-  /* Get the new parent task's TCB */
-
-  newtcb = sched_gettcb(newpid);
-  if (!newtcb)
+  otcb = sched_gettcb(opid);
+  if (!otcb)
     {
       ret = -ESRCH;
       goto errout_with_ints;
     }
 
-  /* Get the child tasks TCB */
+  /* If new parent task's PID (ppid) is zero, then new parent is the
+   * grandparent will be the new parent, i.e., the parent of the current
+   * parent task.
+   */
 
-  chtcb = sched_gettcb(chpid);
-  if (!chtcb)
+  if (ppid == 0)
     {
-      ret = -ECHILD;
-      goto errout_with_ints;
+      ppid = otcb->parent;
     }
+  
+  /* Get the new parent task's TCB (ptcb) */
 
-  /* Verify that oldpid is the parent of chpid */
-
-  if (chtcb->parent != oldpid)
+  ptcb = sched_gettcb(ppid);
+  if (!ptcb)
     {
-      ret = -ECHILD;
+      ret = -ESRCH;
       goto errout_with_ints;
     }
 
-  /* Okay, reparent the child */
+  /* Then reparent the child */
+
+  DEBUGASSERT(otcb->nchildren > 0);
 
-  DEBUGASSERT(oldtcb->nchildren > 0);
-  chtcb->parent = newpid;
-  oldtcb->nchildren--;
-  newtcb->nchildren++;
+  chtcb->parent = ppid;  /* The task specified by ppid is the new parent */
+  otcb->nchildren--;     /* The orignal parent now has one few children */
+  ptcb->nchildren++;     /* The new parent has one additional child */
   ret = OK;
   
 errout_with_ints: