Add RTC and QEI bit definitions

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2721 42af7a65-404d-4744-a932-0658087f49c3

2 files changed, 138 insertions, 187 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h
index 470cd03cc..087e0b8ac 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h
@@ -114,97 +114,66 @@
 #define LPC17_QEI_SET            (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET)

 

 /* Register bit definitions *********************************************************/

-/* Control registers */

+/* The following registers hold 32-bit integer values and have no bit fields defined

+ * in this section:

+ *

+ *   Position register (POS)

+ *   Maximum position register (MAXPOS)

+ *   Position compare register 0 (CMPOS0)

+ *   Position compare register 1 (CMPOS)

+ *   Position compare register 2 (CMPOS2)

+ *   Index count register (INXCNT)

+ *   Index compare register (INXCMP)

+ *   Velocity timer reload register (LOAD)

+ *   Velocity timer register (TIME)

+ *   Velocity counter register (VEL)

+ *   Velocity capture register (CAP)

+ *   Velocity compare register (VELCOMP)

+ *   Digital filter register (FILTER)

+ */

 

+/* Control registers */

 /* Control register */

 

-#define QEI_CON_

-

+#define QEI_CON_RESP             (1 << 0)  /* Bit 0:  Reset position counter */

+#define QEI_CON_RESPI            (1 << 1)  /* Bit 1:  Reset position counter on index */

+#define QEI_CON_RESV             (1 << 2)  /* Bit 2:  Reset velocity */

+#define QEI_CON_RESI             (1 << 3)  /* Bit 3:  Reset index counter */

+                                           /* Bits 4-31: reserved */

 /* Encoder status register */

 

-#define QEI_STAT_

-

+#define QEI_STAT_DIR             (1 << 0)  /* Bit 0:  Direction bit */

+                                           /* Bits 1-31: reserved */

 /* Configuration register */

 

-#define QEI_CONF_

-

-/* Position, index, and timer registers */

-/* Position register */

-

-#define QEI_POS_

-

-/* Maximum position register */

-

-#define QEI_MAXPOS_

-

-/* Position compare register */

-

-#define QEI_CMPOS0_

-

-/* Position compare register */

-

-#define QEI_CMPOS1_

-

-/* Position compare register */

-

-#define QEI_CMPOS2_

-

-/* Index count register */

-

-#define QEI_INXCNT_

-

-/* Index compare register */

-

-#define QEI_INXCMP_

-

-/* Velocity timer reload register */

-

-#define QEI_LOAD_

-

-/* Velocity timer register */

-

-#define QEI_TIME_

-

-/* Velocity counter register */

-

-#define QEI_VEL_

-

-/* Velocity capture register */

-

-#define QEI_CAP_

-

-/* Velocity compare register */

-

-#define QEI_VELCOMP_

-

-/* Digital filter register */

-

-#define QEI_FILTER_

+#define QEI_CONF_DIRINV          (1 << 0)  /* Bit 0:  Direction invert */

+#define QEI_CONF_SIGMODE         (1 << 1)  /* Bit 1:  Signal Mode */

+#define QEI_CONF_CAPMODE         (1 << 2)  /* Bit 2:  Capture Mode */

+#define QEI_CONF_INVINX          (1 << 3)  /* Bit 3:  Invert Index */

+                                           /* Bits 4-31: reserved */

+/* Position, index, and timer registers (all 32-bit integer values with not bit fields */

 

 /* Interrupt registers */

-/* Interrupt enable clear register */

-

-#define QEI_IEC_

-

-/* Interrupt enable set register */

-

-#define QEI_IES_

-

-/* Interrupt status register */

-

-#define QEI_INTSTAT_

-

-/* Interrupt enable register */

-

-#define QEI_IE_

-

-/* Interrupt status clear register */

-

-#define QEI_CLR_

-

-/* Interrupt status set register */

-

-#define QEI_SET_

+/* Interrupt enable clear register (IEC), Interrupt enable set register (IES),

+ * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt

+ * status clear register (CLR), and Interrupt status set register (SET) common

+ * bit definitions.

+ */

+

+#define QEI_INT_INX              (1 << 0)  /* Bit 0:  Index pulse detected */

+#define QEI_INT_TIM              (1 << 1)  /* Bit 1:  Velocity timer overflow occurred */

+#define QEI_INT_VELC             (1 << 2)  /* Bit 2:  Captured velocity less than compare velocity */

+#define QEI_INT_DIR              (1 << 3)  /* Bit 3:  Change of direction detected */

+#define QEI_INT_ERR              (1 << 4)  /* Bit 4:  Encoder phase error detected */

+#define QEI_INT_ENCLK            (1 << 5)  /* Bit 5:  Eencoder clock pulse detected */

+#define QEI_INT_POS0             (1 << 6)  /* Bit 6:  Position 0 compare equal to current position */

+#define QEI_INT_POS1             (1 << 7)  /* Bit 7:  Position 1 compare equal to current position */

+#define QEI_INT_POS2             (1 << 8)  /* Bit 8:  Position 2 compare equal to current position */

+#define QEI_INT_REV              (1 << 9)  /* Bit 9:  Index compare value equal to current index count */

+#define QEI_INT_POS0REV          (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */

+#define QEI_INT_POS1REV          (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */

+#define QEI_INT_POS2REV          (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */

+                                           /* Bits 13-31: reserved */

 

 /************************************************************************************

  * Public Types

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h
index f99fd6580..70e56de87 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h
@@ -144,134 +144,116 @@
 #define LPC17_RTC_ALYEAR        (LPC17_RTC_BASE+LPC17_RTC_ALYEAR_OFFSET)

 

 /* Register bit definitions *********************************************************/

+/* The following registers hold 32-bit values and have no bit fields to be defined:

+ *

+ *   General Purpose Register 0

+ *   General Purpose Register 1

+ *   General Purpose Register 2

+ *   General Purpose Register 3

+ *   General Purpose Register 4

+ */

+

 /* Miscellaneous registers */

 /* Interrupt Location Register */

 

-#define RTC_ILR_

-

+#define RTC_ILR_RTCCIF          (1 << 0)  /* Bit 0:  Counter Increment Interrupt */

+#define RTC_ILR_RTCALF          (1 << 1)  /* Bit 1:  Alarm interrupt */

+                                          /* Bits 2-31: Reserved */

 /* Clock Control Register */

 

-#define RTC_CCR_

-

+#define RTC_CCR_CLKEN           (1 << 0)  /* Bit 0:  Clock Enable */

+#define RTC_CCR_CTCRST          (1 << 1)  /* Bit 1:  CTC Reset */

+                                          /* Bits 2-3: Internal test mode controls */

+#define RTC_CCR_CCALEN          (1 << 4)  /* Bit 4:  Calibration counter enable */

+                                          /* Bits 5-31: Reserved */

 /* Counter Increment Interrupt Register */

 

-#define RTC_CIIR_

-

+#define RTC_CIIR_IMSEC          (1 << 0)  /* Bit 0:  Second interrupt */

+#define RTC_CIIR_IMMIN          (1 << 1)  /* Bit 1:  Minute interrupt */

+#define RTC_CIIR_IMHOUR         (1 << 2)  /* Bit 2:  Hour interrupt */

+#define RTC_CIIR_IMDOM          (1 << 3)  /* Bit 3:  Day of Month value interrupt */

+#define RTC_CIIR_IMDOW          (1 << 4)  /* Bit 4:  Day of Week value interrupt */

+#define RTC_CIIR_IMDOY          (1 << 5)  /* Bit 5:  Day of Year interrupt */

+#define RTC_CIIR_IMMON          (1 << 6)  /* Bit 6:  Month interrupt */

+#define RTC_CIIR_IMYEAR         (1 << 7)  /* Bit 7:  Yearinterrupt */

+                                          /* Bits 8-31: Reserved */

 /* Alarm Mask Register */

 

-#define RTC_AMR_

-

+#define RTC_AMR_SEC             (1 << 0)  /* Bit 0:  Second not compared for alarm */

+#define RTC_AMR_MIN             (1 << 1)  /* Bit 1:  Minutes not compared for alarm */

+#define RTC_AMR_HOUR            (1 << 2)  /* Bit 2:  Hour not compared for alarm */

+#define RTC_AMR_DOM             (1 << 3)  /* Bit 3:  Day of Monthnot compared for alarm */

+#define RTC_AMR_DOW             (1 << 4)  /* Bit 4:  Day of Week not compared for alarm */

+#define RTC_AMR_DOY             (1 << 5)  /* Bit 5:  Day of Year not compared for alarm */

+#define RTC_AMR_MON             (1 << 6)  /* Bit 6:  Month not compared for alarm */

+#define RTC_AMR_YEAR            (1 << 7)  /* Bit 7:  Year not compared for alarm */

+                                          /* Bits 8-31: Reserved */

 /* RTC Auxiliary Enable register */

-

-#define RTC_AUXEN_

-

+                                          /* Bits 0-3: Reserved */

+#define RTC_AUXEN_RTCOSCF       (1 << 4)  /* Bit 4:  RTC Oscillator Fail detect flag */

+                                          /* Bits 5-31: Reserved */

 /* RTC Auxiliary control register */

-

-#define RTC_AUX_

-

+                                          /* Bits 0-3: Reserved */

+#define RTC_AUX_OSCFEN          (1 << 4)  /* Bit 4:  Oscillator Fail Detect interrupt enable */

+                                          /* Bits 5-31: Reserved */

 /* Consolidated time registers */

 /* Consolidated Time Register 0 */

 

-#define RTC_CTIME0_

-

+#define RTC_CTIME0_SEC_SHIFT    (0)       /* Bits 0-5: Seconds */

+#define RTC_CTIME0_SEC_MASK     (63 << RTC_CTIME0_SEC_SHIFT)

+                                          /* Bits 6-7: Reserved */

+#define RTC_CTIME0_MIN_SHIFT    (8)       /* Bits 8-13: Minutes */

+#define RTC_CTIME0_MIN_MASK     (63 << RTC_CTIME0_MIN_SHIFT)

+                                          /* Bits 14-15: Reserved */

+#define RTC_CTIME0_HOURS_SHIFT  (16)      /* Bits 16-20: Hours */

+#define RTC_CTIME0_HOURS_MASK   (31 << RTC_CTIME0_HOURS_SHIFT)

+                                          /* Bits 21-23: Reserved */

+#define RTC_CTIME0_DOW_SHIFT    (24)      /* Bits 24-26: Day of Week */

+#define RTC_CTIME0_DOW_MASK     (7 << RTC_CTIME0_DOW_SHIFT)

+                                          /* Bits 27-31: Reserved */

 /* Consolidated Time Register 1 */

 

-#define RTC_CTIME1_

-

-/* Consolidated Time Register 2 */

-

-#define RTC_CTIME2_

-

+#define RTC_CTIME1_DOM_SHIFT    (0)       /* Bits 0-4: Day of Month */

+#define RTC_CTIME1_DOM_MASK     (31 << RTC_CTIME1_DOM_SHIFT)

+                                          /* Bits 5-7: Reserved */

+#define RTC_CTIME1_MON_SHIFT    (8)       /* Bits 8-11: Month */

+#define RTC_CTIME1_MON_MASK     (15 << RTC_CTIME1_MON_SHIFT)

+                                          /* Bits 12-15: Reserved */

+#define RTC_CTIME1_YEAR_SHIFT   (16)      /* Bits 16-27: Year */

+#define RTC_CTIME1_YEAR_MASK    (0x0fff << RTC_CTIME1_YEAR_SHIFT)

+                                          /* Bits 28-31: Reserved */

+/* Consolidated Time Register 2 (Shouldn't DOY width be 9 bits?) */

+

+#define RTC_CTIME2_DOY_SHIFT    (0)       /* Bits 0-11: Day of Year */

+#define RTC_CTIME2_DOY_MASK     (0x0fff << RTC_CTIME2_DOY_SHIFT)

+                                          /* Bits 12-31: Reserved */

 /* Time counter registers */

-/* Seconds Counter */

-

-#define RTC_SEC_

-

-/* Minutes Register */

-

-#define RTC_MIN_

-

-/* Hours Register */

-

-#define RTC_HOUR_

-

-/* Day of Month Register */

-

-#define RTC_DOM_

-

-/* Day of Week Register */

-

-#define RTC_DOW_

-

-/* Day of Year Register */

-

-#define RTC_DOY_

-

-/* Months Register */

-

-#define RTC_MONTH_

 

-/* Years Register */

-

-#define RTC_YEAR_

+#define RTC_SEC_MASK            (0x003f)

+#define RTC_MIN_MASK            (0x003f)

+#define RTC_HOUR_MASK           (0x001f)

+#define RTC_DOM_MASK            (0x001f)

+#define RTC_DOW_MASK            (0x0007)

+#define RTC_DOY_MASK            (0x01ff)

+#define RTC_MONTH_MASK          (0x000f)

+#define RTC_YEAR_MASK           (0x0fff)

 

 /* Calibration Value Register */

 

-#define RTC_CALIB_

-

-/* General purpose registers */

-/* General Purpose Register 0 */

-

-#define RTC_GPREG0_

-

-/* General Purpose Register 1 */

-

-#define RTC_GPREG1_

-

-/* General Purpose Register 2 */

-

-#define RTC_GPREG2_

-

-/* General Purpose Register 3 */

-

-#define RTC_GPREG3_

-

-/* General Purpose Register 4 */

-

-#define RTC_GPREG4_

-

+#define RTC_CALIB_CALVAL_SHIFT  (0)       /* Bits 0-16: calibration counter counts to this value */

+#define RTC_CALIB_CALVAL_MASK   (0xffff << RTC_CALIB_CALVAL_SHIFT)

+#define RTC_CALIB_CALDIR        (1 << 17) /* Bit 17: Calibration direction */

+                                          /* Bits 12-31: Reserved */

 /* Alarm register group */

-/* Alarm value for Seconds */

-

-#define RTC_ALSEC_

-

-/* Alarm value for Minutes */

-

-#define RTC_ALMIN_

-

-/* Alarm value for Hours */

-

-#define RTC_ALHOUR_

-

-/* Alarm value for Day of Month */

-

-#define RTC_ALDOM_

-

-/* Alarm value for Day of Week */

-

-#define RTC_ALDOW_

-

-/* Alarm value for Day of Year */

-

-#define RTC_ALDOY_

-

-/* Alarm value for Months  */

-

-#define RTC_ALMON_

-

-/* Alarm value for Year */

 

-#define RTC_ALYEAR_

+#define RTC_ALSEC_MASK          (0x003f)

+#define RTC_ALMIN_MASK          (0x003f)

+#define RTC_ALHOUR_MASK         (0x001f)

+#define RTC_ALDOM_MASK          (0x001f)

+#define RTC_ALDOW_MASK          (0x0007)

+#define RTC_ALDOY_MASK          (0x01ff)

+#define RTC_ALMON_MASK          (0x000f)

+#define RTC_ALYEAR_MASK         (0x0fff)

 

 /************************************************************************************

  * Public Types