Add USBDEV power/pin configuration

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2745 42af7a65-404d-4744-a932-0658087f49c3

3 files changed, 29 insertions, 9 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h
index e5321acef..db1cf699c 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h
@@ -296,7 +296,7 @@
 #define GPIO_MCPWM_MCOB2   (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29)
 #define GPIO_PCAP1p1       (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29)
 #define GPIO_MAT0p1_1      (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29)
-#define GPIO_VBUS          (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30)
+#define GPIO_USB_VBUS      (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30)
 #define GPIO_AD0p4         (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30)
 #define GPIO_SSP1_SCK_2    (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31)
 #define GPIO_AD0p5         (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31)
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c
index 3ef2cbf6a..34e09edd0 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c
@@ -621,7 +621,7 @@ static inline void lpc17_uart0config(uint8_t clkdiv)
 
   flags   = irqsave();
   regval  = getreg32(LPC17_SYSCON_PCONP);
-  regval |= ~SYSCON_PCONP_PCUART0;
+  regval |= SYSCON_PCONP_PCUART0;
   putreg32(regval, LPC17_SYSCON_PCONP);
 
   /* Step 2: Enable clocking on UART */
@@ -649,7 +649,7 @@ static inline void lpc17_uart1config(uint8_t clkdiv)
 
   flags   = irqsave();
   regval  = getreg32(LPC17_SYSCON_PCONP);
-  regval |= ~SYSCON_PCONP_PCUART1;
+  regval |= SYSCON_PCONP_PCUART1;
   putreg32(regval, LPC17_SYSCON_PCONP);
 
   /* Step 2: Enable clocking on UART */
@@ -713,7 +713,7 @@ static inline void lpc17_uart3config(uint8_t clkdiv)
 
   flags   = irqsave();
   regval  = getreg32(LPC17_SYSCON_PCONP);
-  regval |= ~SYSCON_PCONP_PCUART3;
+  regval |= SYSCON_PCONP_PCUART3;
   putreg32(regval, LPC17_SYSCON_PCONP);
 
   /* Step 2: Enable clocking on UART */
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c b/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c
index f1bd5e23f..29a5490e6 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c
@@ -3069,11 +3069,8 @@ static int lpc17_pullup(struct usbdev_s *dev, bool enable)
  *   Initialize USB hardware.
  *
  * Assumptions:
- * - This function is called very early in the initialization sequence
- * - PLL and GIO pin initialization is not performed here but should been in
- *   the low-level  boot logic:  PLL1 must be configured for operation at 48MHz
- *   and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB connect
- *   LED.
+ *   This function is called very early in the initialization sequence in order
+ *   to initialize the USB device functionality.
  *
  *******************************************************************************/
 
@@ -3085,9 +3082,32 @@ void up_usbinitialize(void)
 
   usbtrace(TRACE_DEVINIT, 0);
 
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power by setting PCUSB in the PCONP register */
+
+  flags   = irqsave();
+  regval  = getreg32(LPC17_SYSCON_PCONP);
+  regval |= SYSCON_PCONP_PCUSB;
+  putreg32(regval, LPC17_SYSCON_PCONP);
+
+  /* Step 2: Enable clocking on UART (USB clocking was initialized in very
+   * low-level clock setup logic (see lpc17_clockconfig.c)
+   */
+
+  /* Step 3: Configure I/O pins */
+
+  lpc17_configgpio(GPIO_USB_VBUS);    /* VBUS status input */
+  lpc17_configgpio(GPIO_USB_CONNECT); /* SoftConnect control signal */
+  lpc17_configgpio(GPIO_USB_UPLED);   /* GoodLink LED control signal */
+  lpc17_configgpio(GPIO_USB_DP);      /* Positive differential data */
+  lpc17_configgpio(GPIO_USB_DM);      /* Negative differential data */
+
   /* Disable USB interrupts */
 
   lpc17_putreg(0, LPC17_USBDEV_INTST);
+  irqrestore(flags);
 
   /* Initialize the device state structure */