SAMA5 OHCI+EHCI mostly cosmetic changes

3 files changed, 46 insertions, 11 deletions

diff --git a/nuttx/arch/arm/src/sama5/sam_clockconfig.c b/nuttx/arch/arm/src/sama5/sam_clockconfig.c
index f8ecdbd10..0dc6884cd 100644
--- a/nuttx/arch/arm/src/sama5/sam_clockconfig.c
+++ b/nuttx/arch/arm/src/sama5/sam_clockconfig.c
@@ -343,14 +343,37 @@ static inline void sam_usbclockconfig(void)
    *      value and USB Full-speed accuracy.
    *   4) Enable the OHCI clocks, UHP bit in PMC_SCER register.
    *
-   * Steps 2 and 3 are done here.  1 and 2 are performed with the USB device
-   * driver is opened.
+   * Steps 2 and 3 are done here.  1 and 2 are performed with the OHCI
+   * driver is initialized.
    */
 
   putreg32(BOARD_OHCI_INPUT | BOARD_OHCI_DIVIDER << PMC_USB_USBDIV_SHIFT,
           SAM_PMC_USB);
 #endif
 
+#ifdef CONFIG_SAMA5_EHCI
+  /* For High-speed operations, the user has to perform the following:
+   *
+   *   1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
+   *      PMC_PCER register.
+   *   2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
+   *   3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
+   *   4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
+   *   5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
+   *   6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
+   *      register.
+   *   7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
+   *      PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
+   *      selected.
+   *   8) Enable OHCI clocks, UHP bit in PMC_SCER register.
+   *
+   * Steps 2 through 7 performed here.  1 and 8 are performed in the EHCI
+   * driver is initialized.
+   */
+
+#  warning Missing logic
+#endif
+
 #if 0 // #ifdef CONFIG_USBDEV
   uint32_t regval;
 
diff --git a/nuttx/arch/arm/src/sama5/sam_ohci.c b/nuttx/arch/arm/src/sama5/sam_ohci.c
index 43e28029c..2c2fe6582 100644
--- a/nuttx/arch/arm/src/sama5/sam_ohci.c
+++ b/nuttx/arch/arm/src/sama5/sam_ohci.c
@@ -186,7 +186,7 @@ struct sam_eplist_s
   struct sam_gtd_s *tail;      /* Tail transfer descriptor (TD) */
 };
 
-/* This structure retins the state of one root hub port */
+/* This structure retains the state of one root hub port */
 
 struct sam_rhport_s
 {
@@ -2792,9 +2792,6 @@ static int sam_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
   struct sam_ed_s *ed;
   uint32_t dirpid;
   uint32_t regval;
-#if SAM_IOBUFFERS > 0
-  uint8_t *origbuf = NULL;
-#endif
   bool in;
   int ret;
 
@@ -3015,7 +3012,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
 
   /* Enable OHCI clocks */
 
-  regval = getreg32(SAM_PMC_SCER);
+  regval  = getreg32(SAM_PMC_SCER);
   regval |= PMC_UHP;
   putreg32(regval, SAM_PMC_SCER);
   irqrestore(flags);
@@ -3035,7 +3032,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
    * dedicated function
    */
 
-  udbg("Initializing Host Stack\n");
+  udbg("Initializing OHCI Stack\n");
 
   /* Initialize all the HCCA to 0 */
 
diff --git a/nuttx/include/nuttx/usb/ehci.h b/nuttx/include/nuttx/usb/ehci.h
index 0d9ae59c4..01dd69751 100755
--- a/nuttx/include/nuttx/usb/ehci.h
+++ b/nuttx/include/nuttx/usb/ehci.h
@@ -49,6 +49,16 @@
 /********************************************************************************************
  * Pre-processor Definitions
  ********************************************************************************************/
+/* General definitions **********************************************************************/
+/* Endpoint speed values as used in endpoint characteristics field */
+
+#define EHCI_FULL_SPEED               (0) /* Full-Speed (12Mbs) */
+#define EHCI_LOW_SPEED                (1) /* Low-Speed (1.5Mbs) */
+#define EHCI_HIGH_SPEED               (2) /* High-Speed (480 Mb/s) */
+
+#define EHCI_DIR_IN                   (1) /* Direction IN: Peripheral to host */
+#define EHCI_DIR_OUT                  (0) /* Direction OUT: Host to peripheral */
+
 /* PCI Configuration Space Register Offsets *************************************************/
 /* Paragraph 2.1 */
 
@@ -456,8 +466,11 @@
 /* siTD Transfer State. Paragraph 3.4.3 */
 
 #define SITD_XFRSTATE_STATUS_SHIFT     (0)        /* Bits 0-7: Status */
+#define SITD_XFRSTATE_STATUS_MASK      (0xff << SITD_XFRSTATE_STATUS_SHIFT)
 #define SITD_XFRSTATE_CPROGMASK_SHIFT  (8)        /* Bits 8-15: µFrame Complete-split Progress Mask  */
+#define SITD_XFRSTATE_CPROGMASK_MASK   (0xff << SITD_XFRSTATE_CPROGMASK_SHIFT)
 #define SITD_XFRSTATE_NBYTES_SHIFT     (16)       /* Bits 16-25: Total Bytes To Transfer */
+#define SITD_XFRSTATE_NBYTES_MASK      (0x3ff << SITD_XFRSTATE_NBYTES_SHIFT)
                                                   /* Bits 26-29: Reserved */
 #define SITD_XFRSTATE_P                (1 << 30)  /* Bit 30: Page Select */
 #define SITD_XFRSTATE_IOC              (1 << 31)  /* Bit 31: Interrupt On Complete */
@@ -521,7 +534,8 @@
 #define QTD_TOKEN_CPAGE_SHIFT          (12)       /* Bits 12-14: Current Page */
 #define QTD_TOKEN_CPAGE_MASK           (7 << QTD_TOKEN_CPAGE_SHIFT)
 #define QTD_TOKEN_IOC                  (1 << 15)  /* Bit 15: Interrupt On Complete */
-#define QTD_TOKEN_NBYTES               (16)       /* Bits 16-30: Total Bytes to Transfer */
+#define QTD_TOKEN_NBYTES_SHIFT         (16)       /* Bits 16-30: Total Bytes to Transfer */
+#define QTD_TOKEN_NBYTES_MASK          (0x7fff << QTD_TOKEN_NBYTES_SHIFT)
 #define QTD_TOKEN_TOGGLE               (1 << 13)  /* Bit 31: Data Toggle
 
 /* qTD Buffer Page Pointer List. Paragraph 3.5.4 */
@@ -555,7 +569,7 @@
 
 #define QH_EPCHAR_DEVADDR_SHIFT        (0)        /* Bitx 0-6: Device Address */
 #define QH_EPCHAR_DEVADDR_MASK         (0x7f << QH_EPCHAR_DEVADDR_SHIFT)
-#define QH_EPCHAR_I                    (1 << 7)   /* Bit 7: Inactivate on Next Transactionl */
+#define QH_EPCHAR_I                    (1 << 7)   /* Bit 7: Inactivate on Next Transaction */
 #define QH_EPCHAR_ENDPT_SHIFT          (8)        /* Bitx 8-11: Endpoint Number */
 #define QH_EPCHAR_ENDPT_MASK           (15 << QH_EPCHAR_ENDPT_SHIFT)
 #define QH_EPCHAR_EPS_SHIFT            (12)       /* Bitx 12-13: Endpoint Speed */
@@ -634,7 +648,8 @@
 #define QH_TOKEN_CPAGE_SHIFT           (12)       /* Bits 12-14: Current Page */
 #define QH_TOKEN_CPAGE_MASK            (7 << QH_TOKEN_CPAGE_SHIFT)
 #define QH_TOKEN_IOC                   (1 << 15)  /* Bit 15: Interrupt On Complete */
-#define QH_TOKEN_NBYTES                (16)       /* Bits 16-30: Total Bytes to Transfer */
+#define QH_TOKEN_NBYTES_SHIFT          (16)       /* Bits 16-30: Total Bytes to Transfer */
+#define QH_TOKEN_NBYTES_MASK           (0x7fff << QH_TOKEN_NBYTES_SHIFT)
 #define QH_TOKEN_TOGGLE                (1 << 13)  /* Bit 31: Data Toggle
 
 /* Buffer Page Pointer List (NOTE 2)