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author | Gregory Nutt <gnutt@nuttx.org> | 2014-06-19 15:52:42 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2014-06-19 15:52:42 -0600 |
commit | 8159b97c7f3d8ddf8662d71026858131ca85a228 (patch) | |
tree | 468085c603b004bd4cae2f64d0fcfe35afdf742d | |
parent | 18fcff8a4ae716169aa2b9fb6ce959ad2a668455 (diff) | |
download | nuttx-8159b97c7f3d8ddf8662d71026858131ca85a228.tar.gz nuttx-8159b97c7f3d8ddf8662d71026858131ca85a228.tar.bz2 nuttx-8159b97c7f3d8ddf8662d71026858131ca85a228.zip |
SAMA5D4: Fix peripheral clocking macros: AIC and L2CC are continuously clocked
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_irq.c | 16 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_pio.h | 16 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sama5d4x_periphclks.h | 51 |
3 files changed, 57 insertions, 26 deletions
diff --git a/nuttx/arch/arm/src/sama5/sam_irq.c b/nuttx/arch/arm/src/sama5/sam_irq.c index d75838ef8..ad4e1e5c9 100644 --- a/nuttx/arch/arm/src/sama5/sam_irq.c +++ b/nuttx/arch/arm/src/sama5/sam_irq.c @@ -128,9 +128,19 @@ static void sam_dumpaic(const char *msg, int irq) lldbg(" IPR: %08x %08x %08x %08x\n", getreg32(SAM_AIC_IPR0), getreg32(SAM_AIC_IPR1), getreg32(SAM_AIC_IPR2), getreg32(SAM_AIC_IPR3)); + + /* SAMA5D4 does not have the FFSR register */ + +#ifdef SAM_AIC_FFSR lldbg(" IMR: %08x CISR: %08x SPU: %08x FFSR: %08x\n", getreg32(SAM_AIC_IMR), getreg32(SAM_AIC_CISR), getreg32(SAM_AIC_SPU), getreg32(SAM_AIC_FFSR)); +#else + lldbg(" IMR: %08x CISR: %08x SPU: %08x\n", + getreg32(SAM_AIC_IMR), getreg32(SAM_AIC_CISR), + getreg32(SAM_AIC_SPU)); +#endif + lldbg(" DCR: %08x WPMR: %08x WPSR: %08x\n", getreg32(SAM_AIC_DCR), getreg32(SAM_AIC_WPMR), getreg32(SAM_AIC_WPSR)); @@ -191,7 +201,7 @@ static inline size_t sam_vectorsize(void) static uint32_t *sam_spurious(int irq, uint32_t *regs) { - /* This is probably irrevelant since true vectored interrupts are not used + /* This is probably irrelevant since true vectored interrupts are not used * in this implementation. The value of AIC_IVR is ignored. */ @@ -211,7 +221,7 @@ static uint32_t *sam_spurious(int irq, uint32_t *regs) static uint32_t *sam_fiqhandler(int irq, uint32_t *regs) { - /* This is probably irrevelant since FIQs are not used in this + /* This is probably irrelevant since FIQs are not used in this * implementation. */ @@ -439,7 +449,7 @@ void up_irqinitialize(void) * the irq number of the interrupt and then to call arm_doirq to dispatch * the interrupt. * - * Input paramters: + * Input parameters: * regs - A pointer to the register save area on the stack. * ****************************************************************************/ diff --git a/nuttx/arch/arm/src/sama5/sam_pio.h b/nuttx/arch/arm/src/sama5/sam_pio.h index 5ddeb5a06..d70a1bd46 100644 --- a/nuttx/arch/arm/src/sama5/sam_pio.h +++ b/nuttx/arch/arm/src/sama5/sam_pio.h @@ -73,12 +73,12 @@ /* 32-bit Encoding: * - * ..MM MCCC CCDD IIIV PPPB BBBB + * .... .... ..MM MCCC CCDD IIIV PPPB BBBB */ /* Input/Output mode: * - * ..MM M... .... .... .... .... + * .... .... ..MM M... .... .... .... .... */ #define PIO_MODE_SHIFT (19) /* Bits 19-21: PIO mode */ @@ -93,7 +93,7 @@ /* These bits set the configuration of the pin: * NOTE: No definitions for parallel capture mode * - * .... .CCC CC.. .... .... .... + * .... .... .... .CCC CC.. .... .... .... */ #define PIO_CFG_SHIFT (14) /* Bits 14-18: PIO configuration bits */ @@ -107,7 +107,7 @@ /* Drive Strength: * - * .... .... ..DD .... .... .... + * .... .... .... .... ..DD .... .... .... */ #define PIO_DRIVE_SHIFT (12) /* Bits 12-13: Drive strength */ @@ -118,7 +118,7 @@ /* Additional interrupt modes: * - * .... .... .... III. .... .... + * .... .... .... .... .... III. .... .... */ #define PIO_INT_SHIFT (9) /* Bits 9-11: PIO interrupt bits */ @@ -137,7 +137,7 @@ /* If the pin is an PIO output, then this identifies the initial output value: * - * .... .... .... ...V .... .... + * .... .... .... .... .... ...V .... .... */ #define PIO_OUTPUT_SET (1 << 8) /* Bit 8: Inital value of output */ @@ -145,7 +145,7 @@ /* This identifies the PIO port: * - * .... .... .... .... PPP. .... + * .... .... .... .... .... .... PPP. .... */ #define PIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ @@ -158,7 +158,7 @@ /* This identifies the bit in the port: * - * .... .... .... .... ...B BBBB + * .... .... .... .... .... .... ...B BBBB */ #define PIO_PIN_SHIFT (0) /* Bits 0-4: PIO number: 0-31 */ diff --git a/nuttx/arch/arm/src/sama5/sama5d4x_periphclks.h b/nuttx/arch/arm/src/sama5/sama5d4x_periphclks.h index b97a8ec51..c4e14eda6 100644 --- a/nuttx/arch/arm/src/sama5/sama5d4x_periphclks.h +++ b/nuttx/arch/arm/src/sama5/sama5d4x_periphclks.h @@ -52,13 +52,10 @@ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) #define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1) -#define sam_enableperiph2(s) putreg32((1 << ((s) - 64)), SAM_PMC_PCER2) #define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0) #define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1) -#define sam_disableperiph2(s) putreg32((1 << ((s) - 63)), SAM_PMC_PCDR2) #define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0) #define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0) -#define sam_isenabled2(s) (getreg32(SAM_PMC_PCER2) & (1 << ((s) - 64)) != 0) /* Enable peripheral clocking */ @@ -122,10 +119,18 @@ #define sam_twi3_enableclk() sam_enableperiph1(SAM_PID_TWI3) #define sam_catb_enableclk() sam_enableperiph1(SAM_PID_CATB) -#define sam_sfr_enableclk() sam_enableperiph2(SAM_PID_CATB) -#define sam_aic_enableclk() sam_enableperiph2(SAM_PID_CATB) -#define sam_saic_enableclk() sam_enableperiph2(SAM_PID_CATB) -#define sam_l2cc_enableclk() sam_enableperiph2(SAM_PID_CATB) +/* The Advanced Interrupt Controller and L2CC cache controllers are + * continuously clocked. The Power Management Controller has no effect on + * their behavior. + * + * (I presume that this is true of the SFR as well since it has no PMC + * bits to control its clocking). + */ + +#define sam_sfr_enableclk() +#define sam_aic_enableclk() +#define sam_saic_enableclk() +#define sam_l2cc_enableclk() /* Disable peripheral clocking */ @@ -189,10 +194,18 @@ #define sam_twi3_disableclk() sam_disableperiph1(SAM_PID_TWI3) #define sam_catb_disableclk() sam_disableperiph1(SAM_PID_CATB) -#define sam_sfr_disableclk() sam_disableperiph2(SAM_PID_CATB) -#define sam_aic_disableclk() sam_disableperiph2(SAM_PID_CATB) -#define sam_saic_disableclk() sam_disableperiph2(SAM_PID_CATB) -#define sam_l2cc_disableclk() sam_disableperiph2(SAM_PID_CATB) +/* The Advanced Interrupt Controller and L2CC cache controllers are + * continuously clocked. The Power Management Controller has no effect on + * their behavior. + * + * (I presume that this is true of the SFR as well since it has no PMC + * bits to control its clocking). + */ + +#define sam_sfr_disableclk() +#define sam_aic_disableclk() +#define sam_saic_disableclk() +#define sam_l2cc_disableclk() /* Test if peripheral clocking is enabled */ @@ -256,10 +269,18 @@ #define sam_twi3_isenabled() sam_isenabled1(SAM_PID_TWI3) #define sam_catb_isenabled() sam_isenabled1(SAM_PID_CATB) -#define sam_sfr_isenabled() sam_isenabled2(SAM_PID_CATB) -#define sam_aic_isenabled() sam_isenabled2(SAM_PID_CATB) -#define sam_saic_isenabled() sam_isenabled2(SAM_PID_CATB) -#define sam_l2cc_isenabled() sam_isenabled2(SAM_PID_CATB) +/* The Advanced Interrupt Controller and L2CC cache controllers are + * continuously clocked. The Power Management Controller has no effect on + * their behavior. + * + * (I presume that this is true of the SFR as well since it has no PMC + * bits to control its clocking). + */ + +#define sam_sfr_isenabled() (true) +#define sam_aic_isenabled() (true) +#define sam_saic_isenabled() (true) +#define sam_l2cc_isenabled() (true) /************************************************************************************ * Public Types |