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author | Gregory Nutt <gnutt@nuttx.org> | 2014-04-02 16:27:00 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2014-04-02 16:27:00 -0600 |
commit | febd235e77df36985b82064d31911fc29e0265ad (patch) | |
tree | 3c4c905489f39dae9af8a4560394369460c81572 | |
parent | 4da3d71a5b619a314689f8978763b83e20e32300 (diff) | |
download | nuttx-febd235e77df36985b82064d31911fc29e0265ad.tar.gz nuttx-febd235e77df36985b82064d31911fc29e0265ad.tar.bz2 nuttx-febd235e77df36985b82064d31911fc29e0265ad.zip |
SAMA5: Make sure the MMU and caches are disabled on power up; flush the vector region D-Cache after copying interrupt vectors; make sure that D-Cache, I-Cache, and TLBs are invalidated after modifying the AXI MATRIX remapping
-rw-r--r-- | nuttx/ChangeLog | 9 | ||||
-rw-r--r-- | nuttx/arch/arm/src/armv7-a/arm_head.S | 8 | ||||
-rw-r--r-- | nuttx/arch/arm/src/armv7-a/cache.h | 8 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_boot.c | 32 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_irq.c | 34 |
5 files changed, 85 insertions, 6 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 139e4f604..6683cad09 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -7113,3 +7113,12 @@ from kfrolov (2014-4-2). * arch/arm/src/sama5/sam_boot.c, sam_irq.c, chip/sama5d3x_memorymap.h: When running from SDRAM, vectors must lie in SRAM (2014-4-2). + * arch/arm/src/armv7-a/arm_head.S and cache.h: On start-up, make + certain the the MMU and caches are disabled (probably un-necessary) + (2014-4-2). + * arch/arm/src/sama5/sam_boot.c: If we have to copy vectors, then + make sure to clean the DCache to be sure that the copied vectors are + in the physical RAM (2014-4-2). + * arch/arm/src/sama5/sam_irq.c: After we modify the AXI MATRIX, make + sure to invalidate all caches and TLBs (probably un-necessary) + (2014-4-2). diff --git a/nuttx/arch/arm/src/armv7-a/arm_head.S b/nuttx/arch/arm/src/armv7-a/arm_head.S index a2a590658..c8d5466cc 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_head.S +++ b/nuttx/arch/arm/src/armv7-a/arm_head.S @@ -190,6 +190,13 @@ __start: mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT) msr cpsr_c, r0 + /* The MMU and caches should be disabled */ + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(SCTLR_M | SCTLR_C) + bic r0, r0, #(SCTLR_I) + mcr p15, 0, r0, c1, c0, 0 + /* Clear the 16K level 1 page table */ ldr r5, .LCppgtable /* r5=phys. page table */ @@ -389,6 +396,7 @@ __start: * example, we get here via a bootloader and the control register is in some * unknown state. * + * SCTLR_M Bit 0: Enable the MMU * SCTLR_A Bit 1: Strict alignment disabled (reset value) * SCTLR_C Bit 2: DCache disabled (reset value) * diff --git a/nuttx/arch/arm/src/armv7-a/cache.h b/nuttx/arch/arm/src/armv7-a/cache.h index ec27b0f8f..6d121bd45 100644 --- a/nuttx/arch/arm/src/armv7-a/cache.h +++ b/nuttx/arch/arm/src/armv7-a/cache.h @@ -210,7 +210,7 @@ .macro cp15_disable_dcache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Updagte the SCTLR */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm /************************************************************************************ @@ -231,7 +231,7 @@ mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Updagte the SCTLR */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm /************************************************************************************ @@ -501,7 +501,7 @@ static inline void cp15_disable_dcache(void) ( "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Updagte the SCTLR */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ : : : "r0", "memory" @@ -529,7 +529,7 @@ static inline void cp15_disable_caches(void) "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Updagte the SCTLR */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ : : : "r0", "memory" diff --git a/nuttx/arch/arm/src/sama5/sam_boot.c b/nuttx/arch/arm/src/sama5/sam_boot.c index 239f52725..8493c3bf1 100644 --- a/nuttx/arch/arm/src/sama5/sam_boot.c +++ b/nuttx/arch/arm/src/sama5/sam_boot.c @@ -51,6 +51,7 @@ #include "chip.h" #include "arm.h" #include "mmu.h" +#include "cache.h" #include "fpu.h" #include "up_internal.h" #include "up_arch.h" @@ -126,6 +127,8 @@ * Public Variables ****************************************************************************/ +/* Symbols defined via the linker script */ + extern uint32_t _vector_start; /* Beginning of vector block */ extern uint32_t _vector_end; /* End+1 of vector block */ @@ -429,6 +432,25 @@ static void sam_vectorpermissions(uint32_t mmuflags) #endif /**************************************************************************** + * Name: sam_vectorsize + * + * Description: + * Return the size of the vector data + * + ****************************************************************************/ + +static inline size_t sam_vectorsize(void) +{ + uintptr_t src; + uintptr_t end; + + src = (uintptr_t)&_vector_start; + end = (uintptr_t)&_vector_end; + + return (size_t)(end - src); +} + +/**************************************************************************** * Name: sam_vectormapping * * Description: @@ -497,11 +519,11 @@ static void sam_copyvectorblock(void) uint32_t *end; uint32_t *dest; +#ifdef CONFIG_PAGING /* If we are using re-mapped vectors in an area that has been marked * read only, then temporarily mark the mapping write-able (non-buffered). */ -#ifdef CONFIG_PAGING sam_vectorpermissions(MMU_L2_VECTRWFLAGS); #endif @@ -523,10 +545,16 @@ static void sam_copyvectorblock(void) *dest++ = *src++; } +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) /* Make the vectors read-only, cacheable again */ -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) sam_vectorpermissions(MMU_L2_VECTORFLAGS); + +#else + /* Flush the DCache to assure that the vector data is in physical in ISRAM */ + + cp15_clean_dcache((uintptr_t)SAM_VECTOR_VSRAM, + (uintptr_t)SAM_VECTOR_VSRAM + sam_vectorsize()); #endif } diff --git a/nuttx/arch/arm/src/sama5/sam_irq.c b/nuttx/arch/arm/src/sama5/sam_irq.c index afd25bc91..28b95738d 100644 --- a/nuttx/arch/arm/src/sama5/sam_irq.c +++ b/nuttx/arch/arm/src/sama5/sam_irq.c @@ -54,6 +54,8 @@ # include "sam_pio.h" #endif +#include "mmu.h" +#include "cache.h" #include "chip/sam_aic.h" #include "chip/sam_matrix.h" #include "chip/sam_aximx.h" @@ -76,6 +78,11 @@ typedef uint32_t *(*doirq_t)(int irq, uint32_t *regs); volatile uint32_t *current_regs; +/* Symbols defined via the linker script */ + +extern uint32_t _vector_start; /* Beginning of vector block */ +extern uint32_t _vector_end; /* End+1 of vector block */ + /**************************************************************************** * Private Data ****************************************************************************/ @@ -132,6 +139,25 @@ static void sam_dumpaic(const char *msg, int irq) #endif /**************************************************************************** + * Name: sam_vectorsize + * + * Description: + * Return the size of the vector data + * + ****************************************************************************/ + +static inline size_t sam_vectorsize(void) +{ + uintptr_t src; + uintptr_t end; + + src = (uintptr_t)&_vector_start; + end = (uintptr_t)&_vector_end; + + return (size_t)(end - src); +} + +/**************************************************************************** * Name: sam_spurious * * Description: @@ -210,6 +236,7 @@ static uint32_t *sam_fiqhandler(int irq, uint32_t *regs) void up_irqinitialize(void) { + size_t vectorsize; int i; /* The following operations need to be atomic, but since this function is @@ -314,6 +341,13 @@ void up_irqinitialize(void) putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap NOR FLASH */ #endif + /* Make sure that there is no trace of any previous mapping */ + + vectorsize = sam_vectorsize(); + cp15_invalidate_icache(); + cp15_invalidate_dcache(0, vectorsize); + mmu_invalidate_region(0, vectorsize); + /* Restore MATRIX write protection */ #if 0 /* Disabled on reset */ |