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| author | Gregory Nutt <gnutt@nuttx.org> | 2015-02-26 15:39:57 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2015-02-26 15:39:57 -0600 |
| commit | d4e59915c6072e917b5017d5fefe2afb840d4097 (patch) | |
| tree | e858c1ebcaf6e957a8c7153ed335509bf661abc1 | |
| parent | 8fb4981a49e58322a608b4c561f72c2f3d84db74 (diff) | |
| download | nuttx-d4e59915c6072e917b5017d5fefe2afb840d4097.tar.gz nuttx-d4e59915c6072e917b5017d5fefe2afb840d4097.tar.bz2 nuttx-d4e59915c6072e917b5017d5fefe2afb840d4097.zip | |
PIC32MZ: Fix some repeated typos and work around an issue with passing defined parameters to a macro that takes multiple parameters
| -rw-r--r-- | nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h | 12 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h | 1134 |
2 files changed, 577 insertions, 569 deletions
diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h index f8419b1f0..c0fbd48fa 100644 --- a/nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h +++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h @@ -71,10 +71,18 @@ * does not provide sufficient information. The output pin definitions include both the * register value and the register address and the following helper macros can be used * extract one or the other. + * + * NOTE: These odd macro forms are used to work around a pre-processor issue. The argument + * to PPS_OUTPUT_REGADDR is defined to have the form nn,xxxx but the preprocessor would + * claim that only one parameter is passed. The following version takes only one parameter + * and keeps the pre-processor happy. */ -#define PPS_OUTPUT_REGADDR(a,b) ((uintptr_t)(b)) -#define PPS_OUTPUT_REGVAL(a,b) ((uint32_t(a)) +#define __PPS_OUTPUT_REGADDR(a,b) ((uintptr_t)(b)) +#define PPS_OUTPUT_REGADDR(a) __PPS_OUTPUT_REGADDR(a) + +#define __PPS_OUTPUT_REGVAL(a,b) ((uint32_t)(a)) +#define PPS_OUTPUT_REGVAL(a) __PPS_OUTPUT_REGVAL(a) /******************************************************************************************** * Public Types diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h index eac6e2868..bddc7552b 100644 --- a/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h +++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h @@ -1138,572 +1138,572 @@ #define OC3_RPF1R 11, PI32MZ_RPF1R #define OC3_RPF4R 11, PI32MZ_RPF4R #define OC3_RPG1R 11, PI32MZ_RPG1R -#define OC3_RPG8R 11, PI32MZ_RPG8R - -#define OC4_RPA15R 11, PI32MZ_RPA15R -#define OC4_RPB1R 11, PI32MZ_RPB1R -#define OC4_RPB3R 11, PI32MZ_RPB3R -#define OC4_RPC4R 11, PI32MZ_RPC4R -#define OC4_RPC13R 11, PI32MZ_RPC13R -#define OC4_RPD3R 11, PI32MZ_RPD3R -#define OC4_RPD7R 11, PI32MZ_RPD7R -#define OC4_RPD11R 11, PI32MZ_RPD11R -#define OC4_RPD15R 11, PI32MZ_RPD15R -#define OC4_RPE5R 11, PI32MZ_RPE5R -#define OC4_RPF0R 11, PI32MZ_RPF0R -#define OC4_RPF5R 11, PI32MZ_RPF5R -#define OC4_RPG0R 11, PI32MZ_RPG0R -#define OC4_RPG7R 11, PI32MZ_RPG7R - -#define OC5_RPB0R 11, PI32MZ_RPB0R -#define OC5_RPB7R 11, PI32MZ_RPB7R -#define OC5_RPB8R 11, PI32MZ_RPB8R -#define OC5_RPB15R 11, PI32MZ_RPB15R -#define OC5_RPC3R 11, PI32MZ_RPC3R -#define OC5_RPD4R 11, PI32MZ_RPD4R -#define OC5_RPD9R 11, PI32MZ_RPD9R -#define OC5_RPD12R 11, PI32MZ_RPD12R -#define OC5_RPE3R 11, PI32MZ_RPE3R -#define OC5_RPE9R 11, PI32MZ_RPE9R -#define OC5_RPF8R 11, PI32MZ_RPF8R -#define OC5_RPF12R 11, PI32MZ_RPF12R -#define OC5_RPG6R 11, PI32MZ_RPG6R - -#define OC6_RPA14R 12, PI32MZ_RPA14R -#define OC6_RPB5R 12, PI32MZ_RPB5R -#define OC6_RPB9R 12, PI32MZ_RPB9R -#define OC6_RPB10R 12, PI32MZ_RPB10R -#define OC6_RPC1R 12, PI32MZ_RPC1R -#define OC6_RPC14R 12, PI32MZ_RPC14R -#define OC6_RPD2R 12, PI32MZ_RPD2R -#define OC6_RPD6R 12, PI32MZ_RPD6R -#define OC6_RPD10R 12, PI32MZ_RPD10R -#define OC6_RPD14R 12, PI32MZ_RPD14R -#define OC6_RPF1R 12, PI32MZ_RPF1R -#define OC6_RPF4R 12, PI32MZ_RPF4R -#define OC6_RPG1R 12, PI32MZ_RPG1R -#define OC6_RPG8R 12, PI32MZ_RPG8R - -#define OC7_RPA15R 12, PI32MZ_RPA15R -#define OC7_RPB1R 12, PI32MZ_RPB1R -#define OC7_RPB3R 12, PI32MZ_RPB3R -#define OC7_RPC4R 12, PI32MZ_RPC4R -#define OC7_RPC13R 12, PI32MZ_RPC13R -#define OC7_RPD3R 12, PI32MZ_RPD3R -#define OC7_RPD7R 12, PI32MZ_RPD7R -#define OC7_RPD11R 12, PI32MZ_RPD11R -#define OC7_RPD15R 12, PI32MZ_RPD15R -#define OC7_RPE5R 12, PI32MZ_RPE5R -#define OC7_RPF0R 12, PI32MZ_RPF0R -#define OC7_RPF5R 12, PI32MZ_RPF5R -#define OC7_RPG0R 12, PI32MZ_RPG0R -#define OC7_RPG7R 12, PI32MZ_RPG7R - -#define OC8_RPB0R 12, PI32MZ_RPB0R -#define OC8_RPB7R 12, PI32MZ_RPB7R -#define OC8_RPB8R 12, PI32MZ_RPB8R -#define OC8_RPB15R 12, PI32MZ_RPB15R -#define OC8_RPC3R 12, PI32MZ_RPC3R -#define OC8_RPD4R 12, PI32MZ_RPD4R -#define OC8_RPD9R 12, PI32MZ_RPD9R -#define OC8_RPD12R 12, PI32MZ_RPD12R -#define OC8_RPE3R 12, PI32MZ_RPE3R -#define OC8_RPE9R 12, PI32MZ_RPE9R -#define OC8_RPF8R 12, PI32MZ_RPF8R -#define OC8_RPF12R 12, PI32MZ_RPF12R -#define OC8_RPG6R 12, PI32MZ_RPG6R - -#define OC9_RPB2R 13, PI32MZ_RPB2R -#define OC9_RPB6R 13, PI32MZ_RPB6R -#define OC9_RPB14R 13, PI32MZ_RPB14R -#define OC9_RPC2R 13, PI32MZ_RPC2R -#define OC9_RPD0R 13, PI32MZ_RPD0R -#define OC9_RPD1R 13, PI32MZ_RPD1R -#define OC9_RPD5R 13, PI32MZ_RPD5R -#define OC9_RPE8R 13, PI32MZ_RPE8R -#define OC9_RPF2R 13, PI32MZ_RPF2R -#define OC9_RPF3R 13, PI32MZ_RPF3R -#define OC9_RPF13R 13, PI32MZ_RPF13R -#define OC9_RPG9R 13, PI32MZ_RPG9R - -#define REFCLKO1_RPA15R 15, PI32MZ_RPA15R -#define REFCLKO1_RPB1R 15, PI32MZ_RPB1R -#define REFCLKO1_RPB3R 15, PI32MZ_RPB3R -#define REFCLKO1_RPC4R 15, PI32MZ_RPC4R -#define REFCLKO1_RPC13R 15, PI32MZ_RPC13R -#define REFCLKO1_RPD3R 15, PI32MZ_RPD3R -#define REFCLKO1_RPD7R 15, PI32MZ_RPD7R -#define REFCLKO1_RPD11R 15, PI32MZ_RPD11R -#define REFCLKO1_RPD15R 15, PI32MZ_RPD15R -#define REFCLKO1_RPE5R 15, PI32MZ_RPE5R -#define REFCLKO1_RPF0R 15, PI32MZ_RPF0R -#define REFCLKO1_RPF5R 15, PI32MZ_RPF5R -#define REFCLKO1_RPG0R 15, PI32MZ_RPG0R -#define REFCLKO1_RPG7R 15, PI32MZ_RPG7R - -#define REFCLKO3_RPG6R 15, PI32MZ_RPG6R -#define REFCLKO3_RPB0R 15, PI32MZ_RPB0R -#define REFCLKO3_RPB7R 15, PI32MZ_RPB7R -#define REFCLKO3_RPB8R 15, PI32MZ_RPB8R -#define REFCLKO3_RPB15R 15, PI32MZ_RPB15R -#define REFCLKO3_RPC3R 15, PI32MZ_RPC3R -#define REFCLKO3_RPD4R 15, PI32MZ_RPD4R -#define REFCLKO3_RPD9R 15, PI32MZ_RPD9R -#define REFCLKO3_RPD12R 15, PI32MZ_RPD12R -#define REFCLKO3_RPE3R 15, PI32MZ_RPE3R -#define REFCLKO3_RPE9R 15, PI32MZ_RPE9R -#define REFCLKO3_RPF8R 15, PI32MZ_RPF8R -#define REFCLKO3_RPF12R 15, PI32MZ_RPF12R - -#define REFCLKO4_RPA14R 13, PI32MZ_RPA14R -#define REFCLKO4_RPB5R 13, PI32MZ_RPB5R -#define REFCLKO4_RPB9R 13, PI32MZ_RPB9R -#define REFCLKO4_RPB10R 13, PI32MZ_RPB10R -#define REFCLKO4_RPC1R 13, PI32MZ_RPC1R -#define REFCLKO4_RPC14R 13, PI32MZ_RPC14R -#define REFCLKO4_RPD2R 13, PI32MZ_RPD2R -#define REFCLKO4_RPD6R 13, PI32MZ_RPD6R -#define REFCLKO4_RPD10R 13, PI32MZ_RPD10R -#define REFCLKO4_RPD14R 13, PI32MZ_RPD14R -#define REFCLKO4_RPF1R 13, PI32MZ_RPF1R -#define REFCLKO4_RPF4R 13, PI32MZ_RPF4R -#define REFCLKO4_RPG1R 13, PI32MZ_RPG1R -#define REFCLKO4_RPG8R 13, PI32MZ_RPG8R - -#define SDO1_RPA14R 5, PI32MZ_RPA14R -#define SDO1_RPA15R 5, PI32MZ_RPA15R -#define SDO1_RPB1R 5, PI32MZ_RPB1R -#define SDO1_RPB3R 5, PI32MZ_RPB3R -#define SDO1_RPB5R 5, PI32MZ_RPB5R -#define SDO1_RPB9R 5, PI32MZ_RPB9R -#define SDO1_RPB10R 5, PI32MZ_RPB10R -#define SDO1_RPC1R 5, PI32MZ_RPC1R -#define SDO1_RPC4R 5, PI32MZ_RPC4R -#define SDO1_RPC13R 5, PI32MZ_RPC13R -#define SDO1_RPC14R 5, PI32MZ_RPC14R -#define SDO1_RPD2R 5, PI32MZ_RPD2R -#define SDO1_RPD3R 5, PI32MZ_RPD3R -#define SDO1_RPD6R 5, PI32MZ_RPD6R -#define SDO1_RPD7R 5, PI32MZ_RPD7R -#define SDO1_RPD10R 5, PI32MZ_RPD10R -#define SDO1_RPD11R 5, PI32MZ_RPD11R -#define SDO1_RPD14R 5, PI32MZ_RPD14R -#define SDO1_RPD15R 5, PI32MZ_RPD15R -#define SDO1_RPE5R 5, PI32MZ_RPE5R -#define SDO1_RPF0R 5, PI32MZ_RPF0R -#define SDO1_RPF1R 5, PI32MZ_RPF1R -#define SDO1_RPF4R 5, PI32MZ_RPF4R -#define SDO1_RPF5R 5, PI32MZ_RPF5R -#define SDO1_RPG0R 5, PI32MZ_RPG0R -#define SDO1_RPG1R 5, PI32MZ_RPG1R -#define SDO1_RPG7R 5, PI32MZ_RPG7R -#define SDO1_RPG8R 5, PI32MZ_RPG8R - -#define SDO2_RPA14R 6, PI32MZ_RPA14R -#define SDO2_RPA15R 6, PI32MZ_RPA15R -#define SDO2_RPB1R 6, PI32MZ_RPB1R -#define SDO2_RPB3R 6, PI32MZ_RPB3R -#define SDO2_RPB5R 6, PI32MZ_RPB5R -#define SDO2_RPB9R 6, PI32MZ_RPB9R -#define SDO2_RPB10R 6, PI32MZ_RPB10R -#define SDO2_RPC1R 6, PI32MZ_RPC1R -#define SDO2_RPC4R 6, PI32MZ_RPC4R -#define SDO2_RPC13R 6, PI32MZ_RPC13R -#define SDO2_RPC14R 6, PI32MZ_RPC14R -#define SDO2_RPD2R 6, PI32MZ_RPD2R -#define SDO2_RPD3R 6, PI32MZ_RPD3R -#define SDO2_RPD6R 6, PI32MZ_RPD6R -#define SDO2_RPD7R 6, PI32MZ_RPD7R -#define SDO2_RPD10R 6, PI32MZ_RPD10R -#define SDO2_RPD11R 6, PI32MZ_RPD11R -#define SDO2_RPD14R 6, PI32MZ_RPD14R -#define SDO2_RPD15R 6, PI32MZ_RPD15R -#define SDO2_RPE5R 6, PI32MZ_RPE5R -#define SDO2_RPF0R 6, PI32MZ_RPF0R -#define SDO2_RPF1R 6, PI32MZ_RPF1R -#define SDO2_RPF4R 6, PI32MZ_RPF4R -#define SDO2_RPF5R 6, PI32MZ_RPF5R -#define SDO2_RPG0R 6, PI32MZ_RPG0R -#define SDO2_RPG1R 6, PI32MZ_RPG1R -#define SDO2_RPG7R 6, PI32MZ_RPG7R -#define SDO2_RPG8R 6, PI32MZ_RPG8R - -#define SDO3_RPA14R 7, PI32MZ_RPA14R -#define SDO3_RPA15R 7, PI32MZ_RPA15R -#define SDO3_RPB1R 7, PI32MZ_RPB1R -#define SDO3_RPB3R 7, PI32MZ_RPB3R -#define SDO3_RPB5R 7, PI32MZ_RPB5R -#define SDO3_RPB9R 7, PI32MZ_RPB9R -#define SDO3_RPB10R 7, PI32MZ_RPB10R -#define SDO3_RPC1R 7, PI32MZ_RPC1R -#define SDO3_RPC4R 7, PI32MZ_RPC4R -#define SDO3_RPC13R 7, PI32MZ_RPC13R -#define SDO3_RPC14R 7, PI32MZ_RPC14R -#define SDO3_RPD2R 7, PI32MZ_RPD2R -#define SDO3_RPD3R 7, PI32MZ_RPD3R -#define SDO3_RPD6R 7, PI32MZ_RPD6R -#define SDO3_RPD7R 7, PI32MZ_RPD7R -#define SDO3_RPD10R 7, PI32MZ_RPD10R -#define SDO3_RPD11R 7, PI32MZ_RPD11R -#define SDO3_RPD14R 7, PI32MZ_RPD14R -#define SDO3_RPD15R 7, PI32MZ_RPD15R -#define SDO3_RPE5R 7, PI32MZ_RPE5R -#define SDO3_RPF0R 7, PI32MZ_RPF0R -#define SDO3_RPF1R 7, PI32MZ_RPF1R -#define SDO3_RPF4R 7, PI32MZ_RPF4R -#define SDO3_RPF5R 7, PI32MZ_RPF5R -#define SDO3_RPG0R 7, PI32MZ_RPG0R -#define SDO3_RPG1R 7, PI32MZ_RPG1R -#define SDO3_RPG7R 7, PI32MZ_RPG7R -#define SDO3_RPG8R 7, PI32MZ_RPG8R - -#define SDO4_RPA15R 8, PI32MZ_RPA15R -#define SDO4_RPB1R 8, PI32MZ_RPB1R -#define SDO4_RPB2R 8, PI32MZ_RPB2R -#define SDO4_RPB3R 8, PI32MZ_RPB3R -#define SDO4_RPB6R 8, PI32MZ_RPB6R -#define SDO4_RPB14R 8, PI32MZ_RPB14R -#define SDO4_RPC2R 8, PI32MZ_RPC2R -#define SDO4_RPC4R 8, PI32MZ_RPC4R -#define SDO4_RPC13R 8, PI32MZ_RPC13R -#define SDO4_RPD0R 8, PI32MZ_RPD0R -#define SDO4_RPD1R 8, PI32MZ_RPD1R -#define SDO4_RPD3R 8, PI32MZ_RPD3R -#define SDO4_RPD5R 8, PI32MZ_RPD5R -#define SDO4_RPD7R 8, PI32MZ_RPD7R -#define SDO4_RPD11R 8, PI32MZ_RPD11R -#define SDO4_RPD15R 8, PI32MZ_RPD15R -#define SDO4_RPE5R 8, PI32MZ_RPE5R -#define SDO4_RPE8R 8, PI32MZ_RPE8R -#define SDO4_RPF0R 8, PI32MZ_RPF0R -#define SDO4_RPF2R 8, PI32MZ_RPF2R -#define SDO4_RPF3R 8, PI32MZ_RPF3R -#define SDO4_RPF5R 8, PI32MZ_RPF5R -#define SDO4_RPF13R 8, PI32MZ_RPF13R -#define SDO4_RPG0R 8, PI32MZ_RPG0R -#define SDO4_RPG7R 8, PI32MZ_RPG7R -#define SDO4_RPG9R 8, PI32MZ_RPG9R - -#define SDO5_RPA14R 9, PI32MZ_RPA14R -#define SDO5_RPA15R 9, PI32MZ_RPA15R -#define SDO5_RPB1R 9, PI32MZ_RPB1R -#define SDO5_RPB3R 9, PI32MZ_RPB3R -#define SDO5_RPB5R 9, PI32MZ_RPB5R -#define SDO5_RPB9R 9, PI32MZ_RPB9R -#define SDO5_RPB10R 9, PI32MZ_RPB10R -#define SDO5_RPC1R 9, PI32MZ_RPC1R -#define SDO5_RPC4R 9, PI32MZ_RPC4R -#define SDO5_RPC13R 9, PI32MZ_RPC13R -#define SDO5_RPC14R 9, PI32MZ_RPC14R -#define SDO5_RPD2R 9, PI32MZ_RPD2R -#define SDO5_RPD3R 9, PI32MZ_RPD3R -#define SDO5_RPD6R 9, PI32MZ_RPD6R -#define SDO5_RPD7R 9, PI32MZ_RPD7R -#define SDO5_RPD10R 9, PI32MZ_RPD10R -#define SDO5_RPD11R 9, PI32MZ_RPD11R -#define SDO5_RPD14R 9, PI32MZ_RPD14R -#define SDO5_RPD15R 9, PI32MZ_RPD15R -#define SDO5_RPE5R 9, PI32MZ_RPE5R -#define SDO5_RPF0R 9, PI32MZ_RPF0R -#define SDO5_RPF1R 9, PI32MZ_RPF1R -#define SDO5_RPF4R 9, PI32MZ_RPF4R -#define SDO5_RPF5R 9, PI32MZ_RPF5R -#define SDO5_RPG0R 9, PI32MZ_RPG0R -#define SDO5_RPG1R 9, PI32MZ_RPG1R -#define SDO5_RPG7R 9, PI32MZ_RPG7R -#define SDO5_RPG8R 9, PI32MZ_RPG8R - -#define SDO6_RPB0R 10, PI32MZ_RPB0R -#define SDO6_RPB2R 10, PI32MZ_RPB2R -#define SDO6_RPB6R 10, PI32MZ_RPB6R -#define SDO6_RPB7R 10, PI32MZ_RPB7R -#define SDO6_RPB8R 10, PI32MZ_RPB8R -#define SDO6_RPB14R 10, PI32MZ_RPB14R -#define SDO6_RPB15R 10, PI32MZ_RPB15R -#define SDO6_RPC2R 10, PI32MZ_RPC2R -#define SDO6_RPC3R 10, PI32MZ_RPC3R -#define SDO6_RPD0R 10, PI32MZ_RPD0R -#define SDO6_RPD1R 10, PI32MZ_RPD1R -#define SDO6_RPD4R 10, PI32MZ_RPD4R -#define SDO6_RPD5R 10, PI32MZ_RPD5R -#define SDO6_RPD9R 10, PI32MZ_RPD9R -#define SDO6_RPD12R 10, PI32MZ_RPD12R -#define SDO6_RPE3R 10, PI32MZ_RPE3R -#define SDO6_RPE8R 10, PI32MZ_RPE8R -#define SDO6_RPE9R 10, PI32MZ_RPE9R -#define SDO6_RPF2R 10, PI32MZ_RPF2R -#define SDO6_RPF3R 10, PI32MZ_RPF3R -#define SDO6_RPF8R 10, PI32MZ_RPF8R -#define SDO6_RPF12R 10, PI32MZ_RPF12R -#define SDO6_RPF13R 10, PI32MZ_RPF13R -#define SDO6_RPG6R 10, PI32MZ_RPG6R -#define SDO6_RPG9R 10, PI32MZ_RPG9R - -#define SS1_RPB0R 5, PI32MZ_RPB0R -#define SS1_RPB7R 5, PI32MZ_RPB7R -#define SS1_RPB8R 5, PI32MZ_RPB8R -#define SS1_RPB15R 5, PI32MZ_RPB15R -#define SS1_RPC3R 5, PI32MZ_RPC3R -#define SS1_RPD4R 5, PI32MZ_RPD4R -#define SS1_RPD9R 5, PI32MZ_RPD9R -#define SS1_RPD12R 5, PI32MZ_RPD12R -#define SS1_RPE3R 5, PI32MZ_RPE3R -#define SS1_RPE9R 5, PI32MZ_RPE9R -#define SS1_RPF8R 5, PI32MZ_RPF8R -#define SS1_RPF12R 5, PI32MZ_RPF12R -#define SS1_RPG6R 5, PI32MZ_RPG6R - -#define SS2_RPB2R 6, PI32MZ_RPB2R -#define SS2_RPB6R 6, PI32MZ_RPB6R -#define SS2_RPB14R 6, PI32MZ_RPB14R -#define SS2_RPC2R 6, PI32MZ_RPC2R -#define SS2_RPD0R 6, PI32MZ_RPD0R -#define SS2_RPD1R 6, PI32MZ_RPD1R -#define SS2_RPD5R 6, PI32MZ_RPD5R -#define SS2_RPE8R 6, PI32MZ_RPE8R -#define SS2_RPF2R 6, PI32MZ_RPF2R -#define SS2_RPF3R 6, PI32MZ_RPF3R -#define SS2_RPF13R 6, PI32MZ_RPF13R -#define SS2_RPG9R 6, PI32MZ_RPG9R - -#define SS3_RPB0R 7, PI32MZ_RPB0R -#define SS3_RPB7R 7, PI32MZ_RPB7R -#define SS3_RPB8R 7, PI32MZ_RPB8R -#define SS3_RPB15R 7, PI32MZ_RPB15R -#define SS3_RPC3R 7, PI32MZ_RPC3R -#define SS3_RPD4R 7, PI32MZ_RPD4R -#define SS3_RPD9R 7, PI32MZ_RPD9R -#define SS3_RPD12R 7, PI32MZ_RPD12R -#define SS3_RPE3R 7, PI32MZ_RPE3R -#define SS3_RPE9R 7, PI32MZ_RPE9R -#define SS3_RPF8R 7, PI32MZ_RPF8R -#define SS3_RPF12R 7, PI32MZ_RPF12R -#define SS3_RPG6R 7, PI32MZ_RPG6R - -#define SS4_RPB0R 8, PI32MZ_RPB0R -#define SS4_RPB7R 8, PI32MZ_RPB7R -#define SS4_RPB8R 8, PI32MZ_RPB8R -#define SS4_RPB15R 8, PI32MZ_RPB15R -#define SS4_RPC3R 8, PI32MZ_RPC3R -#define SS4_RPD4R 8, PI32MZ_RPD4R -#define SS4_RPD9R 8, PI32MZ_RPD9R -#define SS4_RPD12R 8, PI32MZ_RPD12R -#define SS4_RPE3R 8, PI32MZ_RPE3R -#define SS4_RPE9R 8, PI32MZ_RPE9R -#define SS4_RPF8R 8, PI32MZ_RPF8R -#define SS4_RPF12R 8, PI32MZ_RPF12R -#define SS4_RPG6R 8, PI32MZ_RPG6R - -#define SS5_RPB0R 9, PI32MZ_RPB0R -#define SS5_RPB7R 9, PI32MZ_RPB7R -#define SS5_RPB8R 9, PI32MZ_RPB8R -#define SS5_RPB15R 9, PI32MZ_RPB15R -#define SS5_RPC3R 9, PI32MZ_RPC3R -#define SS5_RPD4R 9, PI32MZ_RPD4R -#define SS5_RPD9R 9, PI32MZ_RPD9R -#define SS5_RPD12R 9, PI32MZ_RPD12R -#define SS5_RPE3R 9, PI32MZ_RPE3R -#define SS5_RPE9R 9, PI32MZ_RPE9R -#define SS5_RPF8R 9, PI32MZ_RPF8R -#define SS5_RPF12R 9, PI32MZ_RPF12R -#define SS5_RPG6R 9, PI32MZ_RPG6R - -#define SS6_RPA14R 10, PI32MZ_RPA14R -#define SS6_RPB5R 10, PI32MZ_RPB5R -#define SS6_RPB9R 10, PI32MZ_RPB9R -#define SS6_RPB10R 10, PI32MZ_RPB10R -#define SS6_RPC1R 10, PI32MZ_RPC1R -#define SS6_RPC14R 10, PI32MZ_RPC14R -#define SS6_RPD2R 10, PI32MZ_RPD2R -#define SS6_RPD6R 10, PI32MZ_RPD6R -#define SS6_RPD10R 10, PI32MZ_RPD10R -#define SS6_RPD14R 10, PI32MZ_RPD14R -#define SS6_RPF1R 10, PI32MZ_RPF1R -#define SS6_RPF4R 10, PI32MZ_RPF4R -#define SS6_RPG1R 10, PI32MZ_RPG1R -#define SS6_RPG8R 10, PI32MZ_RPG8R - -#define U1RTS_RPB2R 1, PI32MZ_RPB2R -#define U1RTS_RPB6R 1, PI32MZ_RPB6R -#define U1RTS_RPB14R 1, PI32MZ_RPB14R -#define U1RTS_RPC2R 1, PI32MZ_RPC2R -#define U1RTS_RPD0R 1, PI32MZ_RPD0R -#define U1RTS_RPD1R 1, PI32MZ_RPD1R -#define U1RTS_RPD5R 1, PI32MZ_RPD5R -#define U1RTS_RPE8R 1, PI32MZ_RPE8R -#define U1RTS_RPF2R 1, PI32MZ_RPF2R -#define U1RTS_RPF3R 1, PI32MZ_RPF3R -#define U1RTS_RPF13R 1, PI32MZ_RPF13R -#define U1RTS_RPG9R 1, PI32MZ_RPG9R - -#define U1TX_RPA15R 1, PI32MZ_RPA15R -#define U1TX_RPB1R 1, PI32MZ_RPB1R -#define U1TX_RPB3R 1, PI32MZ_RPB3R -#define U1TX_RPC4R 1, PI32MZ_RPC4R -#define U1TX_RPC13R 1, PI32MZ_RPC13R -#define U1TX_RPD3R 1, PI32MZ_RPD3R -#define U1TX_RPD7R 1, PI32MZ_RPD7R -#define U1TX_RPD11R 1, PI32MZ_RPD11R -#define U1TX_RPD15R 1, PI32MZ_RPD15R -#define U1TX_RPE5R 1, PI32MZ_RPE5R -#define U1TX_RPF0R 1, PI32MZ_RPF0R -#define U1TX_RPF5R 1, PI32MZ_RPF5R -#define U1TX_RPG0R 1, PI32MZ_RPG0R -#define U1TX_RPG7R 1, PI32MZ_RPG7R - -#define U2RTS_RPA15R 2, PI32MZ_RPA15R -#define U2RTS_RPB1R 2, PI32MZ_RPB1R -#define U2RTS_RPB3R 2, PI32MZ_RPB3R -#define U2RTS_RPC4R 2, PI32MZ_RPC4R -#define U2RTS_RPC13R 2, PI32MZ_RPC13R -#define U2RTS_RPD3R 2, PI32MZ_RPD3R -#define U2RTS_RPD7R 2, PI32MZ_RPD7R -#define U2RTS_RPD11R 2, PI32MZ_RPD11R -#define U2RTS_RPD15R 2, PI32MZ_RPD15R -#define U2RTS_RPE5R 2, PI32MZ_RPE5R -#define U2RTS_RPF0R 2, PI32MZ_RPF0R -#define U2RTS_RPF5R 2, PI32MZ_RPF5R -#define U2RTS_RPG0R 2, PI32MZ_RPG0R -#define U2RTS_RPG7R 2, PI32MZ_RPG7R - -#define U2TX_RPB2R 2, PI32MZ_RPB2R -#define U2TX_RPB6R 2, PI32MZ_RPB6R -#define U2TX_RPB14R 2, PI32MZ_RPB14R -#define U2TX_RPC2R 2, PI32MZ_RPC2R -#define U2TX_RPD0R 2, PI32MZ_RPD0R -#define U2TX_RPD1R 2, PI32MZ_RPD1R -#define U2TX_RPD5R 2, PI32MZ_RPD5R -#define U2TX_RPE8R 2, PI32MZ_RPE8R -#define U2TX_RPF2R 2, PI32MZ_RPF2R -#define U2TX_RPF3R 2, PI32MZ_RPF3R -#define U2TX_RPF13R 2, PI32MZ_RPF13R -#define U2TX_RPG9R 2, PI32MZ_RPG9R - -#define U3RTS_RPB0R 1, PI32MZ_RPB0R -#define U3RTS_RPB7R 1, PI32MZ_RPB7R -#define U3RTS_RPB8R 1, PI32MZ_RPB8R -#define U3RTS_RPB15R 1, PI32MZ_RPB15R -#define U3RTS_RPC3R 1, PI32MZ_RPC3R -#define U3RTS_RPD4R 1, PI32MZ_RPD4R -#define U3RTS_RPD9R 1, PI32MZ_RPD9R -#define U3RTS_RPD12R 1, PI32MZ_RPD12R -#define U3RTS_RPE3R 1, PI32MZ_RPE3R -#define U3RTS_RPE9R 1, PI32MZ_RPE9R -#define U3RTS_RPF8R 1, PI32MZ_RPF8R -#define U3RTS_RPF12R 1, PI32MZ_RPF12R -#define U3RTS_RPG6R 1, PI32MZ_RPG6R - -#define U3TX_RPA14R 1, PI32MZ_RPA14R -#define U3TX_RPB5R 1, PI32MZ_RPB5R -#define U3TX_RPB9R 1, PI32MZ_RPB9R -#define U3TX_RPB10R 1, PI32MZ_RPB10R -#define U3TX_RPC1R 1, PI32MZ_RPC1R -#define U3TX_RPC14R 1, PI32MZ_RPC14R -#define U3TX_RPD2R 1, PI32MZ_RPD2R -#define U3TX_RPD6R 1, PI32MZ_RPD6R -#define U3TX_RPD10R 1, PI32MZ_RPD10R -#define U3TX_RPD14R 1, PI32MZ_RPD14R -#define U3TX_RPF1R 1, PI32MZ_RPF1R -#define U3TX_RPF4R 1, PI32MZ_RPF4R -#define U3TX_RPG1R 1, PI32MZ_RPG1R -#define U3TX_RPG8R 1, PI32MZ_RPG8R - -#define U4RTS_RPA14R 2, PI32MZ_RPA14R -#define U4RTS_RPB5R 2, PI32MZ_RPB5R -#define U4RTS_RPB9R 2, PI32MZ_RPB9R -#define U4RTS_RPB10R 2, PI32MZ_RPB10R -#define U4RTS_RPC1R 2, PI32MZ_RPC1R -#define U4RTS_RPC14R 2, PI32MZ_RPC14R -#define U4RTS_RPD2R 2, PI32MZ_RPD2R -#define U4RTS_RPD6R 2, PI32MZ_RPD6R -#define U4RTS_RPD10R 2, PI32MZ_RPD10R -#define U4RTS_RPD14R 2, PI32MZ_RPD14R -#define U4RTS_RPF1R 2, PI32MZ_RPF1R -#define U4RTS_RPF4R 2, PI32MZ_RPF4R -#define U4RTS_RPG1R 2, PI32MZ_RPG1R -#define U4RTS_RPG8R 2, PI32MZ_RPG8R - -#define U4TX_RPB0R 2, PI32MZ_RPB0R -#define U4TX_RPB7R 2, PI32MZ_RPB7R -#define U4TX_RPB8R 2, PI32MZ_RPB8R -#define U4TX_RPB15R 2, PI32MZ_RPB15R -#define U4TX_RPC3R 2, PI32MZ_RPC3R -#define U4TX_RPD4R 2, PI32MZ_RPD4R -#define U4TX_RPD9R 2, PI32MZ_RPD9R -#define U4TX_RPD12R 2, PI32MZ_RPD12R -#define U4TX_RPE3R 2, PI32MZ_RPE3R -#define U4TX_RPE9R 2, PI32MZ_RPE9R -#define U4TX_RPF8R 2, PI32MZ_RPF8R -#define U4TX_RPF12R 2, PI32MZ_RPF12R -#define U4TX_RPG6R 2, PI32MZ_RPG6R - -#define U5RTS_RPB2R 3, PI32MZ_RPB2R -#define U5RTS_RPB6R 3, PI32MZ_RPB6R -#define U5RTS_RPB14R 3, PI32MZ_RPB14R -#define U5RTS_RPC2R 3, PI32MZ_RPC2R -#define U5RTS_RPD0R 3, PI32MZ_RPD0R -#define U5RTS_RPD1R 3, PI32MZ_RPD1R -#define U5RTS_RPD5R 3, PI32MZ_RPD5R -#define U5RTS_RPE8R 3, PI32MZ_RPE8R -#define U5RTS_RPF2R 3, PI32MZ_RPF2R -#define U5RTS_RPF3R 3, PI32MZ_RPF3R -#define U5RTS_RPF13R 3, PI32MZ_RPF13R -#define U5RTS_RPG9R 3, PI32MZ_RPG9R - -#define U5TX_RPA15R 3, PI32MZ_RPA15R -#define U5TX_RPB1R 3, PI32MZ_RPB1R -#define U5TX_RPB3R 3, PI32MZ_RPB3R -#define U5TX_RPC4R 3, PI32MZ_RPC4R -#define U5TX_RPC13R 3, PI32MZ_RPC13R -#define U5TX_RPD3R 3, PI32MZ_RPD3R -#define U5TX_RPD7R 3, PI32MZ_RPD7R -#define U5TX_RPD11R 3, PI32MZ_RPD11R -#define U5TX_RPD15R 3, PI32MZ_RPD15R -#define U5TX_RPE5R 3, PI32MZ_RPE5R -#define U5TX_RPF0R 3, PI32MZ_RPF0R -#define U5TX_RPF5R 3, PI32MZ_RPF5R -#define U5TX_RPG0R 3, PI32MZ_RPG0R -#define U5TX_RPG7R 3, PI32MZ_RPG7R - -#define U6RTS_RPA15R 4, PI32MZ_RPA15R -#define U6RTS_RPB1R 4, PI32MZ_RPB1R -#define U6RTS_RPB3R 4, PI32MZ_RPB3R -#define U6RTS_RPC4R 4, PI32MZ_RPC4R -#define U6RTS_RPC13R 4, PI32MZ_RPC13R -#define U6RTS_RPD3R 4, PI32MZ_RPD3R -#define U6RTS_RPD7R 4, PI32MZ_RPD7R -#define U6RTS_RPD11R 4, PI32MZ_RPD11R -#define U6RTS_RPD15R 4, PI32MZ_RPD15R -#define U6RTS_RPE5R 4, PI32MZ_RPE5R -#define U6RTS_RPF0R 4, PI32MZ_RPF0R -#define U6RTS_RPF5R 4, PI32MZ_RPF5R -#define U6RTS_RPG0R 4, PI32MZ_RPG0R -#define U6RTS_RPG7R 4, PI32MZ_RPG7R - -#define U6TX_RPB0R 4, PI32MZ_RPB0R -#define U6TX_RPB2R 4, PI32MZ_RPB2R -#define U6TX_RPB6R 4, PI32MZ_RPB6R -#define U6TX_RPB7R 4, PI32MZ_RPB7R -#define U6TX_RPB8R 4, PI32MZ_RPB8R -#define U6TX_RPB14R 4, PI32MZ_RPB14R -#define U6TX_RPB15R 4, PI32MZ_RPB15R -#define U6TX_RPC2R 4, PI32MZ_RPC2R -#define U6TX_RPC3R 4, PI32MZ_RPC3R -#define U6TX_RPD0R 4, PI32MZ_RPD0R -#define U6TX_RPD1R 4, PI32MZ_RPD1R -#define U6TX_RPD4R 4, PI32MZ_RPD4R -#define U6TX_RPD5R 4, PI32MZ_RPD5R -#define U6TX_RPD9R 4, PI32MZ_RPD9R -#define U6TX_RPD12R 4, PI32MZ_RPD12R -#define U6TX_RPE3R 4, PI32MZ_RPE3R -#define U6TX_RPE8R 4, PI32MZ_RPE8R -#define U6TX_RPE9R 4, PI32MZ_RPE9R -#define U6TX_RPF2R 4, PI32MZ_RPF2R -#define U6TX_RPF3R 4, PI32MZ_RPF3R -#define U6TX_RPF8R 4, PI32MZ_RPF8R -#define U6TX_RPF12R 4, PI32MZ_RPF12R -#define U6TX_RPF13R 4, PI32MZ_RPF13R -#define U6TX_RPG6R 4, PI32MZ_RPG6R -#define U6TX_RPG9R 4, PI32MZ_RPG9R +#define OC3_RPG8R 11, PIC32MZ_RPG8R + +#define OC4_RPA15R 11, PIC32MZ_RPA15R +#define OC4_RPB1R 11, PIC32MZ_RPB1R +#define OC4_RPB3R 11, PIC32MZ_RPB3R +#define OC4_RPC4R 11, PIC32MZ_RPC4R +#define OC4_RPC13R 11, PIC32MZ_RPC13R +#define OC4_RPD3R 11, PIC32MZ_RPD3R +#define OC4_RPD7R 11, PIC32MZ_RPD7R +#define OC4_RPD11R 11, PIC32MZ_RPD11R +#define OC4_RPD15R 11, PIC32MZ_RPD15R +#define OC4_RPE5R 11, PIC32MZ_RPE5R +#define OC4_RPF0R 11, PIC32MZ_RPF0R +#define OC4_RPF5R 11, PIC32MZ_RPF5R +#define OC4_RPG0R 11, PIC32MZ_RPG0R +#define OC4_RPG7R 11, PIC32MZ_RPG7R + +#define OC5_RPB0R 11, PIC32MZ_RPB0R +#define OC5_RPB7R 11, PIC32MZ_RPB7R +#define OC5_RPB8R 11, PIC32MZ_RPB8R +#define OC5_RPB15R 11, PIC32MZ_RPB15R +#define OC5_RPC3R 11, PIC32MZ_RPC3R +#define OC5_RPD4R 11, PIC32MZ_RPD4R +#define OC5_RPD9R 11, PIC32MZ_RPD9R +#define OC5_RPD12R 11, PIC32MZ_RPD12R +#define OC5_RPE3R 11, PIC32MZ_RPE3R +#define OC5_RPE9R 11, PIC32MZ_RPE9R +#define OC5_RPF8R 11, PIC32MZ_RPF8R +#define OC5_RPF12R 11, PIC32MZ_RPF12R +#define OC5_RPG6R 11, PIC32MZ_RPG6R + +#define OC6_RPA14R 12, PIC32MZ_RPA14R +#define OC6_RPB5R 12, PIC32MZ_RPB5R +#define OC6_RPB9R 12, PIC32MZ_RPB9R +#define OC6_RPB10R 12, PIC32MZ_RPB10R +#define OC6_RPC1R 12, PIC32MZ_RPC1R +#define OC6_RPC14R 12, PIC32MZ_RPC14R +#define OC6_RPD2R 12, PIC32MZ_RPD2R +#define OC6_RPD6R 12, PIC32MZ_RPD6R +#define OC6_RPD10R 12, PIC32MZ_RPD10R +#define OC6_RPD14R 12, PIC32MZ_RPD14R +#define OC6_RPF1R 12, PIC32MZ_RPF1R +#define OC6_RPF4R 12, PIC32MZ_RPF4R +#define OC6_RPG1R 12, PIC32MZ_RPG1R +#define OC6_RPG8R 12, PIC32MZ_RPG8R + +#define OC7_RPA15R 12, PIC32MZ_RPA15R +#define OC7_RPB1R 12, PIC32MZ_RPB1R +#define OC7_RPB3R 12, PIC32MZ_RPB3R +#define OC7_RPC4R 12, PIC32MZ_RPC4R +#define OC7_RPC13R 12, PIC32MZ_RPC13R +#define OC7_RPD3R 12, PIC32MZ_RPD3R +#define OC7_RPD7R 12, PIC32MZ_RPD7R +#define OC7_RPD11R 12, PIC32MZ_RPD11R +#define OC7_RPD15R 12, PIC32MZ_RPD15R +#define OC7_RPE5R 12, PIC32MZ_RPE5R +#define OC7_RPF0R 12, PIC32MZ_RPF0R +#define OC7_RPF5R 12, PIC32MZ_RPF5R +#define OC7_RPG0R 12, PIC32MZ_RPG0R +#define OC7_RPG7R 12, PIC32MZ_RPG7R + +#define OC8_RPB0R 12, PIC32MZ_RPB0R +#define OC8_RPB7R 12, PIC32MZ_RPB7R +#define OC8_RPB8R 12, PIC32MZ_RPB8R +#define OC8_RPB15R 12, PIC32MZ_RPB15R +#define OC8_RPC3R 12, PIC32MZ_RPC3R +#define OC8_RPD4R 12, PIC32MZ_RPD4R +#define OC8_RPD9R 12, PIC32MZ_RPD9R +#define OC8_RPD12R 12, PIC32MZ_RPD12R +#define OC8_RPE3R 12, PIC32MZ_RPE3R +#define OC8_RPE9R 12, PIC32MZ_RPE9R +#define OC8_RPF8R 12, PIC32MZ_RPF8R +#define OC8_RPF12R 12, PIC32MZ_RPF12R +#define OC8_RPG6R 12, PIC32MZ_RPG6R + +#define OC9_RPB2R 13, PIC32MZ_RPB2R +#define OC9_RPB6R 13, PIC32MZ_RPB6R +#define OC9_RPB14R 13, PIC32MZ_RPB14R +#define OC9_RPC2R 13, PIC32MZ_RPC2R +#define OC9_RPD0R 13, PIC32MZ_RPD0R +#define OC9_RPD1R 13, PIC32MZ_RPD1R +#define OC9_RPD5R 13, PIC32MZ_RPD5R +#define OC9_RPE8R 13, PIC32MZ_RPE8R +#define OC9_RPF2R 13, PIC32MZ_RPF2R +#define OC9_RPF3R 13, PIC32MZ_RPF3R +#define OC9_RPF13R 13, PIC32MZ_RPF13R +#define OC9_RPG9R 13, PIC32MZ_RPG9R + +#define REFCLKO1_RPA15R 15, PIC32MZ_RPA15R +#define REFCLKO1_RPB1R 15, PIC32MZ_RPB1R +#define REFCLKO1_RPB3R 15, PIC32MZ_RPB3R +#define REFCLKO1_RPC4R 15, PIC32MZ_RPC4R +#define REFCLKO1_RPC13R 15, PIC32MZ_RPC13R +#define REFCLKO1_RPD3R 15, PIC32MZ_RPD3R +#define REFCLKO1_RPD7R 15, PIC32MZ_RPD7R +#define REFCLKO1_RPD11R 15, PIC32MZ_RPD11R +#define REFCLKO1_RPD15R 15, PIC32MZ_RPD15R +#define REFCLKO1_RPE5R 15, PIC32MZ_RPE5R +#define REFCLKO1_RPF0R 15, PIC32MZ_RPF0R +#define REFCLKO1_RPF5R 15, PIC32MZ_RPF5R +#define REFCLKO1_RPG0R 15, PIC32MZ_RPG0R +#define REFCLKO1_RPG7R 15, PIC32MZ_RPG7R + +#define REFCLKO3_RPG6R 15, PIC32MZ_RPG6R +#define REFCLKO3_RPB0R 15, PIC32MZ_RPB0R +#define REFCLKO3_RPB7R 15, PIC32MZ_RPB7R +#define REFCLKO3_RPB8R 15, PIC32MZ_RPB8R +#define REFCLKO3_RPB15R 15, PIC32MZ_RPB15R +#define REFCLKO3_RPC3R 15, PIC32MZ_RPC3R +#define REFCLKO3_RPD4R 15, PIC32MZ_RPD4R +#define REFCLKO3_RPD9R 15, PIC32MZ_RPD9R +#define REFCLKO3_RPD12R 15, PIC32MZ_RPD12R +#define REFCLKO3_RPE3R 15, PIC32MZ_RPE3R +#define REFCLKO3_RPE9R 15, PIC32MZ_RPE9R +#define REFCLKO3_RPF8R 15, PIC32MZ_RPF8R +#define REFCLKO3_RPF12R 15, PIC32MZ_RPF12R + +#define REFCLKO4_RPA14R 13, PIC32MZ_RPA14R +#define REFCLKO4_RPB5R 13, PIC32MZ_RPB5R +#define REFCLKO4_RPB9R 13, PIC32MZ_RPB9R +#define REFCLKO4_RPB10R 13, PIC32MZ_RPB10R +#define REFCLKO4_RPC1R 13, PIC32MZ_RPC1R +#define REFCLKO4_RPC14R 13, PIC32MZ_RPC14R +#define REFCLKO4_RPD2R 13, PIC32MZ_RPD2R +#define REFCLKO4_RPD6R 13, PIC32MZ_RPD6R +#define REFCLKO4_RPD10R 13, PIC32MZ_RPD10R +#define REFCLKO4_RPD14R 13, PIC32MZ_RPD14R +#define REFCLKO4_RPF1R 13, PIC32MZ_RPF1R +#define REFCLKO4_RPF4R 13, PIC32MZ_RPF4R +#define REFCLKO4_RPG1R 13, PIC32MZ_RPG1R +#define REFCLKO4_RPG8R 13, PIC32MZ_RPG8R + +#define SDO1_RPA14R 5, PIC32MZ_RPA14R +#define SDO1_RPA15R 5, PIC32MZ_RPA15R +#define SDO1_RPB1R 5, PIC32MZ_RPB1R +#define SDO1_RPB3R 5, PIC32MZ_RPB3R +#define SDO1_RPB5R 5, PIC32MZ_RPB5R +#define SDO1_RPB9R 5, PIC32MZ_RPB9R +#define SDO1_RPB10R 5, PIC32MZ_RPB10R +#define SDO1_RPC1R 5, PIC32MZ_RPC1R +#define SDO1_RPC4R 5, PIC32MZ_RPC4R +#define SDO1_RPC13R 5, PIC32MZ_RPC13R +#define SDO1_RPC14R 5, PIC32MZ_RPC14R +#define SDO1_RPD2R 5, PIC32MZ_RPD2R +#define SDO1_RPD3R 5, PIC32MZ_RPD3R +#define SDO1_RPD6R 5, PIC32MZ_RPD6R +#define SDO1_RPD7R 5, PIC32MZ_RPD7R +#define SDO1_RPD10R 5, PIC32MZ_RPD10R +#define SDO1_RPD11R 5, PIC32MZ_RPD11R +#define SDO1_RPD14R 5, PIC32MZ_RPD14R +#define SDO1_RPD15R 5, PIC32MZ_RPD15R +#define SDO1_RPE5R 5, PIC32MZ_RPE5R +#define SDO1_RPF0R 5, PIC32MZ_RPF0R +#define SDO1_RPF1R 5, PIC32MZ_RPF1R +#define SDO1_RPF4R 5, PIC32MZ_RPF4R +#define SDO1_RPF5R 5, PIC32MZ_RPF5R +#define SDO1_RPG0R 5, PIC32MZ_RPG0R +#define SDO1_RPG1R 5, PIC32MZ_RPG1R +#define SDO1_RPG7R 5, PIC32MZ_RPG7R +#define SDO1_RPG8R 5, PIC32MZ_RPG8R + +#define SDO2_RPA14R 6, PIC32MZ_RPA14R +#define SDO2_RPA15R 6, PIC32MZ_RPA15R +#define SDO2_RPB1R 6, PIC32MZ_RPB1R +#define SDO2_RPB3R 6, PIC32MZ_RPB3R +#define SDO2_RPB5R 6, PIC32MZ_RPB5R +#define SDO2_RPB9R 6, PIC32MZ_RPB9R +#define SDO2_RPB10R 6, PIC32MZ_RPB10R +#define SDO2_RPC1R 6, PIC32MZ_RPC1R +#define SDO2_RPC4R 6, PIC32MZ_RPC4R +#define SDO2_RPC13R 6, PIC32MZ_RPC13R +#define SDO2_RPC14R 6, PIC32MZ_RPC14R +#define SDO2_RPD2R 6, PIC32MZ_RPD2R +#define SDO2_RPD3R 6, PIC32MZ_RPD3R +#define SDO2_RPD6R 6, PIC32MZ_RPD6R +#define SDO2_RPD7R 6, PIC32MZ_RPD7R +#define SDO2_RPD10R 6, PIC32MZ_RPD10R +#define SDO2_RPD11R 6, PIC32MZ_RPD11R +#define SDO2_RPD14R 6, PIC32MZ_RPD14R +#define SDO2_RPD15R 6, PIC32MZ_RPD15R +#define SDO2_RPE5R 6, PIC32MZ_RPE5R +#define SDO2_RPF0R 6, PIC32MZ_RPF0R +#define SDO2_RPF1R 6, PIC32MZ_RPF1R +#define SDO2_RPF4R 6, PIC32MZ_RPF4R +#define SDO2_RPF5R 6, PIC32MZ_RPF5R +#define SDO2_RPG0R 6, PIC32MZ_RPG0R +#define SDO2_RPG1R 6, PIC32MZ_RPG1R +#define SDO2_RPG7R 6, PIC32MZ_RPG7R +#define SDO2_RPG8R 6, PIC32MZ_RPG8R + +#define SDO3_RPA14R 7, PIC32MZ_RPA14R +#define SDO3_RPA15R 7, PIC32MZ_RPA15R +#define SDO3_RPB1R 7, PIC32MZ_RPB1R +#define SDO3_RPB3R 7, PIC32MZ_RPB3R +#define SDO3_RPB5R 7, PIC32MZ_RPB5R +#define SDO3_RPB9R 7, PIC32MZ_RPB9R +#define SDO3_RPB10R 7, PIC32MZ_RPB10R +#define SDO3_RPC1R 7, PIC32MZ_RPC1R +#define SDO3_RPC4R 7, PIC32MZ_RPC4R +#define SDO3_RPC13R 7, PIC32MZ_RPC13R +#define SDO3_RPC14R 7, PIC32MZ_RPC14R +#define SDO3_RPD2R 7, PIC32MZ_RPD2R +#define SDO3_RPD3R 7, PIC32MZ_RPD3R +#define SDO3_RPD6R 7, PIC32MZ_RPD6R +#define SDO3_RPD7R 7, PIC32MZ_RPD7R +#define SDO3_RPD10R 7, PIC32MZ_RPD10R +#define SDO3_RPD11R 7, PIC32MZ_RPD11R +#define SDO3_RPD14R 7, PIC32MZ_RPD14R +#define SDO3_RPD15R 7, PIC32MZ_RPD15R +#define SDO3_RPE5R 7, PIC32MZ_RPE5R +#define SDO3_RPF0R 7, PIC32MZ_RPF0R +#define SDO3_RPF1R 7, PIC32MZ_RPF1R +#define SDO3_RPF4R 7, PIC32MZ_RPF4R +#define SDO3_RPF5R 7, PIC32MZ_RPF5R +#define SDO3_RPG0R 7, PIC32MZ_RPG0R +#define SDO3_RPG1R 7, PIC32MZ_RPG1R +#define SDO3_RPG7R 7, PIC32MZ_RPG7R +#define SDO3_RPG8R 7, PIC32MZ_RPG8R + +#define SDO4_RPA15R 8, PIC32MZ_RPA15R +#define SDO4_RPB1R 8, PIC32MZ_RPB1R +#define SDO4_RPB2R 8, PIC32MZ_RPB2R +#define SDO4_RPB3R 8, PIC32MZ_RPB3R +#define SDO4_RPB6R 8, PIC32MZ_RPB6R +#define SDO4_RPB14R 8, PIC32MZ_RPB14R +#define SDO4_RPC2R 8, PIC32MZ_RPC2R +#define SDO4_RPC4R 8, PIC32MZ_RPC4R +#define SDO4_RPC13R 8, PIC32MZ_RPC13R +#define SDO4_RPD0R 8, PIC32MZ_RPD0R +#define SDO4_RPD1R 8, PIC32MZ_RPD1R +#define SDO4_RPD3R 8, PIC32MZ_RPD3R +#define SDO4_RPD5R 8, PIC32MZ_RPD5R +#define SDO4_RPD7R 8, PIC32MZ_RPD7R +#define SDO4_RPD11R 8, PIC32MZ_RPD11R +#define SDO4_RPD15R 8, PIC32MZ_RPD15R +#define SDO4_RPE5R 8, PIC32MZ_RPE5R +#define SDO4_RPE8R 8, PIC32MZ_RPE8R +#define SDO4_RPF0R 8, PIC32MZ_RPF0R +#define SDO4_RPF2R 8, PIC32MZ_RPF2R +#define SDO4_RPF3R 8, PIC32MZ_RPF3R +#define SDO4_RPF5R 8, PIC32MZ_RPF5R +#define SDO4_RPF13R 8, PIC32MZ_RPF13R +#define SDO4_RPG0R 8, PIC32MZ_RPG0R +#define SDO4_RPG7R 8, PIC32MZ_RPG7R +#define SDO4_RPG9R 8, PIC32MZ_RPG9R + +#define SDO5_RPA14R 9, PIC32MZ_RPA14R +#define SDO5_RPA15R 9, PIC32MZ_RPA15R +#define SDO5_RPB1R 9, PIC32MZ_RPB1R +#define SDO5_RPB3R 9, PIC32MZ_RPB3R +#define SDO5_RPB5R 9, PIC32MZ_RPB5R +#define SDO5_RPB9R 9, PIC32MZ_RPB9R +#define SDO5_RPB10R 9, PIC32MZ_RPB10R +#define SDO5_RPC1R 9, PIC32MZ_RPC1R +#define SDO5_RPC4R 9, PIC32MZ_RPC4R +#define SDO5_RPC13R 9, PIC32MZ_RPC13R +#define SDO5_RPC14R 9, PIC32MZ_RPC14R +#define SDO5_RPD2R 9, PIC32MZ_RPD2R +#define SDO5_RPD3R 9, PIC32MZ_RPD3R +#define SDO5_RPD6R 9, PIC32MZ_RPD6R +#define SDO5_RPD7R 9, PIC32MZ_RPD7R +#define SDO5_RPD10R 9, PIC32MZ_RPD10R +#define SDO5_RPD11R 9, PIC32MZ_RPD11R +#define SDO5_RPD14R 9, PIC32MZ_RPD14R +#define SDO5_RPD15R 9, PIC32MZ_RPD15R +#define SDO5_RPE5R 9, PIC32MZ_RPE5R +#define SDO5_RPF0R 9, PIC32MZ_RPF0R +#define SDO5_RPF1R 9, PIC32MZ_RPF1R +#define SDO5_RPF4R 9, PIC32MZ_RPF4R +#define SDO5_RPF5R 9, PIC32MZ_RPF5R +#define SDO5_RPG0R 9, PIC32MZ_RPG0R +#define SDO5_RPG1R 9, PIC32MZ_RPG1R +#define SDO5_RPG7R 9, PIC32MZ_RPG7R +#define SDO5_RPG8R 9, PIC32MZ_RPG8R + +#define SDO6_RPB0R 10, PIC32MZ_RPB0R +#define SDO6_RPB2R 10, PIC32MZ_RPB2R +#define SDO6_RPB6R 10, PIC32MZ_RPB6R +#define SDO6_RPB7R 10, PIC32MZ_RPB7R +#define SDO6_RPB8R 10, PIC32MZ_RPB8R +#define SDO6_RPB14R 10, PIC32MZ_RPB14R +#define SDO6_RPB15R 10, PIC32MZ_RPB15R +#define SDO6_RPC2R 10, PIC32MZ_RPC2R +#define SDO6_RPC3R 10, PIC32MZ_RPC3R +#define SDO6_RPD0R 10, PIC32MZ_RPD0R +#define SDO6_RPD1R 10, PIC32MZ_RPD1R +#define SDO6_RPD4R 10, PIC32MZ_RPD4R +#define SDO6_RPD5R 10, PIC32MZ_RPD5R +#define SDO6_RPD9R 10, PIC32MZ_RPD9R +#define SDO6_RPD12R 10, PIC32MZ_RPD12R +#define SDO6_RPE3R 10, PIC32MZ_RPE3R +#define SDO6_RPE8R 10, PIC32MZ_RPE8R +#define SDO6_RPE9R 10, PIC32MZ_RPE9R +#define SDO6_RPF2R 10, PIC32MZ_RPF2R +#define SDO6_RPF3R 10, PIC32MZ_RPF3R +#define SDO6_RPF8R 10, PIC32MZ_RPF8R +#define SDO6_RPF12R 10, PIC32MZ_RPF12R +#define SDO6_RPF13R 10, PIC32MZ_RPF13R +#define SDO6_RPG6R 10, PIC32MZ_RPG6R +#define SDO6_RPG9R 10, PIC32MZ_RPG9R + +#define SS1_RPB0R 5, PIC32MZ_RPB0R +#define SS1_RPB7R 5, PIC32MZ_RPB7R +#define SS1_RPB8R 5, PIC32MZ_RPB8R +#define SS1_RPB15R 5, PIC32MZ_RPB15R +#define SS1_RPC3R 5, PIC32MZ_RPC3R +#define SS1_RPD4R 5, PIC32MZ_RPD4R +#define SS1_RPD9R 5, PIC32MZ_RPD9R +#define SS1_RPD12R 5, PIC32MZ_RPD12R +#define SS1_RPE3R 5, PIC32MZ_RPE3R +#define SS1_RPE9R 5, PIC32MZ_RPE9R +#define SS1_RPF8R 5, PIC32MZ_RPF8R +#define SS1_RPF12R 5, PIC32MZ_RPF12R +#define SS1_RPG6R 5, PIC32MZ_RPG6R + +#define SS2_RPB2R 6, PIC32MZ_RPB2R +#define SS2_RPB6R 6, PIC32MZ_RPB6R +#define SS2_RPB14R 6, PIC32MZ_RPB14R +#define SS2_RPC2R 6, PIC32MZ_RPC2R +#define SS2_RPD0R 6, PIC32MZ_RPD0R +#define SS2_RPD1R 6, PIC32MZ_RPD1R +#define SS2_RPD5R 6, PIC32MZ_RPD5R +#define SS2_RPE8R 6, PIC32MZ_RPE8R +#define SS2_RPF2R 6, PIC32MZ_RPF2R +#define SS2_RPF3R 6, PIC32MZ_RPF3R +#define SS2_RPF13R 6, PIC32MZ_RPF13R +#define SS2_RPG9R 6, PIC32MZ_RPG9R + +#define SS3_RPB0R 7, PIC32MZ_RPB0R +#define SS3_RPB7R 7, PIC32MZ_RPB7R +#define SS3_RPB8R 7, PIC32MZ_RPB8R +#define SS3_RPB15R 7, PIC32MZ_RPB15R +#define SS3_RPC3R 7, PIC32MZ_RPC3R +#define SS3_RPD4R 7, PIC32MZ_RPD4R +#define SS3_RPD9R 7, PIC32MZ_RPD9R +#define SS3_RPD12R 7, PIC32MZ_RPD12R +#define SS3_RPE3R 7, PIC32MZ_RPE3R +#define SS3_RPE9R 7, PIC32MZ_RPE9R +#define SS3_RPF8R 7, PIC32MZ_RPF8R +#define SS3_RPF12R 7, PIC32MZ_RPF12R +#define SS3_RPG6R 7, PIC32MZ_RPG6R + +#define SS4_RPB0R 8, PIC32MZ_RPB0R +#define SS4_RPB7R 8, PIC32MZ_RPB7R +#define SS4_RPB8R 8, PIC32MZ_RPB8R +#define SS4_RPB15R 8, PIC32MZ_RPB15R +#define SS4_RPC3R 8, PIC32MZ_RPC3R +#define SS4_RPD4R 8, PIC32MZ_RPD4R +#define SS4_RPD9R 8, PIC32MZ_RPD9R +#define SS4_RPD12R 8, PIC32MZ_RPD12R +#define SS4_RPE3R 8, PIC32MZ_RPE3R +#define SS4_RPE9R 8, PIC32MZ_RPE9R +#define SS4_RPF8R 8, PIC32MZ_RPF8R +#define SS4_RPF12R 8, PIC32MZ_RPF12R +#define SS4_RPG6R 8, PIC32MZ_RPG6R + +#define SS5_RPB0R 9, PIC32MZ_RPB0R +#define SS5_RPB7R 9, PIC32MZ_RPB7R +#define SS5_RPB8R 9, PIC32MZ_RPB8R +#define SS5_RPB15R 9, PIC32MZ_RPB15R +#define SS5_RPC3R 9, PIC32MZ_RPC3R +#define SS5_RPD4R 9, PIC32MZ_RPD4R +#define SS5_RPD9R 9, PIC32MZ_RPD9R +#define SS5_RPD12R 9, PIC32MZ_RPD12R +#define SS5_RPE3R 9, PIC32MZ_RPE3R +#define SS5_RPE9R 9, PIC32MZ_RPE9R +#define SS5_RPF8R 9, PIC32MZ_RPF8R +#define SS5_RPF12R 9, PIC32MZ_RPF12R +#define SS5_RPG6R 9, PIC32MZ_RPG6R + +#define SS6_RPA14R 10, PIC32MZ_RPA14R +#define SS6_RPB5R 10, PIC32MZ_RPB5R +#define SS6_RPB9R 10, PIC32MZ_RPB9R +#define SS6_RPB10R 10, PIC32MZ_RPB10R +#define SS6_RPC1R 10, PIC32MZ_RPC1R +#define SS6_RPC14R 10, PIC32MZ_RPC14R +#define SS6_RPD2R 10, PIC32MZ_RPD2R +#define SS6_RPD6R 10, PIC32MZ_RPD6R +#define SS6_RPD10R 10, PIC32MZ_RPD10R +#define SS6_RPD14R 10, PIC32MZ_RPD14R +#define SS6_RPF1R 10, PIC32MZ_RPF1R +#define SS6_RPF4R 10, PIC32MZ_RPF4R +#define SS6_RPG1R 10, PIC32MZ_RPG1R +#define SS6_RPG8R 10, PIC32MZ_RPG8R + +#define U1RTS_RPB2R 1, PIC32MZ_RPB2R +#define U1RTS_RPB6R 1, PIC32MZ_RPB6R +#define U1RTS_RPB14R 1, PIC32MZ_RPB14R +#define U1RTS_RPC2R 1, PIC32MZ_RPC2R +#define U1RTS_RPD0R 1, PIC32MZ_RPD0R +#define U1RTS_RPD1R 1, PIC32MZ_RPD1R +#define U1RTS_RPD5R 1, PIC32MZ_RPD5R +#define U1RTS_RPE8R 1, PIC32MZ_RPE8R +#define U1RTS_RPF2R 1, PIC32MZ_RPF2R +#define U1RTS_RPF3R 1, PIC32MZ_RPF3R +#define U1RTS_RPF13R 1, PIC32MZ_RPF13R +#define U1RTS_RPG9R 1, PIC32MZ_RPG9R + +#define U1TX_RPA15R 1, PIC32MZ_RPA15R +#define U1TX_RPB1R 1, PIC32MZ_RPB1R +#define U1TX_RPB3R 1, PIC32MZ_RPB3R +#define U1TX_RPC4R 1, PIC32MZ_RPC4R +#define U1TX_RPC13R 1, PIC32MZ_RPC13R +#define U1TX_RPD3R 1, PIC32MZ_RPD3R +#define U1TX_RPD7R 1, PIC32MZ_RPD7R +#define U1TX_RPD11R 1, PIC32MZ_RPD11R +#define U1TX_RPD15R 1, PIC32MZ_RPD15R +#define U1TX_RPE5R 1, PIC32MZ_RPE5R +#define U1TX_RPF0R 1, PIC32MZ_RPF0R +#define U1TX_RPF5R 1, PIC32MZ_RPF5R +#define U1TX_RPG0R 1, PIC32MZ_RPG0R +#define U1TX_RPG7R 1, PIC32MZ_RPG7R + +#define U2RTS_RPA15R 2, PIC32MZ_RPA15R +#define U2RTS_RPB1R 2, PIC32MZ_RPB1R +#define U2RTS_RPB3R 2, PIC32MZ_RPB3R +#define U2RTS_RPC4R 2, PIC32MZ_RPC4R +#define U2RTS_RPC13R 2, PIC32MZ_RPC13R +#define U2RTS_RPD3R 2, PIC32MZ_RPD3R +#define U2RTS_RPD7R 2, PIC32MZ_RPD7R +#define U2RTS_RPD11R 2, PIC32MZ_RPD11R +#define U2RTS_RPD15R 2, PIC32MZ_RPD15R +#define U2RTS_RPE5R 2, PIC32MZ_RPE5R +#define U2RTS_RPF0R 2, PIC32MZ_RPF0R +#define U2RTS_RPF5R 2, PIC32MZ_RPF5R +#define U2RTS_RPG0R 2, PIC32MZ_RPG0R +#define U2RTS_RPG7R 2, PIC32MZ_RPG7R + +#define U2TX_RPB2R 2, PIC32MZ_RPB2R +#define U2TX_RPB6R 2, PIC32MZ_RPB6R +#define U2TX_RPB14R 2, PIC32MZ_RPB14R +#define U2TX_RPC2R 2, PIC32MZ_RPC2R +#define U2TX_RPD0R 2, PIC32MZ_RPD0R +#define U2TX_RPD1R 2, PIC32MZ_RPD1R +#define U2TX_RPD5R 2, PIC32MZ_RPD5R +#define U2TX_RPE8R 2, PIC32MZ_RPE8R +#define U2TX_RPF2R 2, PIC32MZ_RPF2R +#define U2TX_RPF3R 2, PIC32MZ_RPF3R +#define U2TX_RPF13R 2, PIC32MZ_RPF13R +#define U2TX_RPG9R 2, PIC32MZ_RPG9R + +#define U3RTS_RPB0R 1, PIC32MZ_RPB0R +#define U3RTS_RPB7R 1, PIC32MZ_RPB7R +#define U3RTS_RPB8R 1, PIC32MZ_RPB8R +#define U3RTS_RPB15R 1, PIC32MZ_RPB15R +#define U3RTS_RPC3R 1, PIC32MZ_RPC3R +#define U3RTS_RPD4R 1, PIC32MZ_RPD4R +#define U3RTS_RPD9R 1, PIC32MZ_RPD9R +#define U3RTS_RPD12R 1, PIC32MZ_RPD12R +#define U3RTS_RPE3R 1, PIC32MZ_RPE3R +#define U3RTS_RPE9R 1, PIC32MZ_RPE9R +#define U3RTS_RPF8R 1, PIC32MZ_RPF8R +#define U3RTS_RPF12R 1, PIC32MZ_RPF12R +#define U3RTS_RPG6R 1, PIC32MZ_RPG6R + +#define U3TX_RPA14R 1, PIC32MZ_RPA14R +#define U3TX_RPB5R 1, PIC32MZ_RPB5R +#define U3TX_RPB9R 1, PIC32MZ_RPB9R +#define U3TX_RPB10R 1, PIC32MZ_RPB10R +#define U3TX_RPC1R 1, PIC32MZ_RPC1R +#define U3TX_RPC14R 1, PIC32MZ_RPC14R +#define U3TX_RPD2R 1, PIC32MZ_RPD2R +#define U3TX_RPD6R 1, PIC32MZ_RPD6R +#define U3TX_RPD10R 1, PIC32MZ_RPD10R +#define U3TX_RPD14R 1, PIC32MZ_RPD14R +#define U3TX_RPF1R 1, PIC32MZ_RPF1R +#define U3TX_RPF4R 1, PIC32MZ_RPF4R +#define U3TX_RPG1R 1, PIC32MZ_RPG1R +#define U3TX_RPG8R 1, PIC32MZ_RPG8R + +#define U4RTS_RPA14R 2, PIC32MZ_RPA14R +#define U4RTS_RPB5R 2, PIC32MZ_RPB5R +#define U4RTS_RPB9R 2, PIC32MZ_RPB9R +#define U4RTS_RPB10R 2, PIC32MZ_RPB10R +#define U4RTS_RPC1R 2, PIC32MZ_RPC1R +#define U4RTS_RPC14R 2, PIC32MZ_RPC14R +#define U4RTS_RPD2R 2, PIC32MZ_RPD2R +#define U4RTS_RPD6R 2, PIC32MZ_RPD6R +#define U4RTS_RPD10R 2, PIC32MZ_RPD10R +#define U4RTS_RPD14R 2, PIC32MZ_RPD14R +#define U4RTS_RPF1R 2, PIC32MZ_RPF1R +#define U4RTS_RPF4R 2, PIC32MZ_RPF4R +#define U4RTS_RPG1R 2, PIC32MZ_RPG1R +#define U4RTS_RPG8R 2, PIC32MZ_RPG8R + +#define U4TX_RPB0R 2, PIC32MZ_RPB0R +#define U4TX_RPB7R 2, PIC32MZ_RPB7R +#define U4TX_RPB8R 2, PIC32MZ_RPB8R +#define U4TX_RPB15R 2, PIC32MZ_RPB15R +#define U4TX_RPC3R 2, PIC32MZ_RPC3R +#define U4TX_RPD4R 2, PIC32MZ_RPD4R +#define U4TX_RPD9R 2, PIC32MZ_RPD9R +#define U4TX_RPD12R 2, PIC32MZ_RPD12R +#define U4TX_RPE3R 2, PIC32MZ_RPE3R +#define U4TX_RPE9R 2, PIC32MZ_RPE9R +#define U4TX_RPF8R 2, PIC32MZ_RPF8R +#define U4TX_RPF12R 2, PIC32MZ_RPF12R +#define U4TX_RPG6R 2, PIC32MZ_RPG6R + +#define U5RTS_RPB2R 3, PIC32MZ_RPB2R +#define U5RTS_RPB6R 3, PIC32MZ_RPB6R +#define U5RTS_RPB14R 3, PIC32MZ_RPB14R +#define U5RTS_RPC2R 3, PIC32MZ_RPC2R +#define U5RTS_RPD0R 3, PIC32MZ_RPD0R +#define U5RTS_RPD1R 3, PIC32MZ_RPD1R +#define U5RTS_RPD5R 3, PIC32MZ_RPD5R +#define U5RTS_RPE8R 3, PIC32MZ_RPE8R +#define U5RTS_RPF2R 3, PIC32MZ_RPF2R +#define U5RTS_RPF3R 3, PIC32MZ_RPF3R +#define U5RTS_RPF13R 3, PIC32MZ_RPF13R +#define U5RTS_RPG9R 3, PIC32MZ_RPG9R + +#define U5TX_RPA15R 3, PIC32MZ_RPA15R +#define U5TX_RPB1R 3, PIC32MZ_RPB1R +#define U5TX_RPB3R 3, PIC32MZ_RPB3R +#define U5TX_RPC4R 3, PIC32MZ_RPC4R +#define U5TX_RPC13R 3, PIC32MZ_RPC13R +#define U5TX_RPD3R 3, PIC32MZ_RPD3R +#define U5TX_RPD7R 3, PIC32MZ_RPD7R +#define U5TX_RPD11R 3, PIC32MZ_RPD11R +#define U5TX_RPD15R 3, PIC32MZ_RPD15R +#define U5TX_RPE5R 3, PIC32MZ_RPE5R +#define U5TX_RPF0R 3, PIC32MZ_RPF0R +#define U5TX_RPF5R 3, PIC32MZ_RPF5R +#define U5TX_RPG0R 3, PIC32MZ_RPG0R +#define U5TX_RPG7R 3, PIC32MZ_RPG7R + +#define U6RTS_RPA15R 4, PIC32MZ_RPA15R +#define U6RTS_RPB1R 4, PIC32MZ_RPB1R +#define U6RTS_RPB3R 4, PIC32MZ_RPB3R +#define U6RTS_RPC4R 4, PIC32MZ_RPC4R +#define U6RTS_RPC13R 4, PIC32MZ_RPC13R +#define U6RTS_RPD3R 4, PIC32MZ_RPD3R +#define U6RTS_RPD7R 4, PIC32MZ_RPD7R +#define U6RTS_RPD11R 4, PIC32MZ_RPD11R +#define U6RTS_RPD15R 4, PIC32MZ_RPD15R +#define U6RTS_RPE5R 4, PIC32MZ_RPE5R +#define U6RTS_RPF0R 4, PIC32MZ_RPF0R +#define U6RTS_RPF5R 4, PIC32MZ_RPF5R +#define U6RTS_RPG0R 4, PIC32MZ_RPG0R +#define U6RTS_RPG7R 4, PIC32MZ_RPG7R + +#define U6TX_RPB0R 4, PIC32MZ_RPB0R +#define U6TX_RPB2R 4, PIC32MZ_RPB2R +#define U6TX_RPB6R 4, PIC32MZ_RPB6R +#define U6TX_RPB7R 4, PIC32MZ_RPB7R +#define U6TX_RPB8R 4, PIC32MZ_RPB8R +#define U6TX_RPB14R 4, PIC32MZ_RPB14R +#define U6TX_RPB15R 4, PIC32MZ_RPB15R +#define U6TX_RPC2R 4, PIC32MZ_RPC2R +#define U6TX_RPC3R 4, PIC32MZ_RPC3R +#define U6TX_RPD0R 4, PIC32MZ_RPD0R +#define U6TX_RPD1R 4, PIC32MZ_RPD1R +#define U6TX_RPD4R 4, PIC32MZ_RPD4R +#define U6TX_RPD5R 4, PIC32MZ_RPD5R +#define U6TX_RPD9R 4, PIC32MZ_RPD9R +#define U6TX_RPD12R 4, PIC32MZ_RPD12R +#define U6TX_RPE3R 4, PIC32MZ_RPE3R +#define U6TX_RPE8R 4, PIC32MZ_RPE8R +#define U6TX_RPE9R 4, PIC32MZ_RPE9R +#define U6TX_RPF2R 4, PIC32MZ_RPF2R +#define U6TX_RPF3R 4, PIC32MZ_RPF3R +#define U6TX_RPF8R 4, PIC32MZ_RPF8R +#define U6TX_RPF12R 4, PIC32MZ_RPF12R +#define U6TX_RPF13R 4, PIC32MZ_RPF13R +#define U6TX_RPG6R 4, PIC32MZ_RPG6R +#define U6TX_RPG9R 4, PIC32MZ_RPG9R #endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_PPS_H */ |