PIC32MZ: Add memorymap and devcfg header files

6 files changed, 501 insertions, 2 deletions

diff --git a/nuttx/arch/mips/include/pic32mz/irq.h b/nuttx/arch/mips/include/pic32mz/irq.h
index 83de0bf52..9872a4ea7 100644
--- a/nuttx/arch/mips/include/pic32mz/irq.h
+++ b/nuttx/arch/mips/include/pic32mz/irq.h
@@ -47,7 +47,7 @@
 #include <nuttx/config.h>
 #include <arch/pic32mz/chip.h>
 
-#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2)
+#if defined(CHIP_PIC32MZEC)
 #  include <arch/pic32mz/irq_pic32mzxxxec.h>
 #else
 #  error "Unknown PIC32MZ family
diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mz-features.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-features.h
new file mode 100644
index 000000000..8e395a72e
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-features.h
@@ -0,0 +1,51 @@
+/************************************************************************************
+ * arch/mips/src/pic32mz/chip/pic32mz-features.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H
+#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2)
+#  include <chip/pic32mzec-features.h>
+#else
+#  error "Unknown PIC32MZ family
+#endif
+
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H */
diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h
new file mode 100644
index 000000000..ada326b09
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h
@@ -0,0 +1,51 @@
+/************************************************************************************
+ * arch/mips/src/pic32mz/chip/pic32mz-memorymap.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H
+#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2)
+#  include <chip/pic32mzec-memorymap.h>
+#else
+#  error "Unknown PIC32MZ family
+#endif
+
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H */
diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-features.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-features.h
new file mode 100644
index 000000000..637a2835d
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-features.h
@@ -0,0 +1,255 @@
+/************************************************************************************
+ * arch/mips/src/pic32mz/chip/pic32mzec-features.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H
+#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+mips32-memorymap.h:#define KSEG1_BASE 
+
+#define PIC32MZ_LOWERBOOT_K1BASE  (0xbfc00000)
+#define  PIC32MZ_BOOTCFG_K1BASE    (0xbfc0ff40)
+#define PIC32MZ_UPPERBOOT_K1BASE  (0xbfc20000)
+#define PIC32MZ_BOOT1_K1BASE      (0xbfc40000)
+#define PIC32MZ_SEQCFG1_K1BASE    (0xbfc4ff40)
+#define PIC32MZ_ADCCALIB_K1BASE   (0xbfc54000)
+#define PIC32MZ_DEVSN_K1BASE      (0xbfc54020)
+#define PIC32MZ_BOOT2_K1BASE      (0xbfc60000)
+#define PIC32MZ_SEQCFG2_K1BASE    (0xbfc6ff40)
+
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Register/Flash Offsets ***********************************************************/
+
+/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
+
+#define PIC32MZ_CFGCON_OFFSET    0x0000 /* Configuration control register */
+#define PIC32MZ_DEVID_OFFSET     0x0020 /* Device ID and revision register */
+#define PIC32MZ_SYSKEY_OFFSET    0x0030 /* System key register */
+#define PIC32MZ_CFGEBIA_OFFSET   0x00c0 /* External bus interface address pin configuration register */
+#define PIC32MZ_CFGEBIC_OFFSET   0x00d0 /* External bus interface address pin control register */
+#define PIC32MZ_CFGPG_OFFSET     0x00e0 /* Permission group configuration register */
+
+/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
+
+#define PIC32MZ_ADEVCFG3_OFFSET  0x0000 /* Alternate device configuration word 3 */
+#define PIC32MZ_ADEVCFG2_OFFSET  0x0004 /* Alternate device configuration word 2 */
+#define PIC32MZ_ADEVCFG1_OFFSET  0x0008 /* Alternate device configuration word 1 */
+#define PIC32MZ_ADEVCFG0_OFFSET  0x000c /* Alternate device configuration word 0 */
+#define PIC32MZ_ADEVCP3_OFFSET   0x0010 /* Alternate device code protect word 3 */
+#define PIC32MZ_ADEVCP2_OFFSET   0x0014 /* Alternate device code protect word 2 */
+#define PIC32MZ_ADEVCP1_OFFSET   0x0018 /* Alternate device code protect word 1 */
+#define PIC32MZ_ADEVCP0_OFFSET   0x001c /* Alternate device code protect word 0 */
+#define PIC32MZ_ADEVSIGN3_OFFSET 0x0020 /* Alternate evice signature word 3 */
+#define PIC32MZ_ADEVSIGN2_OFFSET 0x0024 /* Alternate evice signature word 2 */
+#define PIC32MZ_ADEVSIGN1_OFFSET 0x0028 /* Alternate evice signature word 1 */
+#define PIC32MZ_ADEVSIGN0_OFFSET 0x002c /* Alternate evice signature word 0 */
+
+/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
+
+#define PIC32MZ_DEVCFG3_OFFSET   0x0080 /* Device configuration word 3 */
+#define PIC32MZ_DEVCFG2_OFFSET   0x0084 /* Device configuration word 2 */
+#define PIC32MZ_DEVCFG1_OFFSET   0x0088 /* Device configuration word 1 */
+#define PIC32MZ_DEVCFG0_OFFSET   0x008c /* Device configuration word 0 */
+#define PIC32MZ_DEVCP3_OFFSET    0x0090 /* Device code protect word 3 */
+#define PIC32MZ_DEVCP2_OFFSET    0x0094 /* Device code protect word 2 */
+#define PIC32MZ_DEVCP1_OFFSET    0x0098 /* Device code protect word 1 */
+#define PIC32MZ_DEVCP0_OFFSET    0x009c /* Device code protect word 0 */
+#define PIC32MZ_DEVSIGN3_OFFSET  0x00a0 /* Device signature word 3 */
+#define PIC32MZ_DEVSIGN2_OFFSET  0x00a4 /* Device signature word 2 */
+#define PIC32MZ_DEVSIGN1_OFFSET  0x00a8 /* Device signature word 1 */
+#define PIC32MZ_DEVSIGN0_OFFSET  0x00ac /* Device signature word 0 */
+
+/* Device ADC Calibration (Boot Flash PIC32MZ_ADCCALIB_K1BASE) */
+
+#define PIC32MZ_DEVADC1_OFFSET   0x0000 /* ADC1 Calibration */
+#define PIC32MZ_DEVADC2_OFFSET   0x0004 /* ADC2 Calibration */
+#define PIC32MZ_DEVADC3_OFFSET   0x0008 /* ADC3 Calibration */
+#define PIC32MZ_DEVADC4_OFFSET   0x000c /* ADC4 Calibration */
+#define PIC32MZ_DEVADC5_OFFSET   0x0010 /* ADC5 Calibration */
+
+/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */
+
+#define PIC32MZ_DEVSN0_OFFSET    0x0000 /* Device serial number 0 */
+#define PIC32MZ_DEVSN1_OFFSET    0x0004 /* Device serial number 1 */
+
+/* Register/Flash Addresses *********************************************************/
+
+/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
+
+#define PIC32MZ_CFGCON           (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGCON_OFFSET)
+#define PIC32MZ_DEVID            (PIC32MZ_CONFIG_K1BASE+PIC32MZ_DEVID_OFFSET)
+#define PIC32MZ_SYSKEY           (PIC32MZ_CONFIG_K1BASE+PIC32MZ_SYSKEY_OFFSET)
+#define PIC32MZ_CFGEBIA          (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGEBIA_OFFSET)
+#define PIC32MZ_CFGEBIC          (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGEBIC_OFFSET)
+#define PIC32MZ_CFGPG            (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGPG_OFFSET)
+
+/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
+
+#define PIC32MZ_ADEVCFG3         (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG3_OFFSET)
+#define PIC32MZ_ADEVCFG2         (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG2_OFFSET)
+#define PIC32MZ_ADEVCFG1         (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG1_OFFSET)
+#define PIC32MZ_ADEVCFG0         (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG0_OFFSET)
+#define PIC32MZ_ADEVCP3          (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP3_OFFSET)
+#define PIC32MZ_ADEVCP2          (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP2_OFFSET)
+#define PIC32MZ_ADEVCP1          (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP1_OFFSET)
+#define PIC32MZ_ADEVCP0          (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP0_OFFSET)
+#define PIC32MZ_ADEVSIGN3        (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN3_OFFSET)
+#define PIC32MZ_ADEVSIGN2        (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN2_OFFSET)
+#define PIC32MZ_ADEVSIGN1        (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN1_OFFSET)
+#define PIC32MZ_ADEVSIGN0        (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN0_OFFSET)
+
+/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
+
+#define PIC32MZ_DEVCFG3          (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG3_OFFSET)
+#define PIC32MZ_DEVCFG2          (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG2_OFFSET)
+#define PIC32MZ_DEVCFG1          (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG1_OFFSET)
+#define PIC32MZ_DEVCFG0          (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG0_OFFSET)
+#define PIC32MZ_DEVCP3           (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP3_OFFSET)
+#define PIC32MZ_DEVCP2           (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP2_OFFSET)
+#define PIC32MZ_DEVCP1           (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP1_OFFSET)
+#define PIC32MZ_DEVCP0           (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP0_OFFSET)
+#define PIC32MZ_DEVSIGN3         (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN3_OFFSET)
+#define PIC32MZ_DEVSIGN2         (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN2_OFFSET)
+#define PIC32MZ_DEVSIGN1         (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN1_OFFSET)
+#define PIC32MZ_DEVSIGN0         (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN0_OFFSET)
+
+/* Device ADC Calibration (Boot Flash PIC32MZ_ADCCALIB_K1BASE) */
+
+#define PIC32MZ_DEVADC1          (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC1_OFFSET)
+#define PIC32MZ_DEVADC2          (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC2_OFFSET)
+#define PIC32MZ_DEVADC3          (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC3_OFFSET)
+#define PIC32MZ_DEVADC4          (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC4_OFFSET)
+#define PIC32MZ_DEVADC5          (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC5_OFFSET)
+
+/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASEPIC32MZ_DEVSN_K1BASE) */
+
+#define PIC32MZ_DEVSN0           (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVSN0_OFFSET)
+#define PIC32MZ_DEVSN1           (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVSN1_OFFSET)
+
+/* Register/Flash Bit Field Definitions *********************************************/
+
+/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
+/* Configuration control register */
+#define CFGCON_
+/* Device ID and revision register */
+#define DEVID_
+/* System key register */
+#define SYSKEY_
+/* External bus interface address pin configuration register */
+#define CFGEBIA_
+/* External bus interface address pin control register */
+#define CFGEBIC_
+/* Permission group configuration register */
+#define CFGPG_
+
+/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
+/* Alternate device configuration word 3 */
+#define ADEVCFG3_
+/* Alternate device configuration word 2 */
+#define ADEVCFG2_
+/* Alternate device configuration word 1 */
+#define ADEVCFG1_
+/* Alternate device configuration word 0 */
+#define ADEVCFG0_
+/* Alternate device code protect word 3 */
+#define ADEVCP3_
+/* Alternate device code protect word 2 */
+#define ADEVCP2_
+/* Alternate device code protect word 1 */
+#define ADEVCP1_
+/* Alternate device code protect word 0 */
+#define ADEVCP0_
+/* Alternate evice signature word 3 */
+#define ADEVSIGN3_
+/* Alternate evice signature word 2 */
+#define ADEVSIGN2_
+/* Alternate evice signature word 1 */
+#define ADEVSIGN1_
+/* Alternate evice signature word 0 */
+#define ADEVSIGN0_
+
+/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
+/* Device configuration word 3 */
+#define DEVCFG3_
+/* Device configuration word 2 */
+#define DEVCFG2_
+/* Device configuration word 1 */
+#define DEVCFG1_
+/* Device configuration word 0 */
+#define DEVCFG0_
+/* Device code protect word 3 */
+#define DEVCP3_
+/* Device code protect word 2 */
+#define DEVCP2_
+/* Device code protect word 1 */
+#define DEVCP1_
+/* Device code protect word 0 */
+#define DEVCP0_
+/* Device signature word 3 */
+#define DEVSIGN3_
+/* Device signature word 2 */
+#define DEVSIGN2_
+/* Device signature word 1 */
+#define DEVSIGN1_
+/* Device signature word 0 */
+#define DEVSIGN0_
+
+/* Device ADC Calibration (Boot Flash PIC32MZ_ADCCALIB_K1BASE) */
+/* ADC1 Calibration */
+#define DEVADC1_
+/* ADC2 Calibration */
+#define DEVADC2_
+/* ADC3 Calibration */
+#define DEVADC3_
+/* ADC4 Calibration */
+#define DEVADC4_
+/* ADC5 Calibration */
+#define DEVADC5_
+
+/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */
+/* Device serial number 0 */
+#define DEVSN0_OFFSET    0x0000 /* Device serial number 0 */
+/* Device serial number 1 */
+#define DEVSN1_OFFSET    0x0004 /* Device serial number 1 */
+
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H */
diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h
new file mode 100644
index 000000000..cb4cbd286
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h
@@ -0,0 +1,142 @@
+/************************************************************************************
+ * arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H
+#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "mips32-memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Physical Memory Map **************************************************************/
+/* Memory Regions */
+
+#define PIC32MZ_DATAMEM_PBASE     0x00000000 /* Size depends on CHIP_DATAMEM_KB */
+#define PIC32MZ_PROGFLASH_PBASE   0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */
+#define PIC32MZ_SFR_PBASE         0x1f800000 /* Special function registers */
+#define PIC32MZ_BOOTFLASH_PBASE   0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */
+#define PIC32MZ_EBIMEM_PBASE      0x20000000 /* External memory via EBI */
+#define PIC32MZ_SQIMEM_PBASE      0x30000000 /* External memory via SQI */
+
+/* Boot FLASH */
+
+#define PIC32MZ_LOWERBOOT_PBASE   0x1fc00000 /* Lower boot alias */
+#define PIC32MZ_CONFIG_PBASE      0x1fc0ff40 /* Configuration space */
+#define PIC32MZ_UPPERBOOT_PBASE   0x1fc20000 /* Upper boot alias */
+#define PIC32MZ_BOOT1_PBASE       0x1fc40000 /* Boot flash 1 */
+#define PIC32MZ_SEQCFG1_PBASE     0x1fc4ff40 /* Sequence/configuration space 1 */
+#define PIC32MZ_ADCCALIB_PBASE    0x1fc54000 /* ADC calibration space */
+#define PIC32MZ_DEVSN_PBASE       0x1fc54020 /* Device serial number */
+#define PIC32MZ_BOOT2_PBASE       0x1fc60000 /* Boot flash 2 */
+#define PIC32MZ_SEQCFG2_PBASE     0x1fc6ff40 /* Sequence/configuration space 2 */
+
+/* Virtual Memory Map ***************************************************************/
+
+#define PIC32MZ_DATAMEM_K0BASE      (KSEG0_BASE + PIC32MZ_DATAMEM_PBASE)
+#define PIC32MZ_PROGFLASH_K0BASE    (KSEG0_BASE + PIC32MZ_PROGFLASH_PBASE)
+#define PIC32MZ_SFR_K0BASE          (KSEG0_BASE + PIC32MZ_SFR_PBASE)
+#define PIC32MZ_BOOTFLASH_K0BASE    (KSEG0_BASE + PIC32MZ_BOOTFLASH_PBASE)
+#define PIC32MZ_EBIMEM_K0BASE       (KSEG0_BASE + PIC32MZ_EBIMEM_PBASE)
+#define PIC32MZ_SQIMEM_K0BASE       (KSEG0_BASE + PIC32MZ_SQIMEM_PBASE)
+
+#define PIC32MZ_DATAMEM_K1BASE      (KSEG1_BASE + PIC32MZ_DATAMEM_PBASE)
+#define PIC32MZ_PROGFLASH_K1BASE    (KSEG1_BASE + PIC32MZ_PROGFLASH_PBASE)
+#define PIC32MZ_SFR_K1BASE          (KSEG1_BASE + PIC32MZ_SFR_PBASE)
+#define PIC32MZ_BOOTFLASH_K1BASE    (KSEG1_BASE + PIC32MZ_BOOTFLASH_PBASE)
+#define PIC32MZ_EBIMEM_K1BASE       (KSEG1_BASE + PIC32MZ_EBIMEM_PBASE)
+#define PIC32MZ_SQIMEM_K1BASE       (KSEG1_BASE + PIC32MZ_SQIMEM_PBASE)
+
+/* Boot FLASH */
+
+#define PIC32MZ_LOWERBOOT_K0BASE    (KSEG0_BASE + PIC32MZ_LOWERBOOT_PBASE)
+#define PIC32MZ_CONFIG_K0BASE       (KSEG0_BASE + PIC32MZ_CONFIG_PBASE)
+#define PIC32MZ_UPPERBOOT_K0BASE    (KSEG0_BASE + PIC32MZ_UPPERBOOT_PBASE)
+#define PIC32MZ_BOOT1_K0BASE        (KSEG0_BASE + PIC32MZ_BOOT1_PBASE)
+#define PIC32MZ_SEQCFG1_K0BASE      (KSEG0_BASE + PIC32MZ_SEQCFG1_PBASE)
+#define PIC32MZ_ADCCALIB_K0BASE     (KSEG0_BASE + PIC32MZ_ADCCALIB_PBASE)
+#define PIC32MZ_DEVSN_K0BASE        (KSEG0_BASE + PIC32MZ_DEVSN_PBASE)
+#define PIC32MZ_BOOT2_K0BASE        (KSEG0_BASE + PIC32MZ_BOOT2_PBASE)
+#define PIC32MZ_SEQCFG2_K0BASE      (KSEG0_BASE + PIC32MZ_SEQCFG2_PBASE)
+
+#define PIC32MZ_LOWERBOOT_K1BASE    (KSEG1_BASE + PIC32MZ_LOWERBOOT_PBASE)
+#define PIC32MZ_CONFIG_K1BASE       (KSEG1_BASE + PIC32MZ_CONFIG_PBASE)
+#define PIC32MZ_UPPERBOOT_K1BASE    (KSEG1_BASE + PIC32MZ_UPPERBOOT_PBASE)
+#define PIC32MZ_BOOT1_K1BASE        (KSEG1_BASE + PIC32MZ_BOOT1_PBASE)
+#define PIC32MZ_SEQCFG1_K1BASE      (KSEG1_BASE + PIC32MZ_SEQCFG1_PBASE)
+#define PIC32MZ_ADCCALIB_K1BASE     (KSEG1_BASE + PIC32MZ_ADCCALIB_PBASE)
+#define PIC32MZ_DEVSN_K1BASE        (KSEG1_BASE + PIC32MZ_DEVSN_PBASE)
+#define PIC32MZ_BOOT2_K1BASE        (KSEG1_BASE + PIC32MZ_BOOT2_PBASE)
+#define PIC32MZ_SEQCFG2_K1BASE      (KSEG1_BASE + PIC32MZ_SEQCFG2_PBASE)
+
+/* Register Base Addresses **********************************************************/
+
+#define PIC32MZ_CONFIG_K1BASE       (PIC32MZ_SFR_K1BASE + 0x00000000) /* Configuration */
+#define PIC32MZ_FLASHC_K1BASE       (PIC32MZ_SFR_K1BASE + 0x00000600) /* Flash Controller */
+#define PIC32MZ_WDT_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00000800) /* Watchdog Timer */
+#define PIC32MZ_DMT_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00000a00) /* Deadman Timer */
+#define PIC32MZ_RTCC_K1BASE         (PIC32MZ_SFR_K1BASE + 0x00000c00) /* RTCC */
+#define PIC32MZ_CVREF_K1BASE        (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */
+#define PIC32MZ_OSC_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */
+#define PIC32MZ_PPS_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */
+#define PIC32MZ_INTC_K1BASE         (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */
+#define PIC32MZ_DMA_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */
+#define PIC32MZ_I2C_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */
+#define PIC32MZ_SPI_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */
+#define PIC32MZ_UART_K1BASE         (PIC32MZ_SFR_K1BASE + 0x00022000) /* UART1-UART6 */
+#define PIC32MZ_PMP_K1BASE          (PIC32MZ_SFR_K1BASE + 0x0002e000) /* PMP */
+#define PIC32MZ_TIMER_K1BASE        (PIC32MZ_SFR_K1BASE + 0x00040000) /* Timer1-Timer9 */
+#define PIC32MZ_IC_K1BASE           (PIC32MZ_SFR_K1BASE + 0x00042000) /* IC1-IC9 */
+#define PIC32MZ_OC_K1BASE           (PIC32MZ_SFR_K1BASE + 0x00044000) /* OC1-OC9 */
+#define PIC32MZ_ADC1_K1BASE         (PIC32MZ_SFR_K1BASE + 0x0004b000) /* ADC1 */
+#define PIC32MZ_CMP_K1BASE          (PIC32MZ_SFR_K1BASE + 0x0004c000) /* Comparator 1, 2 */
+#define PIC32MZ_PORT_K1BASE         (PIC32MZ_SFR_K1BASE + 0x00060000) /* PORTA-PORTK */
+#define PIC32MZ_CAN_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00080000) /* CAN1 and CAN2 */
+#define PIC32MZ_ETH_K1BASE          (PIC32MZ_SFR_K1BASE + 0x00082000) /* Ethernet */
+#define PIC32MZ_PREFETCH_K1BASE     (PIC32MZ_SFR_K1BASE + 0x000e0000) /* Prefetch */
+#define PIC32MZ_EBI_K1BASE          (PIC32MZ_SFR_K1BASE + 0x000e1000) /* EBI */
+#define PIC32MZ_SQI1_K1BASE         (PIC32MZ_SFR_K1BASE + 0x000e2000) /* SQI1 */
+#define PIC32MZ_USB_K1BASE          (PIC32MZ_SFR_K1BASE + 0x000e3000) /* USB */
+#define PIC32MZ_CRYPTO_K1BASE       (PIC32MZ_SFR_K1BASE + 0x000e5000) /* Crypto */
+#define PIC32MZ_RNG_K1BASE          (PIC32MZ_SFR_K1BASE + 0x000e6000) /* RNG */
+#define PIC32MZ_SYSBUS_K1BASE       (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */
+
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H */
diff --git a/nuttx/arch/mips/src/pic32mz/pic32mz-excptmacros.h b/nuttx/arch/mips/src/pic32mz/pic32mz-excptmacros.h
index eac1edad7..08ac71837 100644
--- a/nuttx/arch/mips/src/pic32mz/pic32mz-excptmacros.h
+++ b/nuttx/arch/mips/src/pic32mz/pic32mz-excptmacros.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/mips/src/pic32mz/excptmacros.h
+ * arch/mips/src/pic32mz/pic32mz-excptmacros.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>