PIC32MZ: Framework for startup function. Still has too much PIC32MX garbage in it to be credible

4 files changed, 2124 insertions, 1 deletions

diff --git a/nuttx/arch/mips/src/pic32mz/Make.defs b/nuttx/arch/mips/src/pic32mz/Make.defs
index 2f17629b4..53e5a961f 100644
--- a/nuttx/arch/mips/src/pic32mz/Make.defs
+++ b/nuttx/arch/mips/src/pic32mz/Make.defs
@@ -35,7 +35,7 @@
 
 # The start-up, "head", file
 
-HEAD_ASRC = # pic32mz-head.S
+HEAD_ASRC = pic32mz-head.S
 
 # Common MIPS files
 
diff --git a/nuttx/arch/mips/src/pic32mz/pic32mz-config.h b/nuttx/arch/mips/src/pic32mz/pic32mz-config.h
new file mode 100644
index 000000000..fee820773
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mz/pic32mz-config.h
@@ -0,0 +1,916 @@
+/************************************************************************************
+ * arch/mips/src/pic32mz/pic32mz-config.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CONFIG_H
+#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CONFIG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/board/board.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Interrupt Priorities *************************************************************/
+
+#ifndef CONFIG_PIC32MZ_CTPRIO         /* Core Timer Interrupt */
+#  define CONFIG_PIC32MZ_CTPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_CTPRIO < 4
+#  error "CONFIG_PIC32MZ_CTPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_CTPRIO > 31
+#  error "CONFIG_PIC32MZ_CTPRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_CS0PRIO       /* Core Software Interrupt 0 */
+#  define CONFIG_PIC32MZ_CS0PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_CS0PRIO < 4
+#  error "CONFIG_PIC32MZ_CS0PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_CS0PRIO > 31
+#  error "CONFIG_PIC32MZ_CS0PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_CS1PRIO      /* Core Software Interrupt 1 */
+#  define CONFIG_PIC32MZ_CS1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_CS1PRIO < 4
+#  error "CONFIG_PIC32MZ_CS1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_CS1PRIO > 31
+#  error "CONFIG_PIC32MZ_CS1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_INT0PRIO      /* External interrupt 0 */
+#  define CONFIG_PIC32MZ_INT0PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_INT0PRIO < 4
+#  error "CONFIG_PIC32MZ_INT0PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_INT0PRIO > 31
+#  error "CONFIG_PIC32MZ_INT0PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_INT1PRIO      /* External interrupt 1 */
+#  define CONFIG_PIC32MZ_INT1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_INT1PRIO < 4
+#  error "CONFIG_PIC32MZ_INT1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_INT1PRIO > 31
+#  error "CONFIG_PIC32MZ_INT1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_INT2PRIO      /* External interrupt 2 */
+#  define CONFIG_PIC32MZ_INT2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_INT2PRIO < 4
+#  error "CONFIG_PIC32MZ_INT2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_INT2PRIO > 31
+#  error "CONFIG_PIC32MZ_INT2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_INT3PRIO      /* External interrupt 3 */
+#  define CONFIG_PIC32MZ_INT3PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_INT3PRIO < 4
+#  error "CONFIG_PIC32MZ_INT3PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_INT3PRIO > 31
+#  error "CONFIG_PIC32MZ_INT3PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_INT4PRIO      /* External interrupt 4 */
+#  define CONFIG_PIC32MZ_INT4PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_INT4PRIO < 4
+#  error "CONFIG_PIC32MZ_INT4PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_INT4PRIO > 31
+#  error "CONFIG_PIC32MZ_INT4PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_FSCMPRIO      /* Fail-Safe Clock Monitor */
+#  define CONFIG_PIC32MZ_FSCMPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_FSCMPRIO < 4
+#  error "CONFIG_PIC32MZ_FSCMPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_FSCMPRIO > 31
+#  error "CONFIG_PIC32MZ_FSCMPRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_T1PRIO        /* Timer 1 (System timer) priority */
+#  define CONFIG_PIC32MZ_T1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_T1PRIO < 4
+#  error "CONFIG_PIC32MZ_T1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_T1PRIO > 31
+#  error "CONFIG_PIC32MZ_T1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_T2PRIO        /* Timer 2 priority */
+#  define CONFIG_PIC32MZ_T2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_T2PRIO < 4
+#  error "CONFIG_PIC32MZ_T2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_T2PRIO > 31
+#  error "CONFIG_PIC32MZ_T2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_T3PRIO        /* Timer 3 priority */
+#  define CONFIG_PIC32MZ_T3PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_T3PRIO < 4
+#  error "CONFIG_PIC32MZ_T3PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_T3PRIO > 31
+#  error "CONFIG_PIC32MZ_T3PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_T4PRIO        /* Timer 4 priority */
+#  define CONFIG_PIC32MZ_T4PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_T4PRIO < 4
+#  error "CONFIG_PIC32MZ_T4PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_T4PRIO > 31
+#  error "CONFIG_PIC32MZ_T4PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_T5PRIO        /* Timer 5 priority */
+#  define CONFIG_PIC32MZ_T5PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_T5PRIO < 4
+#  error "CONFIG_PIC32MZ_T5PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_T5PRIO > 31
+#  error "CONFIG_PIC32MZ_T5PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_IC1PRIO       /* Input Capture 1 */
+#  define CONFIG_PIC32MZ_IC1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_IC1PRIO < 4
+#  error "CONFIG_PIC32MZ_IC1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_IC1PRIO > 31
+#  error "CONFIG_PIC32MZ_IC1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_IC2PRIO       /* Input Capture 2 */
+#  define CONFIG_PIC32MZ_IC2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_IC2PRIO < 4
+#  error "CONFIG_PIC32MZ_IC2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_IC2PRIO > 31
+#  error "CONFIG_PIC32MZ_IC2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_IC3PRIO       /* Input Capture 3 */
+#  define CONFIG_PIC32MZ_IC3PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_IC3PRIO < 4
+#  error "CONFIG_PIC32MZ_IC3PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_IC3PRIO > 31
+#  error "CONFIG_PIC32MZ_IC3PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_IC4PRIO       /* Input Capture 4 */
+#  define CONFIG_PIC32MZ_IC4PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_IC4PRIO < 4
+#  error "CONFIG_PIC32MZ_IC4PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_IC4PRIO > 31
+#  error "CONFIG_PIC32MZ_IC4PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_IC5PRIO       /* Input Capture 5 */
+#  define CONFIG_PIC32MZ_IC5PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_IC5PRIO < 4
+#  error "CONFIG_PIC32MZ_IC5PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_IC5PRIO > 31
+#  error "CONFIG_PIC32MZ_IC5PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_OC1PRIO       /* Output Compare 1 */
+#  define CONFIG_PIC32MZ_OC1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_OC1PRIO < 4
+#  error "CONFIG_PIC32MZ_OC1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_OC1PRIO > 31
+#  error "CONFIG_PIC32MZ_OC1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_OC2PRIO       /* Output Compare 2 */
+#  define CONFIG_PIC32MZ_OC2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_OC2PRIO < 4
+#  error "CONFIG_PIC32MZ_OC2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_OC2PRIO > 31
+#  error "CONFIG_PIC32MZ_OC2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_OC3PRIO       /* Output Compare 3 */
+#  define CONFIG_PIC32MZ_OC3PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_OC3PRIO < 4
+#  error "CONFIG_PIC32MZ_OC3PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_OC3PRIO > 31
+#  error "CONFIG_PIC32MZ_OC3PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_OC4PRIO       /* Output Compare 4 */
+#  define CONFIG_PIC32MZ_OC4PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_OC4PRIO < 4
+#  error "CONFIG_PIC32MZ_OC4PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_OC4PRIO > 31
+#  error "CONFIG_PIC32MZ_OC4PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_OC5PRIO       /* Output Compare 5 */
+#  define CONFIG_PIC32MZ_OC5PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_OC5PRIO < 4
+#  error "CONFIG_PIC32MZ_OC5PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_OC5PRIO > 31
+#  error "CONFIG_PIC32MZ_OC5PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_I2C1PRIO      /* I2C 1 */
+#  define CONFIG_PIC32MZ_I2C1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_I2C1PRIO < 4
+#  error "CONFIG_PIC32MZ_I2C1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_I2C1PRIO > 31
+#  error "CONFIG_PIC32MZ_I2C1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_I2C2PRIO      /* I2C 2 */
+#  define CONFIG_PIC32MZ_I2C2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_I2C2PRIO < 4
+#  error "CONFIG_PIC32MZ_I2C2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_I2C2PRIO > 31
+#  error "CONFIG_PIC32MZ_I2C2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_SPI1PRIO      /* SPI 1 */
+#  define CONFIG_PIC32MZ_SPI1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_SPI1PRIO < 4
+#  error "CONFIG_PIC32MZ_SPI1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_SPI1PRIO > 31
+#  error "CONFIG_PIC32MZ_SPI1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_SPI2PRIO      /* SPI 2 */
+#  define CONFIG_PIC32MZ_SPI2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_SPI2PRIO < 4
+#  error "CONFIG_PIC32MZ_SPI2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_SPI2PRIO > 31
+#  error "CONFIG_PIC32MZ_SPI2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_UART1PRIO      /* UART 1 */
+#  define CONFIG_PIC32MZ_UART1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_UART1PRIO < 4
+#  error "CONFIG_PIC32MZ_UART1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_UART1PRIO > 31
+#  error "CONFIG_PIC32MZ_UART1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_UART2PRIO      /* UART 2 */
+#  define CONFIG_PIC32MZ_UART2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_UART2PRIO < 4
+#  error "CONFIG_PIC32MZ_UART2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_UART2PRIO > 31
+#  error "CONFIG_PIC32MZ_UART2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_CNPRIO            /* Input Change Interrupt */
+#  define CONFIG_PIC32MZ_CNPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_CNPRIO < 4
+#  error "CONFIG_PIC32MZ_CNPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_CNPRIO > 31
+#  error "CONFIG_PIC32MZ_CNPRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_ADCPRIO       /* ADC1 Convert Done */
+#  define CONFIG_PIC32MZ_ADCPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_ADCPRIO < 4
+#  error "CONFIG_PIC32MZ_ADCPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_ADCPRIO > 31
+#  error "CONFIG_PIC32MZ_ADCPRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_PMPPRIO       /* Parallel Master Port */
+#  define CONFIG_PIC32MZ_PMPPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_PMPPRIO < 4
+#  error "CONFIG_PIC32MZ_PMPPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_PMPPRIO > 31
+#  error "CONFIG_PIC32MZ_PMPPRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_CM1PRIO       /* Comparator 1 */
+#  define CONFIG_PIC32MZ_CM1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_CM1PRIO < 4
+#  error "CONFIG_PIC32MZ_CM1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_CM1PRIO > 31
+#  error "CONFIG_PIC32MZ_CM1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_CM2PRIO       /* Comparator 2 */
+#  define CONFIG_PIC32MZ_CM2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_CM2PRIO < 4
+#  error "CONFIG_PIC32MZ_CM2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_CM2PRIO > 31
+#  error "CONFIG_PIC32MZ_CM2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_FSCMPRIO      /* Fail-Safe Clock Monitor */
+#  define CONFIG_PIC32MZ_FSCMPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_FSCMPRIO < 4
+#  error "CONFIG_PIC32MZ_FSCMPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_FSCMPRIO > 31
+#  error "CONFIG_PIC32MZ_FSCMPRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_RTCCPRIO      /* Real-Time Clock and Calendar */
+#  define CONFIG_PIC32MZ_RTCCPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_RTCCPRIO < 4
+#  error "CONFIG_PIC32MZ_RTCCPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_RTCCPRIO > 31
+#  error "CONFIG_PIC32MZ_RTCCPRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_DMA0PRIO      /* DMA Channel 0 */
+#  define CONFIG_PIC32MZ_DMA0PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_DMA0PRIO < 4
+#  error "CONFIG_PIC32MZ_DMA0PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_DMA0PRIO > 31
+#  error "CONFIG_PIC32MZ_DMA0PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_DMA1PRIO      /* DMA Channel 1 */
+#  define CONFIG_PIC32MZ_DMA1PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_DMA1PRIO < 4
+#  error "CONFIG_PIC32MZ_DMA1PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_DMA1PRIO > 31
+#  error "CONFIG_PIC32MZ_DMA1PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_DMA2PRIO      /* DMA Channel 2 */
+#  define CONFIG_PIC32MZ_DMA2PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_DMA2PRIO < 4
+#  error "CONFIG_PIC32MZ_DMA2PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_DMA2PRIO > 31
+#  error "CONFIG_PIC32MZ_DMA2PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_DMA3PRIO      /* DMA Channel 3 */
+#  define CONFIG_PIC32MZ_DMA3PRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_DMA3PRIO < 4
+#  error "CONFIG_PIC32MZ_DMA3PRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_DMA3PRIO > 31
+#  error "CONFIG_PIC32MZ_DMA3PRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_FCEPRIO       /* Flash Control Event */
+#  define CONFIG_PIC32MZ_FCEPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_FCEPRIO < 4
+#  error "CONFIG_PIC32MZ_FCEPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_FCEPRIO > 31
+#  error "CONFIG_PIC32MZ_FCEPRIO is too large"
+#endif
+
+#ifndef CONFIG_PIC32MZ_USBPRIO       /* USB */
+#  define CONFIG_PIC32MZ_USBPRIO (INT_IPC_MID_PRIORITY << 2)
+#endif
+#if CONFIG_PIC32MZ_USBPRIO < 4
+#  error "CONFIG_PIC32MZ_USBPRIO is too small"
+#endif
+#if CONFIG_PIC32MZ_USBPRIO > 31
+#  error "CONFIG_PIC32MZ_USBPRIO is too large"
+#endif
+
+/* SYS calls ************************************************************************/
+/* SYS call 1 and 2 are defined for internal use by the PIC32MZ port (see
+ * arch/mips/include/mips32/syscall.h).  In addition, SYS call 3 is the return from
+ * a SYS call in kernel mode.  The first four syscall values must, therefore, be
+ * reserved (0 is not used).
+ */
+
+#ifdef CONFIG_BUILD_KERNEL
+#  if !defined(CONFIG_SYS_RESERVED) || CONFIG_SYS_RESERVED < 4
+#    error "CONFIG_SYS_RESERVED must be defined to be 4 for a kernel build"
+#  elif CONFIG_SYS_RESERVED > 4
+#    warning "CONFIG_SYS_RESERVED should be defined to be 4 for a kernel build"
+#  endif
+#endif
+
+/* UARTs ****************************************************************************/
+/* Don't enable UARTs not supported by the chip. */
+
+#if CHIP_NUARTS < 1
+#  undef CONFIG_PIC32MZ_UART1
+#  undef CONFIG_PIC32MZ_UART2
+#  undef CONFIG_PIC32MZ_UART3
+#  undef CONFIG_PIC32MZ_UART4
+#  undef CONFIG_PIC32MZ_UART5
+#  undef CONFIG_PIC32MZ_UART6
+#elif CHIP_NUARTS < 2
+#  undef CONFIG_PIC32MZ_UART2
+#  undef CONFIG_PIC32MZ_UART3
+#  undef CONFIG_PIC32MZ_UART4
+#  undef CONFIG_PIC32MZ_UART5
+#  undef CONFIG_PIC32MZ_UART6
+#elif CHIP_NUARTS < 3
+#  undef CONFIG_PIC32MZ_UART3
+#  undef CONFIG_PIC32MZ_UART4
+#  undef CONFIG_PIC32MZ_UART5
+#  undef CONFIG_PIC32MZ_UART6
+#elif CHIP_NUARTS < 4
+#  undef CONFIG_PIC32MZ_UART4
+#  undef CONFIG_PIC32MZ_UART5
+#  undef CONFIG_PIC32MZ_UART6
+#elif CHIP_NUARTS < 5
+#  undef CONFIG_PIC32MZ_UART5
+#  undef CONFIG_PIC32MZ_UART6
+#elif CHIP_NUARTS < 6
+#  undef CONFIG_PIC32MZ_UART6
+#endif
+
+/* Are any UARTs enabled? */
+
+#undef HAVE_UART_DEVICE
+#if defined(CONFIG_PIC32MZ_UART1) || defined(CONFIG_PIC32MZ_UART2) || \
+    defined(CONFIG_PIC32MZ_UART4) || defined(CONFIG_PIC32MZ_UART4) || \
+    defined(CONFIG_PIC32MZ_UART5) || defined(CONFIG_PIC32MZ_UART6)
+#  define HAVE_UART_DEVICE 1
+#endif
+
+/* Is there a serial console?  There should be no more than one defined.  It
+ * could be on any UARTn, n=1,.. CHIP_NUARTS
+ */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_PIC32MZ_UART1)
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  undef CONFIG_UART4_SERIAL_CONSOLE
+#  undef CONFIG_UART5_SERIAL_CONSOLE
+#  undef CONFIG_UART6_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_PIC32MZ_UART2)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  undef CONFIG_UART4_SERIAL_CONSOLE
+#  undef CONFIG_UART5_SERIAL_CONSOLE
+#  undef CONFIG_UART6_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_PIC32MZ_UART3)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART4_SERIAL_CONSOLE
+#  undef CONFIG_UART5_SERIAL_CONSOLE
+#  undef CONFIG_UART6_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_PIC32MZ_UART4)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  undef CONFIG_UART5_SERIAL_CONSOLE
+#  undef CONFIG_UART6_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_PIC32MZ_UART5)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  undef CONFIG_UART4_SERIAL_CONSOLE
+#  undef CONFIG_UART6_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && defined(CONFIG_PIC32MZ_UART6)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  undef CONFIG_UART4_SERIAL_CONSOLE
+#  undef CONFIG_UART5_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#else
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  undef CONFIG_UART4_SERIAL_CONSOLE
+#  undef CONFIG_UART5_SERIAL_CONSOLE
+#  undef CONFIG_UART6_SERIAL_CONSOLE
+#  undef HAVE_SERIAL_CONSOLE
+#endif
+
+/* Device Configuration *************************************************************/
+/* DEVCFG3 */
+
+#ifndef CONFIG_PIC32MZ_USERID               /* User ID */
+#  define CONFIG_PIC32MZ_USERID   0x584e    /* "NutX" */
+#endif
+
+#ifndef CONFIG_PIC32MZ_PMDL1WAY             /* Peripheral module disable configuration */
+#  define CONFIG_PIC32MZ_PMDL1WAY 0
+#endif
+
+#ifndef CONFIG_PIC32MZ_IOL1WAY              /* Peripheral pin select configuration */
+#  define CONFIG_PIC32MZ_IOL1WAY  0
+#endif
+
+#ifndef CONFIG_PIC32MZ_SRSSEL               /* Shadow register interrupt priority */
+#  define CONFIG_PIC32MZ_SRSSEL   INT_IPC_MIN_PRIORITY
+#endif
+
+/* Unless overridden in the .config file, all pins are in the default setting */
+
+#ifndef CONFIG_PIC32MZ_FMIIEN               /* Ethernet MII enable: 0=RMII 1=MII */
+#  define CONFIG_PIC32MZ_FMIIEN   1         /* MII enabled */
+#endif
+
+#ifndef CONFIG_PIC32MZ_FETHIO               /* Ethernet I/O Pins 0=alternate 1=default */
+#  define CONFIG_PIC32MZ_FETHIO   1         /* Default Ethernet I/O Pins */
+#endif
+
+#ifndef CONFIG_PIC32MZ_FCANIO               /* SCM1 pin C selection */
+#  define CONFIG_PIC32MZ_FCANIO   1         /* Default CAN I/O Pins */
+#endif
+
+#ifndef CONFIG_PIC32MZ_FSCM1IO              /* SCM1 pin C selection */
+#  define CONFIG_PIC32MZ_FSCM1IO  1         /* Default pin for SCM1C */
+#endif
+
+/* USB or Ports? */
+
+#ifdef CONFIG_PIC32MZ_USB
+#  ifndef CONFIG_PIC32MZ_USBIDO            /* USB USBID Selection */
+#    define CONFIG_PIC32MZ_USBIDO 1        /* USBID pin is controlled by the USB module */
+#  endif
+#  ifndef CONFIG_PIC32MZ_VBUSIO            /* USB VBUSON Selection */
+#    define CONFIG_PIC32MZ_VBUSIO 1        /* VBUSON pin is controlled by the USB module */
+#  endif
+#else
+#  ifndef CONFIG_PIC32MZ_USBIDO            /* USB USBID Selection */
+#    define CONFIG_PIC32MZ_USBIDO 0        /* USBID pin is controlled by the Port function */
+#  endif
+#  ifndef CONFIG_PIC32MZ_VBUSIO            /* USB VBUSON Selection */
+#    define CONFIG_PIC32MZ_VBUSIO 0        /* VBUSON pin is controlled by the Port function */
+#  endif
+#endif
+
+/* DEVCFG2 */
+
+#undef CONFIG_PIC32MZ_PLLIDIV
+#if BOARD_PLL_IDIV == 1
+#  define CONFIG_PIC32MZ_PLLIDIV  DEVCFG2_FPLLIDIV_DIV1
+#elif BOARD_PLL_IDIV == 2
+#  define CONFIG_PIC32MZ_PLLIDIV  DEVCFG2_FPLLIDIV_DIV2
+#elif BOARD_PLL_IDIV == 3
+#  define CONFIG_PIC32MZ_PLLIDIV  DEVCFG2_FPLLIDIV_DIV3
+#elif BOARD_PLL_IDIV == 4
+#  define CONFIG_PIC32MZ_PLLIDIV  DEVCFG2_FPLLIDIV_DIV4
+#elif BOARD_PLL_IDIV == 5
+#  define CONFIG_PIC32MZ_PLLIDIV  DEVCFG2_FPLLIDIV_DIV5
+#elif BOARD_PLL_IDIV == 6
+#  define CONFIG_PIC32MZ_PLLIDIV  DEVCFG2_FPLLIDIV_DIV6
+#elif BOARD_PLL_IDIV == 10
+#  define CONFIG_PIC32MZ_PLLIDIV  DEVCFG2_FPLLIDIV_DIV10
+#elif BOARD_PLL_IDIV == 12
+#  define CONFIG_PIC32MZ_PLLIDIV  DEVCFG2_FPLLIDIV_DIV12
+#else
+#  error "Unsupported BOARD_PLL_IDIV"
+#endif
+
+#undef CONFIG_PIC32MZ_PLLMULT
+#if BOARD_PLL_MULT == 15
+#  define CONFIG_PIC32MZ_PLLMULT  DEVCFG2_FPLLMULT_MUL15
+#elif BOARD_PLL_MULT == 16
+#  define CONFIG_PIC32MZ_PLLMULT  DEVCFG2_FPLLMULT_MUL16
+#elif BOARD_PLL_MULT == 17
+#  define CONFIG_PIC32MZ_PLLMULT  DEVCFG2_FPLLMULT_MUL17
+#elif BOARD_PLL_MULT == 18
+#  define CONFIG_PIC32MZ_PLLMULT  DEVCFG2_FPLLMULT_MUL18
+#elif BOARD_PLL_MULT == 19
+#  define CONFIG_PIC32MZ_PLLMULT  DEVCFG2_FPLLMULT_MUL19
+#elif BOARD_PLL_MULT == 20
+#  define CONFIG_PIC32MZ_PLLMULT  DEVCFG2_FPLLMULT_MUL20
+#elif BOARD_PLL_MULT == 21
+#  define CONFIG_PIC32MZ_PLLMULT  DEVCFG2_FPLLMULT_MUL21
+#elif BOARD_PLL_MULT == 24
+#  define CONFIG_PIC32MZ_PLLMULT  DEVCFG2_FPLLMULT_MUL24
+#else
+#  error "Unsupported BOARD_PLL_MULT"
+#endif
+
+#undef CONFIG_PIC32MZ_UPLLIDIV
+#if BOARD_UPLL_IDIV == 1
+#  define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV1
+#elif BOARD_UPLL_IDIV == 2
+#  define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV2
+#elif BOARD_UPLL_IDIV == 3
+#  define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV3
+#elif BOARD_UPLL_IDIV == 4
+#  define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV4
+#elif BOARD_UPLL_IDIV == 5
+#  define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV5
+#elif BOARD_UPLL_IDIV == 6
+#  define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV6
+#elif BOARD_UPLL_IDIV == 10
+#  define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV10
+#elif BOARD_UPLL_IDIV == 12
+#  define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV12
+#else
+#  error "Unsupported BOARD_UPLL_IDIV"
+#endif
+
+#ifndef CONFIG_PIC32MZ_FUPLLEN
+#  if defined(CONFIG_PIC32MZ_USBDEV) || defined(CONFIG_PIC32MZ_USBHOST)
+#    define CONFIG_PIC32MZ_FUPLLEN 0 /* Enable */
+#  else
+#    define CONFIG_PIC32MZ_FUPLLEN 1 /* Bypass and disable */
+#  endif
+#endif
+
+#undef CONFIG_PIC32MZ_PLLODIV
+#if BOARD_PLL_ODIV == 1
+#  define CONFIG_PIC32MZ_PLLODIV  DEVCFG2_FPLLODIV_DIV1
+#elif BOARD_PLL_ODIV == 2
+#  define CONFIG_PIC32MZ_PLLODIV  DEVCFG2_FPLLODIV_DIV2
+#elif BOARD_PLL_ODIV == 4
+#  define CONFIG_PIC32MZ_PLLODIV  DEVCFG2_FPLLODIV_DIV2
+#elif BOARD_PLL_ODIV == 8
+#  define CONFIG_PIC32MZ_PLLODIV  DEVCFG2_FPLLODIV_DIV2
+#elif BOARD_PLL_ODIV == 16
+#  define CONFIG_PIC32MZ_PLLODIV  DEVCFG2_FPLLODIV_DIV2
+#elif BOARD_PLL_ODIV == 32
+#  define CONFIG_PIC32MZ_PLLODIV  DEVCFG2_FPLLODIV_DIV2
+#elif BOARD_PLL_ODIV == 64
+#  define CONFIG_PIC32MZ_PLLODIV  DEVCFG2_FPLLODIV_DIV2
+#elif BOARD_PLL_ODIV == 128
+#  define CONFIG_PIC32MZ_PLLODIV  DEVCFG2_FPLLODIV_DIV2
+#else
+#  error "Unsupported BOARD_PLL_ODIV"
+#endif
+
+/* DEVCFG1 */
+
+#ifdef BOARD_SOSC_ENABLE
+#  define CONFIG_PIC32MZ_FSOSCEN DEVCFG1_FSOSCEN
+#else
+#  define CONFIG_PIC32MZ_FSOSCEN 0
+#endif
+
+#ifdef BOARD_SOSC_IESO
+#  define CONFIG_PIC32MZ_IESO DEVCFG1_IESO
+#else
+#  define CONFIG_PIC32MZ_IESO 0
+#endif
+
+#undef CONFIG_PIC32MZ_PBDIV
+#if BOARD_PBDIV == 1
+#  define CONFIG_PIC32MZ_PBDIV DEVCFG1_FPBDIV_DIV1
+#elif BOARD_PBDIV == 2
+#  define CONFIG_PIC32MZ_PBDIV DEVCFG1_FPBDIV_DIV2
+#elif BOARD_PBDIV == 4
+#  define CONFIG_PIC32MZ_PBDIV DEVCFG1_FPBDIV_DIV4
+#elif BOARD_PBDIV == 8
+#  define CONFIG_PIC32MZ_PBDIV DEVCFG1_FPBDIV_DIV8
+#else
+#  error "Unsupported BOARD_PBDIV"
+#endif
+
+#undef CONFIG_PIC32MZ_POSCMOD
+#if defined(BOARD_POSC_ECMODE)
+#  define CONFIG_PIC32MZ_POSCMOD DEVCFG1_POSCMOD_EC
+#elif defined(BOARD_POSC_XTMODE)
+#  define CONFIG_PIC32MZ_POSCMOD DEVCFG1_POSCMOD_XT
+#elif defined(BOARD_POSC_HSMODE)
+#  define CONFIG_PIC32MZ_POSCMOD DEVCFG1_POSCMOD_HS
+#elif defined(BOARD_POSC_DISABLED)
+#  define CONFIG_PIC32MZ_POSCMOD DEVCFG1_POSCMOD_DIS
+#else
+#  error "Unknown board POSC mode"
+#endif
+
+#undef CONFIG_PIC32MZ_FNOSC
+#if defined(BOARD_FNOSC_FRC)
+#  define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_FRC
+#elif defined(BOARD_FNOSC_FRCPLL)
+#  define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_FRCPLL
+#elif defined(BOARD_FNOSC_POSC)
+#  define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_POSC
+#elif defined(BOARD_FNOSC_POSCPLL)
+#  define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_POSCPLL
+#elif defined(BOARD_FNOSC_SOSC)
+#  define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_SOSC
+#elif defined(BOARD_FNOSC_LPRC)
+#  define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_LPRC
+#elif defined(BOARD_FNOSC_FRCDIV)
+#  define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_FRCDIV
+#else
+#  error "Unknown board FNOSC selection"
+#endif
+
+#undef CONFIG_PIC32MZ_FCKSM
+#if defined(BOARD_POSC_SWITCH)
+#  if defined(BOARD_POSC_FSCM)
+#    define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_BOTH
+#  else
+#    define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_CSONLY
+#  endif
+#else
+#  define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_NONE
+#endif
+
+#ifndef CONFIG_PIC32MZ_OSCOUT
+#  define CONFIG_PIC32MZ_OSCOUT 0
+#endif
+
+#undef CONFIG_PIC32MZ_WDPS
+#if BOARD_WD_PRESCALER == 1
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_1
+#elif BOARD_WD_PRESCALER == 2
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_2
+#elif BOARD_WD_PRESCALER == 4
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_4
+#elif BOARD_WD_PRESCALER == 8
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_8
+#elif BOARD_WD_PRESCALER == 16
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_16
+#elif BOARD_WD_PRESCALER == 32
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_32
+#elif BOARD_WD_PRESCALER == 64
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_64
+#elif BOARD_WD_PRESCALER == 128
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_128
+#elif BOARD_WD_PRESCALER == 256
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_256
+#elif BOARD_WD_PRESCALER == 512
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_512
+#elif BOARD_WD_PRESCALER == 1024
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_1024
+#elif BOARD_WD_PRESCALER == 2048
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_2048
+#elif BOARD_WD_PRESCALER == 4096
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_4096
+#elif BOARD_WD_PRESCALER == 8192
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_8192
+#elif BOARD_WD_PRESCALER == 16384
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_16384
+#elif BOARD_WD_PRESCALER == 32768
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_32768
+#elif BOARD_WD_PRESCALER == 65536
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_65536
+#elif BOARD_WD_PRESCALER == 131072
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_131072
+#elif BOARD_WD_PRESCALER == 262144
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_262144
+#elif BOARD_WD_PRESCALER == 524288
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_524288
+#elif BOARD_WD_PRESCALER == 1048576
+#  define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_1048576
+#else
+#  error "Unsupported BOARD_WD_PRESCALER"
+#endif
+
+#undef CONFIG_PIC32MZ_WDENABLE
+#if BOARD_WD_ENABLE
+#  define CONFIG_PIC32MZ_WDENABLE DEVCFG1_FWDTEN
+#else
+#  define CONFIG_PIC32MZ_WDENABLE 0
+#endif
+
+/* DEVCFG0 */
+
+#ifndef CONFIG_PIC32MZ_DEBUGGER                 /* Background Debugger Enable */
+#  define CONFIG_PIC32MZ_DEBUGGER         3     /* disabled */
+#endif
+
+#ifndef CONFIG_PIC32MZ_ICESEL                   /* In-Circuit Emulator/Debugger Communication Channel Select */
+#  if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
+#    define CONFIG_PIC32MZ_ICESEL         3     /* Default PGEC1/PGED1 */
+#  else
+#    define CONFIG_PIC32MZ_ICESEL         1     /* Default PGEC1/PGED1 */
+#  endif
+#endif
+
+#ifndef CONFIG_PIC32MZ_PROGFLASHWP              /* Program FLASH write protect */
+#  if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
+#    define CONFIG_PIC32MZ_PROGFLASHWP    0x3ff /* Disabled */
+#  else
+#    define CONFIG_PIC32MZ_PROGFLASHWP    0xff  /* Disabled */
+#  endif
+#endif
+
+#ifndef CONFIG_PIC32MZ_BOOTFLASHWP
+#  define CONFIG_PIC32MZ_BOOTFLASHWP      1     /* Disabled */
+#endif
+
+#ifndef CONFIG_PIC32MZ_CODEWP
+#  define CONFIG_PIC32MZ_CODEWP           1     /* Disabled */
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CONFIG_H */
diff --git a/nuttx/arch/mips/src/pic32mz/pic32mz-excptmacros.h b/nuttx/arch/mips/src/pic32mz/pic32mz-excptmacros.h
new file mode 100644
index 000000000..eac1edad7
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mz/pic32mz-excptmacros.h
@@ -0,0 +1,449 @@
+/********************************************************************************************
+ * arch/mips/src/pic32mz/excptmacros.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_EXCPTMACROS_H
+#define __ARCH_MIPS_SRC_PIC32MZ_EXCPTMACROS_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+#include <arch/pic32mz/cp0.h>
+
+#ifdef __ASSEMBLY__
+
+/********************************************************************************************
+ * Pre-Processor Definitions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Global Symbols
+ ********************************************************************************************/
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	.global		g_intstackbase
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+	.global		g_nestlevel
+#endif
+#endif
+
+/********************************************************************************************
+ * Assembly Language Macros
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * General Usage Example:
+ *
+ * my_exception:
+ *		EXCPT_PROLOGUE t0			- Save registers on stack, enable nested interrupts
+ *		move a0, sp					- Pass register save structure as the parameter 1
+ *		USE_INTSTACK t0, t1, t2		- Switch to the interrupt stack
+ *		jal	handler					- Handle the exception IN=old regs OUT=new regs
+ *		di							- Disable interrupts
+ *		RESTORE_STACK t0, t1		- Undo the operations of USE_STACK
+ *		EXCPT_EPILOGUE v0			- Return to the context returned by handler()
+ *
+ ********************************************************************************************/
+/********************************************************************************************
+ * Name: EXCPT_PROLOGUE
+ *
+ * Description:
+ *   Provides the "prologue" logic that should appear at the beginning of every exception
+ *   handler.
+ *
+ * On Entry:
+ *   sp - Points to the top of the stack
+ *   tmp - Is a register the can be modified for scratch usage (after it has been saved)
+ *   k0 and k1 - Since we are in an exception handler, these are available for use
+ *
+ * At completion:
+ *   Register state is saved on the stack; All registers are available for usage except sp
+ *   and k1:
+ *
+ *   - sp points the beginning of the register save area
+ *   - k1 holds the value of the STATUS register
+ *
+ *   The following registers are modified: k0, k1, sp, a0
+ *
+ ********************************************************************************************/
+
+	.macro	EXCPT_PROLOGUE, tmp
+	.set	noat
+
+	/* Get the SP from the previous shadow set */
+
+#if 0
+	rdpgpr	sp, sp
+#endif
+
+	/* "When entering the interrupt handler routine, the interrupt controller must first
+	 *  save the current priority and exception PC counter from Interrupt  Priority (IPL)
+	 *  bits (Status<15:10>) and the ErrorEPC register, respectively, on the stack. ..."
+	 */
+
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS // Does not work!
+	mfc0	k0, MIPS32_CP0_CAUSE
+	mfc0 	k1, MIPS32_CP0_EPC
+
+	/* Isolate the pending interrupt level in bits 0-5 of k0 */
+
+	srl		k0, k0, CP0_CAUSE_IP_SHIFT
+
+	/* Create the register context stack frame large enough to hold the entire register save
+	 * array.
+	 */
+
+	addiu	sp, sp, -XCPTCONTEXT_SIZE
+
+	/* Save the EPC and STATUS in the register context array */
+
+	sw		k1, REG_EPC(sp)
+	mfc0	k1, MIPS32_CP0_STATUS
+	sw		k1, REG_STATUS(sp)
+
+	/* Then insert pending interrupt level as the current mask level in the CP0 status
+	 * register. Also clear bits 1-4 in new value of the status register:
+	 *
+	 *   Bit 1: Exception Level
+	 *   Bit 2: Error Level
+	 *   Bit 3: (not used in PIC32MZ)
+	 *   Bit 4: Operating mode == USER
+	 */
+
+	ins 	k1, k0, CP0_STATUS_IPL_SHIFT, 6
+	ins		k1, zero, 1, 4
+
+	/* And Enable interrupts */
+
+	mtc0	k1, MIPS32_CP0_STATUS
+#else
+	/* Get the EPC and STATUS register (Don't bother with the CAUSE register if we are
+	 * not supporting nested interrupts)
+	 */
+
+	mfc0 	k0, MIPS32_CP0_EPC
+	mfc0	k1, MIPS32_CP0_STATUS
+
+	/* Create the register context stack frame large enough to hold the entire register
+	 * save array.
+	 */
+
+	addiu	sp, sp, -XCPTCONTEXT_SIZE
+
+	/* Save the EPC and STATUS in the register context array */
+
+	sw		k0, REG_EPC(sp)
+	sw		k1, REG_STATUS(sp)
+#endif
+
+	/* Save floating point registers */
+
+	mfhi	k0
+	sw		k0, REG_MFHI(sp)
+	mflo	k0
+	sw		k0, REG_MFLO(sp)
+
+	/* Save general purpose registers */
+	/* $1: at_reg, assembler temporary */
+
+	sw		$1, REG_AT(sp)
+
+	/* $2-$3 = v0-v1: Return value registers */
+
+	sw		v0, REG_V0(sp)
+	sw		v1, REG_V1(sp)
+
+	/* $4-$7 = a0-a3: Argument registers */
+
+	sw		a0, REG_A0(sp)
+	sw		a1, REG_A1(sp)
+	sw		a2, REG_A2(sp)
+	sw		a3, REG_A3(sp)
+
+	/* $8-$15 = t0-t7: Volatile registers */
+
+	sw		t0, REG_T0(sp)
+	sw		t1, REG_T1(sp)
+	sw		t2, REG_T2(sp)
+	sw		t3, REG_T3(sp)
+	sw		t4, REG_T4(sp)
+	sw		t5, REG_T5(sp)
+	sw		t6, REG_T6(sp)
+	sw		t7, REG_T7(sp)
+
+	/* $16-$23 = s0-s7: Static registers */
+
+	sw		s0, REG_S0(sp)
+	sw		s1, REG_S1(sp)
+	sw		s2, REG_S2(sp)
+	sw		s3, REG_S3(sp)
+	sw		s4, REG_S4(sp)
+	sw		s5, REG_S5(sp)
+	sw		s6, REG_S6(sp)
+	sw		s7, REG_S7(sp)
+
+	/* $24-25 = t8-t9: More Volatile registers */
+
+	sw		t8, REG_T8(sp)
+	sw		t9, REG_T9(sp)
+
+	/* $26-$27 = ko-k1: Reserved for use in exeption handers.  These do not need to be
+	 * saved.
+	 *
+	 * $28 = gp: Only needs to be saved under conditions where there are multiple, per-
+	 * thread values for the GP.
+	 */
+
+#ifdef MIPS32_SAVE_GP
+	sw		gp, REG_GP(sp)
+#endif
+
+	/* $30 = either s8 or fp:  Depends if a frame pointer is used or not */
+
+	sw		s8, REG_S8(sp)
+
+	/* $31 = ra: Return address */
+
+	sw		ra, REG_RA(sp)
+
+	/* $29 = sp:  The value of the stack pointer on return from the exception.  a0 is
+	 * used as a temporary
+	 */
+
+	addiu	\tmp, sp, XCPTCONTEXT_SIZE
+	sw		\tmp, REG_SP(sp)
+	.endm
+
+/********************************************************************************************
+ * Name: EXCPT_EPILOGUE
+ *
+ * Description:
+ *   Provides the "epilogue" logic that should appear at the end of every exception handler.
+ *
+ * On input:
+ *   regs - points to the register save structure.  NOTE:  This *may not* be an address
+ *          lying in a stack!  It might be an address in a TCB!
+ *   Interrupts are disabled (via 'di')
+ *
+ * On completion:
+ *   All registers restored
+ *	 eret is executed to return from the exception
+ *
+ ********************************************************************************************/
+
+	.macro	EXCPT_EPILOGUE, regs
+	.set	noat
+
+	/* Since interrupts are disabled via di can now use k0 and k1 again.  Use k1 as the
+	 * pointer to the register save array.
+	 */
+
+	move	k1, \regs
+
+	/* Restore the floating point register state */
+
+	lw		k0, REG_MFLO(k1)
+	mtlo	k0
+	lw		k0, REG_MFHI(k1)
+	mthi	k0
+
+	/* Restore general purpose registers */
+	/* $1: at_reg, assembler temporary */
+
+	lw		$1, REG_AT(k1)
+
+	/* $2-$3 = v0-v1: Return value registers */
+
+	lw		v0, REG_V0(k1)
+	lw		v1, REG_V1(k1)
+
+	/* $4-$7 = a0-a3: Argument registers */
+
+	lw		a0, REG_A0(k1)
+	lw		a1, REG_A1(k1)
+	lw		a2, REG_A2(k1)
+	lw		a3, REG_A3(k1)
+
+	/* $8-$15 = t0-t7: Volatile registers */
+
+	lw		t0, REG_T0(k1)
+	lw		t1, REG_T1(k1)
+	lw		t2, REG_T2(k1)
+	lw		t3, REG_T3(k1)
+	lw		t4, REG_T4(k1)
+	lw		t5, REG_T5(k1)
+	lw		t6, REG_T6(k1)
+	lw		t7, REG_T7(k1)
+
+	/* $16-$23 = s0-s7: Static registers */
+
+	lw		s0, REG_S0(k1)
+	lw		s1, REG_S1(k1)
+	lw		s2, REG_S2(k1)
+	lw		s3, REG_S3(k1)
+	lw		s4, REG_S4(k1)
+	lw		s5, REG_S5(k1)
+	lw		s6, REG_S6(k1)
+	lw		s7, REG_S7(k1)
+
+	/* $24-25 = t8-t9: More Volatile registers */
+
+	lw		t8, REG_T8(k1)
+	lw		t9, REG_T9(k1)
+
+	/* $26-$27 = ko-k1: Reserved for use in exeption handers.  These do not need to be
+	 * saved.
+	 *
+	 * $28 = gp: Only needs to be saved under conditions where there are multiple, per-
+	 * thread values for the GP.
+	 */
+
+#ifdef MIPS32_SAVE_GP
+	lw		gp, REG_GP(k1)
+#endif
+
+	/* $29 = sp: Stack pointer */
+
+	lw		sp, REG_SP(k1)
+
+	/* $30 = either s8 or fp:  Depends if a frame pointer is used or not */
+
+	lw		s8, REG_S8(k1)
+
+	/* $31 = ra: Return address */
+
+	lw		ra, REG_RA(k1)
+
+	/* Finally, restore CP status and the EPC */
+
+	lw		k0, REG_STATUS(k1)
+	lw		k1, REG_EPC(k1)
+	mtc0	k0, MIPS32_CP0_STATUS
+	ehb
+	mtc0 	k1, MIPS32_CP0_EPC
+	eret
+	nop
+	.endm
+
+/********************************************************************************************
+ * Name: USE_INTSTACK
+ *
+ * Description:
+ *   Switch to the interrupt stack (if enabled in the configuration).
+ *
+ * On Entry:
+ *   sp - Current value of the user stack pointer
+ *   tmp1, tmp2, and tmp3 are registers that can be used temporarily.
+ *   All interrupts should still be disabled.
+ *
+ * At completion:
+ *   If the nesting level is 0, then (1) the user stack pointer is saved at the base of the
+ *   interrupt stack and sp points to the interrupt stack.
+ *   The values of tmp1, tmp2, tmp3, and sp have been altered
+ *
+ ********************************************************************************************/
+
+	.macro	USE_INTSTACK, tmp1, tmp2, tmp3
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+
+	/* Check the nesting level.  If there are no nested interrupts, then we can
+	 * claim the interrupt stack.
+	 */
+
+	la		\tmp1, g_nestlevel
+	lw		\tmp2, (\tmp1)
+	bne		1f
+	nop
+#endif
+
+	/* Use the interrupt stack, pushing the user stack pointer onto the interrupt
+	 * stack first.
+	 */
+
+	la		\tmp3, g_intstackbase
+	lw		\tmp, (\tmp3)
+	sw		sp, (\tmp3)
+	move	sp, \tmp3
+
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+1:
+	/* Increment the interrupt nesting level */
+
+	addiu	\tmp2, \tmp2, 1
+	sw		\tmp2, 0(\tmp1)
+#endif
+#endif
+	.endm
+
+/********************************************************************************************
+ * Name: RESTORE_STACK
+ *
+ * Description:
+ *   Restore the user stack.  Not really.. actually only decrements the nesting level.  We
+ *   always get the new stack pointer for the register save array.
+ *
+ * On Entry:
+ *   tmp1 and tmp2 are registers that can be used temporarily.
+ *   All interrupts must be disabled.
+ *
+ * At completion:
+ *   Current nesting level is decremented
+ *   The values of tmp1 and  tmp2 have been altered
+ *
+ ********************************************************************************************/
+
+	.macro		RESTORE_STACK, tmp1, tmp2
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+
+	/* Decrement the nesting level */
+
+	la		\tmp1, g_nestlevel
+	lw		\tmp2, (\tmp1)
+	addiu	\tmp2, \tmp2, -1
+	sw		\tmp2, 0(\tmp1)
+
+#endif
+#endif
+	.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_EXCPTMACROS_H */
diff --git a/nuttx/arch/mips/src/pic32mz/pic32mz-head.S b/nuttx/arch/mips/src/pic32mz/pic32mz-head.S
new file mode 100644
index 000000000..1e1ea244b
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mz/pic32mz-head.S
@@ -0,0 +1,758 @@
+/****************************************************************************
+ * arch/mips/src/pic32mz/pic32mz-head.S
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/mips32/registers.h>
+#include <arch/pic32mz/cp0.h>
+
+#include "pic32mz-config.h"
+// REVISIT
+//#include "pic32mz-bmx.h"
+#include "pic32mz-excptmacros.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+#ifdef CONFIG_PIC32MZ_MVEC0
+#  error "Multi-vectors not supported"
+#  ifndef CONFIG_PIC32MZ_EBASE
+#    error "EBASE address provided"  /* Should come from the linker script */
+#  endif
+#  ifndef CONFIG_PIC32MZ_VECTORSPACING
+#    error "No vector spacing provided"
+#  endif
+#endif
+
+/* Linker memory organization ***********************************************/
+/* Data memory is organized as follows:
+ *
+ * 1) Possible space reserved for debug data
+ * 2) Ram functions: (.data):
+ *    Start:   _sramfunc
+ *    End(+1): _eramfunc
+ * 3) Initialized data (.data):
+ *    Start:   _sdata
+ *    End(+1): _edata
+ * 4) Uninitialized data (.bss):
+ *    Start:   _sbss
+ *    End(+1): _ebss
+ *
+ * The following are placed outside of the "normal" memory segments -- mostly
+ * so that they do not have to be cleared on power up.
+ *
+ * 5) Idle thread stack:
+ *    Start:   _ebss
+ *    End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE
+ * 6) Optional interrupt stack
+ *    Start:   _ebss+CONFIG_IDLETHREAD_STACKSIZE
+ *    End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
+ * 6a) Heap (without interupt stack)
+ *    Start:   _ebss+CONFIG_IDLETHREAD_STACKSIZE
+ *    End(+1): to the end of memory
+ * 6b) Heap (with interupt stack)
+ *    Start:   _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
+ *    End(+1): to the end of memory
+ */
+
+#define PIC32MZ_STACK_BASE      _ebss
+#define PIC32MZ_STACK_TOP       _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#  define PIC32MZ_INTSTACK_BASE PIC32MZ_STACK_TOP
+#  define PIC32MZ_INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~3)
+#  define PIC32MZ_INTSTACK_TOP  PIC32MZ_STACK_TOP+PIC32MZ_INTSTACK_SIZE
+#  define PIC32MZ_HEAP_BASE     PIC32MZ_INTSTACK_TOP
+#else
+#  define PIC32MZ_HEAP_BASE     PIC32MZ_STACK_TOP
+#endif
+
+/****************************************************************************
+ * Global Symbols
+ ****************************************************************************/
+
+	.file	"pic32mz-head.S"
+
+	/* Exported symbols */
+
+	.globl	__reset
+	.global __start
+	.global halt
+	.global	devconfig
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	.global g_intstackbase
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+	.global	g_nestlevel
+#endif
+#endif
+	.global	g_idle_topstack
+
+	/* Imported symbols */
+
+	.global os_start
+	.global	pic32mz_exception
+	.global pic32mz_decodeirq
+#ifdef CONFIG_PIC32MZ_NMIHANDLER
+	.global	pic32mz_donmi
+#endif
+
+	/* This file contains 32-bit assembly code */
+
+	.set nomips16
+
+/****************************************************************************
+ * Name: __reset
+ *
+ * Description:
+ *   Reset entry point.  This function is positioned at the beginning of
+ *   the boot FLASH by the linker in KSEG1.  Simply jumps to the __start
+ *   logic in KSEG0 (also in the boot FLASH).
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Does not return
+ *
+ ****************************************************************************/
+
+	.section .reset, "ax", @progbits
+	.align	2
+	.set	noreorder
+	.set	micromips
+	.ent	__reset
+
+__reset:
+	.word 0x10000003	/* MIPS32:    branch forward 0x10 bytes from here  */
+						/* MicroMIPS: ADDI32 $0, $0, 0x0007 (nop)          */
+						/* DO NOT change the relative branch               */
+	.word 0x00000000	/* NOP */
+
+	/* If se get here then we are in microMIPS mode.  That is because the
+	 * preceding instructions are all NOP in that case and we fall through
+	 * to here.  Otherwise, we branched to __reset_switch_isa
+	 */
+
+	.set    micromips
+
+__reset_micromips:
+	la		k0, __start	/* Just jump to the startup initialization code */
+	jr		k0
+	nop
+
+	/* Device not in proper ISA mode */
+
+	.align 2
+	.set nomicromips
+
+__reset_halt:
+	b		__reset_halt
+	nop
+
+	.end	__reset
+
+/****************************************************************************
+ * Name: _gen_exception
+ *
+ * Description:
+ *   General Exception Vector Handler.  Jumps to _exception_handler. This
+ *   vector will be positioned at 0xbfc00180 by the linker script. NOTE:
+ *   If we set the BEV bit in the status register so all interrupt vectors
+ *   should go through the _bev_exception.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Does not return
+ *
+ ****************************************************************************/
+
+	.section .gen_excpt,"ax",@progbits
+	.set	noreorder
+	.set	micromips
+	.ent	_gen_exception
+
+_gen_exception:
+	la		k0, _exception_handler
+	jr		k0
+	nop
+	.end _gen_exception
+
+/****************************************************************************
+ * Name: _ebase_exception
+ *
+ * Description:
+ *   Interrupt Exception Vector Handler.  Jumps to _int_handler.  This
+ *   vector will be positioned at 0xbfc00200 by the linker script. NOTE:
+ *   Several vectors (JTAG, TLB fills, etc.) could come through this vector.
+ *   However, this is intended to serve vectors in PIC32MZ single vector
+ *   mode:  The EBASE register will be set to 0xbfc00000 and the vector
+ *   should go to EBASE + 0x0200.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Does not return
+ *
+ ****************************************************************************/
+
+	.section .ebase_excpt,"ax",@progbits
+	.set	noreorder
+	.set	micromips
+	.ent	_ebase_exception
+
+_ebase_exception:
+	la		k0, _int_handler
+	jr		k0
+	nop
+	.end _ebase_exception
+
+/****************************************************************************
+ * Name: _bev_exception
+ *
+ * Description:
+ *   Boot Exception Vector Handler.  Jumps to _exception_handler.  This
+ *   vector will be positioned at 0xbfc00380 by the linker script.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Does not return
+ *
+ ****************************************************************************/
+
+	.section .bev_excpt,"ax",@progbits
+	.set	noreorder
+	.set	micromips
+	.ent	_bev_exception
+
+_bev_exception:
+	la		k0, _exception_handler
+	jr		k0
+	nop
+	.end _bev_exception
+
+/****************************************************************************
+ * Name: _int_exception
+ *
+ * Description:
+ *   Interrupt Exception Vector Handler.  Jumps to _int_handler.  This
+ *   vector will be positioned at 0xbfc00400 by the linker script.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Does not return
+ *
+ ****************************************************************************/
+
+	.section .int_excpt,"ax",@progbits
+	.set	noreorder
+	.set	micromips
+	.ent	_int_exception
+
+_int_exception:
+	la		k0, _int_handler
+	jr		k0
+	nop
+	.end _int_exception
+
+/****************************************************************************
+ * Name: __start
+ *
+ * Description:
+ *   This is the KSEG0 startup code.  It receives control from the reset
+ *   entry point.  This lgic This prepares the processor to execute
+ *   C code, performs some very low-level initialization, then starts NuttX
+ *   (via __start_nuttx
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Does not return
+ *
+ ****************************************************************************/
+
+	.section .start, "ax", @progbits
+	.set	noreorder
+	.set	micromips
+	.ent	__start
+
+__start:
+
+	/* If this function was entered because of an NMI, then turn processing
+	 * over to the NMI handler.
+	 */
+
+#ifdef CONFIG_PIC32MZ_NMIHANDLER
+	mfc0	k0, $12				/* Load CP0 status register */
+	ext		k0, k0, 19, 1		/* Extract NMI bit */
+	beqz	k0, .Lnotnmi
+	nop
+	la		k0, _nmi_handler
+	jr		k0
+	nop
+
+	/* This is not an NMI */
+
+.Lnotnmi:
+#endif
+
+	/* Initialize the stack pointer */
+
+	la		sp, PIC32MZ_STACK_TOP
+
+	/* Initialize the globl pointer (gp).  _gp is initialized by the linker
+	 * script to point to the "middle" of the small variables region.
+	 */
+
+	la		gp, _gp
+
+	/* Initialize Global Pointer in Shadow Set.  The SRSCtl PSS field must
+	 * be set to the shadow set in which to initialize the global pointer.
+	 * Since we only have a single shadow set, we will initialize
+	 * SRSCtl PSS to SRSCtl HSS.  We then write the global pointer to the
+	 * previous shadow set to ensure that on interrupt, the global pointer
+	 * has been initialized.
+	 */
+
+	mfc0	t1, PIC32MZ_CP0_SRSCTL	/* Read SRSCtl register */
+	add		t3, t1, zero			/* Save off current SRSCtl */
+	ext		t2, t1, 26, 4			/* to obtain HSS field */
+	ins		t1, t2, 6, 4			/* Put HSS field */
+	mtc0	t1, PIC32MZ_CP0_SRSCTL	/* into SRSCtl PSS  */
+	wrpgpr	gp, gp					/* Set global pointer in PSS */
+	mtc0	t3, PIC32MZ_CP0_SRSCTL	/* Restore SRSCtl */
+
+	/* Clear uninitialized data sections */
+
+	la		t0, _sbss
+	la		t1, _ebss
+	b		.Lbsscheck
+	nop
+
+.Lbssloop:	
+	sw		zero, 0x0(t0)
+	sw		zero, 0x4(t0)
+	sw		zero, 0x8(t0)
+	sw		zero, 0xc(t0)
+	addu	t0, 16
+
+.Lbsscheck:
+	bltu	t0, t1, .Lbssloop
+	nop
+
+	/* Copy initialized data from program flash to data memory */
+
+	la		t0, _data_loaddr
+	la		t1, _sdata
+	la		t2, _edata
+	b		.Ldatacheck
+	nop
+
+.Ldataloop:	
+	lw		t3, (t0)
+	sw		t3, (t1)
+	addu	t0, 4
+	addu	t1, 4
+
+.Ldatacheck:
+	bltu	t1, t2, .Ldataloop
+	nop
+
+	/* If there are no RAM functions, skip the next two sections --
+	 * copying RAM functions from program flash to data memory and
+	 * initializing bus matrix registers.
+	 */
+
+#ifdef CONFIG_ARCH_RAMFUNCS
+	la		t1, _ramfunc_sizeof
+	beqz	t1, .Lnoramfuncs
+	nop
+
+	/* Copy RAM functions from program flash to data memory */
+
+	la		t0, _ramfunc_loadaddr
+	la		t1, _sramfunc
+	la		t2, _eramfunc
+
+.Lramfuncloop:
+	lw		t3,(t0)
+	sw		t3,(t1)
+	addu	t0,4
+	addu	t1,4
+
+	bltu	t1, t2, .Lramfuncloop
+	nop
+
+	/* Initialize bus matrix registers if RAM functions exist in the
+	 * application
+	 */
+
+	la		t1, _bmxdkpba_address
+	la		t2, PIC32MZ_BMX_DKPBA
+	sw		t1, 0(t2)
+	la		t1, _bmxdudba_address
+	la		t2, PIC32MZ_BMX_DUDBA
+	sw		t1, 0(t2)
+	la		t1, _bmxdupba_address
+	la		t2, PIC32MZ_BMX_DUPBA
+	sw		t1, 0(t2)
+.Lnoramfuncs:
+#endif
+
+	/* Initialize CP0 Count register */
+
+	mtc0	zero, PIC32MZ_CP0_COUNT
+
+	/* Initialize Compare register */
+
+	li		t2, -1
+	mtc0	t2, PIC32MZ_CP0_COMPARE
+
+	/* Initialize EBase register */
+
+#ifdef CONFIG_PIC32MZ_MVEC
+	la		t1, CONFIG_PIC32MZ_EBASE
+	mtc0	t1, PIC32MZ_CP0_EBASE
+
+	/* Initialize IntCtl register */
+
+	li		t1, CONFIG_PIC32MZ_VECTORSPACING
+	li		t2, 0
+	ins		t2, t1, CP0_INTCTL_VS_SHIFT, 5
+	mtc0	t2, PIC32MZ_CP0_INTCTL
+#endif
+
+	/* Initialize CAUSE registers
+	 * - Enable counting of Count register (DC = 0)
+	 * - Use special exception vector (IV = 1)
+	 * - Clear pending software interrupts (IP1:IP0 = 0)
+	 */
+
+	li		t1, CP0_CAUSE_IV
+	mtc0	t1, PIC32MZ_CP0_CAUSE
+
+	/* Initialize STATUS register
+	 * - Access to Coprocessor 0 not allowed in user mode (CU0 = 0)
+	 * - User mode uses configured endianness (RE = 0)
+	 * - Preserve Bootstrap Exception vectors (BEV)
+	 * - Preserve soft reset (SR) and non-maskable interrupt (NMI)
+	 * - CorExtend enabled based on whether CorExtend User Defined
+	 *   Instructions have been implemented (CEE = Config(UDI))
+	 * - Disable any pending interrups (IM7..IM2 = 0, IM1..IM0 = 0)
+	 * - Disable hardware interrupts (IPL7:IPL2 = 0)
+	 * - Base mode is Kernel mode (UM = 0)
+	 * - Error level is normal (ERL = 0)
+	 * - Exception level is normal (EXL = 0)
+	 * - Interrupts are disabled (IE = 0)
+	 */
+
+	mfc0	t0, PIC32MZ_CP0_CONFIG
+	ext		t1, t0, 22,1			/* Extract UDI from Config register */
+	sll		t1, t1, 17				/* Move UDI to Status.CEE location */
+	mfc0	t0, PIC32MZ_CP0_STATUS
+	and		t0, t0, 0x00580000		/* Preserve SR, NMI, and BEV */
+	or		t0, t1, t0				/* Include Status.CEE (from UDI) */
+	mtc0	t0, PIC32MZ_CP0_STATUS
+
+	/* Initialize Status BEV for normal exception vectors */
+
+	mfc0	t0, PIC32MZ_CP0_STATUS
+	and		t0, t0, ~CP0_STATUS_BEV	/* Clear BEV */
+	mtc0	t0, PIC32MZ_CP0_STATUS
+
+	/* Start NuttX. We do this via a thunk in the text section so that
+	 * a normal jump and link can be used, enabling the startup code
+	 * to work properly whether main is written in MIPS16 or MIPS32
+	 * code. I.e., the linker will correctly adjust the JAL to JALX if
+	 * necessary
+	 */
+
+	la		t0, __start_nuttx
+	jr		t0
+	nop
+	.end __start
+
+/****************************************************************************
+ * Name: _exception_handler
+ *
+ * Description:
+ *   BEV/General exception handler.  Calls pic32mz_exception()
+ *
+ ****************************************************************************/
+
+	.section .bev_handler, "ax", @progbits
+	.set	noreorder
+	.set	micromips
+	.ent	_exception_handler
+
+_exception_handler:
+	EXCPT_PROLOGUE t0				/* Save registers on stack, enable nested interrupts */
+	move	a0, sp					/* Pass register save structure as the parameter 1 */
+	USE_INTSTACK t0, t1, t2			/* Switch to the interrupt stack */
+	la		t0, pic32mz_exception		/* Call pic32mz_exception(regs) */
+	jalr	ra, t0
+	nop
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+	di								/* Prohibit nested interrupts from here */
+#endif
+	RESTORE_STACK t0, t1			/* Undo the operations of USE_STACK */
+	EXCPT_EPILOGUE v0				/* Return to the context returned by pic32mz_exception() */
+	.end	_exception_handler
+
+/****************************************************************************
+ * Name: _int_handler
+ *
+ * Description:
+ *   Interrupt exception handler.  Calls up_decodeirq()
+ *
+ ****************************************************************************/
+
+	.section .int_handler, "ax", @progbits
+	.set	noreorder
+	.set	micromips
+	.ent	_int_handler
+
+_int_handler:
+	EXCPT_PROLOGUE t0				/* Save registers on stack, enable nested interrupts */
+	move	a0, sp					/* Pass register save structure as the parameter 1 */
+	USE_INTSTACK t0, t1, t2			/* Switch to the interrupt stack */
+	la		t0, pic32mz_decodeirq	/* Call pic32mz_decodeirq(regs) */
+	jalr	ra, t0
+	nop
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+	di								/* Prohibit nested interrupts from here */
+#endif
+	RESTORE_STACK t0, t1			/* Undo the operations of USE_STACK */
+	EXCPT_EPILOGUE v0				/* Return to the context returned by pic32mz_decodeirq() */
+	.end	_int_handler
+
+/****************************************************************************
+ * Name: _nmi_handler
+ *
+ * Description:
+ *   NMI exception handler.  Calls pic32mz_donmi
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PIC32MZ_NMIHANDLER
+	.section .nmi_handler, "ax", @progbits
+	.set	noreorder
+	.set	micromips
+	.ent	_nmi_handler
+
+_nmi_handler:
+	EXCPT_PROLOGUE t0				/* Save registers on stack, enable nested interrupts */
+	move	a0, sp					/* Pass register save structure as the parameter 1 */
+	USE_INTSTACK t0, t1, t2			/* Switch to the interrupt stack */
+	la		t0, pic32mz_donmi		/* Call up_donmi(regs) */
+	jalr	ra, t0
+	nop
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+	di								/* Prohibit nested interrupts from here */
+#endif
+	RESTORE_STACK t0, t1			/* Undo the operations of USE_STACK */
+	EXCPT_EPILOGUE v0				/* Return to the context returned by pic32mz_donmi() */
+	.end	_nmi_handler
+#endif
+
+/****************************************************************************
+ * Name: __start_nuttx
+ *
+ * Description:
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Does not return
+ *
+ ****************************************************************************/
+
+	.text
+	.set	micromips
+	.ent	__start_nuttx
+
+__start_nuttx:
+	/* Perform low level initialization */
+
+	la		t0, pic32mz_lowinit
+	jalr    ra, t0
+	nop
+
+	/* Call os_start */
+
+	la		t0, os_start
+	jalr	ra, t0
+	nop
+
+	/* Just in case main returns, go into an infinite loop */
+
+halt:
+1:
+	b	 1b
+	nop
+	.end __start_nuttx
+
+/****************************************************************************
+ * Device Configuration
+ ****************************************************************************/
+
+	.section .devcfg, "a"
+	.type	devconfig, object
+devconfig:
+devconfig3:
+#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
+
+	.long	CONFIG_PIC32MZ_USERID  << DEVCFG3_USERID_SHIFT | \
+			CONFIG_PIC32MZ_PMDL1WAY << 28 | CONFIG_PIC32MZ_IOL1WAY << 29 | \
+			CONFIG_PIC32MZ_USBIDO  << 30 | CONFIG_PIC32MZ_VBUSIO  << 31 | \
+			DEVCFG3_UNUSED
+
+#elif defined(CHIP_PIC32MZ3) || defined(CHIP_PIC32MZ4)
+
+	.long	CONFIG_PIC32MZ_USERID  << DEVCFG3_USERID_SHIFT | \
+			DEVCFG3_UNUSED
+
+#elif defined(CHIP_PIC32MZ5) || defined(CHIP_PIC32MZ6) || defined(CHIP_PIC32MZ7)
+
+	.long	CONFIG_PIC32MZ_USERID  << DEVCFG3_USERID_SHIFT | \
+			CONFIG_PIC32MZ_SRSSEL  << DEVCFG3_FSRSSEL_SHIFT | \
+			CONFIG_PIC32MZ_FMIIEN  << 24 | CONFIG_PIC32MZ_FETHIO  << 25 | \
+			CONFIG_PIC32MZ_FCANIO  << 26 | CONFIG_PIC32MZ_FSCM1IO << 29 | \
+			CONFIG_PIC32MZ_USBIDO  << 30 | CONFIG_PIC32MZ_VBUSIO  << 31 | \
+			DEVCFG3_UNUSED
+
+#endif
+
+devconfig2:
+	.long	CONFIG_PIC32MZ_PLLIDIV  | CONFIG_PIC32MZ_PLLMULT | \
+			CONFIG_PIC32MZ_UPLLIDIV | CONFIG_PIC32MZ_PLLODIV | \
+			CONFIG_PIC32MZ_FUPLLEN << 15 | DEVCFG2_UNUSED
+
+devconfig1:
+#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
+
+	.long	CONFIG_PIC32MZ_FNOSC    | CONFIG_PIC32MZ_FSOSCEN  | \
+			CONFIG_PIC32MZ_IESO     | CONFIG_PIC32MZ_POSCMOD  | \
+			CONFIG_PIC32MZ_OSCOUT << 10 | \
+			CONFIG_PIC32MZ_PBDIV    | CONFIG_PIC32MZ_FCKSM    | \
+			DEVCFG1_WINDIS          | CONFIG_PIC32MZ_WDENABLE | \
+			DEVCFG1_FWDTWINSZ_75    | DEVCFG1_UNUSED
+
+#else
+
+	.long	CONFIG_PIC32MZ_FNOSC    | CONFIG_PIC32MZ_FSOSCEN | \
+			CONFIG_PIC32MZ_IESO     | CONFIG_PIC32MZ_POSCMOD | \
+			CONFIG_PIC32MZ_OSCOUT << 10 | \
+			CONFIG_PIC32MZ_PBDIV    | CONFIG_PIC32MZ_FCKSM   | \
+			CONFIG_PIC32MZ_WDENABLE | DEVCFG1_UNUSED
+
+#endif
+
+devconfig0:
+#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
+
+	.long	CONFIG_PIC32MZ_DEBUGGER    << DEVCFG0_DEBUG_SHIFT | \
+			DEVCFG0_JTAGEN | \
+			CONFIG_PIC32MZ_ICESEL      << DEVCFG0_ICESEL_SHIFT | \
+			CONFIG_PIC32MZ_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \
+			CONFIG_PIC32MZ_BOOTFLASHWP << 24 | \
+			CONFIG_PIC32MZ_CODEWP      << 28 | \
+			DEVCFG0_UNUSED
+
+#else
+
+	.long	CONFIG_PIC32MZ_DEBUGGER    << DEVCFG0_DEBUG_SHIFT | \
+			CONFIG_PIC32MZ_ICESEL      << 3 | \
+			CONFIG_PIC32MZ_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \
+			CONFIG_PIC32MZ_BOOTFLASHWP << 24 | \
+			CONFIG_PIC32MZ_CODEWP      << 28 | \
+			DEVCFG0_UNUSED
+
+#endif
+	.size	devconfig, .-devconfig
+
+/****************************************************************************
+ * Global Data
+ ****************************************************************************/
+
+/* Interrupt stack variables */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+
+/* g_instackbase is a pointer to the final, aligned word of the interrupt
+ * stack.
+ */
+
+	.sdata
+	.type	g_intstackbase, object
+g_intstackbase:
+	.long	PIC32MZ_INTSTACK_TOP-4
+	.size	g_intstackbase, .-g_intstackbase
+
+/* g_nextlevel is the exception nesting level... the interrupt stack is not
+ * available to nested exceptions.
+ */
+
+#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
+	.sbss
+	.type	g_nestlevel, object
+g_nestlevel:
+	.skip		4
+#endif
+#endif
+
+/* This global variable is unsigned int g_idle_topstack and is exported here only
+ * because of its coupling to idle thread stack.
+ */
+
+	.sdata
+	.type	g_idle_topstack, object
+g_idle_topstack:
+	.long	PIC32MZ_HEAP_BASE
+	.size	g_idle_topstack, .-g_idle_topstack