Add more register definitions

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@203 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 268 insertions, 138 deletions

diff --git a/nuttx/arch/arm/src/lpc214x/chip.h b/nuttx/arch/arm/src/lpc214x/chip.h
index 3977a3833..51ae83708 100644
--- a/nuttx/arch/arm/src/lpc214x/chip.h
+++ b/nuttx/arch/arm/src/lpc214x/chip.h
@@ -54,62 +54,131 @@
 #define LPC214X_APB_BASE                0xe0000000
 #define LPC214X_AHB_BASE                0xf0000000
 
-/* Interrupts **************************************************************************************/
-
 /* Peripheral Registers ****************************************************************************/
 
 /* Register block base addresses */
 
-#define LPC214X_UART0_BASE              0xe000c000  /* UART0 Base Address */
-#define LPC214X_UART1_BASE              0xe0010000  /* UART1 Base Address */
-#define LPC214X_PINSEL_BASE             0xe002c000  /* Pin funtion select registers */
-#define LPC214X_AD0_BASE                0xe0034000  /* Analog to Digital Converter 0 Base Address*/
-#define LPC214X_AD1_BASE                0xe0060000  /* Analog to Digital Converter 1 Base Address */
-#define LPC214X_MAM_BASE                0xe01fc000  /* Memory Accelerator Module (MAM) Base Address */
-#define LPC214X_MEMMAP                  0xe01fc040  /* Memory Mapping Control */
-#define LPC214X_PLL_BASE                0xe01fc080  /* Phase Locked Loop (PLL) Base Address */
-#define LPC214X_VPBDIV                  0xe01fc100  /* VPBDIV Address */
-#define LPC214X_EMC_BASE                0xffe00000  /* External Memory Controller (EMC) Base Address */
+#define LPC214X_WD_BASE                 0xe0000000  /* Watchdog base address */
+#define LPC214X_TMR0_BASE               0xe0004000  /* Timer 0 base address*/
+#define LPC214X_TMR1_BASE               0xe0008000  /* Timer 1 base address */
+#define LPC214X_UART0_BASE              0xe000c000  /* UART0 base address */
+#define LPC214X_UART1_BASE              0xe0010000  /* UART1 base address */
+#define LPC214X_PWM_BASE                0xe0014000  /* Pulse width modulator (PWM) base address */
+#define LPC214X_I2C_BASE                0xe001C000  /* I2C base address */
+#define LPC214X_SPI0_BASE               0xe0020000  /* Serial Peripheral Interface 0 (SPI0) base */
+#define LPC214X_RTC_BASE                0xe0024000  /* Real Time Clock (RTC) base address */
+#define LPC214X_GPIO0_BASE              0xe0028000  /* General Purpose I/O (GPIO) 0 base address */
+#define LPC214X_GPIO1_BASE              0xe0028010  /* General Purpose I/O (GPIO) 0 base address */
+#define LPC214X_PINSEL_BASE             0xe002c000  /* Pin function select registers */
+#define LPC214X_SPI1_BASE               0xe0030000  /* Serial Peripheral Interface 1 (SPI1) base */
+#define LPC214X_AD0_BASE                0xe0034000  /* Analog to Digital Converter 0 base address*/
+#define LPC214X_AD1_BASE                0xe0060000  /* Analog to Digital Converter 1 base address */
+
+#define LPC214X_SCB_BASE                0xe01fc000  /* System Control Block (SBC) base address */
+#define   LPC214X_MAM_BASE              0xe01fc000  /* Memory Accelerator Module (MAM) base address */
+#define   LPC214X_MEMMAP                0xe01fc040  /* Memory Mapping Control */
+#define   LPC214X_PLL_BASE              0xe01fc080  /* Phase Locked Loop (PLL) base address */
+#define   LPC214X_PCON_BASE             0xe01fc0c0  /* Power Control (PCON) base address */
+#define   LPC214X_VPBDIV                0xe01fc100  /* VPBDIV Address */
+#define   LPC214X_EXT_BASE              0xe01fc140  /* External Interrupt base address */       
+
+#define LPC214X_EMC_BASE                0xffe00000  /* External Memory Controller (EMC) base address */
 #define LPC214X_VIC_BASE                0xfffff000  /* Vectored Interrupt Controller (VIC) Base */
 
+/* Watchdog Register Offsets */
+
+#define LPC214X_WD_MOD_OFFSET           0x00 /* Watchdog Mode Register */
+#define LPC214X_WD_TC_OFFSET            0x04 /* Watchdog Time Constant Register */
+#define LPC214X_WD_FEED_OFFSET          0x08 /* Watchdog Feed Register */
+#define LPC214X_WD_TV_OFFSET            0x0C /* Watchdog Time Value Register */
+
+/* Timer 0 register offsets */
+
+#define LPC214X_TMR_IR_OFFSET           0x00   /* Interrupt Register */
+#define LPC214X_TMR_TCR_OFFSET          0x04   /* Timer Control Register */
+#define LPC214X_TMR_TC_OFFSET           0x08   /* Timer Counter */
+#define LPC214X_TMR_PR_OFFSET           0x0c   /* Prescale Register */
+#define LPC214X_TMR_PC_OFFSET           0x10   /* Prescale Counter Register */
+#define LPC214X_TMR_MCR_OFFSET          0x14   /* Match Control Register */
+#define LPC214X_TMR_MR0_OFFSET          0x18   /* Match Register 0 */
+#define LPC214X_TMR_MR1_OFFSET          0x1c   /* Match Register 1 */
+#define LPC214X_TMR_MR2_OFFSET          0x20   /* Match Register 2 */
+#define LPC214X_TMR_MR3_OFFSET          0x24   /* Match Register 3 */
+#define LPC214X_TMR_CCR_OFFSET          0x28   /* Capture Control Register */
+#define LPC214X_TMR_CR0_OFFSET          0x2c   /* Capture Register 0 */
+#define LPC214X_TMR_CR1_OFFSET          0x30   /* Capture Register 1 */
+#define LPC214X_TMR_CR2_OFFSET          0x34   /* Capture Register 2 */
+#define LPC214X_TMR_CR3_OFFSET          0x38   /* Capture Register 3 */
+#define LPC214X_TMR_EMR_OFFSET          0x3c   /* External Match Register */
+
+#define LPC214X_TMR_CTCR_OFFSET         0x70   /* Count Control Register */
+
 /* UART0/1 Register Offsets */
 
-#define LPC214X_RBR_OFFSET              0x00        /* R: Receive Buffer Register (DLAB=0) */
-#define LPC214X_THR_OFFSET              0x00        /* W: Transmit Holding Register (DLAB=0) */
-#define LPC214X_DLL_OFFSET              0x00        /* W: Divisor Latch Register (LSB) */
-#define LPC214X_IER_OFFSET              0x04        /* W: Interrupt Enable Register (DLAB=0) */
-#define LPC214X_DLM_OFFSET              0x04        /* R/W: Divisor Latch Register (MSB, DLAB=1) */
-#define LPC214X_IIR_OFFSET              0x08        /* R: Interrupt ID Register (DLAB=) */
-#define LPC214X_FCR_OFFSET              0x08        /* W: FIFO Control Register */
-#define LPC214X_LCR_OFFSET              0x0c        /* R/W: Line Control Register */
-#define LPC214X_MCR_OFFSET              0x10        /* R/W: Modem Control REgister (2146/6/8 UART1 Only) */
-#define LPC214X_LSR_OFFSET              0x14        /* R: Scratch Pad Register */
-#define LPC214X_MSR_OFFSET              0x18        /* R/W: MODEM Status Register (2146/6/8 UART1 Only) */
-#define LPC214X_SCR_OFFSET              0x1c        /* R/W: Line Status Register */
-#define LPC214X_ACR_OFFSET              0x20        /* R/W: Autobaud Control Register */
-#define LPC214X_FDR_OFFSET              0x28        /* R/W: Fractional Divider Register */
-#define LPC214X_TER_OFFSET              0x30        /* R/W: Transmit Enable Register */
+#define LPC214X_UART_RBR_OFFSET         0x00   /* R: Receive Buffer Register (DLAB=0) */
+#define LPC214X_UART_THR_OFFSET         0x00   /* W: Transmit Holding Register (DLAB=0) */
+#define LPC214X_UART_DLL_OFFSET         0x00   /* W: Divisor Latch Register (LSB) */
+#define LPC214X_UART_IER_OFFSET         0x04   /* W: Interrupt Enable Register (DLAB=0) */
+#define LPC214X_UART_DLM_OFFSET         0x04   /* R/W: Divisor Latch Register (MSB, DLAB=1) */
+#define LPC214X_UART_IIR_OFFSET         0x08   /* R: Interrupt ID Register (DLAB=) */
+#define LPC214X_UART_FCR_OFFSET         0x08   /* W: FIFO Control Register */
+#define LPC214X_UART_LCR_OFFSET         0x0c   /* R/W: Line Control Register */
+#define LPC214X_UART_MCR_OFFSET         0x10   /* R/W: Modem Control REgister (2146/6/8 UART1 Only) */
+#define LPC214X_UART_LSR_OFFSET         0x14   /* R: Scratch Pad Register */
+#define LPC214X_UART_MSR_OFFSET         0x18   /* R/W: MODEM Status Register (2146/6/8 UART1 Only) */
+#define LPC214X_UART_SCR_OFFSET         0x1c   /* R/W: Line Status Register */
+#define LPC214X_UART_ACR_OFFSET         0x20   /* R/W: Autobaud Control Register */
+#define LPC214X_UART_FDR_OFFSET         0x28   /* R/W: Fractional Divider Register */
+#define LPC214X_UART_TER_OFFSET         0x30   /* R/W: Transmit Enable Register */
+
+/* PWM register offsets */
+
+#define LPC214X_PWM_IR_OFFSET           0x00   /* Interrupt Register */
+#define LPC214X_PWM_TCR_OFFSET          0x04   /* Timer Control Register */
+#define LPC214X_PWM_TC_OFFSET           0x08   /* Timer Counter */
+#define LPC214X_PWM_PR_OFFSET           0x0c   /* Prescale Register */
+#define LPC214X_PWM_PC_OFFSET           0x10   /* Prescale Counter Register */
+#define LPC214X_PWM_MCR_OFFSET          0x14   /* Match Control Register */
+#define LPC214X_PWM_MR0_OFFSET          0x18   /* Match Register 0 */
+#define LPC214X_PWM_MR1_OFFSET          0x1c   /* Match Register 1 */
+#define LPC214X_PWM_MR2_OFFSET          0x20   /* Match Register 2 */
+#define LPC214X_PWM_MR3_OFFSET          0x24   /* Match Register 3 */
+#define LPC214X_PWM_MR4_OFFSET          0x40   /* Match Register 4 */
+#define LPC214X_PWM_MR5_OFFSET          0x44   /* Match Register 5 */
+#define LPC214X_PWM_MR6_OFFSET          0x48   /* Match Register 6 */
+#define LPC214X_PWM_PCR_OFFSET          0x4c   /* Control Register */
+#define LPC214X_PWM_LER_OFFSET          0x50   /* Latch Enable Register */
+
+/* I2C register offsets */
+
+#define LPC214X_I2C_ONSET_OFFSET        0x00   /* Control Set Register */
+#define LPC214X_I2C_STAT_OFFSET         0x04   /* Status Register */
+#define LPC214X_I2C_DAT_OFFSET          0x08   /* Data Register */
+#define LPC214X_I2C_ADR_OFFSET          0x0c   /* Slave Address Register */
+#define LPC214X_I2C_SCLH_OFFSET         0x10   /* SCL Duty Cycle Register (high half word) */
+#define LPC214X_I2C_SCLL_OFFSET         0x14   /* SCL Duty Cycle Register (low half word) */
+#define LPC214X_I2C_ONCLR_OFFSET        0x18   /* Control Clear Register */
 
 /* Pin function select register offsets */
 
-#define LPC214X_PINSEL0_OFFSET          0x00        /* Pin function select register 0 */
-#define LPC214X_PINSEL1_OFFSET          0x04        /* Pin function select register 1 */
-#define LPC214X_PINSEL2_OFFSET          0x14        /* Pin function select register 2 */
+#define LPC214X_PINSEL0_OFFSET          0x00   /* Pin function select register 0 */
+#define LPC214X_PINSEL1_OFFSET          0x04   /* Pin function select register 1 */
+#define LPC214X_PINSEL2_OFFSET          0x14   /* Pin function select register 2 */
 
 /* Analog to Digital (AD) Converter registger offsets */
-#define LPC214X_AD_ADCR_OFFSET          0x00        /* A/D Control Register */
-#define LPC214X_AD_ADGDR_OFFSET         0x04        /* A/D Global Data Register (only one common registger!) */
-#define LPC214X_AD_ADGSR_OFFSET         0x08        /* A/D Global Start Register */
-#define LPC214X_AD_ADINTEN_OFFSET       0x0c        /* A/D Interrupt Enable Register */
-#define LPC214X_AD_ADDR0_OFFSET         0x10        /* A/D Chanel 0 Data Register */
-#define LPC214X_AD_ADDR1_OFFSET         0x14        /* A/D Chanel 0 Data Register */
-#define LPC214X_AD_ADDR2_OFFSET         0x18        /* A/D Chanel 0 Data Register */
-#define LPC214X_AD_ADDR3_OFFSET         0x1c        /* A/D Chanel 0 Data Register */
-#define LPC214X_AD_ADDR4_OFFSET         0x20        /* A/D Chanel 0 Data Register */
-#define LPC214X_AD_ADDR5_OFFSET         0x24        /* A/D Chanel 0 Data Register */
-#define LPC214X_AD_ADDR6_OFFSET         0x28        /* A/D Chanel 0 Data Register */
-#define LPC214X_AD_ADDR7_OFFSET         0x2c        /* A/D Chanel 0 Data Register */
-#define LPC214X_AD_ADSTAT_OFFSET        0x30        /* A/D Status Register */
+#define LPC214X_AD_ADCR_OFFSET          0x00   /* A/D Control Register */
+#define LPC214X_AD_ADGDR_OFFSET         0x04   /* A/D Global Data Register (only one common register!) */
+#define LPC214X_AD_ADGSR_OFFSET         0x08   /* A/D Global Start Register */
+#define LPC214X_AD_ADINTEN_OFFSET       0x0c   /* A/D Interrupt Enable Register */
+#define LPC214X_AD_ADDR0_OFFSET         0x10   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR1_OFFSET         0x14   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR2_OFFSET         0x18   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR3_OFFSET         0x1c   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR4_OFFSET         0x20   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR5_OFFSET         0x24   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR6_OFFSET         0x28   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR7_OFFSET         0x2c   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADSTAT_OFFSET        0x30   /* A/D Status Register */
 
 /* Pin function select registers (these are normally referenced as offsets) */
 
@@ -117,84 +186,145 @@
 #define LPC214X_PINSEL1                 (LPC214X_PINSEL_BASE + LPC214X_PINSEL1_OFFSET)
 #define LPC214X_PINSEL2                 (LPC214X_PINSEL_BASE + LPC214X_PINSEL2_OFFSET)
 
+/* SPI register offsets */
+
+#define LPC214X_SPI_CR0_OFFSET          0x00   /* Control Register 0 */
+#define LPC214X_SPI_CR1_OFFSET          0x04   /* Control Register 1 */
+#define LPC214X_SPI_DR_OFFSET           0x08   /* Data Register */
+#define LPC214X_SPI_SR_OFFSET           0x0c   /* Status Register */
+#define LPC214X_SPI_CPSR_OFFSET         0x10   /* Clock Pre-Scale Regisrer */
+#define LPC214X_SPI_IMSC_OFFSET         0x14   /* Interrupt Mask Set and Clear Register */
+#define LPC214X_SPI_RIS_OFFSET          0x18   /* Raw Interrupt Status Register */
+#define LPC214X_SPI_MIS_OFFSET          0x1c   /* Masked Interrupt Status Register */
+#define LPC214X_SPI_ICR_OFFSET          0x20   /* Interrupt Clear Register */
+
+/* RTC register offsets */
+
+#define LPC214X_RTC_ILR_OFFSET          0x00   /* Interrupt Location Register */
+#define LPC214X_RTC_CTC_OFFSET          0x04   /* Clock Tick Counter */
+#define LPC214X_RTC_CCR_OFFSET          0x08   /* Clock Control Register */
+#define LPC214X_RTC_CIIR_OFFSET         0x0c   /* Counter Increment Interrupt Register */
+#define LPC214X_RTC_AMR_OFFSET          0x10   /* Alarm Mask Register */
+#define LPC214X_RTC_CTIME0_OFFSET       0x14   /* Consolidated Time Register 0 */
+#define LPC214X_RTC_CTIME1_OFFSET       0x18   /* Consolidated Time Register 1 */
+#define LPC214X_RTC_CTIME2_OFFSET       0x1c   /* Consolidated Time Register 2 */
+#define LPC214X_RTC_SEC_OFFSET          0x20   /* Seconds Register */
+#define LPC214X_RTC_MIN_OFFSET          0x24   /* Minutes Register */
+#define LPC214X_RTC_HOUR_OFFSET         0x28   /* Hours Register */
+#define LPC214X_RTC_DOM_OFFSET          0x2c   /* Day Of Month Register */
+#define LPC214X_RTC_DOW_OFFSET          0x30   /* Day Of Week Register */
+#define LPC214X_RTC_DOY_OFFSET          0x34   /* Day Of Year Register */
+#define LPC214X_RTC_MONTH_OFFSET        0x38   /* Months Register */
+#define LPC214X_RTC_YEAR_OFFSET         0x3c   /* Years Register */
+
+#define LPC214X_RTC_ALSEC_OFFSET        0x60   /* Alarm Seconds Register */
+#define LPC214X_RTC_ALMIN_OFFSET        0x64   /* Alarm Minutes Register */
+#define LPC214X_RTC_ALHOUR_OFFSET       0x68   /* Alarm Hours Register */
+#define LPC214X_RTC_ALDOM_OFFSET        0x6c   /* Alarm Day Of Month Register */
+#define LPC214X_RTC_ALDOW_OFFSET        0x70   /* Alarm Day Of Week Register */
+#define LPC214X_RTC_ALDOY_OFFSET        0x74   /* Alarm Day Of Year Register */
+#define LPC214X_RTC_ALMON_OFFSET        0x78   /* Alarm Months Register */
+#define LPC214X_RTC_ALYEAR_OFFSET       0x7c   /* Alarm Years Register */
+#define LPC214X_RTC_PREINT_OFFSET       0x80   /* Prescale Value Register (integer) */
+#define LPC214X_RTC_PREFRAC_OFFSET      0x84   /* Prescale Value Register (fraction) */
+
+/* GPIO register offsets */
+
+#define LPC214X_GPIO_PIN_OFFSET         0x00   /* Pin Value Register */
+#define LPC214X_GPIO_SET_OFFSET         0x04   /* Pin Output Set Register */
+#define LPC214X_GPIO_DIR_OFFSET         0x08   /* Pin Direction Register */
+#define LPC214X_GPIO_CLR_OFFSET         0x0c   /* Pin Output Clear Register */
+
 /* Memory Accelerator Module (MAM) Regiser Offsets */
 
-#define LPC214X_MAMCR_OFFSET            0x00        /* MAM Control Offset*/
-#define LPC214x_MAMTIM_OFFSET           0x04        /* MAM Timing Offset */
+#define LPC214X_MAM_CR_OFFSET           0x00   /* MAM Control Offset*/
+#define LPC214x_MAM_TIM_OFFSET          0x04   /* MAM Timing Offset */
 
 /* Phase Locked Loop (PLL) Register Offsets */
 
-#define LPC214X_PLLCON_OFFSET           0x00        /* PLL Control Offset*/
-#define LPC214X_PLLCFG_OFFSET           0x04        /* PLL Configuration Offset */
-#define LPC214X_PLLSTAT_OFFSET          0x08        /* PLL Status Offset */
-#define LPC214X_PLLFEED_OFFSET          0x0c        /* PLL Feed Offset */
+#define LPC214X_PLL_CON_OFFSET          0x00   /* PLL Control Offset*/
+#define LPC214X_PLL_CFG_OFFSET          0x04   /* PLL Configuration Offset */
+#define LPC214X_PLL_STAT_OFFSET         0x08   /* PLL Status Offset */
+#define LPC214X_PLL_FEED_OFFSET         0x0c   /* PLL Feed Offset */
 
 /* PLL Control Register Bit Settings */
 
-#define LPC214X_PLLCON_PLLE             (1 <<0)     /* PLL Enable */
-#define LPC214X_PLLCON_PLLC             (1 <<1)     /* PLL Connect */
+#define LPC214X_PLL_CON_PLLE            (1 << 0) /* PLL Enable */
+#define LPC214X_PLL_CON_PLLC            (1 << 1) /* PLL Connect */
 
 /* PLL Configuration Register Bit Settings */
 
-#define LPC214X_PLLCFG_MSEL             (0x1f << 0) /* PLL Multiplier */
-#define LPC214X_PLLCFG_PSEL             (0x03 << 5) /* PLL Divider */
-#define LPC214X_PLLSTAT_PLOCK           (1 << 10)   /* PLL Lock Status */
+#define LPC214X_PLL_CFG_MSEL            (0x1f << 0) /* PLL Multiplier */
+#define LPC214X_PLL_CFG_PSEL            (0x03 << 5) /* PLL Divider */
+#define LPC214X_PLL_STAT_PLOCK          (1 << 10)   /* PLL Lock Status */
+
+/* Power Control register offsets */
+
+#define LPC214X_PCON_OFFSET             0x00   /* Control Register */
+#define LPC214X_PCONP_OFFSET            0x04   /* Peripherals Register */
+
+/* External Interrupt register offsets */
+
+#define LPC214X_EXT_INT_OFFSET          0x00   /* Flag Register */
+#define LPC214X_EXT_WAKE_OFFSET         0x04   /* Wakeup Register */
+#define LPC214X_EXT_MODE_OFFSET         0x08   /* Mode Register */
+#define LPC214X_EXT_POLAR_OFFSET        0x0c   /* Polarity Register */
 
 /* External Memory Controller (EMC) definitions */
 
-#define LPC214X_BCFG0_OFFSET            0x00       /* BCFG0 Offset */
-#define LPC214X_BCFG1_OFFSET            0x04       /* BCFG1 Offset */
-#define LPC214X_BCFG2_OFFSET            0x08       /* BCFG2 Offset */
-#define LPC214X_BCFG3_OFFSET            0x0c       /* BCFG3 Offset */
+#define LPC214X_BCFG0_OFFSET            0x00   /* BCFG0 Offset */
+#define LPC214X_BCFG1_OFFSET            0x04   /* BCFG1 Offset */
+#define LPC214X_BCFG2_OFFSET            0x08   /* BCFG2 Offset */
+#define LPC214X_BCFG3_OFFSET            0x0c   /* BCFG3 Offset */
 
 /* Vectored Interrupt Controller (VIC) register offsets */
 
-#define LPC214X_VIC_IRQSTATUS_OFFSET    0x00       /* R: IRQ Status Register */
-#define LPC214X_VIC_FIQSTATUS_OFFSET    0x04       /* R: FIQ Status Register */
-#define LPC214X_VIC_RAWINTR_OFFSET      0x08       /* R: Raw Interrupt Status Register */
-#define LPC214X_VIC_INTSELECT_OFFSET    0x0c       /* RW: Interrupt Select Register */
-#define LPC214X_VIC_INTENABLE_OFFSET    0x10       /* RW: Interrupt Enable Register */
-#define LPC214X_VIC_INTENCLEAR_OFFSET   0x14       /* W: Interrupt Enable Clear Register */
-#define LPC214X_VIC_SOFTINT_OFFSET      0x18       /* RW: Software Interrupt Register */
-#define LPC214X_VIC_SOFTINTCLEAR_OFFSET 0x1c       /* W: Software Interrupt Clear Register */
-#define LPC214X_VIC_PROTECTION_OFFSET   0x20       /* Protection Enable Register */
-
-#define LPC214X_VIC_VECTADDR_OFFSET     0x30       /* RW: Vector Address Register */
-#define LPC214X_VIC_DEFVECTADDR_OFFSET  0x34       /* RW: Default Vector Address Register */
-
-#define LPC214X_VIC_VECTADDR0_OFFSET    0x100      /* RW: Vector Address 0 Register */
-#define LPC214X_VIC_VECTADDR1_OFFSET    0x104      /* RW: Vector Address 1 Register */
-#define LPC214X_VIC_VECTADDR2_OFFSET    0x108      /* RW: Vector Address 2 Register */
-#define LPC214X_VIC_VECTADDR3_OFFSET    0x10c      /* RW: Vector Address 3 Register */
-#define LPC214X_VIC_VECTADDR4_OFFSET    0x110      /* RW: Vector Address 4 Register */
-#define LPC214X_VIC_VECTADDR5_OFFSET    0x114      /* RW: Vector Address 5 Register */
-#define LPC214X_VIC_VECTADDR6_OFFSET    0x118      /* RW: Vector Address 6 Register */
-#define LPC214X_VIC_VECTADDR7_OFFSET    0x11c      /* RW: Vector Address 7 Register */
-#define LPC214X_VIC_VECTADDR8_OFFSET    0x120      /* RW: Vector Address 8 Register */
-#define LPC214X_VIC_VECTADDR9_OFFSET    0x124      /* RW: Vector Address 9 Register */
-#define LPC214X_VIC_VECTADDR10_OFFSET   0x128      /* RW: Vector Address 10 Register */
-#define LPC214X_VIC_VECTADDR11_OFFSET   0x12c      /* RW: Vector Address 11 Register */
-#define LPC214X_VIC_VECTADDR12_OFFSET   0x130      /* RW: Vector Address 12 Register */
-#define LPC214X_VIC_VECTADDR13_OFFSET   0x134      /* RW: Vector Address 13 Register */
-#define LPC214X_VIC_VECTADDR14_OFFSET   0x138      /* RW: Vector Address 14 Register */
-#define LPC214X_VIC_VECTADDR15_OFFSET   0x13c      /* RW: Vector Address 15 Register */
-
-#define LPC214X_VIC_VECTCNTL0_OFFSET    0x200      /* RW: Vector Control 0 Register */
-#define LPC214X_VIC_VECTCNTL1_OFFSET    0x204      /* RW: Vector Control 1 Register */
-#define LPC214X_VIC_VECTCNTL2_OFFSET    0x208      /* RW: Vector Control 2 Register */
-#define LPC214X_VIC_VECTCNTL3_OFFSET    0x20c      /* RW: Vector Control 3 Register */
-#define LPC214X_VIC_VECTCNTL4_OFFSET    0x210      /* RW: Vector Control 4 Register */
-#define LPC214X_VIC_VECTCNTL5_OFFSET    0x214      /* RW: Vector Control 5 Register */
-#define LPC214X_VIC_VECTCNTL6_OFFSET    0x218      /* RW: Vector Control 6 Register */
-#define LPC214X_VIC_VECTCNTL7_OFFSET    0x21c      /* RW: Vector Control 7 Register */
-#define LPC214X_VIC_VECTCNTL8_OFFSET    0x220      /* RW: Vector Control 8 Register */
-#define LPC214X_VIC_VECTCNTL9_OFFSET    0x224      /* RW: Vector Control 9 Register */
-#define LPC214X_VIC_VECTCNTL10_OFFSET   0x228      /* RW: Vector Control 10 Register */
-#define LPC214X_VIC_VECTCNTL11_OFFSET   0x22c      /* RW: Vector Control 11 Register */
-#define LPC214X_VIC_VECTCNTL12_OFFSET   0x230      /* RW: Vector Control 12 Register */
-#define LPC214X_VIC_VECTCNTL13_OFFSET   0x234      /* RW: Vector Control 13 Register */
-#define LPC214X_VIC_VECTCNTL14_OFFSET   0x238      /* RW: Vector Control 14 Register */
-#define LPC214X_VIC_VECTCNTL15_OFFSET   0x23c      /* RW: Vector Control 15 Register */
+#define LPC214X_VIC_IRQSTATUS_OFFSET    0x00   /* R: IRQ Status Register */
+#define LPC214X_VIC_FIQSTATUS_OFFSET    0x04   /* R: FIQ Status Register */
+#define LPC214X_VIC_RAWINTR_OFFSET      0x08   /* R: Raw Interrupt Status Register */
+#define LPC214X_VIC_INTSELECT_OFFSET    0x0c   /* RW: Interrupt Select Register */
+#define LPC214X_VIC_INTENABLE_OFFSET    0x10   /* RW: Interrupt Enable Register */
+#define LPC214X_VIC_INTENCLEAR_OFFSET   0x14   /* W: Interrupt Enable Clear Register */
+#define LPC214X_VIC_SOFTINT_OFFSET      0x18   /* RW: Software Interrupt Register */
+#define LPC214X_VIC_SOFTINTCLEAR_OFFSET 0x1c   /* W: Software Interrupt Clear Register */
+#define LPC214X_VIC_PROTECTION_OFFSET   0x20   /* Protection Enable Register */
+
+#define LPC214X_VIC_VECTADDR_OFFSET     0x30   /* RW: Vector Address Register */
+#define LPC214X_VIC_DEFVECTADDR_OFFSET  0x34   /* RW: Default Vector Address Register */
+
+#define LPC214X_VIC_VECTADDR0_OFFSET    0x100  /* RW: Vector Address 0 Register */
+#define LPC214X_VIC_VECTADDR1_OFFSET    0x104  /* RW: Vector Address 1 Register */
+#define LPC214X_VIC_VECTADDR2_OFFSET    0x108  /* RW: Vector Address 2 Register */
+#define LPC214X_VIC_VECTADDR3_OFFSET    0x10c  /* RW: Vector Address 3 Register */
+#define LPC214X_VIC_VECTADDR4_OFFSET    0x110  /* RW: Vector Address 4 Register */
+#define LPC214X_VIC_VECTADDR5_OFFSET    0x114  /* RW: Vector Address 5 Register */
+#define LPC214X_VIC_VECTADDR6_OFFSET    0x118  /* RW: Vector Address 6 Register */
+#define LPC214X_VIC_VECTADDR7_OFFSET    0x11c  /* RW: Vector Address 7 Register */
+#define LPC214X_VIC_VECTADDR8_OFFSET    0x120  /* RW: Vector Address 8 Register */
+#define LPC214X_VIC_VECTADDR9_OFFSET    0x124  /* RW: Vector Address 9 Register */
+#define LPC214X_VIC_VECTADDR10_OFFSET   0x128  /* RW: Vector Address 10 Register */
+#define LPC214X_VIC_VECTADDR11_OFFSET   0x12c  /* RW: Vector Address 11 Register */
+#define LPC214X_VIC_VECTADDR12_OFFSET   0x130  /* RW: Vector Address 12 Register */
+#define LPC214X_VIC_VECTADDR13_OFFSET   0x134  /* RW: Vector Address 13 Register */
+#define LPC214X_VIC_VECTADDR14_OFFSET   0x138  /* RW: Vector Address 14 Register */
+#define LPC214X_VIC_VECTADDR15_OFFSET   0x13c  /* RW: Vector Address 15 Register */
+
+#define LPC214X_VIC_VECTCNTL0_OFFSET    0x200  /* RW: Vector Control 0 Register */
+#define LPC214X_VIC_VECTCNTL1_OFFSET    0x204  /* RW: Vector Control 1 Register */
+#define LPC214X_VIC_VECTCNTL2_OFFSET    0x208  /* RW: Vector Control 2 Register */
+#define LPC214X_VIC_VECTCNTL3_OFFSET    0x20c  /* RW: Vector Control 3 Register */
+#define LPC214X_VIC_VECTCNTL4_OFFSET    0x210  /* RW: Vector Control 4 Register */
+#define LPC214X_VIC_VECTCNTL5_OFFSET    0x214  /* RW: Vector Control 5 Register */
+#define LPC214X_VIC_VECTCNTL6_OFFSET    0x218  /* RW: Vector Control 6 Register */
+#define LPC214X_VIC_VECTCNTL7_OFFSET    0x21c  /* RW: Vector Control 7 Register */
+#define LPC214X_VIC_VECTCNTL8_OFFSET    0x220  /* RW: Vector Control 8 Register */
+#define LPC214X_VIC_VECTCNTL9_OFFSET    0x224  /* RW: Vector Control 9 Register */
+#define LPC214X_VIC_VECTCNTL10_OFFSET   0x228  /* RW: Vector Control 10 Register */
+#define LPC214X_VIC_VECTCNTL11_OFFSET   0x22c  /* RW: Vector Control 11 Register */
+#define LPC214X_VIC_VECTCNTL12_OFFSET   0x230  /* RW: Vector Control 12 Register */
+#define LPC214X_VIC_VECTCNTL13_OFFSET   0x234  /* RW: Vector Control 13 Register */
+#define LPC214X_VIC_VECTCNTL14_OFFSET   0x238  /* RW: Vector Control 14 Register */
+#define LPC214X_VIC_VECTCNTL15_OFFSET   0x23c  /* RW: Vector Control 15 Register */
 
 /****************************************************************************************************
  * Inline Functions
diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_head.S b/nuttx/arch/arm/src/lpc214x/lpc214x_head.S
index a9e2df3d1..8bae66ef2 100644
--- a/nuttx/arch/arm/src/lpc214x/lpc214x_head.S
+++ b/nuttx/arch/arm/src/lpc214x/lpc214x_head.S
@@ -182,7 +182,7 @@
 #ifndef CONFIG_PINSEL1_VALUE /* Can be selected from the config file */
 #  ifdef CONFIG_ADC_SETUP
 #    define CONFIG_PINSEL1_VALUE 0x01000000; /* Enable DAC */
-#  elsel
+#  else
 #    define CONFIG_PINSEL1_VALUE 0x00000000; /* Reset value */
 #  endif
 #endif
@@ -300,9 +300,9 @@
 #ifdef CONFIG_MAM_SETUP
 	ldr	\base, =LPC214X_MAM_BASE
 	mov	\val, #CONFIG_MAMTIM_VALUE
-	str	\val, [\base, #LPC214x_MAMTIM_OFFSET] 
+	str	\val, [\base, #LPC214x_MAM_TIM_OFFSET] 
 	mov	\val, #CONFIG_MAMCR_VALUE
-	str	\val, [\base, #LPC214X_MAMCR_OFFSET] 
+	str	\val, [\base, #LPC214X_MAM_CR_OFFSET] 
 #endif
 	.endm
 
diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S b/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S
index c092b1dd1..39b955aa5 100644
--- a/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S
+++ b/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S
@@ -140,11 +140,11 @@ up_lowputc:
 	/* On entry, r0 holds the character to be printed */
 
 	ldr	r1, =LPC214X_UART_BASE
-	strb	r0, [r1, #LPC214X_THR_OFFSET]
+	strb	r0, [r1, #LPC214X_UART_THR_OFFSET]
 
 	/* Wait for the byte to be transferred */
 
-1:	ldr	r0, [r1, #LPC214X_LSR_OFFSET]
+1:	ldr	r0, [r1, #LPC214X_UART_LSR_OFFSET]
 	ands	r0, #LPC214X_LSR_TEMT  /* Transmitter empty */
 	beq	1b
 
@@ -176,20 +176,20 @@ up_lowsetup:
 
 	ldr	r0, =LPC214X_UART0_BASE
 	mov	r1, #(LPC214X_LCR_VALUE | LPC214X_LCR_DLAB_ENABLE)
-	strb	r1, [r0, #LPC214X_LCR_OFFSET]
+	strb	r1, [r0, #LPC214X_UART_LCR_OFFSET]
 
 	/* Set the BAUD divisor */
 
 	mov	r1, #(UART_BAUD(LPC214X_UART_BAUD) >> 8)
-	strb	r1, [r0, #LPC214X_DLM_OFFSET]
+	strb	r1, [r0, #LPC214X_UART_DLM_OFFSET]
 
 	mov	r1, #(UART_BAUD(LPC214X_UART_BAUD) & 0xff)
-	strb	r1, [r0, #LPC214X_DLL_OFFSET]
+	strb	r1, [r0, #LPC214X_UART_DLL_OFFSET]
 
 	/* Clear DLAB */
 	
 	mov	r1, #LPC214X_LCR_VALUE
-	strb	r1, [r0, #LPC214X_LCR_OFFSET]
+	strb	r1, [r0, #LPC214X_UART_LCR_OFFSET]
 
 	/* And return */
 
diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_serial.c b/nuttx/arch/arm/src/lpc214x/lpc214x_serial.c
index cc4afd0e2..6309194d8 100644
--- a/nuttx/arch/arm/src/lpc214x/lpc214x_serial.c
+++ b/nuttx/arch/arm/src/lpc214x/lpc214x_serial.c
@@ -220,7 +220,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, ubyte *ier)
     }
 
   priv->ier &= ~LPC214X_IER_ALLIE;
-  up_serialout(priv, LPC214X_IER_OFFSET, priv->ier);
+  up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier);
 }
 
 /****************************************************************************
@@ -230,7 +230,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, ubyte *ier)
 static inline void up_restoreuartint(struct up_dev_s *priv, ubyte ier)
 {
   priv->ier |= ier & LPC214X_IER_ALLIE;
-  up_serialout(priv, LPC214X_IER_OFFSET, priv->ier);
+  up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier);
 }
 
 /****************************************************************************
@@ -245,7 +245,7 @@ static inline void up_waittxfifonotfull(struct up_dev_s *priv)
   for (tmp = 1000 ; tmp > 0 ; tmp--)
     {
       /* Check if the tranmitter holding register (THR) is empty */
-      if ((up_serialin(priv, LPC214X_LSR_OFFSET) & LPC214X_LSR_THRE) != 0)
+      if ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0)
         {
           /* The THR is empty, return */
           break;
@@ -259,7 +259,7 @@ static inline void up_waittxfifonotfull(struct up_dev_s *priv)
 
 static inline void up_enablebreaks(struct up_dev_s *priv, boolean enable)
 {
-  ubyte lcr = up_serialin(priv, LPC214X_LCR_OFFSET);
+  ubyte lcr = up_serialin(priv, LPC214X_UART_LCR_OFFSET);
   if (enable)
     {
       lcr |= LPC214X_LCR_BREAK_ENABLE;
@@ -268,7 +268,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, boolean enable)
     {
       lcr &= ~LPC214X_LCR_BREAK_ENABLE;
     }
-  up_serialout(priv, LPC214X_LCR_OFFSET, lcr);
+  up_serialout(priv, LPC214X_UART_LCR_OFFSET, lcr);
 }
 
 /****************************************************************************
@@ -290,15 +290,15 @@ static int up_setup(struct uart_dev_s *dev)
 
   /* Clear fifos */
 
-  up_serialout(priv, LPC214X_FCR_OFFSET, (LPC214X_FCR_RX_FIFO_RESET|LPC214X_FCR_TX_FIFO_RESET));
+  up_serialout(priv, LPC214X_UART_FCR_OFFSET, (LPC214X_FCR_RX_FIFO_RESET|LPC214X_FCR_TX_FIFO_RESET));
  
   /* Set trigger */
 
-  up_serialout(priv, LPC214X_FCR_OFFSET, (LPC214X_FCR_FIFO_ENABLE|LPC214X_FCR_FIFO_TRIG14));
+  up_serialout(priv, LPC214X_UART_FCR_OFFSET, (LPC214X_FCR_FIFO_ENABLE|LPC214X_FCR_FIFO_TRIG14));
 
   /* Set up the IER */
 
-  priv->ier = up_serialin(priv, LPC214X_IER_OFFSET);
+  priv->ier = up_serialin(priv, LPC214X_UART_IER_OFFSET);
   
   /* Set up the LCR */
   
@@ -329,17 +329,17 @@ static int up_setup(struct uart_dev_s *dev)
 
   /* Enter DLAB=1 */
     
-  up_serialout(priv, LPC214X_LCR_OFFSET, (lcr | LPC214X_LCR_DLAB_ENABLE));
+  up_serialout(priv, LPC214X_UART_LCR_OFFSET, (lcr | LPC214X_LCR_DLAB_ENABLE));
  
   /* Set the BAUD divisor */
 
   baud = UART_BAUD(priv->baud);
-  up_serialout(priv, LPC214X_DLM_OFFSET, baud >> 8);
-  up_serialout(priv, LPC214X_DLL_OFFSET, baud & 0xff);
+  up_serialout(priv, LPC214X_UART_DLM_OFFSET, baud >> 8);
+  up_serialout(priv, LPC214X_UART_DLL_OFFSET, baud & 0xff);
  
   /* Clear DLAB */
 
- up_serialout(priv, LPC214X_LCR_OFFSET, lcr);
+ up_serialout(priv, LPC214X_UART_LCR_OFFSET, lcr);
 #endif
   return OK;
 }
@@ -403,7 +403,7 @@ static int up_interrupt(int irq, void *context)
        * termination conditions
        */
 
-       status  = up_serialin(priv, LPC214X_IIR_OFFSET);
+       status  = up_serialin(priv, LPC214X_UART_IIR_OFFSET);
       
       /* The NO INTERRUPT should be zero */
       
@@ -429,7 +429,7 @@ static int up_interrupt(int irq, void *context)
            {
              /* Read the modem status regisgter (MSR) to clear */
             
-             (void)up_serialin(priv, LPC214X_MSR_OFFSET);
+             (void)up_serialin(priv, LPC214X_UART_MSR_OFFSET);
            }
 
           /* Just clear any line status interrupts */
@@ -438,7 +438,7 @@ static int up_interrupt(int irq, void *context)
             {
               /* Read the line status register (LSR) to clear */
             
-              (void)up_serialin(priv, LPC214X_LSR_OFFSET);
+              (void)up_serialin(priv, LPC214X_UART_LSR_OFFSET);
             }
         }
     }
@@ -518,8 +518,8 @@ static int up_receive(struct uart_dev_s *dev, uint32 *status)
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
   ubyte rbr;
 
-  rbr     = up_serialin(priv, LPC214X_RBR_OFFSET);
-  *status = up_serialin(priv, LPC214X_RBR_OFFSET);
+  rbr     = up_serialin(priv, LPC214X_UART_RBR_OFFSET);
+  *status = up_serialin(priv, LPC214X_UART_RBR_OFFSET);
   return rbr;
 }
 
@@ -544,7 +544,7 @@ static void up_rxint(struct uart_dev_s *dev, boolean enable)
     {
       priv->ier &= ~LPC214X_IER_ERBFI;
     }
-  up_serialout(priv, LPC214X_IER_OFFSET, priv->ier);
+  up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier);
 }
 
 /****************************************************************************
@@ -558,7 +558,7 @@ static void up_rxint(struct uart_dev_s *dev, boolean enable)
 static boolean up_rxfifonotempty(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LPC214X_LSR_OFFSET) & LPC214X_LSR_RDR) != 0);
+  return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_RDR) != 0);
 }
 
 /****************************************************************************
@@ -572,7 +572,7 @@ static boolean up_rxfifonotempty(struct uart_dev_s *dev)
 static void up_send(struct uart_dev_s *dev, int ch)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  up_serialout(priv, LPC214X_THR_OFFSET, (ubyte)ch);
+  up_serialout(priv, LPC214X_UART_THR_OFFSET, (ubyte)ch);
 }
 
 /****************************************************************************
@@ -596,7 +596,7 @@ static void up_txint(struct uart_dev_s *dev, boolean enable)
     {
       priv->ier &= ~LPC214X_IER_ETBEI;
     }
-  up_serialout(priv, LPC214X_IER_OFFSET, priv->ier);
+  up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier);
 }
 
 /****************************************************************************
@@ -610,7 +610,7 @@ static void up_txint(struct uart_dev_s *dev, boolean enable)
 static boolean up_txfifonotfull(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LPC214X_LSR_OFFSET) & LPC214X_LSR_THRE) != 0);
+  return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0);
 }
 
 /****************************************************************************
@@ -624,7 +624,7 @@ static boolean up_txfifonotfull(struct uart_dev_s *dev)
 static boolean up_txfifoempty(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
-  return ((up_serialin(priv, LPC214X_LSR_OFFSET) & LPC214X_LSR_THRE) != 0);
+  return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0);
 }
 
 /****************************************************************************
@@ -693,7 +693,7 @@ int up_putc(int ch)
 
   up_disableuartint(priv, &ier);
   up_waittxfifonotfull(priv);
-  up_serialout(priv, LPC214X_THR_OFFSET, (ubyte)ch);
+  up_serialout(priv, LPC214X_UART_THR_OFFSET, (ubyte)ch);
 
   /* Check for LF */
 
@@ -702,7 +702,7 @@ int up_putc(int ch)
       /* Add CR */
 
       up_waittxfifonotfull(priv);
-      up_serialout(priv, LPC214X_THR_OFFSET, '\r');
+      up_serialout(priv, LPC214X_UART_THR_OFFSET, '\r');
     }
 
   up_waittxfifonotfull(priv);