Flesh out LM3S9618 interrupt control logic

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1774 42af7a65-404d-4744-a932-0658087f49c3

8 files changed, 373 insertions, 75 deletions

diff --git a/nuttx/arch/arm/include/lm3s/irq.h b/nuttx/arch/arm/include/lm3s/irq.h
index d4dc87355..6714c909a 100644
--- a/nuttx/arch/arm/include/lm3s/irq.h
+++ b/nuttx/arch/arm/include/lm3s/irq.h
@@ -51,9 +51,9 @@
  * Definitions
  ************************************************************************************/
 
-/* IRQ numbers.  The IRQ number corresponds to the bit number in interrupt registers.
- * This includes all externally generated interrupts (but excludes processor
- * exceptions)
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
  */
 
 /* Processor Exceptions (vectors 0-15) */
@@ -61,64 +61,65 @@
 #define LMSB_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
                                   /* Vector  0: Reset stack pointer value */
                                   /* Vector  1: Reset (not handler as an IRQ) */
-#define LMSB_IRQ_NMI          (1) /* Vector  2: Non-Maskable Interrupt (NMI) */
-#define LMSB_IRQ_HARDFAULT    (2) /* Vector  3: Hard fault */
-#define LMSB_IRQ_MPU          (3) /* Vector  4: Memory management (MPU) */
-#define LMSB_IRQ_BUSFAULT     (4) /* Vector  5: Bus fault */
-#define LMSB_IRQ_USAGEFAULT   (5) /* Vector  6: Usage fault */
-#define LMSB_IRQ_SVCALL       (6) /* Vector 11: SVC call */
-#define LMSB_IRQ_DBGMONITOR   (7) /* Vector 12: Debug Monitor */
+#define LMSB_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define LMSB_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
+#define LMSB_IRQ_MPU          (4) /* Vector  4: Memory management (MPU) */
+#define LMSB_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
+#define LMSB_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
+#define LMSB_IRQ_SVCALL      (11) /* Vector 11: SVC call */
+#define LMSB_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
                                   /* Vector 13: Reserved */
-#define LMSB_IRQ_PENDSV       (8) /* Vector 14: Penable system service request */
-#define LMSB_IRQ_SYSTICK      (9) /* Vector 15: System tick */
+#define LMSB_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
+#define LMSB_IRQ_SYSTICK     (15) /* Vector 15: System tick */
 
-/* External interrupts (vectors > 16) */
+/* External interrupts (vectors >= 16) */
 
+#define LM3S_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
 #ifdef CONFIG_ARCH_CHIP_LM3S6918
 
-#  define LM3S_IRQ_GPIOA     (10) /* Vector 16: GPIO Port A */
-#  define LM3S_IRQ_GPIOB     (11) /* Vector 17: GPIO Port B */
-#  define LM3S_IRQ_GPIOC     (12) /* Vector 18: GPIO Port C */
-#  define LM3S_IRQ_GPIOD     (13) /* Vector 19: GPIO Port D */
-#  define LM3S_IRQ_GPIOE     (14) /* Vector 20: GPIO Port E */
-#  define LM3S_IRQ_UART0     (15) /* Vector 21: UART 0 */
-#  define LM3S_IRQ_UART1     (16) /* Vector 22: UART 1 */
-#  define LM3S_IRQ_SSI0      (17) /* Vector 23: SSI 0 */
-#  define LM3S_IRQ_I2C0      (18) /* Vector 24: I2C 0 */
+#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
                                   /* Vector 25-29: Reserved */
-#  define LM3S_IRQ_ADC0      (19) /* Vector 30: ADC Sequence 0 */
-#  define LM3S_IRQ_ADC1      (20) /* Vector 31: ADC Sequence 1 */
-#  define LM3S_IRQ_ADC2      (21) /* Vector 32: ADC Sequence 2 */
-#  define LM3S_IRQ_ADC3      (22) /* Vector 33: ADC Sequence 3 */
-#  define LM3S_IRQ_WDOG      (23) /* Vector 34: Watchdog Timer */
-#  define LM3S_IRQ_TIMER0A   (24) /* Vector 35: Timer 0 A */
-#  define LM3S_IRQ_TIMER0B   (25) /* Vector 36: Timer 0 B */
-#  define LM3S_IRQ_TIMER1A   (26) /* Vector 37: Timer 1 A */
-#  define LM3S_IRQ_TIMER1B   (27) /* Vector 38: Timer 1 B */
-#  define LM3S_IRQ_TIMER2A   (28) /* Vector 39: Timer 2 A */
-#  define LM3S_IRQ_TIMER2B   (29) /* Vector 40: Timer 3 B */
-#  define LM3S_IRQ_COMPARE0  (30) /* Vector 41: Analog Comparator 0 */
-#  define LM3S_IRQ_COMPARE1  (31) /* Vector 42: Analog Comparator 1 */
+#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
                                   /* Vector 43: Reserved */
-#  define LM3S_IRQ_SYSCON    (32) /* Vector 44: System Control */
-#  define LM3S_IRQ_FLASHCON  (33) /* Vector 45: FLASH Control */
-#  define LM3S_IRQ_GPIOF     (34) /* Vector 46: GPIO Port F */
-#  define LM3S_IRQ_GPIOG     (35) /* Vector 47: GPIO Port G */
-#  define LM3S_IRQ_GPIOH     (36) /* Vector 48: GPIO Port H */
+#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM3S_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
                                   /* Vector 49: Reserved */
-#  define LM3S_IRQ_SSI1      (37) /* Vector 50: SSI 1 */
-#  define LM3S_IRQ_TIMER3A   (38) /* Vector 51: Timer 3 A */
-#  define LM3S_IRQ_TIMER3B   (39) /* Vector 52: Timer 3 B */
-#  define LM3S_IRQ_I2C1      (40) /* Vector 53: I2C 1 */
+#  define LM3S_IRQ_SSI1      (50) /* Vector 50: SSI 1 */
+#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
                                   /* Vectors 54-57: Reserved */
-#  define LM3S_IRQ_ETHCON    (41) /* Vector 58: Ethernet Controller */
-#  define LM3S_IRQ_HIBERNATE (42) /* Vector 59: Hibernation Module */
+#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
                                   /* Vectors 60-70: Reserved */
 #else
 #  error "IRQ Numbers not specified for this LM3S chip"
 #endif
 
-#define NR_IRQS              (43)
+#define NR_IRQS              (60) /* Really only 43 */
 
 /************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/common/cortexm3_nvic.h b/nuttx/arch/arm/src/common/cortexm3_nvic.h
index d0982a75a..d627a4dab 100644
--- a/nuttx/arch/arm/src/common/cortexm3_nvic.h
+++ b/nuttx/arch/arm/src/common/cortexm3_nvic.h
@@ -109,15 +109,67 @@
 #define NVIC_IRQ192_223_ACTIVE_OFFSET   0x0318 /* IRQ 192-223 active bit register */
 #define NVIC_IRQ224_239_ACTIVE_OFFSET   0x031c /* IRQ 224-239 active bit register */
 
-#define NVIC_IRQ_PRIORITY_OFFSET(n)     (0x0400 + 4*((n) >> 5))
-#define NVIC_IRQ0_31_PRIORITY_OFFSET    0x0400 /* IRQ 0-31 priority register */
-#define NVIC_IRQ32_63_PRIORITY_OFFSET   0x0404 /* IRQ 32-63 priority register */
-#define NVIC_IRQ64_95_PRIORITY_OFFSET   0x0408 /* IRQ 64-95 priority register */
-#define NVIC_IRQ96_127_PRIORITY_OFFSET  0x040c /* IRQ 96-127 priority register */
-#define NVIC_IRQ128_159_PRIORITY_OFFSET 0x0410 /* IRQ 128-159 priority register */
-#define NVIC_IRQ160_191_PRIORITY_OFFSET 0x0414 /* IRQ 160-191 priority register */
-#define NVIC_IRQ192_223_PRIORITY_OFFSET 0x0418 /* IRQ 192-223 priority register */
-#define NVIC_IRQ224_239_PRIORITY_OFFSET 0x041c /* IRQ 224-239 priority register */
+#define NVIC_IRQ_PRIORITY_OFFSET(n)     (0x0400 + 4*((n) >> 2))
+#define NVIC_IRQ0_3_PRIORITY_OFFSET     0x0400 /* IRQ 0-3 priority register */
+#define NVIC_IRQ4_7_PRIORITY_OFFSET     0x0404 /* IRQ 4-7 priority register */
+#define NVIC_IRQ8_11_PRIORITY_OFFSET    0x0408 /* IRQ 8-11 priority register */
+#define NVIC_IRQ12_15_PRIORITY_OFFSET   0x040c /* IRQ 12-15 priority register */
+#define NVIC_IRQ16_19_PRIORITY_OFFSET   0x0410 /* IRQ 16-19 priority register */
+#define NVIC_IRQ20_23_PRIORITY_OFFSET   0x0414 /* IRQ 20-23 priority register */
+#define NVIC_IRQ24_27_PRIORITY_OFFSET   0x0418 /* IRQ 24-29 priority register */
+#define NVIC_IRQ28_31_PRIORITY_OFFSET   0x041c /* IRQ 28-31 priority register */
+#define NVIC_IRQ32_35_PRIORITY_OFFSET   0x0420 /* IRQ 32-35 priority register */
+#define NVIC_IRQ36_39_PRIORITY_OFFSET   0x0424 /* IRQ 36-39 priority register */
+#define NVIC_IRQ40_43_PRIORITY_OFFSET   0x0428 /* IRQ 40-43 priority register */
+#define NVIC_IRQ44_47_PRIORITY_OFFSET   0x042c /* IRQ 44-47 priority register */
+#define NVIC_IRQ48_51_PRIORITY_OFFSET   0x0430 /* IRQ 48-51 priority register */
+#define NVIC_IRQ52_55_PRIORITY_OFFSET   0x0434 /* IRQ 52-55 priority register */
+#define NVIC_IRQ56_59_PRIORITY_OFFSET   0x0438 /* IRQ 56-59 priority register */
+#define NVIC_IRQ60_63_PRIORITY_OFFSET   0x043c /* IRQ 60-63 priority register */
+#define NVIC_IRQ64_67_PRIORITY_OFFSET   0x0440 /* IRQ 64-67 priority register */
+#define NVIC_IRQ68_71_PRIORITY_OFFSET   0x0444 /* IRQ 68-71 priority register */
+#define NVIC_IRQ72_75_PRIORITY_OFFSET   0x0448 /* IRQ 72-75 priority register */
+#define NVIC_IRQ76_79_PRIORITY_OFFSET   0x044c /* IRQ 76-79 priority register */
+#define NVIC_IRQ80_83_PRIORITY_OFFSET   0x0450 /* IRQ 80-83 priority register */
+#define NVIC_IRQ84_87_PRIORITY_OFFSET   0x0454 /* IRQ 84-87 priority register */
+#define NVIC_IRQ88_91_PRIORITY_OFFSET   0x0458 /* IRQ 88-91 priority register */
+#define NVIC_IRQ92_95_PRIORITY_OFFSET   0x045c /* IRQ 92-95 priority register */
+#define NVIC_IRQ96_99_PRIORITY_OFFSET   0x0460 /* IRQ 96-99 priority register */
+#define NVIC_IRQ100_103_PRIORITY_OFFSET 0x0464 /* IRQ 100-103 priority register */
+#define NVIC_IRQ104_107_PRIORITY_OFFSET 0x0468 /* IRQ 104-107 priority register */
+#define NVIC_IRQ108_111_PRIORITY_OFFSET 0x046c /* IRQ 108-111 priority register */
+#define NVIC_IRQ112_115_PRIORITY_OFFSET 0x0470 /* IRQ 112-115 priority register */
+#define NVIC_IRQ116_119_PRIORITY_OFFSET 0x0474 /* IRQ 116-119 priority register */
+#define NVIC_IRQ120_123_PRIORITY_OFFSET 0x0478 /* IRQ 120-123 priority register */
+#define NVIC_IRQ124_127_PRIORITY_OFFSET 0x047c /* IRQ 124-127 priority register */
+#define NVIC_IRQ128_131_PRIORITY_OFFSET 0x0480 /* IRQ 128-131 priority register */
+#define NVIC_IRQ132_135_PRIORITY_OFFSET 0x0484 /* IRQ 132-135 priority register */
+#define NVIC_IRQ136_139_PRIORITY_OFFSET 0x0488 /* IRQ 136-139 priority register */
+#define NVIC_IRQ140_143_PRIORITY_OFFSET 0x048c /* IRQ 140-143 priority register */
+#define NVIC_IRQ144_147_PRIORITY_OFFSET 0x0490 /* IRQ 144-147 priority register */
+#define NVIC_IRQ148_151_PRIORITY_OFFSET 0x0494 /* IRQ 148-151 priority register */
+#define NVIC_IRQ152_155_PRIORITY_OFFSET 0x0498 /* IRQ 152-155 priority register */
+#define NVIC_IRQ156_159_PRIORITY_OFFSET 0x049c /* IRQ 156-159 priority register */
+#define NVIC_IRQ160_163_PRIORITY_OFFSET 0x04a0 /* IRQ 160-163 priority register */
+#define NVIC_IRQ164_167_PRIORITY_OFFSET 0x04a4 /* IRQ 164-167 priority register */
+#define NVIC_IRQ168_171_PRIORITY_OFFSET 0x04a8 /* IRQ 168-171 priority register */
+#define NVIC_IRQ172_175_PRIORITY_OFFSET 0x04ac /* IRQ 172-175 priority register */
+#define NVIC_IRQ176_179_PRIORITY_OFFSET 0x04b0 /* IRQ 176-179 priority register */
+#define NVIC_IRQ180_183_PRIORITY_OFFSET 0x04b4 /* IRQ 180-183 priority register */
+#define NVIC_IRQ184_187_PRIORITY_OFFSET 0x04b8 /* IRQ 184-187 priority register */
+#define NVIC_IRQ188_191_PRIORITY_OFFSET 0x04bc /* IRQ 188-191 priority register */
+#define NVIC_IRQ192_195_PRIORITY_OFFSET 0x04c0 /* IRQ 192-195 priority register */
+#define NVIC_IRQ196_199_PRIORITY_OFFSET 0x04c4 /* IRQ 196-199 priority register */
+#define NVIC_IRQ200_203_PRIORITY_OFFSET 0x04c8 /* IRQ 200-203 priority register */
+#define NVIC_IRQ204_207_PRIORITY_OFFSET 0x04cc /* IRQ 204-207 priority register */
+#define NVIC_IRQ208_211_PRIORITY_OFFSET 0x04d0 /* IRQ 208-211 priority register */
+#define NVIC_IRQ212_215_PRIORITY_OFFSET 0x04d4 /* IRQ 212-215 priority register */
+#define NVIC_IRQ216_219_PRIORITY_OFFSET 0x04d8 /* IRQ 216-219 priority register */
+#define NVIC_IRQ220_223_PRIORITY_OFFSET 0x04dc /* IRQ 220-223 priority register */
+#define NVIC_IRQ224_227_PRIORITY_OFFSET 0x04e0 /* IRQ 224-227 priority register */
+#define NVIC_IRQ228_231_PRIORITY_OFFSET 0x04e4 /* IRQ 228-231 priority register */
+#define NVIC_IRQ232_235_PRIORITY_OFFSET 0x04e8 /* IRQ 232-235 priority register */
+#define NVIC_IRQ236_239_PRIORITY_OFFSET 0x04ec /* IRQ 236-239 priority register */
 
 #define NVIC_CPUID_BASE_OFFSET          0x0d00 /* CPUID base register */
 #define NVIC_INTCTRL_OFFSET             0x0d04 /* Interrupt control state register */
@@ -125,6 +177,7 @@
 #define NVIC_AIRC_OFFSET                0x0d0c /* Application interrupt/reset contol registr */
 #define NVIC_SYSCON_OFFSET              0x0d10 /* System control register */
 #define NVIC_CFGCON_OFFSET              0x0d14 /* Configuration control register */
+#define NVIC_SYSH_PRIORITY_OFFSET(n)    (0x0d14 + 4*((n) >> 2))
 #define NVIC_SYSH4_7_PRIORITY_OFFSET    0x0d18 /* System handlers 4-7 priority register */
 #define NVIC_SYSH8_11_PRIORITY_OFFSET   0x0d1c /* System handler 8-11 priority register */
 #define NVIC_SYSH12_15_PRIORITY_OFFSET  0x0d20 /* System handler 12-15 priority register */
@@ -221,14 +274,65 @@
 #define NVIC_IRQ224_239_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ACTIVE_OFFSET)
 
 #define NVIC_IRQ_PRIORITY(n)          (CORTEXM3_NVIC_BASE + NVIC_IRQ_PRIORITY_OFFSET(n))
-#define NVIC_IRQ0_31_PRIORITY         (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_PRIORITY_OFFSET)
-#define NVIC_IRQ32_63_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_PRIORITY_OFFSET)
-#define NVIC_IRQ64_95_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_PRIORITY_OFFSET)
-#define NVIC_IRQ96_127_PRIORITY       (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_PRIORITY_OFFSET)
-#define NVIC_IRQ128_159_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_PRIORITY_OFFSET)
-#define NVIC_IRQ160_191_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_PRIORITY_OFFSET)
-#define NVIC_IRQ192_223_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_PRIORITY_OFFSET)
-#define NVIC_IRQ224_239_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_PRIORITY_OFFSET)
+#define NVIC_IRQ0_3_PRIORITY          (CORTEXM3_NVIC_BASE + NVIC_IRQ0_3_PRIORITY_OFFSET)
+#define NVIC_IRQ4_7_PRIORITY          (CORTEXM3_NVIC_BASE + NVIC_IRQ4_7_PRIORITY_OFFSET)
+#define NVIC_IRQ8_11_PRIORITY         (CORTEXM3_NVIC_BASE + NVIC_IRQ8_11_PRIORITY_OFFSET)
+#define NVIC_IRQ12_15_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ12_15_PRIORITY_OFFSET)
+#define NVIC_IRQ16_19_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ16_19_PRIORITY_OFFSET)
+#define NVIC_IRQ20_23_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ20_23_PRIORITY_OFFSET)
+#define NVIC_IRQ24_27_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ24_27_PRIORITY_OFFSET)
+#define NVIC_IRQ28_31_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ28_31_PRIORITY_OFFSET)
+#define NVIC_IRQ32_35_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ32_35_PRIORITY_OFFSET)
+#define NVIC_IRQ36_39_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ36_39_PRIORITY_OFFSET)
+#define NVIC_IRQ40_43_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ40_43_PRIORITY_OFFSET)
+#define NVIC_IRQ44_47_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ44_47_PRIORITY_OFFSET)
+#define NVIC_IRQ48_51_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ48_51_PRIORITY_OFFSET)
+#define NVIC_IRQ52_55_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ52_55_PRIORITY_OFFSET)
+#define NVIC_IRQ56_59_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ56_59_PRIORITY_OFFSET)
+#define NVIC_IRQ60_63_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ60_63_PRIORITY_OFFSET)
+#define NVIC_IRQ64_67_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ64_67_PRIORITY_OFFSET)
+#define NVIC_IRQ68_71_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ68_71_PRIORITY_OFFSET)
+#define NVIC_IRQ72_75_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ72_75_PRIORITY_OFFSET)
+#define NVIC_IRQ76_79_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ76_79_PRIORITY_OFFSET)
+#define NVIC_IRQ80_83_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ80_83_PRIORITY_OFFSET)
+#define NVIC_IRQ84_87_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ84_87_PRIORITY_OFFSET)
+#define NVIC_IRQ88_91_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ88_91_PRIORITY_OFFSET)
+#define NVIC_IRQ92_95_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ92_95_PRIORITY_OFFSET)
+#define NVIC_IRQ96_99_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ96_99_PRIORITY_OFFSET)
+#define NVIC_IRQ100_103_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ100_103_PRIORITY_OFFSET)
+#define NVIC_IRQ104_107_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ104_107_PRIORITY_OFFSET)
+#define NVIC_IRQ108_111_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ108_111_PRIORITY_OFFSET)
+#define NVIC_IRQ112_115_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ112_115_PRIORITY_OFFSET)
+#define NVIC_IRQ116_119_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ116_119_PRIORITY_OFFSET)
+#define NVIC_IRQ120_123_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ120_123_PRIORITY_OFFSET)
+#define NVIC_IRQ124_127_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ124_127_PRIORITY_OFFSET)
+#define NVIC_IRQ128_131_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ128_131_PRIORITY_OFFSET)
+#define NVIC_IRQ132_135_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ132_135_PRIORITY_OFFSET)
+#define NVIC_IRQ136_139_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ136_139_PRIORITY_OFFSET)
+#define NVIC_IRQ140_143_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ140_143_PRIORITY_OFFSET)
+#define NVIC_IRQ144_147_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ144_147_PRIORITY_OFFSET)
+#define NVIC_IRQ148_151_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ148_151_PRIORITY_OFFSET)
+#define NVIC_IRQ152_155_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ152_155_PRIORITY_OFFSET)
+#define NVIC_IRQ156_159_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ156_159_PRIORITY_OFFSET)
+#define NVIC_IRQ160_163_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ160_163_PRIORITY_OFFSET)
+#define NVIC_IRQ164_167_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ164_167_PRIORITY_OFFSET)
+#define NVIC_IRQ168_171_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ168_171_PRIORITY_OFFSET)
+#define NVIC_IRQ172_175_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ172_175_PRIORITY_OFFSET)
+#define NVIC_IRQ176_179_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ176_179_PRIORITY_OFFSET)
+#define NVIC_IRQ180_183_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ180_183_PRIORITY_OFFSET)
+#define NVIC_IRQ184_187_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ184_187_PRIORITY_OFFSET)
+#define NVIC_IRQ188_191_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ188_191_PRIORITY_OFFSET)
+#define NVIC_IRQ192_195_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ192_195_PRIORITY_OFFSET)
+#define NVIC_IRQ196_199_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ196_199_PRIORITY_OFFSET)
+#define NVIC_IRQ200_203_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ200_203_PRIORITY_OFFSET)
+#define NVIC_IRQ204_207_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ204_207_PRIORITY_OFFSET)
+#define NVIC_IRQ208_211_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ208_211_PRIORITY_OFFSET)
+#define NVIC_IRQ212_215_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ212_215_PRIORITY_OFFSET)
+#define NVIC_IRQ216_219_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ216_219_PRIORITY_OFFSET)
+#define NVIC_IRQ220_223_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ220_223_PRIORITY_OFFSET)
+#define NVIC_IRQ224_227_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ224_227_PRIORITY_OFFSET)
+#define NVIC_IRQ228_231_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ228_231_PRIORITY_OFFSET)
+#define NVIC_IRQ232_235_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ232_235_PRIORITY_OFFSET)
 
 #define NVIC_CPUID_BASE               (CORTEXM3_NVIC_BASE + NVIC_CPUID_BASE_OFFSET)
 #define NVIC_INTCTRL                  (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_OFFSET)
@@ -236,6 +340,7 @@
 #define NVIC_AIRC                     (CORTEXM3_NVIC_BASE + NVIC_AIRC_OFFSET)
 #define NVIC_SYSCON                   (CORTEXM3_NVIC_BASE + NVIC_SYSCON_OFFSET)
 #define NVIC_CFGCON                   (CORTEXM3_NVIC_BASE + NVIC_CFGCON_OFFSET)
+#define NVIC_SYSH_PRIORITY(n)         (CORTEXM3_NVIC_BASE + NVIC_SYSH_PRIORITY_OFFSET(n))
 #define NVIC_SYSH4_7_PRIORITY         (CORTEXM3_NVIC_BASE + NVIC_SYSH4_7_PRIORITY_OFFSET)
 #define NVIC_SYSH8_11_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_SYSH8_11_PRIORITY_OFFSET)
 #define NVIC_SYSH12_15_PRIORITY       (CORTEXM3_NVIC_BASE + NVIC_SYSH12_15_PRIORITY_OFFSET)
@@ -321,8 +426,6 @@
 
 /* System handler 4-7 priority register */
 
-#define NVIC_SYSH_PRIORITY_DEFAULT     15
-
 #define NVIC_SYSH_PRIORITY_PR4_SHIFT   0
 #define NVIC_SYSH_PRIORITY_PR4_MASK    (0xff << NVIC_SYSH_PRIORITY_PR4_SHIFT)
 #define NVIC_SYSH_PRIORITY_PR5_SHIFT   8
@@ -354,7 +457,22 @@
 #define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
 #define NVIC_SYSH_PRIORITY_PR15_MASK  (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
 
-
+/* System handler control and state register (SYSHCON) */
+
+#define NVIC_SYSHCON_MEMFAULTACT      (1 << 0)  /* Bit 0:  MemManage is active */
+#define NVIC_SYSHCON_BUSFAULTACT      (1 << 1)  /* Bit 1:  BusFault is active */
+#define NVIC_SYSHCON_USGFAULTACT      (1 << 3)  /* Bit 3:  UsageFault is active */
+#define NVIC_SYSHCON_SVCALLACT        (1 << 7)  /* Bit 7:  SVCall is active */
+#define NVIC_SYSHCON_MONITORACT       (1 << 8)  /* Bit 8:  Monitor is active */
+#define NVIC_SYSHCON_PENDSVACT        (1 << 10) /* Bit 10: PendSV is active */
+#define NVIC_SYSHCON_SYSTICKACT       (1 << 11) /* Bit 11: SysTick is active */
+#define NVIC_SYSHCON_USGFAULTPENDED   (1 << 12) /* Bit 12: Usage fault is pended */
+#define NVIC_SYSHCON_MEMFAULTPENDED   (1 << 13) /* Bit 13: MemManage is pended */
+#define NVIC_SYSHCON_BUSFAULTPENDED   (1 << 14) /* Bit 14: BusFault is pended */
+#define NVIC_SYSHCON_SVCALLPENDED     (1 << 15) /* Bit 15: SVCall is pended */
+#define NVIC_SYSHCON_MEMFAULTENA      (1 << 16) /* Bit 16: MemFault enabled */
+#define NVIC_SYSHCON_BUSFAULTENA      (1 << 17) /* Bit 17: BusFault enabled */
+#define NVIC_SYSHCON_USGFAULTENA      (1 << 18) /* Bit 18: UsageFault enabled */
 
 /************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h
index a5175a49f..f6ff0c16a 100644
--- a/nuttx/arch/arm/src/lm3s/chip.h
+++ b/nuttx/arch/arm/src/lm3s/chip.h
@@ -53,6 +53,16 @@
  * Definitions
  ************************************************************************************/
 
+/* The LM3S6918 only supports 8 priority levels.  The hardware priority mechanism
+ * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
+ * the Stellaris family), so any prioritization must be performed in those bits.
+ * The default priority level is set to the middle value
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN     0x00
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80
+#define NVIC_SYSH_PRIORITY_MAX     0xe0
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_irq.c b/nuttx/arch/arm/src/lm3s/lm3s_irq.c
index 31da0754d..b85800cb8 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_irq.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_irq.c
@@ -50,6 +50,12 @@
  * Definitions
  ****************************************************************************/
 
+#define DEFPRIORITY32 \
+  (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
+   NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
+   NVIC_SYSH_PRIORITY_DEFAULT << 8  |\
+   NVIC_SYSH_PRIORITY_DEFAULT)
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
@@ -65,6 +71,70 @@ uint32 *current_regs;
  ****************************************************************************/
 
 /****************************************************************************
+ * Name: lml3s_irqinfo
+ *
+ * Description:
+ *   Given an IRQ number, provide the register and bit setting to enable or
+ *   disable the irq.
+ *
+ ****************************************************************************/
+
+static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit)
+{
+  DEBUGASSERT(irq >= LMSB_IRQ_MPU && irq < NR_IRQS);
+
+  /* Check for external interrupt */
+
+  if (irq >= LM3S_IRQ_INTERRUPTS)
+    {
+      if (irq < LM3S_IRQ_INTERRUPTS + 32)
+        {
+           *regaddr = NVIC_IRQ0_31_ENABLE;
+           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS);
+        }
+      else if (irq < NR_IRQS)
+        {
+           *regaddr = NVIC_IRQ32_63_ENABLE;
+           *bit     = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
+        }
+      else
+        {
+          return ERROR; /* Invalid interrupt */
+        }
+    }
+
+  /* Handler processor exceptions.  Only a few can be disabled */
+
+  else
+    {
+       *regaddr = NVIC_SYSHCON;
+       if (irq == LMSB_IRQ_MPU)
+        {
+          *bit = NVIC_SYSHCON_MEMFAULTENA;
+        }
+      else if (irq == LMSB_IRQ_BUSFAULT)
+        {
+          *bit = NVIC_SYSHCON_BUSFAULTENA;
+        }
+      else if (irq == LMSB_IRQ_USAGEFAULT)
+        {
+          *bit = NVIC_SYSHCON_USGFAULTENA;
+        }
+      else if (irq == LMSB_IRQ_SYSTICK)
+        {
+          *regaddr = NVIC_SYSTICK_CTRL;
+          *bit = NVIC_SYSTICK_CTRL_ENABLE;
+        }
+      else
+        {
+          return ERROR; /* Invalid or unsupported exception */
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
  * Public Funtions
  ****************************************************************************/
 
@@ -74,9 +144,29 @@ uint32 *current_regs;
 
 void up_irqinitialize(void)
 {
-  /* Clear, disable and configure all interrupts. */
-
-# warning "Missing logic"
+  /* Disable all interrupts */
+
+  putreg32(0, NVIC_IRQ0_31_ENABLE);
+  putreg32(0, NVIC_IRQ32_63_ENABLE);
+
+  /* Set all interrrupts (and exceptions) to the default priority */
+
+  putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY);
 
   /* currents_regs is non-NULL only while processing an interrupt */
 
@@ -120,7 +210,18 @@ void up_irqinitialize(void)
 
 void up_disable_irq(int irq)
 {
-# warning "Missing logic"
+  uint32 regaddr;
+  uint32 regval;
+  uint32 bit;
+
+  if (lml3s_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Clear the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval &= ~bit;
+      putreg32(regval, regaddr);
+    }
 }
 
 /****************************************************************************
@@ -133,7 +234,18 @@ void up_disable_irq(int irq)
 
 void up_enable_irq(int irq)
 {
-# warning "Missing logic"
+  uint32 regaddr;
+  uint32 regval;
+  uint32 bit;
+
+  if (lml3s_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Set the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval |= bit;
+      putreg32(regval, regaddr);
+    }
 }
 
 /****************************************************************************
@@ -146,9 +258,47 @@ void up_enable_irq(int irq)
 
 void up_maskack_irq(int irq)
 {
-# warning "Missing logic"
+  up_disable_irq(irq);
 }
 
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   Set the priority of an IRQ.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+  uint32 regaddr;
+  uint32 regval;
+  int shift;
+
+  DEBUGASSERT(irq >= LMSB_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MAX);
+
+  if (irq < LM3S_IRQ_INTERRUPTS)
+    {
+      regaddr = NVIC_SYSH_PRIORITY(irq);
+    }
+  else
+    {
+      irq    -= LM3S_IRQ_INTERRUPTS;
+      regaddr = NVIC_IRQ_PRIORITY(irq);
+    }
+
+  regval      = getreg32(regaddr);
+  shift       = ((irq & 3) << 3);
+  regval     &= ~(0xff << shift);
+  regval     |= (priority << shift);
+  putreg32(regval, regaddr);
+  return OK;
+}
+#endif
 
 /****************************************************************************
  * Name: lm3s_nmi, lm3s_hardfault, lm3s_mpu, lm3s_busfault, lm3s_usagefault,
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_start.c b/nuttx/arch/arm/src/lm3s/lm3s_start.c
index 279b4a961..fba5e9325 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_start.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_start.c
@@ -69,6 +69,8 @@ extern uint32 _edata;           /* End+1 of .data */
 extern uint32 _sbss;            /* Start of .bss */
 extern uint32 _ebss;            /* End+1 of .bss */
 
+extern void lm3s_vectors(void);
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -110,6 +112,14 @@ void _start(void)
   up_lowsetup();
   showprogress('A');
 
+  /* If we booted from a bootloader, then set the NVIC to use our copy of
+   * of the vectors in FLASH.
+   */
+
+#ifdef CONFIG_ARCH_BOOTLOADER
+  putreg32((uint32)lm3s_vectors, NVIC_VECTAB);
+#endif
+
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
    * certain that there are no issues with the state of global variables.
    */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S
index d7be13da5..1d10e9021 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S
+++ b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S
@@ -1,5 +1,5 @@
 /************************************************************************************

- * arch/arm/src/lm3s/lm3s_vectors.S

+ * arch/arm/src/lm3s/lm3slm3s_vectors.S

  *

  *   Copyright (C) 2009 Gregory Nutt. All rights reserved.

  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

@@ -80,8 +80,10 @@
 	.section	.vectors, "ax"

 	.code		16

 	.align		0

+        .globl		lm3s_vectors

+        .type		lm3s_vectors, function

 

-_vectors:

+lm3s_vectors:

 /* Processor Exceptions */

 	.word	IDLE_STACK		/* Vector  0: Reset stack pointer */

 	.word	_start			/* Vector  1: Reset vector */

@@ -161,6 +163,7 @@ _vectors:
 #else

 #  error "Vectors not specified for this LM3S chip"

 #endif

+	.size	lm3s_vectors, .-lm3s_vectors

 

 /************************************************************************************

  * .text

diff --git a/nuttx/configs/eagle100/README.txt b/nuttx/configs/eagle100/README.txt
index b73714aea..4afbe0664 100644
--- a/nuttx/configs/eagle100/README.txt
+++ b/nuttx/configs/eagle100/README.txt
@@ -85,6 +85,10 @@ Eagle100-specific Configuration Options
 
 	   CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
 
+	CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
+
+	   CONFIG_ARCH_IRQPRIO=y
+
 	CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
 	   have LEDs
 
diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig
index 6abfc057d..f30c50ff0 100644
--- a/nuttx/configs/eagle100/ostest/defconfig
+++ b/nuttx/configs/eagle100/ostest/defconfig
@@ -50,6 +50,7 @@
 # CONFIG_DRAM_SIZE - Describes the installed DRAM.
 # CONFIG_DRAM_START - The start address of DRAM (physical)
 # CONFIG_DRAM_END - Last address+1 of installed RAM
+# CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
 # CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
 #   stack. If defined, this symbol is the size of the interrupt
 #   stack in bytes.  If not defined, the user task stacks will be
@@ -68,6 +69,7 @@ CONFIG_BOARD_LOOPSPERMSEC=16945
 CONFIG_DRAM_SIZE=0x00010000
 CONFIG_DRAM_START=0x00000000
 CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+CONFIG_ARCH_IRQPRIO=y
 CONFIG_DRAM_NUTTXENTRY=0x00002000
 CONFIG_ARCH_INTERRUPTSTACK=n
 CONFIG_ARCH_STACKDUMP=y