LM3S integration

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1784 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 15 insertions, 14 deletions

diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c
index a69b4ec14..891a2fdb0 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c
@@ -79,7 +79,7 @@
 #define DEN_0                  0
 #define DEN_X                  0
 
-#define PUR_SHIFT              2
+#define PUR_SHIFT              1
 #define PUR_1                  (1 << PUR_SHIFT)   /* Set/clear bit in GPIO PUR register */
 #define PUR_0                  0
 #define PUR_X                  0
@@ -316,7 +316,7 @@ static inline void lm3s_gpiopadstrength(uint32 base, uint32 pin, uint32 cfgset)
            * DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
            */
 
-          regoffset = LM3S_GPIOA_DR2R;
+          regoffset = LM3S_GPIO_DR2R_OFFSET;
         }
         break;
 
@@ -329,7 +329,7 @@ static inline void lm3s_gpiopadstrength(uint32 base, uint32 pin, uint32 cfgset)
            * in the GPIO DR8R register are automatically cleared by hardware."
            */
 
-          regoffset = LM3S_GPIOA_DR4R;
+          regoffset = LM3S_GPIO_DR4R_OFFSET;
         }
         break;
 
@@ -354,7 +354,7 @@ static inline void lm3s_gpiopadstrength(uint32 base, uint32 pin, uint32 cfgset)
            * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
            */
 
-          regoffset = LM3S_GPIOA_DR8R;
+          regoffset = LM3S_GPIO_DR8R_OFFSET;
         }
         break;
     }
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
index 1df228dec..f6d5272ef 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
@@ -153,14 +153,14 @@
 #define LM3S_REMAINDER  (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
 #define LM3S_DIVFRAC    ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
 
-/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 20,000,000:
+/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
  *
  * LM3S_BRDDEN    = (16 * 115,200)                           = 1,843,200
- * LM3S_BRDI      = 20,000,000 / 1,843,200                   = 10
- * LM3S_REMAINDER = 20,000,000 - 1,843,200 * 10              = 1,568,000
- * LM3S_DIVFRAC   = (1,568,000 * 64 + 921,600) / 1,843,200   = 54
+ * LM3S_BRDI      = 50,000,000 / 1,843,200                   = 27
+ * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27              = 233,600
+ * LM3S_DIVFRAC   = (233,600 * 64 + 921,600) / 1,843,200     = 8
  *
- * Which should yied BAUD = 20,000,000 / (16 * (10 + 54/64)) = 115273.8
+ * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
  */
 
 /**************************************************************************
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
index f44511259..c8886fae3 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
@@ -158,7 +158,7 @@ static inline void lm3s_plllock(void)
     {
       /* Check if the PLL is locked on */
 
-      if (getreg32(LM3S_SYSCON_RIS) & SYSCON_IMC_PLLLIM)
+      if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
         {
           /* Yes.. return now */
 
@@ -212,7 +212,8 @@ void lm3s_clockconfig(uint32 newrcc, uint32 newrcc2)
     {
       /* Enable any selected osciallators */
 
-      rcc &= (~RCC_OSCMASK|(newrcc & RCC_OSCMASK));
+      rcc &= ~RCC_OSCMASK;
+      rcc |= (newrcc & RCC_OSCMASK);
       putreg32(rcc, LM3S_SYSCON_RCC);
 
       /* Wait for the newly selected oscillator(s) to settle.  This is tricky because
@@ -254,7 +255,7 @@ void lm3s_clockconfig(uint32 newrcc, uint32 newrcc2)
 
   lm3s_delay(16);
 
-  /* Set the requested system deivider and disable the non-selected osciallators */
+  /* Set the requested system divider and disable the non-selected osciallators */
 
   rcc &= ~RCC_DIVMASK;
   rcc |= newrcc & RCC_DIVMASK;
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
index 3a9a83f62..885698dd3 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
+++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
@@ -331,9 +331,9 @@
 #define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
 #define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
 #define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */
-#define SYSCON_RCC_SYSDIV_SHIFT       26        /* Bits 26-23: System Clock Divisor */
+#define SYSCON_RCC_SYSDIV_SHIFT       23        /* Bits 26-23: System Clock Divisor */
 #define SYSCON_RCC_SYSDIV_MASK        (0x0f << SYSCON_RCC_SYSDIV_SHIFT)
-#  define SYSCON_RCC_SYSDIV(n)        ((n-1) << SYSCON_RCC_SYSDIV_SHIFT)
+#  define SYSCON_RCC_SYSDIV(n)        (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT)
 #define SYSCON_RCC_ACG                (1 << 27) /* Bit 27: Auto Clock Gating */
 
 /* XTAL to PLL Translation (PLLCFG), offset 0x064 */